Change runtime assembler generator use value and return instead of reference
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a6fa114a5b
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15c65f69aa
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@ -82,91 +82,91 @@ enum AsmIns
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ASM_JSR = 0x2c
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ASM_JSR = 0x2c
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};
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};
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inline void asm_np(byte ** ip, AsmIns ins)
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inline byte asm_np(byte * ip, AsmIns ins)
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{
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{
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(*ip)[0] = ins & 0xff;
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ip[0] = ins & 0xff;
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(*ip)++;
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return 1;
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}
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}
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inline void asm_zp(byte ** ip, AsmIns ins, byte addr)
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inline byte asm_zp(byte * ip, AsmIns ins, byte addr)
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{
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{
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(*ip)[0] = (ins & 0xff) | 0x04;
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ip[0] = (ins & 0xff) | 0x04;
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(*ip)[1] = addr;
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ip[1] = addr;
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(*ip) += 2;
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return 2;
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}
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}
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inline void asm_rl(byte ** ip, AsmIns ins, byte addr)
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inline byte asm_rl(byte * ip, AsmIns ins, byte addr)
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{
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{
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(*ip)[0] = ins & 0xff;
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ip[0] = ins & 0xff;
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(*ip)[1] = addr;
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ip[1] = addr;
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(*ip) += 2;
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return 2;
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}
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}
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inline void asm_im(byte ** ip, AsmIns ins, byte value)
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inline byte asm_im(byte * ip, AsmIns ins, byte value)
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{
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{
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(*ip)[0] = (ins & 0xff) | ((ins & 0x01) << 3);
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ip[0] = (ins & 0xff) | ((ins & 0x01) << 3);
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(*ip)[1] = value;
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ip[1] = value;
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(*ip) += 2;
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return 2;
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}
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}
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inline void asm_zx(byte ** ip, AsmIns ins, byte addr)
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inline byte asm_zx(byte * ip, AsmIns ins, byte addr)
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{
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{
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(*ip)[0] = (ins & 0xff) | 0x05;
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ip[0] = (ins & 0xff) | 0x05;
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(*ip)[1] = addr;
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ip[1] = addr;
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(*ip) += 2;
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return 2;
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}
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}
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inline void asm_zy(byte ** ip, AsmIns ins, byte addr)
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inline byte asm_zy(byte * ip, AsmIns ins, byte addr)
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{
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{
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(*ip)[0] = (ins & 0xff) | 0x05;
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ip[0] = (ins & 0xff) | 0x05;
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(*ip)[1] = addr;
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ip[1] = addr;
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(*ip) += 2;
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return 2;
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}
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}
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inline void asm_ab(byte ** ip, AsmIns ins, unsigned addr)
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inline byte asm_ab(byte * ip, AsmIns ins, unsigned addr)
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{
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{
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(*ip)[0] = (ins & 0xff) ^ 0x0c;
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ip[0] = (ins & 0xff) ^ 0x0c;
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(*ip)[1] = addr & 0xff;
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ip[1] = addr & 0xff;
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(*ip)[2] = addr >> 8;
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ip[2] = addr >> 8;
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(*ip) += 3;
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return 3;
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}
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}
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inline void asm_in(byte ** ip, AsmIns ins, unsigned addr)
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inline byte asm_in(byte * ip, AsmIns ins, unsigned addr)
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{
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{
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(*ip)[0] = (ins & 0xff) ^ 0x2c;
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ip[0] = (ins & 0xff) ^ 0x2c;
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(*ip)[1] = addr & 0xff;
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ip[1] = addr & 0xff;
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(*ip)[2] = addr >> 8;
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ip[2] = addr >> 8;
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(*ip) += 3;
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return 3;
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}
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}
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inline void asm_ax(byte ** ip, AsmIns ins, unsigned addr)
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inline byte asm_ax(byte * ip, AsmIns ins, unsigned addr)
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{
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{
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(*ip)[0] = (ins & 0xff) | 0x1c;
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ip[0] = (ins & 0xff) | 0x1c;
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(*ip)[1] = addr & 0xff;
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ip[1] = addr & 0xff;
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(*ip)[2] = addr >> 8;
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ip[2] = addr >> 8;
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(*ip) += 3;
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return 3;
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}
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}
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inline void asm_ay(byte ** ip, AsmIns ins, unsigned addr)
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inline byte asm_ay(byte * ip, AsmIns ins, unsigned addr)
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{
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{
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(*ip)[0] = (ins & 0xff) | 0x18;
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ip[0] = (ins & 0xff) | 0x18;
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(*ip)[1] = addr & 0xff;
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ip[1] = addr & 0xff;
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(*ip)[2] = addr >> 8;
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ip[2] = addr >> 8;
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(*ip) += 3;
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return 3;
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}
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}
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inline void asm_ix(byte ** ip, AsmIns ins, byte addr)
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inline byte asm_ix(byte * ip, AsmIns ins, byte addr)
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{
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{
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(*ip)[0] = (ins & 0xff) | 0x00;
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ip[0] = (ins & 0xff) | 0x00;
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(*ip)[1] = addr;
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ip[1] = addr;
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(*ip) += 2;
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return 2;
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}
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}
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inline void asm_iy(byte ** ip, AsmIns ins, byte addr)
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inline byte * asm_iy(byte * ip, AsmIns ins, byte addr)
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{
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{
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(*ip)[0] = (ins & 0xff) | 0x01;
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ip[0] = (ins & 0xff) | 0x01;
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(*ip)[1] = addr;
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ip[1] = addr;
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(*ip) += 2;
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return 2;
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}
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}
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#endif
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#endif
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@ -2,6 +2,7 @@
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#include <c64/vic.h>
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#include <c64/vic.h>
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#include <c64/cia.h>
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#include <c64/cia.h>
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#include <c64/asm6502.h>
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volatile char npos = 1, tpos = 0;
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volatile char npos = 1, tpos = 0;
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@ -164,6 +165,12 @@ void rirq_build(RIRQCode * ic, byte size)
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{
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{
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ic->size = size;
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ic->size = size;
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asm_im(ic->code + 0, ASM_LDY, 0);
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asm_im(ic->code + 2, ASM_LDA, 0);
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asm_ab(ic->code + 4, ASM_CPX, 0xd012);
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asm_rl(ic->code + 7, ASM_BCS, -5);
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asm_ab(ic->code + 9, ASM_STY, 0x0000);
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/*
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ic->code[0] = 0xa0; // ldy #
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ic->code[0] = 0xa0; // ldy #
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ic->code[2] = 0xa9; // lda #
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ic->code[2] = 0xa9; // lda #
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ic->code[4] = 0xec; // cpx
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ic->code[4] = 0xec; // cpx
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@ -172,23 +179,28 @@ void rirq_build(RIRQCode * ic, byte size)
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ic->code[7] = 0xb0; // bcs
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ic->code[7] = 0xb0; // bcs
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ic->code[8] = -5;
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ic->code[8] = -5;
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ic->code[9] = 0x8c; // sty
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ic->code[9] = 0x8c; // sty
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*/
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if (size == 1)
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if (size == 1)
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{
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{
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ic->code[12] = 0x60; // rts
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asm_np(ic->code + 12, ASM_RTS);
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//ic->code[12] = 0x60; // rts
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}
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}
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else
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else
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{
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{
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ic->code[12] = 0x8d; // sty
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asm_ab(ic->code + 12, ASM_STA, 0x0000);
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// ic->code[12] = 0x8d; // sty
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byte p = 15;
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byte p = 15;
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for(byte i=2; i<size; i++)
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for(byte i=2; i<size; i++)
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{
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{
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ic->code[p] = 0xa9; // lda #
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p += asm_im(ic->code + p, ASM_LDA, 0x00);
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ic->code[p + 2] = 0x8d; // sta
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p += asm_ab(ic->code + p, ASM_STA, 0x0000);
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p += 5;
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//ic->code[p] = 0xa9; // lda #
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//ic->code[p + 2] = 0x8d; // sta
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//p += 5;
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}
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}
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ic->code[p] = 0x60;
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asm_np(ic->code + p, ASM_RTS);
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//ic->code[p] = 0x60;
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}
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}
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}
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}
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@ -10272,7 +10272,47 @@ bool NativeCodeBasicBlock::PeepHoleOptimizer(int pass)
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}
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}
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}
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}
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#endif
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#endif
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#if 1
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if (
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mIns[i + 0].mType == ASMIT_LDY && mIns[i + 0].mMode == ASMIM_IMMEDIATE && mIns[i + 0].mAddress <= 3 &&
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mIns[i + 1].mType == ASMIT_STA && mIns[i + 1].mMode == ASMIM_INDIRECT_Y)
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{
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int apos, breg, ireg;
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if (FindAddressSumY(i, mIns[i + 1].mAddress, apos, breg, ireg))
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{
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if (breg != mIns[i + 1].mAddress && ireg != mIns[i + 1].mAddress)// || !(mIns[i + 1].mLive & LIVE_MEM))
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{
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int yoffset = mIns[i + 0].mAddress;
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if (breg == mIns[i + 1].mAddress)
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{
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mIns[apos + 3].mType = ASMIT_NOP;
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mIns[apos + 3].mMode = ASMIM_IMPLIED;
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mIns[apos + 6].mType = ASMIT_NOP;
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mIns[apos + 6].mMode = ASMIM_IMPLIED;
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}
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if (mIns[i + 1].mLive & LIVE_CPU_REG_Y)
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{
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mIns.Insert(i + 2, NativeCodeInstruction(ASMIT_LDY, ASMIM_IMMEDIATE, yoffset));
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mIns[i + 2].mLive |= LIVE_CPU_REG_Y;
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}
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mIns[i + 0].mMode = ASMIM_ZERO_PAGE;
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mIns[i + 0].mAddress = ireg;
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mIns[i + 1].mAddress = breg;
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for(int j=0; j<yoffset; j++)
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{
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mIns.Insert(i + 1, NativeCodeInstruction(ASMIT_INY, ASMIM_IMPLIED));
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mIns[i + 1].mLive = mIns[i + 0].mLive;
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}
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progress = true;
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}
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}
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}
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#endif
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}
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}
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@ -10540,13 +10580,15 @@ bool NativeCodeBasicBlock::PeepHoleOptimizer(int pass)
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#endif
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#endif
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#if 1
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#if 1
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if (
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if (
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mIns[i + 0].mType == ASMIT_LDY && mIns[i + 0].mMode == ASMIM_IMMEDIATE && mIns[i + 0].mAddress == 0 &&
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mIns[i + 0].mType == ASMIT_LDY && mIns[i + 0].mMode == ASMIM_IMMEDIATE && mIns[i + 0].mAddress <= 1 &&
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mIns[i + 1].mType == ASMIT_LDA &&
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mIns[i + 1].mType == ASMIT_LDA &&
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mIns[i + 2].mType == ASMIT_STA && mIns[i + 2].mMode == ASMIM_INDIRECT_Y && !(mIns[i + 2].mLive & LIVE_MEM))
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mIns[i + 2].mType == ASMIT_STA && mIns[i + 2].mMode == ASMIM_INDIRECT_Y && !(mIns[i + 2].mLive & LIVE_MEM))
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{
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{
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int apos, breg, ireg;
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int apos, breg, ireg;
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if (FindAddressSumY(i, mIns[i + 2].mAddress, apos, breg, ireg))
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if (FindAddressSumY(i, mIns[i + 2].mAddress, apos, breg, ireg))
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{
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{
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int yoffset = mIns[i + 0].mAddress;
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if (breg == mIns[i + 2].mAddress)
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if (breg == mIns[i + 2].mAddress)
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{
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{
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mIns[apos + 3].mType = ASMIT_NOP;
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mIns[apos + 3].mType = ASMIT_NOP;
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@ -10556,9 +10598,11 @@ bool NativeCodeBasicBlock::PeepHoleOptimizer(int pass)
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}
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}
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if (mIns[i + 2].mLive & LIVE_CPU_REG_Y)
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if (mIns[i + 2].mLive & LIVE_CPU_REG_Y)
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{
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{
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mIns.Insert(i + 3, NativeCodeInstruction(ASMIT_LDY, ASMIM_IMMEDIATE, 0));
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mIns.Insert(i + 3, NativeCodeInstruction(ASMIT_LDY, ASMIM_IMMEDIATE, yoffset));
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mIns[i + 3].mLive |= LIVE_CPU_REG_Y;
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mIns[i + 3].mLive |= LIVE_CPU_REG_Y;
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}
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}
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int ypos = i;
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if (mIns[i + 1].mMode != ASMIM_INDIRECT_Y && mIns[i + 1].mMode != ASMIM_ABSOLUTE_Y)
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if (mIns[i + 1].mMode != ASMIM_INDIRECT_Y && mIns[i + 1].mMode != ASMIM_ABSOLUTE_Y)
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{
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{
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mIns[i + 0].mMode = ASMIM_ZERO_PAGE;
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mIns[i + 0].mMode = ASMIM_ZERO_PAGE;
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@ -10569,8 +10613,16 @@ bool NativeCodeBasicBlock::PeepHoleOptimizer(int pass)
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{
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{
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mIns.Insert(i + 2, NativeCodeInstruction(ASMIT_LDY, ASMIM_ZERO_PAGE, ireg));
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mIns.Insert(i + 2, NativeCodeInstruction(ASMIT_LDY, ASMIM_ZERO_PAGE, ireg));
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mIns[i + 2].mLive = mIns[i + 3].mLive | LIVE_CPU_REG_Y | LIVE_MEM;
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mIns[i + 2].mLive = mIns[i + 3].mLive | LIVE_CPU_REG_Y | LIVE_MEM;
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ypos = i + 2;
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mIns[i + 3].mAddress = breg;
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mIns[i + 3].mAddress = breg;
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}
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}
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if (yoffset == 1)
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{
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mIns.Insert(ypos + 1, NativeCodeInstruction(ASMIT_INY, ASMIM_IMPLIED));
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mIns[ypos + 1].mLive = mIns[ypos].mLive;
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}
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progress = true;
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progress = true;
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}
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}
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}
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}
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