Optimize adds to ors when possible
This commit is contained in:
parent
425aae8f72
commit
57449e3f4a
|
@ -2238,6 +2238,34 @@ bool NativeCodeInstruction::BitFieldForwarding(NativeRegisterDataSet& data, AsmI
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case ASMIT_ADC:
|
case ASMIT_ADC:
|
||||||
|
if (mMode == ASMIM_IMMEDIATE && data.mRegs[CPU_REG_C].mMask == 1 && data.mRegs[CPU_REG_C].mValue == 0)
|
||||||
|
{
|
||||||
|
if ((mAddress & ~data.mRegs[CPU_REG_A].mMask) == 0 && (mAddress & data.mRegs[CPU_REG_A].mValue) == 0)
|
||||||
|
{
|
||||||
|
mType = ASMIT_ORA;
|
||||||
|
data.mRegs[CPU_REG_A].mValue |= mAddress;
|
||||||
|
changed = true;
|
||||||
|
}
|
||||||
|
else if (mAddress == 1 && (data.mRegs[CPU_REG_A].mMask & 3) == 3 && (data.mRegs[CPU_REG_A].mValue & 3) == 1)
|
||||||
|
{
|
||||||
|
mType = ASMIT_EOR;
|
||||||
|
mAddress = 3;
|
||||||
|
data.mRegs[CPU_REG_A].mValue ^= 3;
|
||||||
|
changed = true;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
data.mRegs[CPU_REG_C].mMask = 0;
|
||||||
|
data.mRegs[CPU_REG_A].mMask = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
data.mRegs[CPU_REG_C].mMask = 0;
|
||||||
|
data.mRegs[CPU_REG_A].mMask = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
break;
|
||||||
case ASMIT_SBC:
|
case ASMIT_SBC:
|
||||||
data.mRegs[CPU_REG_C].mMask = 0;
|
data.mRegs[CPU_REG_C].mMask = 0;
|
||||||
data.mRegs[CPU_REG_A].mMask = 0;
|
data.mRegs[CPU_REG_A].mMask = 0;
|
||||||
|
@ -28069,6 +28097,16 @@ bool NativeCodeBasicBlock::PeepHoleOptimizer(NativeCodeProcedure* proc, int pass
|
||||||
mIns[i + 0].mType = ASMIT_NOP; mIns[i + 0].mMode = ASMIM_IMPLIED;
|
mIns[i + 0].mType = ASMIT_NOP; mIns[i + 0].mMode = ASMIM_IMPLIED;
|
||||||
progress = true;
|
progress = true;
|
||||||
}
|
}
|
||||||
|
else if (
|
||||||
|
mIns[i + 0].mType == ASMIT_LSR && mIns[i + 0].mMode == ASMIM_IMPLIED &&
|
||||||
|
mIns[i + 1].mType == ASMIT_AND && mIns[i + 1].mMode == ASMIM_IMMEDIATE &&
|
||||||
|
mIns[i + 2].mType == ASMIT_ASL && mIns[i + 2].mMode == ASMIM_IMPLIED && !(mIns[i + 2].mLive & LIVE_CPU_REG_C))
|
||||||
|
{
|
||||||
|
mIns[i + 0].mType = ASMIT_NOP; mIns[i + 0].mMode = ASMIM_IMPLIED;
|
||||||
|
mIns[i + 1].mAddress = (mIns[i + 1].mAddress << 1) & 0xff;
|
||||||
|
mIns[i + 2].mType = ASMIT_NOP; mIns[i + 2].mMode = ASMIM_IMPLIED;
|
||||||
|
progress = true;
|
||||||
|
}
|
||||||
else if (
|
else if (
|
||||||
mIns[i + 0].mType == ASMIT_INY &&
|
mIns[i + 0].mType == ASMIT_INY &&
|
||||||
mIns[i + 1].mType == ASMIT_INY &&
|
mIns[i + 1].mType == ASMIT_INY &&
|
||||||
|
|
Loading…
Reference in New Issue