Improve 8 to 16 bit signed add
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3d578170db
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@ -3671,6 +3671,13 @@ bool NativeCodeInstruction::ValueForwarding(NativeRegisterDataSet& data, AsmInsT
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data.mRegs[CPU_REG_A] = data.mRegs[CPU_REG_X];
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if (data.mRegs[CPU_REG_A].mMode == NRDM_IMMEDIATE)
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{
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if (!final)
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{
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mType = ASMIT_LDA;
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mMode = ASMIM_IMMEDIATE;
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mAddress = data.mRegs[CPU_REG_A].mValue;
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}
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data.mRegs[CPU_REG_Z].mMode = NRDM_IMMEDIATE;
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data.mRegs[CPU_REG_Z].mValue = data.mRegs[CPU_REG_A].mValue;
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}
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@ -3690,6 +3697,13 @@ bool NativeCodeInstruction::ValueForwarding(NativeRegisterDataSet& data, AsmInsT
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data.mRegs[CPU_REG_A] = data.mRegs[CPU_REG_Y];
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if (data.mRegs[CPU_REG_A].mMode == NRDM_IMMEDIATE)
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{
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if (!final)
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{
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mType = ASMIT_LDA;
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mMode = ASMIM_IMMEDIATE;
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mAddress = data.mRegs[CPU_REG_A].mValue;
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}
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data.mRegs[CPU_REG_Z].mMode = NRDM_IMMEDIATE;
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data.mRegs[CPU_REG_Z].mValue = data.mRegs[CPU_REG_A].mValue;
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}
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@ -20609,6 +20623,42 @@ bool NativeCodeBasicBlock::ExpandADCToBranch(NativeCodeProcedure* proc)
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break;
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}
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#endif
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#if 1
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if (i + 3 < mIns.Size() &&
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mIns[i + 0].mType == ASMIT_LDA && mIns[i + 0].mMode == ASMIM_IMMEDIATE && mIns[i + 0].mAddress == 0x00 &&
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mIns[i + 1].mType == ASMIT_ADC && mIns[i + 1].mMode == ASMIM_IMMEDIATE && mIns[i + 1].mAddress == 0xff &&
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mIns[i + 2].mType == ASMIT_EOR && mIns[i + 2].mMode == ASMIM_IMMEDIATE && mIns[i + 2].mAddress == 0xff &&
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mIns[i + 3].mType == ASMIT_TAX && !(mIns[i + 3].mLive & (LIVE_CPU_REG_C | LIVE_CPU_REG_Z | LIVE_CPU_REG_A)))
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{
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changed = true;
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NativeCodeBasicBlock* iblock = proc->AllocateBlock();
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NativeCodeBasicBlock* rblock = proc->AllocateBlock();
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rblock->mTrueJump = mTrueJump;
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rblock->mFalseJump = mFalseJump;
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rblock->mBranch = mBranch;
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rblock->mBranchIns = mBranchIns;
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const InterInstruction* iins = mIns[i].mIns;
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for (int j = i + 4; j < mIns.Size(); j++)
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rblock->mIns.Push(mIns[j]);
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mIns.SetSize(i);
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mIns.Push(NativeCodeInstruction(iins, ASMIT_LDX, ASMIM_IMMEDIATE, 0));
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mTrueJump = iblock;
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mFalseJump = rblock;
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mBranch = ASMIT_BCS;
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mBranchIns = iins;
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iblock->mIns.Push(NativeCodeInstruction(iins, ASMIT_LDX, ASMIM_IMMEDIATE, 0xff));
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iblock->Close(iins, rblock, nullptr, ASMIT_JMP);
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break;
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}
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#endif
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#if 1
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if (i + 12 < mIns.Size())
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{
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@ -50415,6 +50465,31 @@ bool NativeCodeBasicBlock::PeepHoleOptimizerExits(int pass)
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changed = true;
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}
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}
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else if (sz >= 3 &&
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mIns[sz - 3].ChangesAccuAndFlag() &&
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mIns[sz - 2].mType == ASMIT_STA &&
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mIns[sz - 1].mType == ASMIT_ASL && mIns[sz - 1].mMode == ASMIM_IMPLIED && !(mIns[sz - 1].mLive & LIVE_CPU_REG_A) && !mExitRequiredRegs[CPU_REG_Z] && !mExitRequiredRegs[CPU_REG_C])
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{
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if (mBranch == ASMIT_BCC)
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{
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mBranch = ASMIT_BPL;
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mIns.SetSize(sz - 1);
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sz -= 1;
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mIns[sz - 2].mLive |= LIVE_CPU_REG_Z;
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mIns[sz - 1].mLive |= LIVE_CPU_REG_Z;
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changed = true;
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}
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else if (mBranch == ASMIT_BCS)
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{
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mBranch = ASMIT_BMI;
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mIns.SetSize(sz - 1);
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sz -= 1;
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mIns[sz - 2].mLive |= LIVE_CPU_REG_Z;
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mIns[sz - 1].mLive |= LIVE_CPU_REG_Z;
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changed = true;
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}
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}
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else if (sz >= 2 &&
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mIns[sz - 2].mType == ASMIT_LDA && mIns[sz - 2].mMode == ASMIM_IMMEDIATE && mIns[sz - 2].mAddress == 0 &&
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mIns[sz - 1].mType == ASMIT_ROL && mIns[sz - 1].mMode == ASMIM_IMPLIED && !(mIns[sz - 1].mLive & (LIVE_CPU_REG_A | LIVE_CPU_REG_C)) && !mExitRequiredRegs[CPU_REG_Z])
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