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Fix clrscr() for VIC20

This commit is contained in:
drmortalwombat 2024-08-13 19:16:19 +02:00
parent 8e81e6aad5
commit 7ffa623d92
3 changed files with 54 additions and 2 deletions
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9
include/conio.c
View File

@ -98,6 +98,15 @@ __asm bsplot
__asm bsinit
{
}
#elif defined(__VIC20__)
#define bsout 0xffd2
#define bsin 0xffe4
#define bsplot 0xfff0
__asm bsinit
{
lda #147
jmp $ffd2
}
#else
#define bsout 0xffd2

4
include/stdio.c
View File

@ -583,7 +583,7 @@ char * sformat(char * buff, const char * fmt, int * fps, bool print)
if (c >= '0' && c <='9')
{
int i = 0;
char i = 0;
while (c >= '0' && c <='9')
{
i = i * 10 + c - '0';
@ -594,7 +594,7 @@ char * sformat(char * buff, const char * fmt, int * fps, bool print)
if (c == '.')
{
int i = 0;
char i = 0;
c = *p++;
while (c >= '0' && c <='9')
{

43
oscar64/NativeCodeGenerator.cpp
View File

@ -25397,6 +25397,49 @@ bool NativeCodeBasicBlock::JoinTailCodeSequences(NativeCodeProcedure* proc, bool
}
#endif
#if 1
if (mEntryBlocks.Size() > 1 && mIns.Size() > 0)
{
if (mIns[0].mType == ASMIT_STA)
{
int ts;
if ((ts = mEntryBlocks[0]->mIns.Size()) >= 2 &&
mEntryBlocks[0]->mIns[ts - 2].mType == ASMIT_LDA &&
mEntryBlocks[0]->mIns[ts - 2].mMode == ASMIM_ZERO_PAGE &&
mEntryBlocks[0]->mIns[ts - 1].mType == ASMIT_ADC)
{
int addr = mEntryBlocks[0]->mIns[ts - 2].mAddress;
int i = 1;
while (i < mEntryBlocks.Size() &&
(ts = mEntryBlocks[i]->mIns.Size()) >= 2 &&
mEntryBlocks[i]->mIns[ts - 2].mType == ASMIT_LDA &&
mEntryBlocks[i]->mIns[ts - 2].mMode == ASMIM_ZERO_PAGE &&
mEntryBlocks[i]->mIns[ts - 2].mAddress == addr &&
mEntryBlocks[i]->mIns[ts - 1].mType == ASMIT_ADC)
i++;
if (i == mEntryBlocks.Size())
{
ts = mEntryBlocks[0]->mIns.Size();
mIns.Insert(0, NativeCodeInstruction(mEntryBlocks[0]->mIns[ts - 2].mIns, ASMIT_ADC, mEntryBlocks[0]->mIns[ts - 2]));
for (int i = 0; i < mEntryBlocks.Size(); i++)
{
ts = mEntryBlocks[i]->mIns.Size();
mEntryBlocks[i]->mIns[ts - 1].mType = ASMIT_LDA;
mEntryBlocks[i]->mIns[ts - 2].mType = ASMIT_NOP;
mEntryBlocks[i]->mIns[ts - 2].mMode = ASMIM_IMPLIED;
mEntryBlocks[i]->mExitRequiredRegs += addr;
mEntryBlocks[i]->mExitRequiredRegs += CPU_REG_C;
}
mEntryRequiredRegs += addr;
mEntryRequiredRegs += CPU_REG_C;
changed = true;
}
}
}
}
#endif
#if 0
if (mFalseJump && mIns.Size() > 1)
{