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Loop optimization for x and y used in simple loop

This commit is contained in:
drmortalwombat 2024-10-20 18:09:50 +02:00
parent 94607cab7f
commit a311396cf8
2 changed files with 33 additions and 1 deletions
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2
include/audio/sidfx.c
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@ -75,7 +75,7 @@ inline void sidfx_loop_ch(byte ch)
channels[ch].state = SIDFX_READY; channels[ch].state = SIDFX_READY;
break; break;
case SIDFX_RESET_1: case SIDFX_RESET_1:
// sid.voices[ch].ctrl = SID_CTRL_TEST; sid.voices[ch].ctrl = SID_CTRL_TEST;
channels[ch].state = SIDFX_READY; channels[ch].state = SIDFX_READY;
break; break;
case SIDFX_READY: case SIDFX_READY:

32
oscar64/NativeCodeGenerator.cpp
View File

@ -36853,6 +36853,38 @@ bool NativeCodeBasicBlock::OptimizeSimpleLoopInvariant(NativeCodeProcedure* proc
return true; return true;
} }
if (sz >= 4 && mIns[0].mType == ASMIT_TAY && mIns[sz - 3].mType == ASMIT_INX && mIns[sz - 2].mType == ASMIT_TXA && mIns[sz - 1].mType == ASMIT_CPX && !ChangesYReg(1) && !ReferencesXReg(0, sz - 3))
{
if (!prevBlock)
return OptimizeSimpleLoopInvariant(proc, full);
for (int i = 0; i < sz; i++)
mIns[i].mLive = LIVE_CPU_REG_Y;
mIns[sz - 3].mType = ASMIT_INY;
mIns[sz - 2].mType = ASMIT_TYA;
mIns[sz - 1].mType = ASMIT_CPY;
if (exitBlock->mEntryRequiredRegs[CPU_REG_X])
{
exitBlock->mEntryRequiredRegs += CPU_REG_A;
exitBlock->mIns.Insert(0, NativeCodeInstruction(mIns[sz - 2].mIns, ASMIT_TAX));
}
prevBlock->mIns.Push(mIns[0]);
mIns.Remove(0);
mExitRequiredRegs += CPU_REG_Y;
mEntryRequiredRegs += CPU_REG_Y;
prevBlock->mExitRequiredRegs += CPU_REG_Y;
prevBlock->CheckLive();
CheckLive();
return true;
}
if (sz >= 3 && mIns[0].mType == ASMIT_LDX && mIns[sz - 2].mType == ASMIT_LDA && mIns[0].SameEffectiveAddress(mIns[sz - 2]) && if (sz >= 3 && mIns[0].mType == ASMIT_LDX && mIns[sz - 2].mType == ASMIT_LDA && mIns[0].SameEffectiveAddress(mIns[sz - 2]) &&
mIns[sz - 1].mType == ASMIT_CMP && HasAsmInstructionMode(ASMIT_CPX, mIns[sz - 1].mMode) && !(mIns[sz - 1].mLive & LIVE_CPU_REG_A)) mIns[sz - 1].mType == ASMIT_CMP && HasAsmInstructionMode(ASMIT_CPX, mIns[sz - 1].mMode) && !(mIns[sz - 1].mLive & LIVE_CPU_REG_A))
{ {