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Fix error in intermediate code peephole optimizer

This commit is contained in:
drmortalwombat 2023-06-09 21:21:35 +02:00
parent 404e9ad998
commit ab9ae6bf0e
2 changed files with 38 additions and 8 deletions
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10
oscar64/InterCode.cpp
View File

@ -11646,6 +11646,7 @@ bool InterCodeBasicBlock::SingleTailLoopOptimization(const NumberSet& aliasedPar
if (!CollidingMem(this, lins, i + 1, mInstructions.Size()) && if (!CollidingMem(this, lins, i + 1, mInstructions.Size()) &&
!CollidingMem(tail, lins, 0, j)) !CollidingMem(tail, lins, 0, j))
{ {
#if 1
int k = 1; int k = 1;
while (k + 1 < body.Size() && !CollidingMem(body[k], lins, 0, body[k]->mInstructions.Size())) while (k + 1 < body.Size() && !CollidingMem(body[k], lins, 0, body[k]->mInstructions.Size()))
k++; k++;
@ -11686,6 +11687,7 @@ bool InterCodeBasicBlock::SingleTailLoopOptimization(const NumberSet& aliasedPar
modified = true; modified = true;
} }
#endif
} }
} }
} }
@ -13516,7 +13518,11 @@ bool InterCodeBasicBlock::PeepholeReplaceOptimization(const GrowingVariableArray
if (i + 2 < mInstructions.Size()) if (i + 2 < mInstructions.Size())
{ {
if (mInstructions[i + 0]->mCode == IC_LOAD && if (mInstructions[i + 0]->mCode == IC_NONE)
{
// just skip it
}
else if (mInstructions[i + 0]->mCode == IC_LOAD &&
mInstructions[i + 1]->mCode == IC_LOAD && mInstructions[i + 1]->mCode == IC_LOAD &&
mInstructions[i + 1]->mSrc[0].mTemp == mInstructions[i + 0]->mSrc[0].mTemp && mInstructions[i + 1]->mSrc[0].mTemp == mInstructions[i + 0]->mSrc[0].mTemp &&
mInstructions[i + 0]->mSrc[0].mIntConst > mInstructions[i + 1]->mSrc[0].mIntConst) mInstructions[i + 0]->mSrc[0].mIntConst > mInstructions[i + 1]->mSrc[0].mIntConst)
@ -15981,7 +15987,7 @@ void InterCodeProcedure::Close(void)
{ {
GrowingTypeArray tstack(IT_NONE); GrowingTypeArray tstack(IT_NONE);
CheckFunc = !strcmp(mIdent->mString, "sformat"); CheckFunc = !strcmp(mIdent->mString, "tile_draw_p");
mEntryBlock = mBlocks[0]; mEntryBlock = mBlocks[0];

36
oscar64/NativeCodeGenerator.cpp
View File

@ -19839,7 +19839,9 @@ bool NativeCodeBasicBlock::JoinTailCodeSequences(NativeCodeProcedure* proc, bool
mFalseJump->mIns.Remove(0); mFalseJump->mIns.Remove(0);
mExitRequiredRegs += CPU_REG_A; mExitRequiredRegs += CPU_REG_A;
mFalseJump->mExitRequiredRegs += CPU_REG_A; mFalseJump->mExitRequiredRegs += CPU_REG_A;
mFalseJump->mEntryRequiredRegs += CPU_REG_A;
mTrueJump->mEntryProvidedRegs += CPU_REG_A; mTrueJump->mEntryProvidedRegs += CPU_REG_A;
mTrueJump->mEntryRequiredRegs += CPU_REG_A;
changed = true; changed = true;
mTrueJump->CheckLive(); mTrueJump->CheckLive();
@ -19854,7 +19856,9 @@ bool NativeCodeBasicBlock::JoinTailCodeSequences(NativeCodeProcedure* proc, bool
mFalseJump->mIns.Remove(0); mFalseJump->mIns.Remove(0);
mExitRequiredRegs += CPU_REG_A; mExitRequiredRegs += CPU_REG_A;
mFalseJump->mExitRequiredRegs += CPU_REG_A; mFalseJump->mExitRequiredRegs += CPU_REG_A;
mFalseJump->mEntryRequiredRegs += CPU_REG_A;
mTrueJump->mEntryProvidedRegs += CPU_REG_A; mTrueJump->mEntryProvidedRegs += CPU_REG_A;
mTrueJump->mEntryRequiredRegs += CPU_REG_A;
changed = true; changed = true;
mTrueJump->CheckLive(); mTrueJump->CheckLive();
@ -24580,6 +24584,8 @@ bool NativeCodeBasicBlock::MoveIndirectLoadStoreUp(int at)
mIns[at + 1].mLive |= mIns[j].mLive; mIns[at + 1].mLive |= mIns[j].mLive;
mIns[at + 2].mLive |= mIns[j].mLive; mIns[at + 2].mLive |= mIns[j].mLive;
mIns[j].mLive |= LIVE_CPU_REG_A;
mIns.Insert(j + 1, mIns[at + 1]); mIns.Insert(j + 1, mIns[at + 1]);
mIns.Insert(j + 2, mIns[at + 3]); mIns.Insert(j + 2, mIns[at + 3]);
mIns[at + 4].mType = ASMIT_NOP; mIns[at + 4].mType = ASMIT_NOP;
@ -26539,10 +26545,12 @@ bool NativeCodeBasicBlock::MoveCLCLoadAddZPStoreUp(int at)
for (int i = j + 1; i < at; i++) for (int i = j + 1; i < at; i++)
mIns[i].mLive |= LIVE_CPU_REG_C; mIns[i].mLive |= LIVE_CPU_REG_C;
mIns[at + 0].mLive |= mIns[j].mLive; mIns[at + 0].mLive |= mIns[j].mLive | LIVE_CPU_REG_A;
mIns[at + 2].mLive |= mIns[j].mLive; mIns[at + 2].mLive |= mIns[j].mLive;
mIns[at + 3].mLive |= mIns[j].mLive; mIns[at + 3].mLive |= mIns[j].mLive;
mIns[j].mLive |= LIVE_CPU_REG_A;
mIns.Insert(j + 1, mIns[at + 3]); // STA mIns.Insert(j + 1, mIns[at + 3]); // STA
mIns.Insert(j + 1, mIns[at + 3]); // ADC mIns.Insert(j + 1, mIns[at + 3]); // ADC
mIns.Insert(j + 1, mIns[at + 2]); // CLC mIns.Insert(j + 1, mIns[at + 2]); // CLC
@ -26714,6 +26722,8 @@ bool NativeCodeBasicBlock::MoveLoadShiftRotateUp(int at)
for (int i = j + 1; i < at; i++) for (int i = j + 1; i < at; i++)
mIns[i].mLive |= LIVE_CPU_REG_C; mIns[i].mLive |= LIVE_CPU_REG_C;
mIns[j].mLive |= LIVE_CPU_REG_A;
mIns.Insert(j + 1, mIns[at + 2]); // ROR ZP mIns.Insert(j + 1, mIns[at + 2]); // ROR ZP
mIns.Insert(j + 1, mIns[at + 2]); // LSR mIns.Insert(j + 1, mIns[at + 2]); // LSR
@ -26753,6 +26763,8 @@ bool NativeCodeBasicBlock::MoveLoadAddZPStoreUp(int at)
mIns[at + 1].mLive |= mIns[j].mLive; mIns[at + 1].mLive |= mIns[j].mLive;
mIns[at + 2].mLive |= mIns[j].mLive; mIns[at + 2].mLive |= mIns[j].mLive;
mIns[j].mLive |= LIVE_CPU_REG_A;
mIns.Insert(j + 1, mIns[at + 2]); // STA mIns.Insert(j + 1, mIns[at + 2]); // STA
mIns.Insert(j + 1, mIns[at + 2]); // ADC mIns.Insert(j + 1, mIns[at + 2]); // ADC
@ -29049,6 +29061,12 @@ bool NativeCodeBasicBlock::OptimizeSimpleLoopInvariant(NativeCodeProcedure* proc
if (!prevBlock) if (!prevBlock)
return OptimizeSimpleLoopInvariant(proc, full); return OptimizeSimpleLoopInvariant(proc, full);
mEntryRequiredRegs += CPU_REG_A;
for(int i=0; i<mIns.Size(); i++)
mIns[i].mLive |= LIVE_CPU_REG_A;
mExitRequiredRegs += CPU_REG_A;
prevBlock->mExitRequiredRegs += CPU_REG_A;
prevBlock->mIns.Push(mIns[ai]); prevBlock->mIns.Push(mIns[ai]);
mIns.Remove(ai); mIns.Remove(ai);
@ -29069,6 +29087,8 @@ bool NativeCodeBasicBlock::OptimizeSimpleLoopInvariant(NativeCodeProcedure* proc
mIns.Remove(ai); mIns.Remove(ai);
mEntryRequiredRegs += CPU_REG_A; mEntryRequiredRegs += CPU_REG_A;
for (int i = 0; i < mIns.Size(); i++)
mIns[i].mLive |= LIVE_CPU_REG_A;
mExitRequiredRegs += CPU_REG_A; mExitRequiredRegs += CPU_REG_A;
prevBlock->mExitRequiredRegs += CPU_REG_A; prevBlock->mExitRequiredRegs += CPU_REG_A;
@ -31543,6 +31563,8 @@ bool NativeCodeBasicBlock::OptimizeSelect(NativeCodeProcedure* proc)
char t = vt; vt = vf; vf = t; char t = vt; vt = vf; vf = t;
} }
mIns[mIns.Size() - 1].mLive |= LIVE_CPU_REG_A;
mIns.Push(NativeCodeInstruction(mBranchIns, ASMIT_CMP, ASMIM_IMMEDIATE, 1)); mIns.Push(NativeCodeInstruction(mBranchIns, ASMIT_CMP, ASMIM_IMMEDIATE, 1));
mIns.Push(NativeCodeInstruction(mBranchIns, ASMIT_LDA, ASMIM_IMMEDIATE, 0)); mIns.Push(NativeCodeInstruction(mBranchIns, ASMIT_LDA, ASMIM_IMMEDIATE, 0));
mIns.Push(NativeCodeInstruction(mBranchIns, ASMIT_ADC, ASMIM_IMMEDIATE, 0xff)); mIns.Push(NativeCodeInstruction(mBranchIns, ASMIT_ADC, ASMIM_IMMEDIATE, 0xff));
@ -34008,7 +34030,7 @@ bool NativeCodeBasicBlock::PeepHoleOptimizer(NativeCodeProcedure* proc, int pass
else else
mIns.Insert(i + 0, NativeCodeInstruction(mIns[i + 0].mIns, ASMIT_LDY, ASMIM_ZERO_PAGE, iins->mAddress)); mIns.Insert(i + 0, NativeCodeInstruction(mIns[i + 0].mIns, ASMIT_LDY, ASMIM_ZERO_PAGE, iins->mAddress));
if (i > 0) if (i > 0)
mIns[i + 0].mLive = mIns[i - 1].mLive | LIVE_CPU_REG_Y | LIVE_MEM; mIns[i + 0].mLive |= mIns[i - 1].mLive | LIVE_CPU_REG_Y | LIVE_MEM;
} }
progress = true; progress = true;
@ -34889,10 +34911,11 @@ bool NativeCodeBasicBlock::PeepHoleOptimizer(NativeCodeProcedure* proc, int pass
{ {
mIns[i + 0].mType = ASMIT_CLC; mIns[i + 0].mType = ASMIT_CLC;
mIns[i + 0].mMode = ASMIM_IMPLIED; mIns[i + 0].mMode = ASMIM_IMPLIED;
mIns[i + 0].mLive |= LIVE_CPU_REG_C; mIns[i + 0].mLive |= LIVE_CPU_REG_C | LIVE_CPU_REG_A;
mIns[i + 1].mType = ASMIT_ADC; mIns[i + 1].mType = ASMIT_ADC;
mIns[i + 1].mMode = ASMIM_IMMEDIATE; mIns[i + 1].mMode = ASMIM_IMMEDIATE;
mIns[i + 1].mAddress = 1; mIns[i + 1].mAddress = 1;
mIns[i + 1].mLive |= LIVE_CPU_REG_A;
mIns[i + 2].mType = ASMIT_STA; mIns[i + 2].mType = ASMIT_STA;
progress = true; progress = true;
} }
@ -34901,6 +34924,7 @@ bool NativeCodeBasicBlock::PeepHoleOptimizer(NativeCodeProcedure* proc, int pass
mIns[i + 1].IsShiftOrInc() && mIns[i + 1].IsShiftOrInc() &&
mIns[i + 2].mType == ASMIT_LDA && mIns[i + 2].SameEffectiveAddress(mIns[i + 0]) && !mIns[i + 2].SameEffectiveAddress(mIns[i + 1]) && !(mIns[i + 2].mLive & LIVE_CPU_REG_Z)) mIns[i + 2].mType == ASMIT_LDA && mIns[i + 2].SameEffectiveAddress(mIns[i + 0]) && !mIns[i + 2].SameEffectiveAddress(mIns[i + 1]) && !(mIns[i + 2].mLive & LIVE_CPU_REG_Z))
{ {
mIns[i + 0].mLive |= LIVE_CPU_REG_A;
mIns[i + 1].mLive |= LIVE_CPU_REG_A; mIns[i + 1].mLive |= LIVE_CPU_REG_A;
mIns[i + 2].mType = ASMIT_NOP; mIns[i + 2].mMode = ASMIM_IMPLIED; mIns[i + 2].mType = ASMIT_NOP; mIns[i + 2].mMode = ASMIM_IMPLIED;
progress = true; progress = true;
@ -39173,11 +39197,11 @@ void NativeCodeBasicBlock::CheckLive(void)
if (mEntryRequiredRegs.Size() > 0) if (mEntryRequiredRegs.Size() > 0)
{ {
if (live & LIVE_CPU_REG_A) if (live & LIVE_CPU_REG_A)
assert(mEntryRequiredRegs[CPU_REG_A]); assert(mEntryRegA || mEntryRequiredRegs[CPU_REG_A]);
if (live & LIVE_CPU_REG_X) if (live & LIVE_CPU_REG_X)
assert(mEntryRequiredRegs[CPU_REG_X]); assert(mEntryRegX || mEntryRequiredRegs[CPU_REG_X]);
if (live & LIVE_CPU_REG_Y) if (live & LIVE_CPU_REG_Y)
assert(mEntryRequiredRegs[CPU_REG_Y]); assert(mEntryRegY || mEntryRequiredRegs[CPU_REG_Y]);
} }
#endif #endif
} }