Optimize index register use for one bit high byte
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@ -21011,6 +21011,71 @@ bool NativeCodeBasicBlock::ExpandADCToBranch(NativeCodeProcedure* proc)
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mBranchIns = iins;
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mBranchIns = iins;
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break;
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break;
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}
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}
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else if (mIns[i + 0].mType == ASMIT_LDA && HasAsmInstructionMode(ASMIT_LDY, mIns[i + 0].mMode) &&
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mIns[i + 1].mType == ASMIT_ADC && mIns[i + 1].mMode == ASMIM_IMMEDIATE && mIns[i + 1].mAddress == 0 &&
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mIns[i + 2].mType == ASMIT_TAY &&
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!(mIns[i + 2].mLive & (LIVE_CPU_REG_A | LIVE_CPU_REG_C | LIVE_CPU_REG_Z)))
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{
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changed = true;
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NativeCodeBasicBlock* iblock = proc->AllocateBlock();
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NativeCodeBasicBlock* fblock = proc->AllocateBlock();
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fblock->mTrueJump = mTrueJump;
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fblock->mFalseJump = mFalseJump;
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fblock->mBranch = mBranch;
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fblock->mBranchIns = mBranchIns;
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const InterInstruction* iins(mIns[i].mIns);
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for (int j = i + 3; j < mIns.Size(); j++)
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fblock->mIns.Push(mIns[j]);
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mIns[i].mType = ASMIT_LDY;
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mIns.SetSize(i + 1);
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iblock->mIns.Push(NativeCodeInstruction(iins, ASMIT_INY));
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iblock->mTrueJump = fblock;
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iblock->mBranch = ASMIT_JMP;
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mTrueJump = fblock;
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mFalseJump = iblock;
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mBranch = ASMIT_BCC;
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mBranchIns = iins;
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break;
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}
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else if (mIns[i + 0].mType == ASMIT_LDA && mIns[i + 0].mMode == ASMIM_IMMEDIATE && mIns[i + 0].mAddress == 0 &&
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mIns[i + 1].mType == ASMIT_ADC && HasAsmInstructionMode(ASMIT_LDY, mIns[i + 1].mMode) &&
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mIns[i + 2].mType == ASMIT_TAY &&
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!(mIns[i + 2].mLive & (LIVE_CPU_REG_A | LIVE_CPU_REG_C | LIVE_CPU_REG_Z)))
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{
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changed = true;
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NativeCodeBasicBlock* iblock = proc->AllocateBlock();
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NativeCodeBasicBlock* fblock = proc->AllocateBlock();
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fblock->mTrueJump = mTrueJump;
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fblock->mFalseJump = mFalseJump;
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fblock->mBranch = mBranch;
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fblock->mBranchIns = mBranchIns;
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const InterInstruction* iins(mIns[i].mIns);
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for (int j = i + 3; j < mIns.Size(); j++)
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fblock->mIns.Push(mIns[j]);
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mIns[i] = mIns[i + 1];
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mIns[i].mType = ASMIT_LDY;
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mIns.SetSize(i + 1);
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iblock->mIns.Push(NativeCodeInstruction(iins, ASMIT_INY));
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iblock->mTrueJump = fblock;
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iblock->mBranch = ASMIT_JMP;
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mTrueJump = fblock;
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mFalseJump = iblock;
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mBranch = ASMIT_BCC;
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mBranchIns = iins;
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break;
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}
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else if (mIns[i + 0].mType == ASMIT_LDA &&
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else if (mIns[i + 0].mType == ASMIT_LDA &&
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mIns[i + 1].mType == ASMIT_SBC && mIns[i + 1].mMode == ASMIM_IMMEDIATE && mIns[i + 1].mAddress == 0 &&
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mIns[i + 1].mType == ASMIT_SBC && mIns[i + 1].mMode == ASMIM_IMMEDIATE && mIns[i + 1].mAddress == 0 &&
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mIns[i + 2].mType == ASMIT_STA && mIns[i + 0].SameEffectiveAddress(mIns[i + 2]) &&
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mIns[i + 2].mType == ASMIT_STA && mIns[i + 0].SameEffectiveAddress(mIns[i + 2]) &&
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@ -48758,6 +48823,31 @@ bool NativeCodeBasicBlock::PeepHoleOptimizerIterateN(int i, int pass)
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}
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}
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}
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}
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if (i + 7 < mIns.Size() &&
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mIns[i + 0].mType == ASMIT_CLC &&
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mIns[i + 1].mType == ASMIT_LDA &&
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mIns[i + 2].mType == ASMIT_ADC &&
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mIns[i + 3].mType == ASMIT_STA && mIns[i + 3].mMode == ASMIM_ZERO_PAGE &&
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mIns[i + 4].mType == ASMIT_LDA && !mIns[i + 4].SameEffectiveAddress(mIns[i + 3]) &&
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mIns[i + 5].mType == ASMIT_AND && mIns[i + 5].mMode == ASMIM_IMMEDIATE &&
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mIns[i + 6].mType == ASMIT_CLC &&
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mIns[i + 7].mType == ASMIT_ADC && mIns[i + 7].SameEffectiveAddress(mIns[i + 3]) && !(mIns[i + 7].mLive & (LIVE_MEM | LIVE_CPU_REG_C)))
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{
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NativeCodeInstruction i4(mIns[i + 4]);
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NativeCodeInstruction i5(mIns[i + 5]);
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NativeCodeInstruction i6(mIns[i + 6]);
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i4.mLive |= LIVE_CPU_REG_C;
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i5.mLive |= LIVE_CPU_REG_C;
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mIns.Remove(i + 3, 5);
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mIns.Insert(i + 1, i4);
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mIns.Insert(i + 2, i5);
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mIns[i + 3].mType = ASMIT_ADC;
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mIns.Insert(i + 4, i6);
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return true;
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}
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if (i + 6 < mIns.Size())
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if (i + 6 < mIns.Size())
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{
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{
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if (
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if (
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@ -51039,7 +51129,7 @@ bool NativeCodeBasicBlock::PeepHoleOptimizerExits(int pass)
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if (mBranch == ASMIT_BCC || mBranch == ASMIT_BCS)
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if (mBranch == ASMIT_BCC || mBranch == ASMIT_BCS)
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{
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{
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AsmInsType ty = ASMIT_INV;
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AsmInsType ty = ASMIT_INV;
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NativeCodeBasicBlock* nblock;
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NativeCodeBasicBlock* nblock = nullptr;
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int tr;
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int tr;
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if (mTrueJump->mIns.Size() > 0 && mTrueJump->mIns[0].mType == ASMIT_TAY && !(mTrueJump->mIns[0].mLive & LIVE_CPU_REG_A) && !mFalseJump->mEntryRequiredRegs[CPU_REG_A] && !mFalseJump->mEntryRequiredRegs[CPU_REG_Y])
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if (mTrueJump->mIns.Size() > 0 && mTrueJump->mIns[0].mType == ASMIT_TAY && !(mTrueJump->mIns[0].mLive & LIVE_CPU_REG_A) && !mFalseJump->mEntryRequiredRegs[CPU_REG_A] && !mFalseJump->mEntryRequiredRegs[CPU_REG_Y])
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@ -51067,10 +51157,14 @@ bool NativeCodeBasicBlock::PeepHoleOptimizerExits(int pass)
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nblock = mFalseJump;
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nblock = mFalseJump;
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}
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}
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if (ty != ASMIT_INV)
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if (nblock)
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{
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{
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mIns[sz - 1].mType = ty;
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mIns[sz - 1].mType = ty;
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mIns[sz - 1].mMode = ASMIM_IMPLIED;
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mIns[sz - 1].mMode = ASMIM_IMPLIED;
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if (tr == CPU_REG_Y)
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mIns[sz - 1].mLive |= LIVE_CPU_REG_Y | LIVE_CPU_REG_Z;
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else
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mIns[sz - 1].mLive |= LIVE_CPU_REG_X | LIVE_CPU_REG_Z;
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nblock->mIns.Remove(0);
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nblock->mIns.Remove(0);
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mExitRequiredRegs += tr;
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mExitRequiredRegs += tr;
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nblock->mEntryRequiredRegs += tr;
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nblock->mEntryRequiredRegs += tr;
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