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Disable vtable dispatcher inlining

This commit is contained in:
drmortalwombat 2023-11-02 08:18:09 +01:00
parent 8aeddf0316
commit d9c84e3a15
2 changed files with 33 additions and 0 deletions
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1
oscar64/GlobalAnalyzer.cpp
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@ -794,6 +794,7 @@ Declaration * GlobalAnalyzer::Analyze(Expression* exp, Declaration* procDec, boo
Analyze(exp->mLeft, procDec, lhs); Analyze(exp->mLeft, procDec, lhs);
return exp->mDecValue->mBase; return exp->mDecValue->mBase;
case EX_DISPATCH: case EX_DISPATCH:
procDec->mFlags |= DTF_PREVENT_INLINE;
Analyze(exp->mLeft, procDec, lhs); Analyze(exp->mLeft, procDec, lhs);
// RegisterCall(procDec, exp->mLeft->mDecType); // RegisterCall(procDec, exp->mLeft->mDecType);
break; break;

32
oscar64/NativeCodeGenerator.cpp
View File

@ -39483,6 +39483,38 @@ bool NativeCodeBasicBlock::PeepHoleOptimizer(NativeCodeProcedure* proc, int pass
mIns[i + 4].mType = ASMIT_DEC; mIns[i + 4].mType = ASMIT_DEC;
progress = true; progress = true;
} }
else if (
mIns[i + 0].mType == ASMIT_LDY && (mIns[i + 0].mMode == ASMIM_ZERO_PAGE || mIns[i + 0].mMode == ASMIM_ABSOLUTE) &&
mIns[i + 1].mType == ASMIT_TYA &&
mIns[i + 2].mType == ASMIT_CLC &&
mIns[i + 3].mType == ASMIT_ADC && mIns[i + 3].mMode == ASMIM_IMMEDIATE && (mIns[i + 3].mAddress == 0xff || mIns[i + 3].mAddress == 0x01) &&
mIns[i + 4].mType == ASMIT_STA && mIns[i + 0].SameEffectiveAddress(mIns[i + 4]) && !(mIns[i + 4].mLive & (LIVE_CPU_REG_A | LIVE_CPU_REG_C)))
{
mIns[i + 1].mType = ASMIT_NOP; mIns[i + 1].mMode = ASMIM_IMPLIED;
mIns[i + 2].mType = ASMIT_NOP; mIns[i + 2].mMode = ASMIM_IMPLIED;
mIns[i + 3].mType = ASMIT_NOP; mIns[i + 3].mMode = ASMIM_IMPLIED;
if (mIns[i + 3].mAddress == 0x01)
mIns[i + 4].mType = ASMIT_INC;
else
mIns[i + 4].mType = ASMIT_DEC;
progress = true;
}
else if (
mIns[i + 0].mType == ASMIT_LDX && (mIns[i + 0].mMode == ASMIM_ZERO_PAGE || mIns[i + 0].mMode == ASMIM_ABSOLUTE) &&
mIns[i + 1].mType == ASMIT_TXA &&
mIns[i + 2].mType == ASMIT_CLC &&
mIns[i + 3].mType == ASMIT_ADC && mIns[i + 3].mMode == ASMIM_IMMEDIATE && (mIns[i + 3].mAddress == 0xff || mIns[i + 3].mAddress == 0x01) &&
mIns[i + 4].mType == ASMIT_STA && mIns[i + 0].SameEffectiveAddress(mIns[i + 4]) && !(mIns[i + 4].mLive & (LIVE_CPU_REG_A | LIVE_CPU_REG_C)))
{
mIns[i + 1].mType = ASMIT_NOP; mIns[i + 1].mMode = ASMIM_IMPLIED;
mIns[i + 2].mType = ASMIT_NOP; mIns[i + 2].mMode = ASMIM_IMPLIED;
mIns[i + 3].mType = ASMIT_NOP; mIns[i + 3].mMode = ASMIM_IMPLIED;
if (mIns[i + 3].mAddress == 0x01)
mIns[i + 4].mType = ASMIT_INC;
else
mIns[i + 4].mType = ASMIT_DEC;
progress = true;
}
#endif #endif
#endif #endif
} }