From e82ab0c7ca2568caa9491a2ec5c2296ba9b461af Mon Sep 17 00:00:00 2001
From: drmortalwombat <90205530+drmortalwombat@users.noreply.github.com>
Date: Tue, 6 May 2025 18:38:44 +0200
Subject: [PATCH] Improve shift carry combine

---
 oscar64/NativeCodeGenerator.cpp | 58 +++++++++++++++++++++++++++++++--
 1 file changed, 56 insertions(+), 2 deletions(-)

diff --git a/oscar64/NativeCodeGenerator.cpp b/oscar64/NativeCodeGenerator.cpp
index 02d91ab..8c3bb78 100644
--- a/oscar64/NativeCodeGenerator.cpp
+++ b/oscar64/NativeCodeGenerator.cpp
@@ -3019,8 +3019,17 @@ bool NativeCodeInstruction::BitFieldForwarding(NativeRegisterDataSet& data, AsmI
 	case ASMIT_LDA:
 		if (mMode == ASMIM_IMMEDIATE)
 		{
-			data.mRegs[CPU_REG_A].mMask = 0xff;
-			data.mRegs[CPU_REG_A].mValue = mAddress & 0xff;
+			if (data.mRegs[CPU_REG_A].mMask == 0xff && data.mRegs[CPU_REG_A].mValue == mAddress && !(mLive & LIVE_CPU_REG_Z))
+			{
+				mType = ASMIT_NOP;
+				mMode = ASMIM_IMPLIED;
+				changed = true;
+			}
+			else
+			{
+				data.mRegs[CPU_REG_A].mMask = 0xff;
+				data.mRegs[CPU_REG_A].mValue = mAddress & 0xff;
+			}
 		}
 		else
 		{
@@ -36940,6 +36949,12 @@ bool NativeCodeBasicBlock::BitFieldForwarding(const NativeRegisterDataSet& data)
 								mNDataSet.mRegs[lins.mAddress].mMask = 0xff;
 								mNDataSet.mRegs[lins.mAddress].mValue = 0x00;
 							}
+
+							if (mFDataSet.mRegs[CPU_REG_A].mMask == 0xfe)
+							{
+								mFDataSet.mRegs[CPU_REG_A].mMask = 0xff;
+								mFDataSet.mRegs[CPU_REG_A].mValue = 0x01;
+							}
 						}
 						break;
 					case ASMIT_BNE:
@@ -36969,6 +36984,12 @@ bool NativeCodeBasicBlock::BitFieldForwarding(const NativeRegisterDataSet& data)
 								mFDataSet.mRegs[lins.mAddress].mMask = 0xff;
 								mFDataSet.mRegs[lins.mAddress].mValue = 0x00;
 							}
+
+							if (mNDataSet.mRegs[CPU_REG_A].mMask == 0xfe)
+							{
+								mNDataSet.mRegs[CPU_REG_A].mMask = 0xff;
+								mNDataSet.mRegs[CPU_REG_A].mValue = 0x01;
+							}
 						}
 						break;
 					case ASMIT_BPL:
@@ -45191,6 +45212,39 @@ bool NativeCodeBasicBlock::PeepHoleOptimizerShuffle(int pass)
 	CheckLive();
 #endif
 
+	// Combine and shift
+	for (int i = 1; i + 2 < mIns.Size(); i++)
+	{
+		if (mIns[i + 0].mType == ASMIT_AND && mIns[i + 0].mMode == ASMIM_IMMEDIATE && mIns[i + 0].mAddress == 0x01 &&
+			mIns[i + 1].mType == ASMIT_ORA && mIns[i + 1].mMode == ASMIM_ZERO_PAGE &&
+			mIns[i + 2].mType == ASMIT_STA && mIns[i + 2].mMode == ASMIM_ZERO_PAGE && mIns[i + 1].mAddress == mIns[i + 2].mAddress &&
+			!(mIns[i + 2].mLive & LIVE_CPU_REG_C))
+		{
+			int j = i - 1;
+			while (j >= 0 && !mIns[j].ReferencesZeroPage(mIns[i + 1].mAddress))
+				j--;
+			if (j >= 0 && mIns[j].IsShift() && !(mIns[j].mLive & LIVE_CPU_REG_C))
+			{
+				if (mIns[j].mType == ASMIT_ASL)
+				{
+					mIns[i + 0].mType = ASMIT_LSR; mIns[i + 0].mMode = ASMIM_IMPLIED; mIns[i + 0].mLive |= LIVE_CPU_REG_C;
+					mIns[i + 1].mType = ASMIT_ROL;
+					mIns[i + 2].mType = ASMIT_LDA;
+					mIns[j + 0].mType = ASMIT_NOP; mIns[j + 0].mMode = ASMIM_IMPLIED;
+					changed = true;
+				}
+				else if (mIns[j].mType == ASMIT_LSR)
+				{
+					mIns[i + 0].mType = ASMIT_LSR; mIns[i + 0].mMode = ASMIM_IMPLIED; mIns[i + 0].mLive |= LIVE_CPU_REG_C;
+					mIns[i + 1].mType = ASMIT_ROR;
+					mIns[i + 2].mType = ASMIT_LDA;
+					mIns[j + 0].mType = ASMIT_NOP; mIns[j + 0].mMode = ASMIM_IMPLIED;
+					changed = true;
+				}
+			}
+		}
+	}
+
 #if 1
 	for (int i = 0; i < mIns.Size(); i++)
 	{