From f5dff9620bc7eea9f134c86aced5c8e63adb4081 Mon Sep 17 00:00:00 2001
From: drmortalwombat <90205530+drmortalwombat@users.noreply.github.com>
Date: Tue, 7 Jan 2025 22:07:36 +0100
Subject: [PATCH] Fix degrading merge of stores that prevent absolute
 addressing

---
 oscar64/InterCode.cpp           | 14 +++++++++++++-
 oscar64/NativeCodeGenerator.cpp |  2 ++
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/oscar64/InterCode.cpp b/oscar64/InterCode.cpp
index aa045b4..07a2a59 100644
--- a/oscar64/InterCode.cpp
+++ b/oscar64/InterCode.cpp
@@ -23035,7 +23035,7 @@ void InterCodeProcedure::Close(void)
 {
 	GrowingTypeArray	tstack(IT_NONE);
 	
-	CheckFunc = !strcmp(mIdent->mString, "getActor");
+	CheckFunc = !strcmp(mIdent->mString, "enemies_iterate");
 	CheckCase = false;
 
 	mEntryBlock = mBlocks[0];
@@ -24279,6 +24279,16 @@ bool InterCodeBasicBlock::SameExitCode(const InterCodeBasicBlock* block) const
 						}
 					}
 				}
+				else if (j0 >= 0)
+				{
+					if (mInstructions[j0]->mCode == IC_LEA && mInstructions[j0]->mSrc[1].mTemp < 0 && mInstructions[j0]->mSrc[0].IsUByte())
+						return false;
+				}
+				else if (j1 >= 0)
+				{
+					if (block->mInstructions[j1]->mCode == IC_LEA && block->mInstructions[j1]->mSrc[1].mTemp < 0 && block->mInstructions[j1]->mSrc[0].IsUByte())
+						return false;
+				}
 
 				if (InterTypeSize[ins0->mSrc[0].mType] == 4)
 				{
@@ -24359,6 +24369,8 @@ bool PartitionSameExitCode(GrowingArray<InterCodeBasicBlock* > & eblocks, Growin
 
 bool InterCodeProcedure::ShortLeaMerge(FastNumberSet& activeSet)
 {
+	DisassembleDebug("PreShortLeaMerge");
+
 	int		silvused = mTemporaries.Size();
 
 	int		n = 0;
diff --git a/oscar64/NativeCodeGenerator.cpp b/oscar64/NativeCodeGenerator.cpp
index 39a1a8b..5a100c7 100644
--- a/oscar64/NativeCodeGenerator.cpp
+++ b/oscar64/NativeCodeGenerator.cpp
@@ -48630,6 +48630,8 @@ bool NativeCodeBasicBlock::PeepHoleOptimizerIterate6(int i, int pass)
 		mIns[i + 5].mLive |= (mIns[i + 4].mLive & (LIVE_CPU_REG_C | LIVE_CPU_REG_Z));
 		mIns[i + 0].mLive |= livexy;
 		mIns[i + 1].mLive |= livexy;
+		mIns[i + 2].mLive |= LIVE_CPU_REG_C | livexy;
+		mIns[i + 3].mLive |= LIVE_CPU_REG_C;
 		return true;
 	}