From f6a2db7866460f09787b5fab94f913379edddee2 Mon Sep 17 00:00:00 2001
From: drmortalwombat <90205530+drmortalwombat@users.noreply.github.com>
Date: Thu, 9 Jan 2025 20:12:09 +0100
Subject: [PATCH] Reuse index register transfer to avoid compare

---
 oscar64/NativeCodeGenerator.cpp | 52 ++++++++++++++++++++++++++++++++-
 1 file changed, 51 insertions(+), 1 deletion(-)

diff --git a/oscar64/NativeCodeGenerator.cpp b/oscar64/NativeCodeGenerator.cpp
index 5a100c7..c1726f1 100644
--- a/oscar64/NativeCodeGenerator.cpp
+++ b/oscar64/NativeCodeGenerator.cpp
@@ -50667,7 +50667,6 @@ bool NativeCodeBasicBlock::PeepHoleOptimizerExits(int pass)
 		}
 	}
 
-
 	else if (sz >= 4 &&
 		mIns[sz - 4].mType == ASMIT_EOR && mIns[sz - 4].mMode == ASMIM_IMMEDIATE && mIns[sz - 4].mAddress == 0x80 &&
 		mIns[sz - 3].mType == ASMIT_STA && mIns[sz - 3].mMode == ASMIM_ZERO_PAGE &&
@@ -51034,6 +51033,57 @@ bool NativeCodeBasicBlock::PeepHoleOptimizerExits(int pass)
 	}
 #endif
 
+#if 1
+	if (sz >= 1 && mIns[sz - 1].mType == ASMIT_CMP && mIns[sz - 1].mMode == ASMIM_IMMEDIATE && mIns[sz - 1].mAddress == 0x80 && !(mIns[sz - 1].mLive & LIVE_CPU_REG_Z))
+	{
+		if (mBranch == ASMIT_BCC || mBranch == ASMIT_BCS)
+		{
+			AsmInsType	ty = ASMIT_INV;
+			NativeCodeBasicBlock* nblock;
+			int tr;
+
+			if (mTrueJump->mIns.Size() > 0 && mTrueJump->mIns[0].mType == ASMIT_TAY && !(mTrueJump->mIns[0].mLive & LIVE_CPU_REG_A) && !mFalseJump->mEntryRequiredRegs[CPU_REG_A] && !mFalseJump->mEntryRequiredRegs[CPU_REG_Y])
+			{
+				ty = ASMIT_TAY;
+				tr = CPU_REG_Y;
+				nblock = mTrueJump;
+			}
+			else if (mTrueJump->mIns.Size() > 0 && mTrueJump->mIns[0].mType == ASMIT_TAX && !(mTrueJump->mIns[0].mLive & LIVE_CPU_REG_A) && !mFalseJump->mEntryRequiredRegs[CPU_REG_A] && !mFalseJump->mEntryRequiredRegs[CPU_REG_X])
+			{
+				ty = ASMIT_TAX;
+				tr = CPU_REG_X;
+				nblock = mTrueJump;
+			}
+			else if (mFalseJump->mIns.Size() > 0 && mFalseJump->mIns[0].mType == ASMIT_TAY && !(mFalseJump->mIns[0].mLive & LIVE_CPU_REG_A) && !mTrueJump->mEntryRequiredRegs[CPU_REG_A] && !mTrueJump->mEntryRequiredRegs[CPU_REG_Y])
+			{
+				ty = ASMIT_TAY;
+				tr = CPU_REG_Y;
+				nblock = mFalseJump;
+			}
+			else if (mFalseJump->mIns.Size() > 0 && mFalseJump->mIns[0].mType == ASMIT_TAX && !(mFalseJump->mIns[0].mLive & LIVE_CPU_REG_A) && !mTrueJump->mEntryRequiredRegs[CPU_REG_A] && !mTrueJump->mEntryRequiredRegs[CPU_REG_X])
+			{
+				ty = ASMIT_TAX;
+				tr = CPU_REG_X;
+				nblock = mFalseJump;
+			}
+
+			if (ty != ASMIT_INV)
+			{
+				mIns[sz - 1].mType = ty;
+				mIns[sz - 1].mMode = ASMIM_IMPLIED;
+				nblock->mIns.Remove(0);
+				mExitRequiredRegs += tr;
+				nblock->mEntryRequiredRegs += tr;
+				if (mBranch == ASMIT_BCC)
+					mBranch = ASMIT_BPL;
+				else
+					mBranch = ASMIT_BMI;
+				changed = true;
+			}
+		}
+	}
+#endif
+
 #if 1
 	if (sz > 0 && mFalseJump && mIns[sz - 1].ChangesAccuAndFlag() && mBranch == ASMIT_BMI)
 	{