Whitespace cleanup.
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parent
6870c08157
commit
26c5a8dfdd
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@ -230,7 +230,7 @@ ATIDRIAgpInit(ScreenPtr pScreen)
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MMIO_OUT32(mmio, R128_REG_PCI_GART_PAGE, 1);
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MMIO_OUT32(mmio, R128_REG_PCI_GART_PAGE, 1);
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}
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}
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return TRUE;
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return TRUE;
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}
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}
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static Bool
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static Bool
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@ -254,7 +254,6 @@ ATIDRIPciInit(ScreenPtr pScreen)
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ErrorF("[pci] %d kB allocated with handle 0x%08lx\n",
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ErrorF("[pci] %d kB allocated with handle 0x%08lx\n",
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atis->gartSize*1024, (long)atis->pciMemHandle);
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atis->gartSize*1024, (long)atis->pciMemHandle);
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if (!ATIDRIAddAndMap(atic->drmFd, atis->ringStart, atis->ringMapSize,
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if (!ATIDRIAddAndMap(atic->drmFd, atis->ringStart, atis->ringMapSize,
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DRM_SCATTER_GATHER, DRM_READ_ONLY | DRM_LOCKED | DRM_KERNEL,
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DRM_SCATTER_GATHER, DRM_READ_ONLY | DRM_LOCKED | DRM_KERNEL,
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&atis->ringHandle, (drmAddressPtr)&atis->ring, "ring"))
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&atis->ringHandle, (drmAddressPtr)&atis->ring, "ring"))
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@ -606,8 +605,8 @@ ATIDRIScreenInit(ScreenPtr pScreen)
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}
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}
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/* Add a map for the MMIO registers that will be accessed by any
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/* Add a map for the MMIO registers that will be accessed by any
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* DRI-based clients.
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* DRI-based clients.
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*/
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*/
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atis->registerSize = RADEON_REG_SIZE(atic);
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atis->registerSize = RADEON_REG_SIZE(atic);
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if (drmAddMap(atic->drmFd, RADEON_REG_BASE(pScreenPriv->screen->card),
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if (drmAddMap(atic->drmFd, RADEON_REG_BASE(pScreenPriv->screen->card),
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atis->registerSize, DRM_REGISTERS, DRM_READ_ONLY,
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atis->registerSize, DRM_REGISTERS, DRM_READ_ONLY,
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