Add tracing. Hack Radeon cache registers to use 3D addresses. Works on M6
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6eaca06dac
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3b1f1508b1
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@ -343,6 +343,22 @@ ATIUnmapReg(KdCardInfo *card, ATICardInfo *atic);
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void
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R300CGWorkaround(ATIScreenInfo *atis);
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#define ATI_TRACE 0
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#if ATI_TRACE
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#define ENTER_DRAW(pix) ATIEnterDraw(pix, __FUNCTION__)
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#define LEAVE_DRAW(pix) ATILeaveDraw(pix, __FUNCTION__)
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void
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ATIEnterDraw (PixmapPtr pPixmap, char *function);
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void
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ATILeaveDraw (PixmapPtr pPixmap, char *function);
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#else
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#define ENTER_DRAW(pix)
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#define LEAVE_DRAW(pix)
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#endif
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/* ati_draw.c */
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void
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ATIDrawSetup(ScreenPtr pScreen);
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@ -153,13 +153,16 @@ ATIDrawSetup(ScreenPtr pScreen)
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END_DMA();
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if (atic->is_r100) {
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BEGIN_DMA(4);
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BEGIN_DMA(6);
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OUT_REG(RADEON_REG_SE_CNTL_STATUS, RADEON_TCL_BYPASS);
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OUT_REG(RADEON_REG_SE_COORD_FMT,
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RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
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RADEON_VTX_ST0_NONPARAMETRIC |
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RADEON_VTX_ST1_NONPARAMETRIC |
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RADEON_TEX1_W_ROUTING_USE_W0);
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OUT_REG(RADEON_REG_RB3D_DSTCACHE_MODE,
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RADEON_RB2D_DC_2D_CACHE_AUTOFLUSH|
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RADEON_RB2D_DC_3D_CACHE_AUTOFLUSH);
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END_DMA();
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} else {
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BEGIN_DMA(16);
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@ -186,12 +189,14 @@ RadeonSwitchTo2D(ATIScreenInfo *atis)
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{
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RING_LOCALS;
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ENTER_DRAW(0);
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BEGIN_DMA(4);
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OUT_REG(RADEON_REG_RB2D_DSTCACHE_CTLSTAT,
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RADEON_RB2D_DC_FLUSH);
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OUT_REG(ATI_REG_WAIT_UNTIL,
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RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
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END_DMA();
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LEAVE_DRAW(0);
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}
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void
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@ -199,14 +204,52 @@ RadeonSwitchTo3D(ATIScreenInfo *atis)
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{
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RING_LOCALS;
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ENTER_DRAW(0);
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BEGIN_DMA(4);
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OUT_REG(RADEON_REG_RB2D_DSTCACHE_CTLSTAT,
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RADEON_RB2D_DC_FLUSH);
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OUT_REG(ATI_REG_WAIT_UNTIL,
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RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_2D_IDLECLEAN);
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END_DMA();
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LEAVE_DRAW(0);
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}
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#if ATI_TRACE
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void
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ATIEnterDraw (PixmapPtr pPix, char *function)
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{
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if (pPix)
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{
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KdScreenPriv(pPix->drawable.pScreen);
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CARD32 offset;
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offset = ((CARD8 *)pPix->devPrivate.ptr -
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pScreenPriv->screen->memory_base);
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ErrorF ("Enter %s 0x%x\n", function, offset);
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}
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else
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ErrorF ("Enter %s\n", function);
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}
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void
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ATILeaveDraw (PixmapPtr pPix, char *function)
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{
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if (pPix)
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{
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KdScreenPriv(pPix->drawable.pScreen);
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CARD32 offset;
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offset = ((CARD8 *)pPix->devPrivate.ptr -
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pScreenPriv->screen->memory_base);
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ErrorF ("Leave %s 0x%x\n", function, offset);
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}
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else
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ErrorF ("Leave %s\n", function);
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}
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#endif
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/* Assumes that depth 15 and 16 can be used as depth 16, which is okay since we
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* require src and dest datatypes to be equal.
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*/
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@ -310,6 +353,8 @@ ATIPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
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if (!ATIGetPixmapOffsetPitch(pPix, &dst_pitch_offset))
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return FALSE;
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ENTER_DRAW(pPix);
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if (atic->is_radeon)
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RadeonSwitchTo2D(atis);
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@ -344,12 +389,14 @@ ATIPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
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END_DMA();
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#endif
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LEAVE_DRAW(pPix);
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return TRUE;
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}
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static void
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ATISolid(int x1, int y1, int x2, int y2)
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{
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ENTER_DRAW(0);
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ATIScreenInfo *atis = accel_atis;
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RING_LOCALS;
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@ -373,11 +420,14 @@ ATISolid(int x1, int y1, int x2, int y2)
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OUT_RING(((y2 - y1) << 16) | (x2 - x1));
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END_DMA();
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#endif
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LEAVE_DRAW(0);
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}
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static void
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ATIDoneSolid(void)
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{
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ENTER_DRAW(0);
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LEAVE_DRAW(0);
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}
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static Bool
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@ -405,6 +455,7 @@ ATIPrepareCopy(PixmapPtr pSrc, PixmapPtr pDst, int dx, int dy, int alu, Pixel pm
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if (!ATIGetPixmapOffsetPitch(pDst, &dst_pitch_offset))
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return FALSE;
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ENTER_DRAW (pDst);
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if (atic->is_radeon)
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RadeonSwitchTo2D(atis);
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@ -442,6 +493,7 @@ ATIPrepareCopy(PixmapPtr pSrc, PixmapPtr pDst, int dx, int dy, int alu, Pixel pm
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(dy >= 0 ? ATI_DST_Y_TOP_TO_BOTTOM : 0));
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END_DMA();
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#endif
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LEAVE_DRAW(pDst);
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return TRUE;
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}
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@ -508,6 +560,8 @@ ATIUploadToScreen(PixmapPtr pDst, char *src, int src_pitch)
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Bool success;
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RING_LOCALS;
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ENTER_DRAW (pDst);
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dst_offset = ((CARD8 *)pDst->devPrivate.ptr -
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pScreenPriv->screen->memory_base);
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dst_pitch = pDst->devKind;
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@ -534,6 +588,8 @@ ATIUploadToScreen(PixmapPtr pDst, char *src, int src_pitch)
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if (atis->using_pio)
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return FALSE;
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LEAVE_DRAW (pDst);
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/* XXX: Hostdata uploads aren't working yet. */
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return FALSE;
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@ -545,7 +601,7 @@ ATIUploadToScreen(PixmapPtr pDst, char *src, int src_pitch)
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if (atic->is_radeon) {
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BEGIN_DMA(4);
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OUT_REG(RADEON_REG_RB2D_DSTCACHE_CTLSTAT,
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RADEON_RB2D_DC_FLUSH);
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RADEON_RB2D_DC_FLUSH_ALL);
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OUT_REG(ATI_REG_WAIT_UNTIL,
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RADEON_WAIT_2D_IDLECLEAN |
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RADEON_WAIT_3D_IDLECLEAN |
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@ -586,7 +642,7 @@ ATIUploadToScreen(PixmapPtr pDst, char *src, int src_pitch)
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if (atic->is_radeon) {
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BEGIN_DMA(4);
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OUT_REG(RADEON_REG_RB2D_DSTCACHE_CTLSTAT,
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RADEON_RB2D_DC_FLUSH);
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RADEON_RB2D_DC_FLUSH_ALL);
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OUT_REG(ATI_REG_WAIT_UNTIL,
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RADEON_WAIT_2D_IDLECLEAN |
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RADEON_WAIT_HOST_IDLECLEAN);
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@ -615,6 +671,7 @@ ATIUploadToScratch(PixmapPtr pSrc, PixmapPtr pDst)
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unsigned char *dst, *src;
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RING_LOCALS;
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ENTER_DRAW(pSrc);
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/* Align width to log 2, useful for R128 composite. This should be a
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* KAA flag we check for (and supported in kaa.c in general) since many
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* older bits of hardware are going to want POT pitches.
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@ -669,6 +726,7 @@ ATIUploadToScratch(PixmapPtr pSrc, PixmapPtr pDst)
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END_DMA();
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}
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LEAVE_DRAW(pSrc);
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return TRUE;
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}
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@ -761,6 +819,7 @@ ATIDrawEnable(ScreenPtr pScreen)
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ATIDMASetup(pScreen);
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ATIDrawSetup(pScreen);
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atis->scratch_area = NULL;
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atis->kaa.PrepareBlend = NULL;
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atis->kaa.Blend = NULL;
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atis->kaa.DoneBlend = NULL;
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@ -768,7 +827,10 @@ ATIDrawEnable(ScreenPtr pScreen)
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atis->kaa.PrepareComposite = NULL;
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atis->kaa.Composite = NULL;
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atis->kaa.DoneComposite = NULL;
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atis->kaa.UploadToScreen = NULL;
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atis->kaa.UploadToScratch = NULL;
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#if 1
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/* We can't dispatch 3d commands in PIO mode. */
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if (!atis->using_pio) {
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if (!atic->is_radeon) {
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@ -813,8 +875,8 @@ ATIDrawEnable(ScreenPtr pScreen)
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if (atis->scratch_area != NULL) {
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atis->scratch_next = atis->scratch_area->offset;
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atis->kaa.UploadToScratch = ATIUploadToScratch;
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} else
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atis->kaa.UploadToScratch = NULL;
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}
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#endif
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KdMarkSync(pScreen);
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}
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@ -850,5 +912,7 @@ ATIDrawSync(ScreenPtr pScreen)
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KdScreenPriv(pScreen);
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ATIScreenInfo(pScreenPriv);
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ENTER_DRAW(0);
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ATIWaitIdle(atis);
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LEAVE_DRAW(0);
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}
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@ -1715,7 +1715,26 @@
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# define R200_TXA_REPL_ARG_C_SHIFT 30
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# define R200_TXA_REPL_ARG_C_MASK (3 << 30)
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#define RADEON_REG_RB2D_DSTCACHE_CTLSTAT 0x342c
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#define RADEON_REG_RB2D_DSTCACHE_MODE 0x3428
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#define RADEON_REG_RB3D_DSTCACHE_MODE 0x3258
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# define RADEON_RB2D_DC_CACHE_ENABLE 0
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# define RADEON_RB2D_DC_2D_CACHE_DISABLE 1
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# define RADEON_RB2D_DC_3D_CACHE_DISABLE 1
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# define RADEON_RB2D_DC_CACHE_DISABLE 3
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# define RADEON_RB2D_DC_2D_CACHE_LINESIZE_128 4
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# define RADEON_RB2D_DC_3D_CACHE_LINESIZE_128 8
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# define RADEON_RB2D_DC_2D_CACHE_AUTOFLUSH 0x100
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# define RADEON_RB2D_DC_3D_CACHE_AUTOFLUSH 0x200
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# define RADEON_RB2D_DC_FORCE_RMW 0x10000
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# define RADEON_RB2D_DC_DISABLE_RI_FILL 0x1000000
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# define RADEON_RB2D_DC_DISABLE_RI_READ 0x2000000
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/* XXX The 2D shadow isn't writable on the M6. The right fix is to rename
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* all uses, but Eric is doing that
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*/
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/* #define RADEON_REG_RB2D_DSTCACHE_CTLSTAT 0x342C */
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#define RADEON_REG_RB2D_DSTCACHE_CTLSTAT 0x325C
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#define RADEON_REG_RB3D_DSTCACHE_CTLSTAT 0x325C
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# define RADEON_RB2D_DC_FLUSH (3 << 0)
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# define RADEON_RB2D_DC_FREE (3 << 2)
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# define RADEON_RB2D_DC_FLUSH_ALL 0xf
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@ -251,6 +251,9 @@ R100CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture,
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if (pMaskPicture != NULL && !R100CheckCompositeTexture(pMaskPicture, 1))
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return FALSE;
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if (pDstPicture->componentAlpha)
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return FALSE;
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if (!RadeonGetDestFormat(pDstPicture, &tmp1))
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return FALSE;
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@ -293,6 +296,8 @@ R100PrepareComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture,
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is_transform[1] = FALSE;
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}
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ENTER_DRAW(pDst);
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RadeonSwitchTo3D(atis);
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BEGIN_DMA(12);
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@ -357,6 +362,8 @@ R100PrepareComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture,
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OUT_REG(RADEON_REG_RB3D_BLENDCNTL, blendcntl);
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END_DMA();
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LEAVE_DRAW(pDst);
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return TRUE;
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}
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@ -621,6 +628,8 @@ RadeonComposite(int srcX, int srcY, int maskX, int maskY, int dstX, int dstY,
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RING_LOCALS;
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PictVector v;
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ENTER_DRAW(0);
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/*ErrorF("RadeonComposite (%d,%d) (%d,%d) (%d,%d) (%d,%d)\n",
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srcX, srcY, maskX, maskY,dstX, dstY, w, h);*/
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@ -683,12 +692,16 @@ RadeonComposite(int srcX, int srcY, int maskX, int maskY, int dstX, int dstY,
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VTX_OUT(dstX + w, dstY + h, srcXend, srcYend, maskXend, maskYend);
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VTX_OUT(dstX + w, dstY, srcXend, srcY, maskXend, maskY);
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LEAVE_DRAW(0);
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END_DMA();
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}
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void
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RadeonDoneComposite(void)
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{
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ENTER_DRAW(0);
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LEAVE_DRAW(0);
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}
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Bool
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