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Make R200 PDMA work -- primary queue sizes are now 9 bits, not 8.

This commit is contained in:
Eric Anholt 2005-01-20 01:09:48 +00:00
parent 9bd876768b
commit 7775506534
2 changed files with 25 additions and 5 deletions
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22
hw/kdrive/ati/ati_dma.c
View File

@ -271,6 +271,10 @@ ATIGetAvailPrimary(ATIScreenInfo *atis)
int csq_stat, diff; int csq_stat, diff;
csq_stat = MMIO_IN32(mmio, RADEON_REG_CP_CSQ_STAT); csq_stat = MMIO_IN32(mmio, RADEON_REG_CP_CSQ_STAT);
if (atic->is_r200)
diff = ((csq_stat & R200_CSQ_WPTR_PRIMARY_MASK) >> 9) -
(csq_stat & R200_CSQ_RPTR_PRIMARY_MASK);
else
diff = ((csq_stat & RADEON_CSQ_WPTR_PRIMARY_MASK) >> 8) - diff = ((csq_stat & RADEON_CSQ_WPTR_PRIMARY_MASK) >> 8) -
(csq_stat & RADEON_CSQ_RPTR_PRIMARY_MASK); (csq_stat & RADEON_CSQ_RPTR_PRIMARY_MASK);
@ -762,13 +766,19 @@ ATIPseudoDMAInit(ScreenPtr pScreen)
ATICardInfo(pScreenPriv); ATICardInfo(pScreenPriv);
char *mmio = atic->reg_base; char *mmio = atic->reg_base;
if (atic->is_r200 || atic->is_r300) if (atic->is_r300)
return FALSE; return FALSE;
ATIUploadMicrocode(atis); ATIUploadMicrocode(atis);
ATIEngineReset(atis); ATIEngineReset(atis);
if (atic->is_radeon) { if (atic->is_r200) {
MMIO_OUT32(mmio, RADEON_REG_CP_CSQ_CNTL,
RADEON_CSQ_PRIPIO_INDDIS);
atis->cce_pri_size = MMIO_IN32(mmio, RADEON_REG_CP_CSQ_CNTL) &
R200_CSQ_CNT_PRIMARY_MASK;
MMIO_OUT32(mmio, RADEON_REG_ME_CNTL, RADEON_ME_MODE_FREE_RUN);
} if (atic->is_radeon) {
MMIO_OUT32(mmio, RADEON_REG_CP_CSQ_CNTL, MMIO_OUT32(mmio, RADEON_REG_CP_CSQ_CNTL,
RADEON_CSQ_PRIPIO_INDDIS); RADEON_CSQ_PRIPIO_INDDIS);
atis->cce_pri_size = MMIO_IN32(mmio, RADEON_REG_CP_CSQ_CNTL) & atis->cce_pri_size = MMIO_IN32(mmio, RADEON_REG_CP_CSQ_CNTL) &
@ -863,7 +873,13 @@ ATIDMAInit(ScreenPtr pScreen, Bool use_agp)
MMIO_OUT32(mmio, ATI_REG_CCE_RPTR, atis->ring_read); MMIO_OUT32(mmio, ATI_REG_CCE_RPTR, atis->ring_read);
MMIO_OUT32(mmio, ATI_REG_CCE_RPTR_ADDR, 0 /* XXX? */); MMIO_OUT32(mmio, ATI_REG_CCE_RPTR_ADDR, 0 /* XXX? */);
if (atic->is_radeon) { if (atic->is_r200) {
MMIO_OUT32(mmio, RADEON_REG_CP_CSQ_CNTL,
RADEON_CSQ_PRIBM_INDBM);
atis->cce_pri_size = MMIO_IN32(mmio, RADEON_REG_CP_CSQ_CNTL) &
R200_CSQ_CNT_PRIMARY_MASK;
MMIO_OUT32(mmio, RADEON_REG_ME_CNTL, RADEON_ME_MODE_FREE_RUN);
} else if (atic->is_radeon) {
MMIO_OUT32(mmio, RADEON_REG_CP_CSQ_CNTL, MMIO_OUT32(mmio, RADEON_REG_CP_CSQ_CNTL,
RADEON_CSQ_PRIBM_INDBM); RADEON_CSQ_PRIBM_INDBM);
atis->cce_pri_size = MMIO_IN32(mmio, RADEON_REG_CP_CSQ_CNTL) & atis->cce_pri_size = MMIO_IN32(mmio, RADEON_REG_CP_CSQ_CNTL) &

4
hw/kdrive/ati/ati_reg.h
View File

@ -244,6 +244,8 @@
#define RADEON_REG_CP_CSQ_CNTL 0x0740 #define RADEON_REG_CP_CSQ_CNTL 0x0740
# define RADEON_CSQ_CNT_PRIMARY_MASK 0x000000ff # define RADEON_CSQ_CNT_PRIMARY_MASK 0x000000ff
# define RADEON_CSQ_CNT_INDIRECT_MASK 0x0000ff00 # define RADEON_CSQ_CNT_INDIRECT_MASK 0x0000ff00
# define R200_CSQ_CNT_PRIMARY_MASK 0x000001ff
# define R200_CSQ_CNT_INDIRECT_MASK 0x0003fe00
# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) # define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
@ -274,6 +276,8 @@
# define RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8) # define RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8)
# define RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16) # define RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16)
# define RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24) # define RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24)
# define R200_CSQ_RPTR_PRIMARY_MASK (0x1ff << 0)
# define R200_CSQ_WPTR_PRIMARY_MASK (0x1ff << 9)
#define R128_REG_PM4_MICRO_CNTL 0x07fc #define R128_REG_PM4_MICRO_CNTL 0x07fc
# define R128_PM4_MICRO_FREERUN (1 << 30) # define R128_PM4_MICRO_FREERUN (1 << 30)