diff --git a/GL/glx/Makefile.am b/GL/glx/Makefile.am index 4e21e5012..44d9cf9e4 100644 --- a/GL/glx/Makefile.am +++ b/GL/glx/Makefile.am @@ -31,7 +31,9 @@ INCLUDES = \ nodist_libglx_la_SOURCES = indirect_size.h libglxdri_la_SOURCES = \ - glxdri.c + glxdri.c \ + extension_string.c \ + extension_string.h libglx_la_SOURCES = \ g_disptab.h \ @@ -54,12 +56,14 @@ libglx_la_SOURCES = \ indirect_dispatch.c \ indirect_dispatch.h \ indirect_dispatch_swap.c \ + indirect_program.c \ indirect_reqsize.c \ indirect_reqsize.h \ indirect_size_get.c \ indirect_size_get.h \ indirect_table.c \ indirect_table.h \ + indirect_texture_compression.c \ indirect_util.c \ indirect_util.h \ render2.c \ @@ -73,5 +77,6 @@ libglx_la_SOURCES = \ singlepixswap.c \ singlesize.c \ singlesize.h \ + swap_interval.c \ unpack.h \ xfont.c diff --git a/GL/glx/extension_string.c b/GL/glx/extension_string.c new file mode 100644 index 000000000..a4b202af3 --- /dev/null +++ b/GL/glx/extension_string.c @@ -0,0 +1,165 @@ +/* + * (C) Copyright IBM Corporation 2002-2006 + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * \file extension_string.c + * Routines to manage the GLX extension string and GLX version for AIGLX + * drivers. This code is loosely based on src/glx/x11/glxextensions.c from + * Mesa. + * + * \author Ian Romanick + */ + +#include +#include "extension_string.h" + +#define SET_BIT(m,b) (m[ (b) / 8 ] |= (1U << ((b) % 8))) +#define CLR_BIT(m,b) (m[ (b) / 8 ] &= ~(1U << ((b) % 8))) +#define IS_SET(m,b) ((m[ (b) / 8 ] & (1U << ((b) % 8))) != 0) +#define CONCAT(a,b) a ## b +#define GLX(n) "GLX_" # n, 4 + sizeof( # n ) - 1, CONCAT(n,_bit) +#define VER(a,b) a, b +#define Y 1 +#define N 0 +#define EXT_ENABLED(bit,supported) (IS_SET(supported, bit)) + +struct extension_info { + const char * const name; + unsigned name_len; + + unsigned char bit; + + /** + * This is the lowest version of GLX that "requires" this extension. + * For example, GLX 1.3 requires SGIX_fbconfig, SGIX_pbuffer, and + * SGI_make_current_read. If the extension is not required by any known + * version of GLX, use 0, 0. + */ + unsigned char version_major; + unsigned char version_minor; + + /** + * Is driver support forced by the ABI? + */ + unsigned char driver_support; +}; + +static const struct extension_info known_glx_extensions[] = { +/* GLX_ARB_get_proc_address is implemented on the client. */ + { GLX(ARB_multisample), VER(1,4), Y, }, + + { GLX(EXT_import_context), VER(0,0), Y, }, + { GLX(EXT_texture_from_pixmap), VER(0,0), Y, }, + { GLX(EXT_visual_info), VER(0,0), Y, }, + { GLX(EXT_visual_rating), VER(0,0), Y, }, + + { GLX(MESA_copy_sub_buffer), VER(0,0), N, }, + { GLX(OML_swap_method), VER(0,0), Y, }, + { GLX(SGI_make_current_read), VER(1,3), N, }, + { GLX(SGI_swap_control), VER(0,0), N, }, + { GLX(SGIS_multisample), VER(0,0), Y, }, + { GLX(SGIX_fbconfig), VER(1,3), Y, }, + { GLX(SGIX_pbuffer), VER(1,3), N, }, + { GLX(SGIX_visual_select_group), VER(0,0), Y, }, + { NULL } +}; + + +/** + * Create a GLX extension string for a set of enable bits. + * + * Creates a GLX extension string for the set of bit in \c enable_bits. This + * string is then stored in \c buffer if buffer is not \c NULL. This allows + * two-pass operation. On the first pass the caller passes \c NULL for + * \c buffer, and the function determines how much space is required to store + * the extension string. The caller allocates the buffer and calls the + * function again. + * + * \param enable_bits Bits representing the enabled extensions. + * \param buffer Buffer to store the extension string. May be \c NULL. + * + * \return + * The number of characters in \c buffer that were written to. If \c buffer + * is \c NULL, this is the size of buffer that must be allocated by the + * caller. + */ +int +__glXGetExtensionString(const unsigned char *enable_bits, char *buffer) +{ + unsigned i; + int length = 0; + + + for (i = 0; known_glx_extensions[i].name != NULL; i++) { + const unsigned bit = known_glx_extensions[i].bit; + const size_t len = known_glx_extensions[i].name_len; + + if (EXT_ENABLED(bit, enable_bits)) { + if (buffer != NULL) { + (void) memcpy(& buffer[length], known_glx_extensions[i].name, + len); + + buffer[length + len + 0] = ' '; + buffer[length + len + 1] = '\0'; + } + + length += len + 1; + } + } + + return length + 1; +} + + +void +__glXEnableExtension(unsigned char *enable_bits, const char *ext) +{ + const size_t ext_name_len = strlen(ext); + unsigned i; + + + for (i = 0; known_glx_extensions[i].name != NULL; i++) { + if ((ext_name_len == known_glx_extensions[i].name_len) + && (memcmp(ext, known_glx_extensions[i].name, ext_name_len) == 0)) { + SET_BIT(enable_bits, known_glx_extensions[i].bit); + break; + } + } +} + + +void +__glXInitExtensionEnableBits(unsigned char *enable_bits) +{ + unsigned i; + + + (void) memset(enable_bits, 0, __GLX_EXT_BYTES); + + for (i = 0; known_glx_extensions[i].name != NULL; i++) { + if (known_glx_extensions[i].driver_support) { + SET_BIT(enable_bits, known_glx_extensions[i].bit); + } + } +} diff --git a/GL/glx/extension_string.h b/GL/glx/extension_string.h new file mode 100644 index 000000000..98e91bc18 --- /dev/null +++ b/GL/glx/extension_string.h @@ -0,0 +1,63 @@ +/* + * (C) Copyright IBM Corporation 2002-2006 + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * \file extension_string.h + * Routines to manage the GLX extension string and GLX version for AIGLX + * drivers. This code is loosely based on src/glx/x11/glxextensions.c from + * Mesa. + * + * \author Ian Romanick + */ + +#ifndef GLX_EXTENSION_STRING_H +#define GLX_EXTENSION_STRING_H + +enum { +/* GLX_ARB_get_proc_address is implemented on the client. */ + ARB_multisample_bit = 0, + EXT_import_context_bit, + EXT_texture_from_pixmap_bit, + EXT_visual_info_bit, + EXT_visual_rating_bit, + MESA_copy_sub_buffer_bit, + OML_swap_method_bit, + SGI_make_current_read_bit, + SGI_swap_control_bit, + SGI_video_sync_bit, + SGIS_multisample_bit, + SGIX_fbconfig_bit, + SGIX_pbuffer_bit, + SGIX_visual_select_group_bit, + __NUM_GLX_EXTS, +}; + +#define __GLX_EXT_BYTES ((__NUM_GLX_EXTS + 7) / 8) + +extern int __glXGetExtensionString(const unsigned char *enable_bits, + char *buffer); +extern void __glXEnableExtension(unsigned char *enable_bits, const char *ext); +extern void __glXInitExtensionEnableBits(unsigned char *enable_bits); + +#endif /* GLX_EXTENSION_STRING_H */ diff --git a/GL/glx/glxcmds.c b/GL/glx/glxcmds.c index 3092f853f..ccdf3fa00 100644 --- a/GL/glx/glxcmds.c +++ b/GL/glx/glxcmds.c @@ -2274,9 +2274,6 @@ int __glXDisp_VendorPrivate(__GLXclientState *cl, GLbyte *pc) return Success; } - /* - ** This sample implemention does not support any private requests. - */ cl->client->errorValue = req->vendorCode; return __glXError(GLXUnsupportedPrivateRequest); } diff --git a/GL/glx/glxdri.c b/GL/glx/glxdri.c index fa7f1ddc8..170662c7e 100644 --- a/GL/glx/glxdri.c +++ b/GL/glx/glxdri.c @@ -57,6 +57,7 @@ #include "glapi.h" #include "glthread.h" #include "dispatch.h" +#include "extension_string.h" #define STRINGIFY(macro_or_string) STRINGIFY_ARG (macro_or_string) @@ -71,6 +72,11 @@ struct __GLXDRIscreen { __DRIscreen driScreen; void *driver; + + xf86EnterVTProc *enterVT; + xf86LeaveVTProc *leaveVT; + + unsigned char glx_enable_bits[__GLX_EXT_BYTES]; }; struct __GLXDRIcontext { @@ -145,6 +151,22 @@ __glXDRIenterServer(void) DRIWakeupHandler(NULL, 0, NULL); } +/** + * \bug + * We're jumping through hoops here to get the DRIdrawable which the DRI + * driver tries to keep to it self... cf. FIXME in \c createDrawable. + */ +static void +__glXDRIdrawableFoo(__GLXDRIdrawable *draw) +{ + __GLXDRIscreen * const screen = + (__GLXDRIscreen *) __glXgetActiveScreen(draw->base.pDraw->pScreen->myNum); + + draw->driDrawable = (*screen->driScreen.getDrawable)(NULL, + draw->base.drawId, + screen->driScreen.private); +} + static void __glXDRIdrawableDestroy(__GLXdrawable *private) { @@ -169,16 +191,8 @@ static GLboolean __glXDRIdrawableSwapBuffers(__GLXdrawable *basePrivate) { __GLXDRIdrawable *private = (__GLXDRIdrawable *) basePrivate; - __GLXDRIscreen *screen; - /* FIXME: We're jumping through hoops here to get the DRIdrawable - * which the dri driver tries to keep to it self... cf. FIXME in - * createDrawable. */ - - screen = (__GLXDRIscreen *) __glXgetActiveScreen(private->base.pDraw->pScreen->myNum); - private->driDrawable = (screen->driScreen.getDrawable)(NULL, - private->base.drawId, - screen->driScreen.private); + __glXDRIdrawableFoo(private); (*private->driDrawable->swapBuffers)(NULL, private->driDrawable->private); @@ -186,21 +200,26 @@ __glXDRIdrawableSwapBuffers(__GLXdrawable *basePrivate) return TRUE; } + +static int +__glXDRIdrawableSwapInterval(__GLXdrawable *baseDrawable, int interval) +{ + __GLXDRIdrawable *draw = (__GLXDRIdrawable *) baseDrawable; + + __glXDRIdrawableFoo(draw); + + draw->driDrawable->swap_interval = interval; + return 0; +} + + static void __glXDRIdrawableCopySubBuffer(__GLXdrawable *basePrivate, int x, int y, int w, int h) { __GLXDRIdrawable *private = (__GLXDRIdrawable *) basePrivate; - __GLXDRIscreen *screen; - /* FIXME: We're jumping through hoops here to get the DRIdrawable - * which the dri driver tries to keep to it self... cf. FIXME in - * createDrawable. */ - - screen = (__GLXDRIscreen *) __glXgetActiveScreen(private->base.pDraw->pScreen->myNum); - private->driDrawable = (screen->driScreen.getDrawable)(NULL, - private->base.drawId, - screen->driScreen.private); + __glXDRIdrawableFoo(private); (*private->driDrawable->copySubBuffer)(NULL, private->driDrawable->private, @@ -340,7 +359,12 @@ __glXDRIbindTexImage(__GLXcontext *baseContext, if (pixmap->drawable.depth >= 24) { bpp = 4; format = GL_BGRA; - type = GL_UNSIGNED_BYTE; + type = +#if X_BYTE_ORDER == X_LITTLE_ENDIAN + GL_UNSIGNED_BYTE; +#else + GL_UNSIGNED_INT_8_8_8_8_REV; +#endif } else { bpp = 2; format = GL_RGB; @@ -586,15 +610,27 @@ filter_modes(__GLcontextModes **server_modes, } +static void +enable_glx_extension(void *psc, const char *ext_name) +{ + __GLXDRIscreen * const screen = (__GLXDRIscreen *) psc; + + __glXEnableExtension(screen->glx_enable_bits, ext_name); +} + + static __DRIfuncPtr getProcAddress(const char *proc_name) { + if (strcmp(proc_name, "glxEnableExtension") == 0) { + return (__DRIfuncPtr) enable_glx_extension; + } + return NULL; } static __DRIscreen *findScreen(__DRInativeDisplay *dpy, int scrn) { - __GLXDRIscreen *screen = - (__GLXDRIscreen *) __glXgetActiveScreen(scrn); + __GLXDRIscreen *screen = (__GLXDRIscreen *) __glXgetActiveScreen(scrn); return &screen->driScreen; } @@ -788,6 +824,30 @@ static const __DRIinterfaceMethods interface_methods = { static const char dri_driver_path[] = DRI_DRIVER_PATH; +static Bool +glxDRIEnterVT (int index, int flags) +{ + __GLXDRIscreen *screen = (__GLXDRIscreen *) __glXgetActiveScreen(index); + + LogMessage(X_INFO, "AIGLX: Resuming AIGLX clients after VT switch\n"); + + glxResumeClients(); + + return (*screen->enterVT) (index, flags); +} + +static void +glxDRILeaveVT (int index, int flags) +{ + __GLXDRIscreen *screen = (__GLXDRIscreen *) __glXgetActiveScreen(index); + + LogMessage(X_INFO, "AIGLX: Suspending AIGLX clients for VT switch\n"); + + glxSuspendClients(); + + return (*screen->leaveVT) (index, flags); +} + static __GLXscreen * __glXDRIscreenProbe(ScreenPtr pScreen) { @@ -812,6 +872,8 @@ __glXDRIscreenProbe(ScreenPtr pScreen) void *dev_priv = NULL; char filename[128]; Bool isCapable; + size_t buffer_size; + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; if (!xf86LoaderCheckSymbol("DRIQueryDirectRenderingCapable")) { LogMessage(X_ERROR, "AIGLX: DRI module not loaded\n"); @@ -832,8 +894,13 @@ __glXDRIscreenProbe(ScreenPtr pScreen) screen->base.destroy = __glXDRIscreenDestroy; screen->base.createContext = __glXDRIscreenCreateContext; screen->base.createDrawable = __glXDRIscreenCreateDrawable; + screen->base.swapInterval = __glXDRIdrawableSwapInterval; screen->base.pScreen = pScreen; + __glXInitExtensionEnableBits(screen->glx_enable_bits); + screen->driScreen.screenConfigs = screen; + + /* DRI protocol version. */ dri_version.major = XF86DRI_MAJOR_VERSION; dri_version.minor = XF86DRI_MINOR_VERSION; @@ -977,11 +1044,28 @@ __glXDRIscreenProbe(ScreenPtr pScreen) __glXScreenInit(&screen->base, pScreen); + buffer_size = __glXGetExtensionString(screen->glx_enable_bits, NULL); + if (buffer_size > 0) { + if (screen->base.GLXextensions != NULL) { + xfree(screen->base.GLXextensions); + } + + screen->base.GLXextensions = xnfalloc(buffer_size); + (void) __glXGetExtensionString(screen->glx_enable_bits, + screen->base.GLXextensions); + } + + filter_modes(&screen->base.modes, driver_modes); _gl_context_modes_destroy(driver_modes); __glXsetEnterLeaveServerFuncs(__glXDRIenterServer, __glXDRIleaveServer); + screen->enterVT = pScrn->EnterVT; + pScrn->EnterVT = glxDRIEnterVT; + screen->leaveVT = pScrn->LeaveVT; + pScrn->LeaveVT = glxDRILeaveVT; + LogMessage(X_INFO, "AIGLX: Loaded and initialized %s\n", filename); diff --git a/GL/glx/glxext.c b/GL/glx/glxext.c index 5600d175d..11fb7fcaf 100644 --- a/GL/glx/glxext.c +++ b/GL/glx/glxext.c @@ -59,10 +59,7 @@ xGLXSingleReply __glXReply; ** A set of state for each client. The 0th one is unused because client ** indices start at 1, not 0. */ -__GLXclientState *__glXClients[MAXCLIENTS+1]; - - -static Bool inDispatch; +static __GLXclientState *__glXClients[MAXCLIENTS + 1]; /* ** Forward declarations. @@ -219,6 +216,10 @@ static Bool DrawableGone(__GLXdrawable *glxPriv, XID xid) return True; } +static __GLXcontext *glxPendingDestroyContexts; +static int glxServerLeaveCount; +static int glxBlockClients; + /* ** Free a context. */ @@ -236,13 +237,14 @@ GLboolean __glXFreeContext(__GLXcontext *cx) * __glXDispatch() or as a callback from the resource manager. In * the latter case we need to lift the DRI lock manually. */ - if (!inDispatch) - __glXleaveServer(); - - cx->destroy(cx); - - if (!inDispatch) - __glXenterServer(); + if (glxBlockClients) { + __glXleaveServer(); + cx->destroy(cx); + __glXenterServer(); + } else { + cx->next = glxPendingDestroyContexts; + glxPendingDestroyContexts = cx; + } return GL_TRUE; } @@ -338,7 +340,7 @@ void GlxExtensionInit(void) /* ** Initialize table of client state. There is never a client 0. */ - for (i=1; i <= MAXCLIENTS; i++) { + for (i = 1; i <= MAXCLIENTS; i++) { __glXClients[i] = 0; } @@ -409,11 +411,43 @@ __GLXcontext *__glXForceCurrent(__GLXclientState *cl, GLXContextTag tag, /************************************************************************/ -/* -** Top level dispatcher; all commands are executed from here down. -*/ +void glxSuspendClients(void) +{ + int i; -/* I cried when I wrote this. Damn you XAA! */ + for (i = 1; i <= MAXCLIENTS; i++) { + if (__glXClients[i] == NULL || !__glXClients[i]->inUse) + continue; + + IgnoreClient(__glXClients[i]->client); + } + + glxBlockClients = TRUE; +} + +void glxResumeClients(void) +{ + __GLXcontext *cx, *next; + int i; + + glxBlockClients = FALSE; + + for (i = 1; i <= MAXCLIENTS; i++) { + if (__glXClients[i] == NULL || !__glXClients[i]->inUse) + continue; + + AttendClient(__glXClients[i]->client); + } + + __glXleaveServer(); + for (cx = glxPendingDestroyContexts; cx != NULL; cx = next) { + next = cx->next; + + cx->destroy(cx); + } + glxPendingDestroyContexts = NULL; + __glXenterServer(); +} static void __glXnopEnterServer(void) @@ -438,14 +472,19 @@ void __glXsetEnterLeaveServerFuncs(void (*enter)(void), void __glXenterServer(void) { - (*__glXenterServerFunc)(); + glxServerLeaveCount--; + + if (glxServerLeaveCount == 0) + (*__glXenterServerFunc)(); } void __glXleaveServer(void) { - (*__glXleaveServerFunc)(); -} + if (glxServerLeaveCount == 0) + (*__glXleaveServerFunc)(); + glxServerLeaveCount++; +} /* ** Top level dispatcher; all commands are executed from here down. @@ -491,6 +530,15 @@ static int __glXDispatch(ClientPtr client) return __glXError(GLXBadLargeRequest); } + /* If we're currently blocking GLX clients, just put this guy to + * sleep, reset the request and return. */ + if (glxBlockClients) { + ResetCurrentRequest(client); + client->sequence--; + IgnoreClient(client); + return(client->noClientException); + } + /* ** Use the opcode to index into the procedure table. */ @@ -500,12 +548,8 @@ static int __glXDispatch(ClientPtr client) if (proc != NULL) { __glXleaveServer(); - inDispatch = True; - retval = (*proc)(cl, (GLbyte *) stuff); - inDispatch = False; - __glXenterServer(); } else { @@ -514,9 +558,3 @@ static int __glXDispatch(ClientPtr client) return retval; } - -void __glXNoSuchRenderOpcode(GLbyte *pc) -{ - return; -} - diff --git a/GL/glx/glxext.h b/GL/glx/glxext.h index c494de4a0..edd66a8f0 100644 --- a/GL/glx/glxext.h +++ b/GL/glx/glxext.h @@ -66,15 +66,11 @@ typedef struct { extern GLboolean __glXFreeContext(__GLXcontext *glxc); extern void __glXFlushContextCache(void); -extern void __glXNoSuchRenderOpcode(GLbyte*); extern void __glXErrorCallBack(__GLinterface *gc, GLenum code); extern void __glXClearErrorOccured(void); extern GLboolean __glXErrorOccured(void); extern void __glXResetLargeCommandStatus(__GLXclientState*); -extern int __glXQueryContextInfoEXT(__GLXclientState *cl, GLbyte *pc); -extern int __glXSwapQueryContextInfoEXT(__GLXclientState *cl, GLbyte *pc); - extern int DoMakeCurrent( __GLXclientState *cl, GLXDrawable drawId, GLXDrawable readId, GLXContextID contextId, GLXContextTag tag ); extern int DoGetVisualConfigs(__GLXclientState *cl, unsigned screen, @@ -94,8 +90,6 @@ extern int DoRenderLarge(__GLXclientState *cl, GLbyte *pc, int do_swap); extern void GlxExtensionInit(void); -extern Bool __glXCoreType(void); - extern const char GLServerVersion[]; extern int DoGetString(__GLXclientState *cl, GLbyte *pc, GLboolean need_swap); diff --git a/GL/glx/glxscreens.c b/GL/glx/glxscreens.c index 763e55ed7..43447a4e4 100644 --- a/GL/glx/glxscreens.c +++ b/GL/glx/glxscreens.c @@ -45,10 +45,12 @@ #include "glxutil.h" #include "glxext.h" -const char GLServerVersion[] = "1.2"; +const char GLServerVersion[] = "1.4"; static const char GLServerExtensions[] = "GL_ARB_depth_texture " "GL_ARB_draw_buffers " + "GL_ARB_fragment_program " + "GL_ARB_fragment_program_shadow " "GL_ARB_imaging " "GL_ARB_multisample " "GL_ARB_multitexture " @@ -58,6 +60,7 @@ static const char GLServerExtensions[] = "GL_ARB_shadow " "GL_ARB_shadow_ambient " "GL_ARB_texture_border_clamp " + "GL_ARB_texture_compression " "GL_ARB_texture_cube_map " "GL_ARB_texture_env_add " "GL_ARB_texture_env_combine " @@ -66,10 +69,12 @@ static const char GLServerExtensions[] = "GL_ARB_texture_mirrored_repeat " "GL_ARB_texture_non_power_of_two " "GL_ARB_transpose_matrix " + "GL_ARB_vertex_program " "GL_ARB_window_pos " "GL_EXT_abgr " "GL_EXT_bgra " "GL_EXT_blend_color " + "GL_EXT_blend_equation_separate " "GL_EXT_blend_func_separate " "GL_EXT_blend_logic_op " "GL_EXT_blend_minmax " @@ -94,16 +99,20 @@ static const char GLServerExtensions[] = "GL_EXT_subtexture " "GL_EXT_texture " "GL_EXT_texture3D " + "GL_EXT_texture_compression_dxt1 " + "GL_EXT_texture_compression_s3tc " "GL_EXT_texture_edge_clamp " "GL_EXT_texture_env_add " "GL_EXT_texture_env_combine " "GL_EXT_texture_env_dot3 " + "GL_EXT_texture_filter_ansiotropic " "GL_EXT_texture_lod " "GL_EXT_texture_lod_bias " "GL_EXT_texture_mirror_clamp " "GL_EXT_texture_object " "GL_EXT_texture_rectangle " "GL_EXT_vertex_array " + "GL_3DFX_texture_compression_FXT1 " "GL_APPLE_packed_pixels " "GL_ATI_draw_buffers " "GL_ATI_texture_env_combine3 " @@ -116,13 +125,23 @@ static const char GLServerExtensions[] = "GL_NV_blend_square " "GL_NV_depth_clamp " "GL_NV_fog_distance " + "GL_NV_fragment_program " + "GL_NV_fragment_program_option " + "GL_NV_fragment_program2 " "GL_NV_light_max_exponent " "GL_NV_multisample_filter_hint " "GL_NV_point_sprite " "GL_NV_texgen_reflection " + "GL_NV_texture_compression_vtc " "GL_NV_texture_env_combine4 " "GL_NV_texture_expand_normal " "GL_NV_texture_rectangle " + "GL_NV_vertex_program " + "GL_NV_vertex_program1_1 " + "GL_NV_vertex_program2 " + "GL_NV_vertex_program2_option " + "GL_NV_vertex_program3 " + "GL_OES_compressed_paletted_texture " "GL_SGI_color_matrix " "GL_SGI_color_table " "GL_SGIS_generate_mipmap " diff --git a/GL/glx/glxscreens.h b/GL/glx/glxscreens.h index 8beec17ec..a7700f649 100644 --- a/GL/glx/glxscreens.h +++ b/GL/glx/glxscreens.h @@ -62,6 +62,8 @@ struct __GLXscreen { DrawablePtr pDraw, XID drawId, __GLcontextModes *modes); + int (*swapInterval) (__GLXdrawable *drawable, + int interval); ScreenPtr pScreen; diff --git a/GL/glx/glxserver.h b/GL/glx/glxserver.h index a79520e4a..49cad7328 100644 --- a/GL/glx/glxserver.h +++ b/GL/glx/glxserver.h @@ -136,6 +136,9 @@ void __glXsetEnterLeaveServerFuncs(void (*enter)(void), void __glXenterServer(void); void __glXleaveServer(void); +void glxSuspendClients(void); +void glxResumeClients(void); + /* ** State kept per client. */ @@ -176,8 +179,6 @@ struct __GLXclientStateRec { char *GLClientextensions; }; -extern __GLXclientState *__glXClients[]; - /************************************************************************/ /* @@ -191,7 +192,6 @@ typedef int (*__GLXdispatchVendorPrivProcPtr)(__GLXclientState *, GLbyte *); * Dispatch for GLX commands. */ typedef int (*__GLXprocPtr)(__GLXclientState *, char *pc); -extern __GLXprocPtr __glXProcTable[]; /* * Tables for computing the size of each rendering command. @@ -252,6 +252,4 @@ extern int __glXImageSize(GLenum format, GLenum type, GLint imageHeight, GLint rowLength, GLint skipImages, GLint skipRows, GLint alignment); -extern int __glXDrawArraysReqSize(const GLbyte *pc, Bool swap); - #endif /* !__GLX_server_h__ */ diff --git a/GL/glx/glxutil.h b/GL/glx/glxutil.h index c30a1f9cd..1937ef2cf 100644 --- a/GL/glx/glxutil.h +++ b/GL/glx/glxutil.h @@ -40,36 +40,18 @@ ** */ -extern void __glXNop(void); - /* relate contexts with drawables */ extern void __glXAssociateContext(__GLXcontext *glxc); extern void __glXDeassociateContext(__GLXcontext *glxc); -/* drawable operation */ -extern void __glXGetDrawableSize(__GLdrawablePrivate *glPriv, - GLint *x, GLint *y, - GLuint *width, GLuint *height); -extern GLboolean __glXResizeDrawable(__GLdrawablePrivate *glPriv); -extern GLboolean __glXResizeDrawableBuffers(__GLXdrawable *glxPriv); - /* drawable management */ extern void __glXRefDrawable(__GLXdrawable *glxPriv); extern void __glXUnrefDrawable(__GLXdrawable *glxPriv); -extern __GLXdrawable *__glXCreateDrawable(__GLXscreen *screen, - DrawablePtr pDraw, XID drawId, - __GLcontextModes *modes); extern GLboolean __glXDrawableInit(__GLXdrawable *drawable, __GLXscreen *screen, DrawablePtr pDraw, XID drawID, __GLcontextModes *modes); -extern GLboolean __glXDestroyDrawable(__GLXdrawable *glxPriv); -extern __GLXdrawable *__glXFindDrawable(XID glxpixmapId); -extern __GLXdrawable *__glXGetDrawable(__GLXcontext *ctx, - DrawablePtr pDraw, - XID glxpixmapId); -extern void __glXCacheDrawableSize(__GLXdrawable *glxPriv); /* context helper routines */ extern __GLXcontext *__glXLookupContextByTag(__GLXclientState*, GLXContextTag); @@ -79,4 +61,3 @@ extern void *__glXglDDXScreenInfo(void); extern void *__glXglDDXExtensionInfo(void); #endif /* _glxcmds_h_ */ - diff --git a/GL/glx/indirect_dispatch.c b/GL/glx/indirect_dispatch.c index 9c2b7b12b..d86dedfd5 100644 --- a/GL/glx/indirect_dispatch.c +++ b/GL/glx/indirect_dispatch.c @@ -2756,6 +2756,31 @@ int __glXDisp_AreTexturesResident(__GLXclientState *cl, GLbyte *pc) return error; } +int __glXDisp_AreTexturesResidentEXT(__GLXclientState *cl, GLbyte *pc) +{ + xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; + int error; + __GLXcontext * const cx = __glXForceCurrent(cl, req->contextTag, &error); + + pc += __GLX_VENDPRIV_HDR_SIZE; + if ( cx != NULL ) { + const GLsizei n = *(GLsizei *)(pc + 0); + + GLboolean retval; + GLboolean answerBuffer[200]; + GLboolean * residences = __glXGetAnswerBuffer(cl, n, answerBuffer, sizeof(answerBuffer), 1); + retval = CALL_AreTexturesResident( GET_DISPATCH(), ( + n, + (const GLuint *)(pc + 4), + residences + ) ); + __glXSendReply(cl->client, residences, n, 1, GL_TRUE, retval); + error = Success; + } + + return error; +} + void __glXDisp_CopyTexImage1D(GLbyte * pc) { CALL_CopyTexImage1D( GET_DISPATCH(), ( @@ -2810,6 +2835,26 @@ void __glXDisp_CopyTexSubImage2D(GLbyte * pc) } int __glXDisp_DeleteTextures(__GLXclientState *cl, GLbyte *pc) +{ + xGLXSingleReq * const req = (xGLXSingleReq *) pc; + int error; + __GLXcontext * const cx = __glXForceCurrent(cl, req->contextTag, &error); + + pc += __GLX_SINGLE_HDR_SIZE; + if ( cx != NULL ) { + const GLsizei n = *(GLsizei *)(pc + 0); + + CALL_DeleteTextures( GET_DISPATCH(), ( + n, + (const GLuint *)(pc + 4) + ) ); + error = Success; + } + + return error; +} + +int __glXDisp_DeleteTexturesEXT(__GLXclientState *cl, GLbyte *pc) { xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; int error; @@ -2852,6 +2897,29 @@ int __glXDisp_GenTextures(__GLXclientState *cl, GLbyte *pc) return error; } +int __glXDisp_GenTexturesEXT(__GLXclientState *cl, GLbyte *pc) +{ + xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; + int error; + __GLXcontext * const cx = __glXForceCurrent(cl, req->contextTag, &error); + + pc += __GLX_VENDPRIV_HDR_SIZE; + if ( cx != NULL ) { + const GLsizei n = *(GLsizei *)(pc + 0); + + GLuint answerBuffer[200]; + GLuint * textures = __glXGetAnswerBuffer(cl, n * 4, answerBuffer, sizeof(answerBuffer), 4); + CALL_GenTextures( GET_DISPATCH(), ( + n, + textures + ) ); + __glXSendReply(cl->client, textures, n, 4, GL_TRUE, 0); + error = Success; + } + + return error; +} + int __glXDisp_IsTexture(__GLXclientState *cl, GLbyte *pc) { xGLXSingleReq * const req = (xGLXSingleReq *) pc; @@ -2871,6 +2939,25 @@ int __glXDisp_IsTexture(__GLXclientState *cl, GLbyte *pc) return error; } +int __glXDisp_IsTextureEXT(__GLXclientState *cl, GLbyte *pc) +{ + xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; + int error; + __GLXcontext * const cx = __glXForceCurrent(cl, req->contextTag, &error); + + pc += __GLX_VENDPRIV_HDR_SIZE; + if ( cx != NULL ) { + GLboolean retval; + retval = CALL_IsTexture( GET_DISPATCH(), ( + *(GLuint *)(pc + 0) + ) ); + __glXSendReply(cl->client, dummy_answer, 0, 0, GL_FALSE, retval); + error = Success; + } + + return error; +} + void __glXDisp_PrioritizeTextures(GLbyte * pc) { const GLsizei n = *(GLsizei *)(pc + 0); @@ -3039,6 +3126,35 @@ int __glXDisp_GetColorTableParameterfv(__GLXclientState *cl, GLbyte *pc) return error; } +int __glXDisp_GetColorTableParameterfvSGI(__GLXclientState *cl, GLbyte *pc) +{ + xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; + int error; + __GLXcontext * const cx = __glXForceCurrent(cl, req->contextTag, &error); + + pc += __GLX_VENDPRIV_HDR_SIZE; + if ( cx != NULL ) { + const GLenum pname = *(GLenum *)(pc + 4); + + const GLuint compsize = __glGetColorTableParameterfv_size(pname); + GLfloat answerBuffer[200]; + GLfloat * params = __glXGetAnswerBuffer(cl, compsize * 4, answerBuffer, sizeof(answerBuffer), 4); + + if (params == NULL) return BadAlloc; + __glXClearErrorOccured(); + + CALL_GetColorTableParameterfv( GET_DISPATCH(), ( + *(GLenum *)(pc + 0), + pname, + params + ) ); + __glXSendReply(cl->client, params, compsize, 4, GL_FALSE, 0); + error = Success; + } + + return error; +} + int __glXDisp_GetColorTableParameteriv(__GLXclientState *cl, GLbyte *pc) { xGLXSingleReq * const req = (xGLXSingleReq *) pc; @@ -3068,6 +3184,35 @@ int __glXDisp_GetColorTableParameteriv(__GLXclientState *cl, GLbyte *pc) return error; } +int __glXDisp_GetColorTableParameterivSGI(__GLXclientState *cl, GLbyte *pc) +{ + xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; + int error; + __GLXcontext * const cx = __glXForceCurrent(cl, req->contextTag, &error); + + pc += __GLX_VENDPRIV_HDR_SIZE; + if ( cx != NULL ) { + const GLenum pname = *(GLenum *)(pc + 4); + + const GLuint compsize = __glGetColorTableParameteriv_size(pname); + GLint answerBuffer[200]; + GLint * params = __glXGetAnswerBuffer(cl, compsize * 4, answerBuffer, sizeof(answerBuffer), 4); + + if (params == NULL) return BadAlloc; + __glXClearErrorOccured(); + + CALL_GetColorTableParameteriv( GET_DISPATCH(), ( + *(GLenum *)(pc + 0), + pname, + params + ) ); + __glXSendReply(cl->client, params, compsize, 4, GL_FALSE, 0); + error = Success; + } + + return error; +} + void __glXDisp_ColorSubTable(GLbyte * pc) { const GLvoid * const data = (const GLvoid *) (pc + 40); @@ -3244,6 +3389,35 @@ int __glXDisp_GetConvolutionParameterfv(__GLXclientState *cl, GLbyte *pc) return error; } +int __glXDisp_GetConvolutionParameterfvEXT(__GLXclientState *cl, GLbyte *pc) +{ + xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; + int error; + __GLXcontext * const cx = __glXForceCurrent(cl, req->contextTag, &error); + + pc += __GLX_VENDPRIV_HDR_SIZE; + if ( cx != NULL ) { + const GLenum pname = *(GLenum *)(pc + 4); + + const GLuint compsize = __glGetConvolutionParameterfv_size(pname); + GLfloat answerBuffer[200]; + GLfloat * params = __glXGetAnswerBuffer(cl, compsize * 4, answerBuffer, sizeof(answerBuffer), 4); + + if (params == NULL) return BadAlloc; + __glXClearErrorOccured(); + + CALL_GetConvolutionParameterfv( GET_DISPATCH(), ( + *(GLenum *)(pc + 0), + pname, + params + ) ); + __glXSendReply(cl->client, params, compsize, 4, GL_FALSE, 0); + error = Success; + } + + return error; +} + int __glXDisp_GetConvolutionParameteriv(__GLXclientState *cl, GLbyte *pc) { xGLXSingleReq * const req = (xGLXSingleReq *) pc; @@ -3273,6 +3447,35 @@ int __glXDisp_GetConvolutionParameteriv(__GLXclientState *cl, GLbyte *pc) return error; } +int __glXDisp_GetConvolutionParameterivEXT(__GLXclientState *cl, GLbyte *pc) +{ + xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; + int error; + __GLXcontext * const cx = __glXForceCurrent(cl, req->contextTag, &error); + + pc += __GLX_VENDPRIV_HDR_SIZE; + if ( cx != NULL ) { + const GLenum pname = *(GLenum *)(pc + 4); + + const GLuint compsize = __glGetConvolutionParameteriv_size(pname); + GLint answerBuffer[200]; + GLint * params = __glXGetAnswerBuffer(cl, compsize * 4, answerBuffer, sizeof(answerBuffer), 4); + + if (params == NULL) return BadAlloc; + __glXClearErrorOccured(); + + CALL_GetConvolutionParameteriv( GET_DISPATCH(), ( + *(GLenum *)(pc + 0), + pname, + params + ) ); + __glXSendReply(cl->client, params, compsize, 4, GL_FALSE, 0); + error = Success; + } + + return error; +} + int __glXDisp_GetHistogramParameterfv(__GLXclientState *cl, GLbyte *pc) { xGLXSingleReq * const req = (xGLXSingleReq *) pc; @@ -3302,6 +3505,35 @@ int __glXDisp_GetHistogramParameterfv(__GLXclientState *cl, GLbyte *pc) return error; } +int __glXDisp_GetHistogramParameterfvEXT(__GLXclientState *cl, GLbyte *pc) +{ + xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; + int error; + __GLXcontext * const cx = __glXForceCurrent(cl, req->contextTag, &error); + + pc += __GLX_VENDPRIV_HDR_SIZE; + if ( cx != NULL ) { + const GLenum pname = *(GLenum *)(pc + 4); + + const GLuint compsize = __glGetHistogramParameterfv_size(pname); + GLfloat answerBuffer[200]; + GLfloat * params = __glXGetAnswerBuffer(cl, compsize * 4, answerBuffer, sizeof(answerBuffer), 4); + + if (params == NULL) return BadAlloc; + __glXClearErrorOccured(); + + CALL_GetHistogramParameterfv( GET_DISPATCH(), ( + *(GLenum *)(pc + 0), + pname, + params + ) ); + __glXSendReply(cl->client, params, compsize, 4, GL_FALSE, 0); + error = Success; + } + + return error; +} + int __glXDisp_GetHistogramParameteriv(__GLXclientState *cl, GLbyte *pc) { xGLXSingleReq * const req = (xGLXSingleReq *) pc; @@ -3331,6 +3563,35 @@ int __glXDisp_GetHistogramParameteriv(__GLXclientState *cl, GLbyte *pc) return error; } +int __glXDisp_GetHistogramParameterivEXT(__GLXclientState *cl, GLbyte *pc) +{ + xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; + int error; + __GLXcontext * const cx = __glXForceCurrent(cl, req->contextTag, &error); + + pc += __GLX_VENDPRIV_HDR_SIZE; + if ( cx != NULL ) { + const GLenum pname = *(GLenum *)(pc + 4); + + const GLuint compsize = __glGetHistogramParameteriv_size(pname); + GLint answerBuffer[200]; + GLint * params = __glXGetAnswerBuffer(cl, compsize * 4, answerBuffer, sizeof(answerBuffer), 4); + + if (params == NULL) return BadAlloc; + __glXClearErrorOccured(); + + CALL_GetHistogramParameteriv( GET_DISPATCH(), ( + *(GLenum *)(pc + 0), + pname, + params + ) ); + __glXSendReply(cl->client, params, compsize, 4, GL_FALSE, 0); + error = Success; + } + + return error; +} + int __glXDisp_GetMinmaxParameterfv(__GLXclientState *cl, GLbyte *pc) { xGLXSingleReq * const req = (xGLXSingleReq *) pc; @@ -3360,6 +3621,35 @@ int __glXDisp_GetMinmaxParameterfv(__GLXclientState *cl, GLbyte *pc) return error; } +int __glXDisp_GetMinmaxParameterfvEXT(__GLXclientState *cl, GLbyte *pc) +{ + xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; + int error; + __GLXcontext * const cx = __glXForceCurrent(cl, req->contextTag, &error); + + pc += __GLX_VENDPRIV_HDR_SIZE; + if ( cx != NULL ) { + const GLenum pname = *(GLenum *)(pc + 4); + + const GLuint compsize = __glGetMinmaxParameterfv_size(pname); + GLfloat answerBuffer[200]; + GLfloat * params = __glXGetAnswerBuffer(cl, compsize * 4, answerBuffer, sizeof(answerBuffer), 4); + + if (params == NULL) return BadAlloc; + __glXClearErrorOccured(); + + CALL_GetMinmaxParameterfv( GET_DISPATCH(), ( + *(GLenum *)(pc + 0), + pname, + params + ) ); + __glXSendReply(cl->client, params, compsize, 4, GL_FALSE, 0); + error = Success; + } + + return error; +} + int __glXDisp_GetMinmaxParameteriv(__GLXclientState *cl, GLbyte *pc) { xGLXSingleReq * const req = (xGLXSingleReq *) pc; @@ -3389,6 +3679,35 @@ int __glXDisp_GetMinmaxParameteriv(__GLXclientState *cl, GLbyte *pc) return error; } +int __glXDisp_GetMinmaxParameterivEXT(__GLXclientState *cl, GLbyte *pc) +{ + xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; + int error; + __GLXcontext * const cx = __glXForceCurrent(cl, req->contextTag, &error); + + pc += __GLX_VENDPRIV_HDR_SIZE; + if ( cx != NULL ) { + const GLenum pname = *(GLenum *)(pc + 4); + + const GLuint compsize = __glGetMinmaxParameteriv_size(pname); + GLint answerBuffer[200]; + GLint * params = __glXGetAnswerBuffer(cl, compsize * 4, answerBuffer, sizeof(answerBuffer), 4); + + if (params == NULL) return BadAlloc; + __glXClearErrorOccured(); + + CALL_GetMinmaxParameteriv( GET_DISPATCH(), ( + *(GLenum *)(pc + 0), + pname, + params + ) ); + __glXSendReply(cl->client, params, compsize, 4, GL_FALSE, 0); + error = Success; + } + + return error; +} + void __glXDisp_Histogram(GLbyte * pc) { CALL_Histogram( GET_DISPATCH(), ( @@ -4038,8 +4357,8 @@ void __glXDisp_VertexAttrib1dvARB(GLbyte * pc) #endif CALL_VertexAttrib1dvARB( GET_DISPATCH(), ( - *(GLuint *)(pc + 8), - (const GLdouble *)(pc + 0) + *(GLuint *)(pc + 0), + (const GLdouble *)(pc + 4) ) ); } @@ -4069,8 +4388,8 @@ void __glXDisp_VertexAttrib2dvARB(GLbyte * pc) #endif CALL_VertexAttrib2dvARB( GET_DISPATCH(), ( - *(GLuint *)(pc + 16), - (const GLdouble *)(pc + 0) + *(GLuint *)(pc + 0), + (const GLdouble *)(pc + 4) ) ); } @@ -4100,8 +4419,8 @@ void __glXDisp_VertexAttrib3dvARB(GLbyte * pc) #endif CALL_VertexAttrib3dvARB( GET_DISPATCH(), ( - *(GLuint *)(pc + 24), - (const GLdouble *)(pc + 0) + *(GLuint *)(pc + 0), + (const GLdouble *)(pc + 4) ) ); } @@ -4187,8 +4506,8 @@ void __glXDisp_VertexAttrib4dvARB(GLbyte * pc) #endif CALL_VertexAttrib4dvARB( GET_DISPATCH(), ( - *(GLuint *)(pc + 32), - (const GLdouble *)(pc + 0) + *(GLuint *)(pc + 0), + (const GLdouble *)(pc + 4) ) ); } @@ -4414,131 +4733,6 @@ void __glXDisp_DrawBuffersARB(GLbyte * pc) ) ); } -int __glXDisp_GetColorTableParameterfvSGI(__GLXclientState *cl, GLbyte *pc) -{ - xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; - int error; - __GLXcontext * const cx = __glXForceCurrent(cl, req->contextTag, &error); - - pc += __GLX_VENDPRIV_HDR_SIZE; - if ( cx != NULL ) { - const GLenum pname = *(GLenum *)(pc + 4); - - const GLuint compsize = __glGetColorTableParameterfvSGI_size(pname); - GLfloat answerBuffer[200]; - GLfloat * params = __glXGetAnswerBuffer(cl, compsize * 4, answerBuffer, sizeof(answerBuffer), 4); - - if (params == NULL) return BadAlloc; - __glXClearErrorOccured(); - - CALL_GetColorTableParameterfvSGI( GET_DISPATCH(), ( - *(GLenum *)(pc + 0), - pname, - params - ) ); - __glXSendReply(cl->client, params, compsize, 4, GL_FALSE, 0); - error = Success; - } - - return error; -} - -int __glXDisp_GetColorTableParameterivSGI(__GLXclientState *cl, GLbyte *pc) -{ - xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; - int error; - __GLXcontext * const cx = __glXForceCurrent(cl, req->contextTag, &error); - - pc += __GLX_VENDPRIV_HDR_SIZE; - if ( cx != NULL ) { - const GLenum pname = *(GLenum *)(pc + 4); - - const GLuint compsize = __glGetColorTableParameterivSGI_size(pname); - GLint answerBuffer[200]; - GLint * params = __glXGetAnswerBuffer(cl, compsize * 4, answerBuffer, sizeof(answerBuffer), 4); - - if (params == NULL) return BadAlloc; - __glXClearErrorOccured(); - - CALL_GetColorTableParameterivSGI( GET_DISPATCH(), ( - *(GLenum *)(pc + 0), - pname, - params - ) ); - __glXSendReply(cl->client, params, compsize, 4, GL_FALSE, 0); - error = Success; - } - - return error; -} - -int __glXDisp_AreTexturesResidentEXT(__GLXclientState *cl, GLbyte *pc) -{ - xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; - int error; - __GLXcontext * const cx = __glXForceCurrent(cl, req->contextTag, &error); - - pc += __GLX_VENDPRIV_HDR_SIZE; - if ( cx != NULL ) { - const GLsizei n = *(GLsizei *)(pc + 0); - - GLboolean retval; - GLboolean answerBuffer[200]; - GLboolean * residences = __glXGetAnswerBuffer(cl, n, answerBuffer, sizeof(answerBuffer), 1); - retval = CALL_AreTexturesResidentEXT( GET_DISPATCH(), ( - n, - (const GLuint *)(pc + 4), - residences - ) ); - __glXSendReply(cl->client, residences, n, 1, GL_TRUE, retval); - error = Success; - } - - return error; -} - -int __glXDisp_GenTexturesEXT(__GLXclientState *cl, GLbyte *pc) -{ - xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; - int error; - __GLXcontext * const cx = __glXForceCurrent(cl, req->contextTag, &error); - - pc += __GLX_VENDPRIV_HDR_SIZE; - if ( cx != NULL ) { - const GLsizei n = *(GLsizei *)(pc + 0); - - GLuint answerBuffer[200]; - GLuint * textures = __glXGetAnswerBuffer(cl, n * 4, answerBuffer, sizeof(answerBuffer), 4); - CALL_GenTexturesEXT( GET_DISPATCH(), ( - n, - textures - ) ); - __glXSendReply(cl->client, textures, n, 4, GL_TRUE, 0); - error = Success; - } - - return error; -} - -int __glXDisp_IsTextureEXT(__GLXclientState *cl, GLbyte *pc) -{ - xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; - int error; - __GLXcontext * const cx = __glXForceCurrent(cl, req->contextTag, &error); - - pc += __GLX_VENDPRIV_HDR_SIZE; - if ( cx != NULL ) { - GLboolean retval; - retval = CALL_IsTextureEXT( GET_DISPATCH(), ( - *(GLuint *)(pc + 0) - ) ); - __glXSendReply(cl->client, dummy_answer, 0, 0, GL_FALSE, retval); - error = Success; - } - - return error; -} - void __glXDisp_SampleMaskSGIS(GLbyte * pc) { CALL_SampleMaskSGIS( GET_DISPATCH(), ( @@ -5466,6 +5660,14 @@ void __glXDisp_ProgramNamedParameter4fvNV(GLbyte * pc) ) ); } +void __glXDisp_BlendEquationSeparateEXT(GLbyte * pc) +{ + CALL_BlendEquationSeparateEXT( GET_DISPATCH(), ( + *(GLenum *)(pc + 0), + *(GLenum *)(pc + 4) + ) ); +} + void __glXDisp_BindFramebufferEXT(GLbyte * pc) { CALL_BindFramebufferEXT( GET_DISPATCH(), ( diff --git a/GL/glx/indirect_dispatch.h b/GL/glx/indirect_dispatch.h index a0da3e505..9bf74ebd1 100644 --- a/GL/glx/indirect_dispatch.h +++ b/GL/glx/indirect_dispatch.h @@ -61,8 +61,6 @@ extern HIDDEN void __glXDisp_ActiveTextureARB(GLbyte * pc); extern HIDDEN void __glXDispSwap_ActiveTextureARB(GLbyte * pc); extern HIDDEN void __glXDisp_VertexAttrib4ubvNV(GLbyte * pc); extern HIDDEN void __glXDispSwap_VertexAttrib4ubvNV(GLbyte * pc); -extern HIDDEN int __glXDisp_GetColorTableParameterfvSGI(struct __GLXclientStateRec *, GLbyte *); -extern HIDDEN int __glXDispSwap_GetColorTableParameterfvSGI(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDisp_GetProgramNamedParameterdvNV(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_GetProgramNamedParameterdvNV(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN void __glXDisp_Histogram(GLbyte * pc); @@ -73,6 +71,8 @@ extern HIDDEN void __glXDisp_RasterPos4dv(GLbyte * pc); extern HIDDEN void __glXDispSwap_RasterPos4dv(GLbyte * pc); extern HIDDEN void __glXDisp_PolygonStipple(GLbyte * pc); extern HIDDEN void __glXDispSwap_PolygonStipple(GLbyte * pc); +extern HIDDEN void __glXDisp_BlendEquationSeparateEXT(GLbyte * pc); +extern HIDDEN void __glXDispSwap_BlendEquationSeparateEXT(GLbyte * pc); extern HIDDEN int __glXDisp_GetPixelMapfv(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_GetPixelMapfv(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN void __glXDisp_Color3uiv(GLbyte * pc); @@ -161,6 +161,8 @@ extern HIDDEN void __glXDisp_Color3sv(GLbyte * pc); extern HIDDEN void __glXDispSwap_Color3sv(GLbyte * pc); extern HIDDEN int __glXDisp_GetConvolutionParameteriv(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_GetConvolutionParameteriv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetConvolutionParameterivEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetConvolutionParameterivEXT(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN void __glXDisp_Vertex2dv(GLbyte * pc); extern HIDDEN void __glXDispSwap_Vertex2dv(GLbyte * pc); extern HIDDEN int __glXDisp_GetVisualConfigs(struct __GLXclientStateRec *, GLbyte *); @@ -247,10 +249,10 @@ extern HIDDEN void __glXDisp_PixelMapfv(GLbyte * pc); extern HIDDEN void __glXDispSwap_PixelMapfv(GLbyte * pc); extern HIDDEN void __glXDisp_Color3usv(GLbyte * pc); extern HIDDEN void __glXDispSwap_Color3usv(GLbyte * pc); -extern HIDDEN void __glXDisp_DrawBuffersARB(GLbyte * pc); -extern HIDDEN void __glXDispSwap_DrawBuffersARB(GLbyte * pc); extern HIDDEN int __glXDisp_AreTexturesResident(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_AreTexturesResident(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_AreTexturesResidentEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_AreTexturesResidentEXT(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDisp_IsRenderbufferEXT(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_IsRenderbufferEXT(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN void __glXDisp_PointParameterfvEXT(GLbyte * pc); @@ -319,6 +321,8 @@ extern HIDDEN int __glXDisp_CreateNewContext(struct __GLXclientStateRec *, GLbyt extern HIDDEN int __glXDispSwap_CreateNewContext(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDisp_GetMinmax(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_GetMinmax(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetMinmaxEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetMinmaxEXT(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDisp_GetVertexAttribdvNV(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_GetVertexAttribdvNV(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN void __glXDisp_Normal3fv(GLbyte * pc); @@ -401,14 +405,16 @@ extern HIDDEN void __glXDisp_TexCoord4fv(GLbyte * pc); extern HIDDEN void __glXDispSwap_TexCoord4fv(GLbyte * pc); extern HIDDEN int __glXDisp_WaitX(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_WaitX(struct __GLXclientStateRec *, GLbyte *); -extern HIDDEN void __glXDisp_VertexAttrib2dvNV(GLbyte * pc); -extern HIDDEN void __glXDispSwap_VertexAttrib2dvNV(GLbyte * pc); +extern HIDDEN void __glXDisp_SecondaryColor3uivEXT(GLbyte * pc); +extern HIDDEN void __glXDispSwap_SecondaryColor3uivEXT(GLbyte * pc); extern HIDDEN void __glXDisp_FramebufferRenderbufferEXT(GLbyte * pc); extern HIDDEN void __glXDispSwap_FramebufferRenderbufferEXT(GLbyte * pc); extern HIDDEN void __glXDisp_VertexAttrib1dvNV(GLbyte * pc); extern HIDDEN void __glXDispSwap_VertexAttrib1dvNV(GLbyte * pc); extern HIDDEN int __glXDisp_GenTextures(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_GenTextures(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GenTexturesEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GenTexturesEXT(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN void __glXDisp_FramebufferTexture1DEXT(GLbyte * pc); extern HIDDEN void __glXDispSwap_FramebufferTexture1DEXT(GLbyte * pc); extern HIDDEN int __glXDisp_GetDrawableAttributes(struct __GLXclientStateRec *, GLbyte *); @@ -469,6 +475,8 @@ extern HIDDEN void __glXDisp_CopyTexSubImage3D(GLbyte * pc); extern HIDDEN void __glXDispSwap_CopyTexSubImage3D(GLbyte * pc); extern HIDDEN int __glXDisp_GetColorTable(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_GetColorTable(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetColorTableSGI(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetColorTableSGI(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN void __glXDisp_Indexiv(GLbyte * pc); extern HIDDEN void __glXDispSwap_Indexiv(GLbyte * pc); extern HIDDEN int __glXDisp_CreateContext(struct __GLXclientStateRec *, GLbyte *); @@ -477,6 +485,8 @@ extern HIDDEN void __glXDisp_CopyColorTable(GLbyte * pc); extern HIDDEN void __glXDispSwap_CopyColorTable(GLbyte * pc); extern HIDDEN int __glXDisp_GetHistogramParameterfv(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_GetHistogramParameterfv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetHistogramParameterfvEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetHistogramParameterfvEXT(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN void __glXDisp_Frustum(GLbyte * pc); extern HIDDEN void __glXDispSwap_Frustum(GLbyte * pc); extern HIDDEN int __glXDisp_GetString(struct __GLXclientStateRec *, GLbyte *); @@ -493,6 +503,8 @@ extern HIDDEN void __glXDisp_VertexAttrib1dvARB(GLbyte * pc); extern HIDDEN void __glXDispSwap_VertexAttrib1dvARB(GLbyte * pc); extern HIDDEN int __glXDisp_DeleteTextures(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_DeleteTextures(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_DeleteTexturesEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_DeleteTexturesEXT(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDisp_GetTexLevelParameteriv(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_GetTexLevelParameteriv(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN void __glXDisp_ClearAccum(GLbyte * pc); @@ -549,6 +561,8 @@ extern HIDDEN void __glXDisp_PolygonMode(GLbyte * pc); extern HIDDEN void __glXDispSwap_PolygonMode(GLbyte * pc); extern HIDDEN void __glXDisp_CompressedTexSubImage1DARB(GLbyte * pc); extern HIDDEN void __glXDispSwap_CompressedTexSubImage1DARB(GLbyte * pc); +extern HIDDEN void __glXDisp_VertexAttrib2dvNV(GLbyte * pc); +extern HIDDEN void __glXDispSwap_VertexAttrib2dvNV(GLbyte * pc); extern HIDDEN int __glXDisp_GetVertexAttribivNV(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_GetVertexAttribivNV(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDisp_IsQueryARB(struct __GLXclientStateRec *, GLbyte *); @@ -585,6 +599,8 @@ extern HIDDEN void __glXDisp_Color3dv(GLbyte * pc); extern HIDDEN void __glXDispSwap_Color3dv(GLbyte * pc); extern HIDDEN int __glXDisp_IsTexture(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_IsTexture(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_IsTextureEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_IsTextureEXT(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDisp_DeleteQueriesARB(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_DeleteQueriesARB(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDisp_GetMapdv(struct __GLXclientStateRec *, GLbyte *); @@ -615,6 +631,8 @@ extern HIDDEN int __glXDisp_GetVertexAttribdvARB(struct __GLXclientStateRec *, G extern HIDDEN int __glXDispSwap_GetVertexAttribdvARB(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDisp_GetSeparableFilter(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_GetSeparableFilter(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetSeparableFilterEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetSeparableFilterEXT(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN void __glXDisp_RequestResidentProgramsNV(GLbyte * pc); extern HIDDEN void __glXDispSwap_RequestResidentProgramsNV(GLbyte * pc); extern HIDDEN int __glXDisp_FeedbackBuffer(struct __GLXclientStateRec *, GLbyte *); @@ -633,8 +651,6 @@ extern HIDDEN void __glXDisp_PolygonOffset(GLbyte * pc); extern HIDDEN void __glXDispSwap_PolygonOffset(GLbyte * pc); extern HIDDEN void __glXDisp_ExecuteProgramNV(GLbyte * pc); extern HIDDEN void __glXDispSwap_ExecuteProgramNV(GLbyte * pc); -extern HIDDEN int __glXDisp_GetColorTableParameterivSGI(struct __GLXclientStateRec *, GLbyte *); -extern HIDDEN int __glXDispSwap_GetColorTableParameterivSGI(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN void __glXDisp_Normal3dv(GLbyte * pc); extern HIDDEN void __glXDispSwap_Normal3dv(GLbyte * pc); extern HIDDEN void __glXDisp_Lightf(GLbyte * pc); @@ -679,10 +695,12 @@ extern HIDDEN void __glXDisp_TexEnviv(GLbyte * pc); extern HIDDEN void __glXDispSwap_TexEnviv(GLbyte * pc); extern HIDDEN void __glXDisp_TexSubImage3D(GLbyte * pc); extern HIDDEN void __glXDispSwap_TexSubImage3D(GLbyte * pc); -extern HIDDEN void __glXDisp_SecondaryColor3uivEXT(GLbyte * pc); -extern HIDDEN void __glXDispSwap_SecondaryColor3uivEXT(GLbyte * pc); +extern HIDDEN int __glXDisp_SwapIntervalSGI(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_SwapIntervalSGI(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDisp_GetColorTableParameterfv(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_GetColorTableParameterfv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetColorTableParameterfvSGI(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetColorTableParameterfvSGI(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN void __glXDisp_Bitmap(GLbyte * pc); extern HIDDEN void __glXDispSwap_Bitmap(GLbyte * pc); extern HIDDEN int __glXDisp_GetTexLevelParameterfv(struct __GLXclientStateRec *, GLbyte *); @@ -723,6 +741,8 @@ extern HIDDEN int __glXDisp_ChangeDrawableAttributes(struct __GLXclientStateRec extern HIDDEN int __glXDispSwap_ChangeDrawableAttributes(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDisp_GetMinmaxParameteriv(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_GetMinmaxParameteriv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetMinmaxParameterivEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetMinmaxParameterivEXT(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN void __glXDisp_PixelTransferf(GLbyte * pc); extern HIDDEN void __glXDispSwap_PixelTransferf(GLbyte * pc); extern HIDDEN void __glXDisp_CopyTexImage1D(GLbyte * pc); @@ -753,6 +773,8 @@ extern HIDDEN void __glXDisp_ConvolutionParameterf(GLbyte * pc); extern HIDDEN void __glXDispSwap_ConvolutionParameterf(GLbyte * pc); extern HIDDEN int __glXDisp_GetColorTableParameteriv(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_GetColorTableParameteriv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetColorTableParameterivSGI(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetColorTableParameterivSGI(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDisp_ReleaseTexImageEXT(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_ReleaseTexImageEXT(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN void __glXDisp_CallList(GLbyte * pc); @@ -771,8 +793,6 @@ extern HIDDEN void __glXDisp_BindRenderbufferEXT(GLbyte * pc); extern HIDDEN void __glXDispSwap_BindRenderbufferEXT(GLbyte * pc); extern HIDDEN void __glXDisp_Vertex3sv(GLbyte * pc); extern HIDDEN void __glXDispSwap_Vertex3sv(GLbyte * pc); -extern HIDDEN int __glXDisp_GetColorTableSGI(struct __GLXclientStateRec *, GLbyte *); -extern HIDDEN int __glXDispSwap_GetColorTableSGI(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDisp_BindTexImageEXT(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_BindTexImageEXT(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN void __glXDisp_ProgramLocalParameter4fvARB(GLbyte * pc); @@ -795,10 +815,10 @@ extern HIDDEN void __glXDisp_TexGendv(GLbyte * pc); extern HIDDEN void __glXDispSwap_TexGendv(GLbyte * pc); extern HIDDEN void __glXDisp_ResetMinmax(GLbyte * pc); extern HIDDEN void __glXDispSwap_ResetMinmax(GLbyte * pc); -extern HIDDEN int __glXDisp_GenTexturesEXT(struct __GLXclientStateRec *, GLbyte *); -extern HIDDEN int __glXDispSwap_GenTexturesEXT(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDisp_GetConvolutionParameterfv(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_GetConvolutionParameterfv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetConvolutionParameterfvEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetConvolutionParameterfvEXT(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN void __glXDisp_VertexAttribs4dvNV(GLbyte * pc); extern HIDDEN void __glXDispSwap_VertexAttribs4dvNV(GLbyte * pc); extern HIDDEN int __glXDisp_GetMaterialfv(struct __GLXclientStateRec *, GLbyte *); @@ -825,8 +845,12 @@ extern HIDDEN int __glXDisp_GetProgramLocalParameterdvARB(struct __GLXclientStat extern HIDDEN int __glXDispSwap_GetProgramLocalParameterdvARB(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDisp_GetHistogramParameteriv(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_GetHistogramParameteriv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetHistogramParameterivEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetHistogramParameterivEXT(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDisp_GetConvolutionFilter(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_GetConvolutionFilter(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetConvolutionFilterEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetConvolutionFilterEXT(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDisp_GetProgramivARB(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_GetProgramivARB(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN void __glXDisp_BlendFuncSeparateEXT(GLbyte * pc); @@ -839,8 +863,6 @@ extern HIDDEN void __glXDisp_EvalPoint1(GLbyte * pc); extern HIDDEN void __glXDispSwap_EvalPoint1(GLbyte * pc); extern HIDDEN void __glXDisp_PopMatrix(GLbyte * pc); extern HIDDEN void __glXDispSwap_PopMatrix(GLbyte * pc); -extern HIDDEN int __glXDisp_AreTexturesResidentEXT(struct __GLXclientStateRec *, GLbyte *); -extern HIDDEN int __glXDispSwap_AreTexturesResidentEXT(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDisp_MakeCurrentReadSGI(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_MakeCurrentReadSGI(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDisp_GetTexGeniv(struct __GLXclientStateRec *, GLbyte *); @@ -859,6 +881,8 @@ extern HIDDEN int __glXDisp_GetTexGenfv(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_GetTexGenfv(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDisp_GetHistogram(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_GetHistogram(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetHistogramEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetHistogramEXT(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN void __glXDisp_ActiveStencilFaceEXT(GLbyte * pc); extern HIDDEN void __glXDispSwap_ActiveStencilFaceEXT(GLbyte * pc); extern HIDDEN void __glXDisp_Materialf(GLbyte * pc); @@ -891,6 +915,8 @@ extern HIDDEN int __glXDisp_IsList(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_IsList(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDisp_RenderMode(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_RenderMode(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN void __glXDisp_DrawBuffersARB(GLbyte * pc); +extern HIDDEN void __glXDispSwap_DrawBuffersARB(GLbyte * pc); extern HIDDEN void __glXDisp_LoadName(GLbyte * pc); extern HIDDEN void __glXDispSwap_LoadName(GLbyte * pc); extern HIDDEN void __glXDisp_VertexAttribs4ubvNV(GLbyte * pc); @@ -917,8 +943,6 @@ extern HIDDEN void __glXDisp_VertexAttrib4uivARB(GLbyte * pc); extern HIDDEN void __glXDispSwap_VertexAttrib4uivARB(GLbyte * pc); extern HIDDEN void __glXDisp_ClipPlane(GLbyte * pc); extern HIDDEN void __glXDispSwap_ClipPlane(GLbyte * pc); -extern HIDDEN int __glXDisp_IsTextureEXT(struct __GLXclientStateRec *, GLbyte *); -extern HIDDEN int __glXDispSwap_IsTextureEXT(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDisp_GetPixelMapuiv(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_GetPixelMapuiv(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN void __glXDisp_Indexfv(GLbyte * pc); @@ -1001,6 +1025,8 @@ extern HIDDEN void __glXDisp_VertexAttribs4svNV(GLbyte * pc); extern HIDDEN void __glXDispSwap_VertexAttribs4svNV(GLbyte * pc); extern HIDDEN int __glXDisp_GetMinmaxParameterfv(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN int __glXDispSwap_GetMinmaxParameterfv(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDisp_GetMinmaxParameterfvEXT(struct __GLXclientStateRec *, GLbyte *); +extern HIDDEN int __glXDispSwap_GetMinmaxParameterfvEXT(struct __GLXclientStateRec *, GLbyte *); extern HIDDEN void __glXDisp_VertexAttrib1fvARB(GLbyte * pc); extern HIDDEN void __glXDispSwap_VertexAttrib1fvARB(GLbyte * pc); extern HIDDEN void __glXDisp_VertexAttribs1svNV(GLbyte * pc); diff --git a/GL/glx/indirect_dispatch_swap.c b/GL/glx/indirect_dispatch_swap.c index 06c1d0363..9c58ef1cd 100644 --- a/GL/glx/indirect_dispatch_swap.c +++ b/GL/glx/indirect_dispatch_swap.c @@ -2887,6 +2887,31 @@ int __glXDispSwap_AreTexturesResident(__GLXclientState *cl, GLbyte *pc) return error; } +int __glXDispSwap_AreTexturesResidentEXT(__GLXclientState *cl, GLbyte *pc) +{ + xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; + int error; + __GLXcontext * const cx = __glXForceCurrent(cl, bswap_CARD32( &req->contextTag ), &error); + + pc += __GLX_VENDPRIV_HDR_SIZE; + if ( cx != NULL ) { + const GLsizei n = (GLsizei )bswap_CARD32 ( pc + 0 ); + + GLboolean retval; + GLboolean answerBuffer[200]; + GLboolean * residences = __glXGetAnswerBuffer(cl, n, answerBuffer, sizeof(answerBuffer), 1); + retval = CALL_AreTexturesResident( GET_DISPATCH(), ( + n, + (const GLuint *)bswap_32_array( (uint32_t *) (pc + 4), 0 ), + residences + ) ); + __glXSendReplySwap(cl->client, residences, n, 1, GL_TRUE, retval); + error = Success; + } + + return error; +} + void __glXDispSwap_CopyTexImage1D(GLbyte * pc) { CALL_CopyTexImage1D( GET_DISPATCH(), ( @@ -2941,6 +2966,26 @@ void __glXDispSwap_CopyTexSubImage2D(GLbyte * pc) } int __glXDispSwap_DeleteTextures(__GLXclientState *cl, GLbyte *pc) +{ + xGLXSingleReq * const req = (xGLXSingleReq *) pc; + int error; + __GLXcontext * const cx = __glXForceCurrent(cl, bswap_CARD32( &req->contextTag ), &error); + + pc += __GLX_SINGLE_HDR_SIZE; + if ( cx != NULL ) { + const GLsizei n = (GLsizei )bswap_CARD32 ( pc + 0 ); + + CALL_DeleteTextures( GET_DISPATCH(), ( + n, + (const GLuint *)bswap_32_array( (uint32_t *) (pc + 4), 0 ) + ) ); + error = Success; + } + + return error; +} + +int __glXDispSwap_DeleteTexturesEXT(__GLXclientState *cl, GLbyte *pc) { xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; int error; @@ -2984,6 +3029,30 @@ int __glXDispSwap_GenTextures(__GLXclientState *cl, GLbyte *pc) return error; } +int __glXDispSwap_GenTexturesEXT(__GLXclientState *cl, GLbyte *pc) +{ + xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; + int error; + __GLXcontext * const cx = __glXForceCurrent(cl, bswap_CARD32( &req->contextTag ), &error); + + pc += __GLX_VENDPRIV_HDR_SIZE; + if ( cx != NULL ) { + const GLsizei n = (GLsizei )bswap_CARD32 ( pc + 0 ); + + GLuint answerBuffer[200]; + GLuint * textures = __glXGetAnswerBuffer(cl, n * 4, answerBuffer, sizeof(answerBuffer), 4); + CALL_GenTextures( GET_DISPATCH(), ( + n, + textures + ) ); + (void) bswap_32_array( (uint32_t *) textures, n ); + __glXSendReplySwap(cl->client, textures, n, 4, GL_TRUE, 0); + error = Success; + } + + return error; +} + int __glXDispSwap_IsTexture(__GLXclientState *cl, GLbyte *pc) { xGLXSingleReq * const req = (xGLXSingleReq *) pc; @@ -3003,6 +3072,25 @@ int __glXDispSwap_IsTexture(__GLXclientState *cl, GLbyte *pc) return error; } +int __glXDispSwap_IsTextureEXT(__GLXclientState *cl, GLbyte *pc) +{ + xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; + int error; + __GLXcontext * const cx = __glXForceCurrent(cl, bswap_CARD32( &req->contextTag ), &error); + + pc += __GLX_VENDPRIV_HDR_SIZE; + if ( cx != NULL ) { + GLboolean retval; + retval = CALL_IsTexture( GET_DISPATCH(), ( + (GLuint )bswap_CARD32 ( pc + 0 ) + ) ); + __glXSendReplySwap(cl->client, dummy_answer, 0, 0, GL_FALSE, retval); + error = Success; + } + + return error; +} + void __glXDispSwap_PrioritizeTextures(GLbyte * pc) { const GLsizei n = (GLsizei )bswap_CARD32 ( pc + 0 ); @@ -3172,6 +3260,36 @@ int __glXDispSwap_GetColorTableParameterfv(__GLXclientState *cl, GLbyte *pc) return error; } +int __glXDispSwap_GetColorTableParameterfvSGI(__GLXclientState *cl, GLbyte *pc) +{ + xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; + int error; + __GLXcontext * const cx = __glXForceCurrent(cl, bswap_CARD32( &req->contextTag ), &error); + + pc += __GLX_VENDPRIV_HDR_SIZE; + if ( cx != NULL ) { + const GLenum pname = (GLenum )bswap_ENUM ( pc + 4 ); + + const GLuint compsize = __glGetColorTableParameterfv_size(pname); + GLfloat answerBuffer[200]; + GLfloat * params = __glXGetAnswerBuffer(cl, compsize * 4, answerBuffer, sizeof(answerBuffer), 4); + + if (params == NULL) return BadAlloc; + __glXClearErrorOccured(); + + CALL_GetColorTableParameterfv( GET_DISPATCH(), ( + (GLenum )bswap_ENUM ( pc + 0 ), + pname, + params + ) ); + (void) bswap_32_array( (uint32_t *) params, compsize ); + __glXSendReplySwap(cl->client, params, compsize, 4, GL_FALSE, 0); + error = Success; + } + + return error; +} + int __glXDispSwap_GetColorTableParameteriv(__GLXclientState *cl, GLbyte *pc) { xGLXSingleReq * const req = (xGLXSingleReq *) pc; @@ -3202,6 +3320,36 @@ int __glXDispSwap_GetColorTableParameteriv(__GLXclientState *cl, GLbyte *pc) return error; } +int __glXDispSwap_GetColorTableParameterivSGI(__GLXclientState *cl, GLbyte *pc) +{ + xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; + int error; + __GLXcontext * const cx = __glXForceCurrent(cl, bswap_CARD32( &req->contextTag ), &error); + + pc += __GLX_VENDPRIV_HDR_SIZE; + if ( cx != NULL ) { + const GLenum pname = (GLenum )bswap_ENUM ( pc + 4 ); + + const GLuint compsize = __glGetColorTableParameteriv_size(pname); + GLint answerBuffer[200]; + GLint * params = __glXGetAnswerBuffer(cl, compsize * 4, answerBuffer, sizeof(answerBuffer), 4); + + if (params == NULL) return BadAlloc; + __glXClearErrorOccured(); + + CALL_GetColorTableParameteriv( GET_DISPATCH(), ( + (GLenum )bswap_ENUM ( pc + 0 ), + pname, + params + ) ); + (void) bswap_32_array( (uint32_t *) params, compsize ); + __glXSendReplySwap(cl->client, params, compsize, 4, GL_FALSE, 0); + error = Success; + } + + return error; +} + void __glXDispSwap_ColorSubTable(GLbyte * pc) { const GLvoid * const data = (const GLvoid *) (pc + 40); @@ -3379,6 +3527,36 @@ int __glXDispSwap_GetConvolutionParameterfv(__GLXclientState *cl, GLbyte *pc) return error; } +int __glXDispSwap_GetConvolutionParameterfvEXT(__GLXclientState *cl, GLbyte *pc) +{ + xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; + int error; + __GLXcontext * const cx = __glXForceCurrent(cl, bswap_CARD32( &req->contextTag ), &error); + + pc += __GLX_VENDPRIV_HDR_SIZE; + if ( cx != NULL ) { + const GLenum pname = (GLenum )bswap_ENUM ( pc + 4 ); + + const GLuint compsize = __glGetConvolutionParameterfv_size(pname); + GLfloat answerBuffer[200]; + GLfloat * params = __glXGetAnswerBuffer(cl, compsize * 4, answerBuffer, sizeof(answerBuffer), 4); + + if (params == NULL) return BadAlloc; + __glXClearErrorOccured(); + + CALL_GetConvolutionParameterfv( GET_DISPATCH(), ( + (GLenum )bswap_ENUM ( pc + 0 ), + pname, + params + ) ); + (void) bswap_32_array( (uint32_t *) params, compsize ); + __glXSendReplySwap(cl->client, params, compsize, 4, GL_FALSE, 0); + error = Success; + } + + return error; +} + int __glXDispSwap_GetConvolutionParameteriv(__GLXclientState *cl, GLbyte *pc) { xGLXSingleReq * const req = (xGLXSingleReq *) pc; @@ -3409,6 +3587,36 @@ int __glXDispSwap_GetConvolutionParameteriv(__GLXclientState *cl, GLbyte *pc) return error; } +int __glXDispSwap_GetConvolutionParameterivEXT(__GLXclientState *cl, GLbyte *pc) +{ + xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; + int error; + __GLXcontext * const cx = __glXForceCurrent(cl, bswap_CARD32( &req->contextTag ), &error); + + pc += __GLX_VENDPRIV_HDR_SIZE; + if ( cx != NULL ) { + const GLenum pname = (GLenum )bswap_ENUM ( pc + 4 ); + + const GLuint compsize = __glGetConvolutionParameteriv_size(pname); + GLint answerBuffer[200]; + GLint * params = __glXGetAnswerBuffer(cl, compsize * 4, answerBuffer, sizeof(answerBuffer), 4); + + if (params == NULL) return BadAlloc; + __glXClearErrorOccured(); + + CALL_GetConvolutionParameteriv( GET_DISPATCH(), ( + (GLenum )bswap_ENUM ( pc + 0 ), + pname, + params + ) ); + (void) bswap_32_array( (uint32_t *) params, compsize ); + __glXSendReplySwap(cl->client, params, compsize, 4, GL_FALSE, 0); + error = Success; + } + + return error; +} + int __glXDispSwap_GetHistogramParameterfv(__GLXclientState *cl, GLbyte *pc) { xGLXSingleReq * const req = (xGLXSingleReq *) pc; @@ -3439,6 +3647,36 @@ int __glXDispSwap_GetHistogramParameterfv(__GLXclientState *cl, GLbyte *pc) return error; } +int __glXDispSwap_GetHistogramParameterfvEXT(__GLXclientState *cl, GLbyte *pc) +{ + xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; + int error; + __GLXcontext * const cx = __glXForceCurrent(cl, bswap_CARD32( &req->contextTag ), &error); + + pc += __GLX_VENDPRIV_HDR_SIZE; + if ( cx != NULL ) { + const GLenum pname = (GLenum )bswap_ENUM ( pc + 4 ); + + const GLuint compsize = __glGetHistogramParameterfv_size(pname); + GLfloat answerBuffer[200]; + GLfloat * params = __glXGetAnswerBuffer(cl, compsize * 4, answerBuffer, sizeof(answerBuffer), 4); + + if (params == NULL) return BadAlloc; + __glXClearErrorOccured(); + + CALL_GetHistogramParameterfv( GET_DISPATCH(), ( + (GLenum )bswap_ENUM ( pc + 0 ), + pname, + params + ) ); + (void) bswap_32_array( (uint32_t *) params, compsize ); + __glXSendReplySwap(cl->client, params, compsize, 4, GL_FALSE, 0); + error = Success; + } + + return error; +} + int __glXDispSwap_GetHistogramParameteriv(__GLXclientState *cl, GLbyte *pc) { xGLXSingleReq * const req = (xGLXSingleReq *) pc; @@ -3469,6 +3707,36 @@ int __glXDispSwap_GetHistogramParameteriv(__GLXclientState *cl, GLbyte *pc) return error; } +int __glXDispSwap_GetHistogramParameterivEXT(__GLXclientState *cl, GLbyte *pc) +{ + xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; + int error; + __GLXcontext * const cx = __glXForceCurrent(cl, bswap_CARD32( &req->contextTag ), &error); + + pc += __GLX_VENDPRIV_HDR_SIZE; + if ( cx != NULL ) { + const GLenum pname = (GLenum )bswap_ENUM ( pc + 4 ); + + const GLuint compsize = __glGetHistogramParameteriv_size(pname); + GLint answerBuffer[200]; + GLint * params = __glXGetAnswerBuffer(cl, compsize * 4, answerBuffer, sizeof(answerBuffer), 4); + + if (params == NULL) return BadAlloc; + __glXClearErrorOccured(); + + CALL_GetHistogramParameteriv( GET_DISPATCH(), ( + (GLenum )bswap_ENUM ( pc + 0 ), + pname, + params + ) ); + (void) bswap_32_array( (uint32_t *) params, compsize ); + __glXSendReplySwap(cl->client, params, compsize, 4, GL_FALSE, 0); + error = Success; + } + + return error; +} + int __glXDispSwap_GetMinmaxParameterfv(__GLXclientState *cl, GLbyte *pc) { xGLXSingleReq * const req = (xGLXSingleReq *) pc; @@ -3499,6 +3767,36 @@ int __glXDispSwap_GetMinmaxParameterfv(__GLXclientState *cl, GLbyte *pc) return error; } +int __glXDispSwap_GetMinmaxParameterfvEXT(__GLXclientState *cl, GLbyte *pc) +{ + xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; + int error; + __GLXcontext * const cx = __glXForceCurrent(cl, bswap_CARD32( &req->contextTag ), &error); + + pc += __GLX_VENDPRIV_HDR_SIZE; + if ( cx != NULL ) { + const GLenum pname = (GLenum )bswap_ENUM ( pc + 4 ); + + const GLuint compsize = __glGetMinmaxParameterfv_size(pname); + GLfloat answerBuffer[200]; + GLfloat * params = __glXGetAnswerBuffer(cl, compsize * 4, answerBuffer, sizeof(answerBuffer), 4); + + if (params == NULL) return BadAlloc; + __glXClearErrorOccured(); + + CALL_GetMinmaxParameterfv( GET_DISPATCH(), ( + (GLenum )bswap_ENUM ( pc + 0 ), + pname, + params + ) ); + (void) bswap_32_array( (uint32_t *) params, compsize ); + __glXSendReplySwap(cl->client, params, compsize, 4, GL_FALSE, 0); + error = Success; + } + + return error; +} + int __glXDispSwap_GetMinmaxParameteriv(__GLXclientState *cl, GLbyte *pc) { xGLXSingleReq * const req = (xGLXSingleReq *) pc; @@ -3529,6 +3827,36 @@ int __glXDispSwap_GetMinmaxParameteriv(__GLXclientState *cl, GLbyte *pc) return error; } +int __glXDispSwap_GetMinmaxParameterivEXT(__GLXclientState *cl, GLbyte *pc) +{ + xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; + int error; + __GLXcontext * const cx = __glXForceCurrent(cl, bswap_CARD32( &req->contextTag ), &error); + + pc += __GLX_VENDPRIV_HDR_SIZE; + if ( cx != NULL ) { + const GLenum pname = (GLenum )bswap_ENUM ( pc + 4 ); + + const GLuint compsize = __glGetMinmaxParameteriv_size(pname); + GLint answerBuffer[200]; + GLint * params = __glXGetAnswerBuffer(cl, compsize * 4, answerBuffer, sizeof(answerBuffer), 4); + + if (params == NULL) return BadAlloc; + __glXClearErrorOccured(); + + CALL_GetMinmaxParameteriv( GET_DISPATCH(), ( + (GLenum )bswap_ENUM ( pc + 0 ), + pname, + params + ) ); + (void) bswap_32_array( (uint32_t *) params, compsize ); + __glXSendReplySwap(cl->client, params, compsize, 4, GL_FALSE, 0); + error = Success; + } + + return error; +} + void __glXDispSwap_Histogram(GLbyte * pc) { CALL_Histogram( GET_DISPATCH(), ( @@ -4186,8 +4514,8 @@ void __glXDispSwap_VertexAttrib1dvARB(GLbyte * pc) #endif CALL_VertexAttrib1dvARB( GET_DISPATCH(), ( - (GLuint )bswap_CARD32 ( pc + 8 ), - (const GLdouble *)bswap_64_array( (uint64_t *) (pc + 0), 1 ) + (GLuint )bswap_CARD32 ( pc + 0 ), + (const GLdouble *)bswap_64_array( (uint64_t *) (pc + 4), 1 ) ) ); } @@ -4217,8 +4545,8 @@ void __glXDispSwap_VertexAttrib2dvARB(GLbyte * pc) #endif CALL_VertexAttrib2dvARB( GET_DISPATCH(), ( - (GLuint )bswap_CARD32 ( pc + 16 ), - (const GLdouble *)bswap_64_array( (uint64_t *) (pc + 0), 2 ) + (GLuint )bswap_CARD32 ( pc + 0 ), + (const GLdouble *)bswap_64_array( (uint64_t *) (pc + 4), 2 ) ) ); } @@ -4248,8 +4576,8 @@ void __glXDispSwap_VertexAttrib3dvARB(GLbyte * pc) #endif CALL_VertexAttrib3dvARB( GET_DISPATCH(), ( - (GLuint )bswap_CARD32 ( pc + 24 ), - (const GLdouble *)bswap_64_array( (uint64_t *) (pc + 0), 3 ) + (GLuint )bswap_CARD32 ( pc + 0 ), + (const GLdouble *)bswap_64_array( (uint64_t *) (pc + 4), 3 ) ) ); } @@ -4335,8 +4663,8 @@ void __glXDispSwap_VertexAttrib4dvARB(GLbyte * pc) #endif CALL_VertexAttrib4dvARB( GET_DISPATCH(), ( - (GLuint )bswap_CARD32 ( pc + 32 ), - (const GLdouble *)bswap_64_array( (uint64_t *) (pc + 0), 4 ) + (GLuint )bswap_CARD32 ( pc + 0 ), + (const GLdouble *)bswap_64_array( (uint64_t *) (pc + 4), 4 ) ) ); } @@ -4566,134 +4894,6 @@ void __glXDispSwap_DrawBuffersARB(GLbyte * pc) ) ); } -int __glXDispSwap_GetColorTableParameterfvSGI(__GLXclientState *cl, GLbyte *pc) -{ - xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; - int error; - __GLXcontext * const cx = __glXForceCurrent(cl, bswap_CARD32( &req->contextTag ), &error); - - pc += __GLX_VENDPRIV_HDR_SIZE; - if ( cx != NULL ) { - const GLenum pname = (GLenum )bswap_ENUM ( pc + 4 ); - - const GLuint compsize = __glGetColorTableParameterfvSGI_size(pname); - GLfloat answerBuffer[200]; - GLfloat * params = __glXGetAnswerBuffer(cl, compsize * 4, answerBuffer, sizeof(answerBuffer), 4); - - if (params == NULL) return BadAlloc; - __glXClearErrorOccured(); - - CALL_GetColorTableParameterfvSGI( GET_DISPATCH(), ( - (GLenum )bswap_ENUM ( pc + 0 ), - pname, - params - ) ); - (void) bswap_32_array( (uint32_t *) params, compsize ); - __glXSendReplySwap(cl->client, params, compsize, 4, GL_FALSE, 0); - error = Success; - } - - return error; -} - -int __glXDispSwap_GetColorTableParameterivSGI(__GLXclientState *cl, GLbyte *pc) -{ - xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; - int error; - __GLXcontext * const cx = __glXForceCurrent(cl, bswap_CARD32( &req->contextTag ), &error); - - pc += __GLX_VENDPRIV_HDR_SIZE; - if ( cx != NULL ) { - const GLenum pname = (GLenum )bswap_ENUM ( pc + 4 ); - - const GLuint compsize = __glGetColorTableParameterivSGI_size(pname); - GLint answerBuffer[200]; - GLint * params = __glXGetAnswerBuffer(cl, compsize * 4, answerBuffer, sizeof(answerBuffer), 4); - - if (params == NULL) return BadAlloc; - __glXClearErrorOccured(); - - CALL_GetColorTableParameterivSGI( GET_DISPATCH(), ( - (GLenum )bswap_ENUM ( pc + 0 ), - pname, - params - ) ); - (void) bswap_32_array( (uint32_t *) params, compsize ); - __glXSendReplySwap(cl->client, params, compsize, 4, GL_FALSE, 0); - error = Success; - } - - return error; -} - -int __glXDispSwap_AreTexturesResidentEXT(__GLXclientState *cl, GLbyte *pc) -{ - xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; - int error; - __GLXcontext * const cx = __glXForceCurrent(cl, bswap_CARD32( &req->contextTag ), &error); - - pc += __GLX_VENDPRIV_HDR_SIZE; - if ( cx != NULL ) { - const GLsizei n = (GLsizei )bswap_CARD32 ( pc + 0 ); - - GLboolean retval; - GLboolean answerBuffer[200]; - GLboolean * residences = __glXGetAnswerBuffer(cl, n, answerBuffer, sizeof(answerBuffer), 1); - retval = CALL_AreTexturesResidentEXT( GET_DISPATCH(), ( - n, - (const GLuint *)bswap_32_array( (uint32_t *) (pc + 4), 0 ), - residences - ) ); - __glXSendReplySwap(cl->client, residences, n, 1, GL_TRUE, retval); - error = Success; - } - - return error; -} - -int __glXDispSwap_GenTexturesEXT(__GLXclientState *cl, GLbyte *pc) -{ - xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; - int error; - __GLXcontext * const cx = __glXForceCurrent(cl, bswap_CARD32( &req->contextTag ), &error); - - pc += __GLX_VENDPRIV_HDR_SIZE; - if ( cx != NULL ) { - const GLsizei n = (GLsizei )bswap_CARD32 ( pc + 0 ); - - GLuint answerBuffer[200]; - GLuint * textures = __glXGetAnswerBuffer(cl, n * 4, answerBuffer, sizeof(answerBuffer), 4); - CALL_GenTexturesEXT( GET_DISPATCH(), ( - n, - textures - ) ); - (void) bswap_32_array( (uint32_t *) textures, n ); - __glXSendReplySwap(cl->client, textures, n, 4, GL_TRUE, 0); - error = Success; - } - - return error; -} - -int __glXDispSwap_IsTextureEXT(__GLXclientState *cl, GLbyte *pc) -{ - xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; - int error; - __GLXcontext * const cx = __glXForceCurrent(cl, bswap_CARD32( &req->contextTag ), &error); - - pc += __GLX_VENDPRIV_HDR_SIZE; - if ( cx != NULL ) { - GLboolean retval; - retval = CALL_IsTextureEXT( GET_DISPATCH(), ( - (GLuint )bswap_CARD32 ( pc + 0 ) - ) ); - __glXSendReplySwap(cl->client, dummy_answer, 0, 0, GL_FALSE, retval); - error = Success; - } - - return error; -} - void __glXDispSwap_SampleMaskSGIS(GLbyte * pc) { CALL_SampleMaskSGIS( GET_DISPATCH(), ( @@ -5631,6 +5831,14 @@ void __glXDispSwap_ProgramNamedParameter4fvNV(GLbyte * pc) ) ); } +void __glXDispSwap_BlendEquationSeparateEXT(GLbyte * pc) +{ + CALL_BlendEquationSeparateEXT( GET_DISPATCH(), ( + (GLenum )bswap_ENUM ( pc + 0 ), + (GLenum )bswap_ENUM ( pc + 4 ) + ) ); +} + void __glXDispSwap_BindFramebufferEXT(GLbyte * pc) { CALL_BindFramebufferEXT( GET_DISPATCH(), ( diff --git a/GL/glx/indirect_program.c b/GL/glx/indirect_program.c new file mode 100644 index 000000000..d0fd3d135 --- /dev/null +++ b/GL/glx/indirect_program.c @@ -0,0 +1,163 @@ +/* + * (C) Copyright IBM Corporation 2005, 2006 + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, THE AUTHORS, AND/OR THEIR SUPPLIERS BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * \file indirect_program.c + * Hand-coded routines needed to support programmable pipeline extensions. + * + * \author Ian Romanick + */ + +#define NEED_REPLIES +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#include "glxserver.h" +#include "glxext.h" +#include "singlesize.h" +#include "unpack.h" +#include "indirect_size_get.h" +#include "indirect_dispatch.h" +#include "glapitable.h" +#include "glapi.h" +#include "glthread.h" +#include "dispatch.h" +#include "glapioffsets.h" + +#ifdef __linux__ +#include +#elif defined(__OpenBSD__) +#include +#define bswap_16 __swap16 +#define bswap_32 __swap32 +#define bswap_64 __swap64 +#else +#include +#define bswap_16 bswap16 +#define bswap_32 bswap32 +#define bswap_64 bswap64 +#endif + +static int DoGetProgramString(struct __GLXclientStateRec *cl, GLbyte *pc, + unsigned get_programiv_offset, unsigned get_program_string_offset, + Bool do_swap); + +/** + * Handle both types of glGetProgramString calls. + * + * This single function handles both \c glGetProgramStringARB and + * \c glGetProgramStringNV. The dispatch offsets for the functions to use + * for \c glGetProgramivARB and \c glGetProgramStringARB are passed in by the + * caller. These can be the offsets of either the ARB versions or the NV + * versions. + */ +int DoGetProgramString(struct __GLXclientStateRec *cl, GLbyte *pc, + unsigned get_programiv_offset, + unsigned get_program_string_offset, + Bool do_swap) +{ + xGLXVendorPrivateWithReplyReq * const req = + (xGLXVendorPrivateWithReplyReq *) pc; + int error; + __GLXcontext * const cx = __glXForceCurrent(cl, req->contextTag, & error); + ClientPtr client = cl->client; + + + pc += __GLX_VENDPRIV_HDR_SIZE; + if (cx != NULL) { + GLenum target; + GLenum pname; + GLint compsize = 0; + char *answer = NULL, answerBuffer[200]; + + if (do_swap) { + target = (GLenum) bswap_32(*(int *)(pc + 0)); + pname = (GLenum) bswap_32(*(int *)(pc + 4)); + } + else { + target = *(GLenum *)(pc + 0); + pname = *(GLuint *)(pc + 4); + } + + /* The value of the GL_PROGRAM_LENGTH_ARB and GL_PROGRAM_LENGTH_NV + * enumerants is the same. + */ + CALL_by_offset(GET_DISPATCH(), + (void (GLAPIENTRYP)(GLuint, GLenum, GLint *)), + get_programiv_offset, + (target, GL_PROGRAM_LENGTH_ARB, &compsize)); + + if (compsize != 0) { + __GLX_GET_ANSWER_BUFFER(answer,cl,compsize,1); + __glXClearErrorOccured(); + + CALL_by_offset(GET_DISPATCH(), + (void (GLAPIENTRYP)(GLuint, GLenum, GLubyte *)), + get_program_string_offset, + (target, pname, answer)); + } + + if (__glXErrorOccured()) { + __GLX_BEGIN_REPLY(0); + __GLX_SEND_HEADER(); + } else { + __GLX_BEGIN_REPLY(compsize); + ((xGLXGetTexImageReply *)&__glXReply)->width = compsize; + __GLX_SEND_HEADER(); + __GLX_SEND_VOID_ARRAY(compsize); + } + + error = Success; + } + + return error; +} + +int __glXDisp_GetProgramStringARB(struct __GLXclientStateRec *cl, GLbyte *pc) +{ + return DoGetProgramString(cl, pc, _gloffset_GetProgramivARB, + _gloffset_GetProgramStringARB, False); +} + + +int __glXDispSwap_GetProgramStringARB(struct __GLXclientStateRec *cl, GLbyte *pc) +{ + return DoGetProgramString(cl, pc, _gloffset_GetProgramivARB, + _gloffset_GetProgramStringARB, True); +} + + +int __glXDisp_GetProgramStringNV(struct __GLXclientStateRec *cl, GLbyte *pc) +{ + return DoGetProgramString(cl, pc, _gloffset_GetProgramivNV, + _gloffset_GetProgramStringNV, False); +} + + +int __glXDispSwap_GetProgramStringNV(struct __GLXclientStateRec *cl, GLbyte *pc) +{ + return DoGetProgramString(cl, pc, _gloffset_GetProgramivNV, + _gloffset_GetProgramStringNV, True); +} diff --git a/GL/glx/indirect_size_get.c b/GL/glx/indirect_size_get.c index c16b29a89..150c6a182 100644 --- a/GL/glx/indirect_size_get.c +++ b/GL/glx/indirect_size_get.c @@ -67,1099 +67,1124 @@ INTERNAL PURE FASTCALL GLint -__glCallLists_size( GLenum e ) +__glCallLists_size(GLenum e) { - switch( e ) { - case GL_BYTE: - case GL_UNSIGNED_BYTE: - return 1; - case GL_SHORT: - case GL_UNSIGNED_SHORT: - case GL_2_BYTES: - return 2; - case GL_3_BYTES: - return 3; - case GL_INT: - case GL_UNSIGNED_INT: - case GL_FLOAT: - case GL_4_BYTES: - return 4; - default: return 0; + switch (e) { + case GL_BYTE: + case GL_UNSIGNED_BYTE: + return 1; + case GL_SHORT: + case GL_UNSIGNED_SHORT: + case GL_2_BYTES: + return 2; + case GL_3_BYTES: + return 3; + case GL_INT: + case GL_UNSIGNED_INT: + case GL_FLOAT: + case GL_4_BYTES: + return 4; + default: + return 0; } } INTERNAL PURE FASTCALL GLint -__glFogfv_size( GLenum e ) +__glFogfv_size(GLenum e) { - switch( e ) { - case GL_FOG_INDEX: - case GL_FOG_DENSITY: - case GL_FOG_START: - case GL_FOG_END: - case GL_FOG_MODE: - case GL_FOG_OFFSET_VALUE_SGIX: - case GL_FOG_DISTANCE_MODE_NV: - return 1; - case GL_FOG_COLOR: - return 4; - default: return 0; + switch (e) { + case GL_FOG_INDEX: + case GL_FOG_DENSITY: + case GL_FOG_START: + case GL_FOG_END: + case GL_FOG_MODE: + case GL_FOG_OFFSET_VALUE_SGIX: + case GL_FOG_DISTANCE_MODE_NV: + return 1; + case GL_FOG_COLOR: + return 4; + default: + return 0; } } INTERNAL PURE FASTCALL GLint -__glLightfv_size( GLenum e ) +__glLightfv_size(GLenum e) { - switch( e ) { - case GL_SPOT_EXPONENT: - case GL_SPOT_CUTOFF: - case GL_CONSTANT_ATTENUATION: - case GL_LINEAR_ATTENUATION: - case GL_QUADRATIC_ATTENUATION: - return 1; - case GL_SPOT_DIRECTION: - return 3; - case GL_AMBIENT: - case GL_DIFFUSE: - case GL_SPECULAR: - case GL_POSITION: - return 4; - default: return 0; + switch (e) { + case GL_SPOT_EXPONENT: + case GL_SPOT_CUTOFF: + case GL_CONSTANT_ATTENUATION: + case GL_LINEAR_ATTENUATION: + case GL_QUADRATIC_ATTENUATION: + return 1; + case GL_SPOT_DIRECTION: + return 3; + case GL_AMBIENT: + case GL_DIFFUSE: + case GL_SPECULAR: + case GL_POSITION: + return 4; + default: + return 0; } } INTERNAL PURE FASTCALL GLint -__glLightModelfv_size( GLenum e ) +__glLightModelfv_size(GLenum e) { - switch( e ) { - case GL_LIGHT_MODEL_LOCAL_VIEWER: - case GL_LIGHT_MODEL_TWO_SIDE: - case GL_LIGHT_MODEL_COLOR_CONTROL: + switch (e) { + case GL_LIGHT_MODEL_LOCAL_VIEWER: + case GL_LIGHT_MODEL_TWO_SIDE: + case GL_LIGHT_MODEL_COLOR_CONTROL: /* case GL_LIGHT_MODEL_COLOR_CONTROL_EXT:*/ - return 1; - case GL_LIGHT_MODEL_AMBIENT: - return 4; - default: return 0; + return 1; + case GL_LIGHT_MODEL_AMBIENT: + return 4; + default: + return 0; } } INTERNAL PURE FASTCALL GLint -__glMaterialfv_size( GLenum e ) +__glMaterialfv_size(GLenum e) { - switch( e ) { - case GL_SHININESS: - return 1; - case GL_COLOR_INDEXES: - return 3; - case GL_AMBIENT: - case GL_DIFFUSE: - case GL_SPECULAR: - case GL_EMISSION: - case GL_AMBIENT_AND_DIFFUSE: - return 4; - default: return 0; + switch (e) { + case GL_SHININESS: + return 1; + case GL_COLOR_INDEXES: + return 3; + case GL_AMBIENT: + case GL_DIFFUSE: + case GL_SPECULAR: + case GL_EMISSION: + case GL_AMBIENT_AND_DIFFUSE: + return 4; + default: + return 0; } } INTERNAL PURE FASTCALL GLint -__glTexParameterfv_size( GLenum e ) +__glTexParameterfv_size(GLenum e) { - switch( e ) { - case GL_TEXTURE_MAG_FILTER: - case GL_TEXTURE_MIN_FILTER: - case GL_TEXTURE_WRAP_S: - case GL_TEXTURE_WRAP_T: - case GL_TEXTURE_PRIORITY: - case GL_TEXTURE_WRAP_R: - case GL_TEXTURE_COMPARE_FAIL_VALUE_ARB: + switch (e) { + case GL_TEXTURE_MAG_FILTER: + case GL_TEXTURE_MIN_FILTER: + case GL_TEXTURE_WRAP_S: + case GL_TEXTURE_WRAP_T: + case GL_TEXTURE_PRIORITY: + case GL_TEXTURE_WRAP_R: + case GL_TEXTURE_COMPARE_FAIL_VALUE_ARB: /* case GL_SHADOW_AMBIENT_SGIX:*/ - case GL_TEXTURE_MIN_LOD: - case GL_TEXTURE_MAX_LOD: - case GL_TEXTURE_BASE_LEVEL: - case GL_TEXTURE_MAX_LEVEL: - case GL_TEXTURE_CLIPMAP_FRAME_SGIX: - case GL_TEXTURE_LOD_BIAS_S_SGIX: - case GL_TEXTURE_LOD_BIAS_T_SGIX: - case GL_TEXTURE_LOD_BIAS_R_SGIX: - case GL_GENERATE_MIPMAP: + case GL_TEXTURE_MIN_LOD: + case GL_TEXTURE_MAX_LOD: + case GL_TEXTURE_BASE_LEVEL: + case GL_TEXTURE_MAX_LEVEL: + case GL_TEXTURE_CLIPMAP_FRAME_SGIX: + case GL_TEXTURE_LOD_BIAS_S_SGIX: + case GL_TEXTURE_LOD_BIAS_T_SGIX: + case GL_TEXTURE_LOD_BIAS_R_SGIX: + case GL_GENERATE_MIPMAP: /* case GL_GENERATE_MIPMAP_SGIS:*/ - case GL_TEXTURE_COMPARE_SGIX: - case GL_TEXTURE_COMPARE_OPERATOR_SGIX: - case GL_TEXTURE_MAX_CLAMP_S_SGIX: - case GL_TEXTURE_MAX_CLAMP_T_SGIX: - case GL_TEXTURE_MAX_CLAMP_R_SGIX: - case GL_TEXTURE_MAX_ANISOTROPY_EXT: - case GL_TEXTURE_LOD_BIAS: + case GL_TEXTURE_COMPARE_SGIX: + case GL_TEXTURE_COMPARE_OPERATOR_SGIX: + case GL_TEXTURE_MAX_CLAMP_S_SGIX: + case GL_TEXTURE_MAX_CLAMP_T_SGIX: + case GL_TEXTURE_MAX_CLAMP_R_SGIX: + case GL_TEXTURE_MAX_ANISOTROPY_EXT: + case GL_TEXTURE_LOD_BIAS: /* case GL_TEXTURE_LOD_BIAS_EXT:*/ - case GL_DEPTH_TEXTURE_MODE: + case GL_DEPTH_TEXTURE_MODE: /* case GL_DEPTH_TEXTURE_MODE_ARB:*/ - case GL_TEXTURE_COMPARE_MODE: + case GL_TEXTURE_COMPARE_MODE: /* case GL_TEXTURE_COMPARE_MODE_ARB:*/ - case GL_TEXTURE_COMPARE_FUNC: + case GL_TEXTURE_COMPARE_FUNC: /* case GL_TEXTURE_COMPARE_FUNC_ARB:*/ - case GL_TEXTURE_UNSIGNED_REMAP_MODE_NV: - return 1; - case GL_TEXTURE_CLIPMAP_CENTER_SGIX: - case GL_TEXTURE_CLIPMAP_OFFSET_SGIX: - return 2; - case GL_TEXTURE_CLIPMAP_VIRTUAL_DEPTH_SGIX: - return 3; - case GL_TEXTURE_BORDER_COLOR: - case GL_POST_TEXTURE_FILTER_BIAS_SGIX: - case GL_POST_TEXTURE_FILTER_SCALE_SGIX: - return 4; - default: return 0; + case GL_TEXTURE_UNSIGNED_REMAP_MODE_NV: + return 1; + case GL_TEXTURE_CLIPMAP_CENTER_SGIX: + case GL_TEXTURE_CLIPMAP_OFFSET_SGIX: + return 2; + case GL_TEXTURE_CLIPMAP_VIRTUAL_DEPTH_SGIX: + return 3; + case GL_TEXTURE_BORDER_COLOR: + case GL_POST_TEXTURE_FILTER_BIAS_SGIX: + case GL_POST_TEXTURE_FILTER_SCALE_SGIX: + return 4; + default: + return 0; } } INTERNAL PURE FASTCALL GLint -__glTexEnvfv_size( GLenum e ) +__glTexEnvfv_size(GLenum e) { - switch( e ) { - case GL_ALPHA_SCALE: - case GL_TEXTURE_ENV_MODE: - case GL_TEXTURE_LOD_BIAS: - case GL_COMBINE_RGB: - case GL_COMBINE_ALPHA: - case GL_RGB_SCALE: - case GL_SOURCE0_RGB: - case GL_SOURCE1_RGB: - case GL_SOURCE2_RGB: - case GL_SOURCE3_RGB_NV: - case GL_SOURCE0_ALPHA: - case GL_SOURCE1_ALPHA: - case GL_SOURCE2_ALPHA: - case GL_SOURCE3_ALPHA_NV: - case GL_OPERAND0_RGB: - case GL_OPERAND1_RGB: - case GL_OPERAND2_RGB: - case GL_OPERAND3_RGB_NV: - case GL_OPERAND0_ALPHA: - case GL_OPERAND1_ALPHA: - case GL_OPERAND2_ALPHA: - case GL_OPERAND3_ALPHA_NV: - case GL_COORD_REPLACE_ARB: + switch (e) { + case GL_ALPHA_SCALE: + case GL_TEXTURE_ENV_MODE: + case GL_TEXTURE_LOD_BIAS: + case GL_COMBINE_RGB: + case GL_COMBINE_ALPHA: + case GL_RGB_SCALE: + case GL_SOURCE0_RGB: + case GL_SOURCE1_RGB: + case GL_SOURCE2_RGB: + case GL_SOURCE3_RGB_NV: + case GL_SOURCE0_ALPHA: + case GL_SOURCE1_ALPHA: + case GL_SOURCE2_ALPHA: + case GL_SOURCE3_ALPHA_NV: + case GL_OPERAND0_RGB: + case GL_OPERAND1_RGB: + case GL_OPERAND2_RGB: + case GL_OPERAND3_RGB_NV: + case GL_OPERAND0_ALPHA: + case GL_OPERAND1_ALPHA: + case GL_OPERAND2_ALPHA: + case GL_OPERAND3_ALPHA_NV: + case GL_COORD_REPLACE_ARB: /* case GL_COORD_REPLACE_NV:*/ - return 1; - case GL_TEXTURE_ENV_COLOR: - return 4; - default: return 0; + return 1; + case GL_TEXTURE_ENV_COLOR: + return 4; + default: + return 0; } } INTERNAL PURE FASTCALL GLint -__glTexGendv_size( GLenum e ) +__glTexGendv_size(GLenum e) { - switch( e ) { - case GL_TEXTURE_GEN_MODE: - return 1; - case GL_OBJECT_PLANE: - case GL_EYE_PLANE: - return 4; - default: return 0; + switch (e) { + case GL_TEXTURE_GEN_MODE: + return 1; + case GL_OBJECT_PLANE: + case GL_EYE_PLANE: + return 4; + default: + return 0; } } INTERNAL PURE FASTCALL GLint -__glMap1d_size( GLenum e ) +__glMap1d_size(GLenum e) { - switch( e ) { - case GL_MAP1_INDEX: - case GL_MAP1_TEXTURE_COORD_1: - return 1; - case GL_MAP1_TEXTURE_COORD_2: - return 2; - case GL_MAP1_NORMAL: - case GL_MAP1_TEXTURE_COORD_3: - case GL_MAP1_VERTEX_3: - return 3; - case GL_MAP1_COLOR_4: - case GL_MAP1_TEXTURE_COORD_4: - case GL_MAP1_VERTEX_4: - return 4; - default: return 0; + switch (e) { + case GL_MAP1_INDEX: + case GL_MAP1_TEXTURE_COORD_1: + return 1; + case GL_MAP1_TEXTURE_COORD_2: + return 2; + case GL_MAP1_NORMAL: + case GL_MAP1_TEXTURE_COORD_3: + case GL_MAP1_VERTEX_3: + return 3; + case GL_MAP1_COLOR_4: + case GL_MAP1_TEXTURE_COORD_4: + case GL_MAP1_VERTEX_4: + return 4; + default: + return 0; } } INTERNAL PURE FASTCALL GLint -__glMap2d_size( GLenum e ) +__glMap2d_size(GLenum e) { - switch( e ) { - case GL_MAP2_INDEX: - case GL_MAP2_TEXTURE_COORD_1: - return 1; - case GL_MAP2_TEXTURE_COORD_2: - return 2; - case GL_MAP2_NORMAL: - case GL_MAP2_TEXTURE_COORD_3: - case GL_MAP2_VERTEX_3: - return 3; - case GL_MAP2_COLOR_4: - case GL_MAP2_TEXTURE_COORD_4: - case GL_MAP2_VERTEX_4: - return 4; - default: return 0; + switch (e) { + case GL_MAP2_INDEX: + case GL_MAP2_TEXTURE_COORD_1: + return 1; + case GL_MAP2_TEXTURE_COORD_2: + return 2; + case GL_MAP2_NORMAL: + case GL_MAP2_TEXTURE_COORD_3: + case GL_MAP2_VERTEX_3: + return 3; + case GL_MAP2_COLOR_4: + case GL_MAP2_TEXTURE_COORD_4: + case GL_MAP2_VERTEX_4: + return 4; + default: + return 0; } } INTERNAL PURE FASTCALL GLint -__glGetBooleanv_size( GLenum e ) +__glGetBooleanv_size(GLenum e) { - switch( e ) { - case GL_CURRENT_INDEX: - case GL_CURRENT_RASTER_INDEX: - case GL_CURRENT_RASTER_POSITION_VALID: - case GL_CURRENT_RASTER_DISTANCE: - case GL_POINT_SMOOTH: - case GL_POINT_SIZE: - case GL_SMOOTH_POINT_SIZE_GRANULARITY: - case GL_LINE_SMOOTH: - case GL_LINE_WIDTH: - case GL_LINE_WIDTH_GRANULARITY: - case GL_LINE_STIPPLE: - case GL_LINE_STIPPLE_PATTERN: - case GL_LINE_STIPPLE_REPEAT: - case GL_LIST_MODE: - case GL_MAX_LIST_NESTING: - case GL_LIST_BASE: - case GL_LIST_INDEX: - case GL_POLYGON_SMOOTH: - case GL_POLYGON_STIPPLE: - case GL_EDGE_FLAG: - case GL_CULL_FACE: - case GL_CULL_FACE_MODE: - case GL_FRONT_FACE: - case GL_LIGHTING: - case GL_LIGHT_MODEL_LOCAL_VIEWER: - case GL_LIGHT_MODEL_TWO_SIDE: - case GL_SHADE_MODEL: - case GL_COLOR_MATERIAL_FACE: - case GL_COLOR_MATERIAL_PARAMETER: - case GL_COLOR_MATERIAL: - case GL_FOG: - case GL_FOG_INDEX: - case GL_FOG_DENSITY: - case GL_FOG_START: - case GL_FOG_END: - case GL_FOG_MODE: - case GL_DEPTH_TEST: - case GL_DEPTH_WRITEMASK: - case GL_DEPTH_CLEAR_VALUE: - case GL_DEPTH_FUNC: - case GL_STENCIL_TEST: - case GL_STENCIL_CLEAR_VALUE: - case GL_STENCIL_FUNC: - case GL_STENCIL_VALUE_MASK: - case GL_STENCIL_FAIL: - case GL_STENCIL_PASS_DEPTH_FAIL: - case GL_STENCIL_PASS_DEPTH_PASS: - case GL_STENCIL_REF: - case GL_STENCIL_WRITEMASK: - case GL_MATRIX_MODE: - case GL_NORMALIZE: - case GL_MODELVIEW_STACK_DEPTH: - case GL_PROJECTION_STACK_DEPTH: - case GL_TEXTURE_STACK_DEPTH: - case GL_ATTRIB_STACK_DEPTH: - case GL_ALPHA_TEST: - case GL_ALPHA_TEST_FUNC: - case GL_ALPHA_TEST_REF: - case GL_DITHER: - case GL_BLEND_DST: - case GL_BLEND_SRC: - case GL_BLEND: - case GL_LOGIC_OP_MODE: - case GL_LOGIC_OP: - case GL_AUX_BUFFERS: - case GL_DRAW_BUFFER: - case GL_READ_BUFFER: - case GL_SCISSOR_TEST: - case GL_INDEX_CLEAR_VALUE: - case GL_INDEX_WRITEMASK: - case GL_INDEX_MODE: - case GL_RGBA_MODE: - case GL_DOUBLEBUFFER: - case GL_STEREO: - case GL_RENDER_MODE: - case GL_PERSPECTIVE_CORRECTION_HINT: - case GL_POINT_SMOOTH_HINT: - case GL_LINE_SMOOTH_HINT: - case GL_POLYGON_SMOOTH_HINT: - case GL_FOG_HINT: - case GL_TEXTURE_GEN_S: - case GL_TEXTURE_GEN_T: - case GL_TEXTURE_GEN_R: - case GL_TEXTURE_GEN_Q: - case GL_PIXEL_MAP_I_TO_I: - case GL_PIXEL_MAP_I_TO_I_SIZE: - case GL_PIXEL_MAP_S_TO_S_SIZE: - case GL_PIXEL_MAP_I_TO_R_SIZE: - case GL_PIXEL_MAP_I_TO_G_SIZE: - case GL_PIXEL_MAP_I_TO_B_SIZE: - case GL_PIXEL_MAP_I_TO_A_SIZE: - case GL_PIXEL_MAP_R_TO_R_SIZE: - case GL_PIXEL_MAP_G_TO_G_SIZE: - case GL_PIXEL_MAP_B_TO_B_SIZE: - case GL_PIXEL_MAP_A_TO_A_SIZE: - case GL_UNPACK_SWAP_BYTES: - case GL_UNPACK_LSB_FIRST: - case GL_UNPACK_ROW_LENGTH: - case GL_UNPACK_SKIP_ROWS: - case GL_UNPACK_SKIP_PIXELS: - case GL_UNPACK_ALIGNMENT: - case GL_PACK_SWAP_BYTES: - case GL_PACK_LSB_FIRST: - case GL_PACK_ROW_LENGTH: - case GL_PACK_SKIP_ROWS: - case GL_PACK_SKIP_PIXELS: - case GL_PACK_ALIGNMENT: - case GL_MAP_COLOR: - case GL_MAP_STENCIL: - case GL_INDEX_SHIFT: - case GL_INDEX_OFFSET: - case GL_RED_SCALE: - case GL_RED_BIAS: - case GL_ZOOM_X: - case GL_ZOOM_Y: - case GL_GREEN_SCALE: - case GL_GREEN_BIAS: - case GL_BLUE_SCALE: - case GL_BLUE_BIAS: - case GL_ALPHA_SCALE: - case GL_ALPHA_BIAS: - case GL_DEPTH_SCALE: - case GL_DEPTH_BIAS: - case GL_MAX_EVAL_ORDER: - case GL_MAX_LIGHTS: - case GL_MAX_CLIP_PLANES: - case GL_MAX_TEXTURE_SIZE: - case GL_MAX_PIXEL_MAP_TABLE: - case GL_MAX_ATTRIB_STACK_DEPTH: - case GL_MAX_MODELVIEW_STACK_DEPTH: - case GL_MAX_NAME_STACK_DEPTH: - case GL_MAX_PROJECTION_STACK_DEPTH: - case GL_MAX_TEXTURE_STACK_DEPTH: - case GL_SUBPIXEL_BITS: - case GL_INDEX_BITS: - case GL_RED_BITS: - case GL_GREEN_BITS: - case GL_BLUE_BITS: - case GL_ALPHA_BITS: - case GL_DEPTH_BITS: - case GL_STENCIL_BITS: - case GL_ACCUM_RED_BITS: - case GL_ACCUM_GREEN_BITS: - case GL_ACCUM_BLUE_BITS: - case GL_ACCUM_ALPHA_BITS: - case GL_NAME_STACK_DEPTH: - case GL_AUTO_NORMAL: - case GL_MAP1_COLOR_4: - case GL_MAP1_INDEX: - case GL_MAP1_NORMAL: - case GL_MAP1_TEXTURE_COORD_1: - case GL_MAP1_TEXTURE_COORD_2: - case GL_MAP1_TEXTURE_COORD_3: - case GL_MAP1_TEXTURE_COORD_4: - case GL_MAP1_VERTEX_3: - case GL_MAP1_VERTEX_4: - case GL_MAP2_COLOR_4: - case GL_MAP2_INDEX: - case GL_MAP2_NORMAL: - case GL_MAP2_TEXTURE_COORD_1: - case GL_MAP2_TEXTURE_COORD_2: - case GL_MAP2_TEXTURE_COORD_3: - case GL_MAP2_TEXTURE_COORD_4: - case GL_MAP2_VERTEX_3: - case GL_MAP2_VERTEX_4: - case GL_MAP1_GRID_SEGMENTS: - case GL_TEXTURE_1D: - case GL_TEXTURE_2D: - case GL_POLYGON_OFFSET_UNITS: - case GL_CLIP_PLANE0: - case GL_CLIP_PLANE1: - case GL_CLIP_PLANE2: - case GL_CLIP_PLANE3: - case GL_CLIP_PLANE4: - case GL_CLIP_PLANE5: - case GL_LIGHT0: - case GL_LIGHT1: - case GL_LIGHT2: - case GL_LIGHT3: - case GL_LIGHT4: - case GL_LIGHT5: - case GL_LIGHT6: - case GL_LIGHT7: - case GL_BLEND_EQUATION: + switch (e) { + case GL_CURRENT_INDEX: + case GL_CURRENT_RASTER_INDEX: + case GL_CURRENT_RASTER_POSITION_VALID: + case GL_CURRENT_RASTER_DISTANCE: + case GL_POINT_SMOOTH: + case GL_POINT_SIZE: + case GL_SMOOTH_POINT_SIZE_GRANULARITY: + case GL_LINE_SMOOTH: + case GL_LINE_WIDTH: + case GL_LINE_WIDTH_GRANULARITY: + case GL_LINE_STIPPLE: + case GL_LINE_STIPPLE_PATTERN: + case GL_LINE_STIPPLE_REPEAT: + case GL_LIST_MODE: + case GL_MAX_LIST_NESTING: + case GL_LIST_BASE: + case GL_LIST_INDEX: + case GL_POLYGON_SMOOTH: + case GL_POLYGON_STIPPLE: + case GL_EDGE_FLAG: + case GL_CULL_FACE: + case GL_CULL_FACE_MODE: + case GL_FRONT_FACE: + case GL_LIGHTING: + case GL_LIGHT_MODEL_LOCAL_VIEWER: + case GL_LIGHT_MODEL_TWO_SIDE: + case GL_SHADE_MODEL: + case GL_COLOR_MATERIAL_FACE: + case GL_COLOR_MATERIAL_PARAMETER: + case GL_COLOR_MATERIAL: + case GL_FOG: + case GL_FOG_INDEX: + case GL_FOG_DENSITY: + case GL_FOG_START: + case GL_FOG_END: + case GL_FOG_MODE: + case GL_DEPTH_TEST: + case GL_DEPTH_WRITEMASK: + case GL_DEPTH_CLEAR_VALUE: + case GL_DEPTH_FUNC: + case GL_STENCIL_TEST: + case GL_STENCIL_CLEAR_VALUE: + case GL_STENCIL_FUNC: + case GL_STENCIL_VALUE_MASK: + case GL_STENCIL_FAIL: + case GL_STENCIL_PASS_DEPTH_FAIL: + case GL_STENCIL_PASS_DEPTH_PASS: + case GL_STENCIL_REF: + case GL_STENCIL_WRITEMASK: + case GL_MATRIX_MODE: + case GL_NORMALIZE: + case GL_MODELVIEW_STACK_DEPTH: + case GL_PROJECTION_STACK_DEPTH: + case GL_TEXTURE_STACK_DEPTH: + case GL_ATTRIB_STACK_DEPTH: + case GL_ALPHA_TEST: + case GL_ALPHA_TEST_FUNC: + case GL_ALPHA_TEST_REF: + case GL_DITHER: + case GL_BLEND_DST: + case GL_BLEND_SRC: + case GL_BLEND: + case GL_LOGIC_OP_MODE: + case GL_LOGIC_OP: + case GL_AUX_BUFFERS: + case GL_DRAW_BUFFER: + case GL_READ_BUFFER: + case GL_SCISSOR_TEST: + case GL_INDEX_CLEAR_VALUE: + case GL_INDEX_WRITEMASK: + case GL_INDEX_MODE: + case GL_RGBA_MODE: + case GL_DOUBLEBUFFER: + case GL_STEREO: + case GL_RENDER_MODE: + case GL_PERSPECTIVE_CORRECTION_HINT: + case GL_POINT_SMOOTH_HINT: + case GL_LINE_SMOOTH_HINT: + case GL_POLYGON_SMOOTH_HINT: + case GL_FOG_HINT: + case GL_TEXTURE_GEN_S: + case GL_TEXTURE_GEN_T: + case GL_TEXTURE_GEN_R: + case GL_TEXTURE_GEN_Q: + case GL_PIXEL_MAP_I_TO_I: + case GL_PIXEL_MAP_I_TO_I_SIZE: + case GL_PIXEL_MAP_S_TO_S_SIZE: + case GL_PIXEL_MAP_I_TO_R_SIZE: + case GL_PIXEL_MAP_I_TO_G_SIZE: + case GL_PIXEL_MAP_I_TO_B_SIZE: + case GL_PIXEL_MAP_I_TO_A_SIZE: + case GL_PIXEL_MAP_R_TO_R_SIZE: + case GL_PIXEL_MAP_G_TO_G_SIZE: + case GL_PIXEL_MAP_B_TO_B_SIZE: + case GL_PIXEL_MAP_A_TO_A_SIZE: + case GL_UNPACK_SWAP_BYTES: + case GL_UNPACK_LSB_FIRST: + case GL_UNPACK_ROW_LENGTH: + case GL_UNPACK_SKIP_ROWS: + case GL_UNPACK_SKIP_PIXELS: + case GL_UNPACK_ALIGNMENT: + case GL_PACK_SWAP_BYTES: + case GL_PACK_LSB_FIRST: + case GL_PACK_ROW_LENGTH: + case GL_PACK_SKIP_ROWS: + case GL_PACK_SKIP_PIXELS: + case GL_PACK_ALIGNMENT: + case GL_MAP_COLOR: + case GL_MAP_STENCIL: + case GL_INDEX_SHIFT: + case GL_INDEX_OFFSET: + case GL_RED_SCALE: + case GL_RED_BIAS: + case GL_ZOOM_X: + case GL_ZOOM_Y: + case GL_GREEN_SCALE: + case GL_GREEN_BIAS: + case GL_BLUE_SCALE: + case GL_BLUE_BIAS: + case GL_ALPHA_SCALE: + case GL_ALPHA_BIAS: + case GL_DEPTH_SCALE: + case GL_DEPTH_BIAS: + case GL_MAX_EVAL_ORDER: + case GL_MAX_LIGHTS: + case GL_MAX_CLIP_PLANES: + case GL_MAX_TEXTURE_SIZE: + case GL_MAX_PIXEL_MAP_TABLE: + case GL_MAX_ATTRIB_STACK_DEPTH: + case GL_MAX_MODELVIEW_STACK_DEPTH: + case GL_MAX_NAME_STACK_DEPTH: + case GL_MAX_PROJECTION_STACK_DEPTH: + case GL_MAX_TEXTURE_STACK_DEPTH: + case GL_SUBPIXEL_BITS: + case GL_INDEX_BITS: + case GL_RED_BITS: + case GL_GREEN_BITS: + case GL_BLUE_BITS: + case GL_ALPHA_BITS: + case GL_DEPTH_BITS: + case GL_STENCIL_BITS: + case GL_ACCUM_RED_BITS: + case GL_ACCUM_GREEN_BITS: + case GL_ACCUM_BLUE_BITS: + case GL_ACCUM_ALPHA_BITS: + case GL_NAME_STACK_DEPTH: + case GL_AUTO_NORMAL: + case GL_MAP1_COLOR_4: + case GL_MAP1_INDEX: + case GL_MAP1_NORMAL: + case GL_MAP1_TEXTURE_COORD_1: + case GL_MAP1_TEXTURE_COORD_2: + case GL_MAP1_TEXTURE_COORD_3: + case GL_MAP1_TEXTURE_COORD_4: + case GL_MAP1_VERTEX_3: + case GL_MAP1_VERTEX_4: + case GL_MAP2_COLOR_4: + case GL_MAP2_INDEX: + case GL_MAP2_NORMAL: + case GL_MAP2_TEXTURE_COORD_1: + case GL_MAP2_TEXTURE_COORD_2: + case GL_MAP2_TEXTURE_COORD_3: + case GL_MAP2_TEXTURE_COORD_4: + case GL_MAP2_VERTEX_3: + case GL_MAP2_VERTEX_4: + case GL_MAP1_GRID_SEGMENTS: + case GL_TEXTURE_1D: + case GL_TEXTURE_2D: + case GL_POLYGON_OFFSET_UNITS: + case GL_CLIP_PLANE0: + case GL_CLIP_PLANE1: + case GL_CLIP_PLANE2: + case GL_CLIP_PLANE3: + case GL_CLIP_PLANE4: + case GL_CLIP_PLANE5: + case GL_LIGHT0: + case GL_LIGHT1: + case GL_LIGHT2: + case GL_LIGHT3: + case GL_LIGHT4: + case GL_LIGHT5: + case GL_LIGHT6: + case GL_LIGHT7: + case GL_BLEND_EQUATION: /* case GL_BLEND_EQUATION_EXT:*/ - case GL_CONVOLUTION_1D: - case GL_CONVOLUTION_2D: - case GL_SEPARABLE_2D: - case GL_MAX_CONVOLUTION_WIDTH: + case GL_CONVOLUTION_1D: + case GL_CONVOLUTION_2D: + case GL_SEPARABLE_2D: + case GL_MAX_CONVOLUTION_WIDTH: /* case GL_MAX_CONVOLUTION_WIDTH_EXT:*/ - case GL_MAX_CONVOLUTION_HEIGHT: + case GL_MAX_CONVOLUTION_HEIGHT: /* case GL_MAX_CONVOLUTION_HEIGHT_EXT:*/ - case GL_POST_CONVOLUTION_RED_SCALE: + case GL_POST_CONVOLUTION_RED_SCALE: /* case GL_POST_CONVOLUTION_RED_SCALE_EXT:*/ - case GL_POST_CONVOLUTION_GREEN_SCALE: + case GL_POST_CONVOLUTION_GREEN_SCALE: /* case GL_POST_CONVOLUTION_GREEN_SCALE_EXT:*/ - case GL_POST_CONVOLUTION_BLUE_SCALE: + case GL_POST_CONVOLUTION_BLUE_SCALE: /* case GL_POST_CONVOLUTION_BLUE_SCALE_EXT:*/ - case GL_POST_CONVOLUTION_ALPHA_SCALE: + case GL_POST_CONVOLUTION_ALPHA_SCALE: /* case GL_POST_CONVOLUTION_ALPHA_SCALE_EXT:*/ - case GL_POST_CONVOLUTION_RED_BIAS: + case GL_POST_CONVOLUTION_RED_BIAS: /* case GL_POST_CONVOLUTION_RED_BIAS_EXT:*/ - case GL_POST_CONVOLUTION_GREEN_BIAS: + case GL_POST_CONVOLUTION_GREEN_BIAS: /* case GL_POST_CONVOLUTION_GREEN_BIAS_EXT:*/ - case GL_POST_CONVOLUTION_BLUE_BIAS: + case GL_POST_CONVOLUTION_BLUE_BIAS: /* case GL_POST_CONVOLUTION_BLUE_BIAS_EXT:*/ - case GL_POST_CONVOLUTION_ALPHA_BIAS: + case GL_POST_CONVOLUTION_ALPHA_BIAS: /* case GL_POST_CONVOLUTION_ALPHA_BIAS_EXT:*/ - case GL_HISTOGRAM: - case GL_MINMAX: - case GL_POLYGON_OFFSET_FACTOR: - case GL_RESCALE_NORMAL: + case GL_HISTOGRAM: + case GL_MINMAX: + case GL_POLYGON_OFFSET_FACTOR: + case GL_RESCALE_NORMAL: /* case GL_RESCALE_NORMAL_EXT:*/ - case GL_TEXTURE_BINDING_1D: - case GL_TEXTURE_BINDING_2D: - case GL_TEXTURE_BINDING_3D: - case GL_PACK_SKIP_IMAGES: - case GL_PACK_IMAGE_HEIGHT: - case GL_UNPACK_SKIP_IMAGES: - case GL_UNPACK_IMAGE_HEIGHT: - case GL_TEXTURE_3D: - case GL_VERTEX_ARRAY: - case GL_NORMAL_ARRAY: - case GL_COLOR_ARRAY: - case GL_INDEX_ARRAY: - case GL_TEXTURE_COORD_ARRAY: - case GL_EDGE_FLAG_ARRAY: - case GL_VERTEX_ARRAY_SIZE: - case GL_VERTEX_ARRAY_TYPE: - case GL_VERTEX_ARRAY_STRIDE: - case GL_NORMAL_ARRAY_TYPE: - case GL_NORMAL_ARRAY_STRIDE: - case GL_COLOR_ARRAY_SIZE: - case GL_COLOR_ARRAY_TYPE: - case GL_COLOR_ARRAY_STRIDE: - case GL_INDEX_ARRAY_TYPE: - case GL_INDEX_ARRAY_STRIDE: - case GL_TEXTURE_COORD_ARRAY_SIZE: - case GL_TEXTURE_COORD_ARRAY_TYPE: - case GL_TEXTURE_COORD_ARRAY_STRIDE: - case GL_EDGE_FLAG_ARRAY_STRIDE: - case GL_MULTISAMPLE: + case GL_TEXTURE_BINDING_1D: + case GL_TEXTURE_BINDING_2D: + case GL_TEXTURE_BINDING_3D: + case GL_PACK_SKIP_IMAGES: + case GL_PACK_IMAGE_HEIGHT: + case GL_UNPACK_SKIP_IMAGES: + case GL_UNPACK_IMAGE_HEIGHT: + case GL_TEXTURE_3D: + case GL_VERTEX_ARRAY: + case GL_NORMAL_ARRAY: + case GL_COLOR_ARRAY: + case GL_INDEX_ARRAY: + case GL_TEXTURE_COORD_ARRAY: + case GL_EDGE_FLAG_ARRAY: + case GL_VERTEX_ARRAY_SIZE: + case GL_VERTEX_ARRAY_TYPE: + case GL_VERTEX_ARRAY_STRIDE: + case GL_NORMAL_ARRAY_TYPE: + case GL_NORMAL_ARRAY_STRIDE: + case GL_COLOR_ARRAY_SIZE: + case GL_COLOR_ARRAY_TYPE: + case GL_COLOR_ARRAY_STRIDE: + case GL_INDEX_ARRAY_TYPE: + case GL_INDEX_ARRAY_STRIDE: + case GL_TEXTURE_COORD_ARRAY_SIZE: + case GL_TEXTURE_COORD_ARRAY_TYPE: + case GL_TEXTURE_COORD_ARRAY_STRIDE: + case GL_EDGE_FLAG_ARRAY_STRIDE: + case GL_MULTISAMPLE: /* case GL_MULTISAMPLE_ARB:*/ - case GL_SAMPLE_ALPHA_TO_COVERAGE: + case GL_SAMPLE_ALPHA_TO_COVERAGE: /* case GL_SAMPLE_ALPHA_TO_COVERAGE_ARB:*/ - case GL_SAMPLE_ALPHA_TO_ONE: + case GL_SAMPLE_ALPHA_TO_ONE: /* case GL_SAMPLE_ALPHA_TO_ONE_ARB:*/ - case GL_SAMPLE_COVERAGE: + case GL_SAMPLE_COVERAGE: /* case GL_SAMPLE_COVERAGE_ARB:*/ - case GL_SAMPLE_BUFFERS: + case GL_SAMPLE_BUFFERS: /* case GL_SAMPLE_BUFFERS_ARB:*/ - case GL_SAMPLES: + case GL_SAMPLES: /* case GL_SAMPLES_ARB:*/ - case GL_SAMPLE_COVERAGE_VALUE: + case GL_SAMPLE_COVERAGE_VALUE: /* case GL_SAMPLE_COVERAGE_VALUE_ARB:*/ - case GL_SAMPLE_COVERAGE_INVERT: + case GL_SAMPLE_COVERAGE_INVERT: /* case GL_SAMPLE_COVERAGE_INVERT_ARB:*/ - case GL_COLOR_MATRIX_STACK_DEPTH: - case GL_MAX_COLOR_MATRIX_STACK_DEPTH: - case GL_POST_COLOR_MATRIX_RED_SCALE: - case GL_POST_COLOR_MATRIX_GREEN_SCALE: - case GL_POST_COLOR_MATRIX_BLUE_SCALE: - case GL_POST_COLOR_MATRIX_ALPHA_SCALE: - case GL_POST_COLOR_MATRIX_RED_BIAS: - case GL_POST_COLOR_MATRIX_GREEN_BIAS: - case GL_POST_COLOR_MATRIX_BLUE_BIAS: - case GL_POST_COLOR_MATRIX_ALPHA_BIAS: - case GL_BLEND_DST_RGB: - case GL_BLEND_SRC_RGB: - case GL_BLEND_DST_ALPHA: - case GL_BLEND_SRC_ALPHA: - case GL_COLOR_TABLE: - case GL_POST_CONVOLUTION_COLOR_TABLE: - case GL_POST_COLOR_MATRIX_COLOR_TABLE: - case GL_MAX_ELEMENTS_VERTICES: - case GL_MAX_ELEMENTS_INDICES: - case GL_CLIP_VOLUME_CLIPPING_HINT_EXT: - case GL_OCCLUSION_TEST_HP: - case GL_OCCLUSION_TEST_RESULT_HP: - case GL_LIGHT_MODEL_COLOR_CONTROL: - case GL_CURRENT_FOG_COORD: - case GL_FOG_COORDINATE_ARRAY_TYPE: - case GL_FOG_COORDINATE_ARRAY_STRIDE: - case GL_FOG_COORD_ARRAY: - case GL_COLOR_SUM_ARB: - case GL_SECONDARY_COLOR_ARRAY_SIZE: - case GL_SECONDARY_COLOR_ARRAY_TYPE: - case GL_SECONDARY_COLOR_ARRAY_STRIDE: - case GL_SECONDARY_COLOR_ARRAY: - case GL_ACTIVE_TEXTURE: + case GL_COLOR_MATRIX_STACK_DEPTH: + case GL_MAX_COLOR_MATRIX_STACK_DEPTH: + case GL_POST_COLOR_MATRIX_RED_SCALE: + case GL_POST_COLOR_MATRIX_GREEN_SCALE: + case GL_POST_COLOR_MATRIX_BLUE_SCALE: + case GL_POST_COLOR_MATRIX_ALPHA_SCALE: + case GL_POST_COLOR_MATRIX_RED_BIAS: + case GL_POST_COLOR_MATRIX_GREEN_BIAS: + case GL_POST_COLOR_MATRIX_BLUE_BIAS: + case GL_POST_COLOR_MATRIX_ALPHA_BIAS: + case GL_BLEND_DST_RGB: + case GL_BLEND_SRC_RGB: + case GL_BLEND_DST_ALPHA: + case GL_BLEND_SRC_ALPHA: + case GL_COLOR_TABLE: + case GL_POST_CONVOLUTION_COLOR_TABLE: + case GL_POST_COLOR_MATRIX_COLOR_TABLE: + case GL_MAX_ELEMENTS_VERTICES: + case GL_MAX_ELEMENTS_INDICES: + case GL_CLIP_VOLUME_CLIPPING_HINT_EXT: + case GL_OCCLUSION_TEST_HP: + case GL_OCCLUSION_TEST_RESULT_HP: + case GL_LIGHT_MODEL_COLOR_CONTROL: + case GL_CURRENT_FOG_COORD: + case GL_FOG_COORDINATE_ARRAY_TYPE: + case GL_FOG_COORDINATE_ARRAY_STRIDE: + case GL_FOG_COORD_ARRAY: + case GL_COLOR_SUM_ARB: + case GL_SECONDARY_COLOR_ARRAY_SIZE: + case GL_SECONDARY_COLOR_ARRAY_TYPE: + case GL_SECONDARY_COLOR_ARRAY_STRIDE: + case GL_SECONDARY_COLOR_ARRAY: + case GL_ACTIVE_TEXTURE: /* case GL_ACTIVE_TEXTURE_ARB:*/ - case GL_CLIENT_ACTIVE_TEXTURE: + case GL_CLIENT_ACTIVE_TEXTURE: /* case GL_CLIENT_ACTIVE_TEXTURE_ARB:*/ - case GL_MAX_TEXTURE_UNITS: + case GL_MAX_TEXTURE_UNITS: /* case GL_MAX_TEXTURE_UNITS_ARB:*/ - case GL_TEXTURE_COMPRESSION_HINT: + case GL_TEXTURE_COMPRESSION_HINT: /* case GL_TEXTURE_COMPRESSION_HINT_ARB:*/ - case GL_TEXTURE_RECTANGLE_ARB: + case GL_TEXTURE_RECTANGLE_ARB: /* case GL_TEXTURE_RECTANGLE_NV:*/ - case GL_TEXTURE_BINDING_RECTANGLE_ARB: + case GL_TEXTURE_BINDING_RECTANGLE_ARB: /* case GL_TEXTURE_BINDING_RECTANGLE_NV:*/ - case GL_MAX_RECTANGLE_TEXTURE_SIZE_ARB: + case GL_MAX_RECTANGLE_TEXTURE_SIZE_ARB: /* case GL_MAX_RECTANGLE_TEXTURE_SIZE_NV:*/ - case GL_MAX_TEXTURE_LOD_BIAS: - case GL_MAX_SHININESS_NV: - case GL_MAX_SPOT_EXPONENT_NV: - case GL_TEXTURE_CUBE_MAP: + case GL_MAX_TEXTURE_LOD_BIAS: + case GL_MAX_TEXTURE_MAX_ANISOTROPY_EXT: + case GL_MAX_SHININESS_NV: + case GL_MAX_SPOT_EXPONENT_NV: + case GL_TEXTURE_CUBE_MAP: /* case GL_TEXTURE_CUBE_MAP_ARB:*/ - case GL_TEXTURE_BINDING_CUBE_MAP: + case GL_TEXTURE_BINDING_CUBE_MAP: /* case GL_TEXTURE_BINDING_CUBE_MAP_ARB:*/ - case GL_MAX_CUBE_MAP_TEXTURE_SIZE: + case GL_MAX_CUBE_MAP_TEXTURE_SIZE: /* case GL_MAX_CUBE_MAP_TEXTURE_SIZE_ARB:*/ - case GL_MULTISAMPLE_FILTER_HINT_NV: - case GL_FOG_DISTANCE_MODE_NV: - case GL_VERTEX_PROGRAM_ARB: - case GL_MAX_PROGRAM_MATRIX_STACK_DEPTH_ARB: - case GL_MAX_PROGRAM_MATRICES_ARB: - case GL_CURRENT_MATRIX_STACK_DEPTH_ARB: - case GL_VERTEX_PROGRAM_POINT_SIZE_ARB: - case GL_VERTEX_PROGRAM_TWO_SIDE_ARB: - case GL_PROGRAM_ERROR_POSITION_ARB: - case GL_DEPTH_CLAMP_NV: - case GL_NUM_COMPRESSED_TEXTURE_FORMATS: + case GL_MULTISAMPLE_FILTER_HINT_NV: + case GL_FOG_DISTANCE_MODE_NV: + case GL_VERTEX_PROGRAM_ARB: + case GL_MAX_PROGRAM_MATRIX_STACK_DEPTH_ARB: + case GL_MAX_PROGRAM_MATRICES_ARB: + case GL_CURRENT_MATRIX_STACK_DEPTH_ARB: + case GL_VERTEX_PROGRAM_POINT_SIZE_ARB: + case GL_VERTEX_PROGRAM_TWO_SIDE_ARB: + case GL_PROGRAM_ERROR_POSITION_ARB: + case GL_DEPTH_CLAMP_NV: + case GL_NUM_COMPRESSED_TEXTURE_FORMATS: /* case GL_NUM_TEXTURE_COMPRESSED_FORMATS_ARB:*/ - case GL_MAX_VERTEX_UNITS_ARB: - case GL_ACTIVE_VERTEX_UNITS_ARB: - case GL_WEIGHT_SUM_UNITY_ARB: - case GL_VERTEX_BLEND_ARB: - case GL_CURRENT_WEIGHT_ARB: - case GL_WEIGHT_ARRAY_TYPE_ARB: - case GL_WEIGHT_ARRAY_STRIDE_ARB: - case GL_WEIGHT_ARRAY_SIZE_ARB: - case GL_WEIGHT_ARRAY_ARB: - case GL_PACK_INVERT_MESA: - case GL_FRAGMENT_PROGRAM_ARB: - case GL_MAX_DRAW_BUFFERS_ARB: + case GL_MAX_VERTEX_UNITS_ARB: + case GL_ACTIVE_VERTEX_UNITS_ARB: + case GL_WEIGHT_SUM_UNITY_ARB: + case GL_VERTEX_BLEND_ARB: + case GL_CURRENT_WEIGHT_ARB: + case GL_WEIGHT_ARRAY_TYPE_ARB: + case GL_WEIGHT_ARRAY_STRIDE_ARB: + case GL_WEIGHT_ARRAY_SIZE_ARB: + case GL_WEIGHT_ARRAY_ARB: + case GL_PACK_INVERT_MESA: + case GL_FRAGMENT_PROGRAM_ARB: + case GL_MAX_DRAW_BUFFERS_ARB: /* case GL_MAX_DRAW_BUFFERS_ATI:*/ - case GL_DRAW_BUFFER0_ARB: + case GL_DRAW_BUFFER0_ARB: /* case GL_DRAW_BUFFER0_ATI:*/ - case GL_DRAW_BUFFER1_ARB: + case GL_DRAW_BUFFER1_ARB: /* case GL_DRAW_BUFFER1_ATI:*/ - case GL_DRAW_BUFFER2_ARB: + case GL_DRAW_BUFFER2_ARB: /* case GL_DRAW_BUFFER2_ATI:*/ - case GL_DRAW_BUFFER3_ARB: + case GL_DRAW_BUFFER3_ARB: /* case GL_DRAW_BUFFER3_ATI:*/ - case GL_DRAW_BUFFER4_ARB: + case GL_DRAW_BUFFER4_ARB: /* case GL_DRAW_BUFFER4_ATI:*/ - case GL_DRAW_BUFFER5_ARB: + case GL_DRAW_BUFFER5_ARB: /* case GL_DRAW_BUFFER5_ATI:*/ - case GL_DRAW_BUFFER6_ARB: + case GL_DRAW_BUFFER6_ARB: /* case GL_DRAW_BUFFER6_ATI:*/ - case GL_DRAW_BUFFER7_ARB: + case GL_DRAW_BUFFER7_ARB: /* case GL_DRAW_BUFFER7_ATI:*/ - case GL_DRAW_BUFFER8_ARB: + case GL_DRAW_BUFFER8_ARB: /* case GL_DRAW_BUFFER8_ATI:*/ - case GL_DRAW_BUFFER9_ARB: + case GL_DRAW_BUFFER9_ARB: /* case GL_DRAW_BUFFER9_ATI:*/ - case GL_DRAW_BUFFER10_ARB: + case GL_DRAW_BUFFER10_ARB: /* case GL_DRAW_BUFFER10_ATI:*/ - case GL_DRAW_BUFFER11_ARB: + case GL_DRAW_BUFFER11_ARB: /* case GL_DRAW_BUFFER11_ATI:*/ - case GL_DRAW_BUFFER12_ARB: + case GL_DRAW_BUFFER12_ARB: /* case GL_DRAW_BUFFER12_ATI:*/ - case GL_DRAW_BUFFER13_ARB: + case GL_DRAW_BUFFER13_ARB: /* case GL_DRAW_BUFFER13_ATI:*/ - case GL_DRAW_BUFFER14_ARB: + case GL_DRAW_BUFFER14_ARB: /* case GL_DRAW_BUFFER14_ATI:*/ - case GL_DRAW_BUFFER15_ARB: + case GL_DRAW_BUFFER15_ARB: /* case GL_DRAW_BUFFER15_ATI:*/ - case GL_BLEND_EQUATION_ALPHA_EXT: - case GL_MATRIX_PALETTE_ARB: - case GL_MAX_MATRIX_PALETTE_STACK_DEPTH_ARB: - case GL_MAX_PALETTE_MATRICES_ARB: - case GL_CURRENT_PALETTE_MATRIX_ARB: - case GL_MATRIX_INDEX_ARRAY_ARB: - case GL_CURRENT_MATRIX_INDEX_ARB: - case GL_MATRIX_INDEX_ARRAY_SIZE_ARB: - case GL_MATRIX_INDEX_ARRAY_TYPE_ARB: - case GL_MATRIX_INDEX_ARRAY_STRIDE_ARB: - case GL_POINT_SPRITE_ARB: + case GL_BLEND_EQUATION_ALPHA_EXT: + case GL_MATRIX_PALETTE_ARB: + case GL_MAX_MATRIX_PALETTE_STACK_DEPTH_ARB: + case GL_MAX_PALETTE_MATRICES_ARB: + case GL_CURRENT_PALETTE_MATRIX_ARB: + case GL_MATRIX_INDEX_ARRAY_ARB: + case GL_CURRENT_MATRIX_INDEX_ARB: + case GL_MATRIX_INDEX_ARRAY_SIZE_ARB: + case GL_MATRIX_INDEX_ARRAY_TYPE_ARB: + case GL_MATRIX_INDEX_ARRAY_STRIDE_ARB: + case GL_POINT_SPRITE_ARB: /* case GL_POINT_SPRITE_NV:*/ - case GL_POINT_SPRITE_R_MODE_NV: - case GL_MAX_VERTEX_ATTRIBS_ARB: - case GL_DEPTH_BOUNDS_TEST_EXT: - case GL_STENCIL_TEST_TWO_SIDE_EXT: - case GL_ACTIVE_STENCIL_FACE_EXT: - case GL_RASTER_POSITION_UNCLIPPED_IBM: - return 1; - case GL_SMOOTH_POINT_SIZE_RANGE: - case GL_LINE_WIDTH_RANGE: - case GL_POLYGON_MODE: - case GL_DEPTH_RANGE: - case GL_MAX_VIEWPORT_DIMS: - case GL_MAP1_GRID_DOMAIN: - case GL_MAP2_GRID_SEGMENTS: - case GL_ALIASED_POINT_SIZE_RANGE: - case GL_ALIASED_LINE_WIDTH_RANGE: - case GL_DEPTH_BOUNDS_EXT: - return 2; - case GL_CURRENT_NORMAL: - return 3; - case GL_CURRENT_COLOR: - case GL_CURRENT_TEXTURE_COORDS: - case GL_CURRENT_RASTER_COLOR: - case GL_CURRENT_RASTER_TEXTURE_COORDS: - case GL_CURRENT_RASTER_POSITION: - case GL_LIGHT_MODEL_AMBIENT: - case GL_FOG_COLOR: - case GL_ACCUM_CLEAR_VALUE: - case GL_VIEWPORT: - case GL_SCISSOR_BOX: - case GL_COLOR_CLEAR_VALUE: - case GL_COLOR_WRITEMASK: - case GL_MAP2_GRID_DOMAIN: - case GL_BLEND_COLOR: + case GL_POINT_SPRITE_R_MODE_NV: + case GL_MAX_VERTEX_ATTRIBS_ARB: + case GL_DEPTH_BOUNDS_TEST_EXT: + case GL_STENCIL_TEST_TWO_SIDE_EXT: + case GL_ACTIVE_STENCIL_FACE_EXT: + case GL_RASTER_POSITION_UNCLIPPED_IBM: + return 1; + case GL_SMOOTH_POINT_SIZE_RANGE: + case GL_LINE_WIDTH_RANGE: + case GL_POLYGON_MODE: + case GL_DEPTH_RANGE: + case GL_MAX_VIEWPORT_DIMS: + case GL_MAP1_GRID_DOMAIN: + case GL_MAP2_GRID_SEGMENTS: + case GL_ALIASED_POINT_SIZE_RANGE: + case GL_ALIASED_LINE_WIDTH_RANGE: + case GL_DEPTH_BOUNDS_EXT: + return 2; + case GL_CURRENT_NORMAL: + return 3; + case GL_CURRENT_COLOR: + case GL_CURRENT_TEXTURE_COORDS: + case GL_CURRENT_RASTER_COLOR: + case GL_CURRENT_RASTER_TEXTURE_COORDS: + case GL_CURRENT_RASTER_POSITION: + case GL_LIGHT_MODEL_AMBIENT: + case GL_FOG_COLOR: + case GL_ACCUM_CLEAR_VALUE: + case GL_VIEWPORT: + case GL_SCISSOR_BOX: + case GL_COLOR_CLEAR_VALUE: + case GL_COLOR_WRITEMASK: + case GL_MAP2_GRID_DOMAIN: + case GL_BLEND_COLOR: /* case GL_BLEND_COLOR_EXT:*/ - case GL_CURRENT_SECONDARY_COLOR: - return 4; - case GL_MODELVIEW_MATRIX: - case GL_PROJECTION_MATRIX: - case GL_TEXTURE_MATRIX: - case GL_MODELVIEW0_ARB: - case GL_COLOR_MATRIX: - case GL_MODELVIEW1_ARB: - case GL_CURRENT_MATRIX_ARB: - case GL_MODELVIEW2_ARB: - case GL_MODELVIEW3_ARB: - case GL_MODELVIEW4_ARB: - case GL_MODELVIEW5_ARB: - case GL_MODELVIEW6_ARB: - case GL_MODELVIEW7_ARB: - case GL_MODELVIEW8_ARB: - case GL_MODELVIEW9_ARB: - case GL_MODELVIEW10_ARB: - case GL_MODELVIEW11_ARB: - case GL_MODELVIEW12_ARB: - case GL_MODELVIEW13_ARB: - case GL_MODELVIEW14_ARB: - case GL_MODELVIEW15_ARB: - case GL_MODELVIEW16_ARB: - case GL_MODELVIEW17_ARB: - case GL_MODELVIEW18_ARB: - case GL_MODELVIEW19_ARB: - case GL_MODELVIEW20_ARB: - case GL_MODELVIEW21_ARB: - case GL_MODELVIEW22_ARB: - case GL_MODELVIEW23_ARB: - case GL_MODELVIEW24_ARB: - case GL_MODELVIEW25_ARB: - case GL_MODELVIEW26_ARB: - case GL_MODELVIEW27_ARB: - case GL_MODELVIEW28_ARB: - case GL_MODELVIEW29_ARB: - case GL_MODELVIEW30_ARB: - case GL_MODELVIEW31_ARB: - case GL_TRANSPOSE_CURRENT_MATRIX_ARB: - return 16; - case GL_FOG_COORDINATE_SOURCE: - case GL_COMPRESSED_TEXTURE_FORMATS: - return __glGetBooleanv_variable_size( e ); - default: return 0; + case GL_CURRENT_SECONDARY_COLOR: + return 4; + case GL_MODELVIEW_MATRIX: + case GL_PROJECTION_MATRIX: + case GL_TEXTURE_MATRIX: + case GL_MODELVIEW0_ARB: + case GL_COLOR_MATRIX: + case GL_MODELVIEW1_ARB: + case GL_CURRENT_MATRIX_ARB: + case GL_MODELVIEW2_ARB: + case GL_MODELVIEW3_ARB: + case GL_MODELVIEW4_ARB: + case GL_MODELVIEW5_ARB: + case GL_MODELVIEW6_ARB: + case GL_MODELVIEW7_ARB: + case GL_MODELVIEW8_ARB: + case GL_MODELVIEW9_ARB: + case GL_MODELVIEW10_ARB: + case GL_MODELVIEW11_ARB: + case GL_MODELVIEW12_ARB: + case GL_MODELVIEW13_ARB: + case GL_MODELVIEW14_ARB: + case GL_MODELVIEW15_ARB: + case GL_MODELVIEW16_ARB: + case GL_MODELVIEW17_ARB: + case GL_MODELVIEW18_ARB: + case GL_MODELVIEW19_ARB: + case GL_MODELVIEW20_ARB: + case GL_MODELVIEW21_ARB: + case GL_MODELVIEW22_ARB: + case GL_MODELVIEW23_ARB: + case GL_MODELVIEW24_ARB: + case GL_MODELVIEW25_ARB: + case GL_MODELVIEW26_ARB: + case GL_MODELVIEW27_ARB: + case GL_MODELVIEW28_ARB: + case GL_MODELVIEW29_ARB: + case GL_MODELVIEW30_ARB: + case GL_MODELVIEW31_ARB: + case GL_TRANSPOSE_CURRENT_MATRIX_ARB: + return 16; + case GL_FOG_COORDINATE_SOURCE: + case GL_COMPRESSED_TEXTURE_FORMATS: + return __glGetBooleanv_variable_size(e); + default: + return 0; } } INTERNAL PURE FASTCALL GLint -__glGetTexParameterfv_size( GLenum e ) +__glGetTexParameterfv_size(GLenum e) { - switch( e ) { - case GL_TEXTURE_MAG_FILTER: - case GL_TEXTURE_MIN_FILTER: - case GL_TEXTURE_WRAP_S: - case GL_TEXTURE_WRAP_T: - case GL_TEXTURE_PRIORITY: - case GL_TEXTURE_RESIDENT: - case GL_TEXTURE_WRAP_R: - case GL_TEXTURE_COMPARE_FAIL_VALUE_ARB: + switch (e) { + case GL_TEXTURE_MAG_FILTER: + case GL_TEXTURE_MIN_FILTER: + case GL_TEXTURE_WRAP_S: + case GL_TEXTURE_WRAP_T: + case GL_TEXTURE_PRIORITY: + case GL_TEXTURE_RESIDENT: + case GL_TEXTURE_WRAP_R: + case GL_TEXTURE_COMPARE_FAIL_VALUE_ARB: /* case GL_SHADOW_AMBIENT_SGIX:*/ - case GL_TEXTURE_MIN_LOD: - case GL_TEXTURE_MAX_LOD: - case GL_TEXTURE_BASE_LEVEL: - case GL_TEXTURE_MAX_LEVEL: - case GL_TEXTURE_CLIPMAP_FRAME_SGIX: - case GL_TEXTURE_LOD_BIAS_S_SGIX: - case GL_TEXTURE_LOD_BIAS_T_SGIX: - case GL_TEXTURE_LOD_BIAS_R_SGIX: - case GL_GENERATE_MIPMAP: + case GL_TEXTURE_MIN_LOD: + case GL_TEXTURE_MAX_LOD: + case GL_TEXTURE_BASE_LEVEL: + case GL_TEXTURE_MAX_LEVEL: + case GL_TEXTURE_CLIPMAP_FRAME_SGIX: + case GL_TEXTURE_LOD_BIAS_S_SGIX: + case GL_TEXTURE_LOD_BIAS_T_SGIX: + case GL_TEXTURE_LOD_BIAS_R_SGIX: + case GL_GENERATE_MIPMAP: /* case GL_GENERATE_MIPMAP_SGIS:*/ - case GL_TEXTURE_COMPARE_SGIX: - case GL_TEXTURE_COMPARE_OPERATOR_SGIX: - case GL_TEXTURE_MAX_CLAMP_S_SGIX: - case GL_TEXTURE_MAX_CLAMP_T_SGIX: - case GL_TEXTURE_MAX_CLAMP_R_SGIX: - case GL_TEXTURE_MAX_ANISOTROPY_EXT: - case GL_TEXTURE_LOD_BIAS: + case GL_TEXTURE_COMPARE_SGIX: + case GL_TEXTURE_COMPARE_OPERATOR_SGIX: + case GL_TEXTURE_MAX_CLAMP_S_SGIX: + case GL_TEXTURE_MAX_CLAMP_T_SGIX: + case GL_TEXTURE_MAX_CLAMP_R_SGIX: + case GL_TEXTURE_MAX_ANISOTROPY_EXT: + case GL_TEXTURE_LOD_BIAS: /* case GL_TEXTURE_LOD_BIAS_EXT:*/ - case GL_DEPTH_TEXTURE_MODE: + case GL_DEPTH_TEXTURE_MODE: /* case GL_DEPTH_TEXTURE_MODE_ARB:*/ - case GL_TEXTURE_COMPARE_MODE: + case GL_TEXTURE_COMPARE_MODE: /* case GL_TEXTURE_COMPARE_MODE_ARB:*/ - case GL_TEXTURE_COMPARE_FUNC: + case GL_TEXTURE_COMPARE_FUNC: /* case GL_TEXTURE_COMPARE_FUNC_ARB:*/ - case GL_TEXTURE_UNSIGNED_REMAP_MODE_NV: - return 1; - case GL_TEXTURE_CLIPMAP_CENTER_SGIX: - case GL_TEXTURE_CLIPMAP_OFFSET_SGIX: - return 2; - case GL_TEXTURE_CLIPMAP_VIRTUAL_DEPTH_SGIX: - return 3; - case GL_TEXTURE_BORDER_COLOR: - case GL_POST_TEXTURE_FILTER_BIAS_SGIX: - case GL_POST_TEXTURE_FILTER_SCALE_SGIX: - return 4; - default: return 0; + case GL_TEXTURE_UNSIGNED_REMAP_MODE_NV: + return 1; + case GL_TEXTURE_CLIPMAP_CENTER_SGIX: + case GL_TEXTURE_CLIPMAP_OFFSET_SGIX: + return 2; + case GL_TEXTURE_CLIPMAP_VIRTUAL_DEPTH_SGIX: + return 3; + case GL_TEXTURE_BORDER_COLOR: + case GL_POST_TEXTURE_FILTER_BIAS_SGIX: + case GL_POST_TEXTURE_FILTER_SCALE_SGIX: + return 4; + default: + return 0; } } INTERNAL PURE FASTCALL GLint -__glGetTexLevelParameterfv_size( GLenum e ) +__glGetTexLevelParameterfv_size(GLenum e) { - switch( e ) { - case GL_TEXTURE_WIDTH: - case GL_TEXTURE_HEIGHT: - case GL_TEXTURE_COMPONENTS: - case GL_TEXTURE_BORDER: - case GL_TEXTURE_RED_SIZE: + switch (e) { + case GL_TEXTURE_WIDTH: + case GL_TEXTURE_HEIGHT: + case GL_TEXTURE_COMPONENTS: + case GL_TEXTURE_BORDER: + case GL_TEXTURE_RED_SIZE: /* case GL_TEXTURE_RED_SIZE_EXT:*/ - case GL_TEXTURE_GREEN_SIZE: + case GL_TEXTURE_GREEN_SIZE: /* case GL_TEXTURE_GREEN_SIZE_EXT:*/ - case GL_TEXTURE_BLUE_SIZE: + case GL_TEXTURE_BLUE_SIZE: /* case GL_TEXTURE_BLUE_SIZE_EXT:*/ - case GL_TEXTURE_ALPHA_SIZE: + case GL_TEXTURE_ALPHA_SIZE: /* case GL_TEXTURE_ALPHA_SIZE_EXT:*/ - case GL_TEXTURE_LUMINANCE_SIZE: + case GL_TEXTURE_LUMINANCE_SIZE: /* case GL_TEXTURE_LUMINANCE_SIZE_EXT:*/ - case GL_TEXTURE_INTENSITY_SIZE: + case GL_TEXTURE_INTENSITY_SIZE: /* case GL_TEXTURE_INTENSITY_SIZE_EXT:*/ - case GL_TEXTURE_DEPTH: - case GL_TEXTURE_INDEX_SIZE_EXT: - case GL_TEXTURE_COMPRESSED_IMAGE_SIZE: + case GL_TEXTURE_DEPTH: + case GL_TEXTURE_INDEX_SIZE_EXT: + case GL_TEXTURE_COMPRESSED_IMAGE_SIZE: /* case GL_TEXTURE_COMPRESSED_IMAGE_SIZE_ARB:*/ - case GL_TEXTURE_COMPRESSED: + case GL_TEXTURE_COMPRESSED: /* case GL_TEXTURE_COMPRESSED_ARB:*/ - case GL_TEXTURE_DEPTH_SIZE: + case GL_TEXTURE_DEPTH_SIZE: /* case GL_TEXTURE_DEPTH_SIZE_ARB:*/ - return 1; - default: return 0; + return 1; + default: + return 0; } } INTERNAL PURE FASTCALL GLint -__glColorTableParameterfv_size( GLenum e ) +__glColorTableParameterfv_size(GLenum e) { - switch( e ) { - case GL_COLOR_TABLE_SCALE: - case GL_COLOR_TABLE_BIAS: - return 4; - default: return 0; + switch (e) { + case GL_COLOR_TABLE_SCALE: + case GL_COLOR_TABLE_BIAS: + return 4; + default: + return 0; } } INTERNAL PURE FASTCALL GLint -__glGetColorTableParameterfv_size( GLenum e ) +__glGetColorTableParameterfv_size(GLenum e) { - switch( e ) { - case GL_COLOR_TABLE_FORMAT: + switch (e) { + case GL_COLOR_TABLE_FORMAT: /* case GL_COLOR_TABLE_FORMAT_EXT:*/ - case GL_COLOR_TABLE_WIDTH: + case GL_COLOR_TABLE_WIDTH: /* case GL_COLOR_TABLE_WIDTH_EXT:*/ - case GL_COLOR_TABLE_RED_SIZE: + case GL_COLOR_TABLE_RED_SIZE: /* case GL_COLOR_TABLE_RED_SIZE_EXT:*/ - case GL_COLOR_TABLE_GREEN_SIZE: + case GL_COLOR_TABLE_GREEN_SIZE: /* case GL_COLOR_TABLE_GREEN_SIZE_EXT:*/ - case GL_COLOR_TABLE_BLUE_SIZE: + case GL_COLOR_TABLE_BLUE_SIZE: /* case GL_COLOR_TABLE_BLUE_SIZE_EXT:*/ - case GL_COLOR_TABLE_ALPHA_SIZE: + case GL_COLOR_TABLE_ALPHA_SIZE: /* case GL_COLOR_TABLE_ALPHA_SIZE_EXT:*/ - case GL_COLOR_TABLE_LUMINANCE_SIZE: + case GL_COLOR_TABLE_LUMINANCE_SIZE: /* case GL_COLOR_TABLE_LUMINANCE_SIZE_EXT:*/ - case GL_COLOR_TABLE_INTENSITY_SIZE: + case GL_COLOR_TABLE_INTENSITY_SIZE: /* case GL_COLOR_TABLE_INTENSITY_SIZE_EXT:*/ - return 1; - case GL_COLOR_TABLE_SCALE: - case GL_COLOR_TABLE_BIAS: - return 4; - default: return 0; + return 1; + case GL_COLOR_TABLE_SCALE: + case GL_COLOR_TABLE_BIAS: + return 4; + default: + return 0; } } INTERNAL PURE FASTCALL GLint -__glConvolutionParameterfv_size( GLenum e ) +__glConvolutionParameterfv_size(GLenum e) { - switch( e ) { - case GL_CONVOLUTION_BORDER_MODE: + switch (e) { + case GL_CONVOLUTION_BORDER_MODE: /* case GL_CONVOLUTION_BORDER_MODE_EXT:*/ - return 1; - case GL_CONVOLUTION_FILTER_SCALE: + return 1; + case GL_CONVOLUTION_FILTER_SCALE: /* case GL_CONVOLUTION_FILTER_SCALE_EXT:*/ - case GL_CONVOLUTION_FILTER_BIAS: + case GL_CONVOLUTION_FILTER_BIAS: /* case GL_CONVOLUTION_FILTER_BIAS_EXT:*/ - case GL_CONVOLUTION_BORDER_COLOR: + case GL_CONVOLUTION_BORDER_COLOR: /* case GL_CONVOLUTION_BORDER_COLOR_HP:*/ - return 4; - default: return 0; + return 4; + default: + return 0; } } INTERNAL PURE FASTCALL GLint -__glGetConvolutionParameterfv_size( GLenum e ) +__glGetConvolutionParameterfv_size(GLenum e) { - switch( e ) { - case GL_CONVOLUTION_BORDER_MODE: + switch (e) { + case GL_CONVOLUTION_BORDER_MODE: /* case GL_CONVOLUTION_BORDER_MODE_EXT:*/ - case GL_CONVOLUTION_FORMAT: + case GL_CONVOLUTION_FORMAT: /* case GL_CONVOLUTION_FORMAT_EXT:*/ - case GL_CONVOLUTION_WIDTH: + case GL_CONVOLUTION_WIDTH: /* case GL_CONVOLUTION_WIDTH_EXT:*/ - case GL_CONVOLUTION_HEIGHT: + case GL_CONVOLUTION_HEIGHT: /* case GL_CONVOLUTION_HEIGHT_EXT:*/ - case GL_MAX_CONVOLUTION_WIDTH: + case GL_MAX_CONVOLUTION_WIDTH: /* case GL_MAX_CONVOLUTION_WIDTH_EXT:*/ - case GL_MAX_CONVOLUTION_HEIGHT: + case GL_MAX_CONVOLUTION_HEIGHT: /* case GL_MAX_CONVOLUTION_HEIGHT_EXT:*/ - return 1; - case GL_CONVOLUTION_FILTER_SCALE: + return 1; + case GL_CONVOLUTION_FILTER_SCALE: /* case GL_CONVOLUTION_FILTER_SCALE_EXT:*/ - case GL_CONVOLUTION_FILTER_BIAS: + case GL_CONVOLUTION_FILTER_BIAS: /* case GL_CONVOLUTION_FILTER_BIAS_EXT:*/ - case GL_CONVOLUTION_BORDER_COLOR: + case GL_CONVOLUTION_BORDER_COLOR: /* case GL_CONVOLUTION_BORDER_COLOR_HP:*/ - return 4; - default: return 0; + return 4; + default: + return 0; } } INTERNAL PURE FASTCALL GLint -__glGetHistogramParameterfv_size( GLenum e ) +__glGetHistogramParameterfv_size(GLenum e) { - switch( e ) { - case GL_HISTOGRAM_WIDTH: - case GL_HISTOGRAM_FORMAT: - case GL_HISTOGRAM_RED_SIZE: - case GL_HISTOGRAM_GREEN_SIZE: - case GL_HISTOGRAM_BLUE_SIZE: - case GL_HISTOGRAM_ALPHA_SIZE: - case GL_HISTOGRAM_LUMINANCE_SIZE: - case GL_HISTOGRAM_SINK: - return 1; - default: return 0; + switch (e) { + case GL_HISTOGRAM_WIDTH: + case GL_HISTOGRAM_FORMAT: + case GL_HISTOGRAM_RED_SIZE: + case GL_HISTOGRAM_GREEN_SIZE: + case GL_HISTOGRAM_BLUE_SIZE: + case GL_HISTOGRAM_ALPHA_SIZE: + case GL_HISTOGRAM_LUMINANCE_SIZE: + case GL_HISTOGRAM_SINK: + return 1; + default: + return 0; } } INTERNAL PURE FASTCALL GLint -__glGetMinmaxParameterfv_size( GLenum e ) +__glGetMinmaxParameterfv_size(GLenum e) { - switch( e ) { - case GL_MINMAX_FORMAT: - case GL_MINMAX_SINK: - return 1; - default: return 0; + switch (e) { + case GL_MINMAX_FORMAT: + case GL_MINMAX_SINK: + return 1; + default: + return 0; } } INTERNAL PURE FASTCALL GLint -__glGetProgramivARB_size( GLenum e ) +__glGetProgramivARB_size(GLenum e) { - switch( e ) { - case GL_PROGRAM_LENGTH_ARB: - case GL_PROGRAM_BINDING_ARB: - case GL_PROGRAM_ALU_INSTRUCTIONS_ARB: - case GL_PROGRAM_TEX_INSTRUCTIONS_ARB: - case GL_PROGRAM_TEX_INDIRECTIONS_ARB: - case GL_PROGRAM_NATIVE_ALU_INSTRUCTIONS_ARB: - case GL_PROGRAM_NATIVE_TEX_INSTRUCTIONS_ARB: - case GL_PROGRAM_NATIVE_TEX_INDIRECTIONS_ARB: - case GL_MAX_PROGRAM_ALU_INSTRUCTIONS_ARB: - case GL_MAX_PROGRAM_TEX_INSTRUCTIONS_ARB: - case GL_MAX_PROGRAM_TEX_INDIRECTIONS_ARB: - case GL_MAX_PROGRAM_NATIVE_ALU_INSTRUCTIONS_ARB: - case GL_MAX_PROGRAM_NATIVE_TEX_INSTRUCTIONS_ARB: - case GL_MAX_PROGRAM_NATIVE_TEX_INDIRECTIONS_ARB: - case GL_MAX_TEXTURE_COORDS_ARB: - case GL_MAX_TEXTURE_IMAGE_UNITS_ARB: - case GL_PROGRAM_FORMAT_ARB: - case GL_PROGRAM_INSTRUCTIONS_ARB: - case GL_MAX_PROGRAM_INSTRUCTIONS_ARB: - case GL_PROGRAM_NATIVE_INSTRUCTIONS_ARB: - case GL_MAX_PROGRAM_NATIVE_INSTRUCTIONS_ARB: - case GL_PROGRAM_TEMPORARIES_ARB: - case GL_MAX_PROGRAM_TEMPORARIES_ARB: - case GL_PROGRAM_NATIVE_TEMPORARIES_ARB: - case GL_MAX_PROGRAM_NATIVE_TEMPORARIES_ARB: - case GL_PROGRAM_PARAMETERS_ARB: - case GL_MAX_PROGRAM_PARAMETERS_ARB: - case GL_PROGRAM_NATIVE_PARAMETERS_ARB: - case GL_MAX_PROGRAM_NATIVE_PARAMETERS_ARB: - case GL_PROGRAM_ATTRIBS_ARB: - case GL_MAX_PROGRAM_ATTRIBS_ARB: - case GL_PROGRAM_NATIVE_ATTRIBS_ARB: - case GL_MAX_PROGRAM_NATIVE_ATTRIBS_ARB: - case GL_PROGRAM_ADDRESS_REGISTERS_ARB: - case GL_MAX_PROGRAM_ADDRESS_REGISTERS_ARB: - case GL_PROGRAM_NATIVE_ADDRESS_REGISTERS_ARB: - case GL_MAX_PROGRAM_NATIVE_ADDRESS_REGISTERS_ARB: - case GL_MAX_PROGRAM_LOCAL_PARAMETERS_ARB: - case GL_MAX_PROGRAM_ENV_PARAMETERS_ARB: - case GL_PROGRAM_UNDER_NATIVE_LIMITS_ARB: - case GL_MAX_PROGRAM_EXEC_INSTRUCTIONS_NV: - case GL_MAX_PROGRAM_CALL_DEPTH_NV: - case GL_MAX_PROGRAM_IF_DEPTH_NV: - case GL_MAX_PROGRAM_LOOP_DEPTH_NV: - case GL_MAX_PROGRAM_LOOP_COUNT_NV: - return 1; - default: return 0; + switch (e) { + case GL_PROGRAM_LENGTH_ARB: + case GL_PROGRAM_BINDING_ARB: + case GL_PROGRAM_ALU_INSTRUCTIONS_ARB: + case GL_PROGRAM_TEX_INSTRUCTIONS_ARB: + case GL_PROGRAM_TEX_INDIRECTIONS_ARB: + case GL_PROGRAM_NATIVE_ALU_INSTRUCTIONS_ARB: + case GL_PROGRAM_NATIVE_TEX_INSTRUCTIONS_ARB: + case GL_PROGRAM_NATIVE_TEX_INDIRECTIONS_ARB: + case GL_MAX_PROGRAM_ALU_INSTRUCTIONS_ARB: + case GL_MAX_PROGRAM_TEX_INSTRUCTIONS_ARB: + case GL_MAX_PROGRAM_TEX_INDIRECTIONS_ARB: + case GL_MAX_PROGRAM_NATIVE_ALU_INSTRUCTIONS_ARB: + case GL_MAX_PROGRAM_NATIVE_TEX_INSTRUCTIONS_ARB: + case GL_MAX_PROGRAM_NATIVE_TEX_INDIRECTIONS_ARB: + case GL_MAX_TEXTURE_COORDS_ARB: + case GL_MAX_TEXTURE_IMAGE_UNITS_ARB: + case GL_PROGRAM_FORMAT_ARB: + case GL_PROGRAM_INSTRUCTIONS_ARB: + case GL_MAX_PROGRAM_INSTRUCTIONS_ARB: + case GL_PROGRAM_NATIVE_INSTRUCTIONS_ARB: + case GL_MAX_PROGRAM_NATIVE_INSTRUCTIONS_ARB: + case GL_PROGRAM_TEMPORARIES_ARB: + case GL_MAX_PROGRAM_TEMPORARIES_ARB: + case GL_PROGRAM_NATIVE_TEMPORARIES_ARB: + case GL_MAX_PROGRAM_NATIVE_TEMPORARIES_ARB: + case GL_PROGRAM_PARAMETERS_ARB: + case GL_MAX_PROGRAM_PARAMETERS_ARB: + case GL_PROGRAM_NATIVE_PARAMETERS_ARB: + case GL_MAX_PROGRAM_NATIVE_PARAMETERS_ARB: + case GL_PROGRAM_ATTRIBS_ARB: + case GL_MAX_PROGRAM_ATTRIBS_ARB: + case GL_PROGRAM_NATIVE_ATTRIBS_ARB: + case GL_MAX_PROGRAM_NATIVE_ATTRIBS_ARB: + case GL_PROGRAM_ADDRESS_REGISTERS_ARB: + case GL_MAX_PROGRAM_ADDRESS_REGISTERS_ARB: + case GL_PROGRAM_NATIVE_ADDRESS_REGISTERS_ARB: + case GL_MAX_PROGRAM_NATIVE_ADDRESS_REGISTERS_ARB: + case GL_MAX_PROGRAM_LOCAL_PARAMETERS_ARB: + case GL_MAX_PROGRAM_ENV_PARAMETERS_ARB: + case GL_PROGRAM_UNDER_NATIVE_LIMITS_ARB: + case GL_MAX_PROGRAM_EXEC_INSTRUCTIONS_NV: + case GL_MAX_PROGRAM_CALL_DEPTH_NV: + case GL_MAX_PROGRAM_IF_DEPTH_NV: + case GL_MAX_PROGRAM_LOOP_DEPTH_NV: + case GL_MAX_PROGRAM_LOOP_COUNT_NV: + return 1; + default: + return 0; } } INTERNAL PURE FASTCALL GLint -__glGetVertexAttribdvARB_size( GLenum e ) +__glGetVertexAttribdvARB_size(GLenum e) { - switch( e ) { - case GL_VERTEX_PROGRAM_ARB: - case GL_VERTEX_ATTRIB_ARRAY_ENABLED_ARB: - case GL_VERTEX_ATTRIB_ARRAY_SIZE_ARB: - case GL_VERTEX_ATTRIB_ARRAY_STRIDE_ARB: - case GL_VERTEX_ATTRIB_ARRAY_TYPE_ARB: - case GL_CURRENT_VERTEX_ATTRIB_ARB: - return 1; - default: return 0; + switch (e) { + case GL_VERTEX_PROGRAM_ARB: + case GL_VERTEX_ATTRIB_ARRAY_ENABLED_ARB: + case GL_VERTEX_ATTRIB_ARRAY_SIZE_ARB: + case GL_VERTEX_ATTRIB_ARRAY_STRIDE_ARB: + case GL_VERTEX_ATTRIB_ARRAY_TYPE_ARB: + case GL_CURRENT_VERTEX_ATTRIB_ARB: + return 1; + default: + return 0; } } INTERNAL PURE FASTCALL GLint -__glGetQueryObjectivARB_size( GLenum e ) +__glGetQueryObjectivARB_size(GLenum e) { - switch( e ) { - case GL_QUERY_RESULT_ARB: - case GL_QUERY_RESULT_AVAILABLE_ARB: - return 1; - default: return 0; + switch (e) { + case GL_QUERY_RESULT_ARB: + case GL_QUERY_RESULT_AVAILABLE_ARB: + return 1; + default: + return 0; } } INTERNAL PURE FASTCALL GLint -__glGetQueryivARB_size( GLenum e ) +__glGetQueryivARB_size(GLenum e) { - switch( e ) { - case GL_QUERY_COUNTER_BITS_ARB: - case GL_CURRENT_QUERY_ARB: - return 1; - default: return 0; + switch (e) { + case GL_QUERY_COUNTER_BITS_ARB: + case GL_CURRENT_QUERY_ARB: + return 1; + default: + return 0; } } INTERNAL PURE FASTCALL GLint -__glPointParameterfvEXT_size( GLenum e ) +__glPointParameterfvEXT_size(GLenum e) { - switch( e ) { - case GL_POINT_SIZE_MIN: + switch (e) { + case GL_POINT_SIZE_MIN: /* case GL_POINT_SIZE_MIN_ARB:*/ /* case GL_POINT_SIZE_MIN_SGIS:*/ - case GL_POINT_SIZE_MAX: + case GL_POINT_SIZE_MAX: /* case GL_POINT_SIZE_MAX_ARB:*/ /* case GL_POINT_SIZE_MAX_SGIS:*/ - case GL_POINT_FADE_THRESHOLD_SIZE: + case GL_POINT_FADE_THRESHOLD_SIZE: /* case GL_POINT_FADE_THRESHOLD_SIZE_ARB:*/ /* case GL_POINT_FADE_THRESHOLD_SIZE_SGIS:*/ - case GL_POINT_SPRITE_R_MODE_NV: - case GL_POINT_SPRITE_COORD_ORIGIN: - return 1; - case GL_POINT_DISTANCE_ATTENUATION: + case GL_POINT_SPRITE_R_MODE_NV: + case GL_POINT_SPRITE_COORD_ORIGIN: + return 1; + case GL_POINT_DISTANCE_ATTENUATION: /* case GL_POINT_DISTANCE_ATTENUATION_ARB:*/ /* case GL_POINT_DISTANCE_ATTENUATION_SGIS:*/ - return 3; - default: return 0; + return 3; + default: + return 0; } } INTERNAL PURE FASTCALL GLint -__glGetProgramivNV_size( GLenum e ) +__glGetProgramivNV_size(GLenum e) { - switch( e ) { - case GL_PROGRAM_LENGTH_NV: - case GL_PROGRAM_TARGET_NV: - case GL_PROGRAM_RESIDENT_NV: - return 1; - default: return 0; + switch (e) { + case GL_PROGRAM_LENGTH_NV: + case GL_PROGRAM_TARGET_NV: + case GL_PROGRAM_RESIDENT_NV: + return 1; + default: + return 0; } } INTERNAL PURE FASTCALL GLint -__glGetVertexAttribdvNV_size( GLenum e ) +__glGetVertexAttribdvNV_size(GLenum e) { - switch( e ) { - case GL_ATTRIB_ARRAY_SIZE_NV: - case GL_ATTRIB_ARRAY_STRIDE_NV: - case GL_ATTRIB_ARRAY_TYPE_NV: - case GL_CURRENT_ATTRIB_NV: - return 1; - default: return 0; + switch (e) { + case GL_ATTRIB_ARRAY_SIZE_NV: + case GL_ATTRIB_ARRAY_STRIDE_NV: + case GL_ATTRIB_ARRAY_TYPE_NV: + case GL_CURRENT_ATTRIB_NV: + return 1; + default: + return 0; } } INTERNAL PURE FASTCALL GLint -__glGetFramebufferAttachmentParameterivEXT_size( GLenum e ) +__glGetFramebufferAttachmentParameterivEXT_size(GLenum e) { - switch( e ) { - case GL_FRAMEBUFFER_ATTACHMENT_OBJECT_TYPE_EXT: - case GL_FRAMEBUFFER_ATTACHMENT_OBJECT_NAME_EXT: - case GL_FRAMEBUFFER_ATTACHMENT_TEXTURE_LEVEL_EXT: - case GL_FRAMEBUFFER_ATTACHMENT_TEXTURE_CUBE_MAP_FACE_EXT: - case GL_FRAMEBUFFER_ATTACHMENT_TEXTURE_3D_ZOFFSET_EXT: - return 1; - default: return 0; + switch (e) { + case GL_FRAMEBUFFER_ATTACHMENT_OBJECT_TYPE_EXT: + case GL_FRAMEBUFFER_ATTACHMENT_OBJECT_NAME_EXT: + case GL_FRAMEBUFFER_ATTACHMENT_TEXTURE_LEVEL_EXT: + case GL_FRAMEBUFFER_ATTACHMENT_TEXTURE_CUBE_MAP_FACE_EXT: + case GL_FRAMEBUFFER_ATTACHMENT_TEXTURE_3D_ZOFFSET_EXT: + return 1; + default: + return 0; } } -ALIAS( Fogiv, Fogfv ) -ALIAS( Lightiv, Lightfv ) -ALIAS( LightModeliv, LightModelfv ) -ALIAS( Materialiv, Materialfv ) -ALIAS( TexParameteriv, TexParameterfv ) -ALIAS( TexEnviv, TexEnvfv ) -ALIAS( TexGenfv, TexGendv ) -ALIAS( TexGeniv, TexGendv ) -ALIAS( Map1f, Map1d ) -ALIAS( Map2f, Map2d ) -ALIAS( GetDoublev, GetBooleanv ) -ALIAS( GetFloatv, GetBooleanv ) -ALIAS( GetIntegerv, GetBooleanv ) -ALIAS( GetLightfv, Lightfv ) -ALIAS( GetLightiv, Lightfv ) -ALIAS( GetMaterialfv, Materialfv ) -ALIAS( GetMaterialiv, Materialfv ) -ALIAS( GetTexEnvfv, TexEnvfv ) -ALIAS( GetTexEnviv, TexEnvfv ) -ALIAS( GetTexGendv, TexGendv ) -ALIAS( GetTexGenfv, TexGendv ) -ALIAS( GetTexGeniv, TexGendv ) -ALIAS( GetTexParameteriv, GetTexParameterfv ) -ALIAS( GetTexLevelParameteriv, GetTexLevelParameterfv ) -ALIAS( ColorTableParameteriv, ColorTableParameterfv ) -ALIAS( GetColorTableParameteriv, GetColorTableParameterfv ) -ALIAS( ConvolutionParameteriv, ConvolutionParameterfv ) -ALIAS( GetConvolutionParameteriv, GetConvolutionParameterfv ) -ALIAS( GetHistogramParameteriv, GetHistogramParameterfv ) -ALIAS( GetMinmaxParameteriv, GetMinmaxParameterfv ) -ALIAS( GetVertexAttribfvARB, GetVertexAttribdvARB ) -ALIAS( GetVertexAttribivARB, GetVertexAttribdvARB ) -ALIAS( GetQueryObjectuivARB, GetQueryObjectivARB ) -ALIAS( GetColorTableParameterfvSGI, GetColorTableParameterfv ) -ALIAS( GetColorTableParameterivSGI, GetColorTableParameterfv ) -ALIAS( GetVertexAttribfvNV, GetVertexAttribdvNV ) -ALIAS( GetVertexAttribivNV, GetVertexAttribdvNV ) -ALIAS( PointParameterivNV, PointParameterfvEXT ) - +ALIAS(Fogiv, Fogfv) + ALIAS(Lightiv, Lightfv) + ALIAS(LightModeliv, LightModelfv) + ALIAS(Materialiv, Materialfv) + ALIAS(TexParameteriv, TexParameterfv) + ALIAS(TexEnviv, TexEnvfv) + ALIAS(TexGenfv, TexGendv) + ALIAS(TexGeniv, TexGendv) + ALIAS(Map1f, Map1d) + ALIAS(Map2f, Map2d) + ALIAS(GetDoublev, GetBooleanv) + ALIAS(GetFloatv, GetBooleanv) + ALIAS(GetIntegerv, GetBooleanv) + ALIAS(GetLightfv, Lightfv) + ALIAS(GetLightiv, Lightfv) + ALIAS(GetMaterialfv, Materialfv) + ALIAS(GetMaterialiv, Materialfv) + ALIAS(GetTexEnvfv, TexEnvfv) + ALIAS(GetTexEnviv, TexEnvfv) + ALIAS(GetTexGendv, TexGendv) + ALIAS(GetTexGenfv, TexGendv) + ALIAS(GetTexGeniv, TexGendv) + ALIAS(GetTexParameteriv, GetTexParameterfv) + ALIAS(GetTexLevelParameteriv, GetTexLevelParameterfv) + ALIAS(ColorTableParameteriv, ColorTableParameterfv) + ALIAS(GetColorTableParameteriv, GetColorTableParameterfv) + ALIAS(ConvolutionParameteriv, ConvolutionParameterfv) + ALIAS(GetConvolutionParameteriv, GetConvolutionParameterfv) + ALIAS(GetHistogramParameteriv, GetHistogramParameterfv) + ALIAS(GetMinmaxParameteriv, GetMinmaxParameterfv) + ALIAS(GetVertexAttribfvARB, GetVertexAttribdvARB) + ALIAS(GetVertexAttribivARB, GetVertexAttribdvARB) + ALIAS(GetQueryObjectuivARB, GetQueryObjectivARB) + ALIAS(GetVertexAttribfvNV, GetVertexAttribdvNV) + ALIAS(GetVertexAttribivNV, GetVertexAttribdvNV) + ALIAS(PointParameterivNV, PointParameterfvEXT) # undef PURE # undef FASTCALL # undef INTERNAL diff --git a/GL/glx/indirect_size_get.h b/GL/glx/indirect_size_get.h index c6f9532ce..4fcb55b4e 100644 --- a/GL/glx/indirect_size_get.h +++ b/GL/glx/indirect_size_get.h @@ -73,8 +73,10 @@ extern INTERNAL PURE FASTCALL GLint __glGetTexLevelParameterfv_size(GLenum); extern INTERNAL PURE FASTCALL GLint __glGetTexLevelParameteriv_size(GLenum); extern INTERNAL PURE FASTCALL GLint __glGetColorTableParameterfv_size(GLenum); extern INTERNAL PURE FASTCALL GLint __glGetColorTableParameteriv_size(GLenum); -extern INTERNAL PURE FASTCALL GLint __glGetConvolutionParameterfv_size(GLenum); -extern INTERNAL PURE FASTCALL GLint __glGetConvolutionParameteriv_size(GLenum); +extern INTERNAL PURE FASTCALL GLint +__glGetConvolutionParameterfv_size(GLenum); +extern INTERNAL PURE FASTCALL GLint +__glGetConvolutionParameteriv_size(GLenum); extern INTERNAL PURE FASTCALL GLint __glGetHistogramParameterfv_size(GLenum); extern INTERNAL PURE FASTCALL GLint __glGetHistogramParameteriv_size(GLenum); extern INTERNAL PURE FASTCALL GLint __glGetMinmaxParameterfv_size(GLenum); @@ -86,13 +88,12 @@ extern INTERNAL PURE FASTCALL GLint __glGetVertexAttribivARB_size(GLenum); extern INTERNAL PURE FASTCALL GLint __glGetQueryObjectivARB_size(GLenum); extern INTERNAL PURE FASTCALL GLint __glGetQueryObjectuivARB_size(GLenum); extern INTERNAL PURE FASTCALL GLint __glGetQueryivARB_size(GLenum); -extern INTERNAL PURE FASTCALL GLint __glGetColorTableParameterfvSGI_size(GLenum); -extern INTERNAL PURE FASTCALL GLint __glGetColorTableParameterivSGI_size(GLenum); extern INTERNAL PURE FASTCALL GLint __glGetProgramivNV_size(GLenum); extern INTERNAL PURE FASTCALL GLint __glGetVertexAttribdvNV_size(GLenum); extern INTERNAL PURE FASTCALL GLint __glGetVertexAttribfvNV_size(GLenum); extern INTERNAL PURE FASTCALL GLint __glGetVertexAttribivNV_size(GLenum); -extern INTERNAL PURE FASTCALL GLint __glGetFramebufferAttachmentParameterivEXT_size(GLenum); +extern INTERNAL PURE FASTCALL GLint +__glGetFramebufferAttachmentParameterivEXT_size(GLenum); # undef PURE # undef FASTCALL diff --git a/GL/glx/indirect_table.c b/GL/glx/indirect_table.c index 8671a8475..a6fd3a39a 100644 --- a/GL/glx/indirect_table.c +++ b/GL/glx/indirect_table.c @@ -163,7 +163,7 @@ static const void *Single_function_table[112][2] = { /* [ 85] = 141 */ {__glXDisp_IsList, __glXDispSwap_IsList}, /* [ 86] = 142 */ {__glXDisp_Flush, __glXDispSwap_Flush}, /* [ 87] = 143 */ {__glXDisp_AreTexturesResident, __glXDispSwap_AreTexturesResident}, - /* [ 88] = 144 */ {NULL, NULL}, + /* [ 88] = 144 */ {__glXDisp_DeleteTextures, __glXDispSwap_DeleteTextures}, /* [ 89] = 145 */ {__glXDisp_GenTextures, __glXDispSwap_GenTextures}, /* [ 90] = 146 */ {__glXDisp_IsTexture, __glXDispSwap_IsTexture}, /* [ 91] = 147 */ {__glXDisp_GetColorTable, __glXDispSwap_GetColorTable}, @@ -199,7 +199,7 @@ const struct __glXDispatchInfo Single_dispatch_info = { /*****************************************************************/ /* tree depth = 8 */ -static const int_fast16_t Render_dispatch_tree[96] = { +static const int_fast16_t Render_dispatch_tree[95] = { /* [0] -> opcode range [0, 8192], node depth 1 */ 2, 5, @@ -294,59 +294,52 @@ static const int_fast16_t Render_dispatch_tree[96] = { EMPTY_LEAF, /* [63] -> opcode range [4096, 4352], node depth 5 */ - 3, + 4, LEAF(264), - 72, - 78, + LEAF(280), + 80, + EMPTY_LEAF, + EMPTY_LEAF, LEAF(296), - 81, - EMPTY_LEAF, - 84, - 90, - - /* [72] -> opcode range [4128, 4160], node depth 6 */ - 1, - 75, - EMPTY_LEAF, - - /* [75] -> opcode range [4128, 4144], node depth 7 */ - 1, + LEAF(312), LEAF(328), + LEAF(344), + EMPTY_LEAF, + 83, + 86, + EMPTY_LEAF, + 89, + 92, EMPTY_LEAF, - /* [78] -> opcode range [4160, 4192], node depth 6 */ + /* [80] -> opcode range [4128, 4144], node depth 6 */ 1, - EMPTY_LEAF, - LEAF(336), - - /* [81] -> opcode range [4224, 4256], node depth 6 */ - 1, - LEAF(352), + LEAF(360), EMPTY_LEAF, - /* [84] -> opcode range [4288, 4320], node depth 6 */ - 1, - EMPTY_LEAF, - 87, - - /* [87] -> opcode range [4304, 4320], node depth 7 */ + /* [83] -> opcode range [4256, 4272], node depth 6 */ 1, EMPTY_LEAF, LEAF(368), - /* [90] -> opcode range [4320, 4352], node depth 6 */ - 1, - 93, - EMPTY_LEAF, - - /* [93] -> opcode range [4320, 4336], node depth 7 */ + /* [86] -> opcode range [4272, 4288], node depth 6 */ 1, LEAF(376), EMPTY_LEAF, + /* [89] -> opcode range [4304, 4320], node depth 6 */ + 1, + EMPTY_LEAF, + LEAF(384), + + /* [92] -> opcode range [4320, 4336], node depth 6 */ + 1, + LEAF(392), + EMPTY_LEAF, + }; -static const void *Render_function_table[384][2] = { +static const void *Render_function_table[400][2] = { /* [ 0] = 0 */ {NULL, NULL}, /* [ 1] = 1 */ {__glXDisp_CallList, __glXDispSwap_CallList}, /* [ 2] = 2 */ {__glXDisp_CallLists, __glXDispSwap_CallLists}, @@ -643,97 +636,113 @@ static const void *Render_function_table[384][2] = { /* [ 293] = 4125 */ {__glXDisp_FogCoorddvEXT, __glXDispSwap_FogCoorddvEXT}, /* [ 294] = 4126 */ {__glXDisp_SecondaryColor3bvEXT, __glXDispSwap_SecondaryColor3bvEXT}, /* [ 295] = 4127 */ {__glXDisp_SecondaryColor3svEXT, __glXDispSwap_SecondaryColor3svEXT}, - /* [ 296] = 4192 */ {__glXDisp_VertexAttrib4svARB, __glXDispSwap_VertexAttrib4svARB}, - /* [ 297] = 4193 */ {__glXDisp_VertexAttrib1fvARB, __glXDispSwap_VertexAttrib1fvARB}, - /* [ 298] = 4194 */ {__glXDisp_VertexAttrib2fvARB, __glXDispSwap_VertexAttrib2fvARB}, - /* [ 299] = 4195 */ {__glXDisp_VertexAttrib3fvNV, __glXDispSwap_VertexAttrib3fvNV}, - /* [ 300] = 4196 */ {__glXDisp_VertexAttrib4fvARB, __glXDispSwap_VertexAttrib4fvARB}, - /* [ 301] = 4197 */ {__glXDisp_VertexAttrib1dvARB, __glXDispSwap_VertexAttrib1dvARB}, - /* [ 302] = 4198 */ {__glXDisp_VertexAttrib2dvARB, __glXDispSwap_VertexAttrib2dvARB}, - /* [ 303] = 4199 */ {__glXDisp_VertexAttrib3dvNV, __glXDispSwap_VertexAttrib3dvNV}, - /* [ 304] = 4200 */ {__glXDisp_VertexAttrib4dvNV, __glXDispSwap_VertexAttrib4dvNV}, - /* [ 305] = 4201 */ {__glXDisp_VertexAttrib4NubvARB, __glXDispSwap_VertexAttrib4NubvARB}, - /* [ 306] = 4202 */ {__glXDisp_VertexAttribs1svNV, __glXDispSwap_VertexAttribs1svNV}, - /* [ 307] = 4203 */ {__glXDisp_VertexAttribs2svNV, __glXDispSwap_VertexAttribs2svNV}, - /* [ 308] = 4204 */ {__glXDisp_VertexAttribs3svNV, __glXDispSwap_VertexAttribs3svNV}, - /* [ 309] = 4205 */ {__glXDisp_VertexAttribs4svNV, __glXDispSwap_VertexAttribs4svNV}, - /* [ 310] = 4206 */ {__glXDisp_VertexAttribs1fvNV, __glXDispSwap_VertexAttribs1fvNV}, - /* [ 311] = 4207 */ {__glXDisp_VertexAttribs2fvNV, __glXDispSwap_VertexAttribs2fvNV}, - /* [ 312] = 4208 */ {__glXDisp_VertexAttribs3fvNV, __glXDispSwap_VertexAttribs3fvNV}, - /* [ 313] = 4209 */ {__glXDisp_VertexAttribs4fvNV, __glXDispSwap_VertexAttribs4fvNV}, - /* [ 314] = 4210 */ {__glXDisp_VertexAttribs1dvNV, __glXDispSwap_VertexAttribs1dvNV}, - /* [ 315] = 4211 */ {__glXDisp_VertexAttribs2dvNV, __glXDispSwap_VertexAttribs2dvNV}, - /* [ 316] = 4212 */ {__glXDisp_VertexAttribs3dvNV, __glXDispSwap_VertexAttribs3dvNV}, - /* [ 317] = 4213 */ {__glXDisp_VertexAttribs4dvNV, __glXDispSwap_VertexAttribs4dvNV}, - /* [ 318] = 4214 */ {__glXDisp_VertexAttribs4ubvNV, __glXDispSwap_VertexAttribs4ubvNV}, - /* [ 319] = 4215 */ {__glXDisp_ProgramLocalParameter4fvARB, __glXDispSwap_ProgramLocalParameter4fvARB}, - /* [ 320] = 4216 */ {__glXDisp_ProgramLocalParameter4dvARB, __glXDispSwap_ProgramLocalParameter4dvARB}, - /* [ 321] = 4217 */ {__glXDisp_ProgramStringARB, __glXDispSwap_ProgramStringARB}, - /* [ 322] = 4218 */ {__glXDisp_ProgramNamedParameter4fvNV, __glXDispSwap_ProgramNamedParameter4fvNV}, - /* [ 323] = 4219 */ {__glXDisp_ProgramNamedParameter4dvNV, __glXDispSwap_ProgramNamedParameter4dvNV}, - /* [ 324] = 4220 */ {__glXDisp_ActiveStencilFaceEXT, __glXDispSwap_ActiveStencilFaceEXT}, - /* [ 325] = 4221 */ {__glXDisp_PointParameteriNV, __glXDispSwap_PointParameteriNV}, - /* [ 326] = 4222 */ {__glXDisp_PointParameterivNV, __glXDispSwap_PointParameterivNV}, - /* [ 327] = 4223 */ {NULL, NULL}, - /* [ 328] = 4128 */ {__glXDisp_SecondaryColor3ivEXT, __glXDispSwap_SecondaryColor3ivEXT}, - /* [ 329] = 4129 */ {__glXDisp_SecondaryColor3fvEXT, __glXDispSwap_SecondaryColor3fvEXT}, - /* [ 330] = 4130 */ {__glXDisp_SecondaryColor3dvEXT, __glXDispSwap_SecondaryColor3dvEXT}, - /* [ 331] = 4131 */ {__glXDisp_SecondaryColor3ubvEXT, __glXDispSwap_SecondaryColor3ubvEXT}, - /* [ 332] = 4132 */ {__glXDisp_SecondaryColor3usvEXT, __glXDispSwap_SecondaryColor3usvEXT}, - /* [ 333] = 4133 */ {__glXDisp_SecondaryColor3uivEXT, __glXDispSwap_SecondaryColor3uivEXT}, - /* [ 334] = 4134 */ {__glXDisp_BlendFuncSeparateEXT, __glXDispSwap_BlendFuncSeparateEXT}, - /* [ 335] = 4135 */ {NULL, NULL}, - /* [ 336] = 4176 */ {NULL, NULL}, - /* [ 337] = 4177 */ {NULL, NULL}, - /* [ 338] = 4178 */ {NULL, NULL}, - /* [ 339] = 4179 */ {NULL, NULL}, - /* [ 340] = 4180 */ {__glXDisp_BindProgramNV, __glXDispSwap_BindProgramNV}, - /* [ 341] = 4181 */ {__glXDisp_ExecuteProgramNV, __glXDispSwap_ExecuteProgramNV}, - /* [ 342] = 4182 */ {__glXDisp_RequestResidentProgramsNV, __glXDispSwap_RequestResidentProgramsNV}, - /* [ 343] = 4183 */ {__glXDisp_LoadProgramNV, __glXDispSwap_LoadProgramNV}, - /* [ 344] = 4184 */ {__glXDisp_ProgramParameter4fvNV, __glXDispSwap_ProgramParameter4fvNV}, - /* [ 345] = 4185 */ {__glXDisp_ProgramParameter4dvNV, __glXDispSwap_ProgramParameter4dvNV}, - /* [ 346] = 4186 */ {__glXDisp_ProgramParameters4fvNV, __glXDispSwap_ProgramParameters4fvNV}, - /* [ 347] = 4187 */ {__glXDisp_ProgramParameters4dvNV, __glXDispSwap_ProgramParameters4dvNV}, - /* [ 348] = 4188 */ {__glXDisp_TrackMatrixNV, __glXDispSwap_TrackMatrixNV}, - /* [ 349] = 4189 */ {__glXDisp_VertexAttrib1svNV, __glXDispSwap_VertexAttrib1svNV}, - /* [ 350] = 4190 */ {__glXDisp_VertexAttrib2svARB, __glXDispSwap_VertexAttrib2svARB}, - /* [ 351] = 4191 */ {__glXDisp_VertexAttrib3svNV, __glXDispSwap_VertexAttrib3svNV}, - /* [ 352] = 4224 */ {NULL, NULL}, - /* [ 353] = 4225 */ {NULL, NULL}, - /* [ 354] = 4226 */ {NULL, NULL}, - /* [ 355] = 4227 */ {NULL, NULL}, - /* [ 356] = 4228 */ {NULL, NULL}, - /* [ 357] = 4229 */ {NULL, NULL}, - /* [ 358] = 4230 */ {__glXDisp_VertexAttrib4bvARB, __glXDispSwap_VertexAttrib4bvARB}, - /* [ 359] = 4231 */ {__glXDisp_VertexAttrib4ivARB, __glXDispSwap_VertexAttrib4ivARB}, - /* [ 360] = 4232 */ {__glXDisp_VertexAttrib4ubvARB, __glXDispSwap_VertexAttrib4ubvARB}, - /* [ 361] = 4233 */ {__glXDisp_VertexAttrib4usvARB, __glXDispSwap_VertexAttrib4usvARB}, - /* [ 362] = 4234 */ {__glXDisp_VertexAttrib4uivARB, __glXDispSwap_VertexAttrib4uivARB}, - /* [ 363] = 4235 */ {__glXDisp_VertexAttrib4NbvARB, __glXDispSwap_VertexAttrib4NbvARB}, - /* [ 364] = 4236 */ {__glXDisp_VertexAttrib4NsvARB, __glXDispSwap_VertexAttrib4NsvARB}, - /* [ 365] = 4237 */ {__glXDisp_VertexAttrib4NivARB, __glXDispSwap_VertexAttrib4NivARB}, - /* [ 366] = 4238 */ {__glXDisp_VertexAttrib4NusvARB, __glXDispSwap_VertexAttrib4NusvARB}, - /* [ 367] = 4239 */ {__glXDisp_VertexAttrib4NuivARB, __glXDispSwap_VertexAttrib4NuivARB}, - /* [ 368] = 4312 */ {NULL, NULL}, - /* [ 369] = 4313 */ {NULL, NULL}, - /* [ 370] = 4314 */ {NULL, NULL}, - /* [ 371] = 4315 */ {NULL, NULL}, - /* [ 372] = 4316 */ {__glXDisp_BindRenderbufferEXT, __glXDispSwap_BindRenderbufferEXT}, - /* [ 373] = 4317 */ {__glXDisp_DeleteRenderbuffersEXT, __glXDispSwap_DeleteRenderbuffersEXT}, - /* [ 374] = 4318 */ {__glXDisp_RenderbufferStorageEXT, __glXDispSwap_RenderbufferStorageEXT}, - /* [ 375] = 4319 */ {__glXDisp_BindFramebufferEXT, __glXDispSwap_BindFramebufferEXT}, - /* [ 376] = 4320 */ {__glXDisp_DeleteFramebuffersEXT, __glXDispSwap_DeleteFramebuffersEXT}, - /* [ 377] = 4321 */ {__glXDisp_FramebufferTexture1DEXT, __glXDispSwap_FramebufferTexture1DEXT}, - /* [ 378] = 4322 */ {__glXDisp_FramebufferTexture2DEXT, __glXDispSwap_FramebufferTexture2DEXT}, - /* [ 379] = 4323 */ {__glXDisp_FramebufferTexture3DEXT, __glXDispSwap_FramebufferTexture3DEXT}, - /* [ 380] = 4324 */ {__glXDisp_FramebufferRenderbufferEXT, __glXDispSwap_FramebufferRenderbufferEXT}, - /* [ 381] = 4325 */ {__glXDisp_GenerateMipmapEXT, __glXDispSwap_GenerateMipmapEXT}, - /* [ 382] = 4326 */ {NULL, NULL}, - /* [ 383] = 4327 */ {NULL, NULL}, + /* [ 296] = 4176 */ {NULL, NULL}, + /* [ 297] = 4177 */ {NULL, NULL}, + /* [ 298] = 4178 */ {NULL, NULL}, + /* [ 299] = 4179 */ {NULL, NULL}, + /* [ 300] = 4180 */ {__glXDisp_BindProgramNV, __glXDispSwap_BindProgramNV}, + /* [ 301] = 4181 */ {__glXDisp_ExecuteProgramNV, __glXDispSwap_ExecuteProgramNV}, + /* [ 302] = 4182 */ {__glXDisp_RequestResidentProgramsNV, __glXDispSwap_RequestResidentProgramsNV}, + /* [ 303] = 4183 */ {__glXDisp_LoadProgramNV, __glXDispSwap_LoadProgramNV}, + /* [ 304] = 4184 */ {__glXDisp_ProgramParameter4fvNV, __glXDispSwap_ProgramParameter4fvNV}, + /* [ 305] = 4185 */ {__glXDisp_ProgramParameter4dvNV, __glXDispSwap_ProgramParameter4dvNV}, + /* [ 306] = 4186 */ {__glXDisp_ProgramParameters4fvNV, __glXDispSwap_ProgramParameters4fvNV}, + /* [ 307] = 4187 */ {__glXDisp_ProgramParameters4dvNV, __glXDispSwap_ProgramParameters4dvNV}, + /* [ 308] = 4188 */ {__glXDisp_TrackMatrixNV, __glXDispSwap_TrackMatrixNV}, + /* [ 309] = 4189 */ {__glXDisp_VertexAttrib1svARB, __glXDispSwap_VertexAttrib1svARB}, + /* [ 310] = 4190 */ {__glXDisp_VertexAttrib2svARB, __glXDispSwap_VertexAttrib2svARB}, + /* [ 311] = 4191 */ {__glXDisp_VertexAttrib3svARB, __glXDispSwap_VertexAttrib3svARB}, + /* [ 312] = 4192 */ {__glXDisp_VertexAttrib4svARB, __glXDispSwap_VertexAttrib4svARB}, + /* [ 313] = 4193 */ {__glXDisp_VertexAttrib1fvARB, __glXDispSwap_VertexAttrib1fvARB}, + /* [ 314] = 4194 */ {__glXDisp_VertexAttrib2fvARB, __glXDispSwap_VertexAttrib2fvARB}, + /* [ 315] = 4195 */ {__glXDisp_VertexAttrib3fvARB, __glXDispSwap_VertexAttrib3fvARB}, + /* [ 316] = 4196 */ {__glXDisp_VertexAttrib4fvARB, __glXDispSwap_VertexAttrib4fvARB}, + /* [ 317] = 4197 */ {__glXDisp_VertexAttrib1dvARB, __glXDispSwap_VertexAttrib1dvARB}, + /* [ 318] = 4198 */ {__glXDisp_VertexAttrib2dvARB, __glXDispSwap_VertexAttrib2dvARB}, + /* [ 319] = 4199 */ {__glXDisp_VertexAttrib3dvARB, __glXDispSwap_VertexAttrib3dvARB}, + /* [ 320] = 4200 */ {__glXDisp_VertexAttrib4dvARB, __glXDispSwap_VertexAttrib4dvARB}, + /* [ 321] = 4201 */ {__glXDisp_VertexAttrib4NubvARB, __glXDispSwap_VertexAttrib4NubvARB}, + /* [ 322] = 4202 */ {__glXDisp_VertexAttribs1svNV, __glXDispSwap_VertexAttribs1svNV}, + /* [ 323] = 4203 */ {__glXDisp_VertexAttribs2svNV, __glXDispSwap_VertexAttribs2svNV}, + /* [ 324] = 4204 */ {__glXDisp_VertexAttribs3svNV, __glXDispSwap_VertexAttribs3svNV}, + /* [ 325] = 4205 */ {__glXDisp_VertexAttribs4svNV, __glXDispSwap_VertexAttribs4svNV}, + /* [ 326] = 4206 */ {__glXDisp_VertexAttribs1fvNV, __glXDispSwap_VertexAttribs1fvNV}, + /* [ 327] = 4207 */ {__glXDisp_VertexAttribs2fvNV, __glXDispSwap_VertexAttribs2fvNV}, + /* [ 328] = 4208 */ {__glXDisp_VertexAttribs3fvNV, __glXDispSwap_VertexAttribs3fvNV}, + /* [ 329] = 4209 */ {__glXDisp_VertexAttribs4fvNV, __glXDispSwap_VertexAttribs4fvNV}, + /* [ 330] = 4210 */ {__glXDisp_VertexAttribs1dvNV, __glXDispSwap_VertexAttribs1dvNV}, + /* [ 331] = 4211 */ {__glXDisp_VertexAttribs2dvNV, __glXDispSwap_VertexAttribs2dvNV}, + /* [ 332] = 4212 */ {__glXDisp_VertexAttribs3dvNV, __glXDispSwap_VertexAttribs3dvNV}, + /* [ 333] = 4213 */ {__glXDisp_VertexAttribs4dvNV, __glXDispSwap_VertexAttribs4dvNV}, + /* [ 334] = 4214 */ {__glXDisp_VertexAttribs4ubvNV, __glXDispSwap_VertexAttribs4ubvNV}, + /* [ 335] = 4215 */ {__glXDisp_ProgramLocalParameter4fvARB, __glXDispSwap_ProgramLocalParameter4fvARB}, + /* [ 336] = 4216 */ {__glXDisp_ProgramLocalParameter4dvARB, __glXDispSwap_ProgramLocalParameter4dvARB}, + /* [ 337] = 4217 */ {__glXDisp_ProgramStringARB, __glXDispSwap_ProgramStringARB}, + /* [ 338] = 4218 */ {__glXDisp_ProgramNamedParameter4fvNV, __glXDispSwap_ProgramNamedParameter4fvNV}, + /* [ 339] = 4219 */ {__glXDisp_ProgramNamedParameter4dvNV, __glXDispSwap_ProgramNamedParameter4dvNV}, + /* [ 340] = 4220 */ {__glXDisp_ActiveStencilFaceEXT, __glXDispSwap_ActiveStencilFaceEXT}, + /* [ 341] = 4221 */ {__glXDisp_PointParameteriNV, __glXDispSwap_PointParameteriNV}, + /* [ 342] = 4222 */ {__glXDisp_PointParameterivNV, __glXDispSwap_PointParameterivNV}, + /* [ 343] = 4223 */ {NULL, NULL}, + /* [ 344] = 4224 */ {NULL, NULL}, + /* [ 345] = 4225 */ {NULL, NULL}, + /* [ 346] = 4226 */ {NULL, NULL}, + /* [ 347] = 4227 */ {NULL, NULL}, + /* [ 348] = 4228 */ {__glXDisp_BlendEquationSeparateEXT, __glXDispSwap_BlendEquationSeparateEXT}, + /* [ 349] = 4229 */ {NULL, NULL}, + /* [ 350] = 4230 */ {__glXDisp_VertexAttrib4bvARB, __glXDispSwap_VertexAttrib4bvARB}, + /* [ 351] = 4231 */ {__glXDisp_VertexAttrib4ivARB, __glXDispSwap_VertexAttrib4ivARB}, + /* [ 352] = 4232 */ {__glXDisp_VertexAttrib4ubvARB, __glXDispSwap_VertexAttrib4ubvARB}, + /* [ 353] = 4233 */ {__glXDisp_VertexAttrib4usvARB, __glXDispSwap_VertexAttrib4usvARB}, + /* [ 354] = 4234 */ {__glXDisp_VertexAttrib4uivARB, __glXDispSwap_VertexAttrib4uivARB}, + /* [ 355] = 4235 */ {__glXDisp_VertexAttrib4NbvARB, __glXDispSwap_VertexAttrib4NbvARB}, + /* [ 356] = 4236 */ {__glXDisp_VertexAttrib4NsvARB, __glXDispSwap_VertexAttrib4NsvARB}, + /* [ 357] = 4237 */ {__glXDisp_VertexAttrib4NivARB, __glXDispSwap_VertexAttrib4NivARB}, + /* [ 358] = 4238 */ {__glXDisp_VertexAttrib4NusvARB, __glXDispSwap_VertexAttrib4NusvARB}, + /* [ 359] = 4239 */ {__glXDisp_VertexAttrib4NuivARB, __glXDispSwap_VertexAttrib4NuivARB}, + /* [ 360] = 4128 */ {__glXDisp_SecondaryColor3ivEXT, __glXDispSwap_SecondaryColor3ivEXT}, + /* [ 361] = 4129 */ {__glXDisp_SecondaryColor3fvEXT, __glXDispSwap_SecondaryColor3fvEXT}, + /* [ 362] = 4130 */ {__glXDisp_SecondaryColor3dvEXT, __glXDispSwap_SecondaryColor3dvEXT}, + /* [ 363] = 4131 */ {__glXDisp_SecondaryColor3ubvEXT, __glXDispSwap_SecondaryColor3ubvEXT}, + /* [ 364] = 4132 */ {__glXDisp_SecondaryColor3usvEXT, __glXDispSwap_SecondaryColor3usvEXT}, + /* [ 365] = 4133 */ {__glXDisp_SecondaryColor3uivEXT, __glXDispSwap_SecondaryColor3uivEXT}, + /* [ 366] = 4134 */ {__glXDisp_BlendFuncSeparateEXT, __glXDispSwap_BlendFuncSeparateEXT}, + /* [ 367] = 4135 */ {NULL, NULL}, + /* [ 368] = 4264 */ {NULL, NULL}, + /* [ 369] = 4265 */ {__glXDisp_VertexAttrib1svNV, __glXDispSwap_VertexAttrib1svNV}, + /* [ 370] = 4266 */ {__glXDisp_VertexAttrib2svNV, __glXDispSwap_VertexAttrib2svNV}, + /* [ 371] = 4267 */ {__glXDisp_VertexAttrib3svNV, __glXDispSwap_VertexAttrib3svNV}, + /* [ 372] = 4268 */ {__glXDisp_VertexAttrib4svNV, __glXDispSwap_VertexAttrib4svNV}, + /* [ 373] = 4269 */ {__glXDisp_VertexAttrib1fvNV, __glXDispSwap_VertexAttrib1fvNV}, + /* [ 374] = 4270 */ {__glXDisp_VertexAttrib2fvNV, __glXDispSwap_VertexAttrib2fvNV}, + /* [ 375] = 4271 */ {__glXDisp_VertexAttrib3fvNV, __glXDispSwap_VertexAttrib3fvNV}, + /* [ 376] = 4272 */ {__glXDisp_VertexAttrib4fvNV, __glXDispSwap_VertexAttrib4fvNV}, + /* [ 377] = 4273 */ {__glXDisp_VertexAttrib1dvNV, __glXDispSwap_VertexAttrib1dvNV}, + /* [ 378] = 4274 */ {__glXDisp_VertexAttrib2dvNV, __glXDispSwap_VertexAttrib2dvNV}, + /* [ 379] = 4275 */ {__glXDisp_VertexAttrib3dvNV, __glXDispSwap_VertexAttrib3dvNV}, + /* [ 380] = 4276 */ {__glXDisp_VertexAttrib4dvNV, __glXDispSwap_VertexAttrib4dvNV}, + /* [ 381] = 4277 */ {__glXDisp_VertexAttrib4ubvNV, __glXDispSwap_VertexAttrib4ubvNV}, + /* [ 382] = 4278 */ {NULL, NULL}, + /* [ 383] = 4279 */ {NULL, NULL}, + /* [ 384] = 4312 */ {NULL, NULL}, + /* [ 385] = 4313 */ {NULL, NULL}, + /* [ 386] = 4314 */ {NULL, NULL}, + /* [ 387] = 4315 */ {NULL, NULL}, + /* [ 388] = 4316 */ {__glXDisp_BindRenderbufferEXT, __glXDispSwap_BindRenderbufferEXT}, + /* [ 389] = 4317 */ {__glXDisp_DeleteRenderbuffersEXT, __glXDispSwap_DeleteRenderbuffersEXT}, + /* [ 390] = 4318 */ {__glXDisp_RenderbufferStorageEXT, __glXDispSwap_RenderbufferStorageEXT}, + /* [ 391] = 4319 */ {__glXDisp_BindFramebufferEXT, __glXDispSwap_BindFramebufferEXT}, + /* [ 392] = 4320 */ {__glXDisp_DeleteFramebuffersEXT, __glXDispSwap_DeleteFramebuffersEXT}, + /* [ 393] = 4321 */ {__glXDisp_FramebufferTexture1DEXT, __glXDispSwap_FramebufferTexture1DEXT}, + /* [ 394] = 4322 */ {__glXDisp_FramebufferTexture2DEXT, __glXDispSwap_FramebufferTexture2DEXT}, + /* [ 395] = 4323 */ {__glXDisp_FramebufferTexture3DEXT, __glXDispSwap_FramebufferTexture3DEXT}, + /* [ 396] = 4324 */ {__glXDisp_FramebufferRenderbufferEXT, __glXDispSwap_FramebufferRenderbufferEXT}, + /* [ 397] = 4325 */ {__glXDisp_GenerateMipmapEXT, __glXDispSwap_GenerateMipmapEXT}, + /* [ 398] = 4326 */ {NULL, NULL}, + /* [ 399] = 4327 */ {NULL, NULL}, }; -static const int_fast16_t Render_size_table[384][2] = { +static const int_fast16_t Render_size_table[400][2] = { /* [ 0] = 0 */ { 0, ~0}, /* [ 1] = 1 */ { 8, ~0}, /* [ 2] = 2 */ { 12, 0}, @@ -1030,94 +1039,110 @@ static const int_fast16_t Render_size_table[384][2] = { /* [293] = 4125 */ { 12, ~0}, /* [294] = 4126 */ { 8, ~0}, /* [295] = 4127 */ { 12, ~0}, - /* [296] = 4192 */ { 16, ~0}, - /* [297] = 4193 */ { 12, ~0}, - /* [298] = 4194 */ { 16, ~0}, - /* [299] = 4195 */ { 20, ~0}, - /* [300] = 4196 */ { 24, ~0}, - /* [301] = 4197 */ { 16, ~0}, - /* [302] = 4198 */ { 24, ~0}, - /* [303] = 4199 */ { 32, ~0}, - /* [304] = 4200 */ { 40, ~0}, - /* [305] = 4201 */ { 12, ~0}, - /* [306] = 4202 */ { 12, 51}, - /* [307] = 4203 */ { 12, 52}, - /* [308] = 4204 */ { 12, 53}, - /* [309] = 4205 */ { 12, 54}, - /* [310] = 4206 */ { 12, 55}, - /* [311] = 4207 */ { 12, 56}, - /* [312] = 4208 */ { 12, 57}, - /* [313] = 4209 */ { 12, 58}, - /* [314] = 4210 */ { 12, 59}, - /* [315] = 4211 */ { 12, 60}, - /* [316] = 4212 */ { 12, 61}, - /* [317] = 4213 */ { 12, 62}, - /* [318] = 4214 */ { 12, 63}, - /* [319] = 4215 */ { 28, ~0}, - /* [320] = 4216 */ { 44, ~0}, - /* [321] = 4217 */ { 16, 64}, - /* [322] = 4218 */ { 28, 65}, - /* [323] = 4219 */ { 44, 66}, - /* [324] = 4220 */ { 8, ~0}, - /* [325] = 4221 */ { 12, ~0}, - /* [326] = 4222 */ { 8, 67}, - /* [327] = 4223 */ { 0, ~0}, - /* [328] = 4128 */ { 16, ~0}, - /* [329] = 4129 */ { 16, ~0}, - /* [330] = 4130 */ { 28, ~0}, - /* [331] = 4131 */ { 8, ~0}, - /* [332] = 4132 */ { 12, ~0}, - /* [333] = 4133 */ { 16, ~0}, - /* [334] = 4134 */ { 20, ~0}, - /* [335] = 4135 */ { 0, ~0}, - /* [336] = 4176 */ { 0, ~0}, - /* [337] = 4177 */ { 0, ~0}, - /* [338] = 4178 */ { 0, ~0}, - /* [339] = 4179 */ { 0, ~0}, - /* [340] = 4180 */ { 12, ~0}, - /* [341] = 4181 */ { 28, ~0}, - /* [342] = 4182 */ { 8, 68}, - /* [343] = 4183 */ { 16, 69}, - /* [344] = 4184 */ { 28, ~0}, - /* [345] = 4185 */ { 44, ~0}, - /* [346] = 4186 */ { 16, 70}, - /* [347] = 4187 */ { 16, 71}, - /* [348] = 4188 */ { 20, ~0}, - /* [349] = 4189 */ { 12, ~0}, - /* [350] = 4190 */ { 12, ~0}, - /* [351] = 4191 */ { 16, ~0}, - /* [352] = 4224 */ { 0, ~0}, - /* [353] = 4225 */ { 0, ~0}, - /* [354] = 4226 */ { 0, ~0}, - /* [355] = 4227 */ { 0, ~0}, - /* [356] = 4228 */ { 0, ~0}, - /* [357] = 4229 */ { 0, ~0}, - /* [358] = 4230 */ { 12, ~0}, - /* [359] = 4231 */ { 24, ~0}, - /* [360] = 4232 */ { 12, ~0}, - /* [361] = 4233 */ { 16, ~0}, - /* [362] = 4234 */ { 24, ~0}, - /* [363] = 4235 */ { 12, ~0}, - /* [364] = 4236 */ { 16, ~0}, - /* [365] = 4237 */ { 24, ~0}, - /* [366] = 4238 */ { 16, ~0}, - /* [367] = 4239 */ { 24, ~0}, - /* [368] = 4312 */ { 0, ~0}, - /* [369] = 4313 */ { 0, ~0}, - /* [370] = 4314 */ { 0, ~0}, - /* [371] = 4315 */ { 0, ~0}, - /* [372] = 4316 */ { 12, ~0}, - /* [373] = 4317 */ { 8, 72}, - /* [374] = 4318 */ { 20, ~0}, - /* [375] = 4319 */ { 12, ~0}, - /* [376] = 4320 */ { 8, 73}, - /* [377] = 4321 */ { 24, ~0}, - /* [378] = 4322 */ { 24, ~0}, - /* [379] = 4323 */ { 28, ~0}, - /* [380] = 4324 */ { 20, ~0}, - /* [381] = 4325 */ { 8, ~0}, - /* [382] = 4326 */ { 0, ~0}, - /* [383] = 4327 */ { 0, ~0}, + /* [296] = 4176 */ { 0, ~0}, + /* [297] = 4177 */ { 0, ~0}, + /* [298] = 4178 */ { 0, ~0}, + /* [299] = 4179 */ { 0, ~0}, + /* [300] = 4180 */ { 12, ~0}, + /* [301] = 4181 */ { 28, ~0}, + /* [302] = 4182 */ { 8, 51}, + /* [303] = 4183 */ { 16, 52}, + /* [304] = 4184 */ { 28, ~0}, + /* [305] = 4185 */ { 44, ~0}, + /* [306] = 4186 */ { 16, 53}, + /* [307] = 4187 */ { 16, 54}, + /* [308] = 4188 */ { 20, ~0}, + /* [309] = 4189 */ { 12, ~0}, + /* [310] = 4190 */ { 12, ~0}, + /* [311] = 4191 */ { 16, ~0}, + /* [312] = 4192 */ { 16, ~0}, + /* [313] = 4193 */ { 12, ~0}, + /* [314] = 4194 */ { 16, ~0}, + /* [315] = 4195 */ { 20, ~0}, + /* [316] = 4196 */ { 24, ~0}, + /* [317] = 4197 */ { 16, ~0}, + /* [318] = 4198 */ { 24, ~0}, + /* [319] = 4199 */ { 32, ~0}, + /* [320] = 4200 */ { 40, ~0}, + /* [321] = 4201 */ { 12, ~0}, + /* [322] = 4202 */ { 12, 55}, + /* [323] = 4203 */ { 12, 56}, + /* [324] = 4204 */ { 12, 57}, + /* [325] = 4205 */ { 12, 58}, + /* [326] = 4206 */ { 12, 59}, + /* [327] = 4207 */ { 12, 60}, + /* [328] = 4208 */ { 12, 61}, + /* [329] = 4209 */ { 12, 62}, + /* [330] = 4210 */ { 12, 63}, + /* [331] = 4211 */ { 12, 64}, + /* [332] = 4212 */ { 12, 65}, + /* [333] = 4213 */ { 12, 66}, + /* [334] = 4214 */ { 12, 67}, + /* [335] = 4215 */ { 28, ~0}, + /* [336] = 4216 */ { 44, ~0}, + /* [337] = 4217 */ { 16, 68}, + /* [338] = 4218 */ { 28, 69}, + /* [339] = 4219 */ { 44, 70}, + /* [340] = 4220 */ { 8, ~0}, + /* [341] = 4221 */ { 12, ~0}, + /* [342] = 4222 */ { 8, 71}, + /* [343] = 4223 */ { 0, ~0}, + /* [344] = 4224 */ { 0, ~0}, + /* [345] = 4225 */ { 0, ~0}, + /* [346] = 4226 */ { 0, ~0}, + /* [347] = 4227 */ { 0, ~0}, + /* [348] = 4228 */ { 12, ~0}, + /* [349] = 4229 */ { 0, ~0}, + /* [350] = 4230 */ { 12, ~0}, + /* [351] = 4231 */ { 24, ~0}, + /* [352] = 4232 */ { 12, ~0}, + /* [353] = 4233 */ { 16, ~0}, + /* [354] = 4234 */ { 24, ~0}, + /* [355] = 4235 */ { 12, ~0}, + /* [356] = 4236 */ { 16, ~0}, + /* [357] = 4237 */ { 24, ~0}, + /* [358] = 4238 */ { 16, ~0}, + /* [359] = 4239 */ { 24, ~0}, + /* [360] = 4128 */ { 16, ~0}, + /* [361] = 4129 */ { 16, ~0}, + /* [362] = 4130 */ { 28, ~0}, + /* [363] = 4131 */ { 8, ~0}, + /* [364] = 4132 */ { 12, ~0}, + /* [365] = 4133 */ { 16, ~0}, + /* [366] = 4134 */ { 20, ~0}, + /* [367] = 4135 */ { 0, ~0}, + /* [368] = 4264 */ { 0, ~0}, + /* [369] = 4265 */ { 12, ~0}, + /* [370] = 4266 */ { 12, ~0}, + /* [371] = 4267 */ { 16, ~0}, + /* [372] = 4268 */ { 16, ~0}, + /* [373] = 4269 */ { 12, ~0}, + /* [374] = 4270 */ { 16, ~0}, + /* [375] = 4271 */ { 20, ~0}, + /* [376] = 4272 */ { 24, ~0}, + /* [377] = 4273 */ { 16, ~0}, + /* [378] = 4274 */ { 24, ~0}, + /* [379] = 4275 */ { 32, ~0}, + /* [380] = 4276 */ { 40, ~0}, + /* [381] = 4277 */ { 12, ~0}, + /* [382] = 4278 */ { 0, ~0}, + /* [383] = 4279 */ { 0, ~0}, + /* [384] = 4312 */ { 0, ~0}, + /* [385] = 4313 */ { 0, ~0}, + /* [386] = 4314 */ { 0, ~0}, + /* [387] = 4315 */ { 0, ~0}, + /* [388] = 4316 */ { 12, ~0}, + /* [389] = 4317 */ { 8, 72}, + /* [390] = 4318 */ { 20, ~0}, + /* [391] = 4319 */ { 12, ~0}, + /* [392] = 4320 */ { 8, 73}, + /* [393] = 4321 */ { 24, ~0}, + /* [394] = 4322 */ { 24, ~0}, + /* [395] = 4323 */ { 28, ~0}, + /* [396] = 4324 */ { 20, ~0}, + /* [397] = 4325 */ { 8, ~0}, + /* [398] = 4326 */ { 0, ~0}, + /* [399] = 4327 */ { 0, ~0}, }; static const gl_proto_size_func Render_size_func_table[74] = { @@ -1172,6 +1197,10 @@ static const gl_proto_size_func Render_size_func_table[74] = { __glXTexImage3DReqSize, __glXTexSubImage3DReqSize, __glXPrioritizeTexturesReqSize, + __glXRequestResidentProgramsNVReqSize, + __glXLoadProgramNVReqSize, + __glXProgramParameters4fvNVReqSize, + __glXProgramParameters4dvNVReqSize, __glXVertexAttribs1svNVReqSize, __glXVertexAttribs2svNVReqSize, __glXVertexAttribs3svNVReqSize, @@ -1189,10 +1218,6 @@ static const gl_proto_size_func Render_size_func_table[74] = { __glXProgramNamedParameter4fvNVReqSize, __glXProgramNamedParameter4dvNVReqSize, __glXPointParameterivNVReqSize, - __glXRequestResidentProgramsNVReqSize, - __glXLoadProgramNVReqSize, - __glXProgramParameters4fvNVReqSize, - __glXProgramParameters4dvNVReqSize, __glXDeleteRenderbuffersEXTReqSize, __glXDeleteFramebuffersEXTReqSize, }; @@ -1236,7 +1261,7 @@ static const int_fast16_t VendorPriv_dispatch_tree[155] = { 2, 21, EMPTY_LEAF, - 39, + 36, EMPTY_LEAF, /* [21] -> opcode range [0, 512], node depth 6 */ @@ -1261,57 +1286,57 @@ static const int_fast16_t VendorPriv_dispatch_tree[155] = { /* [33] -> opcode range [0, 32], node depth 10 */ 1, - 36, - EMPTY_LEAF, - - /* [36] -> opcode range [0, 16], node depth 11 */ - 1, - EMPTY_LEAF, LEAF(0), - - /* [39] -> opcode range [1024, 1536], node depth 6 */ - 2, - 44, EMPTY_LEAF, - 56, + + /* [36] -> opcode range [1024, 1536], node depth 6 */ + 2, + 41, + EMPTY_LEAF, + 53, 67, - /* [44] -> opcode range [1024, 1152], node depth 7 */ + /* [41] -> opcode range [1024, 1152], node depth 7 */ + 1, + 44, + EMPTY_LEAF, + + /* [44] -> opcode range [1024, 1088], node depth 8 */ 1, 47, EMPTY_LEAF, - /* [47] -> opcode range [1024, 1088], node depth 8 */ + /* [47] -> opcode range [1024, 1056], node depth 9 */ 1, 50, EMPTY_LEAF, - /* [50] -> opcode range [1024, 1056], node depth 9 */ + /* [50] -> opcode range [1024, 1040], node depth 10 */ 1, - 53, - EMPTY_LEAF, - - /* [53] -> opcode range [1024, 1040], node depth 10 */ - 1, - LEAF(8), - EMPTY_LEAF, - - /* [56] -> opcode range [1280, 1408], node depth 7 */ - 1, - 59, - EMPTY_LEAF, - - /* [59] -> opcode range [1280, 1344], node depth 8 */ - 1, - 62, - EMPTY_LEAF, - - /* [62] -> opcode range [1280, 1312], node depth 9 */ - 2, - EMPTY_LEAF, LEAF(16), + EMPTY_LEAF, + + /* [53] -> opcode range [1280, 1408], node depth 7 */ + 1, + 56, + EMPTY_LEAF, + + /* [56] -> opcode range [1280, 1344], node depth 8 */ + 2, + 61, LEAF(24), - LEAF(32), + EMPTY_LEAF, + 64, + + /* [61] -> opcode range [1280, 1296], node depth 9 */ + 1, + EMPTY_LEAF, + LEAF(40), + + /* [64] -> opcode range [1328, 1344], node depth 9 */ + 1, + LEAF(48), + EMPTY_LEAF, /* [67] -> opcode range [1408, 1536], node depth 7 */ 1, @@ -1326,8 +1351,8 @@ static const int_fast16_t VendorPriv_dispatch_tree[155] = { /* [73] -> opcode range [1408, 1440], node depth 9 */ 2, EMPTY_LEAF, - LEAF(40), - LEAF(48), + LEAF(56), + LEAF(64), EMPTY_LEAF, /* [78] -> opcode range [4096, 6144], node depth 5 */ @@ -1364,7 +1389,7 @@ static const int_fast16_t VendorPriv_dispatch_tree[155] = { /* [98] -> opcode range [4096, 4112], node depth 11 */ 1, - LEAF(56), + LEAF(72), EMPTY_LEAF, /* [101] -> opcode range [5120, 5632], node depth 6 */ @@ -1394,7 +1419,7 @@ static const int_fast16_t VendorPriv_dispatch_tree[155] = { /* [116] -> opcode range [5152, 5168], node depth 11 */ 1, - LEAF(64), + LEAF(80), EMPTY_LEAF, /* [119] -> opcode range [65536, 98304], node depth 2 */ @@ -1454,36 +1479,36 @@ static const int_fast16_t VendorPriv_dispatch_tree[155] = { /* [152] -> opcode range [65536, 65552], node depth 13 */ 1, - LEAF(72), + LEAF(88), EMPTY_LEAF, }; -static const void *VendorPriv_function_table[80][2] = { - /* [ 0] = 8 */ {NULL, NULL}, - /* [ 1] = 9 */ {NULL, NULL}, - /* [ 2] = 10 */ {NULL, NULL}, - /* [ 3] = 11 */ {__glXDisp_AreTexturesResidentEXT, __glXDispSwap_AreTexturesResidentEXT}, - /* [ 4] = 12 */ {__glXDisp_DeleteTextures, __glXDispSwap_DeleteTextures}, - /* [ 5] = 13 */ {__glXDisp_GenTexturesEXT, __glXDispSwap_GenTexturesEXT}, - /* [ 6] = 14 */ {__glXDisp_IsTextureEXT, __glXDispSwap_IsTextureEXT}, - /* [ 7] = 15 */ {NULL, NULL}, - /* [ 8] = 1024 */ {__glXDisp_QueryContextInfoEXT, __glXDispSwap_QueryContextInfoEXT}, - /* [ 9] = 1025 */ {NULL, NULL}, - /* [ 10] = 1026 */ {NULL, NULL}, - /* [ 11] = 1027 */ {NULL, NULL}, - /* [ 12] = 1028 */ {NULL, NULL}, - /* [ 13] = 1029 */ {NULL, NULL}, - /* [ 14] = 1030 */ {NULL, NULL}, - /* [ 15] = 1031 */ {NULL, NULL}, - /* [ 16] = 1288 */ {NULL, NULL}, - /* [ 17] = 1289 */ {NULL, NULL}, - /* [ 18] = 1290 */ {NULL, NULL}, - /* [ 19] = 1291 */ {NULL, NULL}, - /* [ 20] = 1292 */ {NULL, NULL}, - /* [ 21] = 1293 */ {__glXDisp_AreProgramsResidentNV, __glXDispSwap_AreProgramsResidentNV}, - /* [ 22] = 1294 */ {__glXDisp_DeleteProgramsNV, __glXDispSwap_DeleteProgramsNV}, - /* [ 23] = 1295 */ {__glXDisp_GenProgramsNV, __glXDispSwap_GenProgramsNV}, +static const void *VendorPriv_function_table[96][2] = { + /* [ 0] = 0 */ {NULL, NULL}, + /* [ 1] = 1 */ {__glXDisp_GetConvolutionFilterEXT, __glXDispSwap_GetConvolutionFilterEXT}, + /* [ 2] = 2 */ {__glXDisp_GetConvolutionParameterfvEXT, __glXDispSwap_GetConvolutionParameterfvEXT}, + /* [ 3] = 3 */ {__glXDisp_GetConvolutionParameterivEXT, __glXDispSwap_GetConvolutionParameterivEXT}, + /* [ 4] = 4 */ {__glXDisp_GetSeparableFilterEXT, __glXDispSwap_GetSeparableFilterEXT}, + /* [ 5] = 5 */ {__glXDisp_GetHistogramEXT, __glXDispSwap_GetHistogramEXT}, + /* [ 6] = 6 */ {__glXDisp_GetHistogramParameterfvEXT, __glXDispSwap_GetHistogramParameterfvEXT}, + /* [ 7] = 7 */ {__glXDisp_GetHistogramParameterivEXT, __glXDispSwap_GetHistogramParameterivEXT}, + /* [ 8] = 8 */ {__glXDisp_GetMinmaxEXT, __glXDispSwap_GetMinmaxEXT}, + /* [ 9] = 9 */ {__glXDisp_GetMinmaxParameterfvEXT, __glXDispSwap_GetMinmaxParameterfvEXT}, + /* [ 10] = 10 */ {__glXDisp_GetMinmaxParameterivEXT, __glXDispSwap_GetMinmaxParameterivEXT}, + /* [ 11] = 11 */ {__glXDisp_AreTexturesResidentEXT, __glXDispSwap_AreTexturesResidentEXT}, + /* [ 12] = 12 */ {__glXDisp_DeleteTexturesEXT, __glXDispSwap_DeleteTexturesEXT}, + /* [ 13] = 13 */ {__glXDisp_GenTexturesEXT, __glXDispSwap_GenTexturesEXT}, + /* [ 14] = 14 */ {__glXDisp_IsTextureEXT, __glXDispSwap_IsTextureEXT}, + /* [ 15] = 15 */ {NULL, NULL}, + /* [ 16] = 1024 */ {__glXDisp_QueryContextInfoEXT, __glXDispSwap_QueryContextInfoEXT}, + /* [ 17] = 1025 */ {NULL, NULL}, + /* [ 18] = 1026 */ {NULL, NULL}, + /* [ 19] = 1027 */ {NULL, NULL}, + /* [ 20] = 1028 */ {NULL, NULL}, + /* [ 21] = 1029 */ {NULL, NULL}, + /* [ 22] = 1030 */ {NULL, NULL}, + /* [ 23] = 1031 */ {NULL, NULL}, /* [ 24] = 1296 */ {__glXDisp_GetProgramEnvParameterfvARB, __glXDispSwap_GetProgramEnvParameterfvARB}, /* [ 25] = 1297 */ {__glXDisp_GetProgramEnvParameterdvARB, __glXDispSwap_GetProgramEnvParameterdvARB}, /* [ 26] = 1298 */ {__glXDisp_GetProgramivNV, __glXDispSwap_GetProgramivNV}, @@ -1500,46 +1525,62 @@ static const void *VendorPriv_function_table[80][2] = { /* [ 37] = 1309 */ {NULL, NULL}, /* [ 38] = 1310 */ {__glXDisp_GetProgramNamedParameterfvNV, __glXDispSwap_GetProgramNamedParameterfvNV}, /* [ 39] = 1311 */ {__glXDisp_GetProgramNamedParameterdvNV, __glXDispSwap_GetProgramNamedParameterdvNV}, - /* [ 40] = 1416 */ {NULL, NULL}, - /* [ 41] = 1417 */ {NULL, NULL}, - /* [ 42] = 1418 */ {NULL, NULL}, - /* [ 43] = 1419 */ {NULL, NULL}, - /* [ 44] = 1420 */ {NULL, NULL}, - /* [ 45] = 1421 */ {NULL, NULL}, - /* [ 46] = 1422 */ {__glXDisp_IsRenderbufferEXT, __glXDispSwap_IsRenderbufferEXT}, - /* [ 47] = 1423 */ {__glXDisp_GenRenderbuffersEXT, __glXDispSwap_GenRenderbuffersEXT}, - /* [ 48] = 1424 */ {__glXDisp_GetRenderbufferParameterivEXT, __glXDispSwap_GetRenderbufferParameterivEXT}, - /* [ 49] = 1425 */ {__glXDisp_IsFramebufferEXT, __glXDispSwap_IsFramebufferEXT}, - /* [ 50] = 1426 */ {__glXDisp_GenFramebuffersEXT, __glXDispSwap_GenFramebuffersEXT}, - /* [ 51] = 1427 */ {__glXDisp_CheckFramebufferStatusEXT, __glXDispSwap_CheckFramebufferStatusEXT}, - /* [ 52] = 1428 */ {__glXDisp_GetFramebufferAttachmentParameterivEXT, __glXDispSwap_GetFramebufferAttachmentParameterivEXT}, - /* [ 53] = 1429 */ {NULL, NULL}, - /* [ 54] = 1430 */ {NULL, NULL}, - /* [ 55] = 1431 */ {NULL, NULL}, - /* [ 56] = 4096 */ {NULL, NULL}, - /* [ 57] = 4097 */ {NULL, NULL}, - /* [ 58] = 4098 */ {__glXDisp_GetColorTableSGI, __glXDispSwap_GetColorTableSGI}, - /* [ 59] = 4099 */ {__glXDisp_GetColorTableParameterfvSGI, __glXDispSwap_GetColorTableParameterfvSGI}, - /* [ 60] = 4100 */ {__glXDisp_GetColorTableParameterivSGI, __glXDispSwap_GetColorTableParameterivSGI}, - /* [ 61] = 4101 */ {NULL, NULL}, - /* [ 62] = 4102 */ {NULL, NULL}, - /* [ 63] = 4103 */ {NULL, NULL}, - /* [ 64] = 5152 */ {__glXDisp_BindTexImageEXT, __glXDispSwap_BindTexImageEXT}, - /* [ 65] = 5153 */ {__glXDisp_ReleaseTexImageEXT, __glXDispSwap_ReleaseTexImageEXT}, - /* [ 66] = 5154 */ {__glXDisp_CopySubBufferMESA, __glXDispSwap_CopySubBufferMESA}, - /* [ 67] = 5155 */ {NULL, NULL}, - /* [ 68] = 5156 */ {NULL, NULL}, - /* [ 69] = 5157 */ {NULL, NULL}, - /* [ 70] = 5158 */ {NULL, NULL}, - /* [ 71] = 5159 */ {NULL, NULL}, - /* [ 72] = 65536 */ {NULL, NULL}, - /* [ 73] = 65537 */ {__glXDisp_MakeCurrentReadSGI, __glXDispSwap_MakeCurrentReadSGI}, - /* [ 74] = 65538 */ {NULL, NULL}, - /* [ 75] = 65539 */ {NULL, NULL}, - /* [ 76] = 65540 */ {__glXDisp_GetFBConfigsSGIX, __glXDispSwap_GetFBConfigsSGIX}, - /* [ 77] = 65541 */ {__glXDisp_CreateContextWithConfigSGIX, __glXDispSwap_CreateContextWithConfigSGIX}, - /* [ 78] = 65542 */ {__glXDisp_CreateGLXPixmapWithConfigSGIX, __glXDispSwap_CreateGLXPixmapWithConfigSGIX}, - /* [ 79] = 65543 */ {NULL, NULL}, + /* [ 40] = 1288 */ {NULL, NULL}, + /* [ 41] = 1289 */ {NULL, NULL}, + /* [ 42] = 1290 */ {NULL, NULL}, + /* [ 43] = 1291 */ {NULL, NULL}, + /* [ 44] = 1292 */ {NULL, NULL}, + /* [ 45] = 1293 */ {__glXDisp_AreProgramsResidentNV, __glXDispSwap_AreProgramsResidentNV}, + /* [ 46] = 1294 */ {__glXDisp_DeleteProgramsNV, __glXDispSwap_DeleteProgramsNV}, + /* [ 47] = 1295 */ {__glXDisp_GenProgramsNV, __glXDispSwap_GenProgramsNV}, + /* [ 48] = 1328 */ {NULL, NULL}, + /* [ 49] = 1329 */ {NULL, NULL}, + /* [ 50] = 1330 */ {__glXDisp_BindTexImageEXT, __glXDispSwap_BindTexImageEXT}, + /* [ 51] = 1331 */ {__glXDisp_ReleaseTexImageEXT, __glXDispSwap_ReleaseTexImageEXT}, + /* [ 52] = 1332 */ {NULL, NULL}, + /* [ 53] = 1333 */ {NULL, NULL}, + /* [ 54] = 1334 */ {NULL, NULL}, + /* [ 55] = 1335 */ {NULL, NULL}, + /* [ 56] = 1416 */ {NULL, NULL}, + /* [ 57] = 1417 */ {NULL, NULL}, + /* [ 58] = 1418 */ {NULL, NULL}, + /* [ 59] = 1419 */ {NULL, NULL}, + /* [ 60] = 1420 */ {NULL, NULL}, + /* [ 61] = 1421 */ {NULL, NULL}, + /* [ 62] = 1422 */ {__glXDisp_IsRenderbufferEXT, __glXDispSwap_IsRenderbufferEXT}, + /* [ 63] = 1423 */ {__glXDisp_GenRenderbuffersEXT, __glXDispSwap_GenRenderbuffersEXT}, + /* [ 64] = 1424 */ {__glXDisp_GetRenderbufferParameterivEXT, __glXDispSwap_GetRenderbufferParameterivEXT}, + /* [ 65] = 1425 */ {__glXDisp_IsFramebufferEXT, __glXDispSwap_IsFramebufferEXT}, + /* [ 66] = 1426 */ {__glXDisp_GenFramebuffersEXT, __glXDispSwap_GenFramebuffersEXT}, + /* [ 67] = 1427 */ {__glXDisp_CheckFramebufferStatusEXT, __glXDispSwap_CheckFramebufferStatusEXT}, + /* [ 68] = 1428 */ {__glXDisp_GetFramebufferAttachmentParameterivEXT, __glXDispSwap_GetFramebufferAttachmentParameterivEXT}, + /* [ 69] = 1429 */ {NULL, NULL}, + /* [ 70] = 1430 */ {NULL, NULL}, + /* [ 71] = 1431 */ {NULL, NULL}, + /* [ 72] = 4096 */ {NULL, NULL}, + /* [ 73] = 4097 */ {NULL, NULL}, + /* [ 74] = 4098 */ {__glXDisp_GetColorTableSGI, __glXDispSwap_GetColorTableSGI}, + /* [ 75] = 4099 */ {__glXDisp_GetColorTableParameterfvSGI, __glXDispSwap_GetColorTableParameterfvSGI}, + /* [ 76] = 4100 */ {__glXDisp_GetColorTableParameterivSGI, __glXDispSwap_GetColorTableParameterivSGI}, + /* [ 77] = 4101 */ {NULL, NULL}, + /* [ 78] = 4102 */ {NULL, NULL}, + /* [ 79] = 4103 */ {NULL, NULL}, + /* [ 80] = 5152 */ {NULL, NULL}, + /* [ 81] = 5153 */ {NULL, NULL}, + /* [ 82] = 5154 */ {__glXDisp_CopySubBufferMESA, __glXDispSwap_CopySubBufferMESA}, + /* [ 83] = 5155 */ {NULL, NULL}, + /* [ 84] = 5156 */ {NULL, NULL}, + /* [ 85] = 5157 */ {NULL, NULL}, + /* [ 86] = 5158 */ {NULL, NULL}, + /* [ 87] = 5159 */ {NULL, NULL}, + /* [ 88] = 65536 */ {__glXDisp_SwapIntervalSGI, __glXDispSwap_SwapIntervalSGI}, + /* [ 89] = 65537 */ {__glXDisp_MakeCurrentReadSGI, __glXDispSwap_MakeCurrentReadSGI}, + /* [ 90] = 65538 */ {NULL, NULL}, + /* [ 91] = 65539 */ {NULL, NULL}, + /* [ 92] = 65540 */ {__glXDisp_GetFBConfigsSGIX, __glXDispSwap_GetFBConfigsSGIX}, + /* [ 93] = 65541 */ {__glXDisp_CreateContextWithConfigSGIX, __glXDispSwap_CreateContextWithConfigSGIX}, + /* [ 94] = 65542 */ {__glXDisp_CreateGLXPixmapWithConfigSGIX, __glXDispSwap_CreateGLXPixmapWithConfigSGIX}, + /* [ 95] = 65543 */ {NULL, NULL}, }; const struct __glXDispatchInfo VendorPriv_dispatch_info = { diff --git a/GL/glx/indirect_texture_compression.c b/GL/glx/indirect_texture_compression.c new file mode 100644 index 000000000..0c42ea034 --- /dev/null +++ b/GL/glx/indirect_texture_compression.c @@ -0,0 +1,133 @@ +/* + * (C) Copyright IBM Corporation 2005, 2006 + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * IBM, + * AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#define NEED_REPLIES +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#include "glxserver.h" +#include "glxext.h" +#include "singlesize.h" +#include "unpack.h" +#include "indirect_size_get.h" +#include "indirect_dispatch.h" +#include "glapitable.h" +#include "glapi.h" +#include "glthread.h" +#include "dispatch.h" + +#ifdef __linux__ +#include +#elif defined(__OpenBSD__) +#include +#define bswap_16 __swap16 +#define bswap_32 __swap32 +#define bswap_64 __swap64 +#else +#include +#define bswap_16 bswap16 +#define bswap_32 bswap32 +#define bswap_64 bswap64 +#endif + +int __glXDisp_GetCompressedTexImageARB(struct __GLXclientStateRec *cl, GLbyte *pc) +{ + xGLXSingleReq * const req = (xGLXSingleReq *) pc; + int error; + __GLXcontext * const cx = __glXForceCurrent( cl, req->contextTag, & error ); + ClientPtr client = cl->client; + + + pc += __GLX_SINGLE_HDR_SIZE; + if ( cx != NULL ) { + const GLenum target = *(GLenum *)(pc + 0); + const GLint level = *(GLint *)(pc + 4); + GLint compsize = 0; + char *answer, answerBuffer[200]; + + CALL_GetTexLevelParameteriv(GET_DISPATCH(), (target, level, GL_TEXTURE_COMPRESSED_IMAGE_SIZE, &compsize)); + + if ( compsize != 0 ) { + __GLX_GET_ANSWER_BUFFER(answer,cl,compsize,1); + __glXClearErrorOccured(); + CALL_GetCompressedTexImageARB(GET_DISPATCH(), (target, level, answer)); + } + + if (__glXErrorOccured()) { + __GLX_BEGIN_REPLY(0); + __GLX_SEND_HEADER(); + } else { + __GLX_BEGIN_REPLY(compsize); + ((xGLXGetTexImageReply *)&__glXReply)->width = compsize; + __GLX_SEND_HEADER(); + __GLX_SEND_VOID_ARRAY(compsize); + } + + error = Success; + } + + return error; +} + + +int __glXDispSwap_GetCompressedTexImageARB(struct __GLXclientStateRec *cl, GLbyte *pc) +{ + xGLXSingleReq * const req = (xGLXSingleReq *) pc; + int error; + __GLXcontext * const cx = __glXForceCurrent( cl, bswap_32( req->contextTag ), & error ); + ClientPtr client = cl->client; + + + pc += __GLX_SINGLE_HDR_SIZE; + if ( cx != NULL ) { + const GLenum target = (GLenum) bswap_32( *(int *)(pc + 0) ); + const GLint level = (GLint ) bswap_32( *(int *)(pc + 4) ); + GLint compsize = 0; + char *answer, answerBuffer[200]; + + CALL_GetTexLevelParameteriv(GET_DISPATCH(), (target, level, GL_TEXTURE_COMPRESSED_IMAGE_SIZE, &compsize)); + + if ( compsize != 0 ) { + __GLX_GET_ANSWER_BUFFER(answer,cl,compsize,1); + __glXClearErrorOccured(); + CALL_GetCompressedTexImageARB(GET_DISPATCH(), (target, level, answer)); + } + + if (__glXErrorOccured()) { + __GLX_BEGIN_REPLY(0); + __GLX_SEND_HEADER(); + } else { + __GLX_BEGIN_REPLY(compsize); + ((xGLXGetTexImageReply *)&__glXReply)->width = compsize; + __GLX_SEND_HEADER(); + __GLX_SEND_VOID_ARRAY(compsize); + } + + error = Success; + } + + return error; +} diff --git a/GL/glx/single2.c b/GL/glx/single2.c index 357cd317e..3387af2a2 100644 --- a/GL/glx/single2.c +++ b/GL/glx/single2.c @@ -392,13 +392,3 @@ int __glXDisp_GetString(__GLXclientState *cl, GLbyte *pc) { return DoGetString(cl, pc, GL_FALSE); } - -int __glXDisp_GetProgramStringARB(__GLXclientState *cl, GLbyte *pc) -{ - return BadRequest; -} - -int __glXDisp_GetProgramStringNV(__GLXclientState *cl, GLbyte *pc) -{ - return BadRequest; -} diff --git a/GL/glx/single2swap.c b/GL/glx/single2swap.c index 6d5e5ce0d..41a42bb0f 100644 --- a/GL/glx/single2swap.c +++ b/GL/glx/single2swap.c @@ -270,13 +270,3 @@ int __glXDispSwap_GetString(__GLXclientState *cl, GLbyte *pc) { return DoGetString(cl, pc, GL_TRUE); } - -int __glXDispSwap_GetProgramStringARB(__GLXclientState *cl, GLbyte *pc) -{ - return BadRequest; -} - -int __glXDispSwap_GetProgramStringNV(__GLXclientState *cl, GLbyte *pc) -{ - return BadRequest; -} diff --git a/GL/glx/singlepix.c b/GL/glx/singlepix.c index 62588b0d0..98898aa3a 100644 --- a/GL/glx/singlepix.c +++ b/GL/glx/singlepix.c @@ -195,7 +195,7 @@ int __glXDisp_GetPolygonStipple(__GLXclientState *cl, GLbyte *pc) return Success; } -int __glXDisp_GetSeparableFilter(__GLXclientState *cl, GLbyte *pc) +static int GetSeparableFilter(__GLXclientState *cl, GLbyte *pc, GLXContextTag tag) { GLint compsize, compsize2; GLenum format, type, target; @@ -206,12 +206,11 @@ int __glXDisp_GetSeparableFilter(__GLXclientState *cl, GLbyte *pc) char *answer, answerBuffer[200]; GLint width=0, height=0; - cx = __glXForceCurrent(cl, __GLX_GET_SINGLE_CONTEXT_TAG(pc), &error); + cx = __glXForceCurrent(cl, tag, &error); if (!cx) { return error; } - pc += __GLX_SINGLE_HDR_SIZE; format = *(GLenum *)(pc + 4); type = *(GLenum *)(pc + 8); target = *(GLenum *)(pc + 0); @@ -220,8 +219,8 @@ int __glXDisp_GetSeparableFilter(__GLXclientState *cl, GLbyte *pc) /* target must be SEPARABLE_2D, however I guess we can let the GL barf on this one.... */ - CALL_GetConvolutionParameteriv( GET_DISPATCH(), (target, GL_CONVOLUTION_WIDTH, &width) ); - CALL_GetConvolutionParameteriv( GET_DISPATCH(), (target, GL_CONVOLUTION_HEIGHT, &height) ); + CALL_GetConvolutionParameteriv(GET_DISPATCH(), (target, GL_CONVOLUTION_WIDTH, &width)); + CALL_GetConvolutionParameteriv(GET_DISPATCH(), (target, GL_CONVOLUTION_HEIGHT, &height)); /* * The two queries above might fail if we're in a state where queries * are illegal, but then width and height would still be zero anyway. @@ -234,7 +233,7 @@ int __glXDisp_GetSeparableFilter(__GLXclientState *cl, GLbyte *pc) compsize = __GLX_PAD(compsize); compsize2 = __GLX_PAD(compsize2); - CALL_PixelStorei( GET_DISPATCH(), (GL_PACK_SWAP_BYTES, swapBytes) ); + CALL_PixelStorei(GET_DISPATCH(), (GL_PACK_SWAP_BYTES, swapBytes)); __GLX_GET_ANSWER_BUFFER(answer,cl,compsize + compsize2,1); __glXClearErrorOccured(); CALL_GetSeparableFilter( GET_DISPATCH(), ( @@ -260,7 +259,22 @@ int __glXDisp_GetSeparableFilter(__GLXclientState *cl, GLbyte *pc) return Success; } -int __glXDisp_GetConvolutionFilter(__GLXclientState *cl, GLbyte *pc) +int __glXDisp_GetSeparableFilter(__GLXclientState *cl, GLbyte *pc) +{ + const GLXContextTag tag = __GLX_GET_SINGLE_CONTEXT_TAG(pc); + + return GetSeparableFilter(cl, pc + __GLX_SINGLE_HDR_SIZE, tag); +} + +int __glXDisp_GetSeparableFilterEXT(__GLXclientState *cl, GLbyte *pc) +{ + const GLXContextTag tag = __GLX_GET_VENDPRIV_CONTEXT_TAG(pc); + + return GetSeparableFilter(cl, pc + __GLX_VENDPRIV_HDR_SIZE, tag); +} + +static int GetConvolutionFilter(__GLXclientState *cl, GLbyte *pc, + GLXContextTag tag) { GLint compsize; GLenum format, type, target; @@ -271,22 +285,23 @@ int __glXDisp_GetConvolutionFilter(__GLXclientState *cl, GLbyte *pc) char *answer, answerBuffer[200]; GLint width=0, height=0; - cx = __glXForceCurrent(cl, __GLX_GET_SINGLE_CONTEXT_TAG(pc), &error); + cx = __glXForceCurrent(cl, tag, &error); if (!cx) { return error; } - pc += __GLX_SINGLE_HDR_SIZE; format = *(GLenum *)(pc + 4); type = *(GLenum *)(pc + 8); target = *(GLenum *)(pc + 0); swapBytes = *(GLboolean *)(pc + 12); - CALL_GetConvolutionParameteriv( GET_DISPATCH(), (target, GL_CONVOLUTION_WIDTH, &width) ); + CALL_GetConvolutionParameteriv(GET_DISPATCH(), + (target, GL_CONVOLUTION_WIDTH, &width)); if (target == GL_CONVOLUTION_1D) { height = 1; } else { - CALL_GetConvolutionParameteriv( GET_DISPATCH(), (target, GL_CONVOLUTION_HEIGHT, &height) ); + CALL_GetConvolutionParameteriv(GET_DISPATCH(), + (target, GL_CONVOLUTION_HEIGHT, &height)); } /* * The two queries above might fail if we're in a state where queries @@ -295,7 +310,7 @@ int __glXDisp_GetConvolutionFilter(__GLXclientState *cl, GLbyte *pc) compsize = __glGetTexImage_size(target,1,format,type,width,height,1); if (compsize < 0) compsize = 0; - CALL_PixelStorei( GET_DISPATCH(), (GL_PACK_SWAP_BYTES, swapBytes) ); + CALL_PixelStorei(GET_DISPATCH(), (GL_PACK_SWAP_BYTES, swapBytes)); __GLX_GET_ANSWER_BUFFER(answer,cl,compsize,1); __glXClearErrorOccured(); CALL_GetConvolutionFilter( GET_DISPATCH(), ( @@ -319,7 +334,21 @@ int __glXDisp_GetConvolutionFilter(__GLXclientState *cl, GLbyte *pc) return Success; } -int __glXDisp_GetHistogram(__GLXclientState *cl, GLbyte *pc) +int __glXDisp_GetConvolutionFilter(__GLXclientState *cl, GLbyte *pc) +{ + const GLXContextTag tag = __GLX_GET_SINGLE_CONTEXT_TAG(pc); + + return GetConvolutionFilter(cl, pc + __GLX_SINGLE_HDR_SIZE, tag); +} + +int __glXDisp_GetConvolutionFilterEXT(__GLXclientState *cl, GLbyte *pc) +{ + const GLXContextTag tag = __GLX_GET_VENDPRIV_CONTEXT_TAG(pc); + + return GetConvolutionFilter(cl, pc + __GLX_VENDPRIV_HDR_SIZE, tag); +} + +static int GetHistogram(__GLXclientState *cl, GLbyte *pc, GLXContextTag tag) { GLint compsize; GLenum format, type, target; @@ -330,19 +359,19 @@ int __glXDisp_GetHistogram(__GLXclientState *cl, GLbyte *pc) char *answer, answerBuffer[200]; GLint width=0; - cx = __glXForceCurrent(cl, __GLX_GET_SINGLE_CONTEXT_TAG(pc), &error); + cx = __glXForceCurrent(cl, tag, &error); if (!cx) { return error; } - pc += __GLX_SINGLE_HDR_SIZE; format = *(GLenum *)(pc + 4); type = *(GLenum *)(pc + 8); target = *(GLenum *)(pc + 0); swapBytes = *(GLboolean *)(pc + 12); reset = *(GLboolean *)(pc + 13); - CALL_GetHistogramParameteriv( GET_DISPATCH(), (target, GL_HISTOGRAM_WIDTH, &width) ); + CALL_GetHistogramParameteriv(GET_DISPATCH(), + (target, GL_HISTOGRAM_WIDTH, &width)); /* * The one query above might fail if we're in a state where queries * are illegal, but then width would still be zero anyway. @@ -350,10 +379,10 @@ int __glXDisp_GetHistogram(__GLXclientState *cl, GLbyte *pc) compsize = __glGetTexImage_size(target,1,format,type,width,1,1); if (compsize < 0) compsize = 0; - CALL_PixelStorei( GET_DISPATCH(), (GL_PACK_SWAP_BYTES, swapBytes) ); + CALL_PixelStorei(GET_DISPATCH(), (GL_PACK_SWAP_BYTES, swapBytes)); __GLX_GET_ANSWER_BUFFER(answer,cl,compsize,1); __glXClearErrorOccured(); - CALL_GetHistogram( GET_DISPATCH(), (target, reset, format, type, answer) ); + CALL_GetHistogram(GET_DISPATCH(), (target, reset, format, type, answer)); if (__glXErrorOccured()) { __GLX_BEGIN_REPLY(0); @@ -368,7 +397,21 @@ int __glXDisp_GetHistogram(__GLXclientState *cl, GLbyte *pc) return Success; } -int __glXDisp_GetMinmax(__GLXclientState *cl, GLbyte *pc) +int __glXDisp_GetHistogram(__GLXclientState *cl, GLbyte *pc) +{ + const GLXContextTag tag = __GLX_GET_SINGLE_CONTEXT_TAG(pc); + + return GetHistogram(cl, pc + __GLX_SINGLE_HDR_SIZE, tag); +} + +int __glXDisp_GetHistogramEXT(__GLXclientState *cl, GLbyte *pc) +{ + const GLXContextTag tag = __GLX_GET_VENDPRIV_CONTEXT_TAG(pc); + + return GetHistogram(cl, pc + __GLX_VENDPRIV_HDR_SIZE, tag); +} + +static int GetMinmax(__GLXclientState *cl, GLbyte *pc, GLXContextTag tag) { GLint compsize; GLenum format, type, target; @@ -378,12 +421,11 @@ int __glXDisp_GetMinmax(__GLXclientState *cl, GLbyte *pc) int error; char *answer, answerBuffer[200]; - cx = __glXForceCurrent(cl, __GLX_GET_SINGLE_CONTEXT_TAG(pc), &error); + cx = __glXForceCurrent(cl, tag, &error); if (!cx) { return error; } - pc += __GLX_SINGLE_HDR_SIZE; format = *(GLenum *)(pc + 4); type = *(GLenum *)(pc + 8); target = *(GLenum *)(pc + 0); @@ -393,10 +435,10 @@ int __glXDisp_GetMinmax(__GLXclientState *cl, GLbyte *pc) compsize = __glGetTexImage_size(target,1,format,type,2,1,1); if (compsize < 0) compsize = 0; - CALL_PixelStorei( GET_DISPATCH(), (GL_PACK_SWAP_BYTES, swapBytes) ); + CALL_PixelStorei(GET_DISPATCH(), (GL_PACK_SWAP_BYTES, swapBytes)); __GLX_GET_ANSWER_BUFFER(answer,cl,compsize,1); __glXClearErrorOccured(); - CALL_GetMinmax( GET_DISPATCH(), (target, reset, format, type, answer) ); + CALL_GetMinmax(GET_DISPATCH(), (target, reset, format, type, answer)); if (__glXErrorOccured()) { __GLX_BEGIN_REPLY(0); @@ -410,7 +452,21 @@ int __glXDisp_GetMinmax(__GLXclientState *cl, GLbyte *pc) return Success; } -int __glXDisp_GetColorTable(__GLXclientState *cl, GLbyte *pc) +int __glXDisp_GetMinmax(__GLXclientState *cl, GLbyte *pc) +{ + const GLXContextTag tag = __GLX_GET_SINGLE_CONTEXT_TAG(pc); + + return GetMinmax(cl, pc + __GLX_SINGLE_HDR_SIZE, tag); +} + +int __glXDisp_GetMinmaxEXT(__GLXclientState *cl, GLbyte *pc) +{ + const GLXContextTag tag = __GLX_GET_VENDPRIV_CONTEXT_TAG(pc); + + return GetMinmax(cl, pc + __GLX_VENDPRIV_HDR_SIZE, tag); +} + +static int GetColorTable(__GLXclientState *cl, GLbyte *pc, GLXContextTag tag) { GLint compsize; GLenum format, type, target; @@ -421,18 +477,18 @@ int __glXDisp_GetColorTable(__GLXclientState *cl, GLbyte *pc) char *answer, answerBuffer[200]; GLint width=0; - cx = __glXForceCurrent(cl, __GLX_GET_SINGLE_CONTEXT_TAG(pc), &error); + cx = __glXForceCurrent(cl, tag, &error); if (!cx) { return error; } - pc += __GLX_SINGLE_HDR_SIZE; target = *(GLenum *)(pc + 0); format = *(GLenum *)(pc + 4); type = *(GLenum *)(pc + 8); swapBytes = *(GLboolean *)(pc + 12); - CALL_GetColorTableParameteriv( GET_DISPATCH(), (target, GL_COLOR_TABLE_WIDTH, &width) ); + CALL_GetColorTableParameteriv(GET_DISPATCH(), + (target, GL_COLOR_TABLE_WIDTH, &width)); /* * The one query above might fail if we're in a state where queries * are illegal, but then width would still be zero anyway. @@ -440,7 +496,7 @@ int __glXDisp_GetColorTable(__GLXclientState *cl, GLbyte *pc) compsize = __glGetTexImage_size(target,1,format,type,width,1,1); if (compsize < 0) compsize = 0; - CALL_PixelStorei( GET_DISPATCH(), (GL_PACK_SWAP_BYTES, swapBytes) ); + CALL_PixelStorei(GET_DISPATCH(), (GL_PACK_SWAP_BYTES, swapBytes)); __GLX_GET_ANSWER_BUFFER(answer,cl,compsize,1); __glXClearErrorOccured(); CALL_GetColorTable( GET_DISPATCH(), ( @@ -463,60 +519,16 @@ int __glXDisp_GetColorTable(__GLXclientState *cl, GLbyte *pc) return Success; } +int __glXDisp_GetColorTable(__GLXclientState *cl, GLbyte *pc) +{ + const GLXContextTag tag = __GLX_GET_SINGLE_CONTEXT_TAG(pc); + + return GetColorTable(cl, pc + __GLX_SINGLE_HDR_SIZE, tag); +} + int __glXDisp_GetColorTableSGI(__GLXclientState *cl, GLbyte *pc) { - GLint compsize; - GLenum format, type, target; - GLboolean swapBytes; - __GLXcontext *cx; - ClientPtr client = cl->client; - int error; - char *answer, answerBuffer[200]; - GLint width=0; + const GLXContextTag tag = __GLX_GET_VENDPRIV_CONTEXT_TAG(pc); - cx = __glXForceCurrent(cl, __GLX_GET_SINGLE_CONTEXT_TAG(pc), &error); - if (!cx) { - return error; - } - - pc += __GLX_VENDPRIV_HDR_SIZE; - target = *(GLenum *)(pc + 0); - format = *(GLenum *)(pc + 4); - type = *(GLenum *)(pc + 8); - swapBytes = *(GLboolean *)(pc + 12); - - CALL_GetColorTableParameterivSGI( GET_DISPATCH(), (target, GL_COLOR_TABLE_WIDTH, &width) ); - /* - * The one query above might fail if we're in a state where queries - * are illegal, but then width would still be zero anyway. - */ - compsize = __glGetTexImage_size(target,1,format,type,width,1,1); - if (compsize < 0) compsize = 0; - - CALL_PixelStorei( GET_DISPATCH(), (GL_PACK_SWAP_BYTES, swapBytes) ); - __GLX_GET_ANSWER_BUFFER(answer,cl,compsize,1); - __glXClearErrorOccured(); - CALL_GetColorTableSGI( GET_DISPATCH(), ( - *(GLenum *)(pc + 0), - *(GLenum *)(pc + 4), - *(GLenum *)(pc + 8), - answer - ) ); - - if (__glXErrorOccured()) { - __GLX_BEGIN_REPLY(0); - __GLX_SEND_HEADER(); - } else { - __GLX_BEGIN_REPLY(compsize); - ((xGLXGetColorTableReply *)&__glXReply)->width = width; - __GLX_SEND_HEADER(); - __GLX_SEND_VOID_ARRAY(compsize); - } - - return Success; -} - -int __glXDisp_GetCompressedTexImageARB(__GLXclientState *cl, GLbyte *pc) -{ - return BadRequest; + return GetColorTable(cl, pc + __GLX_VENDPRIV_HDR_SIZE, tag); } diff --git a/GL/glx/singlepixswap.c b/GL/glx/singlepixswap.c index d5510b9c0..032b42765 100644 --- a/GL/glx/singlepixswap.c +++ b/GL/glx/singlepixswap.c @@ -219,7 +219,7 @@ int __glXDispSwap_GetPolygonStipple(__GLXclientState *cl, GLbyte *pc) return Success; } -int __glXDispSwap_GetSeparableFilter(__GLXclientState *cl, GLbyte *pc) +static int GetSeparableFilter(__GLXclientState *cl, GLbyte *pc, GLXContextTag tag) { GLint compsize, compsize2; GLenum format, type, target; @@ -231,12 +231,11 @@ int __glXDispSwap_GetSeparableFilter(__GLXclientState *cl, GLbyte *pc) char *answer, answerBuffer[200]; GLint width=0, height=0; - cx = __glXForceCurrent(cl, __GLX_GET_SINGLE_CONTEXT_TAG(pc), &error); + cx = __glXForceCurrent(cl, tag, &error); if (!cx) { return error; } - pc += __GLX_SINGLE_HDR_SIZE; __GLX_SWAP_INT(pc+0); __GLX_SWAP_INT(pc+4); __GLX_SWAP_INT(pc+8); @@ -291,7 +290,21 @@ int __glXDispSwap_GetSeparableFilter(__GLXclientState *cl, GLbyte *pc) return Success; } -int __glXDispSwap_GetConvolutionFilter(__GLXclientState *cl, GLbyte *pc) +int __glXDispSwap_GetSeparableFilter(__GLXclientState *cl, GLbyte *pc) +{ + const GLXContextTag tag = __GLX_GET_SINGLE_CONTEXT_TAG(pc); + + return GetSeparableFilter(cl, pc + __GLX_SINGLE_HDR_SIZE, tag); +} + +int __glXDispSwap_GetSeparableFilterEXT(__GLXclientState *cl, GLbyte *pc) +{ + const GLXContextTag tag = __GLX_GET_VENDPRIV_CONTEXT_TAG(pc); + + return GetSeparableFilter(cl, pc + __GLX_VENDPRIV_HDR_SIZE, tag); +} + +static int GetConvolutionFilter(__GLXclientState *cl, GLbyte *pc, GLXContextTag tag) { GLint compsize; GLenum format, type, target; @@ -303,12 +316,11 @@ int __glXDispSwap_GetConvolutionFilter(__GLXclientState *cl, GLbyte *pc) char *answer, answerBuffer[200]; GLint width=0, height=0; - cx = __glXForceCurrent(cl, __GLX_GET_SINGLE_CONTEXT_TAG(pc), &error); + cx = __glXForceCurrent(cl, tag, &error); if (!cx) { return error; } - pc += __GLX_SINGLE_HDR_SIZE; __GLX_SWAP_INT(pc+0); __GLX_SWAP_INT(pc+4); __GLX_SWAP_INT(pc+8); @@ -357,7 +369,21 @@ int __glXDispSwap_GetConvolutionFilter(__GLXclientState *cl, GLbyte *pc) return Success; } -int __glXDispSwap_GetHistogram(__GLXclientState *cl, GLbyte *pc) +int __glXDispSwap_GetConvolutionFilter(__GLXclientState *cl, GLbyte *pc) +{ + const GLXContextTag tag = __GLX_GET_SINGLE_CONTEXT_TAG(pc); + + return GetConvolutionFilter(cl, pc + __GLX_SINGLE_HDR_SIZE, tag); +} + +int __glXDispSwap_GetConvolutionFilterEXT(__GLXclientState *cl, GLbyte *pc) +{ + const GLXContextTag tag = __GLX_GET_VENDPRIV_CONTEXT_TAG(pc); + + return GetConvolutionFilter(cl, pc + __GLX_VENDPRIV_HDR_SIZE, tag); +} + +static int GetHistogram(__GLXclientState *cl, GLbyte *pc, GLXContextTag tag) { GLint compsize; GLenum format, type, target; @@ -369,12 +395,11 @@ int __glXDispSwap_GetHistogram(__GLXclientState *cl, GLbyte *pc) char *answer, answerBuffer[200]; GLint width=0; - cx = __glXForceCurrent(cl, __GLX_GET_SINGLE_CONTEXT_TAG(pc), &error); + cx = __glXForceCurrent(cl, tag, &error); if (!cx) { return error; } - pc += __GLX_SINGLE_HDR_SIZE; __GLX_SWAP_INT(pc+0); __GLX_SWAP_INT(pc+4); __GLX_SWAP_INT(pc+8); @@ -412,7 +437,21 @@ int __glXDispSwap_GetHistogram(__GLXclientState *cl, GLbyte *pc) return Success; } -int __glXDispSwap_GetMinmax(__GLXclientState *cl, GLbyte *pc) +int __glXDispSwap_GetHistogram(__GLXclientState *cl, GLbyte *pc) +{ + const GLXContextTag tag = __GLX_GET_SINGLE_CONTEXT_TAG(pc); + + return GetHistogram(cl, pc + __GLX_SINGLE_HDR_SIZE, tag); +} + +int __glXDispSwap_GetHistogramEXT(__GLXclientState *cl, GLbyte *pc) +{ + const GLXContextTag tag = __GLX_GET_VENDPRIV_CONTEXT_TAG(pc); + + return GetHistogram(cl, pc + __GLX_VENDPRIV_HDR_SIZE, tag); +} + +static int GetMinmax(__GLXclientState *cl, GLbyte *pc, GLXContextTag tag) { GLint compsize; GLenum format, type, target; @@ -423,12 +462,11 @@ int __glXDispSwap_GetMinmax(__GLXclientState *cl, GLbyte *pc) __GLX_DECLARE_SWAP_VARIABLES; char *answer, answerBuffer[200]; - cx = __glXForceCurrent(cl, __GLX_GET_SINGLE_CONTEXT_TAG(pc), &error); + cx = __glXForceCurrent(cl, tag, &error); if (!cx) { return error; } - pc += __GLX_SINGLE_HDR_SIZE; __GLX_SWAP_INT(pc+0); __GLX_SWAP_INT(pc+4); __GLX_SWAP_INT(pc+8); @@ -459,7 +497,21 @@ int __glXDispSwap_GetMinmax(__GLXclientState *cl, GLbyte *pc) return Success; } -int __glXDispSwap_GetColorTable(__GLXclientState *cl, GLbyte *pc) +int __glXDispSwap_GetMinmax(__GLXclientState *cl, GLbyte *pc) +{ + const GLXContextTag tag = __GLX_GET_SINGLE_CONTEXT_TAG(pc); + + return GetMinmax(cl, pc + __GLX_SINGLE_HDR_SIZE, tag); +} + +int __glXDispSwap_GetMinmaxEXT(__GLXclientState *cl, GLbyte *pc) +{ + const GLXContextTag tag = __GLX_GET_VENDPRIV_CONTEXT_TAG(pc); + + return GetMinmax(cl, pc + __GLX_VENDPRIV_HDR_SIZE, tag); +} + +static int GetColorTable(__GLXclientState *cl, GLbyte *pc, GLXContextTag tag) { GLint compsize; GLenum format, type, target; @@ -471,12 +523,11 @@ int __glXDispSwap_GetColorTable(__GLXclientState *cl, GLbyte *pc) char *answer, answerBuffer[200]; GLint width=0; - cx = __glXForceCurrent(cl, __GLX_GET_SINGLE_CONTEXT_TAG(pc), &error); + cx = __glXForceCurrent(cl, tag, &error); if (!cx) { return error; } - pc += __GLX_SINGLE_HDR_SIZE; __GLX_SWAP_INT(pc+0); __GLX_SWAP_INT(pc+4); __GLX_SWAP_INT(pc+8); @@ -518,66 +569,16 @@ int __glXDispSwap_GetColorTable(__GLXclientState *cl, GLbyte *pc) return Success; } +int __glXDispSwap_GetColorTable(__GLXclientState *cl, GLbyte *pc) +{ + const GLXContextTag tag = __GLX_GET_SINGLE_CONTEXT_TAG(pc); + + return GetColorTable(cl, pc + __GLX_SINGLE_HDR_SIZE, tag); +} + int __glXDispSwap_GetColorTableSGI(__GLXclientState *cl, GLbyte *pc) { - GLint compsize; - GLenum format, type, target; - GLboolean swapBytes; - __GLXcontext *cx; - ClientPtr client = cl->client; - int error; - __GLX_DECLARE_SWAP_VARIABLES; - char *answer, answerBuffer[200]; - GLint width=0; + const GLXContextTag tag = __GLX_GET_VENDPRIV_CONTEXT_TAG(pc); - cx = __glXForceCurrent(cl, __GLX_GET_SINGLE_CONTEXT_TAG(pc), &error); - if (!cx) { - return error; - } - - pc += __GLX_VENDPRIV_HDR_SIZE; - __GLX_SWAP_INT(pc+0); - __GLX_SWAP_INT(pc+4); - __GLX_SWAP_INT(pc+8); - - format = *(GLenum *)(pc + 4); - type = *(GLenum *)(pc + 8); - target = *(GLenum *)(pc + 0); - swapBytes = *(GLboolean *)(pc + 12); - - CALL_GetColorTableParameterivSGI( GET_DISPATCH(), (target, GL_COLOR_TABLE_WIDTH, &width) ); - /* - * The one query above might fail if we're in a state where queries - * are illegal, but then width would still be zero anyway. - */ - compsize = __glGetTexImage_size(target,1,format,type,width,1,1); - if (compsize < 0) compsize = 0; - - CALL_PixelStorei( GET_DISPATCH(), (GL_PACK_SWAP_BYTES, !swapBytes) ); - __GLX_GET_ANSWER_BUFFER(answer,cl,compsize,1); - __glXClearErrorOccured(); - CALL_GetColorTableSGI( GET_DISPATCH(), ( - *(GLenum *)(pc + 0), - *(GLenum *)(pc + 4), - *(GLenum *)(pc + 8), - answer - ) ); - - if (__glXErrorOccured()) { - __GLX_BEGIN_REPLY(0); - __GLX_SWAP_REPLY_HEADER(); - } else { - __GLX_BEGIN_REPLY(compsize); - __GLX_SWAP_REPLY_HEADER(); - __GLX_SWAP_INT(&width); - ((xGLXGetColorTableReply *)&__glXReply)->width = width; - __GLX_SEND_VOID_ARRAY(compsize); - } - - return Success; -} - -int __glXDispSwap_GetCompressedTexImageARB(__GLXclientState *cl, GLbyte *pc) -{ - return BadRequest; + return GetColorTable(cl, pc + __GLX_VENDPRIV_HDR_SIZE, tag); } diff --git a/GL/glx/swap_interval.c b/GL/glx/swap_interval.c new file mode 100644 index 000000000..bcc1c4793 --- /dev/null +++ b/GL/glx/swap_interval.c @@ -0,0 +1,105 @@ +/* + * (C) Copyright IBM Corporation 2006 + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#define NEED_REPLIES +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#include "glxserver.h" +#include "glxutil.h" +#include "glxext.h" +#include "singlesize.h" +#include "unpack.h" +#include "indirect_size_get.h" +#include "indirect_dispatch.h" +#include "glapitable.h" +#include "glapi.h" +#include "glthread.h" +#include "dispatch.h" +#include "glapioffsets.h" + +#ifdef __linux__ +#include +#elif defined(__OpenBSD__) +#include +#define bswap_16 __swap16 +#define bswap_32 __swap32 +#define bswap_64 __swap64 +#else +#include +#define bswap_16 bswap16 +#define bswap_32 bswap32 +#define bswap_64 bswap64 +#endif + +static int DoSwapInterval(__GLXclientState *cl, GLbyte *pc, int do_swap); + +int DoSwapInterval(__GLXclientState *cl, GLbyte *pc, int do_swap) +{ + xGLXVendorPrivateReq * const req = (xGLXVendorPrivateReq *) pc; + ClientPtr client = cl->client; + const GLXContextTag tag = req->contextTag; + __GLXcontext *cx; + GLint interval; + + + cx = __glXLookupContextByTag(cl, tag); + + LogMessage(X_ERROR, "%s: cx = %p, GLX screen = %p\n", __func__, + cx, (cx == NULL) ? NULL : cx->pGlxScreen); + if ((cx == NULL) || (cx->pGlxScreen == NULL)) { + client->errorValue = tag; + return __glXError(GLXBadContext); + } + + if (cx->pGlxScreen->swapInterval == NULL) { + LogMessage(X_ERROR, "AIGLX: cx->pGlxScreen->swapInterval == NULL\n"); + client->errorValue = tag; + return __glXError(GLXUnsupportedPrivateRequest); + } + + if (cx->drawPriv == NULL) { + client->errorValue = tag; + return __glXError(GLXBadDrawable); + } + + pc += __GLX_VENDPRIV_HDR_SIZE; + interval = (do_swap) + ? bswap_32(*(int *)(pc + 0)) + : *(int *)(pc + 0); + + (void) (*cx->pGlxScreen->swapInterval)(cx->drawPriv, interval); + return Success; +} + +int __glXDisp_SwapIntervalSGI(__GLXclientState *cl, GLbyte *pc) +{ + return DoSwapInterval(cl, pc, 0); +} + +int __glXDispSwap_SwapIntervalSGI(__GLXclientState *cl, GLbyte *pc) +{ + return DoSwapInterval(cl, pc, 1); +} diff --git a/GL/symlink-mesa.sh b/GL/symlink-mesa.sh index 7b5ed5c3d..c14c683c6 100755 --- a/GL/symlink-mesa.sh +++ b/GL/symlink-mesa.sh @@ -62,414 +62,99 @@ symlink_mesa_glapi() { src_dir src/mesa/glapi dst_dir mesa/glapi - action dispatch.h - action glapi.c - action glapi.h - action glapioffsets.h - action glapitable.h - action glapitemp.h - action glprocs.h - action glthread.c - action glthread.h + for src in $REAL_SRC_DIR/*.c $REAL_SRC_DIR/*.h; do + action `basename $src` + done } symlink_mesa_main() { src_dir src/mesa/main dst_dir mesa/main - action accum.c - action accum.h - action api_arrayelt.c - action api_arrayelt.h - action api_eval.h - action api_loopback.c - action api_loopback.h - action api_noop.c - action api_noop.h - action api_validate.c - action api_validate.h - action arrayobj.c - action arrayobj.h - action attrib.c - action attrib.h - action bitset.h - action blend.c - action blend.h - action bufferobj.c - action bufferobj.h - action buffers.c - action buffers.h - action clip.c - action clip.h - action colormac.h - action colortab.c - action colortab.h - action config.h - action context.c - action context.h - action convolve.c - action convolve.h - action dd.h - action debug.c - action debug.h - action depth.c - action depth.h - action depthstencil.c - action depthstencil.h - action dlist.c - action dlist.h - action drawpix.c - action drawpix.h - action enable.c - action enable.h - action enums.c - action enums.h - action eval.c - action eval.h - action execmem.c - action extensions.c - action extensions.h - action fbobject.c - action fbobject.h - action feedback.c - action feedback.h - action fog.c - action fog.h - action framebuffer.c - action framebuffer.h - action get.c - action get.h - action getstring.c - action glheader.h - action hash.c - action hash.h - action hint.c - action hint.h - action histogram.c - action histogram.h - action image.c - action image.h - action imports.c - action imports.h - action light.c - action light.h - action lines.c - action lines.h - action macros.h - action matrix.c - action matrix.h - action mm.c - action mm.h - action mtypes.h - action occlude.c - action occlude.h - action pixel.c - action pixel.h - action points.c - action points.h - action polygon.c - action polygon.h - action rastpos.c - action rastpos.h - action rbadaptors.c - action rbadaptors.h - action renderbuffer.c - action renderbuffer.h - action simple_list.h - action state.c - action state.h - action stencil.c - action stencil.h - action texcompress.c - action texcompress.h - action texcompress_fxt1.c - action texcompress_s3tc.c - action texenvprogram.c - action texenvprogram.h - action texformat.c - action texformat.h - action texformat_tmp.h - action teximage.c - action teximage.h - action texobj.c - action texobj.h - action texrender.c - action texrender.h - action texstate.c - action texstate.h - action texstore.c - action texstore.h - action varray.c - action varray.h - action version.h - action vsnprintf.c - action vtxfmt.c - action vtxfmt.h - action vtxfmt_tmp.h + for src in $REAL_SRC_DIR/*.c $REAL_SRC_DIR/*.h; do + action `basename $src` + done } symlink_mesa_math() { src_dir src/mesa/math dst_dir mesa/math - action m_clip_tmp.h - action m_copy_tmp.h - action m_debug.h - action m_debug_clip.c - action m_debug_norm.c - action m_debug_util.h - action m_debug_xform.c - action m_dotprod_tmp.h - action m_eval.c - action m_eval.h - action m_matrix.c - action m_matrix.h - action m_norm_tmp.h - action m_trans_tmp.h - action m_translate.c - action m_translate.h - action m_vector.c - action m_vector.h - action m_xform.c - action m_xform.h - action m_xform_tmp.h - action mathmod.h + for src in $REAL_SRC_DIR/*.c $REAL_SRC_DIR/*.h; do + action `basename $src` + done } symlink_mesa_ac() { src_dir src/mesa/array_cache dst_dir mesa/array_cache - action ac_context.c - action ac_context.h - action ac_import.c - action acache.h + for src in $REAL_SRC_DIR/*.c $REAL_SRC_DIR/*.h; do + action `basename $src` + done } symlink_mesa_swrast() { src_dir src/mesa/swrast dst_dir mesa/swrast - action s_aaline.c - action s_aaline.h - action s_aalinetemp.h - action s_aatriangle.c - action s_aatriangle.h - action s_aatritemp.h - action s_accum.c - action s_accum.h - action s_alpha.c - action s_alpha.h - action s_arbshader.c - action s_arbshader.h - action s_atifragshader.c - action s_atifragshader.h - action s_bitmap.c - action s_blend.c - action s_blend.h - action s_blit.c - action s_buffers.c - action s_context.c - action s_context.h - action s_copypix.c - action s_depth.c - action s_depth.h - action s_drawpix.c - action s_drawpix.h - action s_feedback.c - action s_feedback.h - action s_fog.c - action s_fog.h - action s_imaging.c - action s_lines.c - action s_lines.h - action s_linetemp.h - action s_logic.c - action s_logic.h - action s_masking.c - action s_masking.h - action s_nvfragprog.c - action s_nvfragprog.h - action s_points.c - action s_points.h - action s_pointtemp.h - action s_readpix.c - action s_span.c - action s_span.h - action s_spantemp.h - action s_stencil.c - action s_stencil.h - action s_texcombine.c - action s_texcombine.h - action s_texfilter.c - action s_texfilter.h - action s_texstore.c - action s_triangle.c - action s_triangle.h - action s_trispan.h - action s_tritemp.h - action s_zoom.c - action s_zoom.h - action swrast.h + for src in $REAL_SRC_DIR/*.c $REAL_SRC_DIR/*.h; do + action `basename $src` + done } symlink_mesa_ss() { src_dir src/mesa/swrast_setup dst_dir mesa/swrast_setup - action ss_context.c - action ss_context.h - action ss_triangle.c - action ss_triangle.h - action ss_tritmp.h - action ss_vb.h - action swrast_setup.h + for src in $REAL_SRC_DIR/*.c $REAL_SRC_DIR/*.h; do + action `basename $src` + done } symlink_mesa_tnl() { src_dir src/mesa/tnl dst_dir mesa/tnl - action t_array_api.c - action t_array_api.h - action t_array_import.c - action t_array_import.h - action t_context.c - action t_context.h - action t_pipeline.c - action t_pipeline.h - action t_save_api.c - action t_save_api.h - action t_save_loopback.c - action t_save_playback.c - action t_vb_arbprogram.c - action t_vb_arbprogram.h - action t_vb_arbprogram_sse.c - action t_vb_arbshader.c - action t_vb_cliptmp.h - action t_vb_cull.c - action t_vb_fog.c - action t_vb_light.c - action t_vb_lighttmp.h - action t_vb_normals.c - action t_vb_points.c - action t_vb_program.c - action t_vb_render.c - action t_vb_rendertmp.h - action t_vb_texgen.c - action t_vb_texmat.c - action t_vb_vertex.c - action t_vertex.c - action t_vertex.h - action t_vertex_generic.c - action t_vertex_sse.c - action t_vp_build.c - action t_vp_build.h - action t_vtx_api.c - action t_vtx_api.h - action t_vtx_eval.c - action t_vtx_exec.c - action t_vtx_generic.c - action t_vtx_x86.c - action tnl.h + for src in $REAL_SRC_DIR/*.c $REAL_SRC_DIR/*.h; do + action `basename $src` + done } symlink_mesa_shader() { src_dir src/mesa/shader dst_dir mesa/shader - action arbprogparse.c - action arbprogparse.h - action arbprogram.c - action arbprogram.h - action arbprogram_syn.h - action atifragshader.c - action atifragshader.h - action nvfragparse.c - action nvfragparse.h - action nvprogram.c - action nvprogram.h - action nvvertexec.c - action nvvertexec.h - action nvvertparse.c - action nvvertparse.h - action program.c - action program.h - action program_instruction.h - action shaderobjects.c - action shaderobjects.h - action shaderobjects_3dlabs.c - action shaderobjects_3dlabs.h + for src in $REAL_SRC_DIR/*.c $REAL_SRC_DIR/*.h; do + action `basename $src` + done } symlink_mesa_shader_grammar() { src_dir src/mesa/shader/grammar dst_dir mesa/shader/grammar - action grammar.c - action grammar.h - action grammar_syn.h - action grammar_mesa.c - action grammar_mesa.h + for src in $REAL_SRC_DIR/*.c $REAL_SRC_DIR/*.h; do + action `basename $src` + done } symlink_mesa_shader_slang() { src_dir src/mesa/shader/slang dst_dir mesa/shader/slang - action slang_analyse.c - action slang_analyse.h - action slang_assemble.c - action slang_assemble.h - action slang_assemble_assignment.c - action slang_assemble_assignment.h - action slang_assemble_conditional.c - action slang_assemble_conditional.h - action slang_assemble_constructor.c - action slang_assemble_constructor.h - action slang_assemble_typeinfo.c - action slang_assemble_typeinfo.h - action slang_compile.c - action slang_compile.h - action slang_compile_function.c - action slang_compile_function.h - action slang_compile_operation.c - action slang_compile_operation.h - action slang_compile_struct.c - action slang_compile_struct.h - action slang_compile_variable.c - action slang_compile_variable.h - action slang_execute.c - action slang_execute.h - action slang_execute_x86.c - action slang_export.c - action slang_export.h - action slang_library_noise.c - action slang_library_noise.h - action slang_library_texsample.c - action slang_library_texsample.h - action slang_link.c - action slang_link.h - action slang_mesa.h - action slang_preprocess.c - action slang_preprocess.h - action slang_storage.c - action slang_storage.h - action slang_utility.c - action slang_utility.h - action traverse_wrap.h + for src in $REAL_SRC_DIR/*.c $REAL_SRC_DIR/*.h; do + action `basename $src` + done } symlink_mesa_shader_slang_library() { src_dir src/mesa/shader/slang/library dst_dir mesa/shader/slang/library - action slang_common_builtin_gc.h - action slang_core_gc.h - action slang_fragment_builtin_gc.h - action slang_shader_syn.h - action slang_pp_version_syn.h - action slang_vertex_builtin_gc.h + for src in $REAL_SRC_DIR/*.c $REAL_SRC_DIR/*.h; do + action `basename $src` + done } symlink_mesa_x() { diff --git a/Xext/Makefile.am b/Xext/Makefile.am index ad3f98edf..6ea3d7445 100644 --- a/Xext/Makefile.am +++ b/Xext/Makefile.am @@ -33,6 +33,10 @@ MODULE_SRCS = \ sync.c \ xcmisc.c +# Extra configuration files ship with some extensions +SERVERCONFIGdir = $(libdir)/xserver +SERVERCONFIG_DATA = + # Optional sources included if extension enabled by configure.ac rules # MIT Shared Memory extension @@ -65,16 +69,28 @@ if XINERAMA BUILTIN_SRCS += $(XINERAMA_SRCS) endif +# X-ACE extension: provides hooks for building security policy extensions +# like XC-Security, X-SELinux & XTSol +XACE_SRCS = xace.c xace.h xacestr.h +if XACE +BUILTIN_SRCS += $(XACE_SRCS) +endif + # Security extension: multi-level security to protect clients from each other XCSECURITY_SRCS = security.c securitysrv.h if XCSECURITY BUILTIN_SRCS += $(XCSECURITY_SRCS) -SERVERCONFIGdir = $(libdir)/xserver -SERVERCONFIG_DATA = SecurityPolicy +SERVERCONFIG_DATA += SecurityPolicy AM_CFLAGS += -DDEFAULTPOLICYFILE=\"$(SERVERCONFIGdir)/SecurityPolicy\" endif +XCALIBRATE_SRCS = xcalibrate.c +if XCALIBRATE +BUILTIN_SRCS += $(XCALIBRATE_SRCS) +# XCalibrare needs tslib +endif + # X EVent Interception Extension: allows accessibility helpers & composite # managers to intercept events from input devices and transform as needed # before the clients see them. @@ -144,12 +160,14 @@ libXextmodule_la_SOURCES = $(MODULE_SRCS) endif EXTRA_DIST = \ - SecurityPolicy \ + $(SERVERCONFIG_DATA) \ $(MITSHM_SRCS) \ $(XV_SRCS) \ $(RES_SRCS) \ $(SCREENSAVER_SRCS) \ + $(XACE_SRCS) \ $(XCSECURITY_SRCS) \ + $(XCALIBRATE_SRCS) \ $(XINERAMA_SRCS) \ $(XEVIE_SRCS) \ $(XPRINT_SRCS) \ diff --git a/Xext/appgroup.c b/Xext/appgroup.c index b047945c0..650dc0ab8 100644 --- a/Xext/appgroup.c +++ b/Xext/appgroup.c @@ -41,6 +41,7 @@ from The Open Group. #include "servermd.h" #define _XAG_SERVER_ #include +#include "xacestr.h" #include "securitysrv.h" #include @@ -121,62 +122,11 @@ void XagClientStateChange( pointer nulldata, pointer calldata) { - SecurityAuthorizationPtr pAuth; NewClientInfoRec* pci = (NewClientInfoRec*) calldata; ClientPtr pClient = pci->client; - AppGroupPtr pAppGrp; - XID authId = 0; + AppGroupPtr pAppGrp = pClient->appgroup; int slot; - if (!pClient->appgroup) { - switch (pClient->clientState) { - - case ClientStateAuthenticating: - case ClientStateRunning: - case ClientStateCheckingSecurity: - return; - - case ClientStateInitial: - case ClientStateCheckedSecurity: - /* - * If the client is connecting via a firewall proxy (which - * uses XC-QUERY-SECURITY-1, then the authId is available - * during ClientStateCheckedSecurity, otherwise it's - * available during ClientStateInitial. - * - * Don't get it from pClient because can't guarantee the order - * of the callbacks and the security extension might not have - * plugged it in yet. - */ - authId = AuthorizationIDOfClient(pClient); - break; - - case ClientStateGone: - case ClientStateRetained: - /* - * Don't get if from AuthorizationIDOfClient because can't - * guarantee the order of the callbacks and the security - * extension may have torn down the client's private data - */ - authId = pClient->authId; - break; - } - - if (authId == None) - return; - - pAuth = (SecurityAuthorizationPtr)SecurityLookupIDByType(pClient, - authId, SecurityAuthorizationResType, SecurityReadAccess); - - if (pAuth == NULL) - return; - - for (pAppGrp = appGrpList; pAppGrp != NULL; pAppGrp = pAppGrp->next) - if (pAppGrp->appgroupId == pAuth->group) break; - } else { - pAppGrp = pClient->appgroup; - } - if (!pAppGrp) return; @@ -233,6 +183,7 @@ XagExtensionInit(INITARGS) XagResetProc, StandardMinorOpcode)) { RT_APPGROUP = CreateNewResourceType (XagAppGroupFree); + XaceRegisterCallback(XACE_AUTH_AVAIL, XagCallClientStateChange, NULL); } } @@ -799,12 +750,33 @@ void XagGetDeltaInfo( } void XagCallClientStateChange( - ClientPtr client) + CallbackListPtr *pcbl, + pointer nulldata, + pointer calldata) { - if (appGrpList) { + XaceAuthAvailRec* rec = (XaceAuthAvailRec*) calldata; + ClientPtr pClient = rec->client; + + if (!pClient->appgroup) { + SecurityAuthorizationPtr pAuth; + XID authId = rec->authId; + + /* can't use SecurityLookupIDByType here -- client + * security state hasn't been setup yet. + */ + pAuth = (SecurityAuthorizationPtr)LookupIDByType(authId, + SecurityAuthorizationResType); + if (!pAuth) + return; + + pClient->appgroup = (AppGroupPtr)LookupIDByType(pAuth->group, + RT_APPGROUP); + } + + if (pClient->appgroup) { NewClientInfoRec clientinfo; - clientinfo.client = client; + clientinfo.client = pClient; XagClientStateChange (NULL, NULL, (pointer)&clientinfo); } } diff --git a/Xext/appgroup.h b/Xext/appgroup.h index 39087fe8e..a875068fc 100644 --- a/Xext/appgroup.h +++ b/Xext/appgroup.h @@ -51,7 +51,9 @@ extern ClientPtr XagLeader( ); extern void XagCallClientStateChange( - ClientPtr /* client */ + CallbackListPtr * /* pcbl */, + pointer /* nulldata */, + pointer /* calldata */ ); extern Bool XagIsControlledRoot ( diff --git a/Xext/fontcache.c b/Xext/fontcache.c index 00a45c90e..db0348144 100644 --- a/Xext/fontcache.c +++ b/Xext/fontcache.c @@ -45,8 +45,8 @@ #include "inputstr.h" #include "servermd.h" #define _FONTCACHE_SERVER_ -#include "fontcacheP.h" -#include "fontcachstr.h" +#include +#include #include #include "swaprep.h" diff --git a/Xext/security.c b/Xext/security.c index 4684d783b..54a2b3e3f 100644 --- a/Xext/security.c +++ b/Xext/security.c @@ -36,6 +36,7 @@ in this Software without prior written authorization from The Open Group. #include "gcstruct.h" #include "colormapst.h" #include "propertyst.h" +#include "xacestr.h" #include "securitysrv.h" #include #include @@ -58,6 +59,23 @@ in this Software without prior written authorization from The Open Group. static int SecurityErrorBase; /* first Security error number */ static int SecurityEventBase; /* first Security event number */ +static int securityClientPrivateIndex; +static int securityExtnsnPrivateIndex; + +/* this is what we store as client security state */ +typedef struct { + unsigned int trustLevel; + XID authId; +} SecurityClientStateRec; + +#define STATEVAL(extnsn) \ + ((extnsn)->devPrivates[securityExtnsnPrivateIndex].val) +#define STATEPTR(client) \ + ((client)->devPrivates[securityClientPrivateIndex].ptr) +#define TRUSTLEVEL(client) \ + (((SecurityClientStateRec*)STATEPTR(client))->trustLevel) +#define AUTHID(client) \ + (((SecurityClientStateRec*)STATEPTR(client))->authId) CallbackListPtr SecurityValidateGroupCallback = NULL; /* see security.h */ @@ -65,19 +83,8 @@ RESTYPE SecurityAuthorizationResType; /* resource type for authorizations */ static RESTYPE RTEventClient; -/* Proc vectors for untrusted clients, swapped and unswapped versions. - * These are the same as the normal proc vectors except that extensions - * that haven't declared themselves secure will have ProcBadRequest plugged - * in for their major opcode dispatcher. This prevents untrusted clients - * from guessing extension major opcodes and using the extension even though - * the extension can't be listed or queried. - */ -int (*UntrustedProcVector[256])( - ClientPtr /*client*/ -); -int (*SwappedUntrustedProcVector[256])( - ClientPtr /*client*/ -); +#define CALLBACK(name) static void \ +name(CallbackListPtr *pcbl, pointer nulldata, pointer calldata) /* SecurityAudit * @@ -91,7 +98,7 @@ int (*SwappedUntrustedProcVector[256])( * Writes the message to the log file if security logging is on. */ -void +static void SecurityAudit(char *format, ...) { va_list args; @@ -164,7 +171,7 @@ SecurityDeleteAuthorization( for (i = 1; iauthId == pAuth->id)) + if (clients[i] && (AUTHID(clients[i]) == pAuth->id)) CloseDownClient(clients[i]); } @@ -318,7 +325,7 @@ ProcSecurityQueryVersion( /* paranoia: this "can't happen" because this extension is hidden * from untrusted clients, but just in case... */ - if (client->trustLevel != XSecurityClientTrusted) + if (TRUSTLEVEL(client) != XSecurityClientTrusted) return BadRequest; REQUEST_SIZE_MATCH(xSecurityQueryVersionReq); @@ -404,7 +411,7 @@ ProcSecurityGenerateAuthorization( /* paranoia: this "can't happen" because this extension is hidden * from untrusted clients, but just in case... */ - if (client->trustLevel != XSecurityClientTrusted) + if (TRUSTLEVEL(client) != XSecurityClientTrusted) return BadRequest; /* check request length */ @@ -587,7 +594,7 @@ ProcSecurityRevokeAuthorization( /* paranoia: this "can't happen" because this extension is hidden * from untrusted clients, but just in case... */ - if (client->trustLevel != XSecurityClientTrusted) + if (TRUSTLEVEL(client) != XSecurityClientTrusted) return BadRequest; REQUEST_SIZE_MATCH(xSecurityRevokeAuthorizationReq); @@ -772,12 +779,12 @@ SecurityDetermineEventPropogationLimits( * An audit message is generated if access is denied. */ -Bool -SecurityCheckDeviceAccess(client, dev, fromRequest) - ClientPtr client; - DeviceIntPtr dev; - Bool fromRequest; +CALLBACK(SecurityCheckDeviceAccess) { + XaceDeviceAccessRec *rec = (XaceDeviceAccessRec*)calldata; + ClientPtr client = rec->client; + DeviceIntPtr dev = rec->dev; + Bool fromRequest = rec->fromRequest; WindowPtr pWin, pStopWin; Bool untrusted_got_event; Bool found_event_window; @@ -785,12 +792,12 @@ SecurityCheckDeviceAccess(client, dev, fromRequest) int reqtype = 0; /* trusted clients always allowed to do anything */ - if (client->trustLevel == XSecurityClientTrusted) - return TRUE; + if (TRUSTLEVEL(client) == XSecurityClientTrusted) + return; /* device security other than keyboard is not implemented yet */ if (dev != inputInfo.keyboard) - return TRUE; + return; /* some untrusted client wants access */ @@ -805,7 +812,8 @@ SecurityCheckDeviceAccess(client, dev, fromRequest) case X_SetModifierMapping: SecurityAudit("client %d attempted request %d\n", client->index, reqtype); - return FALSE; + rec->rval = FALSE; + return; default: break; } @@ -817,7 +825,7 @@ SecurityCheckDeviceAccess(client, dev, fromRequest) if (dev->grab) { untrusted_got_event = - ((rClient(dev->grab))->trustLevel != XSecurityClientTrusted); + (TRUSTLEVEL(rClient(dev->grab)) != XSecurityClientTrusted); } else { @@ -832,7 +840,7 @@ SecurityCheckDeviceAccess(client, dev, fromRequest) { found_event_window = TRUE; client = wClient(pWin); - if (client->trustLevel != XSecurityClientTrusted) + if (TRUSTLEVEL(client) != XSecurityClientTrusted) { untrusted_got_event = TRUE; } @@ -845,7 +853,7 @@ SecurityCheckDeviceAccess(client, dev, fromRequest) if (other->mask & eventmask) { client = rClient(other); - if (client->trustLevel != XSecurityClientTrusted) + if (TRUSTLEVEL(client) != XSecurityClientTrusted) { untrusted_got_event = TRUE; break; @@ -873,8 +881,9 @@ SecurityCheckDeviceAccess(client, dev, fromRequest) else SecurityAudit("client %d attempted to access device %d (%s)\n", client->index, dev->id, devname); + rec->rval = FALSE; } - return untrusted_got_event; + return; } /* SecurityCheckDeviceAccess */ @@ -946,20 +955,22 @@ SecurityAuditResourceIDAccess( * Disallowed resource accesses are audited. */ -static pointer -SecurityCheckResourceIDAccess( - ClientPtr client, - XID id, - RESTYPE rtype, - Mask access_mode, - pointer rval) +CALLBACK(SecurityCheckResourceIDAccess) { - int cid = CLIENT_ID(id); - int reqtype = ((xReq *)client->requestBuffer)->reqType; + XaceResourceAccessRec *rec = (XaceResourceAccessRec*)calldata; + ClientPtr client = rec->client; + XID id = rec->id; + RESTYPE rtype = rec->rtype; + Mask access_mode = rec->access_mode; + pointer rval = rec->res; + int cid, reqtype; - if (SecurityUnknownAccess == access_mode) - return rval; /* for compatibility, we have to allow access */ + if (TRUSTLEVEL(client) == XSecurityClientTrusted || + SecurityUnknownAccess == access_mode) + return; /* for compatibility, we have to allow access */ + cid = CLIENT_ID(id); + reqtype = ((xReq *)client->requestBuffer)->reqType; switch (reqtype) { /* these are always allowed */ case X_QueryTree: @@ -971,7 +982,7 @@ SecurityCheckResourceIDAccess( case X_DeleteProperty: case X_RotateProperties: case X_ListProperties: - return rval; + return; default: break; } @@ -991,15 +1002,15 @@ SecurityCheckResourceIDAccess( * competing alternative for grouping clients for security purposes is to * use app groups. dpw */ - if (client->trustLevel == clients[cid]->trustLevel + if (TRUSTLEVEL(client) == TRUSTLEVEL(clients[cid]) #ifdef XAPPGROUP || (RT_COLORMAP == rtype && XagDefaultColormap (client) == (Colormap) id) #endif ) - return rval; + return; else - return SecurityAuditResourceIDAccess(client, id); + goto deny; } else /* server-owned resource - probably a default colormap or root window */ { @@ -1035,7 +1046,7 @@ SecurityCheckResourceIDAccess( ) ) { /* not an ICCCM event */ - return SecurityAuditResourceIDAccess(client, id); + goto deny; } break; } /* case X_SendEvent on root */ @@ -1053,28 +1064,31 @@ SecurityCheckResourceIDAccess( ~(PropertyChangeMask|StructureNotifyMask)) == 0) break; } - return SecurityAuditResourceIDAccess(client, id); + goto deny; } /* case X_ChangeWindowAttributes on root */ default: { /* others not allowed */ - return SecurityAuditResourceIDAccess(client, id); + goto deny; } } } /* end server-owned window or drawable */ else if (SecurityAuthorizationResType == rtype) { SecurityAuthorizationPtr pAuth = (SecurityAuthorizationPtr)rval; - if (pAuth->trustLevel != client->trustLevel) - return SecurityAuditResourceIDAccess(client, id); + if (pAuth->trustLevel != TRUSTLEVEL(client)) + goto deny; } else if (RT_COLORMAP != rtype) { /* don't allow anything else besides colormaps */ - return SecurityAuditResourceIDAccess(client, id); + goto deny; } } - return rval; + return; + deny: + SecurityAuditResourceIDAccess(client, id); + rec->rval = FALSE; /* deny access */ } /* SecurityCheckResourceIDAccess */ @@ -1093,30 +1107,32 @@ SecurityCheckResourceIDAccess( * If a new client is connecting, its authorization ID is copied to * client->authID. If this is a generated authorization, its reference * count is bumped, its timer is cancelled if it was running, and its - * trustlevel is copied to client->trustLevel. + * trustlevel is copied to TRUSTLEVEL(client). * * If a client is disconnecting and the client was using a generated * authorization, the authorization's reference count is decremented, and * if it is now zero, the timer for this authorization is started. */ -static void -SecurityClientStateCallback( - CallbackListPtr *pcbl, - pointer nulldata, - pointer calldata) +CALLBACK(SecurityClientStateCallback) { NewClientInfoRec *pci = (NewClientInfoRec *)calldata; ClientPtr client = pci->client; switch (client->clientState) { + case ClientStateInitial: + TRUSTLEVEL(serverClient) = XSecurityClientTrusted; + AUTHID(serverClient) = None; + break; + case ClientStateRunning: { XID authId = AuthorizationIDOfClient(client); SecurityAuthorizationPtr pAuth; - client->authId = authId; + TRUSTLEVEL(client) = XSecurityClientTrusted; + AUTHID(client) = authId; pAuth = (SecurityAuthorizationPtr)LookupIDByType(authId, SecurityAuthorizationResType); if (pAuth) @@ -1126,23 +1142,20 @@ SecurityClientStateCallback( { if (pAuth->timer) TimerCancel(pAuth->timer); } - client->trustLevel = pAuth->trustLevel; - if (client->trustLevel != XSecurityClientTrusted) - { - client->CheckAccess = SecurityCheckResourceIDAccess; - client->requestVector = client->swapped ? - SwappedUntrustedProcVector : UntrustedProcVector; - } + TRUSTLEVEL(client) = pAuth->trustLevel; } break; } case ClientStateGone: case ClientStateRetained: /* client disconnected */ { - XID authId = client->authId; SecurityAuthorizationPtr pAuth; - pAuth = (SecurityAuthorizationPtr)LookupIDByType(authId, + /* client may not have any state (bad authorization) */ + if (!STATEPTR(client)) + break; + + pAuth = (SecurityAuthorizationPtr)LookupIDByType(AUTHID(client), SecurityAuthorizationResType); if (pAuth) { /* it is a generated authorization */ @@ -1158,124 +1171,68 @@ SecurityClientStateCallback( } } /* SecurityClientStateCallback */ -/* SecurityCensorImage - * - * Called after pScreen->GetImage to prevent pieces or trusted windows from - * being returned in image data from an untrusted window. - * - * Arguments: - * client is the client doing the GetImage. - * pVisibleRegion is the visible region of the window. - * widthBytesLine is the width in bytes of one horizontal line in pBuf. - * pDraw is the source window. - * x, y, w, h is the rectangle of image data from pDraw in pBuf. - * format is the format of the image data in pBuf: ZPixmap or XYPixmap. - * pBuf is the image data. - * - * Returns: nothing. - * - * Side Effects: - * Any part of the rectangle (x, y, w, h) that is outside the visible - * region of the window will be destroyed (overwritten) in pBuf. - */ -void -SecurityCensorImage(client, pVisibleRegion, widthBytesLine, pDraw, x, y, w, h, - format, pBuf) - ClientPtr client; - RegionPtr pVisibleRegion; - long widthBytesLine; - DrawablePtr pDraw; - int x, y, w, h; - unsigned int format; - char * pBuf; +CALLBACK(SecurityCheckDrawableAccess) { - RegionRec imageRegion; /* region representing x,y,w,h */ - RegionRec censorRegion; /* region to obliterate */ - BoxRec imageBox; - int nRects; + XaceDrawableAccessRec *rec = (XaceDrawableAccessRec*)calldata; - imageBox.x1 = x; - imageBox.y1 = y; - imageBox.x2 = x + w; - imageBox.y2 = y + h; - REGION_INIT(pScreen, &imageRegion, &imageBox, 1); - REGION_NULL(pScreen, &censorRegion); + if (TRUSTLEVEL(rec->client) != XSecurityClientTrusted) + rec->rval = FALSE; +} - /* censorRegion = imageRegion - visibleRegion */ - REGION_SUBTRACT(pScreen, &censorRegion, &imageRegion, pVisibleRegion); - nRects = REGION_NUM_RECTS(&censorRegion); - if (nRects > 0) - { /* we have something to censor */ - GCPtr pScratchGC = NULL; - PixmapPtr pPix = NULL; - xRectangle *pRects = NULL; - Bool failed = FALSE; - int depth = 1; - int bitsPerPixel = 1; - int i; - BoxPtr pBox; +CALLBACK(SecurityCheckMapAccess) +{ + XaceMapAccessRec *rec = (XaceMapAccessRec*)calldata; + WindowPtr pWin = rec->pWin; - /* convert region to list-of-rectangles for PolyFillRect */ + if (STATEPTR(rec->client) && + (TRUSTLEVEL(rec->client) != XSecurityClientTrusted) && + (pWin->drawable.class == InputOnly) && + (TRUSTLEVEL(wClient(pWin->parent)) == XSecurityClientTrusted)) - pRects = (xRectangle *)ALLOCATE_LOCAL(nRects * sizeof(xRectangle *)); - if (!pRects) - { - failed = TRUE; - goto failSafe; - } - for (pBox = REGION_RECTS(&censorRegion), i = 0; - i < nRects; - i++, pBox++) - { - pRects[i].x = pBox->x1; - pRects[i].y = pBox->y1 - imageBox.y1; - pRects[i].width = pBox->x2 - pBox->x1; - pRects[i].height = pBox->y2 - pBox->y1; - } + rec->rval = FALSE; +} - /* use pBuf as a fake pixmap */ +CALLBACK(SecurityCheckBackgrndAccess) +{ + XaceMapAccessRec *rec = (XaceMapAccessRec*)calldata; - if (format == ZPixmap) - { - depth = pDraw->depth; - bitsPerPixel = pDraw->bitsPerPixel; - } + if (TRUSTLEVEL(rec->client) != XSecurityClientTrusted) + rec->rval = FALSE; +} - pPix = GetScratchPixmapHeader(pDraw->pScreen, w, h, - depth, bitsPerPixel, - widthBytesLine, (pointer)pBuf); - if (!pPix) - { - failed = TRUE; - goto failSafe; - } +CALLBACK(SecurityCheckExtAccess) +{ + XaceExtAccessRec *rec = (XaceExtAccessRec*)calldata; - pScratchGC = GetScratchGC(depth, pPix->drawable.pScreen); - if (!pScratchGC) - { - failed = TRUE; - goto failSafe; - } + if ((TRUSTLEVEL(rec->client) != XSecurityClientTrusted) && + !STATEVAL(rec->ext)) - ValidateGC(&pPix->drawable, pScratchGC); - (* pScratchGC->ops->PolyFillRect)(&pPix->drawable, - pScratchGC, nRects, pRects); + rec->rval = FALSE; +} - failSafe: - if (failed) - { - /* Censoring was not completed above. To be safe, wipe out - * all the image data so that nothing trusted gets out. - */ - bzero(pBuf, (int)(widthBytesLine * h)); - } - if (pRects) DEALLOCATE_LOCAL(pRects); - if (pScratchGC) FreeScratchGC(pScratchGC); - if (pPix) FreeScratchPixmapHeader(pPix); +CALLBACK(SecurityCheckHostlistAccess) +{ + XaceHostlistAccessRec *rec = (XaceHostlistAccessRec*)calldata; + + if (TRUSTLEVEL(rec->client) != XSecurityClientTrusted) + { + rec->rval = FALSE; + if (rec->access_mode == SecurityWriteAccess) + SecurityAudit("client %d attempted to change host access\n", + rec->client->index); + else + SecurityAudit("client %d attempted to list hosts\n", + rec->client->index); } - REGION_UNINIT(pScreen, &imageRegion); - REGION_UNINIT(pScreen, &censorRegion); -} /* SecurityCensorImage */ +} + +CALLBACK(SecurityDeclareExtSecure) +{ + XaceDeclareExtSecureRec *rec = (XaceDeclareExtSecureRec*)calldata; + + /* security state for extensions is simply a boolean trust value */ + STATEVAL(rec->ext) = rec->secure; +} /**********************************************************************/ @@ -1734,21 +1691,21 @@ SecurityMatchString( #endif -char -SecurityCheckPropertyAccess(client, pWin, propertyName, access_mode) - ClientPtr client; - WindowPtr pWin; - ATOM propertyName; - Mask access_mode; -{ +CALLBACK(SecurityCheckPropertyAccess) +{ + XacePropertyAccessRec *rec = (XacePropertyAccessRec*)calldata; + ClientPtr client = rec->client; + WindowPtr pWin = rec->pWin; + ATOM propertyName = rec->propertyName; + Mask access_mode = rec->access_mode; PropertyAccessPtr pacl; char action = SecurityDefaultAction; /* if client trusted or window untrusted, allow operation */ - if ( (client->trustLevel == XSecurityClientTrusted) || - (wClient(pWin)->trustLevel != XSecurityClientTrusted) ) - return SecurityAllowOperation; + if ( (TRUSTLEVEL(client) == XSecurityClientTrusted) || + (TRUSTLEVEL(wClient(pWin)) != XSecurityClientTrusted) ) + return; #ifdef PROPDEBUG /* For testing, it's more convenient if the property rules file gets @@ -1861,7 +1818,9 @@ SecurityCheckPropertyAccess(client, pWin, propertyName, access_mode) client->index, reqtype, pWin->drawable.id, NameForAtom(propertyName), propertyName, cid, actionstr); } - return action; + /* return codes increase with strictness */ + if (action > rec->rval) + rec->rval = action; } /* SecurityCheckPropertyAccess */ @@ -1901,6 +1860,46 @@ XSecurityOptions(argc, argv, i) } /* XSecurityOptions */ +/* SecurityExtensionSetup + * + * Arguments: none. + * + * Returns: nothing. + * + * Side Effects: + * Sets up the Security extension if possible. + * This function contains things that need to be done + * before any other extension init functions get called. + */ + +void +SecurityExtensionSetup(INITARGS) +{ + /* Allocate the client private index */ + securityClientPrivateIndex = AllocateClientPrivateIndex(); + if (!AllocateClientPrivate(securityClientPrivateIndex, + sizeof (SecurityClientStateRec))) + FatalError("SecurityExtensionSetup: Can't allocate client private.\n"); + + /* Allocate the extension private index */ + securityExtnsnPrivateIndex = AllocateExtensionPrivateIndex(); + if (!AllocateExtensionPrivate(securityExtnsnPrivateIndex, 0)) + FatalError("SecurityExtensionSetup: Can't allocate extnsn private.\n"); + + /* register callbacks */ +#define XaceRC XaceRegisterCallback + XaceRC(XACE_RESOURCE_ACCESS, SecurityCheckResourceIDAccess, NULL); + XaceRC(XACE_DEVICE_ACCESS, SecurityCheckDeviceAccess, NULL); + XaceRC(XACE_PROPERTY_ACCESS, SecurityCheckPropertyAccess, NULL); + XaceRC(XACE_DRAWABLE_ACCESS, SecurityCheckDrawableAccess, NULL); + XaceRC(XACE_MAP_ACCESS, SecurityCheckMapAccess, NULL); + XaceRC(XACE_BACKGRND_ACCESS, SecurityCheckBackgrndAccess, NULL); + XaceRC(XACE_EXT_DISPATCH, SecurityCheckExtAccess, NULL); + XaceRC(XACE_EXT_ACCESS, SecurityCheckExtAccess, NULL); + XaceRC(XACE_HOSTLIST_ACCESS, SecurityCheckHostlistAccess, NULL); + XaceRC(XACE_DECLARE_EXT_SECURE, SecurityDeclareExtSecure, NULL); +} /* SecurityExtensionSetup */ + /* SecurityExtensionInit * @@ -1916,7 +1915,6 @@ void SecurityExtensionInit(INITARGS) { ExtensionEntry *extEntry; - int i; SecurityAuthorizationResType = CreateNewResourceType(SecurityDeleteAuthorization); @@ -1943,25 +1941,6 @@ SecurityExtensionInit(INITARGS) EventSwapVector[SecurityEventBase + XSecurityAuthorizationRevoked] = (EventSwapPtr)SwapSecurityAuthorizationRevokedEvent; - /* initialize untrusted proc vectors */ - - for (i = 0; i < 128; i++) - { - UntrustedProcVector[i] = ProcVector[i]; - SwappedUntrustedProcVector[i] = SwappedProcVector[i]; - } - - /* make sure insecure extensions are not allowed */ - - for (i = 128; i < 256; i++) - { - if (!UntrustedProcVector[i]) - { - UntrustedProcVector[i] = ProcBadRequest; - SwappedUntrustedProcVector[i] = ProcBadRequest; - } - } - SecurityLoadPropertyAccessList(); } /* SecurityExtensionInit */ diff --git a/Xext/securitysrv.h b/Xext/securitysrv.h index 596eead0d..7c6f432fe 100644 --- a/Xext/securitysrv.h +++ b/Xext/securitysrv.h @@ -86,46 +86,11 @@ typedef struct { Bool valid; /* did anyone recognize it? if so, set to TRUE */ } SecurityValidateGroupInfoRec; -/* Proc vectors for untrusted clients, swapped and unswapped versions. - * These are the same as the normal proc vectors except that extensions - * that haven't declared themselves secure will have ProcBadRequest plugged - * in for their major opcode dispatcher. This prevents untrusted clients - * from guessing extension major opcodes and using the extension even though - * the extension can't be listed or queried. - */ -extern int (*UntrustedProcVector[256])(ClientPtr client); -extern int (*SwappedUntrustedProcVector[256])(ClientPtr client); - -extern Bool SecurityCheckDeviceAccess(ClientPtr client, DeviceIntPtr dev, - Bool fromRequest); - -extern void SecurityAudit(char *format, ...); - extern int XSecurityOptions(int argc, char **argv, int i); /* Give this value or higher to the -audit option to get security messages */ #define SECURITY_AUDIT_LEVEL 4 -extern void SecurityCensorImage( - ClientPtr client, - RegionPtr pVisibleRegion, - long widthBytesLine, - DrawablePtr pDraw, - int x, int y, int w, int h, - unsigned int format, - char * pBuf); - -#define SecurityAllowOperation 0 -#define SecurityIgnoreOperation 1 -#define SecurityErrorOperation 2 - -extern char -SecurityCheckPropertyAccess( - ClientPtr client, - WindowPtr pWin, - ATOM propertyName, - Mask access_mode); - #define SECURITY_POLICY_FILE_VERSION "version-1" extern char **SecurityGetSitePolicyStrings(int *n); diff --git a/Xext/xace.c b/Xext/xace.c new file mode 100644 index 000000000..14a5e7963 --- /dev/null +++ b/Xext/xace.c @@ -0,0 +1,496 @@ +/************************************************************ + +Author: Eamon Walsh + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +this permission notice appear in supporting documentation. This permission +notice shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +********************************************************/ + +#ifdef HAVE_DIX_CONFIG_H +#include +#endif + +#include +#include "windowstr.h" +#include "scrnintstr.h" +#include "gcstruct.h" +#include "xacestr.h" +#include "modinit.h" + +CallbackListPtr XaceHooks[XACE_NUM_HOOKS] = {0}; + +/* Proc vectors for untrusted clients, swapped and unswapped versions. + * These are the same as the normal proc vectors except that extensions + * that haven't declared themselves secure will have ProcBadRequest plugged + * in for their major opcode dispatcher. This prevents untrusted clients + * from guessing extension major opcodes and using the extension even though + * the extension can't be listed or queried. + */ +int (*UntrustedProcVector[256])( + ClientPtr /*client*/ +); +int (*SwappedUntrustedProcVector[256])( + ClientPtr /*client*/ +); + +/* Entry point for hook functions. Called by Xserver. + */ +int XaceHook(int hook, ...) +{ + pointer calldata; /* data passed to callback */ + int *prv = NULL; /* points to return value from callback */ + va_list ap; /* argument list */ + va_start(ap, hook); + + /* Marshal arguments for passing to callback. + * Each callback has its own case, which sets up a structure to hold + * the arguments and integer return parameter, or in some cases just + * sets calldata directly to a single argument (with no return result) + */ + switch (hook) + { + case XACE_CORE_DISPATCH: { + XaceCoreDispatchRec rec = { + va_arg(ap, ClientPtr), + TRUE /* default allow */ + }; + calldata = &rec; + prv = &rec.rval; + break; + } + case XACE_RESOURCE_ACCESS: { + XaceResourceAccessRec rec = { + va_arg(ap, ClientPtr), + va_arg(ap, XID), + va_arg(ap, RESTYPE), + va_arg(ap, Mask), + va_arg(ap, pointer), + TRUE /* default allow */ + }; + calldata = &rec; + prv = &rec.rval; + break; + } + case XACE_DEVICE_ACCESS: { + XaceDeviceAccessRec rec = { + va_arg(ap, ClientPtr), + va_arg(ap, DeviceIntPtr), + va_arg(ap, Bool), + TRUE /* default allow */ + }; + calldata = &rec; + prv = &rec.rval; + break; + } + case XACE_PROPERTY_ACCESS: { + XacePropertyAccessRec rec = { + va_arg(ap, ClientPtr), + va_arg(ap, WindowPtr), + va_arg(ap, Atom), + va_arg(ap, Mask), + SecurityAllowOperation /* default allow */ + }; + calldata = &rec; + prv = &rec.rval; + break; + } + case XACE_DRAWABLE_ACCESS: { + XaceDrawableAccessRec rec = { + va_arg(ap, ClientPtr), + va_arg(ap, DrawablePtr), + TRUE /* default allow */ + }; + calldata = &rec; + prv = &rec.rval; + break; + } + case XACE_MAP_ACCESS: + case XACE_BACKGRND_ACCESS: { + XaceMapAccessRec rec = { + va_arg(ap, ClientPtr), + va_arg(ap, WindowPtr), + TRUE /* default allow */ + }; + calldata = &rec; + prv = &rec.rval; + break; + } + case XACE_EXT_DISPATCH: + case XACE_EXT_ACCESS: { + XaceExtAccessRec rec = { + va_arg(ap, ClientPtr), + va_arg(ap, ExtensionEntry*), + TRUE /* default allow */ + }; + calldata = &rec; + prv = &rec.rval; + break; + } + case XACE_HOSTLIST_ACCESS: { + XaceHostlistAccessRec rec = { + va_arg(ap, ClientPtr), + va_arg(ap, Mask), + TRUE /* default allow */ + }; + calldata = &rec; + prv = &rec.rval; + break; + } + case XACE_SITE_POLICY: { + XaceSitePolicyRec rec = { + va_arg(ap, char*), + va_arg(ap, int), + FALSE /* default unrecognized */ + }; + calldata = &rec; + prv = &rec.rval; + break; + } + case XACE_DECLARE_EXT_SECURE: { + XaceDeclareExtSecureRec rec = { + va_arg(ap, ExtensionEntry*), + va_arg(ap, Bool) + }; + calldata = &rec; + break; + } + case XACE_AUTH_AVAIL: { + XaceAuthAvailRec rec = { + va_arg(ap, ClientPtr), + va_arg(ap, XID) + }; + calldata = &rec; + break; + } + case XACE_KEY_AVAIL: { + XaceKeyAvailRec rec = { + va_arg(ap, xEventPtr), + va_arg(ap, DeviceIntPtr), + va_arg(ap, int) + }; + calldata = &rec; + break; + } + case XACE_WINDOW_INIT: { + XaceWindowRec rec = { + va_arg(ap, ClientPtr), + va_arg(ap, WindowPtr) + }; + calldata = &rec; + break; + } + case XACE_AUDIT_BEGIN: { + XaceAuditRec rec = { + va_arg(ap, ClientPtr), + 0 + }; + calldata = &rec; + break; + } + case XACE_AUDIT_END: { + XaceAuditRec rec = { + va_arg(ap, ClientPtr), + va_arg(ap, int) + }; + calldata = &rec; + break; + } + default: { + va_end(ap); + return 0; /* unimplemented hook number */ + } + } + va_end(ap); + + /* call callbacks and return result, if any. */ + CallCallbacks(&XaceHooks[hook], calldata); + return prv ? *prv : 0; +} + +static int +ProcXaceDispatch(ClientPtr client) +{ + REQUEST(xReq); + + switch (stuff->data) + { + default: + return BadRequest; + } +} /* ProcXaceDispatch */ + +static int +SProcXaceDispatch(ClientPtr client) +{ + REQUEST(xReq); + + switch (stuff->data) + { + default: + return BadRequest; + } +} /* SProcXaceDispatch */ + + +/* XaceResetProc + * + * Arguments: + * extEntry is the extension information for the XACE extension. + * + * Returns: nothing. + * + * Side Effects: + * Performs any cleanup needed by XACE at server shutdown time. + */ +static void +XaceResetProc(ExtensionEntry *extEntry) +{ + int i; + + for (i=0; ireqType; + + if (!ProcVector[major]) + return (BadRequest); + + if (!XaceHook(XACE_CORE_DISPATCH, client)) + return (BadAccess); + + return client->swapped ? + (* SwappedProcVector[major])(client) : + (* ProcVector[major])(client); +} + +static int +XaceCatchExtProc(ClientPtr client) +{ + REQUEST(xReq); + int major = stuff->reqType; + ExtensionEntry *ext = GetExtensionEntry(major); + + if (!ext || !ProcVector[major]) + return (BadRequest); + + if (!XaceHook(XACE_EXT_DISPATCH, client, ext)) + return (BadRequest); /* pretend extension doesn't exist */ + + return client->swapped ? + (* SwappedProcVector[major])(client) : + (* ProcVector[major])(client); +} + + +/* SecurityClientStateCallback + * + * Arguments: + * pcbl is &ClientStateCallback. + * nullata is NULL. + * calldata is a pointer to a NewClientInfoRec (include/dixstruct.h) + * which contains information about client state changes. + * + * Returns: nothing. + * + * Side Effects: + * + * If a new client is connecting, its authorization ID is copied to + * client->authID. If this is a generated authorization, its reference + * count is bumped, its timer is cancelled if it was running, and its + * trustlevel is copied to TRUSTLEVEL(client). + * + * If a client is disconnecting and the client was using a generated + * authorization, the authorization's reference count is decremented, and + * if it is now zero, the timer for this authorization is started. + */ + +static void +XaceClientStateCallback( + CallbackListPtr *pcbl, + pointer nulldata, + pointer calldata) +{ + NewClientInfoRec *pci = (NewClientInfoRec *)calldata; + ClientPtr client = pci->client; + + switch (client->clientState) + { + case ClientStateRunning: + { + client->requestVector = client->swapped ? + SwappedUntrustedProcVector : UntrustedProcVector; + break; + } + default: break; + } +} /* XaceClientStateCallback */ + +/* XaceExtensionInit + * + * Initialize the XACE Extension + */ +void XaceExtensionInit(INITARGS) +{ + ExtensionEntry *extEntry; + int i; + + if (!AddCallback(&ClientStateCallback, XaceClientStateCallback, NULL)) + return; + + extEntry = AddExtension(XACE_EXTENSION_NAME, + XaceNumberEvents, XaceNumberErrors, + ProcXaceDispatch, SProcXaceDispatch, + XaceResetProc, StandardMinorOpcode); + + /* initialize dispatching intercept functions */ + for (i = 0; i < 128; i++) + { + UntrustedProcVector[i] = XaceCatchDispatchProc; + SwappedUntrustedProcVector[i] = XaceCatchDispatchProc; + } + for (i = 128; i < 256; i++) + { + UntrustedProcVector[i] = XaceCatchExtProc; + SwappedUntrustedProcVector[i] = XaceCatchExtProc; + } +} + +/* XaceCensorImage + * + * Called after pScreen->GetImage to prevent pieces or trusted windows from + * being returned in image data from an untrusted window. + * + * Arguments: + * client is the client doing the GetImage. + * pVisibleRegion is the visible region of the window. + * widthBytesLine is the width in bytes of one horizontal line in pBuf. + * pDraw is the source window. + * x, y, w, h is the rectangle of image data from pDraw in pBuf. + * format is the format of the image data in pBuf: ZPixmap or XYPixmap. + * pBuf is the image data. + * + * Returns: nothing. + * + * Side Effects: + * Any part of the rectangle (x, y, w, h) that is outside the visible + * region of the window will be destroyed (overwritten) in pBuf. + */ +void +XaceCensorImage(client, pVisibleRegion, widthBytesLine, pDraw, x, y, w, h, + format, pBuf) + ClientPtr client; + RegionPtr pVisibleRegion; + long widthBytesLine; + DrawablePtr pDraw; + int x, y, w, h; + unsigned int format; + char * pBuf; +{ + ScreenPtr pScreen = pDraw->pScreen; + RegionRec imageRegion; /* region representing x,y,w,h */ + RegionRec censorRegion; /* region to obliterate */ + BoxRec imageBox; + int nRects; + + imageBox.x1 = x; + imageBox.y1 = y; + imageBox.x2 = x + w; + imageBox.y2 = y + h; + REGION_INIT(pScreen, &imageRegion, &imageBox, 1); + REGION_NULL(pScreen, &censorRegion); + + /* censorRegion = imageRegion - visibleRegion */ + REGION_SUBTRACT(pScreen, &censorRegion, &imageRegion, pVisibleRegion); + nRects = REGION_NUM_RECTS(&censorRegion); + if (nRects > 0) + { /* we have something to censor */ + GCPtr pScratchGC = NULL; + PixmapPtr pPix = NULL; + xRectangle *pRects = NULL; + Bool failed = FALSE; + int depth = 1; + int bitsPerPixel = 1; + int i; + BoxPtr pBox; + + /* convert region to list-of-rectangles for PolyFillRect */ + + pRects = (xRectangle *)ALLOCATE_LOCAL(nRects * sizeof(xRectangle *)); + if (!pRects) + { + failed = TRUE; + goto failSafe; + } + for (pBox = REGION_RECTS(&censorRegion), i = 0; + i < nRects; + i++, pBox++) + { + pRects[i].x = pBox->x1; + pRects[i].y = pBox->y1 - imageBox.y1; + pRects[i].width = pBox->x2 - pBox->x1; + pRects[i].height = pBox->y2 - pBox->y1; + } + + /* use pBuf as a fake pixmap */ + + if (format == ZPixmap) + { + depth = pDraw->depth; + bitsPerPixel = pDraw->bitsPerPixel; + } + + pPix = GetScratchPixmapHeader(pDraw->pScreen, w, h, + depth, bitsPerPixel, + widthBytesLine, (pointer)pBuf); + if (!pPix) + { + failed = TRUE; + goto failSafe; + } + + pScratchGC = GetScratchGC(depth, pPix->drawable.pScreen); + if (!pScratchGC) + { + failed = TRUE; + goto failSafe; + } + + ValidateGC(&pPix->drawable, pScratchGC); + (* pScratchGC->ops->PolyFillRect)(&pPix->drawable, + pScratchGC, nRects, pRects); + + failSafe: + if (failed) + { + /* Censoring was not completed above. To be safe, wipe out + * all the image data so that nothing trusted gets out. + */ + bzero(pBuf, (int)(widthBytesLine * h)); + } + if (pRects) DEALLOCATE_LOCAL(pRects); + if (pScratchGC) FreeScratchGC(pScratchGC); + if (pPix) FreeScratchPixmapHeader(pPix); + } + REGION_UNINIT(pScreen, &imageRegion); + REGION_UNINIT(pScreen, &censorRegion); +} /* XaceCensorImage */ diff --git a/Xext/xace.h b/Xext/xace.h new file mode 100644 index 000000000..6cb4b4f5d --- /dev/null +++ b/Xext/xace.h @@ -0,0 +1,103 @@ +/************************************************************ + +Author: Eamon Walsh + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +this permission notice appear in supporting documentation. This permission +notice shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +********************************************************/ + +#ifndef _XACE_H +#define _XACE_H + +#define XACE_EXTENSION_NAME "XAccessControlExtension" +#define XACE_MAJOR_VERSION 1 +#define XACE_MINOR_VERSION 0 + +#include "pixmap.h" /* for DrawablePtr */ +#include "regionstr.h" /* for RegionPtr */ + +#define XaceNumberEvents 0 +#define XaceNumberErrors 0 + +/* security hooks */ +/* Constants used to identify the available security hooks + */ +#define XACE_CORE_DISPATCH 0 +#define XACE_EXT_DISPATCH 1 +#define XACE_RESOURCE_ACCESS 2 +#define XACE_DEVICE_ACCESS 3 +#define XACE_PROPERTY_ACCESS 4 +#define XACE_DRAWABLE_ACCESS 5 +#define XACE_MAP_ACCESS 6 +#define XACE_BACKGRND_ACCESS 7 +#define XACE_EXT_ACCESS 8 +#define XACE_HOSTLIST_ACCESS 9 +#define XACE_SITE_POLICY 10 +#define XACE_DECLARE_EXT_SECURE 11 +#define XACE_AUTH_AVAIL 12 +#define XACE_KEY_AVAIL 13 +#define XACE_WINDOW_INIT 14 +#define XACE_AUDIT_BEGIN 15 +#define XACE_AUDIT_END 16 +#define XACE_NUM_HOOKS 17 + +extern CallbackListPtr XaceHooks[XACE_NUM_HOOKS]; + +/* Entry point for hook functions. Called by Xserver. + */ +extern int XaceHook( + int /*hook*/, + ... /*appropriate args for hook*/ + ); + +/* Register a callback for a given hook. + */ +#define XaceRegisterCallback(hook,callback,data) \ + AddCallback(XaceHooks+(hook), callback, data) + +/* Unregister an existing callback for a given hook. + */ +#define XaceDeleteCallback(hook,callback,data) \ + DeleteCallback(XaceHooks+(hook), callback, data) + + +/* From the original Security extension... + */ + +/* Hook return codes */ +#define SecurityAllowOperation 0 +#define SecurityIgnoreOperation 1 +#define SecurityErrorOperation 2 + +/* Proc vectors for untrusted clients, swapped and unswapped versions. + * These are the same as the normal proc vectors except that extensions + * that haven't declared themselves secure will have ProcBadRequest plugged + * in for their major opcode dispatcher. This prevents untrusted clients + * from guessing extension major opcodes and using the extension even though + * the extension can't be listed or queried. + */ +extern int (*UntrustedProcVector[256])(ClientPtr client); +extern int (*SwappedUntrustedProcVector[256])(ClientPtr client); + +extern void XaceCensorImage( + ClientPtr client, + RegionPtr pVisibleRegion, + long widthBytesLine, + DrawablePtr pDraw, + int x, int y, int w, int h, + unsigned int format, + char * pBuf + ); + +#endif /* _XACE_H */ diff --git a/Xext/xacestr.h b/Xext/xacestr.h new file mode 100644 index 000000000..7114d066b --- /dev/null +++ b/Xext/xacestr.h @@ -0,0 +1,135 @@ +/************************************************************ + +Author: Eamon Walsh + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +this permission notice appear in supporting documentation. This permission +notice shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +********************************************************/ + +#ifndef _XACESTR_H +#define _XACESTR_H + +#include +#include "dixstruct.h" +#include "resource.h" +#include "extnsionst.h" +#include "gcstruct.h" +#include "windowstr.h" +#include "inputstr.h" +#include "xace.h" + +/* XACE_CORE_DISPATCH */ +typedef struct { + ClientPtr client; + int rval; +} XaceCoreDispatchRec; + +/* XACE_RESOURCE_ACCESS */ +/* XACE_RESOURCE_CREATE */ +typedef struct { + ClientPtr client; + XID id; + RESTYPE rtype; + Mask access_mode; + pointer res; + int rval; +} XaceResourceAccessRec; + +/* XACE_DEVICE_ACCESS */ +typedef struct { + ClientPtr client; + DeviceIntPtr dev; + Bool fromRequest; + int rval; +} XaceDeviceAccessRec; + +/* XACE_PROPERTY_ACCESS */ +typedef struct { + ClientPtr client; + WindowPtr pWin; + Atom propertyName; + Mask access_mode; + int rval; +} XacePropertyAccessRec; + +/* XACE_DRAWABLE_ACCESS */ +typedef struct { + ClientPtr client; + DrawablePtr pDraw; + int rval; +} XaceDrawableAccessRec; + +/* XACE_MAP_ACCESS */ +/* XACE_BACKGRND_ACCESS */ +typedef struct { + ClientPtr client; + WindowPtr pWin; + int rval; +} XaceMapAccessRec; + +/* XACE_EXT_DISPATCH_ACCESS */ +/* XACE_EXT_ACCESS */ +typedef struct { + ClientPtr client; + ExtensionEntry *ext; + int rval; +} XaceExtAccessRec; + +/* XACE_HOSTLIST_ACCESS */ +typedef struct { + ClientPtr client; + Mask access_mode; + int rval; +} XaceHostlistAccessRec; + +/* XACE_SITE_POLICY */ +typedef struct { + char *policyString; + int len; + int rval; +} XaceSitePolicyRec; + +/* XACE_DECLARE_EXT_SECURE */ +typedef struct { + ExtensionEntry *ext; + Bool secure; +} XaceDeclareExtSecureRec; + +/* XACE_AUTH_AVAIL */ +typedef struct { + ClientPtr client; + XID authId; +} XaceAuthAvailRec; + +/* XACE_KEY_AVAIL */ +typedef struct { + xEventPtr event; + DeviceIntPtr keybd; + int count; +} XaceKeyAvailRec; + +/* XACE_WINDOW_INIT */ +typedef struct { + ClientPtr client; + WindowPtr pWin; +} XaceWindowRec; + +/* XACE_AUDIT_BEGIN */ +/* XACE_AUDIT_END */ +typedef struct { + ClientPtr client; + int requestResult; +} XaceAuditRec; + +#endif /* _XACESTR_H */ diff --git a/Xext/xcalibrate.c b/Xext/xcalibrate.c new file mode 100644 index 000000000..e273c5313 --- /dev/null +++ b/Xext/xcalibrate.c @@ -0,0 +1,262 @@ +/* + * $Id: xcalibrate.c,v 3.1 2004/06/02 20:49:50 pb Exp $ + * + * Copyright © 2003 Philip Blundell + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Philip Blundell not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Philip Blundell makes no + * representations about the suitability of this software for any purpose. It + * is provided "as is" without express or implied warranty. + * + * PHILIP BLUNDELL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL PHILIP BLUNDELL BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifdef HAVE_KDRIVE_CONFIG_H +#include +#endif + +#define NEED_EVENTS +#define NEED_REPLIES + +#include +#include +#include "misc.h" +#include "os.h" +#include "dixstruct.h" +#include "extnsionst.h" +#include "swaprep.h" + +#include +#include + +extern void (*tslib_raw_event_hook)(int x, int y, int pressure, void *closure); +extern void *tslib_raw_event_closure; + +static CARD8 XCalibrateReqCode; +int XCalibrateEventBase; +int XCalibrateReqBase; +int XCalibrateErrorBase; + +static ClientPtr xcalibrate_client; + +static void +xcalibrate_event_hook (int x, int y, int pressure, void *closure) +{ + ClientPtr pClient = (ClientPtr) closure; + xXCalibrateRawTouchscreenEvent ev; + + ev.type = XCalibrateEventBase + X_XCalibrateRawTouchscreen; + ev.sequenceNumber = pClient->sequence; + ev.x = x; + ev.y = y; + ev.pressure = pressure; + + if (!pClient->clientGone) + WriteEventsToClient (pClient, 1, (xEvent *) &ev); +} + +static int +ProcXCalibrateQueryVersion (ClientPtr client) +{ + REQUEST(xXCalibrateQueryVersionReq); + xXCalibrateQueryVersionReply rep; + CARD16 client_major, client_minor; /* not used */ + + REQUEST_SIZE_MATCH (xXCalibrateQueryVersionReq); + + client_major = stuff->majorVersion; + client_minor = stuff->minorVersion; + + fprintf(stderr, "%s(): called\n", __func__); + + rep.type = X_Reply; + rep.length = 0; + rep.sequenceNumber = client->sequence; + rep.majorVersion = XCALIBRATE_MAJOR_VERSION; + rep.minorVersion = XCALIBRATE_MINOR_VERSION; + if (client->swapped) { + int n; + swaps(&rep.sequenceNumber, n); + swapl(&rep.length, n); + swaps(&rep.majorVersion, n); + swaps(&rep.minorVersion, n); + } + WriteToClient(client, sizeof (xXCalibrateQueryVersionReply), (char *)&rep); + return (client->noClientException); +} + +static int +SProcXCalibrateQueryVersion (ClientPtr client) +{ + REQUEST(xXCalibrateQueryVersionReq); + int n; + + REQUEST_SIZE_MATCH (xXCalibrateQueryVersionReq); + swaps(&stuff->majorVersion,n); + swaps(&stuff->minorVersion,n); + return ProcXCalibrateQueryVersion(client); +} + +static int +ProcXCalibrateSetRawMode (ClientPtr client) +{ + REQUEST(xXCalibrateRawModeReq); + xXCalibrateRawModeReply rep; + + REQUEST_SIZE_MATCH (xXCalibrateRawModeReq); + + memset (&rep, 0, sizeof (rep)); + rep.type = X_Reply; + rep.sequenceNumber = client->sequence; + + if (stuff->on) + { + if (xcalibrate_client == NULL) + { + /* Start calibrating. */ + xcalibrate_client = client; + tslib_raw_event_hook = xcalibrate_event_hook; + tslib_raw_event_closure = client; + rep.status = GrabSuccess; + } + else + { + rep.status = AlreadyGrabbed; + } + } + else + { + if (xcalibrate_client == client) + { + /* Stop calibrating. */ + xcalibrate_client = NULL; + tslib_raw_event_hook = NULL; + tslib_raw_event_closure = NULL; + rep.status = GrabSuccess; + + /* Cycle input off and on to reload configuration. */ + KdDisableInput (); + KdEnableInput (); + } + else + { + rep.status = AlreadyGrabbed; + } + } + + if (client->swapped) + { + int n; + + swaps (&rep.sequenceNumber, n); + swaps (&rep.status, n); + } + WriteToClient(client, sizeof (rep), (char *) &rep); + return (client->noClientException); +} + + +static int +SProcXCalibrateSetRawMode (ClientPtr client) +{ + REQUEST(xXCalibrateRawModeReq); + int n; + + REQUEST_SIZE_MATCH (xXCalibrateRawModeReq); + + swaps(&stuff->on, n); + + return ProcXCalibrateSetRawMode(client); +} + +static void +XCalibrateResetProc (ExtensionEntry *extEntry) +{ +} + +static int +ProcXCalibrateDispatch (ClientPtr client) +{ + REQUEST(xReq); + switch (stuff->data) { + case X_XCalibrateQueryVersion: + return ProcXCalibrateQueryVersion(client); + case X_XCalibrateRawMode: + return ProcXCalibrateSetRawMode(client); + default: break; + } + + return BadRequest; +} + +static int +SProcXCalibrateDispatch (ClientPtr client) +{ + REQUEST(xReq); + int n; + + swaps(&stuff->length,n); + + switch (stuff->data) { + case X_XCalibrateQueryVersion: + return SProcXCalibrateQueryVersion(client); + case X_XCalibrateRawMode: + return SProcXCalibrateSetRawMode(client); + + default: break; + } + + return BadRequest; +} + +static void +XCalibrateClientCallback (CallbackListPtr *list, + pointer closure, + pointer data) +{ + NewClientInfoRec *clientinfo = (NewClientInfoRec *) data; + ClientPtr pClient = clientinfo->client; + + if (clientinfo->setup == NULL + && xcalibrate_client != NULL + && xcalibrate_client == pClient) + { + /* Stop calibrating. */ + xcalibrate_client = NULL; + tslib_raw_event_hook = NULL; + tslib_raw_event_closure = NULL; + } +} + +void +XCalibrateExtensionInit(void) +{ + ExtensionEntry *extEntry; + + if (!AddCallback (&ClientStateCallback, XCalibrateClientCallback, 0)) + return; + + extEntry = AddExtension(XCALIBRATE_NAME, XCalibrateNumberEvents, XCalibrateNumberErrors, + ProcXCalibrateDispatch, SProcXCalibrateDispatch, + XCalibrateResetProc, StandardMinorOpcode); + + if (!extEntry) + return; + + XCalibrateReqCode = (unsigned char)extEntry->base; + XCalibrateEventBase = extEntry->eventBase; + XCalibrateErrorBase = extEntry->errorBase; + + xcalibrate_client = 0; +} diff --git a/cfb/cfbteblt8.c b/cfb/cfbteblt8.c index 1db299623..9d4ce5708 100644 --- a/cfb/cfbteblt8.c +++ b/cfb/cfbteblt8.c @@ -301,7 +301,7 @@ typedef unsigned int *glyphPointer; #define StorePixels(o,p) dst[o] = p #define Loop dst += widthDst; #else -#define StorePixels(o,p) *dst++ = (p) +#define StorePixels(o,p) do { *dst = (p); dst++; } while (0) #define Loop dst += widthLeft; #endif diff --git a/configure.ac b/configure.ac index 1b72eb95c..b2ec29d66 100644 --- a/configure.ac +++ b/configure.ac @@ -82,7 +82,8 @@ AC_TYPE_PID_T dnl Checks for library functions. AC_FUNC_VPRINTF AC_CHECK_FUNCS([geteuid getuid link memmove memset mkstemp strchr strrchr \ - strtol getopt getopt_long vsnprintf walkcontext backtrace]) + strtol getopt getopt_long vsnprintf walkcontext backtrace \ + getisax]) AC_FUNC_ALLOCA dnl Old HAS_* names used in os/*.c. AC_CHECK_FUNC([getdtablesize], @@ -413,9 +414,12 @@ AC_ARG_ENABLE(dri, AS_HELP_STRING([--enable-dri], [Build DRI extensio AC_ARG_ENABLE(xinerama, AS_HELP_STRING([--disable-xinerama], [Build Xinerama extension (default: enabled)]), [XINERAMA=$enableval], [XINERAMA=yes]) AC_ARG_ENABLE(xf86vidmode, AS_HELP_STRING([--disable-xf86vidmode], [Build XF86VidMode extension (default: enabled)]), [XF86VIDMODE=$enableval], [XF86VIDMODE=yes]) AC_ARG_ENABLE(xf86misc, AS_HELP_STRING([--disable-xf86misc], [Build XF86Misc extension (default: enabled)]), [XF86MISC=$enableval], [XF86MISC=yes]) -AC_ARG_ENABLE(xcsecurity, AS_HELP_STRING([--disable-xcsecurity], [Build Security extension (default: enabled)]), [XCSECURITY=$enableval], [XCSECURITY=yes]) +AC_ARG_ENABLE(xace, AS_HELP_STRING([--disable-xace], [Build X-ACE extension (default: enabled)]), [XACE=$enableval], [XACE=yes]) +AC_ARG_ENABLE(xcsecurity, AS_HELP_STRING([--disable-xcsecurity], [Build Security extension (default: enabled)]), [XCSECURITY=$enableval], [XCSECURITY=$XACE]) +AC_ARG_ENABLE(appgroup, AS_HELP_STRING([--disable-appgroup], [Build XC-APPGROUP extension (default: enabled)]), [APPGROUP=$enableval], [APPGROUP=$XCSECURITY]) +AC_ARG_ENABLE(xcalibrate, AS_HELP_STRING([--enable-xcalibrate], [Build XCalibrate extension (default: disabled)]), [XCALIBRATE=$enableval], [XCALIBRATE=no]) +AC_ARG_ENABLE(tslib, AS_HELP_STRING([--enable-tslib], [Build kdrive tslib touchscreen support (default: disabled)]), [TSLIB=$enableval], [TSLIB=no]) AC_ARG_ENABLE(xevie, AS_HELP_STRING([--disable-xevie], [Build XEvIE extension (default: enabled)]), [XEVIE=$enableval], [XEVIE=yes]) -AC_ARG_ENABLE(appgroup, AS_HELP_STRING([--disable-appgroup], [Build XC-APPGROUP extension (default: enabled)]), [APPGROUP=$enableval], [APPGROUP=yes]) AC_ARG_ENABLE(cup, AS_HELP_STRING([--disable-cup], [Build TOG-CUP extension (default: enabled)]), [CUP=$enableval], [CUP=yes]) AC_ARG_ENABLE(evi, AS_HELP_STRING([--disable-evi], [Build Extended-Visual-Information extension (default: enabled)]), [EVI=$enableval], [EVI=yes]) AC_ARG_ENABLE(multibuffer, AS_HELP_STRING([--enable-multibuffer], [Build Multibuffer extension (default: disabled)]), [MULTIBUFFER=$enableval], [MULTIBUFFER=no]) @@ -424,6 +428,7 @@ AC_ARG_ENABLE(dbe, AS_HELP_STRING([--disable-dbe], [Build DBE extensi AC_ARG_ENABLE(xf86bigfont, AS_HELP_STRING([--disable-xf86bigfont], [Build XF86 Big Font extension (default: enabled)]), [XF86BIGFONT=$enableval], [XF86BIGFONT=yes]) AC_ARG_ENABLE(dpms, AS_HELP_STRING([--disable-dpms], [Build DPMS extension (default: enabled)]), [DPMSExtension=$enableval], [DPMSExtension=yes]) AC_ARG_ENABLE(xinput, AS_HELP_STRING([--disable-xinput], [Build XInput Extension (default: enabled)]), [XINPUT=$enableval], [XINPUT=yes]) +AC_ARG_ENABLE(xfree86-utils, AS_HELP_STRING([--enable-xfree86-utils], [Build xfree86 DDX utilities (default: enabled)]), [XF86UTILS=$enableval], [XF86UTILS=yes]) dnl DDXes. AC_ARG_ENABLE(xorg, AS_HELP_STRING([--enable-xorg], [Build Xorg server (default: auto)]), [XORG=$enableval], [XORG=auto]) @@ -578,7 +583,12 @@ if test "x$GLX" = xyes && ! test "x$MESA_SOURCE" = x; then AC_DEFINE(GLXEXT, 1, [Build GLX extension]) GLX_LIBS='$(top_builddir)/GL/glx/libglx.la $(top_builddir)/GL/mesa/libGLcore.la' test -d GL || mkdir GL - $srcdir/GL/symlink-mesa.sh $MESA_SOURCE GL/ + case $host_os in + solaris*) + SYMLINK_MESA="/usr/bin/bash $srcdir/GL/symlink-mesa.sh" ;; + *) SYMLINK_MESA=$srcdir/GL/symlink-mesa.sh ;; + esac + $SYMLINK_MESA $MESA_SOURCE GL/ if test $? -ne 0; then AC_MSG_ERROR([Failed to link Mesa source tree. Please specify a proper path to Mesa sources, or disable GLX.]) fi @@ -619,8 +629,16 @@ if test "x$XINERAMA" = xyes; then REQUIRED_MODULES="$REQUIRED_MODULES xineramaproto" fi +AM_CONDITIONAL(XACE, [test "x$XACE" = xyes]) +if test "x$XACE" = xyes; then + AC_DEFINE(XACE, 1, [Build X-ACE extension]) +fi + AM_CONDITIONAL(XCSECURITY, [test "x$XCSECURITY" = xyes]) if test "x$XCSECURITY" = xyes; then + if test "x$XACE" != xyes; then + AC_MSG_ERROR([cannot build Security extension without X-ACE]) + fi AC_DEFINE(XCSECURITY, 1, [Build Security extension]) fi @@ -630,12 +648,11 @@ if test "x$XEVIE" = xyes; then REQUIRED_MODULES="$REQUIRED_MODULES evieproto" fi -if test "x$APPGROUP" = xyes && test "x$XCSECURITY" != xyes; then - AC_MSG_NOTICE([Disabling APPGROUP extension]) - APPGROUP=no -fi AM_CONDITIONAL(APPGROUP, [test "x$APPGROUP" = xyes]) if test "x$APPGROUP" = xyes; then + if test "x$XACE" != xyes || test "x$XCSECURITY" != xyes; then + AC_MSG_ERROR([cannot build APPGROUP extension without X-ACE and XC-SECURITY]) + fi AC_DEFINE(XAPPGROUP, 1, [Build APPGROUP extension]) fi @@ -696,6 +713,14 @@ if test "x$XPRINT" = xyes; then REQUIRED_MODULES="$REQUIRED_MODULES printproto" fi +if test "x$XCALIBRATE" = xyes && test "$KDRIVE" = yes; then + AC_DEFINE(XCALIBRATE, 1, [Build XCalibrate extension]) + REQUIRED_MODULES="$REQUIRED_MODULES xcalibrateproto" +else + XCALIBRATE=no +fi +AM_CONDITIONAL(XCALIBRATE, [test "x$XCALIBRATE" = xyes]) + AC_DEFINE(RENDER, 1, [Support RENDER extension]) RENDER_LIB='$(top_builddir)/render/librender.la' RENDER_INC='-I$(top_srcdir)/render' @@ -725,6 +750,8 @@ if test "x$XINPUT" = xyes; then XI_INC='-I$(top_srcdir)/Xi' fi +AM_CONDITIONAL(XF86UTILS, test "x$XF86UTILS" = xyes) + AC_DEFINE(SHAPE, 1, [Support SHAPE extension]) AC_DEFINE(XKB, 1, [Build XKB]) @@ -794,6 +821,7 @@ VENDOR_MAN_VERSION="Version ${VENDOR_VERSION_STRING}" AC_DEFINE_DIR(COMPILEDDEFAULTFONTPATH, FONTPATH, [Default font path]) AC_DEFINE_DIR(RGB_DB, RGBPATH, [Default RGB path]) +AC_DEFINE_DIR(BASE_FONT_PATH, FONTDIR, [Default base font path]) AC_DEFINE_DIR(DRI_DRIVER_PATH, DRI_DRIVER_PATH, [Default DRI driver path]) AC_DEFINE_UNQUOTED(XVENDORNAME, ["$VENDOR_STRING"], [Vendor name]) AC_DEFINE_UNQUOTED(XVENDORNAMESHORT, ["$VENDOR_STRING_SHORT"], [Short vendor name]) @@ -1419,7 +1447,6 @@ AM_CONDITIONAL(XWIN_XV, [test "x$XWIN" = xyes && test "x$XV" = xyes]) dnl kdrive DDX -dnl utterly incomplete yet XEYPHR_LIBS= XEPHYR_INCS= @@ -1443,6 +1470,13 @@ if test "$KDRIVE" = yes; then fi # tslib... + if test "x$TSLIB" = xyes; then + PKG_CHECK_MODULES([TSLIB], [tslib-0.0], [HAVE_TSLIB="yes"], [HAVE_TSLIB="no"]) + if test "x$HAVE_TSLIB" = xno; then + AC_MSG_ERROR([tslib must be installed to build the tslib driver. See http://tslib.berlios.de/]) + fi + AC_DEFINE(TSLIB, 1, [Have tslib support]) + fi # damage shadow extension glx (NOTYET) fb mi KDRIVE_INC='-I$(top_srcdir)/hw/kdrive/src' @@ -1450,7 +1484,7 @@ if test "$KDRIVE" = yes; then KDRIVE_OS_INC='-I$(top_srcdir)/hw/kdrive/linux' KDRIVE_INCS="$KDRIVE_PURE_INCS $KDRIVE_OS_INC" - KDRIVE_CFLAGS="$XSERVER_CFLAGS -DHAVE_KDRIVE_CONFIG_H" + KDRIVE_CFLAGS="$XSERVER_CFLAGS -DHAVE_KDRIVE_CONFIG_H $TSLIB_CFLAGS" # dix os fb mi extension glx (NOTYET) damage shadow xpstubs #KDRIVE_PURE_LIBS="$DIX_LIB $OS_LIB $FB_LIB $XEXT_LIB $MIEXT_DAMAGE_LIB \ @@ -1459,25 +1493,26 @@ if test "$KDRIVE" = yes; then KDRIVE_LIB='$(top_builddir)/hw/kdrive/src/libkdrive.a' KDRIVE_OS_LIB='$(top_builddir)/hw/kdrive/linux/liblinux.a' KDRIVE_STUB_LIB='$(top_builddir)/hw/kdrive/src/libkdrivestubs.a' - KDRIVE_LIBS="$DIX_LIB $KDRIVE_LIB $KDRIVE_OS_LIB $KDRIVE_PURE_LIBS $KDRIVE_STUB_LIB" + KDRIVE_LIBS="$DIX_LIB $KDRIVE_LIB $KDRIVE_OS_LIB $KDRIVE_PURE_LIBS $KDRIVE_STUB_LIB $TSLIB_LIBS" # check if we can build Xephyr PKG_CHECK_MODULES(XEPHYR, x11 xext xfont xau xdmcp, [xephyr="yes"], [xephyr="no"]) # check for SDL SDK AC_CHECK_HEADERS([SDL/SDL.h]) + if test "x$XSDL" = xauto; then + XSDL="$ac_cv_header_SDL_SDL_h" + fi fi AC_SUBST(KDRIVE_INCS) AC_SUBST(KDRIVE_PURE_INCS) AC_SUBST(KDRIVE_CFLAGS) AC_SUBST(KDRIVE_PURE_LIBS) AC_SUBST(KDRIVE_LIBS) -AM_CONDITIONAL(TSLIB, false) +AM_CONDITIONAL(TSLIB, [test "x$HAVE_TSLIB" = xyes]) AM_CONDITIONAL(H3600_TS, false) AM_CONDITIONAL(KDRIVEVESA, [test x"$ac_cv_header_sys_vm86_h" = xyes]) AM_CONDITIONAL(KDRIVEFBDEV, [test x"$ac_cv_header_linux_fb_h" = xyes]) -#AM_CONDITIONAL(KDRIVEVESA, false) -#AM_CONDITIONAL(KDRIVEFBDEV, false) # Xephyr needs nanosleep() which is in librt on Solaris AC_CHECK_FUNC([nanosleep], [], @@ -1488,13 +1523,12 @@ XEPHYR_LIBS="$XEPHYR_LIBS $XSERVER_LIBS" AC_SUBST([XEPHYR_LIBS]) AC_SUBST([XEPHYR_INCS]) -AM_CONDITIONAL(XSDLSERVER, [test x"$ac_cv_header_SDL_SDL_h" = xyes]) -if test x"$ac_cv_header_SDL_SDL_h" = xyes -o x"$XSDL" = xyes; then - # PKG_CHECK_MODULES(XSDL_EXTRA, Xfont xau $XDMCP_MODULES) +if test x"$XSDL" = xyes; then AC_DEFINE(XSDLSERVER,,[Build Xsdl server]) XSDL_LIBS="`sdl-config --libs` $XSERVER_LIBS" XSDL_INCS="`sdl-config --cflags` $XSERVER_CFLAGS" fi +AM_CONDITIONAL(XSDLSERVER, [test x"$XSDL" = xyes]) AC_SUBST([XSDL_LIBS]) AC_SUBST([XSDL_INCS]) @@ -1550,8 +1584,8 @@ AC_SUBST(XORGCONFIG_DEP_LIBS) dnl xorgcfg GUI configuration utility AC_ARG_ENABLE(xorgcfg, AS_HELP_STRING([--enable-xorgcfg], - [Build xorgcfg GUI configuration utility (default: yes)]), - [XORGCFG=$enableval],[XORGCFG=yes]) + [Build xorgcfg GUI configuration utility (default: no)]), + [XORGCFG=$enableval],[XORGCFG=no]) if test x$XORGCFG = xyes ; then PKG_CHECK_MODULES([XORGCFG_DEP], [xkbui >= 1.0.2 xkbfile xxf86misc xxf86vm xaw7 xmu xt xpm xext x11]) diff --git a/dix/devices.c b/dix/devices.c index bcf8f4fa6..607510203 100644 --- a/dix/devices.c +++ b/dix/devices.c @@ -69,8 +69,8 @@ SOFTWARE. #ifdef XKB #include #endif -#ifdef XCSECURITY -#include "securitysrv.h" +#ifdef XACE +#include "xace.h" #endif #include "dispatch.h" @@ -946,8 +946,8 @@ ProcSetModifierMapping(ClientPtr client) } } -#ifdef XCSECURITY - if (!SecurityCheckDeviceAccess(client, keybd, TRUE)) +#ifdef XACE + if (!XaceHook(XACE_DEVICE_ACCESS, client, keybd, TRUE)) return BadAccess; #endif @@ -1063,9 +1063,8 @@ ProcChangeKeyboardMapping(ClientPtr client) client->errorValue = stuff->keySymsPerKeyCode; return BadValue; } -#ifdef XCSECURITY - if (!SecurityCheckDeviceAccess(client, inputInfo.keyboard, - TRUE)) +#ifdef XACE + if (!XaceHook(XACE_DEVICE_ACCESS, client, inputInfo.keyboard, TRUE)) return BadAccess; #endif keysyms.minKeyCode = stuff->firstKeyCode; @@ -1211,8 +1210,8 @@ ProcChangeKeyboardControl (ClientPtr client) vmask = stuff->mask; if (client->req_len != (sizeof(xChangeKeyboardControlReq)>>2)+Ones(vmask)) return BadLength; -#ifdef XCSECURITY - if (!SecurityCheckDeviceAccess(client, keybd, TRUE)) +#ifdef XACE + if (!XaceHook(XACE_DEVICE_ACCESS, client, keybd, TRUE)) return BadAccess; #endif vlist = (XID *)&stuff[1]; /* first word of values */ @@ -1600,8 +1599,8 @@ ProcQueryKeymap(ClientPtr client) rep.type = X_Reply; rep.sequenceNumber = client->sequence; rep.length = 2; -#ifdef XCSECURITY - if (!SecurityCheckDeviceAccess(client, inputInfo.keyboard, TRUE)) +#ifdef XACE + if (!XaceHook(XACE_DEVICE_ACCESS, client, inputInfo.keyboard, TRUE)) { bzero((char *)&rep.map[0], 32); } diff --git a/dix/dispatch.c b/dix/dispatch.c index 08b015991..7c4d539fa 100644 --- a/dix/dispatch.c +++ b/dix/dispatch.c @@ -104,8 +104,8 @@ int ProcInitialConnection(); #include "panoramiX.h" #include "panoramiXsrv.h" #endif -#ifdef XCSECURITY -#include "securitysrv.h" +#ifdef XACE +#include "xace.h" #endif #ifdef XAPPGROUP #include "appgroup.h" @@ -451,7 +451,15 @@ Dispatch(void) if (result > (maxBigRequestSize << 2)) result = BadLength; else +#ifdef XACE + { + XaceHook(XACE_AUDIT_BEGIN, client); result = (* client->requestVector[MAJOROP])(client); + XaceHook(XACE_AUDIT_END, client, result); + } +#else + result = (* client->requestVector[MAJOROP])(client); +#endif /* XACE */ if (result != Success) { @@ -1099,11 +1107,10 @@ ProcConvertSelection(register ClientPtr client) CurrentSelections[i].selection != stuff->selection) i++; if ((i < NumCurrentSelections) && (CurrentSelections[i].window != None) -#ifdef XCSECURITY - && (!client->CheckAccess || - (* client->CheckAccess)(client, CurrentSelections[i].window, - RT_WINDOW, SecurityReadAccess, - CurrentSelections[i].pWin)) +#ifdef XACE + && XaceHook(XACE_RESOURCE_ACCESS, client, + CurrentSelections[i].window, RT_WINDOW, + SecurityReadAccess, CurrentSelections[i].pWin) #endif ) { @@ -2095,7 +2102,7 @@ DoGetImage(register ClientPtr client, int format, Drawable drawable, Mask plane = 0; char *pBuf; xGetImageReply xgi; -#ifdef XCSECURITY +#ifdef XACE RegionPtr pVisibleRegion = NULL; #endif @@ -2201,9 +2208,9 @@ DoGetImage(register ClientPtr client, int format, Drawable drawable, WriteReplyToClient(client, sizeof (xGetImageReply), &xgi); } -#ifdef XCSECURITY - if (client->trustLevel != XSecurityClientTrusted && - pDraw->type == DRAWABLE_WINDOW) +#ifdef XACE + if (pDraw->type == DRAWABLE_WINDOW && + !XaceHook(XACE_DRAWABLE_ACCESS, client, pDraw)) { pVisibleRegion = NotClippedByChildren((WindowPtr)pDraw); if (pVisibleRegion) @@ -2231,9 +2238,9 @@ DoGetImage(register ClientPtr client, int format, Drawable drawable, format, planemask, (pointer) pBuf); -#ifdef XCSECURITY +#ifdef XACE if (pVisibleRegion) - SecurityCensorImage(client, pVisibleRegion, widthBytesLine, + XaceCensorImage(client, pVisibleRegion, widthBytesLine, pDraw, x, y + linesDone, width, nlines, format, pBuf); #endif @@ -2272,9 +2279,9 @@ DoGetImage(register ClientPtr client, int format, Drawable drawable, format, plane, (pointer)pBuf); -#ifdef XCSECURITY +#ifdef XACE if (pVisibleRegion) - SecurityCensorImage(client, pVisibleRegion, + XaceCensorImage(client, pVisibleRegion, widthBytesLine, pDraw, x, y + linesDone, width, nlines, format, pBuf); @@ -2300,7 +2307,7 @@ DoGetImage(register ClientPtr client, int format, Drawable drawable, } } } -#ifdef XCSECURITY +#ifdef XACE if (pVisibleRegion) REGION_DESTROY(pDraw->pScreen, pVisibleRegion); #endif @@ -3274,11 +3281,10 @@ ProcListHosts(register ClientPtr client) /* REQUEST(xListHostsReq); */ REQUEST_SIZE_MATCH(xListHostsReq); -#ifdef XCSECURITY +#ifdef XACE /* untrusted clients can't list hosts */ - if (client->trustLevel != XSecurityClientTrusted) + if (!XaceHook(XACE_HOSTLIST_ACCESS, client, SecurityReadAccess)) { - SecurityAudit("client %d attempted to list hosts\n", client->index); return BadAccess; } #endif @@ -3606,8 +3612,13 @@ CloseDownRetainedResources() } } +extern int clientPrivateLen; +extern unsigned *clientPrivateSizes; +extern unsigned totalClientSize; + void InitClient(ClientPtr client, int i, pointer ospriv) { + bzero(client, totalClientSize); client->index = i; client->sequence = 0; client->clientAsMask = ((Mask)i) << CLIENTOFFSET; @@ -3646,11 +3657,6 @@ void InitClient(ClientPtr client, int i, pointer ospriv) } #endif client->replyBytesRemaining = 0; -#ifdef XCSECURITY - client->trustLevel = XSecurityClientTrusted; - client->CheckAccess = NULL; - client->authId = 0; -#endif #ifdef XAPPGROUP client->appgroup = NULL; #endif @@ -3663,10 +3669,6 @@ void InitClient(ClientPtr client, int i, pointer ospriv) #endif } -extern int clientPrivateLen; -extern unsigned *clientPrivateSizes; -extern unsigned totalClientSize; - int InitClientPrivates(ClientPtr client) { @@ -3699,6 +3701,17 @@ InitClientPrivates(ClientPtr client) else ppriv->ptr = (pointer)NULL; } + + /* Allow registrants to initialize the serverClient devPrivates */ + if (!client->index && ClientStateCallback) + { + NewClientInfoRec clientinfo; + + clientinfo.client = client; + clientinfo.prefix = (xConnSetupPrefix *)NULL; + clientinfo.setup = (xConnSetup *) NULL; + CallCallbacks((&ClientStateCallback), (pointer)&clientinfo); + } return 1; } diff --git a/dix/dixutils.c b/dix/dixutils.c index b35754dbb..a395d4474 100644 --- a/dix/dixutils.c +++ b/dix/dixutils.c @@ -95,8 +95,8 @@ Author: Adobe Systems Incorporated #include "scrnintstr.h" #define XK_LATIN1 #include -#ifdef XCSECURITY -#include "securitysrv.h" +#ifdef XACE +#include "xace.h" #endif /* @@ -196,7 +196,7 @@ CompareISOLatin1Lowered(unsigned char *s1, int s1len, return (int) c1 - (int) c2; } -#ifdef XCSECURITY +#ifdef XACE /* SecurityLookupWindow and SecurityLookupDrawable: * Look up the window/drawable taking into account the client doing @@ -204,32 +204,16 @@ CompareISOLatin1Lowered(unsigned char *s1, int s1len, * if it exists and the client is allowed access, else return NULL. * Most Proc* functions should be calling these instead of * LookupWindow and LookupDrawable, which do no access checks. + * XACE note: need to see if client->lastDrawableID can still be used here. */ _X_EXPORT WindowPtr SecurityLookupWindow(XID rid, ClientPtr client, Mask access_mode) { - WindowPtr pWin; - client->errorValue = rid; if(rid == INVALID) return NULL; - if (client->trustLevel != XSecurityClientTrusted) - return (WindowPtr)SecurityLookupIDByType(client, rid, RT_WINDOW, access_mode); - if (client->lastDrawableID == rid) - { - if (client->lastDrawable->type == DRAWABLE_WINDOW) - return ((WindowPtr) client->lastDrawable); - return (WindowPtr) NULL; - } - pWin = (WindowPtr)SecurityLookupIDByType(client, rid, RT_WINDOW, access_mode); - if (pWin && pWin->drawable.type == DRAWABLE_WINDOW) { - client->lastDrawable = (DrawablePtr) pWin; - client->lastDrawableID = rid; - client->lastGCID = INVALID; - client->lastGC = (GCPtr)NULL; - } - return pWin; + return (WindowPtr)SecurityLookupIDByType(client, rid, RT_WINDOW, access_mode); } @@ -240,11 +224,6 @@ SecurityLookupDrawable(XID rid, ClientPtr client, Mask access_mode) if(rid == INVALID) return (pointer) NULL; - if (client->trustLevel != XSecurityClientTrusted) - return (DrawablePtr)SecurityLookupIDByClass(client, rid, RC_DRAWABLE, - access_mode); - if (client->lastDrawableID == rid) - return ((pointer) client->lastDrawable); pDraw = (DrawablePtr)SecurityLookupIDByClass(client, rid, RC_DRAWABLE, access_mode); if (pDraw && (pDraw->type != UNDRAWABLE_WINDOW)) @@ -268,7 +247,7 @@ LookupDrawable(XID rid, ClientPtr client) return SecurityLookupDrawable(rid, client, SecurityUnknownAccess); } -#else /* not XCSECURITY */ +#else /* not XACE */ WindowPtr LookupWindow(XID rid, ClientPtr client) @@ -310,7 +289,7 @@ LookupDrawable(XID rid, ClientPtr client) return (pointer)NULL; } -#endif /* XCSECURITY */ +#endif /* XACE */ _X_EXPORT ClientPtr LookupClient(XID rid, ClientPtr client) diff --git a/dix/events.c b/dix/events.c index 7225543a3..c57a30ed8 100644 --- a/dix/events.c +++ b/dix/events.c @@ -135,8 +135,8 @@ of the copyright holder. extern Bool XkbFilterEvents(ClientPtr, int, xEvent *); #endif -#ifdef XCSECURITY -#include "securitysrv.h" +#ifdef XACE +#include "xace.h" #endif #ifdef XEVIE @@ -2476,8 +2476,8 @@ CheckPassiveGrabsOnWindow( (grab->confineTo->realized && BorderSizeNotEmpty(grab->confineTo)))) { -#ifdef XCSECURITY - if (!SecurityCheckDeviceAccess(wClient(pWin), device, FALSE)) +#ifdef XACE + if (!XaceHook(XACE_DEVICE_ACCESS, wClient(pWin), device, FALSE)) return FALSE; #endif #ifdef XKB @@ -2846,6 +2846,10 @@ drawable.id:0; DeliverFocusedEvent(keybd, xE, sprite.win, count); if (deactivateGrab) (*keybd->DeactivateGrab)(keybd); + +#ifdef XACE + XaceHook(XACE_KEY_AVAIL, xE, keybd, count); +#endif } #ifdef XKB @@ -3279,10 +3283,10 @@ EnterLeaveEvent( { xKeymapEvent ke; -#ifdef XCSECURITY +#ifdef XACE ClientPtr client = grab ? rClient(grab) : clients[CLIENT_ID(pWin->drawable.id)]; - if (!SecurityCheckDeviceAccess(client, keybd, FALSE)) + if (!XaceHook(XACE_DEVICE_ACCESS, client, keybd, FALSE)) { bzero((char *)&ke.map[0], 31); } @@ -3374,9 +3378,9 @@ FocusEvent(DeviceIntPtr dev, int type, int mode, int detail, register WindowPtr ((pWin->eventMask | wOtherEventMasks(pWin)) & KeymapStateMask)) { xKeymapEvent ke; -#ifdef XCSECURITY +#ifdef XACE ClientPtr client = clients[CLIENT_ID(pWin->drawable.id)]; - if (!SecurityCheckDeviceAccess(client, dev, FALSE)) + if (!XaceHook(XACE_DEVICE_ACCESS, client, dev, FALSE)) { bzero((char *)&ke.map[0], 31); } @@ -3645,8 +3649,8 @@ ProcSetInputFocus(client) REQUEST(xSetInputFocusReq); REQUEST_SIZE_MATCH(xSetInputFocusReq); -#ifdef XCSECURITY - if (!SecurityCheckDeviceAccess(client, inputInfo.keyboard, TRUE)) +#ifdef XACE + if (!XaceHook(XACE_DEVICE_ACCESS, client, inputInfo.keyboard, TRUE)) return Success; #endif return SetInputFocus(client, inputInfo.keyboard, stuff->focus, @@ -3910,8 +3914,8 @@ ProcGrabKeyboard(ClientPtr client) int result; REQUEST_SIZE_MATCH(xGrabKeyboardReq); -#ifdef XCSECURITY - if (!SecurityCheckDeviceAccess(client, inputInfo.keyboard, TRUE)) +#ifdef XACE + if (!XaceHook(XACE_DEVICE_ACCESS, client, inputInfo.keyboard, TRUE)) { result = Success; rep.status = AlreadyGrabbed; diff --git a/dix/extension.c b/dix/extension.c index 5ad457940..f58c73138 100644 --- a/dix/extension.c +++ b/dix/extension.c @@ -59,8 +59,8 @@ SOFTWARE. #include "gcstruct.h" #include "scrnintstr.h" #include "dispatch.h" -#ifdef XCSECURITY -#include "securitysrv.h" +#ifdef XACE +#include "xace.h" #endif #define EXTENSION_BASE 128 @@ -76,6 +76,39 @@ int lastEvent = EXTENSION_EVENT_BASE; static int lastError = FirstExtensionError; static unsigned int NumExtensions = 0; +extern int extensionPrivateLen; +extern unsigned *extensionPrivateSizes; +extern unsigned totalExtensionSize; + +static void +InitExtensionPrivates(ExtensionEntry *ext) +{ + register char *ptr; + DevUnion *ppriv; + register unsigned *sizes; + register unsigned size; + register int i; + + if (totalExtensionSize == sizeof(ExtensionEntry)) + ppriv = (DevUnion *)NULL; + else + ppriv = (DevUnion *)(ext + 1); + + ext->devPrivates = ppriv; + sizes = extensionPrivateSizes; + ptr = (char *)(ppriv + extensionPrivateLen); + for (i = extensionPrivateLen; --i >= 0; ppriv++, sizes++) + { + if ( (size = *sizes) ) + { + ppriv->ptr = (pointer)ptr; + ptr += size; + } + else + ppriv->ptr = (pointer)NULL; + } +} + _X_EXPORT ExtensionEntry * AddExtension(char *name, int NumEvents, int NumErrors, int (*MainProc)(ClientPtr c1), @@ -92,9 +125,11 @@ AddExtension(char *name, int NumEvents, int NumErrors, (unsigned)(lastError + NumErrors > LAST_ERROR)) return((ExtensionEntry *) NULL); - ext = (ExtensionEntry *) xalloc(sizeof(ExtensionEntry)); + ext = (ExtensionEntry *) xalloc(totalExtensionSize); if (!ext) return((ExtensionEntry *) NULL); + bzero(ext, totalExtensionSize); + InitExtensionPrivates(ext); ext->name = (char *)xalloc(strlen(name) + 1); ext->num_aliases = 0; ext->aliases = (char **)NULL; @@ -144,9 +179,6 @@ AddExtension(char *name, int NumEvents, int NumErrors, ext->errorBase = 0; ext->errorLast = 0; } -#ifdef XCSECURITY - ext->secure = FALSE; -#endif return(ext); } @@ -207,26 +239,27 @@ CheckExtension(const char *extname) return NULL; } +/* + * Added as part of Xace. + */ +ExtensionEntry * +GetExtensionEntry(int major) +{ + if (major < EXTENSION_BASE) + return NULL; + major -= EXTENSION_BASE; + if (major >= NumExtensions) + return NULL; + return extensions[major]; +} + _X_EXPORT void DeclareExtensionSecurity(char *extname, Bool secure) { -#ifdef XCSECURITY +#ifdef XACE int i = FindExtension(extname, strlen(extname)); if (i >= 0) - { - int majorop = extensions[i]->base; - extensions[i]->secure = secure; - if (secure) - { - UntrustedProcVector[majorop] = ProcVector[majorop]; - SwappedUntrustedProcVector[majorop] = SwappedProcVector[majorop]; - } - else - { - UntrustedProcVector[majorop] = ProcBadRequest; - SwappedUntrustedProcVector[majorop] = ProcBadRequest; - } - } + XaceHook(XACE_DECLARE_EXT_SECURE, extensions[i], secure); #endif } @@ -304,10 +337,9 @@ ProcQueryExtension(ClientPtr client) { i = FindExtension((char *)&stuff[1], stuff->nbytes); if (i < 0 -#ifdef XCSECURITY - /* don't show insecure extensions to untrusted clients */ - || (client->trustLevel == XSecurityClientUntrusted && - !extensions[i]->secure) +#ifdef XACE + /* call callbacks to find out whether to show extension */ + || !XaceHook(XACE_EXT_ACCESS, client, extensions[i]) #endif ) reply.present = xFalse; @@ -344,10 +376,9 @@ ProcListExtensions(ClientPtr client) for (i=0; itrustLevel == XSecurityClientUntrusted && - !extensions[i]->secure) +#ifdef XACE + /* call callbacks to find out whether to show extension */ + if (!XaceHook(XACE_EXT_ACCESS, client, extensions[i])) continue; #endif total_length += strlen(extensions[i]->name) + 1; @@ -362,9 +393,8 @@ ProcListExtensions(ClientPtr client) for (i=0; itrustLevel == XSecurityClientUntrusted && - !extensions[i]->secure) +#ifdef XACE + if (!XaceHook(XACE_EXT_ACCESS, client, extensions[i])) continue; #endif *bufptr++ = len = strlen(extensions[i]->name); diff --git a/dix/main.c b/dix/main.c index 3fb4cdd9c..f3cde189c 100644 --- a/dix/main.c +++ b/dix/main.c @@ -354,6 +354,7 @@ main(int argc, char *argv[], char *envp[]) InitAtoms(); InitEvents(); InitGlyphCaching(); + ResetExtensionPrivates(); ResetClientPrivates(); ResetScreenPrivates(); ResetWindowPrivates(); diff --git a/dix/privates.c b/dix/privates.c index 46b696416..b20a1dbf0 100644 --- a/dix/privates.c +++ b/dix/privates.c @@ -42,6 +42,7 @@ from The Open Group. #include "servermd.h" #include "site.h" #include "inputstr.h" +#include "extnsionst.h" /* * See the Wrappers and devPrivates section in "Definition of the @@ -49,6 +50,63 @@ from The Open Group. * for information on how to use devPrivates. */ +/* + * extension private machinery + */ + +static int extensionPrivateCount; +int extensionPrivateLen; +unsigned *extensionPrivateSizes; +unsigned totalExtensionSize; + +void +ResetExtensionPrivates() +{ + extensionPrivateCount = 0; + extensionPrivateLen = 0; + xfree(extensionPrivateSizes); + extensionPrivateSizes = (unsigned *)NULL; + totalExtensionSize = + ((sizeof(ExtensionEntry) + sizeof(long) - 1) / sizeof(long)) * sizeof(long); +} + +_X_EXPORT int +AllocateExtensionPrivateIndex() +{ + return extensionPrivateCount++; +} + +_X_EXPORT Bool +AllocateExtensionPrivate(int index2, unsigned amount) +{ + unsigned oldamount; + + /* Round up sizes for proper alignment */ + amount = ((amount + (sizeof(long) - 1)) / sizeof(long)) * sizeof(long); + + if (index2 >= extensionPrivateLen) + { + unsigned *nsizes; + nsizes = (unsigned *)xrealloc(extensionPrivateSizes, + (index2 + 1) * sizeof(unsigned)); + if (!nsizes) + return FALSE; + while (extensionPrivateLen <= index2) + { + nsizes[extensionPrivateLen++] = 0; + totalExtensionSize += sizeof(DevUnion); + } + extensionPrivateSizes = nsizes; + } + oldamount = extensionPrivateSizes[index2]; + if (amount > oldamount) + { + extensionPrivateSizes[index2] = amount; + totalExtensionSize += (amount - oldamount); + } + return TRUE; +} + /* * client private machinery */ diff --git a/dix/property.c b/dix/property.c index 5588a90b0..da983838f 100644 --- a/dix/property.c +++ b/dix/property.c @@ -58,8 +58,8 @@ SOFTWARE. #include "dixstruct.h" #include "dispatch.h" #include "swaprep.h" -#ifdef XCSECURITY -#include "securitysrv.h" +#ifdef XACE +#include "xace.h" #endif /***************************************************************** @@ -118,12 +118,12 @@ ProcRotateProperties(ClientPtr client) return(BadAlloc); for (i = 0; i < stuff->nAtoms; i++) { -#ifdef XCSECURITY - char action = SecurityCheckPropertyAccess(client, pWin, atoms[i], +#ifdef XACE + char action = XaceHook(XACE_PROPERTY_ACCESS, client, pWin, atoms[i], SecurityReadAccess|SecurityWriteAccess); #endif if (!ValidAtom(atoms[i]) -#ifdef XCSECURITY +#ifdef XACE || (SecurityErrorOperation == action) #endif ) @@ -132,7 +132,7 @@ ProcRotateProperties(ClientPtr client) client->errorValue = atoms[i]; return BadAtom; } -#ifdef XCSECURITY +#ifdef XACE if (SecurityIgnoreOperation == action) { DEALLOCATE_LOCAL(props); @@ -233,8 +233,8 @@ ProcChangeProperty(ClientPtr client) return(BadAtom); } -#ifdef XCSECURITY - switch (SecurityCheckPropertyAccess(client, pWin, stuff->property, +#ifdef XACE + switch (XaceHook(XACE_PROPERTY_ACCESS, client, pWin, stuff->property, SecurityWriteAccess)) { case SecurityErrorOperation: @@ -501,13 +501,13 @@ ProcGetProperty(ClientPtr client) if (!pProp) return NullPropertyReply(client, None, 0, &reply); -#ifdef XCSECURITY +#ifdef XACE { Mask access_mode = SecurityReadAccess; if (stuff->delete) access_mode |= SecurityDestroyAccess; - switch(SecurityCheckPropertyAccess(client, pWin, stuff->property, + switch(XaceHook(XACE_PROPERTY_ACCESS, client, pWin, stuff->property, access_mode)) { case SecurityErrorOperation: @@ -663,8 +663,8 @@ ProcDeleteProperty(register ClientPtr client) return (BadAtom); } -#ifdef XCSECURITY - switch(SecurityCheckPropertyAccess(client, pWin, stuff->property, +#ifdef XACE + switch(XaceHook(XACE_PROPERTY_ACCESS, client, pWin, stuff->property, SecurityDestroyAccess)) { case SecurityErrorOperation: diff --git a/dix/resource.c b/dix/resource.c index 39374cc8d..b2d01c8f3 100644 --- a/dix/resource.c +++ b/dix/resource.c @@ -120,6 +120,9 @@ Equipment Corporation. #include "panoramiX.h" #include "panoramiXsrv.h" #endif +#ifdef XACE +#include "xace.h" +#endif #include static void RebuildTable( @@ -818,8 +821,6 @@ LegalNewID(XID id, register ClientPtr client) !LookupIDByClass(id, RC_ANY))); } -#ifdef XCSECURITY - /* SecurityLookupIDByType and SecurityLookupIDByClass: * These are the heart of the resource ID security system. They take * two additional arguments compared to the old LookupID functions: @@ -835,10 +836,6 @@ SecurityLookupIDByType(ClientPtr client, XID id, RESTYPE rtype, Mask mode) register ResourcePtr res; pointer retval = NULL; - assert(client == NullClient || - (client->index <= currentMaxClients && clients[client->index] == client)); - assert( (rtype & TypeMask) <= lastResourceType); - if (((cid = CLIENT_ID(id)) < MAXCLIENTS) && clientTable[cid].buckets) { @@ -851,8 +848,11 @@ SecurityLookupIDByType(ClientPtr client, XID id, RESTYPE rtype, Mask mode) break; } } - if (retval && client && client->CheckAccess) - retval = (* client->CheckAccess)(client, id, rtype, mode, retval); +#ifdef XACE + if (retval && client && + !XaceHook(XACE_RESOURCE_ACCESS, client, id, rtype, mode, retval)) + retval = NULL; +#endif return retval; } @@ -864,10 +864,6 @@ SecurityLookupIDByClass(ClientPtr client, XID id, RESTYPE classes, Mask mode) register ResourcePtr res = NULL; pointer retval = NULL; - assert(client == NullClient || - (client->index <= currentMaxClients && clients[client->index] == client)); - assert (classes >= lastResourceClass); - if (((cid = CLIENT_ID(id)) < MAXCLIENTS) && clientTable[cid].buckets) { @@ -880,8 +876,11 @@ SecurityLookupIDByClass(ClientPtr client, XID id, RESTYPE classes, Mask mode) break; } } - if (retval && client && client->CheckAccess) - retval = (* client->CheckAccess)(client, id, res->type, mode, retval); +#ifdef XACE + if (retval && client && + !XaceHook(XACE_RESOURCE_ACCESS, client, id, res->type, mode, retval)) + retval = NULL; +#endif return retval; } @@ -902,50 +901,3 @@ LookupIDByClass(XID id, RESTYPE classes) return SecurityLookupIDByClass(NullClient, id, classes, SecurityUnknownAccess); } - -#else /* not XCSECURITY */ - -/* - * LookupIDByType returns the object with the given id and type, else NULL. - */ -pointer -LookupIDByType(XID id, RESTYPE rtype) -{ - int cid; - register ResourcePtr res; - - if (((cid = CLIENT_ID(id)) < MAXCLIENTS) && - clientTable[cid].buckets) - { - res = clientTable[cid].resources[Hash(cid, id)]; - - for (; res; res = res->next) - if ((res->id == id) && (res->type == rtype)) - return res->value; - } - return (pointer)NULL; -} - -/* - * LookupIDByClass returns the object with the given id and any one of the - * given classes, else NULL. - */ -pointer -LookupIDByClass(XID id, RESTYPE classes) -{ - int cid; - register ResourcePtr res; - - if (((cid = CLIENT_ID(id)) < MAXCLIENTS) && - clientTable[cid].buckets) - { - res = clientTable[cid].resources[Hash(cid, id)]; - - for (; res; res = res->next) - if ((res->id == id) && (res->type & classes)) - return res->value; - } - return (pointer)NULL; -} - -#endif /* XCSECURITY */ diff --git a/dix/window.c b/dix/window.c index 0beeb3a4d..3dfeda36e 100644 --- a/dix/window.c +++ b/dix/window.c @@ -126,8 +126,8 @@ Equipment Corporation. #ifdef XAPPGROUP #include "appgroup.h" #endif -#ifdef XCSECURITY -#include "securitysrv.h" +#ifdef XACE +#include "xace.h" #endif /****** @@ -530,6 +530,10 @@ InitRootWindow(WindowPtr pWin) /* We SHOULD check for an error value here XXX */ (*pScreen->ChangeWindowAttributes)(pWin, backFlag); +#ifdef XACE + XaceHook(XACE_WINDOW_INIT, serverClient, pWin); +#endif + MapWindow(pWin, serverClient); } @@ -731,11 +735,11 @@ CreateWindow(Window wid, register WindowPtr pParent, int x, int y, unsigned w, } pWin->borderWidth = bw; -#ifdef XCSECURITY +#ifdef XACE /* can't let untrusted clients have background None windows; * they make it too easy to steal window contents */ - if (client->trustLevel != XSecurityClientTrusted) + if (!XaceHook(XACE_BACKGRND_ACCESS, client, pWin)) { pWin->backgroundState = BackgroundPixel; pWin->background.pixel = 0; @@ -762,6 +766,10 @@ CreateWindow(Window wid, register WindowPtr pParent, int x, int y, unsigned w, REGION_NULL(pScreen, &pWin->winSize); REGION_NULL(pScreen, &pWin->borderSize); +#ifdef XACE + XaceHook(XACE_WINDOW_INIT, client, pWin); +#endif + pHead = RealChildHead(pParent); if (pHead) { @@ -1025,9 +1033,9 @@ ChangeWindowAttributes(register WindowPtr pWin, Mask vmask, XID *vlist, ClientPt borderRelative = TRUE; if (pixID == None) { -#ifdef XCSECURITY +#ifdef XACE /* can't let untrusted clients have background None windows */ - if (client->trustLevel == XSecurityClientTrusted) + if (XaceHook(XACE_BACKGRND_ACCESS, client, pWin)) { #endif if (pWin->backgroundState == BackgroundPixmap) @@ -1036,7 +1044,7 @@ ChangeWindowAttributes(register WindowPtr pWin, Mask vmask, XID *vlist, ClientPt MakeRootTile(pWin); else pWin->backgroundState = None; -#ifdef XCSECURITY +#ifdef XACE } else { /* didn't change the background to None, so don't tell ddx */ @@ -2724,13 +2732,9 @@ MapWindow(register WindowPtr pWin, ClientPtr client) if (pWin->mapped) return(Success); -#ifdef XCSECURITY - /* don't let an untrusted client map a child-of-trusted-window, InputOnly - * window; too easy to steal device input - */ - if ( (client->trustLevel != XSecurityClientTrusted) && - (pWin->drawable.class == InputOnly) && - (wClient(pWin->parent)->trustLevel == XSecurityClientTrusted) ) +#ifdef XACE + /* general check for permission to map window */ + if (!XaceHook(XACE_MAP_ACCESS, client, pWin)) return Success; #endif diff --git a/doc/Xserver.man.pre b/doc/Xserver.man.pre index b9597f15c..d65acde6a 100644 --- a/doc/Xserver.man.pre +++ b/doc/Xserver.man.pre @@ -181,7 +181,7 @@ prints a usage message. causes all remaining command line arguments to be ignored. .TP 8 .B \-maxbigreqsize \fIsize\fP -sets the maxmium big request to +sets the maximum big request to .I size MB. .TP 8 @@ -449,7 +449,7 @@ the text after the /; it is used to distinguish between instances of ::= a | i | e - ::= | | + ::= | | ::= " * " diff --git a/fb/Makefile.am b/fb/Makefile.am index 11b2d2fea..1649669c0 100644 --- a/fb/Makefile.am +++ b/fb/Makefile.am @@ -1,4 +1,4 @@ -noinst_LTLIBRARIES = libfb.la libfbmmx.la +noinst_LTLIBRARIES = libfb.la libwfb.la libfbmmx.la INCLUDES = \ -I$(top_srcdir)/hw/xfree86/os-support \ @@ -7,11 +7,13 @@ INCLUDES = \ AM_CFLAGS = $(DIX_CFLAGS) if XORG -sdk_HEADERS = fb.h fbrop.h fbpseudocolor.h fboverlay.h +sdk_HEADERS = fb.h fbrop.h fbpseudocolor.h fboverlay.h wfbrename.h endif +libfb_la_CFLAGS = $(AM_CFLAGS) + if MMX_CAPABLE -AM_CFLAGS += -DUSE_MMX +libfb_la_CFLAGS += -DUSE_MMX libfbmmx_la_CFLAGS = \ $(DIX_CFLAGS) \ @@ -23,6 +25,8 @@ libfbmmx_la_CFLAGS = \ --param large-function-growth=10000 endif +libwfb_la_CFLAGS = $(AM_CFLAGS) -DFB_ACCESS_WRAPPER + libfbmmx_la_SOURCES = \ fbmmx.c \ fbmmx.h @@ -70,6 +74,8 @@ libfb_la_SOURCES = \ fbedge.c \ fbedgeimp.h +libwfb_la_SOURCES = $(libfb_la_SOURCES) + libfb_la_LIBADD = libfbmmx.la EXTRA_DIST = fbcmap.c diff --git a/fb/fb.h b/fb/fb.h index 3742cf01a..de0b3a8c2 100644 --- a/fb/fb.h +++ b/fb/fb.h @@ -44,6 +44,39 @@ #include "picture.h" #endif +#ifdef FB_ACCESS_WRAPPER + +#include "wfbrename.h" +#define FBPREFIX(x) wfb##x +#define WRITE(ptr, val) ((*wfbWriteMemory)((ptr), (val), sizeof(*(ptr)))) +#define READ(ptr) ((*wfbReadMemory)((ptr), sizeof(*(ptr)))) + +#define MEMCPY_WRAPPED(dst, src, size) do { \ + size_t _i; \ + CARD8 *_dst = (CARD8*)(dst), *_src = (CARD8*)(src); \ + for(_i = 0; _i < size; _i++) { \ + WRITE(_dst +_i, READ(_src + _i)); \ + } \ +} while(0) + +#define MEMSET_WRAPPED(dst, val, size) do { \ + size_t _i; \ + CARD8 *_dst = (CARD8*)(dst); \ + for(_i = 0; _i < size; _i++) { \ + WRITE(_dst +_i, (val)); \ + } \ +} while(0) + +#else + +#define FBPREFIX(x) fb##x +#define WRITE(ptr, val) (*(ptr) = (val)) +#define READ(ptr) (*(ptr)) +#define MEMCPY_WRAPPED(dst, src, size) memcpy((dst), (src), (size)) +#define MEMSET_WRAPPED(dst, val, size) memset((dst), (val), (size)) + +#endif + /* * This single define controls the basic size of data manipulated * by this software; it must be log2(sizeof (FbBits) * 8) @@ -222,8 +255,8 @@ extern void fbSetBits (FbStip *bits, int stride, FbStip data); #define FbPtrOffset(p,o,t) ((t *) ((CARD8 *) (p) + (o))) #define FbSelectPatternPart(xor,o,t) ((xor) >> (FbPatternOffset (o,t) << 3)) -#define FbStorePart(dst,off,t,xor) (*FbPtrOffset(dst,off,t) = \ - FbSelectPart(xor,off,t)) +#define FbStorePart(dst,off,t,xor) (WRITE(FbPtrOffset(dst,off,t), \ + FbSelectPart(xor,off,t))) #ifndef FbSelectPart #define FbSelectPart(x,o,t) FbSelectPatternPart(x,o,t) #endif @@ -403,7 +436,7 @@ extern void fbSetBits (FbStip *bits, int stride, FbStip data); FbStorePart(dst,sizeof (FbBits) - 1,CARD8,xor); \ break; \ default: \ - *dst = FbDoMaskRRop(*dst, and, xor, l); \ + WRITE(dst, FbDoMaskRRop(READ(dst), and, xor, l)); \ break; \ } \ } @@ -423,7 +456,7 @@ extern void fbSetBits (FbStip *bits, int stride, FbStip data); break; \ FbDoRightMaskByteRRop6Cases(dst,xor) \ default: \ - *dst = FbDoMaskRRop (*dst, and, xor, r); \ + WRITE(dst, FbDoMaskRRop (READ(dst), and, xor, r)); \ } \ } #endif @@ -455,20 +488,20 @@ extern void fbSetBits (FbStip *bits, int stride, FbStip data); * The term "lane" comes from the hardware term "byte-lane" which */ -#define FbLaneCase1(n,a,o) ((n) == 0x01 ? \ - (*(CARD8 *) ((a)+FbPatternOffset(o,CARD8)) = \ - fgxor) : 0) -#define FbLaneCase2(n,a,o) ((n) == 0x03 ? \ - (*(CARD16 *) ((a)+FbPatternOffset(o,CARD16)) = \ +#define FbLaneCase1(n,a,o) ((n) == 0x01 ? (void) \ + WRITE((CARD8 *) ((a)+FbPatternOffset(o,CARD8)), \ + fgxor) : (void) 0) +#define FbLaneCase2(n,a,o) ((n) == 0x03 ? (void) \ + WRITE((CARD16 *) ((a)+FbPatternOffset(o,CARD16)), \ fgxor) : \ ((void)FbLaneCase1((n)&1,a,o), \ FbLaneCase1((n)>>1,a,(o)+1))) -#define FbLaneCase4(n,a,o) ((n) == 0x0f ? \ - (*(CARD32 *) ((a)+FbPatternOffset(o,CARD32)) = \ +#define FbLaneCase4(n,a,o) ((n) == 0x0f ? (void) \ + WRITE((CARD32 *) ((a)+FbPatternOffset(o,CARD32)), \ fgxor) : \ ((void)FbLaneCase2((n)&3,a,o), \ FbLaneCase2((n)>>2,a,(o)+2))) -#define FbLaneCase8(n,a,o) ((n) == 0x0ff ? (*(FbBits *) ((a)+(o)) = fgxor) : \ +#define FbLaneCase8(n,a,o) ((n) == 0x0ff ? (void) (*(FbBits *) ((a)+(o)) = fgxor) : \ ((void)FbLaneCase4((n)&15,a,o), \ FbLaneCase4((n)>>4,a,(o)+4))) @@ -588,6 +621,32 @@ extern WindowPtr *WindowTable; #define FB_SCREEN_PRIVATE #endif +/* Framebuffer access wrapper */ +typedef FbBits (*ReadMemoryProcPtr)(const void *src, int size); +typedef void (*WriteMemoryProcPtr)(void *dst, FbBits value, int size); +typedef void (*SetupWrapProcPtr)(ReadMemoryProcPtr *pRead, + WriteMemoryProcPtr *pWrite, + DrawablePtr pDraw); +typedef void (*FinishWrapProcPtr)(DrawablePtr pDraw); + +#ifdef FB_ACCESS_WRAPPER + +#define fbPrepareAccess(pDraw) \ + fbGetScreenPrivate((pDraw)->pScreen)->setupWrap( \ + &wfbReadMemory, \ + &wfbWriteMemory, \ + (pDraw)) +#define fbFinishAccess(pDraw) \ + fbGetScreenPrivate((pDraw)->pScreen)->finishWrap(pDraw) + +#else + +#define fbPrepareAccess(pPix) +#define fbFinishAccess(pDraw) + +#endif + + #ifdef FB_SCREEN_PRIVATE extern int fbScreenPrivateIndex; extern int fbGetScreenPrivateIndex(void); @@ -596,6 +655,10 @@ extern int fbGetScreenPrivateIndex(void); typedef struct { unsigned char win32bpp; /* window bpp for 32-bpp images */ unsigned char pix32bpp; /* pixmap bpp for 32-bpp images */ +#ifdef FB_ACCESS_WRAPPER + SetupWrapProcPtr setupWrap; /* driver hook to set pixmap access wrapping */ + FinishWrapProcPtr finishWrap; /* driver hook to clean up pixmap access wrapping */ +#endif } FbScreenPrivRec, *FbScreenPrivPtr; #define fbGetScreenPrivate(pScreen) ((FbScreenPrivPtr) \ @@ -674,6 +737,7 @@ typedef struct { (xoff) = __fbPixOffXPix(_pPix); \ (yoff) = __fbPixOffYPix(_pPix); \ } \ + fbPrepareAccess(pDrawable); \ (pointer) = (FbBits *) _pPix->devPrivate.ptr; \ (stride) = ((int) _pPix->devKind) / sizeof (FbBits); (void)(stride); \ (bpp) = _pPix->drawable.bitsPerPixel; (void)(bpp); \ @@ -690,6 +754,7 @@ typedef struct { (xoff) = __fbPixOffXPix(_pPix); \ (yoff) = __fbPixOffYPix(_pPix); \ } \ + fbPrepareAccess(pDrawable); \ (pointer) = (FbStip *) _pPix->devPrivate.ptr; \ (stride) = ((int) _pPix->devKind) / sizeof (FbStip); (void)(stride); \ (bpp) = _pPix->drawable.bitsPerPixel; (void)(bpp); \ @@ -1738,6 +1803,30 @@ fbSetupScreen(ScreenPtr pScreen, int width, /* pixel width of frame buffer */ int bpp); /* bits per pixel of frame buffer */ +Bool +wfbFinishScreenInit(ScreenPtr pScreen, + pointer pbits, + int xsize, + int ysize, + int dpix, + int dpiy, + int width, + int bpp, + SetupWrapProcPtr setupWrap, + FinishWrapProcPtr finishWrap); + +Bool +wfbScreenInit(ScreenPtr pScreen, + pointer pbits, + int xsize, + int ysize, + int dpix, + int dpiy, + int width, + int bpp, + SetupWrapProcPtr setupWrap, + FinishWrapProcPtr finishWrap); + Bool fbFinishScreenInit(ScreenPtr pScreen, pointer pbits, @@ -1994,6 +2083,11 @@ fbReplicatePixel (Pixel p, int bpp); void fbReduceRasterOp (int rop, FbBits fg, FbBits pm, FbBits *andp, FbBits *xorp); +#ifdef FB_ACCESS_WRAPPER +extern ReadMemoryProcPtr wfbReadMemory; +extern WriteMemoryProcPtr wfbWriteMemory; +#endif + /* * fbwindow.c */ diff --git a/fb/fb24_32.c b/fb/fb24_32.c index 572da4865..00b739b25 100644 --- a/fb/fb24_32.c +++ b/fb/fb24_32.c @@ -38,18 +38,18 @@ * by reading/writing aligned CARD32s where it's easy */ -#define Get8(a) ((CARD32) *(a)) +#define Get8(a) ((CARD32) READ(a)) #if BITMAP_BIT_ORDER == MSBFirst #define Get24(a) ((Get8(a) << 16) | (Get8((a)+1) << 8) | Get8((a)+2)) -#define Put24(a,p) (((a)[0] = (CARD8) ((p) >> 16)), \ - ((a)[1] = (CARD8) ((p) >> 8)), \ - ((a)[2] = (CARD8) (p))) +#define Put24(a,p) ((WRITE((a+0), (CARD8) ((p) >> 16))), \ + (WRITE((a+1), (CARD8) ((p) >> 8))), \ + (WRITE((a+2), (CARD8) (p)))) #else #define Get24(a) (Get8(a) | (Get8((a)+1) << 8) | (Get8((a)+2)<<16)) -#define Put24(a,p) (((a)[0] = (CARD8) (p)), \ - ((a)[1] = (CARD8) ((p) >> 8)), \ - ((a)[2] = (CARD8) ((p) >> 16))) +#define Put24(a,p) ((WRITE((a+0), (CARD8) (p))), \ + (WRITE((a+1), (CARD8) ((p) >> 8))), \ + (WRITE((a+2), (CARD8) ((p) >> 16)))) #endif typedef void (*fb24_32BltFunc) (CARD8 *srcLine, @@ -106,7 +106,7 @@ fb24_32BltDown (CARD8 *srcLine, while (((long) dst & 3) && w) { w--; - pixel = *src++; + pixel = READ(src++); pixel = FbDoDestInvarientMergeRop(pixel); Put24 (dst, pixel); dst += 3; @@ -115,35 +115,35 @@ fb24_32BltDown (CARD8 *srcLine, while (w >= 4) { CARD32 s0, s1; - s0 = *src++; + s0 = READ(src++); s0 = FbDoDestInvarientMergeRop(s0); - s1 = *src++; + s1 = READ(src++); s1 = FbDoDestInvarientMergeRop(s1); #if BITMAP_BIT_ORDER == LSBFirst - *(CARD32 *)(dst) = (s0 & 0xffffff) | (s1 << 24); + WRITE((CARD32 *)dst, (s0 & 0xffffff) | (s1 << 24)); #else - *(CARD32 *)(dst) = (s0 << 8) | ((s1 & 0xffffff) >> 16); + WRITE((CARD32 *)dst, (s0 << 8) | ((s1 & 0xffffff) >> 16)); #endif - s0 = *src++; + s0 = READ(src++); s0 = FbDoDestInvarientMergeRop(s0); #if BITMAP_BIT_ORDER == LSBFirst - *(CARD32 *)(dst+4) = ((s1 & 0xffffff) >> 8) | (s0 << 16); + WRITE((CARD32 *)(dst+4), ((s1 & 0xffffff) >> 8) | (s0 << 16)); #else - *(CARD32 *)(dst+4) = (s1 << 16) | ((s0 & 0xffffff) >> 8); + WRITE((CARD32 *)(dst+4), (s1 << 16) | ((s0 & 0xffffff) >> 8)); #endif - s1 = *src++; + s1 = READ(src++); s1 = FbDoDestInvarientMergeRop(s1); #if BITMAP_BIT_ORDER == LSBFirst - *(CARD32 *)(dst+8) = ((s0 & 0xffffff) >> 16) | (s1 << 8); + WRITE((CARD32 *)(dst+8), ((s0 & 0xffffff) >> 16) | (s1 << 8)); #else - *(CARD32 *)(dst+8) = (s0 << 24) | (s1 & 0xffffff); + WRITE((CARD32 *)(dst+8), (s0 << 24) | (s1 & 0xffffff)); #endif dst += 12; w -= 4; } while (w--) { - pixel = *src++; + pixel = READ(src++); pixel = FbDoDestInvarientMergeRop(pixel); Put24 (dst, pixel); dst += 3; @@ -153,7 +153,7 @@ fb24_32BltDown (CARD8 *srcLine, { while (w--) { - pixel = *src++; + pixel = READ(src++); dpixel = Get24 (dst); pixel = FbDoMergeRop(pixel, dpixel); Put24 (dst, pixel); @@ -205,40 +205,40 @@ fb24_32BltUp (CARD8 *srcLine, w--; pixel = Get24(src); src += 3; - *dst++ = FbDoDestInvarientMergeRop(pixel); + WRITE(dst++, FbDoDestInvarientMergeRop(pixel)); } /* Do four aligned pixels at a time */ while (w >= 4) { CARD32 s0, s1; - s0 = *(CARD32 *)(src); + s0 = READ((CARD32 *)src); #if BITMAP_BIT_ORDER == LSBFirst pixel = s0 & 0xffffff; #else pixel = s0 >> 8; #endif - *dst++ = FbDoDestInvarientMergeRop(pixel); - s1 = *(CARD32 *)(src+4); + WRITE(dst++, FbDoDestInvarientMergeRop(pixel)); + s1 = READ((CARD32 *)(src+4)); #if BITMAP_BIT_ORDER == LSBFirst pixel = (s0 >> 24) | ((s1 << 8) & 0xffffff); #else pixel = ((s0 << 16) & 0xffffff) | (s1 >> 16); #endif - *dst++ = FbDoDestInvarientMergeRop(pixel); - s0 = *(CARD32 *)(src+8); + WRITE(dst++, FbDoDestInvarientMergeRop(pixel)); + s0 = READ((CARD32 *)(src+8)); #if BITMAP_BIT_ORDER == LSBFirst pixel = (s1 >> 16) | ((s0 << 16) & 0xffffff); #else pixel = ((s1 << 8) & 0xffffff) | (s0 >> 24); #endif - *dst++ = FbDoDestInvarientMergeRop(pixel); + WRITE(dst++, FbDoDestInvarientMergeRop(pixel)); #if BITMAP_BIT_ORDER == LSBFirst pixel = s0 >> 8; #else pixel = s0 & 0xffffff; #endif - *dst++ = FbDoDestInvarientMergeRop(pixel); + WRITE(dst++, FbDoDestInvarientMergeRop(pixel)); src += 12; w -= 4; } @@ -247,7 +247,7 @@ fb24_32BltUp (CARD8 *srcLine, w--; pixel = Get24(src); src += 3; - *dst++ = FbDoDestInvarientMergeRop(pixel); + WRITE(dst++, FbDoDestInvarientMergeRop(pixel)); } } else @@ -256,7 +256,7 @@ fb24_32BltUp (CARD8 *srcLine, { pixel = Get24(src); src += 3; - *dst = FbDoMergeRop(pixel, *dst); + WRITE(dst, FbDoMergeRop(pixel, READ(dst))); dst++; } } @@ -305,6 +305,8 @@ fb24_32GetSpans(DrawablePtr pDrawable, ppt++; pwidth++; } + + fbFinishAccess (pDrawable); } void @@ -366,6 +368,8 @@ fb24_32SetSpans (DrawablePtr pDrawable, ppt++; pwidth++; } + + fbFinishAccess (pDrawable); } /* @@ -429,6 +433,8 @@ fb24_32PutZImage (DrawablePtr pDrawable, alu, pm); } + + fbFinishAccess (pDrawable); } void @@ -463,6 +469,8 @@ fb24_32GetImage (DrawablePtr pDrawable, fb24_32BltUp (src + (y + srcYoff) * srcStride, srcStride, x + srcXoff, (CARD8 *) d, dstStride, 0, w, h, GXcopy, pm); + + fbFinishAccess (pDrawable); } void @@ -519,6 +527,9 @@ fb24_32CopyMtoN (DrawablePtr pSrcDrawable, pPriv->pm); pbox++; } + + fbFinishAccess (pSrcDrawable); + fbFinishAccess (pDstDrawable); } PixmapPtr @@ -563,6 +574,9 @@ fb24_32ReformatTile(PixmapPtr pOldTile, int bitsPerPixel) GXcopy, FB_ALLONES); + fbFinishAccess (&pOldTile->drawable); + fbFinishAccess (&pNewTile->drawable); + return pNewTile; } diff --git a/fb/fballpriv.c b/fb/fballpriv.c index 3c05ff36e..4f807ed8d 100644 --- a/fb/fballpriv.c +++ b/fb/fballpriv.c @@ -90,3 +90,8 @@ fbAllocatePrivates(ScreenPtr pScreen, int *pGCIndex) #endif return TRUE; } + +#ifdef FB_ACCESS_WRAPPER +ReadMemoryProcPtr wfbReadMemory; +WriteMemoryProcPtr wfbWriteMemory; +#endif diff --git a/fb/fbarc.c b/fb/fbarc.c index 8f4d2960e..d2c1a76f1 100644 --- a/fb/fbarc.c +++ b/fb/fbarc.c @@ -109,6 +109,7 @@ fbPolyArc (DrawablePtr pDrawable, miPolyArc(pDrawable, pGC, 1, parcs); parcs++; } + fbFinishAccess (pDrawable); } else #endif diff --git a/fb/fbbits.c b/fb/fbbits.c index 56b58df4e..cefe943b6 100644 --- a/fb/fbbits.c +++ b/fb/fbbits.c @@ -103,14 +103,14 @@ #define BITSUNIT BYTE #define BITSMUL 3 -#define FbDoTypeStore(b,t,x,s) (*((t *) (b)) = (x) >> (s)) -#define FbDoTypeRRop(b,t,a,x,s) (*((t *) (b)) = FbDoRRop(*((t *) (b)),\ - (a) >> (s), \ - (x) >> (s))) -#define FbDoTypeMaskRRop(b,t,a,x,m,s) (*((t *) (b)) = FbDoMaskRRop(*((t *) (b)),\ - (a) >> (s), \ - (x) >> (s), \ - (m) >> (s)) +#define FbDoTypeStore(b,t,x,s) WRITE(((t *) (b)), (x) >> (s)) +#define FbDoTypeRRop(b,t,a,x,s) WRITE((t *) (b), FbDoRRop(READ((t *) (b)),\ + (a) >> (s), \ + (x) >> (s))) +#define FbDoTypeMaskRRop(b,t,a,x,m,s) WRITE((t *) (b), FbDoMaskRRop(READ((t *) (b)),\ + (a) >> (s), \ + (x) >> (s), \ + (m) >> (s))) #if BITMAP_BIT_ORDER == LSBFirst #define BITSSTORE(b,x) ((unsigned long) (b) & 1 ? \ (FbDoTypeStore (b, CARD8, x, 0), \ diff --git a/fb/fbbits.h b/fb/fbbits.h index e5c006dbb..603c02929 100644 --- a/fb/fbbits.h +++ b/fb/fbbits.h @@ -42,13 +42,13 @@ #ifdef BITSSTORE #define STORE(b,x) BITSSTORE(b,x) #else -#define STORE(b,x) (*(b) = (x)) +#define STORE(b,x) WRITE((b), (x)) #endif #ifdef BITSRROP #define RROP(b,a,x) BITSRROP(b,a,x) #else -#define RROP(b,a,x) (*(b) = FbDoRRop (*(b), (a), (x))) +#define RROP(b,a,x) WRITE((b), FbDoRRop (READ(b), (a), (x))) #endif #ifdef BITSUNIT @@ -119,6 +119,8 @@ BRESSOLID (DrawablePtr pDrawable, e += e3; } } + + fbFinishAccess (pDrawable); } #endif @@ -263,6 +265,8 @@ onOffOdd: dashlen = len; } } + + fbFinishAccess (pDrawable); } #endif @@ -541,18 +545,18 @@ ARC (FbBits *dst, # define WRITE_ADDR4(n) ((n)) #endif -#define WRITE1(d,n,fg) ((d)[WRITE_ADDR1(n)] = (BITS) (fg)) +#define WRITE1(d,n,fg) WRITE(d + WRITE_ADDR1(n), (BITS) (fg)) #ifdef BITS2 -# define WRITE2(d,n,fg) (*((BITS2 *) &((d)[WRITE_ADDR2(n)])) = (BITS2) (fg)) +# define WRITE2(d,n,fg) WRITE((BITS2 *) &((d)[WRITE_ADDR2(n)]), (BITS2) (fg)) #else -# define WRITE2(d,n,fg) WRITE1(d,(n)+1,WRITE1(d,n,fg)) +# define WRITE2(d,n,fg) (WRITE1(d,n,fg), WRITE1(d,(n)+1,fg)) #endif #ifdef BITS4 -# define WRITE4(d,n,fg) (*((BITS4 *) &((d)[WRITE_ADDR4(n)])) = (BITS4) (fg)) +# define WRITE4(d,n,fg) WRITE((BITS4 *) &((d)[WRITE_ADDR4(n)]), (BITS4) (fg)) #else -# define WRITE4(d,n,fg) WRITE2(d,(n)+2,WRITE2(d,n,fg)) +# define WRITE4(d,n,fg) (WRITE2(d,n,fg), WRITE2(d,(n)+2,fg)) #endif void @@ -710,8 +714,10 @@ POLYLINE (DrawablePtr pDrawable, intToX(pt2) + xoff, intToY(pt2) + yoff, npt == 0 && pGC->capStyle != CapNotLast, &dashoffset); - if (!npt) + if (!npt) { + fbFinishAccess (pDrawable); return; + } pt1 = pt2; pt2 = *pts++; npt--; @@ -776,6 +782,7 @@ POLYLINE (DrawablePtr pDrawable, { RROP(bits,and,xor); } + fbFinishAccess (pDrawable); return; } pt1 = pt2; @@ -786,6 +793,8 @@ POLYLINE (DrawablePtr pDrawable, } } } + + fbFinishAccess (pDrawable); } #endif @@ -883,20 +892,20 @@ POLYSEGMENT (DrawablePtr pDrawable, FbMaskBits (dstX, width, startmask, nmiddle, endmask); if (startmask) { - *dstLine = FbDoMaskRRop (*dstLine, andBits, xorBits, startmask); + WRITE(dstLine, FbDoMaskRRop (READ(dstLine), andBits, xorBits, startmask)); dstLine++; } if (!andBits) while (nmiddle--) - *dstLine++ = xorBits; + WRITE(dstLine++, xorBits); else while (nmiddle--) { - *dstLine = FbDoRRop (*dstLine, andBits, xorBits); + WRITE(dstLine, FbDoRRop (READ(dstLine), andBits, xorBits)); dstLine++; } if (endmask) - *dstLine = FbDoMaskRRop (*dstLine, andBits, xorBits, endmask); + WRITE(dstLine, FbDoMaskRRop (READ(dstLine), andBits, xorBits, endmask)); } else { @@ -950,6 +959,8 @@ POLYSEGMENT (DrawablePtr pDrawable, } } } + + fbFinishAccess (pDrawable); } #endif diff --git a/fb/fbblt.c b/fb/fbblt.c index d176a7c27..e18981a83 100644 --- a/fb/fbblt.c +++ b/fb/fbblt.c @@ -92,10 +92,10 @@ fbBlt (FbBits *srcLine, if (!upsidedown) for (i = 0; i < height; i++) - memcpy(dst + i * dstStride, src + i * srcStride, width); + MEMCPY_WRAPPED(dst + i * dstStride, src + i * srcStride, width); else for (i = height - 1; i >= 0; i--) - memcpy(dst + i * dstStride, src + i * srcStride, width); + MEMCPY_WRAPPED(dst + i * dstStride, src + i * srcStride, width); return; } @@ -137,7 +137,7 @@ fbBlt (FbBits *srcLine, { if (endmask) { - bits = *--src; + bits = READ(--src); --dst; FbDoRightMaskByteMergeRop(dst, bits, endbyte, endmask); } @@ -145,20 +145,20 @@ fbBlt (FbBits *srcLine, if (destInvarient) { while (n--) - *--dst = FbDoDestInvarientMergeRop(*--src); + WRITE(--dst, FbDoDestInvarientMergeRop(READ(--src))); } else { while (n--) { - bits = *--src; + bits = READ(--src); --dst; - *dst = FbDoMergeRop (bits, *dst); + WRITE(dst, FbDoMergeRop (bits, READ(dst))); } } if (startmask) { - bits = *--src; + bits = READ(--src); --dst; FbDoLeftMaskByteMergeRop(dst, bits, startbyte, startmask); } @@ -167,7 +167,7 @@ fbBlt (FbBits *srcLine, { if (startmask) { - bits = *src++; + bits = READ(src++); FbDoLeftMaskByteMergeRop(dst, bits, startbyte, startmask); dst++; } @@ -198,20 +198,20 @@ fbBlt (FbBits *srcLine, } #endif while (n--) - *dst++ = FbDoDestInvarientMergeRop(*src++); + WRITE(dst++, FbDoDestInvarientMergeRop(READ(src++))); } else { while (n--) { - bits = *src++; - *dst = FbDoMergeRop (bits, *dst); + bits = READ(src++); + WRITE(dst, FbDoMergeRop (bits, READ(dst))); dst++; } } if (endmask) { - bits = *src; + bits = READ(src); FbDoRightMaskByteMergeRop(dst, bits, endbyte, endmask); } } @@ -240,13 +240,13 @@ fbBlt (FbBits *srcLine, if (reverse) { if (srcX < dstX) - bits1 = *--src; + bits1 = READ(--src); if (endmask) { bits = FbScrRight(bits1, rightShift); if (FbScrRight(endmask, leftShift)) { - bits1 = *--src; + bits1 = READ(--src); bits |= FbScrLeft(bits1, leftShift); } --dst; @@ -258,10 +258,10 @@ fbBlt (FbBits *srcLine, while (n--) { bits = FbScrRight(bits1, rightShift); - bits1 = *--src; + bits1 = READ(--src); bits |= FbScrLeft(bits1, leftShift); --dst; - *dst = FbDoDestInvarientMergeRop(bits); + WRITE(dst, FbDoDestInvarientMergeRop(bits)); } } else @@ -269,10 +269,10 @@ fbBlt (FbBits *srcLine, while (n--) { bits = FbScrRight(bits1, rightShift); - bits1 = *--src; + bits1 = READ(--src); bits |= FbScrLeft(bits1, leftShift); --dst; - *dst = FbDoMergeRop(bits, *dst); + WRITE(dst, FbDoMergeRop(bits, READ(dst))); } } if (startmask) @@ -280,7 +280,7 @@ fbBlt (FbBits *srcLine, bits = FbScrRight(bits1, rightShift); if (FbScrRight(startmask, leftShift)) { - bits1 = *--src; + bits1 = READ(--src); bits |= FbScrLeft(bits1, leftShift); } --dst; @@ -290,13 +290,13 @@ fbBlt (FbBits *srcLine, else { if (srcX > dstX) - bits1 = *src++; + bits1 = READ(src++); if (startmask) { bits = FbScrLeft(bits1, leftShift); if (FbScrLeft(startmask, rightShift)) { - bits1 = *src++; + bits1 = READ(src++); bits |= FbScrRight(bits1, rightShift); } FbDoLeftMaskByteMergeRop (dst, bits, startbyte, startmask); @@ -308,9 +308,9 @@ fbBlt (FbBits *srcLine, while (n--) { bits = FbScrLeft(bits1, leftShift); - bits1 = *src++; + bits1 = READ(src++); bits |= FbScrRight(bits1, rightShift); - *dst = FbDoDestInvarientMergeRop(bits); + WRITE(dst, FbDoDestInvarientMergeRop(bits)); dst++; } } @@ -319,9 +319,9 @@ fbBlt (FbBits *srcLine, while (n--) { bits = FbScrLeft(bits1, leftShift); - bits1 = *src++; + bits1 = READ(src++); bits |= FbScrRight(bits1, rightShift); - *dst = FbDoMergeRop(bits, *dst); + WRITE(dst, FbDoMergeRop(bits, READ(dst))); dst++; } } @@ -330,7 +330,7 @@ fbBlt (FbBits *srcLine, bits = FbScrLeft(bits1, leftShift); if (FbScrLeft(endmask, rightShift)) { - bits1 = *src; + bits1 = READ(src); bits |= FbScrRight(bits1, rightShift); } FbDoRightMaskByteMergeRop (dst, bits, endbyte, endmask); @@ -425,45 +425,45 @@ fbBlt24Line (FbBits *src, { if (endmask) { - bits = *--src; + bits = READ(--src); --dst; - *dst = FbDoMaskMergeRop (bits, *dst, mask & endmask); + WRITE(dst, FbDoMaskMergeRop (bits, READ(dst), mask & endmask)); mask = FbPrev24Pix (mask); } while (n--) { - bits = *--src; + bits = READ(--src); --dst; - *dst = FbDoMaskMergeRop (bits, *dst, mask); + WRITE(dst, FbDoMaskMergeRop (bits, READ(dst), mask)); mask = FbPrev24Pix (mask); } if (startmask) { - bits = *--src; + bits = READ(--src); --dst; - *dst = FbDoMaskMergeRop(bits, *dst, mask & startmask); + WRITE(dst, FbDoMaskMergeRop(bits, READ(dst), mask & startmask)); } } else { if (startmask) { - bits = *src++; - *dst = FbDoMaskMergeRop (bits, *dst, mask & startmask); + bits = READ(src++); + WRITE(dst, FbDoMaskMergeRop (bits, READ(dst), mask & startmask)); dst++; mask = FbNext24Pix(mask); } while (n--) { - bits = *src++; - *dst = FbDoMaskMergeRop (bits, *dst, mask); + bits = READ(src++); + WRITE(dst, FbDoMaskMergeRop (bits, READ(dst), mask)); dst++; mask = FbNext24Pix(mask); } if (endmask) { - bits = *src; - *dst = FbDoMaskMergeRop(bits, *dst, mask & endmask); + bits = READ(src); + WRITE(dst, FbDoMaskMergeRop(bits, READ(dst), mask & endmask)); } } } @@ -484,26 +484,26 @@ fbBlt24Line (FbBits *src, if (reverse) { if (srcX < dstX) - bits1 = *--src; + bits1 = READ(--src); if (endmask) { bits = FbScrRight(bits1, rightShift); if (FbScrRight(endmask, leftShift)) { - bits1 = *--src; + bits1 = READ(--src); bits |= FbScrLeft(bits1, leftShift); } --dst; - *dst = FbDoMaskMergeRop (bits, *dst, mask & endmask); + WRITE(dst, FbDoMaskMergeRop (bits, READ(dst), mask & endmask)); mask = FbPrev24Pix(mask); } while (n--) { bits = FbScrRight(bits1, rightShift); - bits1 = *--src; + bits1 = READ(--src); bits |= FbScrLeft(bits1, leftShift); --dst; - *dst = FbDoMaskMergeRop(bits, *dst, mask); + WRITE(dst, FbDoMaskMergeRop(bits, READ(dst), mask)); mask = FbPrev24Pix(mask); } if (startmask) @@ -511,32 +511,32 @@ fbBlt24Line (FbBits *src, bits = FbScrRight(bits1, rightShift); if (FbScrRight(startmask, leftShift)) { - bits1 = *--src; + bits1 = READ(--src); bits |= FbScrLeft(bits1, leftShift); } --dst; - *dst = FbDoMaskMergeRop (bits, *dst, mask & startmask); + WRITE(dst, FbDoMaskMergeRop (bits, READ(dst), mask & startmask)); } } else { if (srcX > dstX) - bits1 = *src++; + bits1 = READ(src++); if (startmask) { bits = FbScrLeft(bits1, leftShift); - bits1 = *src++; + bits1 = READ(src++); bits |= FbScrRight(bits1, rightShift); - *dst = FbDoMaskMergeRop (bits, *dst, mask & startmask); + WRITE(dst, FbDoMaskMergeRop (bits, READ(dst), mask & startmask)); dst++; mask = FbNext24Pix(mask); } while (n--) { bits = FbScrLeft(bits1, leftShift); - bits1 = *src++; + bits1 = READ(src++); bits |= FbScrRight(bits1, rightShift); - *dst = FbDoMaskMergeRop(bits, *dst, mask); + WRITE(dst, FbDoMaskMergeRop(bits, READ(dst), mask)); dst++; mask = FbNext24Pix(mask); } @@ -545,10 +545,10 @@ fbBlt24Line (FbBits *src, bits = FbScrLeft(bits1, leftShift); if (FbScrLeft(endmask, rightShift)) { - bits1 = *src; + bits1 = READ(src); bits |= FbScrRight(bits1, rightShift); } - *dst = FbDoMaskMergeRop (bits, *dst, mask & endmask); + WRITE(dst, FbDoMaskMergeRop (bits, READ(dst), mask & endmask)); } } } @@ -707,8 +707,8 @@ fbBltOdd (FbBits *srcLine, { if (startmask) { - bits = *src++; - *dst = FbDoMaskMergeRop (bits, *dst, startmask); + bits = READ(src++); + WRITE(dst, FbDoMaskMergeRop (bits, READ(dst), startmask)); dst++; } n = nmiddle; @@ -716,8 +716,8 @@ fbBltOdd (FbBits *srcLine, { while (n--) { - bits = *src++; - *dst = FbDoDestInvarientMergeRop(bits); + bits = READ(src++); + WRITE(dst, FbDoDestInvarientMergeRop(bits)); dst++; } } @@ -725,28 +725,28 @@ fbBltOdd (FbBits *srcLine, { while (n--) { - bits = *src++; - *dst = FbDoMergeRop (bits, *dst); + bits = READ(src++); + WRITE(dst, FbDoMergeRop (bits, READ(dst))); dst++; } } if (endmask) { - bits = *src; - *dst = FbDoMaskMergeRop(bits, *dst, endmask); + bits = READ(src); + WRITE(dst, FbDoMaskMergeRop(bits, READ(dst), endmask)); } } else { bits = 0; if (srcX > dstX) - bits = *src++; + bits = READ(src++); if (startmask) { bits1 = FbScrLeft(bits, leftShift); - bits = *src++; + bits = READ(src++); bits1 |= FbScrRight(bits, rightShift); - *dst = FbDoMaskMergeRop (bits1, *dst, startmask); + WRITE(dst, FbDoMaskMergeRop (bits1, READ(dst), startmask)); dst++; } n = nmiddle; @@ -755,9 +755,9 @@ fbBltOdd (FbBits *srcLine, while (n--) { bits1 = FbScrLeft(bits, leftShift); - bits = *src++; + bits = READ(src++); bits1 |= FbScrRight(bits, rightShift); - *dst = FbDoDestInvarientMergeRop(bits1); + WRITE(dst, FbDoDestInvarientMergeRop(bits1)); dst++; } } @@ -766,9 +766,9 @@ fbBltOdd (FbBits *srcLine, while (n--) { bits1 = FbScrLeft(bits, leftShift); - bits = *src++; + bits = READ(src++); bits1 |= FbScrRight(bits, rightShift); - *dst = FbDoMergeRop(bits1, *dst); + WRITE(dst, FbDoMergeRop(bits1, READ(dst))); dst++; } } @@ -777,10 +777,10 @@ fbBltOdd (FbBits *srcLine, bits1 = FbScrLeft(bits, leftShift); if (FbScrLeft(endmask, rightShift)) { - bits = *src; + bits = READ(src); bits1 |= FbScrRight(bits, rightShift); } - *dst = FbDoMaskMergeRop (bits1, *dst, endmask); + WRITE(dst, FbDoMaskMergeRop (bits1, READ(dst), endmask)); } } } diff --git a/fb/fbbltone.c b/fb/fbbltone.c index f06357a37..d2c180fef 100644 --- a/fb/fbbltone.c +++ b/fb/fbbltone.c @@ -51,12 +51,12 @@ #define LoadBits {\ if (leftShift) { \ - bitsRight = (src < srcEnd ? *src++ : 0); \ + bitsRight = (src < srcEnd ? READ(src++) : 0); \ bits = (FbStipLeft (bitsLeft, leftShift) | \ FbStipRight(bitsRight, rightShift)); \ bitsLeft = bitsRight; \ } else \ - bits = (src < srcEnd ? *src++ : 0); \ + bits = (src < srcEnd ? READ(src++) : 0); \ } #ifndef FBNOPIXADDR @@ -285,7 +285,7 @@ fbBltOne (FbStip *src, bitsLeft = 0; if (srcX > dstS) - bitsLeft = *src++; + bitsLeft = READ(src++); if (n) { /* @@ -338,7 +338,7 @@ fbBltOne (FbStip *src, else #endif mask = fbBits[FbLeftStipBits(bits,pixelsPerDst)]; - *dst = FbOpaqueStipple (mask, fgxor, bgxor); + WRITE(dst, FbOpaqueStipple (mask, fgxor, bgxor)); dst++; bits = FbStipLeft(bits, pixelsPerDst); } @@ -368,8 +368,8 @@ fbBltOne (FbStip *src, if (left || !transparent) { mask = fbBits[left]; - *dst = FbStippleRRop (*dst, mask, - fgand, fgxor, bgand, bgxor); + WRITE(dst, FbStippleRRop (READ(dst), mask, + fgand, fgxor, bgand, bgxor)); } dst++; bits = FbStipLeft(bits, pixelsPerDst); @@ -537,7 +537,7 @@ const FbBits fbStipple24Bits[3][1 << FbStip24Len] = { stip = FbLeftStipBits(bits, len); \ } else { \ stip = FbLeftStipBits(bits, remain); \ - bits = (src < srcEnd ? *src++ : 0); \ + bits = (src < srcEnd ? READ(src++) : 0); \ __len = (len) - remain; \ stip = FbMergePartStip24Bits(stip, FbLeftStipBits(bits, __len), \ remain, __len); \ @@ -548,7 +548,7 @@ const FbBits fbStipple24Bits[3][1 << FbStip24Len] = { } #define fbInitStipBits(offset,len,stip) {\ - bits = FbStipLeft (*src++,offset); \ + bits = FbStipLeft (READ(src++),offset); \ remain = FB_STIP_UNIT - offset; \ fbFirstStipBits(len,stip); \ stip = FbMergeStip24Bits (0, stip, len); \ @@ -631,10 +631,11 @@ fbBltOne24 (FbStip *srcLine, if (leftMask) { mask = fbStipple24Bits[rot >> 3][stip]; - *dst = (*dst & ~leftMask) | (FbOpaqueStipple (mask, - FbRot24(fgxor, rot), - FbRot24(bgxor, rot)) - & leftMask); + WRITE(dst, (READ(dst) & ~leftMask) | + (FbOpaqueStipple (mask, + FbRot24(fgxor, rot), + FbRot24(bgxor, rot)) + & leftMask)); dst++; fbNextStipBits(rot,stip); } @@ -642,19 +643,20 @@ fbBltOne24 (FbStip *srcLine, while (nl--) { mask = fbStipple24Bits[rot>>3][stip]; - *dst = FbOpaqueStipple (mask, - FbRot24(fgxor, rot), - FbRot24(bgxor, rot)); + WRITE(dst, FbOpaqueStipple (mask, + FbRot24(fgxor, rot), + FbRot24(bgxor, rot))); dst++; fbNextStipBits(rot,stip); } if (rightMask) { mask = fbStipple24Bits[rot >> 3][stip]; - *dst = (*dst & ~rightMask) | (FbOpaqueStipple (mask, - FbRot24(fgxor, rot), - FbRot24(bgxor, rot)) - & rightMask); + WRITE(dst, (READ(dst) & ~rightMask) | + (FbOpaqueStipple (mask, + FbRot24(fgxor, rot), + FbRot24(bgxor, rot)) + & rightMask)); } dst += dstStride; src += srcStride; @@ -674,7 +676,7 @@ fbBltOne24 (FbStip *srcLine, if (stip) { mask = fbStipple24Bits[rot >> 3][stip] & leftMask; - *dst = (*dst & ~mask) | (FbRot24(fgxor, rot) & mask); + WRITE(dst, (READ(dst) & ~mask) | (FbRot24(fgxor, rot) & mask)); } dst++; fbNextStipBits (rot, stip); @@ -685,7 +687,7 @@ fbBltOne24 (FbStip *srcLine, if (stip) { mask = fbStipple24Bits[rot>>3][stip]; - *dst = (*dst & ~mask) | (FbRot24(fgxor,rot) & mask); + WRITE(dst, (READ(dst) & ~mask) | (FbRot24(fgxor,rot) & mask)); } dst++; fbNextStipBits (rot, stip); @@ -695,7 +697,7 @@ fbBltOne24 (FbStip *srcLine, if (stip) { mask = fbStipple24Bits[rot >> 3][stip] & rightMask; - *dst = (*dst & ~mask) | (FbRot24(fgxor, rot) & mask); + WRITE(dst, (READ(dst) & ~mask) | (FbRot24(fgxor, rot) & mask)); } } dst += dstStride; @@ -712,12 +714,12 @@ fbBltOne24 (FbStip *srcLine, if (leftMask) { mask = fbStipple24Bits[rot >> 3][stip]; - *dst = FbStippleRRopMask (*dst, mask, - FbRot24(fgand, rot), - FbRot24(fgxor, rot), - FbRot24(bgand, rot), - FbRot24(bgxor, rot), - leftMask); + WRITE(dst, FbStippleRRopMask (READ(dst), mask, + FbRot24(fgand, rot), + FbRot24(fgxor, rot), + FbRot24(bgand, rot), + FbRot24(bgxor, rot), + leftMask)); dst++; fbNextStipBits(rot,stip); } @@ -725,23 +727,23 @@ fbBltOne24 (FbStip *srcLine, while (nl--) { mask = fbStipple24Bits[rot >> 3][stip]; - *dst = FbStippleRRop (*dst, mask, - FbRot24(fgand, rot), - FbRot24(fgxor, rot), - FbRot24(bgand, rot), - FbRot24(bgxor, rot)); + WRITE(dst, FbStippleRRop (READ(dst), mask, + FbRot24(fgand, rot), + FbRot24(fgxor, rot), + FbRot24(bgand, rot), + FbRot24(bgxor, rot))); dst++; fbNextStipBits(rot,stip); } if (rightMask) { mask = fbStipple24Bits[rot >> 3][stip]; - *dst = FbStippleRRopMask (*dst, mask, - FbRot24(fgand, rot), - FbRot24(fgxor, rot), - FbRot24(bgand, rot), - FbRot24(bgxor, rot), - rightMask); + WRITE(dst, FbStippleRRopMask (READ(dst), mask, + FbRot24(fgand, rot), + FbRot24(fgxor, rot), + FbRot24(bgand, rot), + FbRot24(bgxor, rot), + rightMask)); } dst += dstStride; } @@ -832,7 +834,7 @@ fbBltPlane (FbBits *src, if (srcBpp == 24) srcMask0 = FbRot24(pm,rot0) & FbBitsMask(0, srcBpp); #endif - srcBits = *s++; + srcBits = READ(s++); dstMask = dstMaskFirst; dstUnion = 0; @@ -844,7 +846,7 @@ fbBltPlane (FbBits *src, { if (!srcMask) { - srcBits = *s++; + srcBits = READ(s++); #ifdef FB_24BIT if (srcBpp == 24) srcMask0 = FbNext24Pix(srcMask0) & FbBitsMask(0,24); @@ -853,9 +855,9 @@ fbBltPlane (FbBits *src, } if (!dstMask) { - *d = FbStippleRRopMask(*d, dstBits, - fgand, fgxor, bgand, bgxor, - dstUnion); + WRITE(d, FbStippleRRopMask(READ(d), dstBits, + fgand, fgxor, bgand, bgxor, + dstUnion)); d++; dstMask = FbStipMask(0,1); dstUnion = 0; @@ -871,9 +873,9 @@ fbBltPlane (FbBits *src, dstMask = FbStipRight(dstMask,1); } if (dstUnion) - *d = FbStippleRRopMask(*d,dstBits, - fgand, fgxor, bgand, bgxor, - dstUnion); + WRITE(d, FbStippleRRopMask(READ(d),dstBits, + fgand, fgxor, bgand, bgxor, + dstUnion)); } } diff --git a/fb/fbcompose.c b/fb/fbcompose.c index b1903e90b..6ea948307 100644 --- a/fb/fbcompose.c +++ b/fb/fbcompose.c @@ -53,7 +53,7 @@ typedef FASTCALL void (*fetchProc)(const FbBits *bits, int x, int width, CARD32 static FASTCALL void fbFetch_a8r8g8b8 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexedPtr indexed) { - memcpy(buffer, (const CARD32 *)bits + x, width*sizeof(CARD32)); + MEMCPY_WRAPPED(buffer, (const CARD32 *)bits + x, width*sizeof(CARD32)); } static FASTCALL void @@ -62,7 +62,7 @@ fbFetch_x8r8g8b8 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexe const CARD32 *pixel = (const CARD32 *)bits + x; const CARD32 *end = pixel + width; while (pixel < end) { - *buffer++ = *pixel++ | 0xff000000; + WRITE(buffer++, READ(pixel++) | 0xff000000); } } @@ -72,9 +72,9 @@ fbFetch_a8b8g8r8 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexe const CARD32 *pixel = (CARD32 *)bits + x; const CARD32 *end = pixel + width; while (pixel < end) { - *buffer++ = ((*pixel & 0xff00ff00) | - ((*pixel >> 16) & 0xff) | - ((*pixel & 0xff) << 16)); + WRITE(buffer++, ((READ(pixel) & 0xff00ff00) | + ((READ(pixel) >> 16) & 0xff) | + ((READ(pixel) & 0xff) << 16))); ++pixel; } } @@ -85,10 +85,10 @@ fbFetch_x8b8g8r8 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexe const CARD32 *pixel = (CARD32 *)bits + x; const CARD32 *end = pixel + width; while (pixel < end) { - *buffer++ = 0xff000000 | - ((*pixel & 0x0000ff00) | - ((*pixel >> 16) & 0xff) | - ((*pixel & 0xff) << 16)); + WRITE(buffer++, 0xff000000 | + ((READ(pixel) & 0x0000ff00) | + ((READ(pixel) >> 16) & 0xff) | + ((READ(pixel) & 0xff) << 16))); ++pixel; } } @@ -101,7 +101,7 @@ fbFetch_r8g8b8 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexedP while (pixel < end) { CARD32 b = Fetch24(pixel) | 0xff000000; pixel += 3; - *buffer++ = b; + WRITE(buffer++, b); } } @@ -113,13 +113,13 @@ fbFetch_b8g8r8 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexedP while (pixel < end) { CARD32 b = 0xff000000; #if IMAGE_BYTE_ORDER == MSBFirst - b |= (*pixel++); - b |= (*pixel++ << 8); - b |= (*pixel++ << 16); + b |= (READ(pixel++)); + b |= (READ(pixel++) << 8); + b |= (READ(pixel++) << 16); #else - b |= (*pixel++ << 16); - b |= (*pixel++ << 8); - b |= (*pixel++); + b |= (READ(pixel++) << 16); + b |= (READ(pixel++) << 8); + b |= (READ(pixel++)); #endif } } @@ -130,13 +130,13 @@ fbFetch_r5g6b5 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexedP const CARD16 *pixel = (const CARD16 *)bits + x; const CARD16 *end = pixel + width; while (pixel < end) { - CARD32 p = *pixel++; + CARD32 p = READ(pixel++); CARD32 r = (((p) << 3) & 0xf8) | (((p) << 5) & 0xfc00) | (((p) << 8) & 0xf80000); r |= (r >> 5) & 0x70007; r |= (r >> 6) & 0x300; - *buffer++ = 0xff000000 | r; + WRITE(buffer++, 0xff000000 | r); } } @@ -146,13 +146,13 @@ fbFetch_b5g6r5 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexedP const CARD16 *pixel = (const CARD16 *)bits + x; const CARD16 *end = pixel + width; while (pixel < end) { - CARD32 p = *pixel++; + CARD32 p = READ(pixel++); CARD32 r,g,b; b = ((p & 0xf800) | ((p & 0xe000) >> 5)) >> 8; g = ((p & 0x07e0) | ((p & 0x0600) >> 6)) << 5; r = ((p & 0x001c) | ((p & 0x001f) << 5)) << 14; - *buffer++ = (0xff000000 | r | g | b); + WRITE(buffer++, (0xff000000 | r | g | b)); } } @@ -162,14 +162,14 @@ fbFetch_a1r5g5b5 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexe const CARD16 *pixel = (const CARD16 *)bits + x; const CARD16 *end = pixel + width; while (pixel < end) { - CARD32 p = *pixel++; + CARD32 p = READ(pixel++); CARD32 r,g,b, a; a = (CARD32) ((CARD8) (0 - ((p & 0x8000) >> 15))) << 24; r = ((p & 0x7c00) | ((p & 0x7000) >> 5)) << 9; g = ((p & 0x03e0) | ((p & 0x0380) >> 5)) << 6; b = ((p & 0x001c) | ((p & 0x001f) << 5)) >> 2; - *buffer++ = (a | r | g | b); + WRITE(buffer++, (a | r | g | b)); } } @@ -179,13 +179,13 @@ fbFetch_x1r5g5b5 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexe const CARD16 *pixel = (const CARD16 *)bits + x; const CARD16 *end = pixel + width; while (pixel < end) { - CARD32 p = *pixel++; + CARD32 p = READ(pixel++); CARD32 r,g,b; r = ((p & 0x7c00) | ((p & 0x7000) >> 5)) << 9; g = ((p & 0x03e0) | ((p & 0x0380) >> 5)) << 6; b = ((p & 0x001c) | ((p & 0x001f) << 5)) >> 2; - *buffer++ = (0xff000000 | r | g | b); + WRITE(buffer++, (0xff000000 | r | g | b)); } } @@ -195,14 +195,14 @@ fbFetch_a1b5g5r5 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexe const CARD16 *pixel = (const CARD16 *)bits + x; const CARD16 *end = pixel + width; while (pixel < end) { - CARD32 p = *pixel++; + CARD32 p = READ(pixel++); CARD32 r,g,b, a; a = (CARD32) ((CARD8) (0 - ((p & 0x8000) >> 15))) << 24; b = ((p & 0x7c00) | ((p & 0x7000) >> 5)) >> 7; g = ((p & 0x03e0) | ((p & 0x0380) >> 5)) << 6; r = ((p & 0x001c) | ((p & 0x001f) << 5)) << 14; - *buffer++ = (a | r | g | b); + WRITE(buffer++, (a | r | g | b)); } } @@ -212,13 +212,13 @@ fbFetch_x1b5g5r5 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexe const CARD16 *pixel = (const CARD16 *)bits + x; const CARD16 *end = pixel + width; while (pixel < end) { - CARD32 p = *pixel++; + CARD32 p = READ(pixel++); CARD32 r,g,b; b = ((p & 0x7c00) | ((p & 0x7000) >> 5)) >> 7; g = ((p & 0x03e0) | ((p & 0x0380) >> 5)) << 6; r = ((p & 0x001c) | ((p & 0x001f) << 5)) << 14; - *buffer++ = (0xff000000 | r | g | b); + WRITE(buffer++, (0xff000000 | r | g | b)); } } @@ -228,14 +228,14 @@ fbFetch_a4r4g4b4 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexe const CARD16 *pixel = (const CARD16 *)bits + x; const CARD16 *end = pixel + width; while (pixel < end) { - CARD32 p = *pixel++; + CARD32 p = READ(pixel++); CARD32 r,g,b, a; a = ((p & 0xf000) | ((p & 0xf000) >> 4)) << 16; r = ((p & 0x0f00) | ((p & 0x0f00) >> 4)) << 12; g = ((p & 0x00f0) | ((p & 0x00f0) >> 4)) << 8; b = ((p & 0x000f) | ((p & 0x000f) << 4)); - *buffer++ = (a | r | g | b); + WRITE(buffer++, (a | r | g | b)); } } @@ -245,13 +245,13 @@ fbFetch_x4r4g4b4 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexe const CARD16 *pixel = (const CARD16 *)bits + x; const CARD16 *end = pixel + width; while (pixel < end) { - CARD32 p = *pixel++; + CARD32 p = READ(pixel++); CARD32 r,g,b; r = ((p & 0x0f00) | ((p & 0x0f00) >> 4)) << 12; g = ((p & 0x00f0) | ((p & 0x00f0) >> 4)) << 8; b = ((p & 0x000f) | ((p & 0x000f) << 4)); - *buffer++ = (0xff000000 | r | g | b); + WRITE(buffer++, (0xff000000 | r | g | b)); } } @@ -261,14 +261,14 @@ fbFetch_a4b4g4r4 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexe const CARD16 *pixel = (const CARD16 *)bits + x; const CARD16 *end = pixel + width; while (pixel < end) { - CARD32 p = *pixel++; + CARD32 p = READ(pixel++); CARD32 r,g,b, a; a = ((p & 0xf000) | ((p & 0xf000) >> 4)) << 16; b = ((p & 0x0f00) | ((p & 0x0f00) >> 4)) >> 4; g = ((p & 0x00f0) | ((p & 0x00f0) >> 4)) << 8; r = ((p & 0x000f) | ((p & 0x000f) << 4)) << 16; - *buffer++ = (a | r | g | b); + WRITE(buffer++, (a | r | g | b)); } } @@ -278,13 +278,13 @@ fbFetch_x4b4g4r4 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexe const CARD16 *pixel = (const CARD16 *)bits + x; const CARD16 *end = pixel + width; while (pixel < end) { - CARD32 p = *pixel++; + CARD32 p = READ(pixel++); CARD32 r,g,b; b = ((p & 0x0f00) | ((p & 0x0f00) >> 4)) >> 4; g = ((p & 0x00f0) | ((p & 0x00f0) >> 4)) << 8; r = ((p & 0x000f) | ((p & 0x000f) << 4)) << 16; - *buffer++ = (0xff000000 | r | g | b); + WRITE(buffer++, (0xff000000 | r | g | b)); } } @@ -294,7 +294,7 @@ fbFetch_a8 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexedPtr i const CARD8 *pixel = (const CARD8 *)bits + x; const CARD8 *end = pixel + width; while (pixel < end) { - *buffer++ = (*pixel++) << 24; + WRITE(buffer++, READ(pixel++) << 24); } } @@ -304,7 +304,7 @@ fbFetch_r3g3b2 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexedP const CARD8 *pixel = (const CARD8 *)bits + x; const CARD8 *end = pixel + width; while (pixel < end) { - CARD32 p = *pixel++; + CARD32 p = READ(pixel++); CARD32 r,g,b; r = ((p & 0xe0) | ((p & 0xe0) >> 3) | ((p & 0xc0) >> 6)) << 16; @@ -313,7 +313,7 @@ fbFetch_r3g3b2 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexedP ((p & 0x03) << 2) | ((p & 0x03) << 4) | ((p & 0x03) << 6)); - *buffer++ = (0xff000000 | r | g | b); + WRITE(buffer++, (0xff000000 | r | g | b)); } } @@ -323,7 +323,7 @@ fbFetch_b2g3r3 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexedP const CARD8 *pixel = (const CARD8 *)bits + x; const CARD8 *end = pixel + width; while (pixel < end) { - CARD32 p = *pixel++; + CARD32 p = READ(pixel++); CARD32 r,g,b; b = (((p & 0xc0) ) | @@ -334,7 +334,7 @@ fbFetch_b2g3r3 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexedP r = (((p & 0x07) ) | ((p & 0x07) << 3) | ((p & 0x06) << 6)) << 16; - *buffer++ = (0xff000000 | r | g | b); + WRITE(buffer++, (0xff000000 | r | g | b)); } } @@ -344,14 +344,14 @@ fbFetch_a2r2g2b2 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexe const CARD8 *pixel = (const CARD8 *)bits + x; const CARD8 *end = pixel + width; while (pixel < end) { - CARD32 p = *pixel++; + CARD32 p = READ(pixel++); CARD32 a,r,g,b; a = ((p & 0xc0) * 0x55) << 18; r = ((p & 0x30) * 0x55) << 12; g = ((p & 0x0c) * 0x55) << 6; b = ((p & 0x03) * 0x55); - *buffer++ = a|r|g|b; + WRITE(buffer++, a|r|g|b); } } @@ -361,14 +361,14 @@ fbFetch_a2b2g2r2 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexe const CARD8 *pixel = (const CARD8 *)bits + x; const CARD8 *end = pixel + width; while (pixel < end) { - CARD32 p = *pixel++; + CARD32 p = READ(pixel++); CARD32 a,r,g,b; a = ((p & 0xc0) * 0x55) << 18; b = ((p & 0x30) * 0x55) >> 6; g = ((p & 0x0c) * 0x55) << 6; r = ((p & 0x03) * 0x55) << 16; - *buffer++ = a|r|g|b; + WRITE(buffer++, a|r|g|b); } } @@ -378,8 +378,8 @@ fbFetch_c8 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexedPtr i const CARD8 *pixel = (const CARD8 *)bits + x; const CARD8 *end = pixel + width; while (pixel < end) { - CARD32 p = *pixel++; - *buffer++ = indexed->rgba[p]; + CARD32 p = READ(pixel++); + WRITE(buffer++, indexed->rgba[p]); } } @@ -389,8 +389,8 @@ fbFetch_x4a4 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexedPtr const CARD8 *pixel = (const CARD8 *)bits + x; const CARD8 *end = pixel + width; while (pixel < end) { - CARD8 p = (*pixel++) & 0xf; - *buffer++ = (p | (p << 4)) << 24; + CARD8 p = READ(pixel++) & 0xf; + WRITE(buffer++, (p | (p << 4)) << 24); } } @@ -409,7 +409,7 @@ fbFetch_a4 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexedPtr i CARD32 p = Fetch4(bits, i + x); p |= p << 4; - *buffer++ = p << 24; + WRITE(buffer++, p << 24); } } @@ -424,7 +424,7 @@ fbFetch_r1g2b1 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexedP r = ((p & 0x8) * 0xff) << 13; g = ((p & 0x6) * 0x55) << 7; b = ((p & 0x1) * 0xff); - *buffer++ = 0xff000000|r|g|b; + WRITE(buffer++, 0xff000000|r|g|b); } } @@ -439,7 +439,7 @@ fbFetch_b1g2r1 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexedP b = ((p & 0x8) * 0xff) >> 3; g = ((p & 0x6) * 0x55) << 7; r = ((p & 0x1) * 0xff) << 16; - *buffer++ = 0xff000000|r|g|b; + WRITE(buffer++, 0xff000000|r|g|b); } } @@ -455,7 +455,7 @@ fbFetch_a1r1g1b1 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexe r = ((p & 0x4) * 0xff) << 14; g = ((p & 0x2) * 0xff) << 7; b = ((p & 0x1) * 0xff); - *buffer++ = a|r|g|b; + WRITE(buffer++, a|r|g|b); } } @@ -471,7 +471,7 @@ fbFetch_a1b1g1r1 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexe r = ((p & 0x4) * 0xff) >> 3; g = ((p & 0x2) * 0xff) << 7; b = ((p & 0x1) * 0xff) << 16; - *buffer++ = a|r|g|b; + WRITE(buffer++, a|r|g|b); } } @@ -482,7 +482,7 @@ fbFetch_c4 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexedPtr i for (i = 0; i < width; ++i) { CARD32 p = Fetch4(bits, i + x); - *buffer++ = indexed->rgba[p]; + WRITE(buffer++, indexed->rgba[p]); } } @@ -503,7 +503,7 @@ fbFetch_a1 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexedPtr i a |= a << 1; a |= a << 2; a |= a << 4; - *buffer++ = a << 24; + WRITE(buffer++, a << 24); } } @@ -520,7 +520,7 @@ fbFetch_g1 (const FbBits *bits, int x, int width, CARD32 *buffer, miIndexedPtr i a = p >> ((i+x) & 0x1f); #endif a = a & 1; - *buffer++ = indexed->rgba[a]; + WRITE(buffer++, indexed->rgba[a]); } } @@ -585,19 +585,19 @@ typedef FASTCALL CARD32 (*fetchPixelProc)(const FbBits *bits, int offset, miInde static FASTCALL CARD32 fbFetchPixel_a8r8g8b8 (const FbBits *bits, int offset, miIndexedPtr indexed) { - return ((CARD32 *)bits)[offset]; + return READ((CARD32 *)bits + offset); } static FASTCALL CARD32 fbFetchPixel_x8r8g8b8 (const FbBits *bits, int offset, miIndexedPtr indexed) { - return ((CARD32 *)bits)[offset] | 0xff000000; + return READ((CARD32 *)bits + offset) | 0xff000000; } static FASTCALL CARD32 fbFetchPixel_a8b8g8r8 (const FbBits *bits, int offset, miIndexedPtr indexed) { - CARD32 pixel = ((CARD32 *)bits)[offset]; + CARD32 pixel = READ((CARD32 *)bits + offset); return ((pixel & 0xff000000) | ((pixel >> 16) & 0xff) | @@ -608,7 +608,7 @@ fbFetchPixel_a8b8g8r8 (const FbBits *bits, int offset, miIndexedPtr indexed) static FASTCALL CARD32 fbFetchPixel_x8b8g8r8 (const FbBits *bits, int offset, miIndexedPtr indexed) { - CARD32 pixel = ((CARD32 *)bits)[offset]; + CARD32 pixel = READ((CARD32 *)bits + offset); return ((0xff000000) | ((pixel >> 16) & 0xff) | @@ -622,14 +622,14 @@ fbFetchPixel_r8g8b8 (const FbBits *bits, int offset, miIndexedPtr indexed) CARD8 *pixel = ((CARD8 *) bits) + (offset*3); #if IMAGE_BYTE_ORDER == MSBFirst return (0xff000000 | - (pixel[0] << 16) | - (pixel[1] << 8) | - (pixel[2])); + (READ(pixel + 0) << 16) | + (READ(pixel + 1) << 8) | + (READ(pixel + 2))); #else return (0xff000000 | - (pixel[2] << 16) | - (pixel[1] << 8) | - (pixel[0])); + (READ(pixel + 2) << 16) | + (READ(pixel + 1) << 8) | + (READ(pixel + 0))); #endif } @@ -639,21 +639,21 @@ fbFetchPixel_b8g8r8 (const FbBits *bits, int offset, miIndexedPtr indexed) CARD8 *pixel = ((CARD8 *) bits) + (offset*3); #if IMAGE_BYTE_ORDER == MSBFirst return (0xff000000 | - (pixel[2] << 16) | - (pixel[1] << 8) | - (pixel[0])); + (READ(pixel + 2) << 16) | + (READ(pixel + 1) << 8) | + (READ(pixel + 0))); #else return (0xff000000 | - (pixel[0] << 16) | - (pixel[1] << 8) | - (pixel[2])); + (READ(pixel + 0) << 16) | + (READ(pixel + 1) << 8) | + (READ(pixel + 2))); #endif } static FASTCALL CARD32 fbFetchPixel_r5g6b5 (const FbBits *bits, int offset, miIndexedPtr indexed) { - CARD32 pixel = ((CARD16 *) bits)[offset]; + CARD32 pixel = READ((CARD16 *) bits + offset); CARD32 r,g,b; r = ((pixel & 0xf800) | ((pixel & 0xe000) >> 5)) << 8; @@ -665,7 +665,7 @@ fbFetchPixel_r5g6b5 (const FbBits *bits, int offset, miIndexedPtr indexed) static FASTCALL CARD32 fbFetchPixel_b5g6r5 (const FbBits *bits, int offset, miIndexedPtr indexed) { - CARD32 pixel = ((CARD16 *) bits)[offset]; + CARD32 pixel = READ((CARD16 *) bits + offset); CARD32 r,g,b; b = ((pixel & 0xf800) | ((pixel & 0xe000) >> 5)) >> 8; @@ -677,7 +677,7 @@ fbFetchPixel_b5g6r5 (const FbBits *bits, int offset, miIndexedPtr indexed) static FASTCALL CARD32 fbFetchPixel_a1r5g5b5 (const FbBits *bits, int offset, miIndexedPtr indexed) { - CARD32 pixel = ((CARD16 *) bits)[offset]; + CARD32 pixel = READ((CARD16 *) bits + offset); CARD32 a,r,g,b; a = (CARD32) ((CARD8) (0 - ((pixel & 0x8000) >> 15))) << 24; @@ -690,7 +690,7 @@ fbFetchPixel_a1r5g5b5 (const FbBits *bits, int offset, miIndexedPtr indexed) static FASTCALL CARD32 fbFetchPixel_x1r5g5b5 (const FbBits *bits, int offset, miIndexedPtr indexed) { - CARD32 pixel = ((CARD16 *) bits)[offset]; + CARD32 pixel = READ((CARD16 *) bits + offset); CARD32 r,g,b; r = ((pixel & 0x7c00) | ((pixel & 0x7000) >> 5)) << 9; @@ -702,7 +702,7 @@ fbFetchPixel_x1r5g5b5 (const FbBits *bits, int offset, miIndexedPtr indexed) static FASTCALL CARD32 fbFetchPixel_a1b5g5r5 (const FbBits *bits, int offset, miIndexedPtr indexed) { - CARD32 pixel = ((CARD16 *) bits)[offset]; + CARD32 pixel = READ((CARD16 *) bits + offset); CARD32 a,r,g,b; a = (CARD32) ((CARD8) (0 - ((pixel & 0x8000) >> 15))) << 24; @@ -715,7 +715,7 @@ fbFetchPixel_a1b5g5r5 (const FbBits *bits, int offset, miIndexedPtr indexed) static FASTCALL CARD32 fbFetchPixel_x1b5g5r5 (const FbBits *bits, int offset, miIndexedPtr indexed) { - CARD32 pixel = ((CARD16 *) bits)[offset]; + CARD32 pixel = READ((CARD16 *) bits + offset); CARD32 r,g,b; b = ((pixel & 0x7c00) | ((pixel & 0x7000) >> 5)) >> 7; @@ -727,7 +727,7 @@ fbFetchPixel_x1b5g5r5 (const FbBits *bits, int offset, miIndexedPtr indexed) static FASTCALL CARD32 fbFetchPixel_a4r4g4b4 (const FbBits *bits, int offset, miIndexedPtr indexed) { - CARD32 pixel = ((CARD16 *) bits)[offset]; + CARD32 pixel = READ((CARD16 *) bits + offset); CARD32 a,r,g,b; a = ((pixel & 0xf000) | ((pixel & 0xf000) >> 4)) << 16; @@ -740,7 +740,7 @@ fbFetchPixel_a4r4g4b4 (const FbBits *bits, int offset, miIndexedPtr indexed) static FASTCALL CARD32 fbFetchPixel_x4r4g4b4 (const FbBits *bits, int offset, miIndexedPtr indexed) { - CARD32 pixel = ((CARD16 *) bits)[offset]; + CARD32 pixel = READ((CARD16 *) bits + offset); CARD32 r,g,b; r = ((pixel & 0x0f00) | ((pixel & 0x0f00) >> 4)) << 12; @@ -752,7 +752,7 @@ fbFetchPixel_x4r4g4b4 (const FbBits *bits, int offset, miIndexedPtr indexed) static FASTCALL CARD32 fbFetchPixel_a4b4g4r4 (const FbBits *bits, int offset, miIndexedPtr indexed) { - CARD32 pixel = ((CARD16 *) bits)[offset]; + CARD32 pixel = READ((CARD16 *) bits + offset); CARD32 a,r,g,b; a = ((pixel & 0xf000) | ((pixel & 0xf000) >> 4)) << 16; @@ -765,7 +765,7 @@ fbFetchPixel_a4b4g4r4 (const FbBits *bits, int offset, miIndexedPtr indexed) static FASTCALL CARD32 fbFetchPixel_x4b4g4r4 (const FbBits *bits, int offset, miIndexedPtr indexed) { - CARD32 pixel = ((CARD16 *) bits)[offset]; + CARD32 pixel = READ((CARD16 *) bits + offset); CARD32 r,g,b; b = ((pixel & 0x0f00) | ((pixel & 0x0f00) >> 4)) >> 4; @@ -777,7 +777,7 @@ fbFetchPixel_x4b4g4r4 (const FbBits *bits, int offset, miIndexedPtr indexed) static FASTCALL CARD32 fbFetchPixel_a8 (const FbBits *bits, int offset, miIndexedPtr indexed) { - CARD32 pixel = ((CARD8 *) bits)[offset]; + CARD32 pixel = READ((CARD8 *) bits + offset); return pixel << 24; } @@ -785,7 +785,7 @@ fbFetchPixel_a8 (const FbBits *bits, int offset, miIndexedPtr indexed) static FASTCALL CARD32 fbFetchPixel_r3g3b2 (const FbBits *bits, int offset, miIndexedPtr indexed) { - CARD32 pixel = ((CARD8 *) bits)[offset]; + CARD32 pixel = READ((CARD8 *) bits + offset); CARD32 r,g,b; r = ((pixel & 0xe0) | ((pixel & 0xe0) >> 3) | ((pixel & 0xc0) >> 6)) << 16; @@ -800,7 +800,7 @@ fbFetchPixel_r3g3b2 (const FbBits *bits, int offset, miIndexedPtr indexed) static FASTCALL CARD32 fbFetchPixel_b2g3r3 (const FbBits *bits, int offset, miIndexedPtr indexed) { - CARD32 pixel = ((CARD8 *) bits)[offset]; + CARD32 pixel = READ((CARD8 *) bits + offset); CARD32 r,g,b; b = (((pixel & 0xc0) ) | @@ -817,7 +817,7 @@ fbFetchPixel_b2g3r3 (const FbBits *bits, int offset, miIndexedPtr indexed) static FASTCALL CARD32 fbFetchPixel_a2r2g2b2 (const FbBits *bits, int offset, miIndexedPtr indexed) { - CARD32 pixel = ((CARD8 *) bits)[offset]; + CARD32 pixel = READ((CARD8 *) bits + offset); CARD32 a,r,g,b; a = ((pixel & 0xc0) * 0x55) << 18; @@ -830,7 +830,7 @@ fbFetchPixel_a2r2g2b2 (const FbBits *bits, int offset, miIndexedPtr indexed) static FASTCALL CARD32 fbFetchPixel_a2b2g2r2 (const FbBits *bits, int offset, miIndexedPtr indexed) { - CARD32 pixel = ((CARD8 *) bits)[offset]; + CARD32 pixel = READ((CARD8 *) bits + offset); CARD32 a,r,g,b; a = ((pixel & 0xc0) * 0x55) << 18; @@ -843,14 +843,14 @@ fbFetchPixel_a2b2g2r2 (const FbBits *bits, int offset, miIndexedPtr indexed) static FASTCALL CARD32 fbFetchPixel_c8 (const FbBits *bits, int offset, miIndexedPtr indexed) { - CARD32 pixel = ((CARD8 *) bits)[offset]; + CARD32 pixel = READ((CARD8 *) bits + offset); return indexed->rgba[pixel]; } static FASTCALL CARD32 fbFetchPixel_x4a4 (const FbBits *bits, int offset, miIndexedPtr indexed) { - CARD32 pixel = ((CARD8 *) bits)[offset]; + CARD32 pixel = READ((CARD8 *) bits + offset); return ((pixel & 0xf) | ((pixel & 0xf) << 4)) << 24; } @@ -1027,7 +1027,7 @@ typedef FASTCALL void (*storeProc) (FbBits *bits, const CARD32 *values, int x, i static FASTCALL void fbStore_a8r8g8b8 (FbBits *bits, const CARD32 *values, int x, int width, miIndexedPtr indexed) { - memcpy(((CARD32 *)bits) + x, values, width*sizeof(CARD32)); + MEMCPY_WRAPPED(((CARD32 *)bits) + x, values, width*sizeof(CARD32)); } static FASTCALL void @@ -1036,7 +1036,7 @@ fbStore_x8r8g8b8 (FbBits *bits, const CARD32 *values, int x, int width, miIndexe int i; CARD32 *pixel = (CARD32 *)bits + x; for (i = 0; i < width; ++i) - *pixel++ = values[i] & 0xffffff; + WRITE(pixel++, READ(values + i) & 0xffffff); } static FASTCALL void @@ -1045,7 +1045,7 @@ fbStore_a8b8g8r8 (FbBits *bits, const CARD32 *values, int x, int width, miIndexe int i; CARD32 *pixel = (CARD32 *)bits + x; for (i = 0; i < width; ++i) - *pixel++ = (values[i] & 0xff00ff00) | ((values[i] >> 16) & 0xff) | ((values[i] & 0xff) << 16); + WRITE(pixel++, (READ(values + i) & 0xff00ff00) | ((READ(values + i) >> 16) & 0xff) | ((READ(values + i) & 0xff) << 16)); } static FASTCALL void @@ -1054,7 +1054,7 @@ fbStore_x8b8g8r8 (FbBits *bits, const CARD32 *values, int x, int width, miIndexe int i; CARD32 *pixel = (CARD32 *)bits + x; for (i = 0; i < width; ++i) - *pixel++ = (values[i] & 0x0000ff00) | ((values[i] >> 16) & 0xff) | ((values[i] & 0xff) << 16); + WRITE(pixel++, (READ(values + i) & 0x0000ff00) | ((READ(values + i) >> 16) & 0xff) | ((READ(values + i) & 0xff) << 16)); } static FASTCALL void @@ -1063,7 +1063,7 @@ fbStore_r8g8b8 (FbBits *bits, const CARD32 *values, int x, int width, miIndexedP int i; CARD8 *pixel = ((CARD8 *) bits) + 3*x; for (i = 0; i < width; ++i) { - Store24(pixel, values[i]); + Store24(pixel, READ(values + i)); pixel += 3; } } @@ -1074,14 +1074,15 @@ fbStore_b8g8r8 (FbBits *bits, const CARD32 *values, int x, int width, miIndexedP int i; CARD8 *pixel = ((CARD8 *) bits) + 3*x; for (i = 0; i < width; ++i) { + CARD32 val = READ(values + i); #if IMAGE_BYTE_ORDER == MSBFirst - *pixel++ = Blue(values[i]); - *pixel++ = Green(values[i]); - *pixel++ = Red(values[i]); + WRITE(pixel++, Blue(val)); + WRITE(pixel++, Green(val)); + WRITE(pixel++, Red(val)); #else - *pixel++ = Red(values[i]); - *pixel++ = Green(values[i]); - *pixel++ = Blue(values[i]); + WRITE(pixel++, Red(val)); + WRITE(pixel++, Green(val)); + WRITE(pixel++, Blue(val)); #endif } } @@ -1092,10 +1093,10 @@ fbStore_r5g6b5 (FbBits *bits, const CARD32 *values, int x, int width, miIndexedP int i; CARD16 *pixel = ((CARD16 *) bits) + x; for (i = 0; i < width; ++i) { - CARD32 s = values[i]; - *pixel++ = ((s >> 3) & 0x001f) | - ((s >> 5) & 0x07e0) | - ((s >> 8) & 0xf800); + CARD32 s = READ(values + i); + WRITE(pixel++, ((s >> 3) & 0x001f) | + ((s >> 5) & 0x07e0) | + ((s >> 8) & 0xf800)); } } @@ -1105,10 +1106,10 @@ fbStore_b5g6r5 (FbBits *bits, const CARD32 *values, int x, int width, miIndexedP int i; CARD16 *pixel = ((CARD16 *) bits) + x; for (i = 0; i < width; ++i) { - Split(values[i]); - *pixel++ = (((b << 8) & 0xf800) | - ((g << 3) & 0x07e0) | - ((r >> 3) )); + Split(READ(values + i)); + WRITE(pixel++, ((b << 8) & 0xf800) | + ((g << 3) & 0x07e0) | + ((r >> 3) )); } } @@ -1118,11 +1119,11 @@ fbStore_a1r5g5b5 (FbBits *bits, const CARD32 *values, int x, int width, miIndexe int i; CARD16 *pixel = ((CARD16 *) bits) + x; for (i = 0; i < width; ++i) { - Splita(values[i]); - *pixel++ = (((a << 8) & 0x8000) | - ((r << 7) & 0x7c00) | - ((g << 2) & 0x03e0) | - ((b >> 3) )); + Splita(READ(values + i)); + WRITE(pixel++, ((a << 8) & 0x8000) | + ((r << 7) & 0x7c00) | + ((g << 2) & 0x03e0) | + ((b >> 3) )); } } @@ -1132,10 +1133,10 @@ fbStore_x1r5g5b5 (FbBits *bits, const CARD32 *values, int x, int width, miIndexe int i; CARD16 *pixel = ((CARD16 *) bits) + x; for (i = 0; i < width; ++i) { - Split(values[i]); - *pixel++ = (((r << 7) & 0x7c00) | - ((g << 2) & 0x03e0) | - ((b >> 3) )); + Split(READ(values + i)); + WRITE(pixel++, ((r << 7) & 0x7c00) | + ((g << 2) & 0x03e0) | + ((b >> 3) )); } } @@ -1145,11 +1146,11 @@ fbStore_a1b5g5r5 (FbBits *bits, const CARD32 *values, int x, int width, miIndexe int i; CARD16 *pixel = ((CARD16 *) bits) + x; for (i = 0; i < width; ++i) { - Splita(values[i]); - *pixel++ = (((a << 8) & 0x8000) | - ((b << 7) & 0x7c00) | - ((g << 2) & 0x03e0) | - ((r >> 3) )); + Splita(READ(values + i)); + WRITE(pixel++, ((a << 8) & 0x8000) | + ((b << 7) & 0x7c00) | + ((g << 2) & 0x03e0) | + ((r >> 3) )); } } @@ -1159,10 +1160,10 @@ fbStore_x1b5g5r5 (FbBits *bits, const CARD32 *values, int x, int width, miIndexe int i; CARD16 *pixel = ((CARD16 *) bits) + x; for (i = 0; i < width; ++i) { - Split(values[i]); - *pixel++ = (((b << 7) & 0x7c00) | - ((g << 2) & 0x03e0) | - ((r >> 3) )); + Split(READ(values + i)); + WRITE(pixel++, ((b << 7) & 0x7c00) | + ((g << 2) & 0x03e0) | + ((r >> 3) )); } } @@ -1172,11 +1173,11 @@ fbStore_a4r4g4b4 (FbBits *bits, const CARD32 *values, int x, int width, miIndexe int i; CARD16 *pixel = ((CARD16 *) bits) + x; for (i = 0; i < width; ++i) { - Splita(values[i]); - *pixel++ = (((a << 8) & 0xf000) | - ((r << 4) & 0x0f00) | - ((g ) & 0x00f0) | - ((b >> 4) )); + Splita(READ(values + i)); + WRITE(pixel++, ((a << 8) & 0xf000) | + ((r << 4) & 0x0f00) | + ((g ) & 0x00f0) | + ((b >> 4) )); } } @@ -1186,10 +1187,10 @@ fbStore_x4r4g4b4 (FbBits *bits, const CARD32 *values, int x, int width, miIndexe int i; CARD16 *pixel = ((CARD16 *) bits) + x; for (i = 0; i < width; ++i) { - Split(values[i]); - *pixel++ = (((r << 4) & 0x0f00) | - ((g ) & 0x00f0) | - ((b >> 4) )); + Split(READ(values + i)); + WRITE(pixel++, ((r << 4) & 0x0f00) | + ((g ) & 0x00f0) | + ((b >> 4) )); } } @@ -1199,11 +1200,11 @@ fbStore_a4b4g4r4 (FbBits *bits, const CARD32 *values, int x, int width, miIndexe int i; CARD16 *pixel = ((CARD16 *) bits) + x; for (i = 0; i < width; ++i) { - Splita(values[i]); - *pixel++ = (((a << 8) & 0xf000) | - ((b << 4) & 0x0f00) | - ((g ) & 0x00f0) | - ((r >> 4) )); + Splita(READ(values + i)); + WRITE(pixel++, ((a << 8) & 0xf000) | + ((b << 4) & 0x0f00) | + ((g ) & 0x00f0) | + ((r >> 4) )); } } @@ -1213,10 +1214,10 @@ fbStore_x4b4g4r4 (FbBits *bits, const CARD32 *values, int x, int width, miIndexe int i; CARD16 *pixel = ((CARD16 *) bits) + x; for (i = 0; i < width; ++i) { - Split(values[i]); - *pixel++ = (((b << 4) & 0x0f00) | - ((g ) & 0x00f0) | - ((r >> 4) )); + Split(READ(values + i)); + WRITE(pixel++, ((b << 4) & 0x0f00) | + ((g ) & 0x00f0) | + ((r >> 4) )); } } @@ -1226,7 +1227,7 @@ fbStore_a8 (FbBits *bits, const CARD32 *values, int x, int width, miIndexedPtr i int i; CARD8 *pixel = ((CARD8 *) bits) + x; for (i = 0; i < width; ++i) { - *pixel++ = values[i] >> 24; + WRITE(pixel++, READ(values + i) >> 24); } } @@ -1236,10 +1237,10 @@ fbStore_r3g3b2 (FbBits *bits, const CARD32 *values, int x, int width, miIndexedP int i; CARD8 *pixel = ((CARD8 *) bits) + x; for (i = 0; i < width; ++i) { - Split(values[i]); - *pixel++ = (((r ) & 0xe0) | - ((g >> 3) & 0x1c) | - ((b >> 6) )); + Split(READ(values + i)); + WRITE(pixel++, ((r ) & 0xe0) | + ((g >> 3) & 0x1c) | + ((b >> 6) )); } } @@ -1249,10 +1250,10 @@ fbStore_b2g3r3 (FbBits *bits, const CARD32 *values, int x, int width, miIndexedP int i; CARD8 *pixel = ((CARD8 *) bits) + x; for (i = 0; i < width; ++i) { - Split(values[i]); - *pixel++ = (((b ) & 0xe0) | - ((g >> 3) & 0x1c) | - ((r >> 6) )); + Split(READ(values + i)); + WRITE(pixel++, ((b ) & 0xe0) | + ((g >> 3) & 0x1c) | + ((r >> 6) )); } } @@ -1262,11 +1263,11 @@ fbStore_a2r2g2b2 (FbBits *bits, const CARD32 *values, int x, int width, miIndexe int i; CARD8 *pixel = ((CARD8 *) bits) + x; for (i = 0; i < width; ++i) { - Splita(values[i]); - *pixel++ = (((a ) & 0xc0) | - ((r >> 2) & 0x30) | - ((g >> 4) & 0x0c) | - ((b >> 6) )); + Splita(READ(values + i)); + WRITE(pixel++, ((a ) & 0xc0) | + ((r >> 2) & 0x30) | + ((g >> 4) & 0x0c) | + ((b >> 6) )); } } @@ -1276,7 +1277,7 @@ fbStore_c8 (FbBits *bits, const CARD32 *values, int x, int width, miIndexedPtr i int i; CARD8 *pixel = ((CARD8 *) bits) + x; for (i = 0; i < width; ++i) { - *pixel++ = miIndexToEnt24(indexed,values[i]); + WRITE(pixel++, miIndexToEnt24(indexed,READ(values + i))); } } @@ -1286,7 +1287,7 @@ fbStore_x4a4 (FbBits *bits, const CARD32 *values, int x, int width, miIndexedPtr int i; CARD8 *pixel = ((CARD8 *) bits) + x; for (i = 0; i < width; ++i) { - *pixel++ = values[i] >> 28; + WRITE(pixel++, READ(values + i) >> 28); } } @@ -1306,7 +1307,7 @@ fbStore_a4 (FbBits *bits, const CARD32 *values, int x, int width, miIndexedPtr i { int i; for (i = 0; i < width; ++i) { - Store4(bits, i + x, values[i]>>28); + Store4(bits, i + x, READ(values + i)>>28); } } @@ -1317,7 +1318,7 @@ fbStore_r1g2b1 (FbBits *bits, const CARD32 *values, int x, int width, miIndexedP for (i = 0; i < width; ++i) { CARD32 pixel; - Split(values[i]); + Split(READ(values + i)); pixel = (((r >> 4) & 0x8) | ((g >> 5) & 0x6) | ((b >> 7) )); @@ -1332,7 +1333,7 @@ fbStore_b1g2r1 (FbBits *bits, const CARD32 *values, int x, int width, miIndexedP for (i = 0; i < width; ++i) { CARD32 pixel; - Split(values[i]); + Split(READ(values + i)); pixel = (((b >> 4) & 0x8) | ((g >> 5) & 0x6) | ((r >> 7) )); @@ -1346,7 +1347,7 @@ fbStore_a1r1g1b1 (FbBits *bits, const CARD32 *values, int x, int width, miIndexe int i; for (i = 0; i < width; ++i) { CARD32 pixel; - Splita(values[i]); + Splita(READ(values + i)); pixel = (((a >> 4) & 0x8) | ((r >> 5) & 0x4) | ((g >> 6) & 0x2) | @@ -1361,7 +1362,7 @@ fbStore_a1b1g1r1 (FbBits *bits, const CARD32 *values, int x, int width, miIndexe int i; for (i = 0; i < width; ++i) { CARD32 pixel; - Splita(values[i]); + Splita(READ(values + i)); pixel = (((a >> 4) & 0x8) | ((b >> 5) & 0x4) | ((g >> 6) & 0x2) | @@ -1377,7 +1378,7 @@ fbStore_c4 (FbBits *bits, const CARD32 *values, int x, int width, miIndexedPtr i for (i = 0; i < width; ++i) { CARD32 pixel; - pixel = miIndexToEnt24(indexed, values[i]); + pixel = miIndexToEnt24(indexed, READ(values + i)); Store4(bits, i + x, pixel); } } @@ -1390,8 +1391,8 @@ fbStore_a1 (FbBits *bits, const CARD32 *values, int x, int width, miIndexedPtr i CARD32 *pixel = ((CARD32 *) bits) + ((i+x) >> 5); CARD32 mask = FbStipMask((i+x) & 0x1f, 1); - CARD32 v = values[i] & 0x80000000 ? mask : 0; - *pixel = (*pixel & ~mask) | v; + CARD32 v = READ(values + i) & 0x80000000 ? mask : 0; + WRITE(pixel, (READ(pixel) & ~mask) | v); } } @@ -1403,8 +1404,8 @@ fbStore_g1 (FbBits *bits, const CARD32 *values, int x, int width, miIndexedPtr i CARD32 *pixel = ((CARD32 *) bits) + ((i+x) >> 5); CARD32 mask = FbStipMask((i+x) & 0x1f, 1); - CARD32 v = miIndexToEntY24(indexed,values[i]) ? mask : 0; - *pixel = (*pixel & ~mask) | v; + CARD32 v = miIndexToEntY24(indexed,READ(values + i)) ? mask : 0; + WRITE(pixel, (READ(pixel) & ~mask) | v); } } @@ -1469,10 +1470,10 @@ fbCombineMaskU (CARD32 *src, const CARD32 *mask, int width) { int i; for (i = 0; i < width; ++i) { - CARD32 a = mask[i] >> 24; - CARD32 s = src[i]; + CARD32 a = READ(mask + i) >> 24; + CARD32 s = READ(src + i); FbByteMul(s, a); - src[i] = s; + WRITE(src + i, s); } } @@ -1483,13 +1484,13 @@ fbCombineMaskU (CARD32 *src, const CARD32 *mask, int width) static FASTCALL void fbCombineClear (CARD32 *dest, const CARD32 *src, int width) { - memset(dest, 0, width*sizeof(CARD32)); + MEMSET_WRAPPED(dest, 0, width*sizeof(CARD32)); } static FASTCALL void fbCombineSrcU (CARD32 *dest, const CARD32 *src, int width) { - memcpy(dest, src, width*sizeof(CARD32)); + MEMCPY_WRAPPED(dest, src, width*sizeof(CARD32)); } @@ -1498,12 +1499,12 @@ fbCombineOverU (CARD32 *dest, const CARD32 *src, int width) { int i; for (i = 0; i < width; ++i) { - CARD32 s = src[i]; - CARD32 d = dest[i]; + CARD32 s = READ(src + i); + CARD32 d = READ(dest + i); CARD32 ia = Alpha(~s); FbByteMulAdd(d, ia, s); - dest[i] = d; + WRITE(dest + i, d); } } @@ -1512,11 +1513,11 @@ fbCombineOverReverseU (CARD32 *dest, const CARD32 *src, int width) { int i; for (i = 0; i < width; ++i) { - CARD32 s = src[i]; - CARD32 d = dest[i]; - CARD32 ia = Alpha(~dest[i]); + CARD32 s = READ(src + i); + CARD32 d = READ(dest + i); + CARD32 ia = Alpha(~READ(dest + i)); FbByteMulAdd(s, ia, d); - dest[i] = s; + WRITE(dest + i, s); } } @@ -1525,10 +1526,10 @@ fbCombineInU (CARD32 *dest, const CARD32 *src, int width) { int i; for (i = 0; i < width; ++i) { - CARD32 s = src[i]; - CARD32 a = Alpha(dest[i]); + CARD32 s = READ(src + i); + CARD32 a = Alpha(READ(dest + i)); FbByteMul(s, a); - dest[i] = s; + WRITE(dest + i, s); } } @@ -1537,10 +1538,10 @@ fbCombineInReverseU (CARD32 *dest, const CARD32 *src, int width) { int i; for (i = 0; i < width; ++i) { - CARD32 d = dest[i]; - CARD32 a = Alpha(src[i]); + CARD32 d = READ(dest + i); + CARD32 a = Alpha(READ(src + i)); FbByteMul(d, a); - dest[i] = d; + WRITE(dest + i, d); } } @@ -1549,10 +1550,10 @@ fbCombineOutU (CARD32 *dest, const CARD32 *src, int width) { int i; for (i = 0; i < width; ++i) { - CARD32 s = src[i]; - CARD32 a = Alpha(~dest[i]); + CARD32 s = READ(src + i); + CARD32 a = Alpha(~READ(dest + i)); FbByteMul(s, a); - dest[i] = s; + WRITE(dest + i, s); } } @@ -1561,10 +1562,10 @@ fbCombineOutReverseU (CARD32 *dest, const CARD32 *src, int width) { int i; for (i = 0; i < width; ++i) { - CARD32 d = dest[i]; - CARD32 a = Alpha(~src[i]); + CARD32 d = READ(dest + i); + CARD32 a = Alpha(~READ(src + i)); FbByteMul(d, a); - dest[i] = d; + WRITE(dest + i, d); } } @@ -1573,13 +1574,13 @@ fbCombineAtopU (CARD32 *dest, const CARD32 *src, int width) { int i; for (i = 0; i < width; ++i) { - CARD32 s = src[i]; - CARD32 d = dest[i]; + CARD32 s = READ(src + i); + CARD32 d = READ(dest + i); CARD32 dest_a = Alpha(d); CARD32 src_ia = Alpha(~s); FbByteAddMul(s, dest_a, d, src_ia); - dest[i] = s; + WRITE(dest + i, s); } } @@ -1588,13 +1589,13 @@ fbCombineAtopReverseU (CARD32 *dest, const CARD32 *src, int width) { int i; for (i = 0; i < width; ++i) { - CARD32 s = src[i]; - CARD32 d = dest[i]; + CARD32 s = READ(src + i); + CARD32 d = READ(dest + i); CARD32 src_a = Alpha(s); CARD32 dest_ia = Alpha(~d); FbByteAddMul(s, dest_ia, d, src_a); - dest[i] = s; + WRITE(dest + i, s); } } @@ -1603,13 +1604,13 @@ fbCombineXorU (CARD32 *dest, const CARD32 *src, int width) { int i; for (i = 0; i < width; ++i) { - CARD32 s = src[i]; - CARD32 d = dest[i]; + CARD32 s = READ(src + i); + CARD32 d = READ(dest + i); CARD32 src_ia = Alpha(~s); CARD32 dest_ia = Alpha(~d); FbByteAddMul(s, dest_ia, d, src_ia); - dest[i] = s; + WRITE(dest + i, s); } } @@ -1618,10 +1619,10 @@ fbCombineAddU (CARD32 *dest, const CARD32 *src, int width) { int i; for (i = 0; i < width; ++i) { - CARD32 s = src[i]; - CARD32 d = dest[i]; + CARD32 s = READ(src + i); + CARD32 d = READ(dest + i); FbByteAdd(d, s); - dest[i] = d; + WRITE(dest + i, d); } } @@ -1630,8 +1631,8 @@ fbCombineSaturateU (CARD32 *dest, const CARD32 *src, int width) { int i; for (i = 0; i < width; ++i) { - CARD32 s = src[i]; - CARD32 d = dest[i]; + CARD32 s = READ(src + i); + CARD32 d = READ(dest + i); CARD16 sa, da; sa = s >> 24; @@ -1642,7 +1643,7 @@ fbCombineSaturateU (CARD32 *dest, const CARD32 *src, int width) FbByteMul(s, sa); } FbByteAdd(d, s); - dest[i] = d; + WRITE(dest + i, d); } } @@ -1716,8 +1717,8 @@ fbCombineDisjointGeneralU (CARD32 *dest, const CARD32 *src, int width, CARD8 com { int i; for (i = 0; i < width; ++i) { - CARD32 s = src[i]; - CARD32 d = dest[i]; + CARD32 s = READ(src + i); + CARD32 d = READ(dest + i); CARD32 m,n,o,p; CARD16 Fa, Fb, t, u, v; CARD8 sa = s >> 24; @@ -1757,7 +1758,7 @@ fbCombineDisjointGeneralU (CARD32 *dest, const CARD32 *src, int width, CARD8 com o = FbGen (s,d,16,Fa,Fb,t, u, v); p = FbGen (s,d,24,Fa,Fb,t, u, v); s = m|n|o|p; - dest[i] = s; + WRITE(dest + i, s); } } @@ -1766,19 +1767,19 @@ fbCombineDisjointOverU (CARD32 *dest, const CARD32 *src, int width) { int i; for (i = 0; i < width; ++i) { - CARD32 s = src[i]; + CARD32 s = READ(src + i); CARD16 a = s >> 24; if (a != 0x00) { if (a != 0xff) { - CARD32 d = dest[i]; + CARD32 d = READ(dest + i); a = fbCombineDisjointOutPart (d >> 24, a); FbByteMulAdd(d, a, s); s = d; } - dest[i] = s; + WRITE(dest + i, s); } } } @@ -1855,8 +1856,8 @@ fbCombineConjointGeneralU (CARD32 *dest, const CARD32 *src, int width, CARD8 com { int i; for (i = 0; i < width; ++i) { - CARD32 s = src[i]; - CARD32 d = dest[i]; + CARD32 s = READ(src + i); + CARD32 d = READ(dest + i); CARD32 m,n,o,p; CARD16 Fa, Fb, t, u, v; CARD8 sa = s >> 24; @@ -1896,7 +1897,7 @@ fbCombineConjointGeneralU (CARD32 *dest, const CARD32 *src, int width, CARD8 com o = FbGen (s,d,16,Fa,Fb,t, u, v); p = FbGen (s,d,24,Fa,Fb,t, u, v); s = m|n|o|p; - dest[i] = s; + WRITE(dest + i, s); } } @@ -2009,32 +2010,32 @@ fbCombineMaskC (CARD32 *src, CARD32 *mask, int width) { int i; for (i = 0; i < width; ++i) { - CARD32 a = mask[i]; + CARD32 a = READ(mask + i); CARD32 x; CARD16 xa; if (!a) { - src[i] = 0; + WRITE(src + i, 0); continue; } - x = src[i]; + x = READ(src + i); if (a == 0xffffffff) { x = x >> 24; x |= x << 8; x |= x << 16; - mask[i] = x; + WRITE(mask + i, x); continue; } xa = x >> 24; FbByteMulC(x, a); - src[i] = x; + WRITE(src + i, x); FbByteMul(a, xa); - mask[i] = a; + WRITE(mask + i, a); } } @@ -2043,21 +2044,21 @@ fbCombineMaskValueC (CARD32 *src, const CARD32 *mask, int width) { int i; for (i = 0; i < width; ++i) { - CARD32 a = mask[i]; + CARD32 a = READ(mask + i); CARD32 x; if (!a) { - src[i] = 0; + WRITE(src + i, 0); continue; } if (a == 0xffffffff) continue; - x = src[i]; + x = READ(src + i); FbByteMulC(x, a); - src[i] = x; + WRITE(src + i, x); } } @@ -2067,13 +2068,13 @@ fbCombineMaskAlphaC (const CARD32 *src, CARD32 *mask, int width) { int i; for (i = 0; i < width; ++i) { - CARD32 a = mask[i]; + CARD32 a = READ(mask + i); CARD32 x; if (!a) continue; - x = src[i] >> 24; + x = READ(src + i) >> 24; if (x == 0xff) continue; if (a == 0xffffffff) @@ -2081,12 +2082,12 @@ fbCombineMaskAlphaC (const CARD32 *src, CARD32 *mask, int width) x = x >> 24; x |= x << 8; x |= x << 16; - mask[i] = x; + WRITE(mask + i, x); continue; } FbByteMul(a, x); - mask[i] = a; + WRITE(mask + i, a); } } @@ -2100,7 +2101,7 @@ static FASTCALL void fbCombineSrcC (CARD32 *dest, CARD32 *src, CARD32 *mask, int width) { fbCombineMaskValueC(src, mask, width); - memcpy(dest, src, width*sizeof(CARD32)); + MEMCPY_WRAPPED(dest, src, width*sizeof(CARD32)); } static FASTCALL void @@ -2109,18 +2110,18 @@ fbCombineOverC (CARD32 *dest, CARD32 *src, CARD32 *mask, int width) int i; fbCombineMaskC(src, mask, width); for (i = 0; i < width; ++i) { - CARD32 s = src[i]; - CARD32 a = ~mask[i]; + CARD32 s = READ(src + i); + CARD32 a = ~READ(mask + i); if (a != 0xffffffff) { if (a) { - CARD32 d = dest[i]; + CARD32 d = READ(dest + i); FbByteMulAddC(d, a, s); s = d; } - dest[i] = s; + WRITE(dest + i, s); } } } @@ -2131,17 +2132,17 @@ fbCombineOverReverseC (CARD32 *dest, CARD32 *src, CARD32 *mask, int width) int i; fbCombineMaskValueC(src, mask, width); for (i = 0; i < width; ++i) { - CARD32 d = dest[i]; + CARD32 d = READ(dest + i); CARD32 a = ~d >> 24; if (a) { - CARD32 s = src[i]; + CARD32 s = READ(src + i); if (a != 0xff) { FbByteMulAdd(s, a, d); } - dest[i] = s; + WRITE(dest + i, s); } } } @@ -2152,18 +2153,18 @@ fbCombineInC (CARD32 *dest, CARD32 *src, CARD32 *mask, int width) int i; fbCombineMaskValueC(src, mask, width); for (i = 0; i < width; ++i) { - CARD32 d = dest[i]; + CARD32 d = READ(dest + i); CARD16 a = d >> 24; CARD32 s = 0; if (a) { - s = src[i]; + s = READ(src + i); if (a != 0xff) { FbByteMul(s, a); } } - dest[i] = s; + WRITE(dest + i, s); } } @@ -2173,17 +2174,17 @@ fbCombineInReverseC (CARD32 *dest, CARD32 *src, CARD32 *mask, int width) int i; fbCombineMaskAlphaC(src, mask, width); for (i = 0; i < width; ++i) { - CARD32 a = mask[i]; + CARD32 a = READ(mask + i); if (a != 0xffffffff) { CARD32 d = 0; if (a) { - d = dest[i]; + d = READ(dest + i); FbByteMulC(d, a); } - dest[i] = d; + WRITE(dest + i, d); } } } @@ -2194,18 +2195,18 @@ fbCombineOutC (CARD32 *dest, CARD32 *src, CARD32 *mask, int width) int i; fbCombineMaskValueC(src, mask, width); for (i = 0; i < width; ++i) { - CARD32 d = dest[i]; + CARD32 d = READ(dest + i); CARD16 a = ~d >> 24; CARD32 s = 0; if (a) { - s = src[i]; + s = READ(src + i); if (a != 0xff) { FbByteMul(s, a); } } - dest[i] = s; + WRITE(dest + i, s); } } @@ -2215,17 +2216,17 @@ fbCombineOutReverseC (CARD32 *dest, CARD32 *src, CARD32 *mask, int width) int i; fbCombineMaskAlphaC(src, mask, width); for (i = 0; i < width; ++i) { - CARD32 a = ~mask[i]; + CARD32 a = ~READ(mask + i); if (a != 0xffffffff) { CARD32 d = 0; if (a) { - d = dest[i]; + d = READ(dest + i); FbByteMulC(d, a); } - dest[i] = d; + WRITE(dest + i, d); } } } @@ -2236,12 +2237,12 @@ fbCombineAtopC (CARD32 *dest, CARD32 *src, CARD32 *mask, int width) int i; fbCombineMaskC(src, mask, width); for (i = 0; i < width; ++i) { - CARD32 d = dest[i]; - CARD32 s = src[i]; - CARD32 ad = ~mask[i]; + CARD32 d = READ(dest + i); + CARD32 s = READ(src + i); + CARD32 ad = ~READ(mask + i); CARD16 as = d >> 24; FbByteAddMulC(d, ad, s, as); - dest[i] = d; + WRITE(dest + i, d); } } @@ -2252,12 +2253,12 @@ fbCombineAtopReverseC (CARD32 *dest, CARD32 *src, CARD32 *mask, int width) fbCombineMaskC(src, mask, width); for (i = 0; i < width; ++i) { - CARD32 d = dest[i]; - CARD32 s = src[i]; - CARD32 ad = mask[i]; + CARD32 d = READ(dest + i); + CARD32 s = READ(src + i); + CARD32 ad = READ(mask + i); CARD16 as = ~d >> 24; FbByteAddMulC(d, ad, s, as); - dest[i] = d; + WRITE(dest + i, d); } } @@ -2267,12 +2268,12 @@ fbCombineXorC (CARD32 *dest, CARD32 *src, CARD32 *mask, int width) int i; fbCombineMaskC(src, mask, width); for (i = 0; i < width; ++i) { - CARD32 d = dest[i]; - CARD32 s = src[i]; - CARD32 ad = ~mask[i]; + CARD32 d = READ(dest + i); + CARD32 s = READ(src + i); + CARD32 ad = ~READ(mask + i); CARD16 as = ~d >> 24; FbByteAddMulC(d, ad, s, as); - dest[i] = d; + WRITE(dest + i, d); } } @@ -2282,10 +2283,10 @@ fbCombineAddC (CARD32 *dest, CARD32 *src, CARD32 *mask, int width) int i; fbCombineMaskValueC(src, mask, width); for (i = 0; i < width; ++i) { - CARD32 s = src[i]; - CARD32 d = dest[i]; + CARD32 s = READ(src + i); + CARD32 d = READ(dest + i); FbByteAdd(d, s); - dest[i] = d; + WRITE(dest + i, d); } } @@ -2300,12 +2301,12 @@ fbCombineSaturateC (CARD32 *dest, CARD32 *src, CARD32 *mask, int width) CARD16 t, u, v; CARD32 m,n,o,p; - d = dest[i]; - s = src[i]; - sa = (mask[i] >> 24); - sr = (mask[i] >> 16) & 0xff; - sg = (mask[i] >> 8) & 0xff; - sb = (mask[i] ) & 0xff; + d = READ(dest + i); + s = READ(src + i); + sa = (READ(mask + i) >> 24); + sr = (READ(mask + i) >> 16) & 0xff; + sg = (READ(mask + i) >> 8) & 0xff; + sb = (READ(mask + i) ) & 0xff; da = ~d >> 24; if (sb <= da) @@ -2328,7 +2329,7 @@ fbCombineSaturateC (CARD32 *dest, CARD32 *src, CARD32 *mask, int width) else p = FbGen (s, d, 24, (da << 8) / sa, 0xff, t, u, v); - dest[i] = m|n|o|p; + WRITE(dest + i, m|n|o|p); } } @@ -2345,9 +2346,9 @@ fbCombineDisjointGeneralC (CARD32 *dest, CARD32 *src, CARD32 *mask, int width, C CARD32 sa; CARD8 da; - s = src[i]; - sa = mask[i]; - d = dest[i]; + s = READ(src + i); + sa = READ(mask + i); + d = READ(dest + i); da = d >> 24; switch (combine & CombineA) { @@ -2400,7 +2401,7 @@ fbCombineDisjointGeneralC (CARD32 *dest, CARD32 *src, CARD32 *mask, int width, C o = FbGen (s,d,16,FbGet8(Fa,16),FbGet8(Fb,16),t, u, v); p = FbGen (s,d,24,FbGet8(Fa,24),FbGet8(Fb,24),t, u, v); s = m|n|o|p; - dest[i] = s; + WRITE(dest + i, s); } } @@ -2465,9 +2466,9 @@ fbCombineConjointGeneralC (CARD32 *dest, CARD32 *src, CARD32 *mask, int width, C CARD32 sa; CARD8 da; - s = src[i]; - sa = mask[i]; - d = dest[i]; + s = READ(src + i); + sa = READ(mask + i); + d = READ(dest + i); da = d >> 24; switch (combine & CombineA) { @@ -2520,7 +2521,7 @@ fbCombineConjointGeneralC (CARD32 *dest, CARD32 *src, CARD32 *mask, int width, C o = FbGen (s,d,16,FbGet8(Fa,16),FbGet8(Fb,16),t, u, v); p = FbGen (s,d,24,FbGet8(Fa,24),FbGet8(Fb,24),t, u, v); s = m|n|o|p; - dest[i] = s; + WRITE(dest + i, s); } } @@ -2651,7 +2652,8 @@ static void fbFetchSolid(PicturePtr pict, int x, int y, int width, CARD32 *buffe end = buffer + width; while (buffer < end) - *buffer++ = color; + WRITE(buffer++, color); + fbFinishAccess (pict->pDrawable); } static void fbFetch(PicturePtr pict, int x, int y, int width, CARD32 *buffer) @@ -2670,6 +2672,7 @@ static void fbFetch(PicturePtr pict, int x, int y, int width, CARD32 *buffer) bits += y*stride; fetch(bits, x, width, buffer, indexed); + fbFinishAccess (pict->pDrawable); } #define MOD(a,b) ((a) < 0 ? ((b) - ((-(a) - 1) % (b))) - 1 : (a) % (b)) @@ -2717,7 +2720,7 @@ static void fbFetchSourcePict(PicturePtr pict, int x, int y, int width, CARD32 * if (pGradient->type == SourcePictTypeSolidFill) { register CARD32 color = pGradient->solidFill.color; while (buffer < end) { - *buffer++ = color; + WRITE(buffer++, color); } } else if (pGradient->type == SourcePictTypeLinear) { PictVector v, unit; @@ -2759,7 +2762,7 @@ static void fbFetchSourcePict(PicturePtr pict, int x, int y, int width, CARD32 * inc = (a * unit.vector[0] + b * unit.vector[1]) >> 16; } while (buffer < end) { - *buffer++ = gradientPixel(pGradient, t, pict->repeatType); + WRITE(buffer++, gradientPixel(pGradient, t, pict->repeatType)); t += inc; } } else { @@ -2774,7 +2777,7 @@ static void fbFetchSourcePict(PicturePtr pict, int x, int y, int width, CARD32 * y = ((xFixed_48_16)v.vector[1] << 16) / v.vector[2]; t = ((a*x + b*y) >> 16) + off; } - *buffer++ = gradientPixel(pGradient, t, pict->repeatType); + WRITE(buffer++, gradientPixel(pGradient, t, pict->repeatType)); v.vector[0] += unit.vector[0]; v.vector[1] += unit.vector[1]; v.vector[2] += unit.vector[2]; @@ -2818,9 +2821,9 @@ static void fbFetchSourcePict(PicturePtr pict, int x, int y, int width, CARD32 * double c = -(rx*rx + ry*ry); double det = (b * b) - (4 * pGradient->radial.a * c); double s = (-b + sqrt(det))/(2. * pGradient->radial.a); - *buffer = gradientPixel(pGradient, - (xFixed_48_16)((s*pGradient->radial.m + pGradient->radial.b)*65536), - pict->repeatType); + WRITE(buffer, gradientPixel(pGradient, + (xFixed_48_16)((s*pGradient->radial.m + pGradient->radial.b)*65536), + pict->repeatType)); ++buffer; rx += cx; ry += cy; @@ -2841,9 +2844,9 @@ static void fbFetchSourcePict(PicturePtr pict, int x, int y, int width, CARD32 * c = -(x*x + y*y); det = (b * b) - (4 * pGradient->radial.a * c); s = (-b + sqrt(det))/(2. * pGradient->radial.a); - *buffer = gradientPixel(pGradient, - (xFixed_48_16)((s*pGradient->radial.m + pGradient->radial.b)*65536), - pict->repeatType); + WRITE(buffer, gradientPixel(pGradient, + (xFixed_48_16)((s*pGradient->radial.m + pGradient->radial.b)*65536), + pict->repeatType)); ++buffer; rx += cx; ry += cy; @@ -2858,8 +2861,8 @@ static void fbFetchSourcePict(PicturePtr pict, int x, int y, int width, CARD32 * while (buffer < end) { double angle = atan2(ry, rx) + a; - *buffer = gradientPixel(pGradient, (xFixed_48_16) (angle * (65536. / (2*M_PI))), - pict->repeatType); + WRITE(buffer, gradientPixel(pGradient, (xFixed_48_16) (angle * (65536. / (2*M_PI))), + pict->repeatType)); ++buffer; rx += cx; ry += cy; @@ -2877,8 +2880,8 @@ static void fbFetchSourcePict(PicturePtr pict, int x, int y, int width, CARD32 * x -= pGradient->conical.center.x/65536.; y -= pGradient->conical.center.y/65536.; angle = atan2(y, x) + a; - *buffer = gradientPixel(pGradient, (xFixed_48_16) (angle * (65536. / (2*M_PI))), - pict->repeatType); + WRITE(buffer, gradientPixel(pGradient, (xFixed_48_16) (angle * (65536. / (2*M_PI))), + pict->repeatType)); ++buffer; rx += cx; ry += cy; @@ -2921,8 +2924,10 @@ static void fbFetchTransformed(PicturePtr pict, int x, int y, int width, CARD32 /* when using convolution filters one might get here without a transform */ if (pict->transform) { - if (!PictureTransformPoint3d (pict->transform, &v)) + if (!PictureTransformPoint3d (pict->transform, &v)) { + fbFinishAccess (pict->pDrawable); return; + } unit.vector[0] = pict->transform->matrix[0][0]; unit.vector[1] = pict->transform->matrix[1][0]; unit.vector[2] = pict->transform->matrix[2][0]; @@ -2939,7 +2944,7 @@ static void fbFetchTransformed(PicturePtr pict, int x, int y, int width, CARD32 if (REGION_NUM_RECTS(pict->pCompositeClip) == 1) { for (i = 0; i < width; ++i) { if (!v.vector[2]) { - buffer[i] = 0; + WRITE(buffer + i, 0); } else { if (!affine) { y = MOD(DIV(v.vector[1],v.vector[2]), pict->pDrawable->height); @@ -2948,7 +2953,7 @@ static void fbFetchTransformed(PicturePtr pict, int x, int y, int width, CARD32 y = MOD(v.vector[1]>>16, pict->pDrawable->height); x = MOD(v.vector[0]>>16, pict->pDrawable->width); } - buffer[i] = fetch(bits + (y + dy)*stride, x + dx, indexed); + WRITE(buffer + i, fetch(bits + (y + dy)*stride, x + dx, indexed)); } v.vector[0] += unit.vector[0]; v.vector[1] += unit.vector[1]; @@ -2957,7 +2962,7 @@ static void fbFetchTransformed(PicturePtr pict, int x, int y, int width, CARD32 } else { for (i = 0; i < width; ++i) { if (!v.vector[2]) { - buffer[i] = 0; + WRITE(buffer + i, 0); } else { if (!affine) { y = MOD(DIV(v.vector[1],v.vector[2]), pict->pDrawable->height); @@ -2967,9 +2972,9 @@ static void fbFetchTransformed(PicturePtr pict, int x, int y, int width, CARD32 x = MOD(v.vector[0]>>16, pict->pDrawable->width); } if (POINT_IN_REGION (0, pict->pCompositeClip, x + dx, y + dy, &box)) - buffer[i] = fetch(bits + (y + dy)*stride, x + dx, indexed); + WRITE(buffer + i, fetch(bits + (y + dy)*stride, x + dx, indexed)); else - buffer[i] = 0; + WRITE(buffer + i, 0); } v.vector[0] += unit.vector[0]; v.vector[1] += unit.vector[1]; @@ -2981,7 +2986,7 @@ static void fbFetchTransformed(PicturePtr pict, int x, int y, int width, CARD32 box = pict->pCompositeClip->extents; for (i = 0; i < width; ++i) { if (!v.vector[2]) { - buffer[i] = 0; + WRITE(buffer + i, 0); } else { if (!affine) { y = DIV(v.vector[1],v.vector[2]); @@ -2990,8 +2995,8 @@ static void fbFetchTransformed(PicturePtr pict, int x, int y, int width, CARD32 y = v.vector[1]>>16; x = v.vector[0]>>16; } - buffer[i] = ((x < box.x1-dx) | (x >= box.x2-dx) | (y < box.y1-dy) | (y >= box.y2-dy)) ? - 0 : fetch(bits + (y + dy)*stride, x + dx, indexed); + WRITE(buffer + i, ((x < box.x1-dx) | (x >= box.x2-dx) | (y < box.y1-dy) | (y >= box.y2-dy)) ? + 0 : fetch(bits + (y + dy)*stride, x + dx, indexed)); } v.vector[0] += unit.vector[0]; v.vector[1] += unit.vector[1]; @@ -3000,7 +3005,7 @@ static void fbFetchTransformed(PicturePtr pict, int x, int y, int width, CARD32 } else { for (i = 0; i < width; ++i) { if (!v.vector[2]) { - buffer[i] = 0; + WRITE(buffer + i, 0); } else { if (!affine) { y = DIV(v.vector[1],v.vector[2]); @@ -3010,9 +3015,9 @@ static void fbFetchTransformed(PicturePtr pict, int x, int y, int width, CARD32 x = v.vector[0]>>16; } if (POINT_IN_REGION (0, pict->pCompositeClip, x + dx, y + dy, &box)) - buffer[i] = fetch(bits + (y + dy)*stride, x + dx, indexed); + WRITE(buffer + i, fetch(bits + (y + dy)*stride, x + dx, indexed)); else - buffer[i] = 0; + WRITE(buffer + i, 0); } v.vector[0] += unit.vector[0]; v.vector[1] += unit.vector[1]; @@ -3031,7 +3036,7 @@ static void fbFetchTransformed(PicturePtr pict, int x, int y, int width, CARD32 if (REGION_NUM_RECTS(pict->pCompositeClip) == 1) { for (i = 0; i < width; ++i) { if (!v.vector[2]) { - buffer[i] = 0; + WRITE(buffer + i, 0); } else { int x1, x2, y1, y2, distx, idistx, disty, idisty; FbBits *b; @@ -3083,7 +3088,7 @@ static void fbFetchTransformed(PicturePtr pict, int x, int y, int width, CARD32 ft = FbGet8(tl,24) * idistx + FbGet8(tr,24) * distx; fb = FbGet8(bl,24) * idistx + FbGet8(br,24) * distx; r |= (((ft * idisty + fb * disty) << 8) & 0xff000000); - buffer[i] = r; + WRITE(buffer + i, r); } v.vector[0] += unit.vector[0]; v.vector[1] += unit.vector[1]; @@ -3092,7 +3097,7 @@ static void fbFetchTransformed(PicturePtr pict, int x, int y, int width, CARD32 } else { for (i = 0; i < width; ++i) { if (!v.vector[2]) { - buffer[i] = 0; + WRITE(buffer + i, 0); } else { int x1, x2, y1, y2, distx, idistx, disty, idisty; FbBits *b; @@ -3148,7 +3153,7 @@ static void fbFetchTransformed(PicturePtr pict, int x, int y, int width, CARD32 ft = FbGet8(tl,24) * idistx + FbGet8(tr,24) * distx; fb = FbGet8(bl,24) * idistx + FbGet8(br,24) * distx; r |= (((ft * idisty + fb * disty) << 8) & 0xff000000); - buffer[i] = r; + WRITE(buffer + i, r); } v.vector[0] += unit.vector[0]; v.vector[1] += unit.vector[1]; @@ -3160,7 +3165,7 @@ static void fbFetchTransformed(PicturePtr pict, int x, int y, int width, CARD32 box = pict->pCompositeClip->extents; for (i = 0; i < width; ++i) { if (!v.vector[2]) { - buffer[i] = 0; + WRITE(buffer + i, 0); } else { int x1, x2, y1, y2, distx, idistx, disty, idisty, x_off; FbBits *b; @@ -3214,7 +3219,7 @@ static void fbFetchTransformed(PicturePtr pict, int x, int y, int width, CARD32 ft = FbGet8(tl,24) * idistx + FbGet8(tr,24) * distx; fb = FbGet8(bl,24) * idistx + FbGet8(br,24) * distx; r |= (((ft * idisty + fb * disty) << 8) & 0xff000000); - buffer[i] = r; + WRITE(buffer + i, r); } v.vector[0] += unit.vector[0]; v.vector[1] += unit.vector[1]; @@ -3223,7 +3228,7 @@ static void fbFetchTransformed(PicturePtr pict, int x, int y, int width, CARD32 } else { for (i = 0; i < width; ++i) { if (!v.vector[2]) { - buffer[i] = 0; + WRITE(buffer + i, 0); } else { int x1, x2, y1, y2, distx, idistx, disty, idisty, x_off; FbBits *b; @@ -3275,7 +3280,7 @@ static void fbFetchTransformed(PicturePtr pict, int x, int y, int width, CARD32 ft = FbGet8(tl,24) * idistx + FbGet8(tr,24) * distx; fb = FbGet8(bl,24) * idistx + FbGet8(br,24) * distx; r |= (((ft * idisty + fb * disty) << 8) & 0xff000000); - buffer[i] = r; + WRITE(buffer + i, r); } v.vector[0] += unit.vector[0]; v.vector[1] += unit.vector[1]; @@ -3292,7 +3297,7 @@ static void fbFetchTransformed(PicturePtr pict, int x, int y, int width, CARD32 params += 2; for (i = 0; i < width; ++i) { if (!v.vector[2]) { - buffer[i] = 0; + WRITE(buffer + i, 0); } else { int x1, x2, y1, y2, x, y; INT32 srtot, sgtot, sbtot, satot; @@ -3342,16 +3347,18 @@ static void fbFetchTransformed(PicturePtr pict, int x, int y, int width, CARD32 if (sgtot < 0) sgtot = 0; else if (sgtot > 0xff) sgtot = 0xff; if (sbtot < 0) sbtot = 0; else if (sbtot > 0xff) sbtot = 0xff; - buffer[i] = ((satot << 24) | - (srtot << 16) | - (sgtot << 8) | - (sbtot )); + WRITE(buffer + i, ((satot << 24) | + (srtot << 16) | + (sgtot << 8) | + (sbtot ))); } v.vector[0] += unit.vector[0]; v.vector[1] += unit.vector[1]; v.vector[2] += unit.vector[2]; } } + + fbFinishAccess (pict->pDrawable); } @@ -3372,10 +3379,10 @@ static void fbFetchExternalAlpha(PicturePtr pict, int x, int y, int width, CARD3 fbFetchTransformed(pict->alphaMap, x - pict->alphaOrigin.x, y - pict->alphaOrigin.y, width, alpha_buffer); for (i = 0; i < width; ++i) { int a = alpha_buffer[i]>>24; - buffer[i] = (a << 24) - | (div_255(Red(buffer[i]) * a) << 16) - | (div_255(Green(buffer[i]) * a) << 8) - | (div_255(Blue(buffer[i]) * a)); + WRITE(buffer + i, (a << 24) + | (div_255(Red(READ(buffer + i)) * a) << 16) + | (div_255(Green(READ(buffer + i)) * a) << 8) + | (div_255(Blue(READ(buffer + i)) * a))); } if (alpha_buffer != _alpha_buffer) @@ -3397,6 +3404,7 @@ static void fbStore(PicturePtr pict, int x, int y, int width, CARD32 *buffer) bits += y*stride; store(bits, buffer, x, width, indexed); + fbFinishAccess (pict->pDrawable); } static void fbStoreExternalAlpha(PicturePtr pict, int x, int y, int width, CARD32 *buffer) @@ -3436,6 +3444,9 @@ static void fbStoreExternalAlpha(PicturePtr pict, int x, int y, int width, CARD3 store(bits, buffer, x, width, indexed); astore(alpha_bits, buffer, ax - pict->alphaOrigin.x, width, aindexed); + + fbFinishAccess (pict->alphaMap->pDrawable); + fbFinishAccess (pict->pDrawable); } typedef void (*scanStoreProc)(PicturePtr , int , int , int , CARD32 *); diff --git a/fb/fbcopy.c b/fb/fbcopy.c index 0d1cb7faf..164cd3d67 100644 --- a/fb/fbcopy.c +++ b/fb/fbcopy.c @@ -103,6 +103,8 @@ fbCopyNtoN (DrawablePtr pSrcDrawable, #endif pbox++; } + fbFinishAccess (pDstDrawable); + fbFinishAccess (pSrcDrawable); } void @@ -173,6 +175,9 @@ fbCopy1toN (DrawablePtr pSrcDrawable, } pbox++; } + + fbFinishAccess (pDstDrawable); + fbFinishAccess (pSrcDrawable); } void @@ -221,6 +226,8 @@ fbCopyNto1 (DrawablePtr pSrcDrawable, (FbStip) pPriv->and, (FbStip) pPriv->xor, (FbStip) pPriv->bgand, (FbStip) pPriv->bgxor, bitplane); + fbFinishAccess (pDstDrawable); + fbFinishAccess (pSrcDrawable); } else { @@ -281,6 +288,9 @@ fbCopyNto1 (DrawablePtr pSrcDrawable, pPriv->and, pPriv->xor, pPriv->bgand, pPriv->bgxor); xfree (tmp); + + fbFinishAccess (pDstDrawable); + fbFinishAccess (pSrcDrawable); } pbox++; } diff --git a/fb/fbedge.c b/fb/fbedge.c index b6ca829a4..70fc423bd 100644 --- a/fb/fbedge.c +++ b/fb/fbedge.c @@ -60,9 +60,9 @@ #define StepAlpha ((__ap += __ao), (__ao ^= 1)) #define AddAlpha(a) { \ - CARD8 __o = *__ap; \ + CARD8 __o = READ(__ap); \ CARD8 __a = (a) + Get4(__o, __ao); \ - *__ap = Put4 (__o, __ao, __a | (0 - ((__a) >> 4))); \ + WRITE(__ap, Put4 (__o, __ao, __a | (0 - ((__a) >> 4)))); \ } #include "fbedgeimp.h" @@ -102,7 +102,7 @@ add_saturate_8 (CARD8 *buf, int value, int length) { while (length--) { - *buf = clip255 (*buf + value); + WRITE(buf, clip255 (READ(buf) + value)); buf++; } } @@ -164,11 +164,11 @@ fbRasterizeEdges8 (FbBits *buf, /* Add coverage across row */ if (lxi == rxi) { - ap[lxi] = clip255 (ap[lxi] + rxs - lxs); + WRITE(ap +lxi, clip255 (READ(ap + lxi) + rxs - lxs)); } else { - ap[lxi] = clip255 (ap[lxi] + N_X_FRAC(8) - lxs); + WRITE(ap + lxi, clip255 (READ(ap + lxi) + N_X_FRAC(8) - lxs)); /* Move forward so that lxi/rxi is the pixel span */ lxi++; @@ -238,7 +238,7 @@ fbRasterizeEdges8 (FbBits *buf, * necessary to avoid a buffer overrun, (when rx * is exactly on a pixel boundary). */ if (rxs) - ap[rxi] = clip255 (ap[rxi] + rxs); + WRITE(ap + rxi, clip255 (READ(ap + rxi) + rxs)); } } @@ -247,7 +247,7 @@ fbRasterizeEdges8 (FbBits *buf, if (fill_start != fill_end) { if (fill_size == N_Y_FRAC(8)) { - memset (ap + fill_start, 0xff, fill_end - fill_start); + MEMSET_WRAPPED (ap + fill_start, 0xff, fill_end - fill_start); } else { @@ -273,7 +273,7 @@ fbRasterizeEdges8 (FbBits *buf, { if (fill_size == N_Y_FRAC(8)) { - memset (ap + fill_start, 0xff, fill_end - fill_start); + MEMSET_WRAPPED (ap + fill_start, 0xff, fill_end - fill_start); } else { diff --git a/fb/fbedgeimp.h b/fb/fbedgeimp.h index 877393516..57da31a39 100644 --- a/fb/fbedgeimp.h +++ b/fb/fbedgeimp.h @@ -76,12 +76,14 @@ rasterizeEdges (FbBits *buf, x &= FB_MASK; FbMaskBits (x, width, startmask, nmiddle, endmask); - if (startmask) - *a++ |= startmask; + if (startmask) { + WRITE(a, READ(a) | startmask); + a++; + } while (nmiddle--) - *a++ = FB_ALLONES; + WRITE(a++, FB_ALLONES); if (endmask) - *a |= endmask; + WRITE(a, READ(a) | endmask); } #else { diff --git a/fb/fbfill.c b/fb/fbfill.c index ad5025c84..7ef3a70f9 100644 --- a/fb/fbfill.c +++ b/fb/fbfill.c @@ -49,8 +49,10 @@ fbFill (DrawablePtr pDrawable, case FillSolid: #ifdef USE_MMX if (!pPriv->and && fbHaveMMX()) - if (fbSolidFillmmx (pDrawable, x, y, width, height, pPriv->xor)) + if (fbSolidFillmmx (pDrawable, x, y, width, height, pPriv->xor)) { + fbFinishAccess (pDrawable); return; + } #endif fbSolid (dst + (y + dstYoff) * dstStride, dstStride, @@ -92,6 +94,7 @@ fbFill (DrawablePtr pDrawable, (pGC->patOrg.x + pDrawable->x + dstXoff), pGC->patOrg.y + pDrawable->y - y); + fbFinishAccess (&pStip->drawable); } else { @@ -129,6 +132,7 @@ fbFill (DrawablePtr pDrawable, bgand, bgxor, pGC->patOrg.x + pDrawable->x + dstXoff, pGC->patOrg.y + pDrawable->y - y); + fbFinishAccess (&pStip->drawable); } break; } @@ -157,10 +161,12 @@ fbFill (DrawablePtr pDrawable, dstBpp, (pGC->patOrg.x + pDrawable->x + dstXoff) * dstBpp, pGC->patOrg.y + pDrawable->y - y); + fbFinishAccess (&pTile->drawable); break; } } fbValidateDrawable (pDrawable); + fbFinishAccess (pDrawable); } void @@ -215,8 +221,10 @@ fbSolidBoxClipped (DrawablePtr pDrawable, if (fbSolidFillmmx (pDrawable, partX1, partY1, (partX2 - partX1), (partY2 - partY1), - xor)) + xor)) { + fbFinishAccess (pDrawable); return; + } } #endif fbSolid (dst + (partY1 + dstYoff) * dstStride, @@ -228,4 +236,5 @@ fbSolidBoxClipped (DrawablePtr pDrawable, (partY2 - partY1), and, xor); } + fbFinishAccess (pDrawable); } diff --git a/fb/fbgc.c b/fb/fbgc.c index 5b5581093..3f8bf25e7 100644 --- a/fb/fbgc.c +++ b/fb/fbgc.c @@ -106,16 +106,18 @@ fbPadPixmap (PixmapPtr pPixmap) mask = FbBitsMask (0, width); while (height--) { - b = *bits & mask; + b = READ(bits) & mask; w = width; while (w < FB_UNIT) { b = b | FbScrRight(b, w); w <<= 1; } - *bits = b; + WRITE(bits, b); bits += stride; } + + fbFinishAccess (&pPixmap->drawable); } /* @@ -153,7 +155,7 @@ fbLineRepeat (FbBits *bits, int len, int width) width = (width + FB_UNIT-1) >> FB_SHIFT; bits++; while (--width) - if (*bits != first) + if (READ(bits) != first) return FALSE; return TRUE; } @@ -183,10 +185,13 @@ fbCanEvenStipple (PixmapPtr pStipple, int bpp) /* check to see that the stipple repeats horizontally */ while (h--) { - if (!fbLineRepeat (bits, len, pStipple->drawable.width)) + if (!fbLineRepeat (bits, len, pStipple->drawable.width)) { + fbFinishAccess (&pStipple->drawable); return FALSE; + } bits += stride; } + fbFinishAccess (&pStipple->drawable); return TRUE; } diff --git a/fb/fbgetsp.c b/fb/fbgetsp.c index f77ea8c52..ffd8a1d7d 100644 --- a/fb/fbgetsp.c +++ b/fb/fbgetsp.c @@ -84,4 +84,6 @@ fbGetSpans(DrawablePtr pDrawable, ppt++; pwidth++; } + + fbFinishAccess (pDrawable); } diff --git a/fb/fbglyph.c b/fb/fbglyph.c index 8e819401b..2c19b742f 100644 --- a/fb/fbglyph.c +++ b/fb/fbglyph.c @@ -62,11 +62,11 @@ fbGlyphIn (RegionPtr pRegion, #ifdef FB_24BIT #ifndef FBNOPIXADDR -#define WRITE1(d,n,fg) ((d)[n] = (CARD8) fg) -#define WRITE2(d,n,fg) (*(CARD16 *) &(d[n]) = (CARD16) fg) -#define WRITE4(d,n,fg) (*(CARD32 *) &(d[n]) = (CARD32) fg) +#define WRITE1(d,n,fg) WRITE((d) + (n), (CARD8) fg) +#define WRITE2(d,n,fg) WRITE((CARD16 *) &(d[n]), (CARD16) fg) +#define WRITE4(d,n,fg) WRITE((CARD32 *) &(d[n]), (CARD32) fg) #if FB_UNIT == 6 && IMAGE_BYTE_ORDER == LSBFirst -#define WRITE8(d) (*(FbBits *) &(d[0]) = fg) +#define WRITE8(d) WRITE((FbBits *) &(d[0]), fg) #else #define WRITE8(d) WRITE4(d,0,_ABCA), WRITE4(d,4,_BCAB) #endif @@ -157,7 +157,7 @@ fbGlyph24 (FbBits *dstBits, lshift = 4 - shift; while (height--) { - bits = *stipple++; + bits = READ(stipple++); n = lshift; dst = dstLine; while (bits) @@ -284,7 +284,7 @@ fbPolyGlyphBlt (DrawablePtr pDrawable, glyph = 0; if (pGC->fillStyle == FillSolid && pPriv->and == 0) { - fbGetDrawable (pDrawable, dst, dstStride, dstBpp, dstXoff, dstYoff); + dstBpp = pDrawable->bitsPerPixel; switch (dstBpp) { case 8: glyph = fbGlyph8; break; case 16: glyph = fbGlyph16; break; @@ -312,6 +312,7 @@ fbPolyGlyphBlt (DrawablePtr pDrawable, if (glyph && gWidth <= sizeof (FbStip) * 8 && fbGlyphIn (fbGetCompositeClip(pGC), gx, gy, gWidth, gHeight)) { + fbGetDrawable (pDrawable, dst, dstStride, dstBpp, dstXoff, dstYoff); (*glyph) (dst + (gy + dstYoff) * dstStride, dstStride, dstBpp, @@ -319,6 +320,7 @@ fbPolyGlyphBlt (DrawablePtr pDrawable, pPriv->xor, gx + dstXoff, gHeight); + fbFinishAccess (pDrawable); } else #endif @@ -375,7 +377,7 @@ fbImageGlyphBlt (DrawablePtr pDrawable, glyph = 0; if (pPriv->and == 0) { - fbGetDrawable (pDrawable, dst, dstStride, dstBpp, dstXoff, dstYoff); + dstBpp = pDrawable->bitsPerPixel; switch (dstBpp) { case 8: glyph = fbGlyph8; break; case 16: glyph = fbGlyph16; break; @@ -443,6 +445,7 @@ fbImageGlyphBlt (DrawablePtr pDrawable, if (glyph && gWidth <= sizeof (FbStip) * 8 && fbGlyphIn (fbGetCompositeClip(pGC), gx, gy, gWidth, gHeight)) { + fbGetDrawable (pDrawable, dst, dstStride, dstBpp, dstXoff, dstYoff); (*glyph) (dst + (gy + dstYoff) * dstStride, dstStride, dstBpp, @@ -450,6 +453,7 @@ fbImageGlyphBlt (DrawablePtr pDrawable, pPriv->fg, gx + dstXoff, gHeight); + fbFinishAccess (pDrawable); } else #endif diff --git a/fb/fbimage.c b/fb/fbimage.c index bf5c06b57..06a3c84fe 100644 --- a/fb/fbimage.c +++ b/fb/fbimage.c @@ -68,7 +68,7 @@ fbPutImage (DrawablePtr pDrawable, break; case XYPixmap: srcStride = BitmapBytePad(w + leftPad) / sizeof (FbStip); - for (i = 1 << (pDrawable->depth - 1); i; i >>= 1) + for (i = (unsigned long)1 << (pDrawable->depth - 1); i; i >>= 1) { if (i & pGC->planemask) { @@ -170,6 +170,8 @@ fbPutZImage (DrawablePtr pDrawable, pm, dstBpp); } + + fbFinishAccess (pDrawable); } void @@ -277,6 +279,8 @@ fbPutXYImage (DrawablePtr pDrawable, fgand, fgxor, bgand, bgxor); } } + + fbFinishAccess (pDrawable); } void @@ -361,4 +365,6 @@ fbGetImage (DrawablePtr pDrawable, fbXorStip(GXcopy,0,FB_STIP_ALLONES), planeMask); } + + fbFinishAccess (pDrawable); } diff --git a/fb/fbpict.c b/fb/fbpict.c index c208643dd..d839994ae 100644 --- a/fb/fbpict.c +++ b/fb/fbpict.c @@ -137,22 +137,25 @@ fbCompositeSolidMask_nx8x8888 (CARD8 op, while (w--) { - m = *mask++; + m = READ(mask++); if (m == 0xff) { if (srca == 0xff) - *dst = src & dstMask; + WRITE(dst, src & dstMask); else - *dst = fbOver (src, *dst) & dstMask; + WRITE(dst, fbOver (src, READ(dst)) & dstMask); } else if (m) { d = fbIn (src, m); - *dst = fbOver (d, *dst) & dstMask; + WRITE(dst, fbOver (d, READ(dst)) & dstMask); } dst++; } } + + fbFinishAccess (pMask->pDrawable); + fbFinishAccess (pDst->pDrawable); } void @@ -196,17 +199,17 @@ fbCompositeSolidMask_nx8888x8888C (CARD8 op, while (w--) { - ma = *mask++; + ma = READ(mask++); if (ma == 0xffffffff) { if (srca == 0xff) - *dst = src & dstMask; + WRITE(dst, src & dstMask); else - *dst = fbOver (src, *dst) & dstMask; + WRITE(dst, fbOver (src, READ(dst)) & dstMask); } else if (ma) { - d = *dst; + d = READ(dst); #define FbInOverC(src,srca,msk,dst,i,result) { \ CARD16 __a = FbGet8(msk,i); \ CARD32 __t, __ta; \ @@ -221,11 +224,14 @@ fbCompositeSolidMask_nx8888x8888C (CARD8 op, FbInOverC (src, srca, ma, d, 8, n); FbInOverC (src, srca, ma, d, 16, o); FbInOverC (src, srca, ma, d, 24, p); - *dst = m|n|o|p; + WRITE(dst, m|n|o|p); } dst++; } } + + fbFinishAccess (pMask->pDrawable); + fbFinishAccess (pDst->pDrawable); } void @@ -268,7 +274,7 @@ fbCompositeSolidMask_nx8x0888 (CARD8 op, while (w--) { - m = *mask++; + m = READ(mask++); if (m == 0xff) { if (srca == 0xff) @@ -288,6 +294,9 @@ fbCompositeSolidMask_nx8x0888 (CARD8 op, dst += 3; } } + + fbFinishAccess (pMask->pDrawable); + fbFinishAccess (pDst->pDrawable); } void @@ -330,27 +339,30 @@ fbCompositeSolidMask_nx8x0565 (CARD8 op, while (w--) { - m = *mask++; + m = READ(mask++); if (m == 0xff) { if (srca == 0xff) d = src; else { - d = *dst; + d = READ(dst); d = fbOver24 (src, cvt0565to8888(d)); } - *dst = cvt8888to0565(d); + WRITE(dst, cvt8888to0565(d)); } else if (m) { - d = *dst; + d = READ(dst); d = fbOver24 (fbIn(src,m), cvt0565to8888(d)); - *dst = cvt8888to0565(d); + WRITE(dst, cvt8888to0565(d)); } dst++; } } + + fbFinishAccess (pMask->pDrawable); + fbFinishAccess (pDst->pDrawable); } void @@ -397,33 +409,36 @@ fbCompositeSolidMask_nx8888x0565C (CARD8 op, while (w--) { - ma = *mask++; + ma = READ(mask++); if (ma == 0xffffffff) { if (srca == 0xff) { - *dst = src16; + WRITE(dst, src16); } else { - d = *dst; + d = READ(dst); d = fbOver24 (src, cvt0565to8888(d)); - *dst = cvt8888to0565(d); + WRITE(dst, cvt8888to0565(d)); } } else if (ma) { - d = *dst; + d = READ(dst); d = cvt0565to8888(d); FbInOverC (src, srca, ma, d, 0, m); FbInOverC (src, srca, ma, d, 8, n); FbInOverC (src, srca, ma, d, 16, o); d = m|n|o; - *dst = cvt8888to0565(d); + WRITE(dst, cvt8888to0565(d)); } dst++; } } + + fbFinishAccess (pMask->pDrawable); + fbFinishAccess (pDst->pDrawable); } void @@ -461,15 +476,18 @@ fbCompositeSrc_8888x8888 (CARD8 op, while (w--) { - s = *src++; + s = READ(src++); a = s >> 24; if (a == 0xff) - *dst = s & dstMask; + WRITE(dst, s & dstMask); else if (a) - *dst = fbOver (s, *dst) & dstMask; + WRITE(dst, fbOver (s, READ(dst)) & dstMask); dst++; } } + + fbFinishAccess (pSrc->pDrawable); + fbFinishAccess (pDst->pDrawable); } void @@ -506,7 +524,7 @@ fbCompositeSrc_8888x0888 (CARD8 op, while (w--) { - s = *src++; + s = READ(src++); a = s >> 24; if (a) { @@ -519,6 +537,9 @@ fbCompositeSrc_8888x0888 (CARD8 op, dst += 3; } } + + fbFinishAccess (pSrc->pDrawable); + fbFinishAccess (pDst->pDrawable); } void @@ -555,7 +576,7 @@ fbCompositeSrc_8888x0565 (CARD8 op, while (w--) { - s = *src++; + s = READ(src++); a = s >> 24; if (a) { @@ -563,14 +584,17 @@ fbCompositeSrc_8888x0565 (CARD8 op, d = s; else { - d = *dst; + d = READ(dst); d = fbOver24 (s, cvt0565to8888(d)); } - *dst = cvt8888to0565(d); + WRITE(dst, cvt8888to0565(d)); } dst++; } } + + fbFinishAccess (pDst->pDrawable); + fbFinishAccess (pSrc->pDrawable); } void @@ -605,8 +629,11 @@ fbCompositeSrc_0565x0565 (CARD8 op, w = width; while (w--) - *dst++ = *src++; + WRITE(dst, READ(src++)); } + + fbFinishAccess (pDst->pDrawable); + fbFinishAccess (pSrc->pDrawable); } void @@ -643,20 +670,23 @@ fbCompositeSrcAdd_8000x8000 (CARD8 op, while (w--) { - s = *src++; + s = READ(src++); if (s) { if (s != 0xff) { - d = *dst; + d = READ(dst); t = d + s; s = t | (0 - (t >> 8)); } - *dst = s; + WRITE(dst, s); } dst++; } } + + fbFinishAccess (pDst->pDrawable); + fbFinishAccess (pSrc->pDrawable); } void @@ -694,12 +724,12 @@ fbCompositeSrcAdd_8888x8888 (CARD8 op, while (w--) { - s = *src++; + s = READ(src++); if (s) { if (s != 0xffffffff) { - d = *dst; + d = READ(dst); if (d) { m = FbAdd(s,d,0,t); @@ -709,11 +739,14 @@ fbCompositeSrcAdd_8888x8888 (CARD8 op, s = m|n|o|p; } } - *dst = s; + WRITE(dst, s); } dst++; } } + + fbFinishAccess (pDst->pDrawable); + fbFinishAccess (pSrc->pDrawable); } void @@ -757,6 +790,9 @@ fbCompositeSrcAdd_1000x1000 (CARD8 op, FALSE, FALSE); + + fbFinishAccess(pDst->pDrawable); + fbFinishAccess(pSrc->pDrawable); } void @@ -821,6 +857,9 @@ fbCompositeSolidMask_nx1xn (CARD8 op, src, FB_ALLONES, 0x0); + + fbFinishAccess (pDst->pDrawable); + fbFinishAccess (pMask->pDrawable); } # define mod(a,b) ((b) == 1 ? 0 : (a) >= 0 ? (a) % (b) : (b) - (-a) % (b)) @@ -1396,6 +1435,10 @@ fbPictureInit (ScreenPtr pScreen, PictFormatPtr formats, int nformats) */ #if !defined(__amd64__) && !defined(__x86_64__) +#ifdef HAVE_GETISAX +#include +#endif + enum CPUFeatures { NoFeatures = 0, MMX = 0x1, @@ -1406,7 +1449,23 @@ enum CPUFeatures { }; static unsigned int detectCPUFeatures(void) { + unsigned int features = 0; unsigned int result; + +#ifdef HAVE_GETISAX + if (getisax(&result, 1)) { + if (result & AV_386_CMOV) + features |= CMOV; + if (result & AV_386_MMX) + features |= MMX; + if (result & AV_386_AMD_MMX) + features |= MMX_Extensions; + if (result & AV_386_SSE) + features |= SSE; + if (result & AV_386_SSE2) + features |= SSE2; + } +#else char vendor[13]; vendor[0] = 0; vendor[12] = 0; @@ -1415,7 +1474,8 @@ static unsigned int detectCPUFeatures(void) { * %esp here. We can't declare either one as clobbered * since they are special registers (%ebx is the "PIC * register" holding an offset to global data, %esp the - * stack pointer), so we need to make sure they have their+ * original values when we access the output operands. + * stack pointer), so we need to make sure they have their + * original values when we access the output operands. */ __asm__ ("pushf\n" "pop %%eax\n" @@ -1451,7 +1511,6 @@ static unsigned int detectCPUFeatures(void) { : "%eax", "%ecx", "%edx" ); - unsigned int features = 0; if (result) { /* result now contains the standard feature bits */ if (result & (1 << 15)) @@ -1485,6 +1544,7 @@ static unsigned int detectCPUFeatures(void) { features |= MMX_Extensions; } } +#endif /* HAVE_GETISAX */ return features; } diff --git a/fb/fbpict.h b/fb/fbpict.h index 4ad032471..19d555781 100644 --- a/fb/fbpict.h +++ b/fb/fbpict.h @@ -76,13 +76,13 @@ fbGetDrawable((pict)->pDrawable,__bits__,__stride__,__bpp__,__xoff__,__yoff__); \ switch (__bpp__) { \ case 32: \ - (bits) = *(CARD32 *) __bits__; \ + (bits) = READ((CARD32 *) __bits__); \ break; \ case 24: \ (bits) = Fetch24 ((CARD8 *) __bits__); \ break; \ case 16: \ - (bits) = *(CARD16 *) __bits__; \ + (bits) = READ((CARD16 *) __bits__); \ (bits) = cvt0565to8888(bits); \ break; \ default: \ @@ -99,6 +99,7 @@ /* manage missing src alpha */ \ if ((pict)->pFormat->direct.alphaMask == 0) \ (bits) |= 0xff000000; \ + fbFinishAccess ((pict)->pDrawable); \ } #define fbComposeGetStart(pict,x,y,type,stride,line,mul) {\ @@ -120,22 +121,22 @@ #if IMAGE_BYTE_ORDER == MSBFirst #define Fetch24(a) ((unsigned long) (a) & 1 ? \ - ((*(a) << 16) | *((CARD16 *) ((a)+1))) : \ - ((*((CARD16 *) (a)) << 8) | *((a)+2))) + ((READ(a) << 16) | READ((CARD16 *) ((a)+1))) : \ + ((READ((CARD16 *) (a)) << 8) | READ((a)+2))) #define Store24(a,v) ((unsigned long) (a) & 1 ? \ - ((*(a) = (CARD8) ((v) >> 16)), \ - (*((CARD16 *) ((a)+1)) = (CARD16) (v))) : \ - ((*((CARD16 *) (a)) = (CARD16) ((v) >> 8)), \ - (*((a)+2) = (CARD8) (v)))) + (WRITE(a, (CARD8) ((v) >> 16)), \ + WRITE((CARD16 *) ((a)+1), (CARD16) (v))) : \ + (WRITE((CARD16 *) (a), (CARD16) ((v) >> 8)), \ + WRITE((a)+2, (CARD8) (v)))) #else #define Fetch24(a) ((unsigned long) (a) & 1 ? \ - ((*(a)) | (*((CARD16 *) ((a)+1)) << 8)) : \ - ((*((CARD16 *) (a))) | (*((a)+2) << 16))) + (READ(a) | (READ((CARD16 *) ((a)+1)) << 8)) : \ + (READ((CARD16 *) (a)) | (READ((a)+2) << 16))) #define Store24(a,v) ((unsigned long) (a) & 1 ? \ - ((*(a) = (CARD8) (v)), \ - (*((CARD16 *) ((a)+1)) = (CARD16) ((v) >> 8))) : \ - ((*((CARD16 *) (a)) = (CARD16) (v)),\ - (*((a)+2) = (CARD8) ((v) >> 16)))) + (WRITE(a, (CARD8) (v)), \ + WRITE((CARD16 *) ((a)+1), (CARD16) ((v) >> 8))) : \ + (WRITE((CARD16 *) (a), (CARD16) (v)),\ + WRITE((a)+2, (CARD8) ((v) >> 16)))) #endif /* diff --git a/fb/fbpixmap.c b/fb/fbpixmap.c index f79f7010d..c2ddcb0e9 100644 --- a/fb/fbpixmap.c +++ b/fb/fbpixmap.c @@ -160,6 +160,8 @@ fbPixmapToRegion(PixmapPtr pPix) FirstRect = REGION_BOXPTR(pReg); rects = FirstRect; + fbPrepareAccess(&pPix->drawable); + pwLine = (FbBits *) pPix->devPrivate.ptr; nWidth = pPix->devKind >> (FB_SHIFT-3); @@ -174,7 +176,7 @@ fbPixmapToRegion(PixmapPtr pPix) irectLineStart = rects - FirstRect; /* If the Screen left most bit of the word is set, we're starting in * a box */ - if(*pw & mask0) + if(READ(pw) & mask0) { fInBox = TRUE; rx1 = 0; @@ -185,7 +187,7 @@ fbPixmapToRegion(PixmapPtr pPix) pwLineEnd = pw + (width >> FB_SHIFT); for (base = 0; pw < pwLineEnd; base += FB_UNIT) { - w = *pw++; + w = READ(pw++); if (fInBox) { if (!~w) @@ -226,7 +228,7 @@ fbPixmapToRegion(PixmapPtr pPix) if(width & FB_MASK) { /* Process final partial word on line */ - w = *pw++; + w = READ(pw++); for(ib = 0; ib < (width & FB_MASK); ib++) { /* If the Screen left most bit of the word is set, we're @@ -311,6 +313,8 @@ fbPixmapToRegion(PixmapPtr pPix) pReg->data = (RegDataPtr)NULL; } } + + fbFinishAccess(&pPix->drawable); #ifdef DEBUG if (!miValidRegion(pReg)) FatalError("Assertion failed file %s, line %d: expr\n", __FILE__, __LINE__); @@ -362,6 +366,7 @@ fbValidateDrawable (DrawablePtr pDrawable) if (!fbValidateBits (first, stride, FB_HEAD_BITS) || !fbValidateBits (last, stride, FB_TAIL_BITS)) fbInitializeDrawable(pDrawable); + fbFinishAccess (pDrawable); } void @@ -383,5 +388,6 @@ fbInitializeDrawable (DrawablePtr pDrawable) last = bits + stride * pDrawable->height; fbSetBits (first, stride, FB_HEAD_BITS); fbSetBits (last, stride, FB_TAIL_BITS); + fbFinishAccess (pDrawable); } #endif /* FB_DEBUG */ diff --git a/fb/fbpoint.c b/fb/fbpoint.c index 7154b53a1..c03ea18cc 100644 --- a/fb/fbpoint.c +++ b/fb/fbpoint.c @@ -90,20 +90,20 @@ fbDots (FbBits *dstOrig, FbMaskStip (x, 24, leftMask, n, rightMask); if (leftMask) { - *d = FbDoMaskRRop (*d, andT, xorT, leftMask); + WRITE(d, FbDoMaskRRop (READ(d), andT, xorT, leftMask)); andT = FbNext24Stip(andT); xorT = FbNext24Stip(xorT); d++; } if (rightMask) - *d = FbDoMaskRRop(*d, andT, xorT, rightMask); + WRITE(d, FbDoMaskRRop(READ(d), andT, xorT, rightMask)); } else #endif { FbStip mask; mask = FbStipMask(x, dstBpp); - *d = FbDoMaskRRop (*d, and, xor, mask); + WRITE(d, FbDoMaskRRop (READ(d), and, xor, mask)); } } } @@ -160,4 +160,5 @@ fbPolyPoint (DrawablePtr pDrawable, nBox--; pBox++) (*dots) (dst, dstStride, dstBpp, pBox, pptInit, nptInit, pDrawable->x, pDrawable->y, dstXoff, dstYoff, and, xor); + fbFinishAccess (pDrawable); } diff --git a/fb/fbpseudocolor.c b/fb/fbpseudocolor.c index 2233f95dc..271e98145 100644 --- a/fb/fbpseudocolor.c +++ b/fb/fbpseudocolor.c @@ -875,6 +875,8 @@ xxCopyPseudocolorRegion(ScreenPtr pScreen, RegionPtr pReg, register CARD16 *d; int w; + fbPrepareAccess((DrawablePtr)pScreen->devPrivate); + dst_base = (CARD16*) ((PixmapPtr)pScreen->devPrivate)->devPrivate.ptr; dst_stride = (int)((PixmapPtr)pScreen->devPrivate)->devKind / sizeof (CARD16); @@ -899,6 +901,8 @@ xxCopyPseudocolorRegion(ScreenPtr pScreen, RegionPtr pReg, } pbox++; } + + fbFinishAccess(&((PixmapPtr)pScreen->devPrivate)->drawable); } static void @@ -1200,7 +1204,7 @@ GCFuncs xxGCFuncs = { xxChangeClip, xxDestroyClip, xxCopyClip }; -GCOps xxGCOps = { +static GCOps xxGCOps = { xxFillSpans, xxSetSpans, xxPutImage, xxCopyArea, xxCopyPlane, xxPolyPoint, diff --git a/fb/fbpush.c b/fb/fbpush.c index 0632766d0..bb7bcefef 100644 --- a/fb/fbpush.c +++ b/fb/fbpush.c @@ -58,7 +58,7 @@ fbPushPattern (DrawablePtr pDrawable, w = width; s = src; src += srcStride; - bits = *s++; + bits = READ(s++); xspan = x; while (w) { @@ -73,7 +73,7 @@ fbPushPattern (DrawablePtr pDrawable, bitsMask = FbStipRight (bitsMask, 1); if (!bitsMask) { - bits = *s++; + bits = READ(s++); bitsMask = FbBitsMask(0,1); } } while (bits & bitsMask); @@ -92,7 +92,7 @@ fbPushPattern (DrawablePtr pDrawable, bitsMask = FbStipRight (bitsMask, 1); if (!bitsMask) { - bits = *s++; + bits = READ(s++); bitsMask = FbBitsMask(0,1); } } while (!(bits & bitsMask)); @@ -165,6 +165,7 @@ fbPushFill (DrawablePtr pDrawable, fbAnd(GXnoop,(FbBits) 0,FB_ALLONES), fbXor(GXnoop,(FbBits) 0,FB_ALLONES)); } + fbFinishAccess (pDrawable); } else { diff --git a/fb/fbscreen.c b/fb/fbscreen.c index b88375810..045ca8fd2 100644 --- a/fb/fbscreen.c +++ b/fb/fbscreen.c @@ -155,6 +155,19 @@ fbSetupScreen(ScreenPtr pScreen, return TRUE; } +#ifdef FB_ACCESS_WRAPPER +Bool +wfbFinishScreenInit(ScreenPtr pScreen, + pointer pbits, + int xsize, + int ysize, + int dpix, + int dpiy, + int width, + int bpp, + SetupWrapProcPtr setupWrap, + FinishWrapProcPtr finishWrap) +#else Bool fbFinishScreenInit(ScreenPtr pScreen, pointer pbits, @@ -164,6 +177,7 @@ fbFinishScreenInit(ScreenPtr pScreen, int dpiy, int width, int bpp) +#endif { VisualPtr visuals; DepthPtr depths; @@ -222,6 +236,10 @@ fbFinishScreenInit(ScreenPtr pScreen, fbGetScreenPrivate(pScreen)->win32bpp = 32; fbGetScreenPrivate(pScreen)->pix32bpp = 32; } +#ifdef FB_ACCESS_WRAPPER + fbGetScreenPrivate(pScreen)->setupWrap = setupWrap; + fbGetScreenPrivate(pScreen)->finishWrap = finishWrap; +#endif #endif rootdepth = 0; if (!fbInitVisuals (&visuals, &depths, &nvisuals, &ndepths, &rootdepth, @@ -256,6 +274,27 @@ fbFinishScreenInit(ScreenPtr pScreen, } /* dts * (inch/dot) * (25.4 mm / inch) = mm */ +#ifdef FB_ACCESS_WRAPPER +Bool +wfbScreenInit(ScreenPtr pScreen, + pointer pbits, + int xsize, + int ysize, + int dpix, + int dpiy, + int width, + int bpp, + SetupWrapProcPtr setupWrap, + FinishWrapProcPtr finishWrap) +{ + if (!fbSetupScreen(pScreen, pbits, xsize, ysize, dpix, dpiy, width, bpp)) + return FALSE; + if (!wfbFinishScreenInit(pScreen, pbits, xsize, ysize, dpix, dpiy, + width, bpp, setupWrap, finishWrap)) + return FALSE; + return TRUE; +} +#else Bool fbScreenInit(ScreenPtr pScreen, pointer pbits, @@ -273,6 +312,7 @@ fbScreenInit(ScreenPtr pScreen, return FALSE; return TRUE; } +#endif #ifdef FB_OLD_SCREEN diff --git a/fb/fbseg.c b/fb/fbseg.c index d66e42468..31076379b 100644 --- a/fb/fbseg.c +++ b/fb/fbseg.c @@ -79,7 +79,7 @@ fbBresSolid (DrawablePtr pDrawable, mask = fbBresShiftMask(mask,signdx,dstBpp); if (!mask) { - *dst = FbDoMaskRRop (*dst, and, xor, bits); + WRITE(dst, FbDoMaskRRop (READ(dst), and, xor, bits)); bits = 0; dst += signdx; mask = mask0; @@ -87,20 +87,20 @@ fbBresSolid (DrawablePtr pDrawable, e += e1; if (e >= 0) { - *dst = FbDoMaskRRop (*dst, and, xor, bits); + WRITE(dst, FbDoMaskRRop (READ(dst), and, xor, bits)); bits = 0; dst += dstStride; e += e3; } } if (bits) - *dst = FbDoMaskRRop (*dst, and, xor, bits); + WRITE(dst, FbDoMaskRRop (READ(dst), and, xor, bits)); } else { while (len--) { - *dst = FbDoMaskRRop (*dst, and, xor, mask); + WRITE(dst, FbDoMaskRRop (READ(dst), and, xor, mask)); dst += dstStride; e += e1; if (e >= 0) @@ -115,6 +115,8 @@ fbBresSolid (DrawablePtr pDrawable, } } } + + fbFinishAccess (pDrawable); } void @@ -164,9 +166,9 @@ fbBresDash (DrawablePtr pDrawable, while (len--) { if (even) - *dst = FbDoMaskRRop (*dst, and, xor, mask); + WRITE(dst, FbDoMaskRRop (READ(dst), and, xor, mask)); else if (doOdd) - *dst = FbDoMaskRRop (*dst, bgand, bgxor, mask); + WRITE(dst, FbDoMaskRRop (READ(dst), bgand, bgxor, mask)); if (axis == X_AXIS) { mask = fbBresShiftMask(mask,signdx,dstBpp); @@ -199,6 +201,8 @@ fbBresDash (DrawablePtr pDrawable, } FbDashStep (dashlen, even); } + + fbFinishAccess (pDrawable); } void @@ -371,13 +375,13 @@ fbBresSolid24RRop (DrawablePtr pDrawable, FbMaskStip (x, 24, leftMask, nl, rightMask); if (leftMask) { - *d = FbDoMaskRRop (*d, andT, xorT, leftMask); + WRITE(d, FbDoMaskRRop (READ(d), andT, xorT, leftMask)); d++; andT = FbNext24Stip (andT); xorT = FbNext24Stip (xorT); } if (rightMask) - *d = FbDoMaskRRop (*d, andT, xorT, rightMask); + WRITE(d, FbDoMaskRRop (READ(d), andT, xorT, rightMask)); if (axis == X_AXIS) { x1 += signdx; @@ -399,6 +403,8 @@ fbBresSolid24RRop (DrawablePtr pDrawable, } } } + + fbFinishAccess (pDrawable); } static void @@ -468,13 +474,13 @@ fbBresDash24RRop (DrawablePtr pDrawable, FbMaskStip (x, 24, leftMask, nl, rightMask); if (leftMask) { - *d = FbDoMaskRRop (*d, andT, xorT, leftMask); + WRITE(d, FbDoMaskRRop (READ(d), andT, xorT, leftMask)); d++; andT = FbNext24Stip (andT); xorT = FbNext24Stip (xorT); } if (rightMask) - *d = FbDoMaskRRop (*d, andT, xorT, rightMask); + WRITE(d, FbDoMaskRRop (READ(d), andT, xorT, rightMask)); } if (axis == X_AXIS) { @@ -498,6 +504,8 @@ fbBresDash24RRop (DrawablePtr pDrawable, } FbDashStep (dashlen, even); } + + fbFinishAccess (pDrawable); } #endif diff --git a/fb/fbsetsp.c b/fb/fbsetsp.c index c59c13ceb..06332568b 100644 --- a/fb/fbsetsp.c +++ b/fb/fbsetsp.c @@ -99,5 +99,6 @@ fbSetSpans (DrawablePtr pDrawable, pwidth++; } fbValidateDrawable (pDrawable); + fbFinishAccess (pDrawable); } diff --git a/fb/fbsolid.c b/fb/fbsolid.c index 89effe63b..6b5ed0fa1 100644 --- a/fb/fbsolid.c +++ b/fb/fbsolid.c @@ -70,12 +70,12 @@ fbSolid (FbBits *dst, n = nmiddle; if (!and) while (n--) - *dst++ = xor; + WRITE(dst++, xor); else while (n--) { - *dst = FbDoRRop (*dst, and, xor); - dst++; + WRITE(dst, FbDoRRop (READ(dst), and, xor)); + dst++; } if (endmask) FbDoRightMaskByteRRop(dst,endbyte,endmask,and,xor); @@ -160,26 +160,26 @@ fbSolid24 (FbBits *dst, { if (startmask) { - *dst = FbDoMaskRRop(*dst, andS, xorS, startmask); - dst++; + WRITE(dst, FbDoMaskRRop(READ(dst), andS, xorS, startmask)); + dst++; } n = nmiddle; if (!and0) { while (n >= 3) { - *dst++ = xor0; - *dst++ = xor1; - *dst++ = xor2; + WRITE(dst++, xor0); + WRITE(dst++, xor1); + WRITE(dst++, xor2); n -= 3; } if (n) { - *dst++ = xor0; + WRITE(dst++, xor0); n--; if (n) { - *dst++ = xor1; + WRITE(dst++, xor1); } } } @@ -187,28 +187,28 @@ fbSolid24 (FbBits *dst, { while (n >= 3) { - *dst = FbDoRRop (*dst, and0, xor0); - dst++; - *dst = FbDoRRop (*dst, and1, xor1); - dst++; - *dst = FbDoRRop (*dst, and2, xor2); - dst++; + WRITE(dst, FbDoRRop (READ(dst), and0, xor0)); + dst++; + WRITE(dst, FbDoRRop (READ(dst), and1, xor1)); + dst++; + WRITE(dst, FbDoRRop (READ(dst), and2, xor2)); + dst++; n -= 3; } if (n) { - *dst = FbDoRRop (*dst, and0, xor0); - dst++; + WRITE(dst, FbDoRRop (READ(dst), and0, xor0)); + dst++; n--; if (n) { - *dst = FbDoRRop (*dst, and1, xor1); - dst++; + WRITE(dst, FbDoRRop (READ(dst), and1, xor1)); + dst++; } } } if (endmask) - *dst = FbDoMaskRRop (*dst, andE, xorE, endmask); + WRITE(dst, FbDoMaskRRop (READ(dst), andE, xorE, endmask)); dst += dstStride; } } diff --git a/fb/fbstipple.c b/fb/fbstipple.c index ce971481e..de8d1f814 100644 --- a/fb/fbstipple.c +++ b/fb/fbstipple.c @@ -155,7 +155,7 @@ fbEvenStipple (FbBits *dst, /* * Extract stipple bits for this scanline; */ - bits = *s; + bits = READ(s); s += stipStride; if (s == stipEnd) s = stip; @@ -199,12 +199,12 @@ fbEvenStipple (FbBits *dst, n = nmiddle; if (!and) while (n--) - *dst++ = xor; + WRITE(dst++, xor); else { while (n--) { - *dst = FbDoRRop (*dst, and, xor); + WRITE(dst, FbDoRRop (READ(dst), and, xor)); dst++; } } diff --git a/fb/fbtile.c b/fb/fbtile.c index 0d0cfe174..e7df1af5a 100644 --- a/fb/fbtile.c +++ b/fb/fbtile.c @@ -80,7 +80,7 @@ fbEvenTile (FbBits *dst, /* * Pick up bits for this scanline */ - bits = *t++; + bits = READ(t++); if (t == tileEnd) t = tile; bits = FbRotLeft(bits,rot); and = fbAnd(alu,bits,pm); @@ -94,11 +94,11 @@ fbEvenTile (FbBits *dst, n = nmiddle; if (!and) while (n--) - *dst++ = xor; + WRITE(dst++, xor); else while (n--) { - *dst = FbDoRRop (*dst, and, xor); + WRITE(dst, FbDoRRop (READ(dst), and, xor)); dst++; } if (endmask) diff --git a/fb/fbtrap.c b/fb/fbtrap.c index 863969527..4c67bcdfb 100644 --- a/fb/fbtrap.c +++ b/fb/fbtrap.c @@ -95,6 +95,8 @@ fbAddTraps (PicturePtr pPicture, } traps++; } + + fbFinishAccess (pPicture->pDrawable); } void @@ -142,6 +144,8 @@ fbRasterizeTrapezoid (PicturePtr pPicture, fbRasterizeEdges (buf, bpp, width, stride, &l, &r, t, b); } + + fbFinishAccess (pPicture->pDrawable); } static int diff --git a/fb/fbwindow.c b/fb/fbwindow.c index 968b5a61d..cac662cc7 100644 --- a/fb/fbwindow.c +++ b/fb/fbwindow.c @@ -118,6 +118,9 @@ fbCopyWindowProc (DrawablePtr pSrcDrawable, upsidedown); pbox++; } + + fbFinishAccess (pDstDrawable); + fbFinishAccess (pSrcDrawable); } void @@ -249,6 +252,8 @@ fbFillRegionSolid (DrawablePtr pDrawable, fbValidateDrawable (pDrawable); pbox++; } + + fbFinishAccess (pDrawable); } #ifdef PANORAMIX @@ -311,6 +316,9 @@ fbFillRegionTiled (DrawablePtr pDrawable, yRot - (pbox->y1 + dstYoff)); pbox++; } + + fbFinishAccess (&pTile->drawable); + fbFinishAccess (pDrawable); } void diff --git a/fb/wfbrename.h b/fb/wfbrename.h new file mode 100644 index 000000000..8f875c88b --- /dev/null +++ b/fb/wfbrename.h @@ -0,0 +1,198 @@ +#define fb16Lane wfb16Lane +#define fb24_32CopyMtoN wfb24_32CopyMtoN +#define fb24_32CreateScreenResources wfb24_32CreateScreenResources +#define fb24_32GetImage wfb24_32GetImage +#define fb24_32GetSpans wfb24_32GetSpans +#define fb24_32ModifyPixmapHeader wfb24_32ModifyPixmapHeader +#define fb24_32PutZImage wfb24_32PutZImage +#define fb24_32ReformatTile wfb24_32ReformatTile +#define fb24_32SetSpans wfb24_32SetSpans +#define fb32Lane wfb32Lane +#define fb8Lane wfb8Lane +#define fbAddTraps wfbAddTraps +#define fbAddTriangles wfbAddTriangles +#define fbAllocatePrivates wfbAllocatePrivates +#define fbArc16 wfbArc16 +#define fbArc24 wfbArc24 +#define fbArc32 wfbArc32 +#define fbArc8 wfbArc8 +#define fbBlt wfbBlt +#define fbBlt24 wfbBlt24 +#define fbBltOne wfbBltOne +#define fbBltOne24 wfbBltOne24 +#define fbBltPlane wfbBltPlane +#define fbBltStip wfbBltStip +#define fbBres wfbBres +#define fbBresDash wfbBresDash +#define fbBresDash16 wfbBresDash16 +#define fbBresDash24 wfbBresDash24 +#define fbBresDash32 wfbBresDash32 +#define fbBresDash8 wfbBresDash8 +#define fbBresFill wfbBresFill +#define fbBresFillDash wfbBresFillDash +#define fbBresSolid wfbBresSolid +#define fbBresSolid16 wfbBresSolid16 +#define fbBresSolid24 wfbBresSolid24 +#define fbBresSolid32 wfbBresSolid32 +#define fbBresSolid8 wfbBresSolid8 +#define fbChangeWindowAttributes wfbChangeWindowAttributes +#define fbClearVisualTypes wfbClearVisualTypes +#define fbCloseScreen wfbCloseScreen +#define fbComposite wfbComposite +#define fbCompositeGeneral wfbCompositeGeneral +#define fbCompositeSolidMask_nx1xn wfbCompositeSolidMask_nx1xn +#define fbCompositeSolidMask_nx8888x0565C wfbCompositeSolidMask_nx8888x0565C +#define fbCompositeSolidMask_nx8888x8888C wfbCompositeSolidMask_nx8888x8888C +#define fbCompositeSolidMask_nx8x0565 wfbCompositeSolidMask_nx8x0565 +#define fbCompositeSolidMask_nx8x0888 wfbCompositeSolidMask_nx8x0888 +#define fbCompositeSolidMask_nx8x8888 wfbCompositeSolidMask_nx8x8888 +#define fbCompositeSrc_0565x0565 wfbCompositeSrc_0565x0565 +#define fbCompositeSrc_8888x0565 wfbCompositeSrc_8888x0565 +#define fbCompositeSrc_8888x0888 wfbCompositeSrc_8888x0888 +#define fbCompositeSrc_8888x8888 wfbCompositeSrc_8888x8888 +#define fbCompositeSrcAdd_1000x1000 wfbCompositeSrcAdd_1000x1000 +#define fbCompositeSrcAdd_8000x8000 wfbCompositeSrcAdd_8000x8000 +#define fbCompositeSrcAdd_8888x8888 wfbCompositeSrcAdd_8888x8888 +#define fbCopy1toN wfbCopy1toN +#define fbCopyArea wfbCopyArea +#define fbCopyNto1 wfbCopyNto1 +#define fbCopyNtoN wfbCopyNtoN +#define fbCopyPlane wfbCopyPlane +#define fbCopyRegion wfbCopyRegion +#define fbCopyWindow wfbCopyWindow +#define fbCopyWindowProc wfbCopyWindowProc +#define fbCreateDefColormap wfbCreateDefColormap +#define fbCreateGC wfbCreateGC +#define fbCreatePixmap wfbCreatePixmap +#define fbCreatePixmapBpp wfbCreatePixmapBpp +#define fbCreateWindow wfbCreateWindow +#define fbDestroyPixmap wfbDestroyPixmap +#define fbDestroyWindow wfbDestroyWindow +#define fbDoCopy wfbDoCopy +#define fbDots wfbDots +#define fbDots16 wfbDots16 +#define fbDots24 wfbDots24 +#define fbDots32 wfbDots32 +#define fbDots8 wfbDots8 +#define fbEvenStipple wfbEvenStipple +#define fbEvenTile wfbEvenTile +#define fbExpandDirectColors wfbExpandDirectColors +#define fbFill wfbFill +#define fbFillRegionSolid wfbFillRegionSolid +#define fbFillRegionTiled wfbFillRegionTiled +#define fbFillSpans wfbFillSpans +#define fbFixCoordModePrevious wfbFixCoordModePrevious +#define fbGCFuncs wfbGCFuncs +#define fbGCOps wfbGCOps +#define fbGCPrivateIndex wfbGCPrivateIndex +#define fbGeneration wfbGeneration +#define fbGetGCPrivateIndex wfbGetGCPrivateIndex +#define fbGetImage wfbGetImage +#define fbGetScreenPrivateIndex wfbGetScreenPrivateIndex +#define fbGetSpans wfbGetSpans +#define _fbGetWindowPixmap _wfbGetWindowPixmap +#define fbGetWinPrivateIndex wfbGetWinPrivateIndex +#define fbGlyph16 wfbGlyph16 +#define fbGlyph24 wfbGlyph24 +#define fbGlyph32 wfbGlyph32 +#define fbGlyph8 wfbGlyph8 +#define fbGlyphIn wfbGlyphIn +#define fbHasVisualTypes wfbHasVisualTypes +#define fbImageGlyphBlt wfbImageGlyphBlt +#define fbIn wfbIn +#define fbInitializeColormap wfbInitializeColormap +#define fbInitVisuals wfbInitVisuals +#define fbInstallColormap wfbInstallColormap +#define fbLaneTable wfbLaneTable +#define fbListInstalledColormaps wfbListInstalledColormaps +#define fbMapWindow wfbMapWindow +#define FbMergeRopBits wFbMergeRopBits +#define fbOddStipple wfbOddStipple +#define fbOddTile wfbOddTile +#define fbOver wfbOver +#define fbOver24 wfbOver24 +#define fbOverlayCloseScreen wfbOverlayCloseScreen +#define fbOverlayCopyWindow wfbOverlayCopyWindow +#define fbOverlayCreateScreenResources wfbOverlayCreateScreenResources +#define fbOverlayCreateWindow wfbOverlayCreateWindow +#define fbOverlayFinishScreenInit wfbOverlayFinishScreenInit +#define fbOverlayGeneration wfbOverlayGeneration +#define fbOverlayGetScreenPrivateIndex wfbOverlayGetScreenPrivateIndex +#define fbOverlayPaintKey wfbOverlayPaintKey +#define fbOverlayPaintWindow wfbOverlayPaintWindow +#define fbOverlayScreenPrivateIndex wfbOverlayScreenPrivateIndex +#define fbOverlaySetupScreen wfbOverlaySetupScreen +#define fbOverlayUpdateLayerRegion wfbOverlayUpdateLayerRegion +#define fbOverlayWindowExposures wfbOverlayWindowExposures +#define fbOverlayWindowLayer wfbOverlayWindowLayer +#define fbPadPixmap wfbPadPixmap +#define fbPaintWindow wfbPaintWindow +#define fbPictureInit wfbPictureInit +#define fbPixmapToRegion wfbPixmapToRegion +#define fbPolyArc wfbPolyArc +#define fbPolyFillRect wfbPolyFillRect +#define fbPolyGlyphBlt wfbPolyGlyphBlt +#define fbPolyLine wfbPolyLine +#define fbPolyline16 wfbPolyline16 +#define fbPolyline24 wfbPolyline24 +#define fbPolyline32 wfbPolyline32 +#define fbPolyline8 wfbPolyline8 +#define fbPolyPoint wfbPolyPoint +#define fbPolySegment wfbPolySegment +#define fbPolySegment16 wfbPolySegment16 +#define fbPolySegment24 wfbPolySegment24 +#define fbPolySegment32 wfbPolySegment32 +#define fbPolySegment8 wfbPolySegment8 +#define fbPositionWindow wfbPositionWindow +#define fbPushFill wfbPushFill +#define fbPushImage wfbPushImage +#define fbPushPattern wfbPushPattern +#define fbPushPixels wfbPushPixels +#define fbPutImage wfbPutImage +#define fbPutXYImage wfbPutXYImage +#define fbPutZImage wfbPutZImage +#define fbQueryBestSize wfbQueryBestSize +#define fbRasterizeEdges wfbRasterizeEdges +#define fbRasterizeTrapezoid wfbRasterizeTrapezoid +#define fbRealizeFont wfbRealizeFont +#define fbReduceRasterOp wfbReduceRasterOp +#define fbReplicatePixel wfbReplicatePixel +#define fbResolveColor wfbResolveColor +#define fbRestoreAreas wfbRestoreAreas +#define fbSaveAreas wfbSaveAreas +#define fbScreenPrivateIndex wfbScreenPrivateIndex +#define fbSegment wfbSegment +#define fbSelectBres wfbSelectBres +#define fbSetSpans wfbSetSpans +#define fbSetupScreen wfbSetupScreen +#define fbSetVisualTypes wfbSetVisualTypes +#define fbSetVisualTypesAndMasks wfbSetVisualTypesAndMasks +#define _fbSetWindowPixmap _wfbSetWindowPixmap +#define fbSolid wfbSolid +#define fbSolid24 wfbSolid24 +#define fbSolidBoxClipped wfbSolidBoxClipped +#define fbStipple wfbStipple +#define fbStipple1Bits wfbStipple1Bits +#define fbStipple24Bits wfbStipple24Bits +#define fbStipple2Bits wfbStipple2Bits +#define fbStipple4Bits wfbStipple4Bits +#define fbStipple8Bits wfbStipple8Bits +#define fbStippleTable wfbStippleTable +#define fbTile wfbTile +#define fbTransparentSpan wfbTransparentSpan +#define fbUninstallColormap wfbUninstallColormap +#define fbUnmapWindow wfbUnmapWindow +#define fbUnrealizeFont wfbUnrealizeFont +#define fbValidateGC wfbValidateGC +#define fbWinPrivateIndex wfbWinPrivateIndex +#define fbZeroLine wfbZeroLine +#define fbZeroSegment wfbZeroSegment +#define xxScrPrivateIndex wfbxxScrPrivateIndex +#define xxGCPrivateIndex wfbxxGCPrivateIndex +#define xxColormapPrivateIndex wfbxxColormapPrivateIndex +#define xxGeneration wfbxxGeneration +#define xxPrintVisuals wfbxxPrintVisuals +#define xxGCFuncs wfbxxGCFuncs +#define xxGCOps wfbxxGCOps +#define xxSetup wfbxxSetup +#define composeFunctions wfbComposeFunctions diff --git a/hw/dmx/Makefile.am b/hw/dmx/Makefile.am index 81b62f1fe..89136b904 100644 --- a/hw/dmx/Makefile.am +++ b/hw/dmx/Makefile.am @@ -16,6 +16,9 @@ GLX_INCS = -I$(top_srcdir)/hw/xfree86/dixmods/extmod \ GLX_DEFS = @GL_CFLAGS@ endif +# It's essential that fbcmap.c be compiled with this flag for DMX to work!! +DMX_CFLAGS = -DXFree86Server=1 + if BUILDDOCS SUBDIRS += doc endif @@ -83,8 +86,10 @@ Xdmx_LDADD = $(XORG_CORE_LIBS) \ Xdmx_CFLAGS = \ -DHAVE_DMX_CONFIG_H \ + $(DIX_CFLAGS) \ $(GLX_INCS) \ $(GLX_DEFS) \ + $(DMX_CFLAGS) \ @DMXMODULES_CFLAGS@ # Man page diff --git a/hw/dmx/dmx.h b/hw/dmx/dmx.h index 18e75de90..becb2da38 100644 --- a/hw/dmx/dmx.h +++ b/hw/dmx/dmx.h @@ -51,6 +51,10 @@ #ifndef DMX_H #define DMX_H +#if HAVE_DMX_CONFIG_H +#include +#endif + #include "gcstruct.h" /* Handle client-side include files in one place. */ diff --git a/hw/dmx/dmxcmap.c b/hw/dmx/dmxcmap.c index b4279e7ce..9a9781f53 100644 --- a/hw/dmx/dmxcmap.c +++ b/hw/dmx/dmxcmap.c @@ -40,6 +40,7 @@ #endif #include "dmx.h" +#include "dmxlog.h" #include "dmxsync.h" #include "dmxcmap.h" #include "dmxvisual.h" @@ -83,12 +84,18 @@ Bool dmxBECreateColormap(ColormapPtr pColormap) VisualPtr pVisual = pColormap->pVisual; Visual *visual = dmxLookupVisual(pScreen, pVisual); - pCmapPriv->cmap = XCreateColormap(dmxScreen->beDisplay, - dmxScreen->scrnWin, - visual, - (pVisual->class & DynamicClass ? - AllocAll : AllocNone)); - return (pCmapPriv->cmap != 0); + if (visual) { + pCmapPriv->cmap = XCreateColormap(dmxScreen->beDisplay, + dmxScreen->scrnWin, + visual, + (pVisual->class & DynamicClass ? + AllocAll : AllocNone)); + return (pCmapPriv->cmap != 0); + } + else { + dmxLog(dmxWarning, "dmxBECreateColormap: No visual found\n"); + return 0; + } } /** Create colormap on back-end server associated with \a pColormap's diff --git a/hw/dmx/dmxcursor.c b/hw/dmx/dmxcursor.c index a49fc9f43..e74a05215 100644 --- a/hw/dmx/dmxcursor.c +++ b/hw/dmx/dmxcursor.c @@ -664,8 +664,8 @@ static Bool _dmxUnrealizeCursor(ScreenPtr pScreen, CursorPtr pCursor) { DMXScreenInfo *dmxScreen = &dmxScreens[pScreen->myNum]; - DMXDBG3("_dmxUnrealizeCursor(%d,%p) %p\n", - pScreen->myNum, pCursor, pCursorPriv); + DMXDBG2("_dmxUnrealizeCursor(%d,%p)\n", + pScreen->myNum, pCursor); if (dmxScreen->beDisplay) { if (dmxBEFreeCursor(pScreen, pCursor)) diff --git a/hw/kdrive/ati/Makefile.am b/hw/kdrive/ati/Makefile.am index b23418129..3732d7d72 100644 --- a/hw/kdrive/ati/Makefile.am +++ b/hw/kdrive/ati/Makefile.am @@ -31,10 +31,6 @@ INCLUDES = \ bin_PROGRAMS = Xati -if TSLIB -TSLIB_FLAG = -lts -endif - noinst_LIBRARIES = libati.a libati_a_SOURCES = \ @@ -65,8 +61,12 @@ ATI_LIBS = \ Xati_LDADD = \ $(ATI_LIBS) \ @KDRIVE_LIBS@ \ - @XSERVER_LIBS@ \ - $(TSLIB_FLAG) + @XSERVER_LIBS@ -Xati_DEPENDENCIES = $(ATI_LIBS) +Xati_DEPENDENCIES = \ + libati.a \ + $(FBDEV_LIBS) \ + $(VESA_LIBS) \ + $(DRI_LIBS) + diff --git a/hw/kdrive/chips/Makefile.am b/hw/kdrive/chips/Makefile.am index e3080774b..80fb2ddea 100644 --- a/hw/kdrive/chips/Makefile.am +++ b/hw/kdrive/chips/Makefile.am @@ -5,10 +5,6 @@ INCLUDES = \ bin_PROGRAMS = Xchips -if TSLIB -TSLIB_FLAG = -lts -endif - noinst_LIBRARIES = libchips.a libchips_a_SOURCES = \ @@ -19,15 +15,16 @@ libchips_a_SOURCES = \ Xchips_SOURCES = \ chipsstub.c -CHIPS_LIBS = \ - libchips.a \ +CHIPS_LIBS = \ + libchips.a \ $(top_builddir)/hw/kdrive/vesa/libvesa.a \ @KDRIVE_LIBS@ Xchips_LDADD = \ $(CHIPS_LIBS) \ - @KDRIVE_LIBS@ \ - @XSERVER_LIBS@ \ - $(TSLIB_FLAG) + @KDRIVE_LIBS@ \ + @XSERVER_LIBS@ -Xchips_DEPENDENCIES = $(CHIPS_LIBS) @KDRIVE_LIBS@ +Xchips_DEPENDENCIES = \ + libchips.a \ + $(top_builddir)/hw/kdrive/vesa/libvesa.a diff --git a/hw/kdrive/ephyr/Makefile.am b/hw/kdrive/ephyr/Makefile.am index f423bfe40..8f51bbe08 100644 --- a/hw/kdrive/ephyr/Makefile.am +++ b/hw/kdrive/ephyr/Makefile.am @@ -5,11 +5,6 @@ INCLUDES = \ noinst_LIBRARIES = libxephyr.a libxephyr-hostx.a -if TSLIB -TSLIB_LIBS = -lts -endif - - bin_PROGRAMS = Xephyr libxephyr_a_SOURCES = \ @@ -34,11 +29,8 @@ Xephyr_LDADD = \ ../../../exa/libexa.la \ @KDRIVE_LIBS@ \ @KDRIVE_LIBS@ \ - $(TSLIB_LIBS) \ @XEPHYR_LIBS@ Xephyr_DEPENDENCIES = \ libxephyr.a \ - libxephyr-hostx.a \ - @KDRIVE_LIBS@ \ - ../../../exa/libexa.la + libxephyr-hostx.a diff --git a/hw/kdrive/epson/Makefile.am b/hw/kdrive/epson/Makefile.am index 0538f4c39..665d13651 100644 --- a/hw/kdrive/epson/Makefile.am +++ b/hw/kdrive/epson/Makefile.am @@ -4,10 +4,6 @@ INCLUDES = \ bin_PROGRAMS = Xepson -if TSLIB -TSLIB_FLAG = -lts -endif - noinst_LIBRARIES = libepson.a libepson_a_SOURCES = \ @@ -25,9 +21,8 @@ EPSON_LIBS = \ @KDRIVE_LIBS@ Xepson_LDADD = \ - $(EPSON_LIBS) \ + $(EPSON_LIBS) \ @KDRIVE_LIBS@ \ - @XSERVER_LIBS@ \ - $(TSLIB_FLAG) + @XSERVER_LIBS@ -Xepson_DEPENDENCIES = $(EPSON_LIBS) @KDRIVE_LIBS@ +Xepson_DEPENDENCIES = libepson.a diff --git a/hw/kdrive/fake/Makefile.am b/hw/kdrive/fake/Makefile.am index f3a6a3453..3a53e3dbb 100644 --- a/hw/kdrive/fake/Makefile.am +++ b/hw/kdrive/fake/Makefile.am @@ -28,6 +28,4 @@ Xfake_LDADD = \ @XSERVER_LIBS@ Xfake_DEPENDENCIES = \ - libfake.a \ - @KDRIVE_LIBS@ - + libfake.a diff --git a/hw/kdrive/fbdev/Makefile.am b/hw/kdrive/fbdev/Makefile.am index fce6df9f4..3a8c65bbb 100644 --- a/hw/kdrive/fbdev/Makefile.am +++ b/hw/kdrive/fbdev/Makefile.am @@ -6,10 +6,6 @@ noinst_LIBRARIES = libfbdev.a bin_PROGRAMS = Xfbdev -if TSLIB -TSLIB_FLAG = -lts -endif - libfbdev_a_SOURCES = \ fbdev.c \ fbdev.h @@ -20,10 +16,7 @@ Xfbdev_SOURCES = \ Xfbdev_LDADD = \ libfbdev.a \ @KDRIVE_LIBS@ \ - @XSERVER_LIBS@ \ - $(TSLIB_FLAG) + @XSERVER_LIBS@ Xfbdev_DEPENDENCIES = \ - libfbdev.a \ - @KDRIVE_LIBS@ - + libfbdev.a diff --git a/hw/kdrive/fbdev/fbdev.c b/hw/kdrive/fbdev/fbdev.c index 86384f0a4..20bf75800 100644 --- a/hw/kdrive/fbdev/fbdev.c +++ b/hw/kdrive/fbdev/fbdev.c @@ -33,16 +33,24 @@ extern int KdTsPhyScreen; +char *fbdevDevicePath = NULL; + Bool fbdevInitialize (KdCardInfo *card, FbdevPriv *priv) { int k; unsigned long off; - if ((priv->fd = open("/dev/fb0", O_RDWR)) < 0 && \ - (priv->fd = open("/dev/fb/0", O_RDWR)) < 0) { - perror("Error opening /dev/fb0"); - return FALSE; - } + + if (fbdevDevicePath == NULL) + fbdevDevicePath = "/dev/fb0"; + + if ((priv->fd = open(fbdevDevicePath, O_RDWR)) < 0) + { + ErrorF("Error opening framebuffer %s: %s\n", + fbdevDevicePath, strerror(errno)); + return FALSE; + } + /* quiet valgrind */ memset (&priv->fix, '\0', sizeof (priv->fix)); if ((k=ioctl(priv->fd, FBIOGET_FSCREENINFO, &priv->fix)) < 0) { diff --git a/hw/kdrive/fbdev/fbdev.h b/hw/kdrive/fbdev/fbdev.h index d37b99597..b7951db72 100644 --- a/hw/kdrive/fbdev/fbdev.h +++ b/hw/kdrive/fbdev/fbdev.h @@ -53,6 +53,7 @@ typedef struct _fbdevScrPriv { } FbdevScrPriv; extern KdCardFuncs fbdevFuncs; +extern char* fbdevDevicePath; Bool fbdevInitialize (KdCardInfo *card, FbdevPriv *priv); diff --git a/hw/kdrive/fbdev/fbinit.c b/hw/kdrive/fbdev/fbinit.c index ba9d1c695..ee373276b 100644 --- a/hw/kdrive/fbdev/fbinit.c +++ b/hw/kdrive/fbdev/fbinit.c @@ -54,15 +54,28 @@ InitInput (int argc, char **argv) void ddxUseMsg (void) { - KdUseMsg(); + KdUseMsg(); + ErrorF("\nXfbdev Device Usage:\n"); + ErrorF("-fb path Framebuffer device to use. Defaults to /dev/fb0\n"); + ErrorF("\n"); } int ddxProcessArgument (int argc, char **argv, int i) { - return KdProcessArgument (argc, argv, i); -} + if (!strcmp (argv[i], "-fb")) + { + if (i+1 < argc) + { + fbdevDevicePath = argv[i+1]; + return 2; + } + UseMsg(); + exit(1); + } + return KdProcessArgument (argc, argv, i); +} KdCardFuncs fbdevFuncs = { diff --git a/hw/kdrive/i810/Makefile.am b/hw/kdrive/i810/Makefile.am index d676a6902..808d8f70b 100644 --- a/hw/kdrive/i810/Makefile.am +++ b/hw/kdrive/i810/Makefile.am @@ -6,9 +6,6 @@ bin_PROGRAMS = Xi810 noinst_LIBRARIES = libi810.a -if TSLIB -TSLIB_FLAG = -lts -endif libi810_a_SOURCES = \ i810_cursor.c \ @@ -29,7 +26,6 @@ I810_LIBS = \ Xi810_LDADD = \ $(I810_LIBS) \ @KDRIVE_LIBS@ \ - @XSERVER_LIBS@ \ - $(TSLIB_FLAG) + @XSERVER_LIBS@ -Xi810_DEPENDENCIES = $(I810_LIBS) @KDRIVE_LIBS@ +Xi810_DEPENDENCIES = libi810.a diff --git a/hw/kdrive/mach64/Makefile.am b/hw/kdrive/mach64/Makefile.am index 299565fdb..e924aef71 100644 --- a/hw/kdrive/mach64/Makefile.am +++ b/hw/kdrive/mach64/Makefile.am @@ -34,4 +34,4 @@ Xmach64_LDADD = \ $(TSLIB_FLAG) -Xmach64_DEPENDENCIES = $(MACH64_LIBS) @KDRIVE_LIBS@ +Xmach64_DEPENDENCIES = $(MACH64_LIBS) diff --git a/hw/kdrive/mga/Makefile.am b/hw/kdrive/mga/Makefile.am index 64d260ede..d8ebae920 100644 --- a/hw/kdrive/mga/Makefile.am +++ b/hw/kdrive/mga/Makefile.am @@ -32,4 +32,6 @@ Xmga_LDADD = \ @XSERVER_LIBS@ \ $(TSLIB_FLAG) -Xmga_DEPENDENCIES = $(MGA_LIBS) @KDRIVE_LIBS@ +Xmga_DEPENDENCIES = \ + libmga.a \ + $(top_builddir)/hw/kdrive/vesa/libvesa.a diff --git a/hw/kdrive/neomagic/Makefile.am b/hw/kdrive/neomagic/Makefile.am index b37bfc303..9f8e02919 100644 --- a/hw/kdrive/neomagic/Makefile.am +++ b/hw/kdrive/neomagic/Makefile.am @@ -16,10 +16,6 @@ INCLUDES = \ bin_PROGRAMS = Xneomagic -if TSLIB -TSLIB_FLAG = -lts -endif - noinst_LIBRARIES = libneomagic.a libneomagic_a_SOURCES = \ @@ -41,7 +37,10 @@ NEOMAGIC_LIBS = \ Xneomagic_LDADD = \ $(NEOMAGIC_LIBS) \ @KDRIVE_LIBS@ \ - @XSERVER_LIBS@ \ - $(TSLIB_FLAG) + @XSERVER_LIBS@ -Xneomagic_DEPENDENCIES = $(NEOMAGIC_LIBS) @KDRIVE_LIBS@ + +Xneomagic_DEPENDENCIES = \ + libneomagic.a \ + ${FBDEV_LIBS} \ + ${VESA_LIBS} diff --git a/hw/kdrive/nvidia/Makefile.am b/hw/kdrive/nvidia/Makefile.am index 48551a3a6..d7b26cfa1 100644 --- a/hw/kdrive/nvidia/Makefile.am +++ b/hw/kdrive/nvidia/Makefile.am @@ -30,7 +30,8 @@ NVIDIA_LIBS = \ Xnvidia_LDADD = \ $(NVIDIA_LIBS) \ @KDRIVE_LIBS@ \ - @XSERVER_LIBS@ \ - $(TSLIB_FLAG) + @XSERVER_LIBS@ -Xnvidia_DEPENDENCIES = $(NVIDIA_LIBS) @KDRIVE_LIBS@ +Xnvidia_DEPENDENCIES = \ + libnvidia.a \ + $(top_builddir)/hw/kdrive/vesa/libvesa.a diff --git a/hw/kdrive/pm2/Makefile.am b/hw/kdrive/pm2/Makefile.am index 1a712072a..24ef15042 100644 --- a/hw/kdrive/pm2/Makefile.am +++ b/hw/kdrive/pm2/Makefile.am @@ -5,10 +5,6 @@ INCLUDES = \ bin_PROGRAMS = Xpm2 -if TSLIB -TSLIB_FLAG = -lts -endif - noinst_LIBRARIES = libpm2.a libpm2_a_SOURCES = \ @@ -28,7 +24,9 @@ PM2_LIBS = \ Xpm2_LDADD = \ $(PM2_LIBS) \ @KDRIVE_LIBS@ \ - @XSERVER_LIBS@ \ - $(TSLIB_FLAG) + @XSERVER_LIBS@ -Xpm2_DEPENDENCIES = $(PM2_LIBS) @KDRIVE_LIBS@ + +Xpm2_DEPENDENCIES = \ + libpm2.a \ + $(top_builddir)/hw/kdrive/vesa/libvesa.a diff --git a/hw/kdrive/r128/Makefile.am b/hw/kdrive/r128/Makefile.am index b33e138e1..da42af95f 100644 --- a/hw/kdrive/r128/Makefile.am +++ b/hw/kdrive/r128/Makefile.am @@ -5,10 +5,6 @@ INCLUDES = \ bin_PROGRAMS = Xr128 -if TSLIB -TSLIB_FLAG = -lts -endif - noinst_LIBRARIES = libr128.a libr128_a_SOURCES = \ @@ -27,7 +23,9 @@ R128_LIBS = \ Xr128_LDADD = \ $(R128_LIBS) \ @KDRIVE_LIBS@ \ - @XSERVER_LIBS@ \ - $(TSLIB_FLAG) + @XSERVER_LIBS@ -Xr128_DEPENDENCIES = $(R128_LIBS) @KDRIVE_LIBS@ + +Xr128_DEPENDENCIES = \ + libr128.a \ + $(top_builddir)/hw/kdrive/vesa/libvesa.a diff --git a/hw/kdrive/sdl/Makefile.am b/hw/kdrive/sdl/Makefile.am index ba6ed4d4a..cc3873ca8 100644 --- a/hw/kdrive/sdl/Makefile.am +++ b/hw/kdrive/sdl/Makefile.am @@ -16,5 +16,3 @@ Xsdl_LDADD = @KDRIVE_PURE_LIBS@ \ @XSERVER_LIBS@ \ $(TSLIB_FLAG) \ @XSDL_LIBS@ - -Xsdl_DEPENDENCIES = @KDRIVE_LIBS@ diff --git a/hw/kdrive/sis300/Makefile.am b/hw/kdrive/sis300/Makefile.am index efd1e9ab4..6a6e0bf80 100644 --- a/hw/kdrive/sis300/Makefile.am +++ b/hw/kdrive/sis300/Makefile.am @@ -43,4 +43,4 @@ Xsis_LDADD = \ @KDRIVE_LIBS@ \ $(TSLIB_FLAG) -Xsis_DEPENDENCIES = $(SIS_LIBS) @KDRIVE_LIBS@ +Xsis_DEPENDENCIES = $(SIS_LIBS) diff --git a/hw/kdrive/smi/Makefile.am b/hw/kdrive/smi/Makefile.am index a214e762e..86a9ea947 100644 --- a/hw/kdrive/smi/Makefile.am +++ b/hw/kdrive/smi/Makefile.am @@ -6,10 +6,6 @@ INCLUDES = \ bin_PROGRAMS = Xsmi -if TSLIB -TSLIB_FLAG = -lts -endif - noinst_LIBRARIES = libsmi.a # smivideo.c # not ready yet @@ -32,7 +28,10 @@ SMI_LIBS = \ Xsmi_LDADD = \ $(SMI_LIBS) \ @KDRIVE_LIBS@ \ - @XSERVER_LIBS@ \ - $(TSLIB_FLAG) + @XSERVER_LIBS@ -Xsmi_DEPENDENCIES = $(SMI_LIBS) @KDRIVE_LIBS@ + +Xsmi_DEPENDENCIES = \ + libsmi.a \ + $(top_builddir)/hw/kdrive/fbdev/libfbdev.a \ + $(top_builddir)/hw/kdrive/vesa/libvesa.a diff --git a/hw/kdrive/vesa/Makefile.am b/hw/kdrive/vesa/Makefile.am index 01bc0a3e1..70ba55fa7 100644 --- a/hw/kdrive/vesa/Makefile.am +++ b/hw/kdrive/vesa/Makefile.am @@ -6,11 +6,6 @@ noinst_LIBRARIES = libvesa.a bin_PROGRAMS = Xvesa -if TSLIB -TSLIB_FLAG = -lts -endif - - libvesa_a_SOURCES = \ vesa.c \ vesa.h \ @@ -28,9 +23,7 @@ Xvesa_LDADD = \ libvesa.a \ @KDRIVE_LIBS@ \ @KDRIVE_LIBS@ \ - $(TSLIB_FLAG) \ @XSERVER_LIBS@ Xvesa_DEPENDENCIES = \ - libvesa.a \ - @KDRIVE_LIBS@ + libvesa.a diff --git a/hw/kdrive/via/Makefile.am b/hw/kdrive/via/Makefile.am index 4d52df9b1..7dcfd7c5b 100644 --- a/hw/kdrive/via/Makefile.am +++ b/hw/kdrive/via/Makefile.am @@ -31,4 +31,4 @@ Xvia_LDADD = \ @XSERVER_LIBS@ \ $(TSLIB_FLAG) -Xvia_DEPENDENCIES = $(VIA_LIBS) @KDRIVE_LIBS@ +Xvia_DEPENDENCIES = $(VIA_LIBS) diff --git a/hw/xfree86/Makefile.am b/hw/xfree86/Makefile.am index 830cf2977..e138db88f 100644 --- a/hw/xfree86/Makefile.am +++ b/hw/xfree86/Makefile.am @@ -1,13 +1,19 @@ +include $(top_srcdir)/cpprules.in + if DRI DRI_SUBDIR = dri endif +if XF86UTILS +XF86UTILS_SUBDIR = utils +endif + DOC_SUBDIR = doc SUBDIRS = common ddc dummylib i2c x86emu int10 fbdevhw os-support parser rac \ ramdac shadowfb vbe vgahw xaa xf1bpp xf4bpp xf8_16bpp \ xf8_32bpp loader dixmods exa \ - $(DRI_SUBDIR) utils $(DOC_SUBDIR) + $(DRI_SUBDIR) $(XF86UTILS_SUBDIR) $(DOC_SUBDIR) DIST_SUBDIRS = common ddc dummylib i2c x86emu int10 fbdevhw os-support \ parser rac ramdac shadowfb vbe vgahw xaa xf1bpp xf4bpp \ @@ -78,7 +84,23 @@ endif optionsdir = $(libdir)/X11 dist_options_DATA = Options +BUILT_SOURCES = xorg.conf.example +CLEAN = xorg.conf.example xorg.conf.example.pre EXTRA_DIST = xorgconf.cpp +CPP_FILES_FLAGS = \ + -DRGBPATH=\"$(RGB_DB)\" \ + -DLOCALFONTPATH="\"$(BASE_FONT_PATH)/local\"" \ + -DMISCFONTPATH="\"$(BASE_FONT_PATH)/misc\"" \ + -DT1FONTPATH="\"$(BASE_FONT_PATH)/Type1\"" \ + -DTRUETYPEFONTPATH="\"$(BASE_FONT_PATH)/TTF\"" \ + -DCIDFONTPATH="\"$(BASE_FONT_PATH)/CID\"" \ + -DDPI75FONTPATH="\"$(BASE_FONT_PATH)/75dpi\"" \ + -DDPI100FONTPATH="\"$(BASE_FONT_PATH)/100dpi\"" \ + -DMODULEPATH=\"$(DEFAULT_MODULE_PATH)\" + relink: rm -f Xorg && $(MAKE) Xorg + +xorg.conf.example.pre: xorgconf.cpp + cp $< $@ diff --git a/hw/xfree86/common/xf86.h b/hw/xfree86/common/xf86.h index 6e97295d0..7da1fc29e 100644 --- a/hw/xfree86/common/xf86.h +++ b/hw/xfree86/common/xf86.h @@ -36,6 +36,12 @@ #ifndef _XF86_H #define _XF86_H +#if HAVE_XORG_CONFIG_H +#include +#elif HAVE_DIX_CONFIG_H +#include +#endif + #include #include "xf86str.h" diff --git a/hw/xfree86/common/xf86Cursor.c b/hw/xfree86/common/xf86Cursor.c index 61f0ce55e..dcdf46674 100644 --- a/hw/xfree86/common/xf86Cursor.c +++ b/hw/xfree86/common/xf86Cursor.c @@ -234,7 +234,6 @@ xf86SwitchMode(ScreenPtr pScreen, DisplayModePtr mode) xf86EnterServerState(SETUP); Switched = (*pScr->SwitchMode)(pScr->scrnIndex, mode, 0); - xf86EnterServerState(OPERATING); if (Switched) { pScr->currentMode = mode; @@ -269,6 +268,7 @@ xf86SwitchMode(ScreenPtr pScreen, DisplayModePtr mode) pScr->frameY1 = pScr->virtualY - 1; } } + xf86EnterServerState(OPERATING); if (pScr->AdjustFrame) (*pScr->AdjustFrame)(pScr->scrnIndex, pScr->frameX0, pScr->frameY0, 0); diff --git a/hw/xfree86/common/xf86Init.c b/hw/xfree86/common/xf86Init.c index 334754da1..3989570c2 100644 --- a/hw/xfree86/common/xf86Init.c +++ b/hw/xfree86/common/xf86Init.c @@ -1192,11 +1192,6 @@ InitOutput(ScreenInfo *pScreenInfo, int argc, char **argv) #endif } - if ((serverGeneration == 1) && LoaderCheckUnresolved(LD_RESOLV_IFDONE)) { - /* For now, just a warning */ - xf86Msg(X_WARNING, "Some symbols could not be resolved!\n"); - } - xf86PostScreenInit(); xf86InitOrigins(); @@ -1987,8 +1982,8 @@ xf86PrintBanner() "Bugs may be filed in the bugzilla at http://bugs.freedesktop.org/.\n" "Select the \"xorg\" product for bugs you find in this release.\n" "Before reporting bugs in pre-release versions please check the\n" - "latest version in the X.Org Foundation CVS repository.\n" - "See http://wiki.x.org/wiki/CvsPage for CVS access instructions.\n"); + "latest version in the X.Org Foundation git repository.\n" + "See http://wiki.x.org/wiki/GitPage for git access instructions.\n"); #endif ErrorF("\nX Window System Version %d.%d.%d", XORG_VERSION_MAJOR, diff --git a/hw/xfree86/common/xf86Module.h b/hw/xfree86/common/xf86Module.h index f54be49e6..cf404fb89 100644 --- a/hw/xfree86/common/xf86Module.h +++ b/hw/xfree86/common/xf86Module.h @@ -84,7 +84,7 @@ typedef enum { * mask is 0xFFFF0000. */ #define ABI_ANSIC_VERSION SET_ABI_VERSION(0, 3) -#define ABI_VIDEODRV_VERSION SET_ABI_VERSION(1, 0) +#define ABI_VIDEODRV_VERSION SET_ABI_VERSION(1, 1) #define ABI_XINPUT_VERSION SET_ABI_VERSION(0, 6) #define ABI_EXTENSION_VERSION SET_ABI_VERSION(0, 3) #define ABI_FONT_VERSION SET_ABI_VERSION(0, 5) diff --git a/hw/xfree86/common/xf86PciInfo.h b/hw/xfree86/common/xf86PciInfo.h index b8ba73f6a..0630cfa82 100644 --- a/hw/xfree86/common/xf86PciInfo.h +++ b/hw/xfree86/common/xf86PciInfo.h @@ -92,6 +92,7 @@ #define PCI_VENDOR_TRITECH 0x1292 #define PCI_VENDOR_NVIDIA_SGS 0x12D2 #define PCI_VENDOR_VMWARE 0x15AD +#define PCI_VENDOR_AST 0x1A03 #define PCI_VENDOR_3DLABS 0x3D3D #define PCI_VENDOR_AVANCE_2 0x4005 #define PCI_VENDOR_HERCULES 0x4843 @@ -358,6 +359,9 @@ #define PCI_CHIP_RS350_7834 0x7834 #define PCI_CHIP_RS350_7835 0x7835 +/* ASPEED Technology (AST) */ +#define PCI_CHIP_AST2000 0x2000 + /* Avance Logic */ #define PCI_CHIP_ALG2064 0x2064 #define PCI_CHIP_ALG2301 0x2301 diff --git a/hw/xfree86/common/xf86xv.c b/hw/xfree86/common/xf86xv.c index 89cb6bac4..3e908b86a 100644 --- a/hw/xfree86/common/xf86xv.c +++ b/hw/xfree86/common/xf86xv.c @@ -974,6 +974,7 @@ xf86XVEnlistPortInWindow(WindowPtr pWin, XvPortRecPrivatePtr portPriv) if(!winPriv) { winPriv = xalloc(sizeof(XF86XVWindowRec)); if(!winPriv) return BadAlloc; + memset(winPriv, 0, sizeof(XF86XVWindowRec)); winPriv->PortRec = portPriv; winPriv->next = PrivRoot; pWin->devPrivates[XF86XVWindowIndex].ptr = (pointer)winPriv; @@ -1026,6 +1027,9 @@ xf86XVDestroyWindow(WindowPtr pWin) pPriv->pDraw = NULL; tmp = WinPriv; + if(WinPriv->pGC) { + FreeGC(WinPriv->pGC, 0); + } WinPriv = WinPriv->next; xfree(tmp); } @@ -1118,6 +1122,8 @@ xf86XVClipNotify(WindowPtr pWin, int dx, int dy) while(WinPriv) { pPriv = WinPriv->PortRec; + if(!pPriv) goto next; + if(pPriv->pCompositeClip && pPriv->FreeCompositeClip) REGION_DESTROY(pScreen, pPriv->pCompositeClip); @@ -1148,6 +1154,7 @@ xf86XVClipNotify(WindowPtr pWin, int dx, int dy) } } +next: pPrev = WinPriv; WinPriv = WinPriv->next; } @@ -1739,9 +1746,13 @@ xf86XVPutImage( REGION_UNINIT(pScreen, &VPReg); } - if(portPriv->pDraw) { + /* If we are changing windows, unregister our port in the old window */ + if(portPriv->pDraw && (portPriv->pDraw != pDraw)) xf86XVRemovePortFromWindow((WindowPtr)(portPriv->pDraw), portPriv); - } + + /* Register our port with the new window */ + ret = xf86XVEnlistPortInWindow((WindowPtr)pDraw, portPriv); + if(ret != Success) goto PUT_IMAGE_BAILOUT; if(!REGION_NOTEMPTY(pScreen, &ClipRegion)) { clippedAway = TRUE; @@ -1772,7 +1783,6 @@ xf86XVPutImage( if((ret == Success) && (portPriv->AdaptorRec->flags & VIDEO_OVERLAID_IMAGES)) { - xf86XVEnlistPortInWindow((WindowPtr)pDraw, portPriv); portPriv->isOn = XV_ON; portPriv->pDraw = pDraw; portPriv->drw_x = drw_x; portPriv->drw_y = drw_y; @@ -1813,6 +1823,56 @@ xf86XVQueryImageAttributes( format->id, width, height, pitches, offsets); } + +_X_EXPORT void +xf86XVFillKeyHelperDrawable (DrawablePtr pDraw, CARD32 key, RegionPtr clipboxes) +{ + ScreenPtr pScreen = pDraw->pScreen; + WindowPtr pWin = (WindowPtr)pDraw; + XF86XVWindowPtr pPriv = GET_XF86XV_WINDOW(pWin); + GCPtr pGC = NULL; + XID pval[2]; + BoxPtr pbox = REGION_RECTS(clipboxes); + int i, nbox = REGION_NUM_RECTS(clipboxes); + xRectangle *rects; + + if(!xf86Screens[pScreen->myNum]->vtSema) return; + + if(pPriv) + pGC = pPriv->pGC; + + if(!pGC) { + int status; + pval[0] = key; + pval[1] = IncludeInferiors; + pGC = CreateGC(pDraw, GCForeground | GCSubwindowMode, pval, &status); + if(!pGC) return; + ValidateGC(pDraw, pGC); + if (pPriv) pPriv->pGC = pGC; + } else if (key != pGC->fgPixel){ + pval[0] = key; + ChangeGC(pGC, GCForeground, pval); + ValidateGC(pDraw, pGC); + } + + REGION_TRANSLATE(pDraw->pScreen, clipboxes, -pDraw->x, -pDraw->y); + + rects = ALLOCATE_LOCAL(nbox * sizeof(xRectangle)); + + for(i = 0; i < nbox; i++, pbox++) { + rects[i].x = pbox->x1; + rects[i].y = pbox->y1; + rects[i].width = pbox->x2 - pbox->x1; + rects[i].height = pbox->y2 - pbox->y1; + } + + (*pGC->ops->PolyFillRect)(pDraw, pGC, nbox, rects); + + if (!pPriv) FreeGC(pGC, 0); + + DEALLOCATE_LOCAL(rects); +} + _X_EXPORT void xf86XVFillKeyHelper (ScreenPtr pScreen, CARD32 key, RegionPtr clipboxes) { diff --git a/hw/xfree86/common/xf86xv.h b/hw/xfree86/common/xf86xv.h index e0feb57b8..817e2b994 100644 --- a/hw/xfree86/common/xf86xv.h +++ b/hw/xfree86/common/xf86xv.h @@ -232,6 +232,9 @@ void xf86XVFreeVideoAdaptorRec(XF86VideoAdaptorPtr ptr); void xf86XVFillKeyHelper (ScreenPtr pScreen, CARD32 key, RegionPtr clipboxes); +void +xf86XVFillKeyHelperDrawable (DrawablePtr pDraw, CARD32 key, RegionPtr clipboxes); + Bool xf86XVClipVideoHelper( BoxPtr dst, diff --git a/hw/xfree86/common/xf86xvpriv.h b/hw/xfree86/common/xf86xvpriv.h index ced053679..e716c9c6a 100644 --- a/hw/xfree86/common/xf86xvpriv.h +++ b/hw/xfree86/common/xf86xvpriv.h @@ -80,6 +80,7 @@ typedef struct { typedef struct _XF86XVWindowRec{ XvPortRecPrivatePtr PortRec; struct _XF86XVWindowRec *next; + GCPtr pGC; } XF86XVWindowRec, *XF86XVWindowPtr; #endif /* _XF86XVPRIV_H_ */ diff --git a/hw/xfree86/dixmods/Makefile.am b/hw/xfree86/dixmods/Makefile.am index 65dad8a86..c34ddd6e3 100644 --- a/hw/xfree86/dixmods/Makefile.am +++ b/hw/xfree86/dixmods/Makefile.am @@ -18,6 +18,7 @@ module_LTLIBRARIES = libafb.la \ libcfb.la \ libcfb32.la \ libfb.la \ + libwfb.la \ libmfb.la \ libshadow.la @@ -66,6 +67,11 @@ libfb_la_LIBADD = $(top_builddir)/fb/libfb.la libfb_la_SOURCES = $(top_builddir)/fb/fbcmap.c fbmodule.c libfb_la_CFLAGS = -DXFree86Server $(AM_CFLAGS) +libwfb_la_LDFLAGS = -avoid-version +libwfb_la_LIBADD = $(top_builddir)/fb/libwfb.la +libwfb_la_SOURCES = $(top_builddir)/fb/fbcmap.c fbmodule.c +libwfb_la_CFLAGS = -DXFree86Server $(AM_CFLAGS) -DFB_ACCESS_WRAPPER + libglx_la_LDFLAGS = -avoid-version if AIGLX GLXDRI_LIBRARY = $(top_builddir)/GL/glx/libglxdri.la diff --git a/hw/xfree86/dixmods/extmod/modinit.h b/hw/xfree86/dixmods/extmod/modinit.h index bb68bcb9d..41f060b2a 100644 --- a/hw/xfree86/dixmods/extmod/modinit.h +++ b/hw/xfree86/dixmods/extmod/modinit.h @@ -125,7 +125,12 @@ extern void ShmRegisterFuncs( ShmFuncsPtr funcs); #endif +#ifdef XACE +extern void XaceExtensionInit(INITARGS); +#endif + #if 1 +extern void SecurityExtensionSetup(INITARGS); extern void SecurityExtensionInit(INITARGS); #endif diff --git a/hw/xfree86/dixmods/fbmodule.c b/hw/xfree86/dixmods/fbmodule.c index e8e6cd7c6..4df2646dd 100644 --- a/hw/xfree86/dixmods/fbmodule.c +++ b/hw/xfree86/dixmods/fbmodule.c @@ -33,7 +33,11 @@ static XF86ModuleVersionInfo VersRec = { +#ifdef FB_ACCESS_WRAPPER + "wfb", +#else "fb", +#endif MODULEVENDORSTRING, MODINFOSTRING1, MODINFOSTRING2, @@ -45,4 +49,4 @@ static XF86ModuleVersionInfo VersRec = {0,0,0,0} /* signature, to be patched into the file by a tool */ }; -_X_EXPORT XF86ModuleData fbModuleData = { &VersRec, NULL, NULL }; +_X_EXPORT XF86ModuleData FBPREFIX(ModuleData) = { &VersRec, NULL, NULL }; diff --git a/hw/xfree86/doc/man/xorg.conf.man.pre b/hw/xfree86/doc/man/xorg.conf.man.pre index e94804c3b..abf31468a 100644 --- a/hw/xfree86/doc/man/xorg.conf.man.pre +++ b/hw/xfree86/doc/man/xorg.conf.man.pre @@ -1081,7 +1081,7 @@ Include the set of modes listed in the .B Modes section called .IR modesection-id. -This make all of the modes defined in that section available for use by +This makes all of the modes defined in that section available for use by this monitor. .TP 7 .BI "Mode \*q" name \*q diff --git a/hw/xfree86/dri/dri.c b/hw/xfree86/dri/dri.c index 2c9864776..8f604fb98 100644 --- a/hw/xfree86/dri/dri.c +++ b/hw/xfree86/dri/dri.c @@ -992,6 +992,10 @@ DRICreateDrawable(ScreenPtr pScreen, Drawable id, pWin = (WindowPtr)pDrawable; if ((pDRIDrawablePriv = DRI_DRAWABLE_PRIV_FROM_WINDOW(pWin))) { pDRIDrawablePriv->refCount++; + + if (!pDRIDrawablePriv->hwDrawable) { + drmCreateDrawable(pDRIPriv->drmFD, &pDRIDrawablePriv->hwDrawable); + } } else { /* allocate a DRI Window Private record */ @@ -1000,13 +1004,13 @@ DRICreateDrawable(ScreenPtr pScreen, Drawable id, } /* Only create a drm_drawable_t once */ - if (drmCreateDrawable(pDRIPriv->drmFD, hHWDrawable)) { + if (drmCreateDrawable(pDRIPriv->drmFD, + &pDRIDrawablePriv->hwDrawable)) { xfree(pDRIDrawablePriv); return FALSE; } /* add it to the list of DRI drawables for this screen */ - pDRIDrawablePriv->hwDrawable = *hHWDrawable; pDRIDrawablePriv->pScreen = pScreen; pDRIDrawablePriv->refCount = 1; pDRIDrawablePriv->drawableIndex = -1; @@ -1029,6 +1033,15 @@ DRICreateDrawable(ScreenPtr pScreen, Drawable id, /* track this in case this window is destroyed */ AddResource(id, DRIDrawablePrivResType, (pointer)pWin); } + + if (pDRIDrawablePriv->hwDrawable) { + drmUpdateDrawableInfo(pDRIPriv->drmFD, + pDRIDrawablePriv->hwDrawable, + DRM_DRAWABLE_CLIPRECTS, + REGION_NUM_RECTS(&pWin->clipList), + REGION_RECTS(&pWin->clipList)); + *hHWDrawable = pDRIDrawablePriv->hwDrawable; + } } else { /* pixmap (or for GLX 1.3, a PBuffer) */ /* NOT_DONE */ @@ -1813,6 +1826,11 @@ DRIClipNotify(WindowPtr pWin, int dx, int dy) pDRIPriv->pSAREA->drawableTable[pDRIDrawablePriv->drawableIndex].stamp = DRIDrawableValidationStamp++; + + drmUpdateDrawableInfo(pDRIPriv->drmFD, pDRIDrawablePriv->hwDrawable, + DRM_DRAWABLE_CLIPRECTS, + REGION_NUM_RECTS(&pWin->clipList), + REGION_RECTS(&pWin->clipList)); } /* call lower wrapped functions */ diff --git a/hw/xfree86/loader/dixsym.c b/hw/xfree86/loader/dixsym.c index 22fe501f3..27a3093b1 100644 --- a/hw/xfree86/loader/dixsym.c +++ b/hw/xfree86/loader/dixsym.c @@ -162,7 +162,7 @@ _X_HIDDEN void *dixLookupTab[] = { SYMFUNC(QueueWorkProc) SYMFUNC(RegisterBlockAndWakeupHandlers) SYMFUNC(RemoveBlockAndWakeupHandlers) -#ifdef XCSECURITY +#ifdef XACE SYMFUNC(SecurityLookupDrawable) SYMFUNC(SecurityLookupWindow) #endif @@ -255,6 +255,8 @@ _X_HIDDEN void *dixLookupTab[] = { SYMFUNC(GetScratchPixmapHeader) SYMFUNC(FreeScratchPixmapHeader) /* privates.c */ + SYMFUNC(AllocateExtensionPrivate) + SYMFUNC(AllocateExtensionPrivateIndex) SYMFUNC(AllocateClientPrivate) SYMFUNC(AllocateClientPrivateIndex) SYMFUNC(AllocateGCPrivate) @@ -282,10 +284,8 @@ _X_HIDDEN void *dixLookupTab[] = { SYMFUNC(LookupIDByType) SYMFUNC(LookupIDByClass) SYMFUNC(LegalNewID) -#ifdef XCSECURITY SYMFUNC(SecurityLookupIDByClass) SYMFUNC(SecurityLookupIDByType) -#endif SYMFUNC(FindClientResourcesByType) SYMFUNC(FindAllClientResources) SYMVAR(lastResourceType) diff --git a/hw/xfree86/loader/xf86sym.c b/hw/xfree86/loader/xf86sym.c index f001cf5d9..1c3384d9d 100644 --- a/hw/xfree86/loader/xf86sym.c +++ b/hw/xfree86/loader/xf86sym.c @@ -611,6 +611,7 @@ _X_HIDDEN void *xfree86LookupTab[] = { SYMFUNC(xf86XVAllocateVideoAdaptorRec) SYMFUNC(xf86XVFreeVideoAdaptorRec) SYMFUNC(xf86XVFillKeyHelper) + SYMFUNC(xf86XVFillKeyHelperDrawable) SYMFUNC(xf86XVClipVideoHelper) SYMFUNC(xf86XVCopyYUV12ToPacked) SYMFUNC(xf86XVCopyPacked) diff --git a/hw/xfree86/os-support/bus/linuxPci.c b/hw/xfree86/os-support/bus/linuxPci.c index a9db5c887..0a1d16727 100644 --- a/hw/xfree86/os-support/bus/linuxPci.c +++ b/hw/xfree86/os-support/bus/linuxPci.c @@ -71,7 +71,13 @@ static pciBusFuncs_t linuxFuncs0 = { /* pciAddrBusToHost */ linuxPpcBusAddrToHostAddr, #else /* pciAddrHostToBus */ pciAddrNOOP, +/* linuxTransAddrBusToHost is busted on sparc64 but the PCI rework tree + * makes it all moot, so we kludge it for now */ +#if defined(__sparc__) +/* pciAddrBusToHost */ pciAddrNOOP, +#else /* pciAddrBusToHost */ linuxTransAddrBusToHost, +#endif /* __sparc64__ */ #endif /* pciControlBridge */ NULL, diff --git a/hw/xfree86/os-support/drm/xf86drm.c b/hw/xfree86/os-support/drm/xf86drm.c index 3759920c2..214e58ba7 100644 --- a/hw/xfree86/os-support/drm/xf86drm.c +++ b/hw/xfree86/os-support/drm/xf86drm.c @@ -1388,6 +1388,22 @@ int drmDestroyDrawable(int fd, drm_drawable_t handle) return 0; } +int drmUpdateDrawableInfo(int fd, drm_drawable_t handle, + drm_drawable_info_type_t type, unsigned int num, + void *data) +{ + drm_update_draw_t update; + + update.handle = handle; + update.type = type; + update.num = num; + update.data = (unsigned long long)(unsigned long)data; + + if (ioctl(fd, DRM_IOCTL_UPDATE_DRAW, &update)) return -errno; + + return 0; +} + /** * Acquire the AGP device. * diff --git a/hw/xfree86/os-support/xf86drm.h b/hw/xfree86/os-support/xf86drm.h index 88f5e0ffc..107670672 100644 --- a/hw/xfree86/os-support/xf86drm.h +++ b/hw/xfree86/os-support/xf86drm.h @@ -543,6 +543,9 @@ extern int drmSwitchToContext(int fd, drm_context_t context); extern int drmDestroyContext(int fd, drm_context_t handle); extern int drmCreateDrawable(int fd, drm_drawable_t * handle); extern int drmDestroyDrawable(int fd, drm_drawable_t handle); +extern int drmUpdateDrawableInfo(int fd, drm_drawable_t handle, + drm_drawable_info_type_t type, + unsigned int num, void *data); extern int drmCtlInstHandler(int fd, int irq); extern int drmCtlUninstHandler(int fd); extern int drmInstallSIGIOHandler(int fd, diff --git a/hw/xfree86/parser/Makefile.am b/hw/xfree86/parser/Makefile.am index acda83d27..46ef79060 100644 --- a/hw/xfree86/parser/Makefile.am +++ b/hw/xfree86/parser/Makefile.am @@ -1,5 +1,8 @@ if INSTALL_LIBXF86CONFIG lib_LIBRARIES = libxf86config.a +LIBHEADERS = \ + xf86Optrec.h \ + xf86Parser.h else noinst_LIBRARIES = libxf86config.a endif @@ -32,3 +35,6 @@ EXTRA_DIST = \ xf86Parser.h \ xf86tokens.h \ cpconfig.c + +sdk_HEADERS = \ + $(LIBHEADERS) diff --git a/hw/xfree86/parser/Monitor.c b/hw/xfree86/parser/Monitor.c index 4a8575049..9dd0b1b1c 100644 --- a/hw/xfree86/parser/Monitor.c +++ b/hw/xfree86/parser/Monitor.c @@ -675,7 +675,7 @@ xf86printMonitorSection (FILE * cf, XF86ConfMonitorPtr ptr) ptr->mon_width, ptr->mon_height); if ( ptr->mon_n_hsync || ptr->mon_n_vrefresh ) - fprintf(cf," ### Comment all HorizSync and VertSync values to use DDC:\n"); + fprintf(cf," ### Comment all HorizSync and VertRefresh values to use DDC:\n"); for (i = 0; i < ptr->mon_n_hsync; i++) { fprintf (cf, "\tHorizSync %2.1f - %2.1f\n", diff --git a/hw/xfree86/parser/scan.c b/hw/xfree86/parser/scan.c index 5b29ab855..f81c45afe 100644 --- a/hw/xfree86/parser/scan.c +++ b/hw/xfree86/parser/scan.c @@ -157,9 +157,128 @@ xf86strToUL (char *str) return (tot); } +/* + * xf86getNextLine -- + * + * read from the configFile FILE stream until we encounter a new + * line; this is effectively just a big wrapper for fgets(3). + * + * xf86getToken() assumes that we will read up to the next + * newline; we need to grow configBuf and configRBuf as needed to + * support that. + */ + +static char* +xf86getNextLine(void) +{ + static int configBufLen = CONFIG_BUF_LEN; + char *tmpConfigBuf, *tmpConfigRBuf; + int c, i, pos = 0, eolFound = 0; + char *ret = NULL; + + /* + * reallocate the string if it was grown last time (i.e., is no + * longer CONFIG_BUF_LEN); we malloc the new strings first, so + * that if either of the mallocs fail, we can fall back on the + * existing buffer allocations + */ + + if (configBufLen != CONFIG_BUF_LEN) { + + tmpConfigBuf = xf86confmalloc(CONFIG_BUF_LEN); + tmpConfigRBuf = xf86confmalloc(CONFIG_BUF_LEN); + + if (!tmpConfigBuf || !tmpConfigRBuf) { + + /* + * at least one of the mallocs failed; keep the old buffers + * and free any partial allocations + */ + + xf86conffree(tmpConfigBuf); + xf86conffree(tmpConfigRBuf); + + } else { + + /* + * malloc succeeded; free the old buffers and use the new + * buffers + */ + + configBufLen = CONFIG_BUF_LEN; + + xf86conffree(configBuf); + xf86conffree(configRBuf); + + configBuf = tmpConfigBuf; + configRBuf = tmpConfigRBuf; + } + } + + /* read in another block of chars */ + + do { + ret = fgets(configBuf + pos, configBufLen - pos - 1, configFile); + + if (!ret) break; + + /* search for EOL in the new block of chars */ + + for (i = pos; i < (configBufLen - 1); i++) { + c = configBuf[i]; + + if (c == '\0') break; + + if ((c == '\n') || (c == '\r')) { + eolFound = 1; + break; + } + } + + /* + * if we didn't find EOL, then grow the string and + * read in more + */ + + if (!eolFound) { + + tmpConfigBuf = xf86confrealloc(configBuf, configBufLen + CONFIG_BUF_LEN); + tmpConfigRBuf = xf86confrealloc(configRBuf, configBufLen + CONFIG_BUF_LEN); + + if (!tmpConfigBuf || !tmpConfigRBuf) { + + /* + * at least one of the reallocations failed; use the + * new allocation that succeeded, but we have to + * fallback to the previous configBufLen size and use + * the string we have, even though we don't have an + * EOL + */ + + if (tmpConfigBuf) configBuf = tmpConfigBuf; + if (tmpConfigRBuf) configRBuf = tmpConfigRBuf; + + break; + + } else { + + /* reallocation succeeded */ + + configBuf = tmpConfigBuf; + configRBuf = tmpConfigRBuf; + pos = i; + configBufLen += CONFIG_BUF_LEN; + } + } + + } while (!eolFound); + + return (ret); +} + /* * xf86getToken -- - * Read next Token form the config file. Handle the global variable + * Read next Token from the config file. Handle the global variable * pushToken. */ int @@ -193,7 +312,7 @@ again: { char *ret; if (configFile) - ret = fgets (configBuf, CONFIG_BUF_LEN - 1, configFile); + ret = xf86getNextLine(); else { if (builtinConfig[builtinIndex] == NULL) ret = NULL; diff --git a/hw/xfree86/rac/Makefile.am b/hw/xfree86/rac/Makefile.am index 328ed197d..2d8d87975 100644 --- a/hw/xfree86/rac/Makefile.am +++ b/hw/xfree86/rac/Makefile.am @@ -1,4 +1,4 @@ -module_LIBRARIES = librac.a +noinst_LIBRARIES = librac.a librac_a_SOURCES = xf86RAC.c sdk_HEADERS = xf86RAC.h diff --git a/hw/xfree86/scanpci/extrapci.ids b/hw/xfree86/scanpci/extrapci.ids new file mode 100644 index 000000000..08e7af992 --- /dev/null +++ b/hw/xfree86/scanpci/extrapci.ids @@ -0,0 +1,43 @@ +# +# Modifications and additions to the standard list of PCI IDs in +# pci.ids. +# +# To modify an entry, simply add the modified version here. +# To leave part of an entry unchanged, use '"' for the name +# (e.g., leave the vendor name unchanged while adding/modifying +# a device). To delete an entry, set the name to '-'. +# +# One syntax extension is allowing a 16-bit class value to be +# specified for a device (see the syntax description below). +# +# Don't make gratuitous changes, and please send back +# changes/additions that aren't X-specific to the pciids +# project (http://pciids.sf.net/). +# +# + +# Vendors, devices and subsystems. Please keep sorted. + +# Syntax: +# vendor vendor_name +# device device_name <-- single tab +# C class <-- two tabs +# subvendor subdevice subsystem_name <-- two tabs +# +# Use lower-case hex digits for all numeric values. + +# Example: Add a new chipset for vendor who's ID is xyzw +# +# xyzw " +# 20ce New Chipset Description + +1102 " + 0002 " + C 0401 + +# Some NVIDIA cards that are not in the master pci.ids file yet. +10de " + 0147 GeForce 6700 XL + 0160 GeForce 6500 + 0169 GeForce 6250 + diff --git a/hw/xfree86/scanpci/pci.ids b/hw/xfree86/scanpci/pci.ids new file mode 100644 index 000000000..c6f565370 --- /dev/null +++ b/hw/xfree86/scanpci/pci.ids @@ -0,0 +1,12658 @@ +# +# List of PCI ID's +# +# Maintained by Martin Mares and other volunteers from the +# Linux PCI ID's Project at http://pciids.sf.net/. +# +# New data are always welcome, especially if accurate. If you have +# anything to contribute, please follow the instructions at the web site +# or send a diff -u against the most recent pci.ids to pci-ids@ucw.cz. +# +# This file can be distributed under either the GNU General Public License +# (version 2 or higher) or the 3-clause BSD License. +# +# Daily snapshot on Tue 2006-10-03 01:05:01 +# + +# Vendors, devices and subsystems. Please keep sorted. + +# Syntax: +# vendor vendor_name +# device device_name <-- single tab +# subvendor subdevice subsystem_name <-- two tabs + +0000 Gammagraphx, Inc. +001a Ascend Communications, Inc. +0033 Paradyne corp. +003d Lockheed Martin-Marietta Corp +# Real TJN ID is e159, but they got it wrong several times --mj +0059 Tiger Jet Network Inc. (Wrong ID) +0070 Hauppauge computer works Inc. +0071 Nebula Electronics Ltd. +0095 Silicon Image, Inc. (Wrong ID) + 0680 Ultra ATA/133 IDE RAID CONTROLLER CARD +# Wrong ID used in subsystem ID of the TELES.S0/PCI 2.x ISDN adapter +00a7 Teles AG (Wrong ID) +00f5 BFG Technologies, Inc. +0100 Ncipher Corp Ltd +0123 General Dynamics +# 018a is not LevelOne but there is a board misprogrammed +018a LevelOne + 0106 FPC-0106TX misprogrammed [RTL81xx] +# 021b is not Compaq but there is a board misprogrammed +021b Compaq Computer Corporation + 8139 HNE-300 (RealTek RTL8139c) [iPaq Networking] +0270 Hauppauge computer works Inc. (Wrong ID) +0291 Davicom Semiconductor, Inc. + 8212 DM9102A(DM9102AE, SM9102AF) Ethernet 100/10 MBit(Rev 40) +# SpeedStream is Efficient Networks, Inc, a Siemens Company +02ac SpeedStream + 1012 1012 PCMCIA 10/100 Ethernet Card [RTL81xx] +0315 SK-Electronics Co., Ltd. +0357 TTTech AG + 000a TTP-Monitoring Card V2.0 +0432 SCM Microsystems, Inc. + 0001 Pluto2 DVB-T Receiver for PCMCIA [EasyWatch MobilSet] +045e Microsoft + 006e MN-510 802.11b wireless USB paddle + 00c2 MN-710 wireless USB paddle +0482 Kyocera +04cf Myson Century, Inc + 8818 CS8818 USB2.0-to-ATAPI Bridge Controller with Embedded PHY +050d Belkin + 001a FSD7000 802.11g PCI Wireless card + 0109 F5U409-CU USB/Serial Portable Adapter + 7050 F5D7050 802.11g Wireless USB Adapter +05a9 OmniVision + 8519 OV519 series +05e3 CyberDoor + 0701 CBD516 +066f Sigmatel Inc. + 3410 SMTP3410 + 3500 SMTP3500 +0675 Dynalink + 1700 IS64PH ISDN Adapter + 1702 IS64PH ISDN Adapter + 1703 ISDN Adapter (PCI Bus, DV, W) + 1704 ISDN Adapter (PCI Bus, D, C) +067b Prolific Technology, Inc. + 2303 PL-2303 USB-to-Serial Converter + 3507 PL-3507 Hi-Speed USB & IEEE 1394 Combo to IDE Bridge Controller +0721 Sapphire, Inc. +07e2 ELMEG Communication Systems GmbH +# Wrong ID used in subsystem ID of VIA USB controllers. +0925 VIA Technologies, Inc. (Wrong ID) +093a PixArt Imaging Inc. +09c1 Arris + 0704 CM 200E Cable Modem +0a89 BREA Technologies Inc +0b0b Rhino Equiment Corp. + 0105 Rhino R1T1 + 0205 Rhino R4FXO + 0305 Rhino R4T1 + 0405 Rhino R8FXX + 0505 Rhino R24FXX + 0506 Rhino R2T1 + 0605 Rhino R2T1 + 0705 Rhino R24FXS +0b49 ASCII Corporation + 064f Trance Vibrator +0ccd TerraTec Electronic GmbH + 0038 Cinergy T^2 DVB-T Receiver +0e11 Compaq Computer Corporation + 0001 PCI to EISA Bridge + 0002 PCI to ISA Bridge + 0046 Smart Array 64xx + 0e11 409a Smart Array 641 + 0e11 409b Smart Array 642 + 0e11 409c Smart Array 6400 + 0e11 409d Smart Array 6400 EM + 0049 NC7132 Gigabit Upgrade Module + 004a NC6136 Gigabit Server Adapter + 005a Remote Insight II board - Lights-Out + 007c NC7770 1000BaseTX + 007d NC6770 1000BaseTX + 0085 NC7780 1000BaseTX + 00b1 Remote Insight II board - PCI device + 00bb NC7760 + 00ca NC7771 + 00cb NC7781 + 00cf NC7772 + 00d0 NC7782 + 00d1 NC7783 + 00e3 NC7761 + 0508 Netelligent 4/16 Token Ring + 1000 Triflex/Pentium Bridge, Model 1000 + 2000 Triflex/Pentium Bridge, Model 2000 + 3032 QVision 1280/p + 3033 QVision 1280/p + 3034 QVision 1280/p + 4000 4000 [Triflex] + 4030 SMART-2/P + 4031 SMART-2SL + 4032 Smart Array 3200 + 4033 Smart Array 3100ES + 4034 Smart Array 221 + 4040 Integrated Array + 4048 Compaq Raid LC2 + 4050 Smart Array 4200 + 4051 Smart Array 4250ES + 4058 Smart Array 431 + 4070 Smart Array 5300 + 4080 Smart Array 5i + 4082 Smart Array 532 + 4083 Smart Array 5312 + 4091 Smart Array 6i + 409a Smart Array 641 + 409b Smart Array 642 + 409c Smart Array 6400 + 409d Smart Array 6400 EM + 6010 HotPlug PCI Bridge 6010 + 7020 USB Controller + a0ec Fibre Channel Host Controller + a0f0 Advanced System Management Controller + a0f3 Triflex PCI to ISA Bridge + a0f7 PCI Hotplug Controller + 8086 002a PCI Hotplug Controller A + 8086 002b PCI Hotplug Controller B + a0f8 ZFMicro Chipset USB + a0fc FibreChannel HBA Tachyon + ae10 Smart-2/P RAID Controller + 0e11 4030 Smart-2/P Array Controller + 0e11 4031 Smart-2SL Array Controller + 0e11 4032 Smart Array Controller + 0e11 4033 Smart 3100ES Array Controller + ae29 MIS-L + ae2a MPC + ae2b MIS-E + ae31 System Management Controller + ae32 Netelligent 10/100 TX PCI UTP + ae33 Triflex Dual EIDE Controller + ae34 Netelligent 10 T PCI UTP + ae35 Integrated NetFlex-3/P + ae40 Netelligent Dual 10/100 TX PCI UTP + ae43 Netelligent Integrated 10/100 TX UTP + ae69 CETUS-L + ae6c Northstar + ae6d NorthStar CPU to PCI Bridge + b011 Netelligent 10/100 TX Embedded UTP + b012 Netelligent 10 T/2 PCI UTP/Coax + b01e NC3120 Fast Ethernet NIC + b01f NC3122 Fast Ethernet NIC + b02f NC1120 Ethernet NIC + b030 Netelligent 10/100 TX UTP + b04a 10/100 TX PCI Intel WOL UTP Controller + b060 Smart Array 5300 Controller + b0c6 NC3161 Fast Ethernet NIC + b0c7 NC3160 Fast Ethernet NIC + b0d7 NC3121 Fast Ethernet NIC + b0dd NC3131 Fast Ethernet NIC + b0de NC3132 Fast Ethernet Module + b0df NC6132 Gigabit Module + b0e0 NC6133 Gigabit Module + b0e1 NC3133 Fast Ethernet Module + b123 NC6134 Gigabit NIC + b134 NC3163 Fast Ethernet NIC + b13c NC3162 Fast Ethernet NIC + b144 NC3123 Fast Ethernet NIC + b163 NC3134 Fast Ethernet NIC + b164 NC3165 Fast Ethernet Upgrade Module + b178 Smart Array 5i/532 + 0e11 4080 Smart Array 5i + 0e11 4082 Smart Array 532 + 0e11 4083 Smart Array 5312 + b1a4 NC7131 Gigabit Server Adapter + b200 Memory Hot-Plug Controller + b203 Integrated Lights Out Controller + b204 Integrated Lights Out Processor + f130 NetFlex-3/P ThunderLAN 1.0 + f150 NetFlex-3/P ThunderLAN 2.3 +0e21 Cowon Systems, Inc. +0e55 HaSoTec GmbH +0eac SHF Communication Technologies AG +# Formerly NCR +1000 LSI Logic / Symbios Logic + 0001 53c810 + 1000 1000 LSI53C810AE PCI to SCSI I/O Processor + 0002 53c820 + 0003 53c825 + 1000 1000 LSI53C825AE PCI to SCSI I/O Processor (Ultra Wide) + 0004 53c815 + 0005 53c810AP + 0006 53c860 + 1000 1000 LSI53C860E PCI to Ultra SCSI I/O Processor + 000a 53c1510 + 0e11 b143 Integrated Dual Channel Wide Ultra2 SCSI Controller + 1000 1000 LSI53C1510 PCI to Dual Channel Wide Ultra2 SCSI Controller (Nonintelligent mode) + 000b 53C896/897 + 0e11 6004 EOB003 Series SCSI host adapter + 1000 1000 LSI53C896/7 PCI to Dual Channel Ultra2 SCSI Multifunction Controller + 1000 1010 LSI22910 PCI to Dual Channel Ultra2 SCSI host adapter + 1000 1020 LSI21002 PCI to Dual Channel Ultra2 SCSI host adapter + 13e9 1000 6221L-4U (Dual U2W SCSI, dual 10/100TX, graphics) + 000c 53c895 + 1000 1010 LSI8951U PCI to Ultra2 SCSI host adapter + 1000 1020 LSI8952U PCI to Ultra2 SCSI host adapter + 1de1 3906 DC-390U2B SCSI adapter + 1de1 3907 DC-390U2W + 000d 53c885 + 000f 53c875 + 0e11 7004 Embedded Ultra Wide SCSI Controller + 1000 1000 LSI53C876/E PCI to Dual Channel SCSI Controller + 1000 1010 LSI22801 PCI to Dual Channel Ultra SCSI host adapter + 1000 1020 LSI22802 PCI to Dual Channel Ultra SCSI host adapter + 1092 8760 FirePort 40 Dual SCSI Controller + 1775 10d0 V5D Single Board Computer Wide Ultra SCSI + 1775 10d1 V5D Single Board Computer Ultra SCSI + 1de1 3904 DC390F/U Ultra Wide SCSI Adapter + 4c53 1000 CC7/CR7/CP7/VC7/VP7/VR7 mainboard + 4c53 1050 CT7 mainboard + 0010 53C1510 + 0e11 4040 Integrated Array Controller + 0e11 4048 RAID LC2 Controller + 1000 1000 53C1510 PCI to Dual Channel Wide Ultra2 SCSI Controller (Intelligent mode) + 0012 53c895a + 1000 1000 LSI53C895A PCI to Ultra2 SCSI Controller + 0013 53c875a + 1000 1000 LSI53C875A PCI to Ultra SCSI Controller + 0020 53c1010 Ultra3 SCSI Adapter + 1000 1000 LSI53C1010-33 PCI to Dual Channel Ultra160 SCSI Controller + 107b 1040 Server Onboard 53C1010-33 + 1de1 1020 DC-390U3W + 0021 53c1010 66MHz Ultra3 SCSI Adapter + 1000 1000 LSI53C1000/1000R/1010R/1010-66 PCI to Ultra160 SCSI Controller + 1000 1010 Asus TR-DLS onboard 53C1010-66 + 103c 1330 Ultra160 SCSI [A7059A] + 103c 1340 Ultra160 SCSI [A7060A] + 124b 1070 PMC-USCSI3 + 4c53 1080 CT8 mainboard + 4c53 1300 P017 mezzanine (32-bit PMC) + 4c53 1310 P017 mezzanine (64-bit PMC) + 0030 53c1030 PCI-X Fusion-MPT Dual Ultra320 SCSI + 0e11 00da ProLiant ML 350 + 1028 0123 PowerEdge 2600 + 1028 014a PowerEdge 1750 + 1028 016c PowerEdge 1850 MPT Fusion SCSI/RAID (Perc 4) + 1028 0183 PowerEdge 1800 + 1028 1010 LSI U320 SCSI Controller + 103c 12c5 Ultra320 SCSI [A7173A] + 124b 1170 PMC-USCSI320 + 1734 1052 Primergy RX300 S2 + 0031 53c1030ZC PCI-X Fusion-MPT Dual Ultra320 SCSI + 0032 53c1035 PCI-X Fusion-MPT Dual Ultra320 SCSI + 1000 1000 LSI53C1020/1030 PCI-X to Ultra320 SCSI Controller + 0033 1030ZC_53c1035 PCI-X Fusion-MPT Dual Ultra320 SCSI + 0040 53c1035 PCI-X Fusion-MPT Dual Ultra320 SCSI + 1000 0033 MegaRAID SCSI 320-2XR + 1000 0066 MegaRAID SCSI 320-2XRWS + 0041 53C1035ZC PCI-X Fusion-MPT Dual Ultra320 SCSI + 0050 SAS1064 PCI-X Fusion-MPT SAS + 0054 SAS1068 PCI-X Fusion-MPT SAS + 0056 SAS1064E PCI-Express Fusion-MPT SAS + 0058 SAS1068E PCI-Express Fusion-MPT SAS + 005a SAS1066E PCI-Express Fusion-MPT SAS + 005c SAS1064A PCI-X Fusion-MPT SAS + 005e SAS1066 PCI-X Fusion-MPT SAS + 0060 MegaRAID SAS 1078 + 1028 1f0a PERC 6/E Adapter RAID Controller + 1028 1f0b PERC 6/i Adapter RAID Controller + 1028 1f0c PERC 6/i Integrated RAID Controller + 1028 1f0d PERC 6/i Enhanced RAID Controller + 0062 SAS1078 PCI-Express Fusion-MPT SAS + 1000 0062 SAS1078 PCI-Express Fusion-MPT SAS + 008f 53c875J + 1092 8000 FirePort 40 SCSI Controller + 1092 8760 FirePort 40 Dual SCSI Host Adapter + 0407 MegaRAID + 1000 0530 MegaRAID 530 SCSI 320-0X RAID Controller + 1000 0531 MegaRAID 531 SCSI 320-4X RAID Controller + 1000 0532 MegaRAID 532 SCSI 320-2X RAID Controller + 1028 0531 PowerEdge Expandable RAID Controller 4/QC + 1028 0533 PowerEdge Expandable RAID Controller 4/QC + 8086 0530 MegaRAID Intel RAID Controller SRCZCRX + 8086 0532 MegaRAID Intel RAID Controller SRCU42X + 0408 MegaRAID + 1000 0001 MegaRAID SCSI 320-1E RAID Controller + 1000 0002 MegaRAID SCSI 320-2E RAID Controller + 1025 004d MegaRAID ACER ROMB-2E RAID Controller + 1028 0001 PowerEdge RAID Controller PERC4e/SC + 1028 0002 PowerEdge RAID Controller PERC4e/DC + 1734 1065 FSC MegaRAID PCI Express ROMB + 8086 0002 MegaRAID Intel RAID Controller SRCU42E + 0409 MegaRAID + 1000 3004 MegaRAID SATA 300-4X RAID Controller + 1000 3008 MegaRAID SATA 300-8X RAID Controller + 8086 3008 MegaRAID RAID Controller SRCS28X + 8086 3431 MegaRAID RAID Controller Alief SROMBU42E + 8086 3499 MegaRAID RAID Controller Harwich SROMBU42E + 0411 MegaRAID SAS + 1000 1001 MegaRAID SAS 8408E + 1000 1002 MegaRAID SAS 8480E + 1000 1003 MegaRAID SAS 8344ELP + 1000 1004 MegaRAID SAS 8308ELP + 1000 100c MegaRAID SATA 300-12E + 1000 100d MegaRAID SATA 300-16E + 1000 2004 MegaRAID SATA 300-8ELP + 1000 2005 MegaRAID SATA 300-4ELP + 1033 8287 MegaRAID SAS PCI Express ROMB + 1054 3016 MegaRAID SAS RoMB Server + 1734 1081 MegaRAID SAS PCI Express ROMB + 1734 10a3 MegaRAID SAS PCI Express ROMB + 8086 1001 SRCSAS18E RAID Controller + 8086 1003 SRCSAS144E RAID Controller + 8086 3500 SROMBSAS18E RAID Controller + 8086 3501 SROMBSAS18E RAID Controller + 8086 3504 SROMBSAS18E RAID Controller + 0413 MegaRAID SAS Verde ZCR + 1000 1005 MegaRAID SAS 8300XLP + 0621 FC909 Fibre Channel Adapter + 0622 FC929 Fibre Channel Adapter + 1000 1020 44929 O Dual Fibre Channel card + 0623 FC929 LAN + 0624 FC919 Fibre Channel Adapter + 0625 FC919 LAN + 0626 FC929X Fibre Channel Adapter + 1000 1010 7202-XP-LC Dual Fibre Channel card + 0627 FC929X LAN + 0628 FC919X Fibre Channel Adapter + 0629 FC919X LAN + 0640 FC949X Fibre Channel Adapter + 0642 FC939X Fibre Channel Adapter + 0646 FC949ES Fibre Channel Adapter + 0701 83C885 NT50 DigitalScape Fast Ethernet + 0702 Yellowfin G-NIC gigabit ethernet + 1318 0000 PEI100X + 0804 SA2010 + 0805 SA2010ZC + 0806 SA2020 + 0807 SA2020ZC + 0901 61C102 + 1000 63C815 + 1960 MegaRAID + 1000 0518 MegaRAID 518 SCSI 320-2 Controller + 1000 0520 MegaRAID 520 SCSI 320-1 Controller + 1000 0522 MegaRAID 522 i4 133 RAID Controller + 1000 0523 MegaRAID SATA 150-6 RAID Controller + 1000 4523 MegaRAID SATA 150-4 RAID Controller + 1000 a520 MegaRAID ZCR SCSI 320-0 Controller + 1028 0518 MegaRAID 518 DELL PERC 4/DC RAID Controller + 1028 0520 MegaRAID 520 DELL PERC 4/SC RAID Controller + 1028 0531 PowerEdge Expandable RAID Controller 4/QC + 1028 0533 PowerEdge Expandable RAID Controller 4/QC + 8086 0520 MegaRAIDRAID Controller SRCU41L + 8086 0523 MegaRAID RAID Controller SRCS16 +1001 Kolter Electronic + 0010 PCI 1616 Measurement card with 32 digital I/O lines + 0011 OPTO-PCI Opto-Isolated digital I/O board + 0012 PCI-AD/DA Analogue I/O board + 0013 PCI-OPTO-RELAIS Digital I/O board with relay outputs + 0014 PCI-Counter/Timer Counter Timer board + 0015 PCI-DAC416 Analogue output board + 0016 PCI-MFB Analogue I/O board + 0017 PROTO-3 PCI Prototyping board + 9100 INI-9100/9100W SCSI Host +1002 ATI Technologies Inc + 3150 M24 1P [Radeon Mobility X600] + 3152 M22 [Radeon Mobility X300] + 3154 M24 1T [FireGL M24 GL] + 3e50 RV380 0x3e50 [Radeon X600] + 3e54 RV380 0x3e54 [FireGL V3200] + 3e70 RV380 [Radeon X600] Secondary + 4136 Radeon IGP 320 M + 4137 Radeon IGP330/340/350 + 4144 R300 AD [Radeon 9500 Pro] + 4145 R300 AE [Radeon 9700 Pro] + 4146 R300 AF [Radeon 9700 Pro] + 4147 R300 AG [FireGL Z1/X1] + 4148 R350 AH [Radeon 9800] + 4149 R350 AI [Radeon 9800] + 414a R350 AJ [Radeon 9800] + 414b R350 AK [Fire GL X2] + 4150 RV350 AP [Radeon 9600] + 1002 0002 R9600 Pro primary (Asus OEM for HP) + 1002 0003 R9600 Pro secondary (Asus OEM for HP) + 1002 4722 All-in-Wonder 2006 AGP Edition + 1458 4024 Giga-Byte GV-R96128D Primary + 148c 2064 PowerColor R96A-C3N + 148c 2066 PowerColor R96A-C3N + 174b 7c19 Sapphire Atlantis Radeon 9600 Pro + 174b 7c29 GC-R9600PRO Primary [Sapphire] + 17ee 2002 Radeon 9600 256Mb Primary + 18bc 0101 GC-R9600PRO Primary + 4151 RV350 AQ [Radeon 9600] + 1043 c004 A9600SE + 4152 RV350 AR [Radeon 9600] + 1002 0002 Radeon 9600XT + 1002 4772 All-in-Wonder 9600 XT + 1043 c002 Radeon 9600 XT TVD + 1043 c01a A9600XT/TD + 174b 7c29 Sapphire Radeon 9600XT + 1787 4002 Radeon 9600 XT + 4153 RV350 AS [Radeon 9550] + 1043 010c A9550GE/TD + 1462 932c 865PE Neo2-V (MS-6788) mainboard + 4154 RV350 AT [Fire GL T2] + 4155 RV350 AU [Fire GL T2] + 4156 RV350 AV [Fire GL T2] + 4157 RV350 AW [Fire GL T2] + 4158 68800AX [Mach32] + 4164 R300 AD [Radeon 9500 Pro] (Secondary) + 4165 R300 AE [Radeon 9700 Pro] (Secondary) + 4166 R300 AF [Radeon 9700 Pro] (Secondary) + 4168 Radeon R350 [Radeon 9800] (Secondary) + 4170 RV350 AP [Radeon 9600] (Secondary) + 1002 0003 R9600 Pro secondary (Asus OEM for HP) + 1002 4723 All-in-Wonder 2006 AGP Edition (Secondary) + 1458 4025 Giga-Byte GV-R96128D Secondary + 148c 2067 PowerColor R96A-C3N (Secondary) + 174b 7c28 GC-R9600PRO Secondary [Sapphire] + 17ee 2003 Radeon 9600 256Mb Secondary + 18bc 0100 GC-R9600PRO Secondary + 4171 RV350 AQ [Radeon 9600] (Secondary) + 1043 c005 A9600SE (Secondary) + 4172 RV350 AR [Radeon 9600] (Secondary) + 1002 0003 Radeon 9600XT (Secondary) + 1002 4773 All-in-Wonder 9600 XT (Secondary) + 1043 c003 A9600XT (Secondary) + 1043 c01b A9600XT/TD (Secondary) + 174b 7c28 Sapphire Radeon 9600XT (Secondary) + 1787 4003 Radeon 9600 XT (Secondary) + 4173 RV350 AS [Radeon 9550] (Secondary) + 1043 010d A9550GE/TD (Secondary) + 4237 Radeon 7000 IGP + 4242 R200 BB [Radeon All in Wonder 8500DV] + 1002 02aa Radeon 8500 AIW DV Edition + 4243 R200 BC [Radeon All in Wonder 8500] + 4336 Radeon Mobility U1 + 1002 4336 Pavilion ze4300 ATI Radeon Mobility U1 (IGP 320 M) + 103c 0024 Pavilion ze4400 builtin Video + 161f 2029 eMachines M5312 builtin Video + 4337 Radeon IGP 330M/340M/350M + 1014 053a ThinkPad R40e (2684-HVG) builtin VGA controller + 103c 0850 Radeon IGP 345M + 4341 IXP150 AC'97 Audio Controller + 4345 EHCI USB Controller + 4347 OHCI USB Controller #1 + 4348 OHCI USB Controller #2 + 4349 ATI Dual Channel Bus Master PCI IDE Controller + 434d IXP AC'97 Modem + 4353 ATI SMBus + 4354 215CT [Mach64 CT] + 4358 210888CX [Mach64 CX] + 4363 ATI SMBus + 436e ATI 436E Serial ATA Controller + 4370 IXP SB400 AC'97 Audio Controller + 1025 0079 Aspire 5024WLMMi + 103c 308b MX6125 + 107b 0300 MX6421 + 4371 IXP SB400 PCI-PCI Bridge + 103c 308b MX6125 + 4372 IXP SB400 SMBus Controller + 1025 0080 Aspire 5024WLMMi + 103c 308b MX6125 + 4373 IXP SB400 USB2 Host Controller + 1025 0080 Aspire 5024WLMMi + 103c 308b MX6125 + 4374 IXP SB400 USB Host Controller + 103c 308b MX6125 + 4375 IXP SB400 USB Host Controller + 1025 0080 Aspire 5024WLMMi + 103c 308b MX6125 + 4376 Standard Dual Channel PCI IDE Controller ATI + 1025 0080 Aspire 5024WLMMi + 103c 308b MX6125 + 4377 IXP SB400 PCI-ISA Bridge + 1025 0080 Aspire 5024WLMi + 103c 308b MX6125 + 4378 ATI SB400 - AC'97 Modem Controller + 1025 0080 Aspire 5024WLMMi + 103c 308b MX6125 + 4379 ATI 4379 Serial ATA Controller + 437a ATI 437A Serial ATA Controller + 437b SB450 HDA Audio + 4380 SB600 Non-Raid-5 SATA + 4381 SB600 Raid-5 SATA + 4382 SB600 AC97 Audio + 4383 SB600 Azalia + 4384 SB600 PCI to PCI Bridge + 4385 SB600 SMBus + 4386 SB600 USB Controller (EHCI) + 4387 SB600 USB (OHCI0) + 4388 SB600 USB (OHCI1) + 4389 SB600 USB (OHCI2) + 438a SB600 USB (OHCI3) + 438b SB600 USB (OHCI4) + 438c SB600 IDE + 438d SB600 PCI to LPC Bridge + 438e SB600 AC97 Modem + 4437 Radeon Mobility 7000 IGP + 4554 210888ET [Mach64 ET] + 4654 Mach64 VT + 4742 3D Rage Pro AGP 1X/2X + 1002 0040 Rage Pro Turbo AGP 2X + 1002 0044 Rage Pro Turbo AGP 2X + 1002 0061 Rage Pro AIW AGP 2X + 1002 0062 Rage Pro AIW AGP 2X + 1002 0063 Rage Pro AIW AGP 2X + 1002 0080 Rage Pro Turbo AGP 2X + 1002 0084 Rage Pro Turbo AGP 2X + 1002 4742 Rage Pro Turbo AGP 2X + 1002 8001 Rage Pro Turbo AGP 2X + 1028 0082 Rage Pro Turbo AGP 2X + 1028 4082 Optiplex GX1 Onboard Display Adapter + 1028 8082 Rage Pro Turbo AGP 2X + 1028 c082 Rage Pro Turbo AGP 2X + 8086 4152 Xpert 98D AGP 2X + 8086 464a Rage Pro Turbo AGP 2X + 4744 3D Rage Pro AGP 1X + 1002 4744 Rage Pro Turbo AGP + 4747 3D Rage Pro + 4749 3D Rage Pro + 1002 0061 Rage Pro AIW + 1002 0062 Rage Pro AIW + 474c Rage XC + 474d Rage XL AGP 2X + 1002 0004 Xpert 98 RXL AGP 2X + 1002 0008 Xpert 98 RXL AGP 2X + 1002 0080 Rage XL AGP 2X + 1002 0084 Xpert 98 AGP 2X + 1002 474d Rage XL AGP + 1033 806a Rage XL AGP + 474e Rage XC AGP + 1002 474e Rage XC AGP + 474f Rage XL + 1002 0008 Rage XL + 1002 474f Rage XL + 4750 3D Rage Pro 215GP + 1002 0040 Rage Pro Turbo + 1002 0044 Rage Pro Turbo + 1002 0080 Rage Pro Turbo + 1002 0084 Rage Pro Turbo + 1002 4750 Rage Pro Turbo + 4751 3D Rage Pro 215GQ + 4752 Rage XL + 0e11 001e Proliant Rage XL + 1002 0008 Rage XL + 1002 4752 Proliant Rage XL + 1002 8008 Rage XL + 1028 00ce PowerEdge 1400 + 1028 00d1 PowerEdge 2550 + 1028 00d9 PowerEdge 2500 + 1028 0134 PowerEdge 600SC + 103c 10e1 NetServer Rage XL + 107b 6400 6400 Server + 1734 007a Primergy RX300 + 8086 3411 SDS2 Mainboard + 8086 3427 S875WP1-E mainboard + 4753 Rage XC + 1002 4753 Rage XC + 4754 3D Rage I/II 215GT [Mach64 GT] + 4755 3D Rage II+ 215GTB [Mach64 GTB] + 4756 3D Rage IIC 215IIC [Mach64 GT IIC] + 1002 4756 Rage IIC + 4757 3D Rage IIC AGP + 1002 4757 Rage IIC AGP + 1028 0089 Rage 3D IIC + 1028 008e PowerEdge 1300 onboard video + 1028 4082 Rage 3D IIC + 1028 8082 Rage 3D IIC + 1028 c082 Rage 3D IIC + 4758 210888GX [Mach64 GX] + 4759 3D Rage IIC + 475a 3D Rage IIC AGP + 1002 0084 Rage 3D Pro AGP 2x XPERT 98 + 1002 0087 Rage 3D IIC + 1002 475a Rage IIC AGP + 4964 Radeon RV250 Id [Radeon 9000] + 4965 Radeon RV250 Ie [Radeon 9000] + 4966 Radeon RV250 If [Radeon 9000] + 10f1 0002 RV250 If [Tachyon G9000 PRO] + 148c 2039 RV250 If [Radeon 9000 Pro "Evil Commando"] + 1509 9a00 RV250 If [Radeon 9000 "AT009"] + 1681 0040 RV250 If [3D prophet 9000] + 174b 7176 RV250 If [Sapphire Radeon 9000 Pro] + 174b 7192 RV250 If [Radeon 9000 "Atlantis"] + 17af 2005 RV250 If [Excalibur Radeon 9000 Pro] + 17af 2006 RV250 If [Excalibur Radeon 9000] + 4967 Radeon RV250 Ig [Radeon 9000] + 496e Radeon RV250 [Radeon 9000] (Secondary) + 4a48 R420 JH [Radeon X800] + 4a49 R420 JI [Radeon X800PRO] + 4a4a R420 JJ [Radeon X800SE] + 4a4b R420 JK [Radeon X800] + 4a4c R420 JL [Radeon X800] + 4a4d R420 JM [FireGL X3] + 4a4e M18 JN [Radeon Mobility 9800] + 4a50 R420 JP [Radeon X800XT] + 4a54 R420 [Radeon X800 VE] + 4a69 R420 [Radeon X800 PRO/GTO] (Secondary) + 4a6a R420 [Radeon X800] (Secondary) + 4a6b R420 [Radeon X800] (Secondary) + 4a70 R420 [X800XT-PE] (Secondary) + 4a74 R420 [Radeon X800 VE] (Secondary) + 4b49 R480 [Radeon X850XT] + 4b4b R480 [Radeon X850Pro] + 4b4c R481 [Radeon X850XT-PE] + 4b69 R480 [Radeon X850XT] (Secondary) + 4b6b R480 [Radeon X850Pro] (Secondary) + 4b6c R481 [Radeon X850XT-PE] (Secondary) + 4c42 3D Rage LT Pro AGP-133 + 0e11 b0e7 Rage LT Pro (Compaq Presario 5240) + 0e11 b0e8 Rage 3D LT Pro + 0e11 b10e 3D Rage LT Pro (Compaq Armada 1750) + 1002 0040 Rage LT Pro AGP 2X + 1002 0044 Rage LT Pro AGP 2X + 1002 4c42 Rage LT Pro AGP 2X + 1002 8001 Rage LT Pro AGP 2X + 1028 0085 Rage 3D LT Pro + 4c44 3D Rage LT Pro AGP-66 + 4c45 Rage Mobility M3 AGP + 4c46 Rage Mobility M3 AGP 2x + 1028 00b1 Latitude C600 + 4c47 3D Rage LT-G 215LG + 4c49 3D Rage LT Pro + 1002 0004 Rage LT Pro + 1002 0040 Rage LT Pro + 1002 0044 Rage LT Pro + 1002 4c49 Rage LT Pro + 4c4d Rage Mobility P/M AGP 2x + 0e11 b111 Armada M700 + 0e11 b160 Armada E500 + 1002 0084 Xpert 98 AGP 2X (Mobility) + 1014 0154 ThinkPad A20m/A21m + 1028 00aa Latitude CPt + 1028 00bb Latitude CPx + 10e1 10cf Fujitsu Siemens LifeBook C Series + 1179 ff00 Satellite 1715XCDS laptop + 13bd 1019 PC-AR10 + 4c4e Rage Mobility L AGP 2x + 4c50 3D Rage LT Pro + 1002 4c50 Rage LT Pro + 4c51 3D Rage LT Pro + 4c52 Rage Mobility P/M + 1033 8112 Versa Note VXi + 4c53 Rage Mobility L + 4c54 264LT [Mach64 LT] + 4c57 Radeon Mobility M7 LW [Radeon Mobility 7500] + 1014 0517 ThinkPad T30 + 1028 00e6 Radeon Mobility M7 LW (Dell Inspiron 8100) + 1028 012a Latitude C640 + 144d c006 Radeon Mobility M7 LW in vpr Matrix 170B4 + 4c58 Radeon RV200 LX [Mobility FireGL 7800 M7] + 4c59 Radeon Mobility M6 LY + 0e11 b111 Evo N600c + 1014 0235 ThinkPad A30/A30p (2652/2653) + 1014 0239 ThinkPad X22/X23/X24 + 104d 80e7 VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP + 104d 8140 PCG-Z1SP laptop + 1509 1930 Medion MD9703 + 4c5a Radeon Mobility M6 LZ + 4c64 Radeon R250 Ld [Radeon Mobility 9000 M9] + 4c65 Radeon R250 Le [Radeon Mobility 9000 M9] + 4c66 Radeon R250 [Mobility FireGL 9000] + 4c67 Radeon R250 Lg [Radeon Mobility 9000 M9] +# Secondary chip to the Lf + 4c6e Radeon R250 Ln [Radeon Mobility 9000 M9] [Secondary] + 4d46 Rage Mobility M4 AGP + 4d4c Rage Mobility M4 AGP + 4e44 Radeon R300 ND [Radeon 9700 Pro] + 1002 515e Radeon ES1000 + 1002 5965 Radeon ES1000 + 4e45 Radeon R300 NE [Radeon 9500 Pro] + 1002 0002 Radeon R300 NE [Radeon 9500 Pro] + 1681 0002 Hercules 3D Prophet 9500 PRO [Radeon 9500 Pro] + 4e46 RV350 NF [Radeon 9600] + 4e47 Radeon R300 NG [FireGL X1] + 4e48 Radeon R350 [Radeon 9800 Pro] + 4e49 Radeon R350 [Radeon 9800] + 4e4a RV350 NJ [Radeon 9800 XT] + 4e4b R350 NK [Fire GL X2] + 4e50 RV350 [Mobility Radeon 9600 M10] + 1025 005a TravelMate 290 + 103c 088c NC8000 laptop + 103c 0890 NC6000 laptop + 1462 0311 MSI M510A + 1734 1055 Amilo M1420W + 4e51 M10 NQ [Radeon Mobility 9600] + 4e52 RV350 [Mobility Radeon 9600 M10] + 4e53 M10 NS [Radeon Mobility 9600] + 4e54 M10 NT [FireGL Mobility T2] + 4e56 M11 NV [FireGL Mobility T2e] + 4e64 Radeon R300 [Radeon 9700 Pro] (Secondary) + 4e65 Radeon R300 [Radeon 9500 Pro] (Secondary) + 1002 0003 Radeon R300 NE [Radeon 9500 Pro] + 1681 0003 Hercules 3D Prophet 9500 PRO [Radeon 9500 Pro] (Secondary) + 4e66 RV350 NF [Radeon 9600] (Secondary) + 4e67 Radeon R300 [FireGL X1] (Secondary) + 4e68 Radeon R350 [Radeon 9800 Pro] (Secondary) + 4e69 Radeon R350 [Radeon 9800] (Secondary) + 4e6a RV350 NJ [Radeon 9800 XT] (Secondary) + 1002 4e71 ATI Technologies Inc M10 NQ [Radeon Mobility 9600] + 4e71 M10 NQ [Radeon Mobility 9600] (Secondary) + 4f72 RV250 [Radeon 9000 Series] + 4f73 Radeon RV250 [Radeon 9000 Series] (Secondary) + 5041 Rage 128 PA/PRO + 5042 Rage 128 PB/PRO AGP 2x + 5043 Rage 128 PC/PRO AGP 4x + 5044 Rage 128 PD/PRO TMDS + 1002 0028 Rage 128 AIW + 1002 0029 Rage 128 AIW + 5045 Rage 128 PE/PRO AGP 2x TMDS + 5046 Rage 128 PF/PRO AGP 4x TMDS + 1002 0004 Rage Fury Pro + 1002 0008 Rage Fury Pro/Xpert 2000 Pro + 1002 0014 Rage Fury Pro + 1002 0018 Rage Fury Pro/Xpert 2000 Pro + 1002 0028 Rage 128 Pro AIW AGP + 1002 002a Rage 128 Pro AIW AGP + 1002 0048 Rage Fury Pro + 1002 2000 Rage Fury MAXX AGP 4x (TMDS) (VGA device) + 1002 2001 Rage Fury MAXX AGP 4x (TMDS) (Extra device?!) + 5047 Rage 128 PG/PRO + 5048 Rage 128 PH/PRO AGP 2x + 5049 Rage 128 PI/PRO AGP 4x + 504a Rage 128 PJ/PRO TMDS + 504b Rage 128 PK/PRO AGP 2x TMDS + 504c Rage 128 PL/PRO AGP 4x TMDS + 504d Rage 128 PM/PRO + 504e Rage 128 PN/PRO AGP 2x + 504f Rage 128 PO/PRO AGP 4x + 5050 Rage 128 PP/PRO TMDS [Xpert 128] + 1002 0008 Xpert 128 + 5051 Rage 128 PQ/PRO AGP 2x TMDS + 5052 Rage 128 PR/PRO AGP 4x TMDS + 5053 Rage 128 PS/PRO + 5054 Rage 128 PT/PRO AGP 2x + 5055 Rage 128 PU/PRO AGP 4x + 5056 Rage 128 PV/PRO TMDS + 5057 Rage 128 PW/PRO AGP 2x TMDS + 5058 Rage 128 PX/PRO AGP 4x TMDS + 5144 Radeon R100 QD [Radeon 7200] + 1002 0008 Radeon 7000/Radeon VE + 1002 0009 Radeon 7000/Radeon + 1002 000a Radeon 7000/Radeon + 1002 001a Radeon 7000/Radeon + 1002 0029 Radeon AIW + 1002 0038 Radeon 7000/Radeon + 1002 0039 Radeon 7000/Radeon + 1002 008a Radeon 7000/Radeon + 1002 00ba Radeon 7000/Radeon + 1002 0139 Radeon 7000/Radeon + 1002 028a Radeon 7000/Radeon + 1002 02aa Radeon AIW + 1002 053a Radeon 7000/Radeon + 5145 Radeon R100 QE + 5146 Radeon R100 QF + 5147 Radeon R100 QG + 5148 Radeon R200 QH [Radeon 8500] + 1002 010a FireGL 8800 64Mb + 1002 0152 FireGL 8800 128Mb + 1002 0162 FireGL 8700 32Mb + 1002 0172 FireGL 8700 64Mb + 5149 Radeon R200 QI + 514a Radeon R200 QJ + 514b Radeon R200 QK + 514c Radeon R200 QL [Radeon 8500 LE] + 1002 003a Radeon R200 QL [Radeon 8500 LE] + 1002 013a Radeon 8500 + 148c 2026 R200 QL [Radeon 8500 Evil Master II Multi Display Edition] + 1681 0010 Radeon 8500 [3D Prophet 8500 128Mb] + 174b 7149 Radeon R200 QL [Sapphire Radeon 8500 LE] + 514d Radeon R200 QM [Radeon 9100] + 514e Radeon R200 QN [Radeon 8500LE] + 514f Radeon R200 QO [Radeon 8500LE] + 5154 R200 QT [Radeon 8500] + 5155 R200 QU [Radeon 9100] + 5157 Radeon RV200 QW [Radeon 7500] + 1002 013a Radeon 7500 + 1002 103a Dell Optiplex GX260 + 1458 4000 RV200 QW [RADEON 7500 PRO MAYA AR] + 148c 2024 RV200 QW [Radeon 7500LE Dual Display] + 148c 2025 RV200 QW [Radeon 7500 Evil Master Multi Display Edition] + 148c 2036 RV200 QW [Radeon 7500 PCI Dual Display] + 174b 7146 RV200 QW [Radeon 7500 LE] + 174b 7147 RV200 QW [Sapphire Radeon 7500LE] + 174b 7161 Radeon RV200 QW [Radeon 7500 LE] + 17af 0202 RV200 QW [Excalibur Radeon 7500LE] + 5158 Radeon RV200 QX [Radeon 7500] + 5159 Radeon RV100 QY [Radeon 7000/VE] + 1002 000a Radeon 7000/Radeon VE + 1002 000b Radeon 7000 + 1002 0038 Radeon 7000/Radeon VE + 1002 003a Radeon 7000/Radeon VE + 1002 00ba Radeon 7000/Radeon VE + 1002 013a Radeon 7000/Radeon VE + 1002 0908 XVR-100 (supplied by Sun) +# The IBM card doubles as an ATI PCI video adapter + 1014 029a Remote Supervisor Adapter II (RSA2) + 1014 02c8 IBM eServer xSeries server mainboard + 1028 019a PowerEdge SC1425 + 103c 1292 Radeon 7000 + 1458 4002 RV100 QY [RADEON 7000 PRO MAYA AV Series] + 148c 2003 RV100 QY [Radeon 7000 Multi-Display Edition] + 148c 2023 RV100 QY [Radeon 7000 Evil Master Multi-Display] + 174b 7112 RV100 QY [Sapphire Radeon VE 7000] + 174b 7c28 Sapphire Radeon VE 7000 DDR + 1787 0202 RV100 QY [Excalibur Radeon 7000] + 17ee 1001 Radeon 7000 64MB DDR + DVI + 515a Radeon RV100 QZ [Radeon 7000/VE] + 515e ES1000 + 515f ES1000 + 5168 Radeon R200 Qh + 5169 Radeon R200 Qi + 516a Radeon R200 Qj + 516b Radeon R200 Qk +# This one is not in ATI documentation, but is in XFree86 source code + 516c Radeon R200 Ql + 5245 Rage 128 RE/SG + 1002 0008 Xpert 128 + 1002 0028 Rage 128 AIW + 1002 0029 Rage 128 AIW + 1002 0068 Rage 128 AIW + 5246 Rage 128 RF/SG AGP + 1002 0004 Magnum/Xpert 128/Xpert 99 + 1002 0008 Magnum/Xpert128/X99/Xpert2000 + 1002 0028 Rage 128 AIW AGP + 1002 0044 Rage Fury/Xpert 128/Xpert 2000 + 1002 0068 Rage 128 AIW AGP + 1002 0448 Rage Fury + 5247 Rage 128 RG + 524b Rage 128 RK/VR + 524c Rage 128 RL/VR AGP + 1002 0008 Xpert 99/Xpert 2000 + 1002 0088 Xpert 99 + 5345 Rage 128 SE/4x + 5346 Rage 128 SF/4x AGP 2x + 1002 0048 RAGE 128 16MB VGA TVOUT AMC PAL + 5347 Rage 128 SG/4x AGP 4x + 5348 Rage 128 SH + 534b Rage 128 SK/4x + 534c Rage 128 SL/4x AGP 2x + 534d Rage 128 SM/4x AGP 4x + 1002 0008 Xpert 99/Xpert 2000 + 1002 0018 Xpert 2000 + 534e Rage 128 4x + 5354 Mach 64 VT + 1002 5654 Mach 64 reference + 5446 Rage 128 Pro Ultra TF + 1002 0004 Rage Fury Pro + 1002 0008 Rage Fury Pro/Xpert 2000 Pro + 1002 0018 Rage Fury Pro/Xpert 2000 Pro + 1002 0028 Rage 128 AIW Pro AGP + 1002 0029 Rage 128 AIW + 1002 002a Rage 128 AIW Pro AGP + 1002 002b Rage 128 AIW + 1002 0048 Xpert 2000 Pro + 544c Rage 128 Pro Ultra TL + 5452 Rage 128 Pro Ultra TR + 1002 001c Rage 128 Pro 4XL + 103c 1279 Rage 128 Pro 4XL + 5453 Rage 128 Pro Ultra TS + 5454 Rage 128 Pro Ultra TT + 5455 Rage 128 Pro Ultra TU + 5460 M22 [Radeon Mobility M300] + 5462 M24 [Radeon Mobility X600] + 5464 M22 [FireGL GL] + 5548 R423 UH [Radeon X800 (PCIE)] + 5549 R423 UI [Radeon X800PRO (PCIE)] + 554a R423 UJ [Radeon X800LE (PCIE)] + 554b R423 UK [Radeon X800SE (PCIE)] + 554d R430 [Radeon X800 XL] (PCIe) + 554f R430 [Radeon X800 (PCIE)] + 5550 R423 [Fire GL V7100] + 5551 R423 UQ [FireGL V7200 (PCIE)] + 5552 R423 UR [FireGL V5100 (PCIE)] + 5554 R423 UT [FireGL V7100 (PCIE)] + 5569 R423 UI [Radeon X800PRO (PCIE)] Secondary + 556b Radeon R423 UK (PCIE) [X800 SE] (Secondary) + 556d R430 [Radeon X800 XL] (PCIe) Secondary + 556f R430 [Radeon X800 (PCIE) Secondary] + 5571 R423GL-SE ATI FIREGL V5100 PCI-EX Secondary + 564a M26 [Mobility FireGL V5000] + 564b M26 [Mobility FireGL V5000] + 564f M26 [Radeon Mobility X700 XL] (PCIE) + 5652 M26 [Radeon Mobility X700] + 5653 Radeon Mobility X700 (PCIE) + 1025 0080 Aspire 5024WLMi + 5654 264VT [Mach64 VT] + 1002 5654 Mach64VT Reference + 5655 264VT3 [Mach64 VT3] + 5656 264VT4 [Mach64 VT4] + 5830 RS300 Host Bridge + 5831 RS300 Host Bridge + 5832 RS300 Host Bridge + 5833 Radeon 9100 IGP Host Bridge + 5834 Radeon 9100 IGP + 5835 RS300M AGP [Radeon Mobility 9100IGP] + 5838 Radeon 9100 IGP AGP Bridge + 5940 RV280 [Radeon 9200 PRO] (Secondary) + 5941 RV280 [Radeon 9200] (Secondary) + 1458 4019 Gigabyte Radeon 9200 + 174b 7c12 Sapphire Radeon 9200 + 17af 200d Excalibur Radeon 9200 + 18bc 0050 GeXcube GC-R9200-C3 (Secondary) + 5944 RV280 [Radeon 9200 SE (PCI)] + 5950 RS480 Host Bridge + 1025 0080 Aspire 5024WLMMi + 103c 308b MX6125 + 5951 ATI Radeon Xpress 200 (RS480/RS482/RX480/RX482) Chipset - Host bridge + 5954 RS480 [Radeon Xpress 200G Series] + 1002 5954 RV370 [Radeon Xpress 200G Series] + 5955 ATI Radeon XPRESS 200M 5955 (PCIE) + 1002 5955 RS480 0x5955 [ATI Radeon XPRESS 200M 5955 (PCIE)] + 103c 308b MX6125 + 5960 RV280 [Radeon 9200 PRO] + 5961 RV280 [Radeon 9200] + 1002 2f72 All-in-Wonder 9200 Series + 1019 4c30 Radeon 9200 VIVO + 12ab 5961 YUAN SMARTVGA Radeon 9200 + 1458 4018 Gigabyte Radeon 9200 + 174b 7c13 Sapphire Radeon 9200 + 17af 200c Excalibur Radeon 9200 + 18bc 0050 Radeon 9200 Game Buster + 18bc 0051 GeXcube GC-R9200-C3 + 18bc 0053 Radeon 9200 Game Buster VIVO + 5962 RV280 [Radeon 9200] + 5964 RV280 [Radeon 9200 SE] + 1043 c006 ASUS Radeon 9200 SE / TD / 128M + 1458 4018 Radeon 9200 SE + 1458 4032 Radeon 9200 SE 128MB + 147b 6191 R9200SE-DT + 148c 2073 CN-AG92E + 174b 7c13 Sapphire Radeon 9200 SE + 1787 5964 Excalibur 9200SE VIVO 128M + 17af 2012 Radeon 9200 SE Excalibur + 18bc 0170 Sapphire Radeon 9200 SE 128MB Game Buster + 18bc 0173 GC-R9200L(SE)-C3H [Radeon 9200 Game Buster] + 5969 ES1000 + 5974 RS482 [Radeon Xpress 200] + 5975 RS482 [Radeon Xpress 200M] + 5a33 Radeon Xpress 200 Host Bridge + 5a34 RS480 PCI-X Root Port +# Comes in pair with 5a3f + 5a36 RS480 PCI Bridge + 5a38 RS480 PCI Bridge +# Comes in pair with 5a38 + 5a39 RS480 PCI Bridge + 5a3f RS480 PCI Bridge + 5a41 RS400 [Radeon Xpress 200] + 5a42 RS400 [Radeon Xpress 200M] + 5a61 RC410 [Radeon Xpress 200] + 5a62 RC410 [Radeon Xpress 200M] + 5b60 RV370 5B60 [Radeon X300 (PCIE)] + 1043 002a Extreme AX300SE-X + 1043 032e Extreme AX300/TD + 1462 0400 RX300SE-TD128E (MS-8940 REV:200) + 1462 0402 RX300SE-TD128E (MS-8940) + 196d 1086 X300SE HM + 5b62 RV380 [Radeon X600 (PCIE)] + 5b63 RV370 [Sapphire X550 Silent] + 5b64 RV370 5B64 [FireGL V3100 (PCIE)] + 5b65 RV370 5B65 [FireGL D1100 (PCIE)] + 5b70 RV370 [Radeon X300SE] + 1462 0403 RX300SE-TD128E (MS-8940) (secondary display) + 196d 1087 X300SE HM + 5b72 RV380 [Radeon X600] + 5b73 RV370 secondary [Sapphire X550 Silent] + 5b74 RV370 5B64 [FireGL V3100 (PCIE)] (Secondary) + 5c61 M9+ 5C61 [Radeon Mobility 9200 (AGP)] + 5c63 M9+ 5C63 [Radeon Mobility 9200 (AGP)] + 1002 5c63 Apple iBook G4 2004 + 5d44 RV280 [Radeon 9200 SE] (Secondary) + 1458 4019 Radeon 9200 SE (Secondary) + 1458 4032 Radeon 9200 SE 128MB + 174b 7c12 Sapphire Radeon 9200 SE (Secondary) + 1787 5965 Excalibur 9200SE VIVO 128M (Secondary) + 17af 2013 Radeon 9200 SE Excalibur (Secondary) + 18bc 0171 Radeon 9200 SE 128MB Game Buster (Secondary) + 18bc 0172 GC-R9200L(SE)-C3H [Radeon 9200 Game Buster] + 5d48 M28 [Radeon Mobility X800XT] + 5d49 M28 [Mobility FireGL V5100] + 5d4a Mobility Radeon X800 + 5d4d R480 [Radeon X850XT Platinum (PCIE)] + 5d4f R480 [Radeon X800 GTO (PCIE)] + 5d52 R480 [Radeon X850XT (PCIE)] (Primary) + 1002 0b12 PowerColor X850XT PCIe Primary + 1002 0b13 PowerColor X850XT PCIe Secondary + 5d57 R423 5F57 [Radeon X800XT (PCIE)] + 5d6d R480 [Radeon X850XT Platinum (PCIE)] (Secondary) + 5d6f R480 [Radeon X800 GTO (PCIE)] (Secondary) + 5d72 R480 [Radeon X850XT (PCIE)] (Secondary) + 5d77 R423 5F57 [Radeon X800XT (PCIE)] (Secondary) + 5e48 RV410 [FireGL V5000] + 5e49 RV410 [FireGL V3300] + 5e4a RV410 [Radeon X700XT] + 5e4b RV410 [Radeon X700 Pro (PCIE)] + 5e4c RV410 [Radeon X700SE] + 5e4d RV410 [Radeon X700 (PCIE)] + 148c 2116 PowerColor Bravo X700 + 5e4f RV410 [Radeon X700] + 5e6b RV410 [Radeon X700 Pro (PCIE)] Secondary + 5e6d RV410 [Radeon X700 (PCIE)] (Secondary) + 148c 2117 PowerColor Bravo X700 + 5f57 R423 [Radeon X800XT (PCIE)] + 700f PCI Bridge [IGP 320M] + 7010 PCI Bridge [IGP 340M] + 7100 R520 [Radeon X1800] + 7102 M58 [Radeon Mobility X1800] + 7103 M58 [Mobility FireGL V7200] + 7104 R520 GL ATI FireGL V7200 Primary + 7105 R520 [FireGL] + 7106 M58 [Mobility FireGL V7100] + 7108 M58 [Radeon Mobility X1800] + 7109 R520 [Radeon X1800] + 1002 0322 All-in-Wonder X1800XL + 1002 0d02 Radeon X1800 CrossFire Edition + 710a R520 [Radeon X1800] + 710b R520 [Radeon X1800] + 710c R520 [Radeon X1800] + 7120 R520 [Radeon X1800] (Secondary) + 7124 R520 GL ATI FireGL V7200 Secondary + 7129 R520 [Radeon X1800] (Secondary) + 1002 0323 All-in-Wonder X1800XL (Secondary) + 1002 0d03 Radeon X1800 CrossFire Edition (Secondary) + 7140 RV515 [Radeon X1600] + 7142 RV515 [Radeon X1300] + 1002 0322 All-in-Wonder 2006 PCI-E Edition + 7145 Radeon Mobility X1400 + 7146 RV515 [Radeon X1300] + 1002 0322 All-in-Wonder 2006 PCI-E Edition + 7149 M52 [ATI Mobility Radeon X1300] + 714a M52 [ATI Mobility Radeon X1300] + 714b M52 [ATI Mobility Radeon X1300] + 714c M52 [ATI Mobility Radeon X1300] + 714d RV515 [Radeon X1300] + 714e RV515 [Radeon X1300] + 7152 RV515 GL ATI FireGL V3300 Primary + 715e RV515 [Radeon X1300] + 7162 RV515 [Radeon X1300] (Secondary) + 1002 0323 All-in-Wonder 2006 PCI-E Edition (Secondary) + 7166 RV515 [Radeon X1300] (Secondary) + 1002 0323 All-in-Wonder 2006 PCI-E Edition (Secondary) + 7172 RV515 GL ATI FireGL V3300 Secondary + 7180 RV516 Radeon X1300 Series Primary + 7181 RV516 XT Radeon X1600 Series Primary + 71a0 RV516 Radeon X1300 Series Secondary + 71a1 RV516 XT Radeon X1600 Series Secondary + 71c0 RV530 [Radeon X1600] + 71c2 RV530 [Radeon X1600] + 71c4 M56GL [ATI Mobility FireGL V5200] + 17aa 2007 ThinkPad T60p + 71c5 M56P [Radeon Mobility X1600] + 71c6 RV530LE [Radeon X1600] + 71ce RV530LE [Radeon X1600] + 71d5 M66-P ATI Mobility Radeon X1700 + 71d6 M66-XT ATI Mobility Radeon X1700 + 71de RV530LE [Radeon X1600] + 71e0 RV530 [Radeon X1600] (Secondary) + 71e2 RV530 [Radeon X1600] (Secondary) + 7240 R580 [Radeon X1900] + 7241 R580 [Radeon X1900] + 7242 R580 [Radeon X1900] + 7243 R580 [Radeon X1900] + 7244 R580 [Radeon X1900] + 7245 R580 [Radeon X1900] + 7246 R580 [Radeon X1900] + 7247 R580 [Radeon X1900] + 7248 R580 [Radeon X1900] + 7249 R580 [Radeon X1900 XT] Primary + 724a R580 [Radeon X1900] + 724b R580 [Radeon X1900] + 724c R580 [Radeon X1900] + 724d R580 [Radeon X1900] + 724e R580 [FireGL V7300/V7350] Primary (PCIE) + 7269 R580 [Radeon X1900 XT] Secondary + 726e R580 [FireGL V7300/V7350] Secondary (PCIE) + 7833 Radeon 9100 IGP Host Bridge + 7834 Radeon 9100 PRO IGP + 7835 Radeon Mobility 9200 IGP + 7838 Radeon 9100 IGP PCI/AGP Bridge + 7c37 RV350 AQ [Radeon 9600 SE] + cab0 AGP Bridge [IGP 320M] + cab2 RS200/RS200M AGP Bridge [IGP 340M] + cab3 R200 AGP Bridge [Mobility Radeon 7000 IGP] + cbb2 RS200/RS200M AGP Bridge [IGP 340M] +1003 ULSI Systems + 0201 US201 +1004 VLSI Technology Inc + 0005 82C592-FC1 + 0006 82C593-FC1 + 0007 82C594-AFC2 + 0008 82C596/7 [Wildcat] + 0009 82C597-AFC2 + 000c 82C541 [Lynx] + 000d 82C543 [Lynx] + 0101 82C532 + 0102 82C534 [Eagle] + 0103 82C538 + 0104 82C535 + 0105 82C147 + 0200 82C975 + 0280 82C925 + 0304 QSound ThunderBird PCI Audio + 1004 0304 QSound ThunderBird PCI Audio + 122d 1206 DSP368 Audio + 1483 5020 XWave Thunder 3D Audio + 0305 QSound ThunderBird PCI Audio Gameport + 1004 0305 QSound ThunderBird PCI Audio Gameport + 122d 1207 DSP368 Audio Gameport + 1483 5021 XWave Thunder 3D Audio Gameport + 0306 QSound ThunderBird PCI Audio Support Registers + 1004 0306 QSound ThunderBird PCI Audio Support Registers + 122d 1208 DSP368 Audio Support Registers + 1483 5022 XWave Thunder 3D Audio Support Registers + 0307 Thunderbird + 0308 Thunderbird + 0702 VAS96011 [Golden Gate II] + 0703 Tollgate +1005 Avance Logic Inc. [ALI] + 2064 ALG2032/2064 + 2128 ALG2364A + 2301 ALG2301 + 2302 ALG2302 + 2364 ALG2364 + 2464 ALG2364A + 2501 ALG2564A/25128A +1006 Reply Group +1007 NetFrame Systems Inc +1008 Epson +100a Phoenix Technologies +100b National Semiconductor Corporation + 0001 DP83810 + 0002 87415/87560 IDE + 000e 87560 Legacy I/O + 000f FireWire Controller + 0011 NS87560 National PCI System I/O + 0012 USB Controller + 0020 DP83815 (MacPhyter) Ethernet Controller + 103c 0024 Pavilion ze4400 builtin Network + 12d9 000c Aculab E1/T1 PMXc cPCI carrier card + 1385 f311 FA311 / FA312 (FA311 with WoL HW) + 0021 PC87200 PCI to ISA Bridge + 0022 DP83820 10/100/1000 Ethernet Controller + 0028 Geode GX2 Host Bridge + 002a CS5535 South Bridge + 002b CS5535 ISA bridge + 002d CS5535 IDE + 002e CS5535 Audio + 002f CS5535 USB + 0030 Geode GX2 Graphics Processor + 0035 DP83065 [Saturn] 10/100/1000 Ethernet Controller + 0500 SCx200 Bridge + 0501 SCx200 SMI + 0502 SCx200 IDE + 0503 SCx200 Audio + 0504 SCx200 Video + 0505 SCx200 XBus + 0510 SC1100 Bridge + 0511 SC1100 SMI + 0515 SC1100 XBus + d001 87410 IDE +100c Tseng Labs Inc + 3202 ET4000/W32p rev A + 3205 ET4000/W32p rev B + 3206 ET4000/W32p rev C + 3207 ET4000/W32p rev D + 3208 ET6000 + 4702 ET6300 +100d AST Research Inc +100e Weitek + 9000 P9000 Viper + 9001 P9000 Viper + 9002 P9000 Viper + 9100 P9100 Viper Pro/SE +1010 Video Logic, Ltd. +1011 Digital Equipment Corporation + 0001 DECchip 21050 + 0002 DECchip 21040 [Tulip] + 0004 DECchip 21030 [TGA] + 0007 NVRAM [Zephyr NVRAM] + 0008 KZPSA [KZPSA] + 0009 DECchip 21140 [FasterNet] + 1025 0310 21140 Fast Ethernet + 10b8 2001 SMC9332BDT EtherPower 10/100 + 10b8 2002 SMC9332BVT EtherPower T4 10/100 + 10b8 2003 SMC9334BDT EtherPower 10/100 (1-port) + 1109 2400 ANA-6944A/TX Fast Ethernet + 1112 2300 RNS2300 Fast Ethernet + 1112 2320 RNS2320 Fast Ethernet + 1112 2340 RNS2340 Fast Ethernet + 1113 1207 EN-1207-TX Fast Ethernet + 1186 1100 DFE-500TX Fast Ethernet + 1186 1112 DFE-570TX Fast Ethernet + 1186 1140 DFE-660 Cardbus Ethernet 10/100 + 1186 1142 DFE-660 Cardbus Ethernet 10/100 + 11f6 0503 Freedomline Fast Ethernet + 1282 9100 AEF-380TXD Fast Ethernet + 1385 1100 FA310TX Fast Ethernet + 2646 0001 KNE100TX Fast Ethernet + 000a 21230 Video Codec + 000d PBXGB [TGA2] + 000f PCI-to-PDQ Interface Chip [PFI] + 1011 def1 FDDI controller (DEFPA) + 103c def1 FDDI controller (3X-DEFPA) + 0014 DECchip 21041 [Tulip Pass 3] + 1186 0100 DE-530+ + 0016 DGLPB [OPPO] + 0017 PV-PCI Graphics Controller (ZLXp-L) + 0019 DECchip 21142/43 + 1011 500a DE500A Fast Ethernet + 1011 500b DE500B Fast Ethernet + 1014 0001 10/100 EtherJet Cardbus + 1025 0315 ALN315 Fast Ethernet + 1033 800c PC-9821-CS01 100BASE-TX Interface Card + 1033 800d PC-9821NR-B06 100BASE-TX Interface Card + 103c 125a 10/100Base-TX (PCI) [A5506B] + 108d 0016 Rapidfire 2327 10/100 Ethernet + 108d 0017 GoCard 2250 Ethernet 10/100 Cardbus + 10b8 2005 SMC8032DT Extreme Ethernet 10/100 + 10b8 8034 SMC8034 Extreme Ethernet 10/100 + 10ef 8169 Cardbus Fast Ethernet + 1109 2a00 ANA-6911A/TX Fast Ethernet + 1109 2b00 ANA-6911A/TXC Fast Ethernet + 1109 3000 ANA-6922/TX Fast Ethernet + 1113 1207 Cheetah Fast Ethernet + 1113 2220 Cardbus Fast Ethernet + 115d 0002 Cardbus Ethernet 10/100 + 1179 0203 Fast Ethernet + 1179 0204 Cardbus Fast Ethernet + 1186 1100 DFE-500TX Fast Ethernet + 1186 1101 DFE-500TX Fast Ethernet + 1186 1102 DFE-500TX Fast Ethernet + 1186 1112 DFE-570TX Quad Fast Ethernet + 1259 2800 AT-2800Tx Fast Ethernet + 1266 0004 Eagle Fast EtherMAX + 12af 0019 NetFlyer Cardbus Fast Ethernet + 1374 0001 Cardbus Ethernet Card 10/100 + 1374 0002 Cardbus Ethernet Card 10/100 + 1374 0007 Cardbus Ethernet Card 10/100 + 1374 0008 Cardbus Ethernet Card 10/100 + 1385 2100 FA510 + 1395 0001 10/100 Ethernet CardBus PC Card + 13d1 ab01 EtherFast 10/100 Cardbus (PCMPC200) + 1498 000a TPMC880-10 10/100Base-T and 10Base2 PMC Ethernet Adapter + 1498 000b TPMC880-11 Single 10/100Base-T PMC Ethernet Adapter + 1498 000c TPMC880-12 Single 10Base2 PMC Ethernet Adapter + 14cb 0100 LNDL-100N 100Base-TX Ethernet PC Card + 8086 0001 EtherExpress PRO/100 Mobile CardBus 32 + 001a Farallon PN9000SX Gigabit Ethernet + 0021 DECchip 21052 + 0022 DECchip 21150 + 0023 DECchip 21150 + 0024 DECchip 21152 + 0025 DECchip 21153 + 0026 DECchip 21154 + 0034 56k Modem Cardbus + 1374 0003 56k Modem Cardbus + 0045 DECchip 21553 + 0046 DECchip 21554 + 0e11 4050 Integrated Smart Array + 0e11 4051 Integrated Smart Array + 0e11 4058 Integrated Smart Array + 103c 10c2 NetRAID-4M + 12d9 000a IP Telephony card + 4c53 1050 CT7 mainboard + 4c53 1051 CE7 mainboard + 9005 0364 5400S (Mustang) + 9005 0365 5400S (Mustang) + 9005 1364 Dell PowerEdge RAID Controller 2 + 9005 1365 Dell PowerEdge RAID Controller 2 + e4bf 1000 CC8-1-BLUES + 1065 StrongARM DC21285 + 1069 0020 DAC960P / DAC1164P +1012 Micronics Computers Inc +1013 Cirrus Logic + 0038 GD 7548 + 0040 GD 7555 Flat Panel GUI Accelerator + 004c GD 7556 Video/Graphics LCD/CRT Ctrlr + 00a0 GD 5430/40 [Alpine] + 00a2 GD 5432 [Alpine] + 00a4 GD 5434-4 [Alpine] + 00a8 GD 5434-8 [Alpine] + 00ac GD 5436 [Alpine] + 00b0 GD 5440 + 00b8 GD 5446 + 00bc GD 5480 + 1013 00bc CL-GD5480 + 00d0 GD 5462 + 00d2 GD 5462 [Laguna I] + 00d4 GD 5464 [Laguna] + 00d5 GD 5464 BD [Laguna] + 00d6 GD 5465 [Laguna] + 13ce 8031 Barco Metheus 2 Megapixel, Dual Head + 13cf 8031 Barco Metheus 2 Megapixel, Dual Head + 00e8 GD 5436U + 1100 CL 6729 + 1110 PD 6832 PCMCIA/CardBus Ctrlr + 1112 PD 6834 PCMCIA/CardBus Ctrlr + 1113 PD 6833 PCMCIA/CardBus Ctrlr + 1200 GD 7542 [Nordic] + 1202 GD 7543 [Viking] + 1204 GD 7541 [Nordic Light] + 4000 MD 5620 [CLM Data Fax Voice] + 4400 CD 4400 + 6001 CS 4610/11 [CrystalClear SoundFusion Audio Accelerator] + 1014 1010 CS4610 SoundFusion Audio Accelerator + 6003 CS 4614/22/24/30 [CrystalClear SoundFusion Audio Accelerator] + 1013 4280 Crystal SoundFusion PCI Audio Accelerator + 1014 0153 ThinkPad A20m + 153b 112e DMX XFire 1024 + 153b 1136 SiXPack 5.1+ + 1681 0050 Game Theater XP + 1681 a011 Fortissimo III 7.1 + 5053 3357 Santa Cruz + 6004 CS 4614/22/24 [CrystalClear SoundFusion Audio Accelerator] + 6005 Crystal CS4281 PCI Audio + 1013 4281 Crystal CS4281 PCI Audio + 10cf 10a8 Crystal CS4281 PCI Audio + 10cf 10a9 Crystal CS4281 PCI Audio + 10cf 10aa Crystal CS4281 PCI Audio + 10cf 10ab Crystal CS4281 PCI Audio + 10cf 10ac Crystal CS4281 PCI Audio + 10cf 10ad Crystal CS4281 PCI Audio + 10cf 10b4 Crystal CS4281 PCI Audio + 1179 0001 Crystal CS4281 PCI Audio + 14c0 000c Crystal CS4281 PCI Audio +1014 IBM + 0002 PCI to MCA Bridge + 0005 Alta Lite + 0007 Alta MP + 000a Fire Coral + 0017 CPU to PCI Bridge + 0018 TR Auto LANstreamer + 001b GXT-150P + 001c Carrera + 001d 82G2675 + 0020 GXT1000 Graphics Adapter + 0022 IBM27-82351 + 002d Python + 002e SCSI RAID Adapter [ServeRAID] + 1014 002e ServeRAID-3x + 1014 022e ServeRAID-4H + 0031 2 Port Serial Adapter +# AS400 iSeries PCI sync serial card + 1014 0031 2721 WAN IOA - 2 Port Sync Serial Adapter + 0036 Miami + 0037 82660 CPU to PCI Bridge + 003a CPU to PCI Bridge + 003c GXT250P/GXT255P Graphics Adapter + 003e 16/4 Token ring UTP/STP controller + 1014 003e Token-Ring Adapter + 1014 00cd Token-Ring Adapter + Wake-On-LAN + 1014 00ce 16/4 Token-Ring Adapter 2 + 1014 00cf 16/4 Token-Ring Adapter Special + 1014 00e4 High-Speed 100/16/4 Token-Ring Adapter + 1014 00e5 16/4 Token-Ring Adapter 2 + Wake-On-LAN + 1014 016d iSeries 2744 Card + 0045 SSA Adapter + 0046 MPIC interrupt controller + 0047 PCI to PCI Bridge + 0048 PCI to PCI Bridge + 0049 Warhead SCSI Controller + 004e ATM Controller (14104e00) + 004f ATM Controller (14104f00) + 0050 ATM Controller (14105000) + 0053 25 MBit ATM Controller + 0054 GXT500P/GXT550P Graphics Adapter + 0057 MPEG PCI Bridge + 0058 SSA Adapter [Advanced SerialRAID/X] + 005c i82557B 10/100 + 005e GXT800P Graphics Adapter + 007c ATM Controller (14107c00) + 007d 3780IDSP [MWave] + 008b EADS PCI to PCI Bridge + 008e GXT3000P Graphics Adapter + 0090 GXT 3000P + 1014 008e GXT-3000P + 0091 SSA Adapter + 0095 20H2999 PCI Docking Bridge + 0096 Chukar chipset SCSI controller + 1014 0097 iSeries 2778 DASD IOA + 1014 0098 iSeries 2763 DASD IOA + 1014 0099 iSeries 2748 DASD IOA + 009f PCI 4758 Cryptographic Accelerator + 00a5 ATM Controller (1410a500) + 00a6 ATM 155MBPS MM Controller (1410a600) + 00b7 256-bit Graphics Rasterizer [Fire GL1] + 1092 00b8 FireGL1 AGP 32Mb + 00b8 GXT2000P Graphics Adapter + 00be ATM 622MBPS Controller (1410be00) + 00dc Advanced Systems Management Adapter (ASMA) + 00fc CPC710 Dual Bridge and Memory Controller (PCI-64) + 0104 Gigabit Ethernet-SX Adapter + 0105 CPC710 Dual Bridge and Memory Controller (PCI-32) + 010f Remote Supervisor Adapter (RSA) + 0142 Yotta Video Compositor Input + 1014 0143 Yotta Input Controller (ytin) + 0144 Yotta Video Compositor Output + 1014 0145 Yotta Output Controller (ytout) + 0156 405GP PLB to PCI Bridge + 015e 622Mbps ATM PCI Adapter + 0160 64bit/66MHz PCI ATM 155 MMF + 016e GXT4000P Graphics Adapter + 0170 GXT6000P Graphics Adapter + 017d GXT300P Graphics Adapter + 0180 Snipe chipset SCSI controller + 1014 0241 iSeries 2757 DASD IOA + 1014 0264 Quad Channel PCI-X U320 SCSI RAID Adapter (2780) + 0188 EADS-X PCI-X to PCI-X Bridge + 01a7 PCI-X to PCI-X Bridge + 01bd ServeRAID Controller + 1014 01be ServeRAID-4M + 1014 01bf ServeRAID-4L + 1014 0208 ServeRAID-4Mx + 1014 020e ServeRAID-4Lx + 1014 022e ServeRAID-4H + 1014 0258 ServeRAID-5i + 1014 0259 ServeRAID-5i + 01c1 64bit/66MHz PCI ATM 155 UTP + 01e6 Cryptographic Accelerator + 01ff 10/100 Mbps Ethernet + 0219 Multiport Serial Adapter + 1014 021a Dual RVX + 1014 0251 Internal Modem/RVX + 1014 0252 Quad Internal Modem + 021b GXT6500P Graphics Adapter + 021c GXT4500P Graphics Adapter + 0233 GXT135P Graphics Adapter + 0266 PCI-X Dual Channel SCSI + 0268 Gigabit Ethernet-SX Adapter (PCI-X) + 0269 10/100/1000 Base-TX Ethernet Adapter (PCI-X) + 028c Citrine chipset SCSI controller + 1014 028d Dual Channel PCI-X DDR SAS RAID Adapter (572E) + 1014 02be Dual Channel PCI-X DDR U320 SCSI RAID Adapter (571B) + 1014 02c0 Dual Channel PCI-X DDR U320 SCSI Adapter (571A) + 1014 030d PCI-X DDR Auxiliary Cache Adapter (575B) + 02a1 Calgary PCI-X Host Bridge + 02bd Obsidian chipset SCSI controller + 1014 02c1 PCI-X DDR 3Gb SAS Adapter (572A/572C) + 1014 02c2 PCI-X DDR 3Gb SAS RAID Adapter (572B/571D) + 0302 Winnipeg PCI-X Host Bridge + 0308 CalIOC2 PCI-E Root Port + 0314 ZISC 036 Neural accelerator card + 3022 QLA3022 Network Adapter + 4022 QLA3022 Network Adapter + ffff MPIC-2 interrupt controller +1015 LSI Logic Corp of Canada +1016 ICL Personal Systems +1017 SPEA Software AG + 5343 SPEA 3D Accelerator +1018 Unisys Systems +1019 Elitegroup Computer Systems +101a AT&T GIS (NCR) + 0005 100VG ethernet +101b Vitesse Semiconductor +101c Western Digital + 0193 33C193A + 0196 33C196A + 0197 33C197A + 0296 33C296A + 3193 7193 + 3197 7197 + 3296 33C296A + 4296 34C296 + 9710 Pipeline 9710 + 9712 Pipeline 9712 + c24a 90C +101e American Megatrends Inc. + 0009 MegaRAID 428 Ultra RAID Controller (rev 03) + 1960 MegaRAID + 101e 0471 MegaRAID 471 Enterprise 1600 RAID Controller + 101e 0475 MegaRAID 475 Express 500/500LC RAID Controller + 101e 0477 MegaRAID 477 Elite 3100 RAID Controller + 101e 0493 MegaRAID 493 Elite 1600 RAID Controller + 101e 0494 MegaRAID 494 Elite 1650 RAID Controller + 101e 0503 MegaRAID 503 Enterprise 1650 RAID Controller + 101e 0511 MegaRAID 511 i4 IDE RAID Controller + 101e 0522 MegaRAID 522 i4133 RAID Controller + 1028 0471 PowerEdge RAID Controller 3/QC + 1028 0475 PowerEdge RAID Controller 3/SC + 1028 0493 PowerEdge RAID Controller 3/DC + 1028 0511 PowerEdge Cost Effective RAID Controller ATA100/4Ch + 103c 60e7 NetRAID-1M + 9010 MegaRAID 428 Ultra RAID Controller + 9030 EIDE Controller + 9031 EIDE Controller + 9032 EIDE & SCSI Controller + 9033 SCSI Controller + 9040 Multimedia card + 9060 MegaRAID 434 Ultra GT RAID Controller + 9063 MegaRAC + 101e 0767 Dell Remote Assistant Card 2 +101f PictureTel +1020 Hitachi Computer Products +1021 OKI Electric Industry Co. Ltd. +1022 Advanced Micro Devices [AMD] + 1100 K8 [Athlon64/Opteron] HyperTransport Technology Configuration + 1101 K8 [Athlon64/Opteron] Address Map + 1102 K8 [Athlon64/Opteron] DRAM Controller + 1103 K8 [Athlon64/Opteron] Miscellaneous Control + 2000 79c970 [PCnet32 LANCE] + 1014 2000 NetFinity 10/100 Fast Ethernet + 1022 2000 PCnet - Fast 79C971 + 103c 104c Ethernet with LAN remote power Adapter + 103c 1064 Ethernet with LAN remote power Adapter + 103c 1065 Ethernet with LAN remote power Adapter + 103c 106c Ethernet with LAN remote power Adapter + 103c 106e Ethernet with LAN remote power Adapter + 103c 10ea Ethernet with LAN remote power Adapter + 1113 1220 EN1220 10/100 Fast Ethernet + 1259 2450 AT-2450 10/100 Fast Ethernet + 1259 2454 AT-2450v4 10Mb Ethernet Adapter + 1259 2700 AT-2700TX 10/100 Fast Ethernet + 1259 2701 AT-2700FX 100Mb Ethernet + 1259 2702 AT-2700FTX 10/100 Mb Fiber/Copper Fast Ethernet + 1259 2703 AT-2701FX + 1259 2704 AT-2701FTX 10/100 Mb Fiber/Copper Fast Ethernet + 4c53 1000 CC7/CR7/CP7/VC7/VP7/VR7 mainboard + 4c53 1010 CP5/CR6 mainboard + 4c53 1020 VR6 mainboard + 4c53 1030 PC5 mainboard + 4c53 1040 CL7 mainboard + 4c53 1060 PC7 mainboard + 2001 79c978 [HomePNA] + 1092 0a78 Multimedia Home Network Adapter + 1668 0299 ActionLink Home Network Adapter + 2003 Am 1771 MBW [Alchemy] + 2020 53c974 [PCscsi] + 2040 79c974 + 2081 Geode LX Video + 2082 Geode LX AES Security Block + 208f CS5536 GeodeLink PCI South Bridge + 2090 CS5536 [Geode companion] ISA + 2091 CS5536 [Geode companion] FLASH + 2093 CS5536 [Geode companion] Audio + 2094 CS5536 [Geode companion] OHC + 2095 CS5536 [Geode companion] EHC + 2096 CS5536 [Geode companion] UDC + 2097 CS5536 [Geode companion] UOC + 209a CS5536 [Geode companion] IDE + 3000 ELanSC520 Microcontroller + 7006 AMD-751 [Irongate] System Controller + 7007 AMD-751 [Irongate] AGP Bridge + 700a AMD-IGR4 AGP Host to PCI Bridge + 700b AMD-IGR4 PCI to PCI Bridge + 700c AMD-760 MP [IGD4-2P] System Controller + 700d AMD-760 MP [IGD4-2P] AGP Bridge + 700e AMD-760 [IGD4-1P] System Controller + 700f AMD-760 [IGD4-1P] AGP Bridge + 7400 AMD-755 [Cobra] ISA + 7401 AMD-755 [Cobra] IDE + 7403 AMD-755 [Cobra] ACPI + 7404 AMD-755 [Cobra] USB + 7408 AMD-756 [Viper] ISA + 7409 AMD-756 [Viper] IDE + 740b AMD-756 [Viper] ACPI + 740c AMD-756 [Viper] USB + 7410 AMD-766 [ViperPlus] ISA + 7411 AMD-766 [ViperPlus] IDE + 7413 AMD-766 [ViperPlus] ACPI + 7414 AMD-766 [ViperPlus] USB + 7440 AMD-768 [Opus] ISA + 1043 8044 A7M-D Mainboard + 7441 AMD-768 [Opus] IDE + 7443 AMD-768 [Opus] ACPI + 1043 8044 A7M-D Mainboard + 7445 AMD-768 [Opus] Audio + 7446 AMD-768 [Opus] MC97 Modem (Smart Link HAMR5600 compatible) + 7448 AMD-768 [Opus] PCI + 7449 AMD-768 [Opus] USB + 7450 AMD-8131 PCI-X Bridge + 7451 AMD-8131 PCI-X IOAPIC + 7454 AMD-8151 System Controller + 7455 AMD-8151 AGP Bridge + 7458 AMD-8132 PCI-X Bridge + 7459 AMD-8132 PCI-X IOAPIC + 7460 AMD-8111 PCI + 161f 3017 HDAMB + 7461 AMD-8111 USB + 7462 AMD-8111 Ethernet + 7464 AMD-8111 USB + 161f 3017 HDAMB + 7468 AMD-8111 LPC + 161f 3017 HDAMB + 7469 AMD-8111 IDE + 1022 2b80 AMD-8111 IDE [Quartet] + 161f 3017 HDAMB + 746a AMD-8111 SMBus 2.0 + 746b AMD-8111 ACPI + 161f 3017 HDAMB + 746d AMD-8111 AC97 Audio + 161f 3017 HDAMB + 746e AMD-8111 MC97 Modem + 756b AMD-8111 ACPI +1023 Trident Microsystems + 0194 82C194 + 2000 4DWave DX + 2001 4DWave NX + 122d 1400 Trident PCI288-Q3DII (NX) + 2100 CyberBlade XP4m32 + 2200 XGI Volari XP5 + 8400 CyberBlade/i7 + 1023 8400 CyberBlade i7 AGP + 8420 CyberBlade/i7d + 0e11 b15a CyberBlade i7 AGP + 8500 CyberBlade/i1 + 8520 CyberBlade i1 + 0e11 b16e CyberBlade i1 AGP + 1023 8520 CyberBlade i1 AGP + 8620 CyberBlade/i1 + 1014 0502 ThinkPad R30/T30 + 1014 1025 Travelmate 352TE + 8820 CyberBlade XPAi1 + 9320 TGUI 9320 + 9350 GUI Accelerator + 9360 Flat panel GUI Accelerator + 9382 Cyber 9382 [Reference design] + 9383 Cyber 9383 [Reference design] + 9385 Cyber 9385 [Reference design] + 9386 Cyber 9386 + 9388 Cyber 9388 + 9397 Cyber 9397 + 939a Cyber 9397DVD + 9420 TGUI 9420 + 9430 TGUI 9430 + 9440 TGUI 9440 + 9460 TGUI 9460 + 9470 TGUI 9470 + 9520 Cyber 9520 + 9525 Cyber 9525 + 10cf 1094 Lifebook C6155 + 9540 Cyber 9540 + 9660 TGUI 9660/938x/968x + 9680 TGUI 9680 + 9682 TGUI 9682 + 9683 TGUI 9683 + 9685 ProVIDIA 9685 + 9750 3DImage 9750 + 1014 9750 3DImage 9750 + 1023 9750 3DImage 9750 + 9753 TGUI 9753 + 9754 TGUI 9754 + 9759 TGUI 975 + 9783 TGUI 9783 + 9785 TGUI 9785 + 9850 3DImage 9850 + 9880 Blade 3D PCI/AGP + 1023 9880 Blade 3D + 9910 CyberBlade/XP + 9930 CyberBlade/XPm +1024 Zenith Data Systems +1025 Acer Incorporated [ALI] + 0090 BCM440x 100Base-TX Fast Ethernet + 1435 M1435 + 1445 M1445 + 1449 M1449 + 1451 M1451 + 1461 M1461 + 1489 M1489 + 1511 M1511 + 1512 ALI M1512 Aladdin + 1513 M1513 + 1521 ALI M1521 Aladdin III CPU Bridge + 10b9 1521 ALI M1521 Aladdin III CPU Bridge + 1523 ALI M1523 ISA Bridge + 10b9 1523 ALI M1523 ISA Bridge + 1531 M1531 Northbridge [Aladdin IV/IV+] + 1533 M1533 PCI-to-ISA Bridge + 10b9 1533 ALI M1533 Aladdin IV/V ISA South Bridge + 1535 M1535 PCI Bridge + Super I/O + FIR + 1541 M1541 Northbridge [Aladdin V] + 10b9 1541 ALI M1541 Aladdin V/V+ AGP+PCI North Bridge + 1542 M1542 Northbridge [Aladdin V] + 1543 M1543 PCI-to-ISA Bridge + Super I/O + FIR + 1561 M1561 Northbridge [Aladdin 7] + 1621 M1621 Northbridge [Aladdin-Pro II] + 1631 M1631 Northbridge+3D Graphics [Aladdin TNT2] + 1641 M1641 Northbridge [Aladdin-Pro IV] + 1647 M1647 [MaGiK1] PCI North Bridge + 1671 M1671 Northbridge [ALADDiN-P4] + 1672 Northbridge [CyberALADDiN-P4] + 3141 M3141 + 3143 M3143 + 3145 M3145 + 3147 M3147 + 3149 M3149 + 3151 M3151 + 3307 M3307 MPEG-I Video Controller + 3309 M3309 MPEG-II Video w/ Software Audio Decoder + 3321 M3321 MPEG-II Audio/Video Decoder + 5212 M4803 + 5215 ALI PCI EIDE Controller + 5217 M5217H + 5219 M5219 + 5225 M5225 + 5229 M5229 + 5235 M5235 + 5237 M5237 PCI USB Host Controller + 5240 EIDE Controller + 5241 PCMCIA Bridge + 5242 General Purpose Controller + 5243 PCI to PCI Bridge Controller + 5244 Floppy Disk Controller + 5247 M1541 PCI to PCI Bridge + 5251 M5251 P1394 Controller + 5427 PCI to AGP Bridge + 5451 M5451 PCI AC-Link Controller Audio Device + 5453 M5453 PCI AC-Link Controller Modem Device + 7101 M7101 PCI PMU Power Management Controller + 10b9 7101 M7101 PCI PMU Power Management Controller +1028 Dell + 0001 PowerEdge Expandable RAID Controller 2/Si + 1028 0001 PowerEdge 2400 + 0002 PowerEdge Expandable RAID Controller 3/Di + 1028 0002 PowerEdge 4400 + 0003 PowerEdge Expandable RAID Controller 3/Si + 1028 0003 PowerEdge 2450 + 0006 PowerEdge Expandable RAID Controller 3/Di + 0007 Remote Access Card III + 0008 Remote Access Card III + 0009 Remote Access Card III: BMC/SMIC device not present + 000a PowerEdge Expandable RAID Controller 3/Di + 000c Embedded Remote Access or ERA/O + 000d Embedded Remote Access: BMC/SMIC device + 000e PowerEdge Expandable RAID controller 4/Di + 000f PowerEdge Expandable RAID controller 4/Di + 0010 Remote Access Card 4 + 0011 Remote Access Card 4 Daughter Card + 0012 Remote Access Card 4 Daughter Card Virtual UART + 0013 PowerEdge Expandable RAID controller 4 + 1028 016c PowerEdge Expandable RAID Controller 4e/Si + 1028 016d PowerEdge Expandable RAID Controller 4e/Di + 1028 016e PowerEdge Expandable RAID Controller 4e/Di + 1028 016f PowerEdge Expandable RAID Controller 4e/Di + 1028 0170 PowerEdge Expandable RAID Controller 4e/Di + 0014 Remote Access Card 4 Daughter Card SMIC interface + 0015 PowerEdge Expandable RAID controller 5i +1029 Siemens Nixdorf IS +102a LSI Logic + 0000 HYDRA + 0010 ASPEN + 001f AHA-2940U2/U2W /7890/7891 SCSI Controllers + 9005 000f 2940U2W SCSI Controller + 9005 0106 2940U2W SCSI Controller + 9005 a180 2940U2W SCSI Controller + 00c5 AIC-7899 U160/m SCSI Controller + 1028 00c5 PowerEdge 2550/2650/4600 + 00cf AIC-7899P U160/m + 1028 0106 PowerEdge 4600 + 1028 0121 PowerEdge 2650 +102b Matrox Graphics, Inc. +# DJ: I've a suspicion that 0010 is a duplicate of 0d10. + 0010 MGA-I [Impression?] + 0100 MGA 1064SG [Mystique] + 0518 MGA-II [Athena] + 0519 MGA 2064W [Millennium] + 051a MGA 1064SG [Mystique] + 102b 0100 MGA-1064SG Mystique + 102b 1100 MGA-1084SG Mystique + 102b 1200 MGA-1084SG Mystique + 1100 102b MGA-1084SG Mystique + 110a 0018 Scenic Pro C5 (D1025) + 051b MGA 2164W [Millennium II] + 102b 051b MGA-2164W Millennium II + 102b 1100 MGA-2164W Millennium II + 102b 1200 MGA-2164W Millennium II + 051e MGA 1064SG [Mystique] AGP + 051f MGA 2164W [Millennium II] AGP + 0520 MGA G200 + 102b dbc2 G200 Multi-Monitor + 102b dbc8 G200 Multi-Monitor + 102b dbe2 G200 Multi-Monitor + 102b dbe8 G200 Multi-Monitor + 102b ff03 Millennium G200 SD + 102b ff04 Marvel G200 + 0521 MGA G200 AGP + 1014 ff03 Millennium G200 AGP + 102b 48e9 Mystique G200 AGP + 102b 48f8 Millennium G200 SD AGP + 102b 4a60 Millennium G200 LE AGP + 102b 4a64 Millennium G200 AGP + 102b c93c Millennium G200 AGP + 102b c9b0 Millennium G200 AGP + 102b c9bc Millennium G200 AGP + 102b ca60 Millennium G250 LE AGP + 102b ca6c Millennium G250 AGP + 102b dbbc Millennium G200 AGP + 102b dbc2 Millennium G200 MMS (Dual G200) + 102b dbc3 G200 Multi-Monitor + 102b dbc8 Millennium G200 MMS (Dual G200) + 102b dbd2 G200 Multi-Monitor + 102b dbd3 G200 Multi-Monitor + 102b dbd4 G200 Multi-Monitor + 102b dbd5 G200 Multi-Monitor + 102b dbd8 G200 Multi-Monitor + 102b dbd9 G200 Multi-Monitor + 102b dbe2 Millennium G200 MMS (Quad G200) + 102b dbe3 G200 Multi-Monitor + 102b dbe8 Millennium G200 MMS (Quad G200) + 102b dbf2 G200 Multi-Monitor + 102b dbf3 G200 Multi-Monitor + 102b dbf4 G200 Multi-Monitor + 102b dbf5 G200 Multi-Monitor + 102b dbf8 G200 Multi-Monitor + 102b dbf9 G200 Multi-Monitor + 102b f806 Mystique G200 Video AGP + 102b ff00 MGA-G200 AGP + 102b ff02 Mystique G200 AGP + 102b ff03 Millennium G200 AGP + 102b ff04 Marvel G200 AGP + 110a 0032 MGA-G200 AGP + 0522 MGA G200e [Pilot] ServerEngines (SEP1) + 0525 MGA G400/G450 + 0e11 b16f MGA-G400 AGP + 102b 0328 Millennium G400 16Mb SDRAM + 102b 0338 Millennium G400 16Mb SDRAM + 102b 0378 Millennium G400 32Mb SDRAM + 102b 0541 Millennium G450 Dual Head + 102b 0542 Millennium G450 Dual Head LX + 102b 0543 Millennium G450 Single Head LX + 102b 0641 Millennium G450 32Mb SDRAM Dual Head + 102b 0642 Millennium G450 32Mb SDRAM Dual Head LX + 102b 0643 Millennium G450 32Mb SDRAM Single Head LX + 102b 07c0 Millennium G450 Dual Head LE + 102b 07c1 Millennium G450 SDR Dual Head LE + 102b 0d41 Millennium G450 Dual Head PCI + 102b 0d42 Millennium G450 Dual Head LX PCI + 102b 0d43 Millennium G450 32Mb Dual Head PCI + 102b 0e00 Marvel G450 eTV + 102b 0e01 Marvel G450 eTV + 102b 0e02 Marvel G450 eTV + 102b 0e03 Marvel G450 eTV + 102b 0f80 Millennium G450 Low Profile + 102b 0f81 Millennium G450 Low Profile + 102b 0f82 Millennium G450 Low Profile DVI + 102b 0f83 Millennium G450 Low Profile DVI + 102b 19d8 Millennium G400 16Mb SGRAM + 102b 19f8 Millennium G400 32Mb SGRAM + 102b 2159 Millennium G400 Dual Head 16Mb + 102b 2179 Millennium G400 MAX/Dual Head 32Mb + 102b 217d Millennium G400 Dual Head Max + 102b 23c0 Millennium G450 + 102b 23c1 Millennium G450 + 102b 23c2 Millennium G450 DVI + 102b 23c3 Millennium G450 DVI + 102b 2f58 Millennium G400 + 102b 2f78 Millennium G400 + 102b 3693 Marvel G400 AGP + 102b 5dd0 4Sight II + 102b 5f50 4Sight II + 102b 5f51 4Sight II + 102b 5f52 4Sight II + 102b 9010 Millennium G400 Dual Head + 1458 0400 GA-G400 + 1705 0001 Millennium G450 32MB SGRAM + 1705 0002 Millennium G450 16MB SGRAM + 1705 0003 Millennium G450 32MB + 1705 0004 Millennium G450 16MB + 0527 MGA Parhelia AGP + 102b 0840 Parhelia 128Mb + 102b 0850 Parhelia 256MB AGP 4X + 0528 Parhelia 8X + 102b 1020 Parhelia 128MB + 102b 1030 Parhelia 256 MB Dual DVI + 102b 14e1 Parhelia PCI 256MB + 102b 2021 QID Pro + 0d10 MGA Ultima/Impression + 1000 MGA G100 [Productiva] + 102b ff01 Productiva G100 + 102b ff05 Productiva G100 Multi-Monitor + 1001 MGA G100 [Productiva] AGP + 102b 1001 MGA-G100 AGP + 102b ff00 MGA-G100 AGP + 102b ff01 MGA-G100 Productiva AGP + 102b ff03 Millennium G100 AGP + 102b ff04 MGA-G100 AGP + 102b ff05 MGA-G100 Productiva AGP Multi-Monitor + 110a 001e MGA-G100 AGP + 2007 MGA Mistral + 2527 MGA G550 AGP + 102b 0f83 Millennium G550 + 102b 0f84 Millennium G550 Dual Head DDR 32Mb + 102b 1e41 Millennium G550 + 2537 Millenium P650/P750 + 102b 1820 Millennium P750 64MB + 102b 1830 Millennium P650 64MB + 102b 1c10 QID 128MB + 102b 2811 Millennium P650 Low-profile PCI 64MB + 102b 2c11 QID Low-profile PCI + 2538 Millenium P650 PCIe + 102b 08c7 Millennium P650 PCIe 128MB + 102b 0907 Millennium P650 PCIe 64MB + 102b 1047 Millennium P650 LP PCIe 128MB + 102b 1087 Millennium P650 LP PCIe 64MB + 102b 2538 Parhelia APVe + 102b 3007 QID Low-profile PCIe + 4536 VIA Framegrabber + 4cdc Morphis Vision System Jpeg2000 + 4fc5 Morphis Vision System + 5e10 Morphis Vision System Aux/IO + 6573 Shark 10/100 Multiport SwitchNIC +102c Chips and Technologies + 00b8 F64310 + 00c0 F69000 HiQVideo + 102c 00c0 F69000 HiQVideo + 4c53 1000 CC7/CR7/CP7/VC7/VP7/VR7 mainboard + 4c53 1010 CP5/CR6 mainboard + 4c53 1020 VR6 mainboard + 4c53 1030 PC5 mainboard + 4c53 1050 CT7 mainboard + 4c53 1051 CE7 mainboard + 00d0 F65545 + 00d8 F65545 + 00dc F65548 + 00e0 F65550 + 00e4 F65554 + 00e5 F65555 HiQVPro + 0e11 b049 Armada 1700 Laptop Display Controller + 1179 0001 Satellite Pro + 00f0 F68554 + 00f4 F68554 HiQVision + 00f5 F68555 + 0c30 F69030 + 4c53 1000 CC7/CR7/CP7/VC7/VP7/VR7 mainboard + 4c53 1050 CT7 mainboard + 4c53 1051 CE7 mainboard + 4c53 1080 CT8 mainboard +102d Wyse Technology Inc. + 50dc 3328 Audio +102e Olivetti Advanced Technology +102f Toshiba America + 0009 r4x00 + 000a TX3927 MIPS RISC PCI Controller + 0020 ATM Meteor 155 + 102f 00f8 ATM Meteor 155 + 0030 TC35815CF PCI 10/100 Mbit Ethernet Controller + 0031 TC35815CF PCI 10/100 Mbit Ethernet Controller with WOL + 0105 TC86C001 [goku-s] IDE + 0106 TC86C001 [goku-s] USB 1.1 Host + 0107 TC86C001 [goku-s] USB Device Controller + 0108 TC86C001 [goku-s] I2C/SIO/GPIO Controller + 0180 TX4927/38 MIPS RISC PCI Controller + 0181 TX4925 MIPS RISC PCI Controller + 0182 TX4937 MIPS RISC PCI Controller +1030 TMC Research +1031 Miro Computer Products AG + 5601 DC20 ASIC + 5607 Video I/O & motion JPEG compressor + 5631 Media 3D + 6057 MiroVideo DC10/DC30+ +1032 Compaq +1033 NEC Corporation + 0000 Vr4181A USB Host or Function Control Unit + 0001 PCI to 486-like bus Bridge + 0002 PCI to VL98 Bridge + 0003 ATM Controller + 0004 R4000 PCI Bridge + 0005 PCI to 486-like bus Bridge + 0006 PC-9800 Graphic Accelerator + 0007 PCI to UX-Bus Bridge + 0008 PC-9800 Graphic Accelerator + 0009 PCI to PC9800 Core-Graph Bridge + 0016 PCI to VL Bridge + 001a [Nile II] + 0021 Vrc4373 [Nile I] + 0029 PowerVR PCX1 + 002a PowerVR 3D + 002c Star Alpha 2 + 002d PCI to C-bus Bridge + 0035 USB + 1033 0035 Hama USB 2.0 CardBus + 1179 0001 USB + 12ee 7000 Root Hub + 14c2 0105 PTI-205N USB 2.0 Host Controller + 1799 0001 Root Hub + 1931 000a GlobeTrotter Fusion Quad Lite (PPP data) + 1931 000b GlobeTrotter Fusion Quad Lite (GSM data) + 807d 0035 PCI-USB2 (OHCI subsystem) + 003b PCI to C-bus Bridge + 003e NAPCCARD Cardbus Controller + 0046 PowerVR PCX2 [midas] + 005a Vrc5074 [Nile 4] + 0063 Firewarden + 0067 PowerVR Neon 250 Chipset + 1010 0020 PowerVR Neon 250 AGP 32Mb + 1010 0080 PowerVR Neon 250 AGP 16Mb + 1010 0088 PowerVR Neon 250 16Mb + 1010 0090 PowerVR Neon 250 AGP 16Mb + 1010 0098 PowerVR Neon 250 16Mb + 1010 00a0 PowerVR Neon 250 AGP 32Mb + 1010 00a8 PowerVR Neon 250 32Mb + 1010 0120 PowerVR Neon 250 AGP 32Mb + 0072 uPD72874 IEEE1394 OHCI 1.1 3-port PHY-Link Ctrlr + 0074 56k Voice Modem + 1033 8014 RCV56ACF 56k Voice Modem + 009b Vrc5476 + 00a5 VRC4173 + 00a6 VRC5477 AC97 + 00cd IEEE 1394 [OrangeLink] Host Controller + 12ee 8011 Root hub + 00ce IEEE 1394 Host Controller + 00df Vr4131 + 00e0 USB 2.0 + 12ee 7001 Root hub + 14c2 0205 PTI-205N USB 2.0 Host Controller + 1799 0002 Root Hub + 807d 1043 PCI-USB2 (EHCI subsystem) + 00e7 IEEE 1394 Host Controller + 00f2 uPD72874 IEEE1394 OHCI 1.1 3-port PHY-Link Ctrlr + 00f3 uPD6113x Multimedia Decoder/Processor [EMMA2] + 010c VR7701 + 0125 uPD720400 PCI Express - PCI/PCI-X Bridge + 013a Dual Tuner/MPEG Encoder +1034 Framatome Connectors USA Inc. +1035 Comp. & Comm. Research Lab +1036 Future Domain Corp. + 0000 TMC-18C30 [36C70] +1037 Hitachi Micro Systems +1038 AMP, Inc +1039 Silicon Integrated Systems [SiS] + 0001 Virtual PCI-to-PCI bridge (AGP) + 0002 SG86C202 + 0003 SiS AGP Port (virtual PCI-to-PCI bridge) + 0004 PCI-to-PCI bridge + 0006 85C501/2/3 + 0008 SiS85C503/5513 (LPC Bridge) + 0009 ACPI + 000a PCI-to-PCI bridge + 0016 SiS961/2 SMBus Controller + 0018 SiS85C503/5513 (LPC Bridge) + 0180 RAID bus controller 180 SATA/PATA [SiS] + 0181 SATA + 0182 182 SATA/RAID Controller + 0186 AHCI Controller (0106) + 0190 190 Gigabit Ethernet Adapter + 0191 191 Gigabit Ethernet Adapter + 0200 5597/5598/6326 VGA + 1039 0000 SiS5597 SVGA (Shared RAM) + 0204 82C204 + 0205 SG86C205 + 0300 300/305 PCI/AGP VGA Display Adapter + 107d 2720 Leadtek WinFast VR300 + 0310 315H PCI/AGP VGA Display Adapter + 0315 315 PCI/AGP VGA Display Adapter + 0325 315PRO PCI/AGP VGA Display Adapter + 0330 330 [Xabre] PCI/AGP VGA Display Adapter + 0406 85C501/2 + 0496 85C496 + 0530 530 Host + 0540 540 Host + 0550 550 Host + 0597 5513C + 0601 85C601 + 0620 620 Host + 0630 630 Host + 0633 633 Host + 0635 635 Host + 0645 SiS645 Host & Memory & AGP Controller + 0646 SiS645DX Host & Memory & AGP Controller + 0648 645xx + 0650 650/M650 Host + 0651 651 Host + 0655 655 Host + 0660 660 Host + 0661 661FX/M661FX/M661MX Host + 0662 662 Host + 0730 730 Host + 0733 733 Host + 0735 735 Host + 0740 740 Host + 0741 741/741GX/M741 Host + 0745 745 Host + 0746 746 Host + 0755 755 Host + 0760 760/M760 Host + 0761 761/M761 Host + 0900 SiS900 PCI Fast Ethernet + 1019 0a14 K7S5A motherboard + 1039 0900 SiS900 10/100 Ethernet Adapter + 1043 8035 CUSI-FX motherboard + 0961 SiS961 [MuTIOL Media IO] + 0962 SiS962 [MuTIOL Media IO] + 0963 SiS963 [MuTIOL Media IO] + 0964 SiS964 [MuTIOL Media IO] + 0965 SiS965 [MuTIOL Media IO] + 0966 SiS966 [MuTIOL Media IO] + 0968 SiS968 [MuTIOL Media IO] + 1180 SATA Controller / IDE mode + 1182 SATA Controller / RAID mode + 1183 SATA Controller / IDE mode + 1184 AHCI Controller / RAID mode + 1185 AHCI IDE Controller (0106) + 3602 83C602 + 5107 5107 + 5300 SiS540 PCI Display Adapter + 5315 550 PCI/AGP VGA Display Adapter + 5401 486 PCI Chipset + 5511 5511/5512 + 5513 5513 [IDE] + 1019 0970 P6STP-FL motherboard + 1039 5513 SiS5513 EIDE Controller (A,B step) + 1043 8035 CUSI-FX motherboard + 5517 5517 + 5571 5571 + 5581 5581 Pentium Chipset + 5582 5582 + 5591 5591/5592 Host + 5596 5596 Pentium Chipset + 5597 5597 [SiS5582] + 5600 5600 Host + 6204 Video decoder & MPEG interface + 6205 VGA Controller + 6236 6236 3D-AGP + 6300 630/730 PCI/AGP VGA Display Adapter + 1019 0970 P6STP-FL motherboard + 1043 8035 CUSI-FX motherboard + 6306 530/620 PCI/AGP VGA Display Adapter + 1039 6306 SiS530,620 GUI Accelerator+3D + 6325 65x/M650/740 PCI/AGP VGA Display Adapter + 6326 86C326 5598/6326 + 1039 6326 SiS6326 GUI Accelerator + 1092 0a50 SpeedStar A50 + 1092 0a70 SpeedStar A70 + 1092 4910 SpeedStar A70 + 1092 4920 SpeedStar A70 + 1569 6326 SiS6326 GUI Accelerator + 6330 661/741/760 PCI/AGP or 662/761Gx PCIE VGA Display Adapter + 1039 6330 [M]661xX/[M]741[GX]/[M]760 PCI/AGP VGA Adapter + 6350 770/670 PCIE VGA Display Adapter + 6351 771/671 PCIE VGA Display Adapter + 7001 USB 1.0 Controller + 1019 0a14 K7S5A motherboard + 1039 7000 Onboard USB Controller + 1462 5470 K7SOM+ 5.2C Motherboard + 7002 USB 2.0 Controller + 1509 7002 Onboard USB Controller + 7007 FireWire Controller + 7012 AC'97 Sound Controller + 15bd 1001 DFI 661FX motherboard +# There are may be different modem codecs here (Intel537 compatible and incompatible) + 7013 AC'97 Modem Controller + 7016 SiS7016 PCI Fast Ethernet Adapter + 1039 7016 SiS7016 10/100 Ethernet Adapter + 7018 SiS PCI Audio Accelerator + 1014 01b6 SiS PCI Audio Accelerator + 1014 01b7 SiS PCI Audio Accelerator + 1019 7018 SiS PCI Audio Accelerator + 1025 000e SiS PCI Audio Accelerator + 1025 0018 SiS PCI Audio Accelerator + 1039 7018 SiS PCI Audio Accelerator + 1043 800b SiS PCI Audio Accelerator + 1054 7018 SiS PCI Audio Accelerator + 107d 5330 SiS PCI Audio Accelerator + 107d 5350 SiS PCI Audio Accelerator + 1170 3209 SiS PCI Audio Accelerator + 1462 400a SiS PCI Audio Accelerator + 14a4 2089 SiS PCI Audio Accelerator + 14cd 2194 SiS PCI Audio Accelerator + 14ff 1100 SiS PCI Audio Accelerator + 152d 8808 SiS PCI Audio Accelerator + 1558 1103 SiS PCI Audio Accelerator + 1558 2200 SiS PCI Audio Accelerator + 1563 7018 SiS PCI Audio Accelerator + 15c5 0111 SiS PCI Audio Accelerator + 270f a171 SiS PCI Audio Accelerator + a0a0 0022 SiS PCI Audio Accelerator + 7019 SiS7019 Audio Accelerator + 7502 Azalia Audio Controller +103a Seiko Epson Corporation +103b Tatung Co. of America +103c Hewlett-Packard Company + 002a NX9000 Notebook + 1005 A4977A Visualize EG + 1008 Visualize FX + 1028 Tach TL Fibre Channel Host Adapter + 1029 Tach XL2 Fibre Channel Host Adapter + 107e 000f Interphase 5560 Fibre Channel Adapter + 9004 9210 1Gb/2Gb Family Fibre Channel Controller + 9004 9211 1Gb/2Gb Family Fibre Channel Controller + 102a Tach TS Fibre Channel Host Adapter + 107e 000e Interphase 5540/5541 Fibre Channel Adapter + 9004 9110 1Gb/2Gb Family Fibre Channel Controller + 9004 9111 1Gb/2Gb Family Fibre Channel Controller + 1030 J2585A DeskDirect 10/100VG NIC + 1031 J2585B HP 10/100VG PCI LAN Adapter + 103c 1040 J2973A DeskDirect 10BaseT NIC + 103c 1041 J2585B DeskDirect 10/100VG NIC + 103c 1042 J2970A DeskDirect 10BaseT/2 NIC + 1040 J2973A DeskDirect 10BaseT NIC + 1041 J2585B DeskDirect 10/100 NIC + 1042 J2970A DeskDirect 10BaseT/2 NIC + 1048 Diva Serial [GSP] Multiport UART + 103c 1049 Tosca Console + 103c 104a Tosca Secondary + 103c 104b Maestro SP2 + 103c 1223 Superdome Console + 103c 1226 Keystone SP2 + 103c 1227 Powerbar SP2 + 103c 1282 Everest SP2 + 103c 1301 Diva RMP3 + 1054 PCI Local Bus Adapter + 1064 79C970 PCnet Ethernet Controller + 108b Visualize FXe + 10c1 NetServer Smart IRQ Router + 10ed TopTools Remote Control + 10f0 rio System Bus Adapter + 10f1 rio I/O Controller + 1200 82557B 10/100 NIC + 1219 NetServer PCI Hot-Plug Controller + 121a NetServer SMIC Controller + 121b NetServer Legacy COM Port Decoder + 121c NetServer PCI COM Port Decoder + 1229 zx1 System Bus Adapter + 122a zx1 I/O Controller + 122e PCI-X Local Bus Adapter + 127b sx1000 System Bus Adapter + 127c sx1000 I/O Controller + 1290 Auxiliary Diva Serial Port + 1291 Auxiliary Diva Serial Port + 12b4 zx1 QuickSilver AGP8x Local Bus Adapter + 12eb sx2000 System Bus Adapter + 12ec sx2000 I/O Controller + 12ee PCI-X 2.0 Local Bus Adapter + 12f8 Broadcom BCM4306 802.11b/g Wireless LAN + 12fa BCM4306 802.11b/g Wireless LAN Controller + 2910 E2910A PCIBus Exerciser + 2925 E2925A 32 Bit, 33 MHzPCI Exerciser & Analyzer + 3080 Pavilion ze2028ea + 3085 Realtek RTL8139/8139C/8139C+ + 3220 Smart Array P600 + 103c 3225 3 Gb/s SAS RAID + 3230 Smart Array Controller + 4030 zx2 System Bus Adapter + 4031 zx2 I/O Controller + 4037 PCIe Local Bus Adapter + 403b PCIe Root Port + 60e8 NetRAID-2M : ZX1/M (OEM AMI MegaRAID 493) +103e Solliday Engineering +103f Synopsys/Logic Modeling Group +1040 Accelgraphics Inc. +1041 Computrend +1042 Micron + 1000 PC Tech RZ1000 + 1001 PC Tech RZ1001 + 3000 Samurai_0 + 3010 Samurai_1 + 3020 Samurai_IDE +1043 ASUSTeK Computer Inc. + 0675 ISDNLink P-IN100-ST-D + 0675 1704 ISDN Adapter (PCI Bus, D, C) + 0675 1707 ISDN Adapter (PCI Bus, DV, W) + 10cf 105e ISDN Adapter (PCI Bus, DV, W) + 0c11 A7N8X Motherboard nForce2 IDE/USB/SMBus + 4015 v7100 SDRAM [GeForce2 MX] + 4021 v7100 Combo Deluxe [GeForce2 MX + TV tuner] + 4057 v8200 GeForce 3 + 8043 v8240 PAL 128M [P4T] Motherboard + 8047 v8420 Deluxe [GeForce4 Ti4200] + 807b v9280/TD [Geforce4 TI4200 8X With TV-Out and DVI] + 8095 A7N8X Motherboard nForce2 AC97 Audio + 80ac A7N8X Motherboard nForce2 AGP/Memory + 80bb v9180 Magic/T [GeForce4 MX440 AGP 8x 64MB TV-out] + 80c5 nForce3 chipset motherboard [SK8N] + 80df v9520 Magic/T + 815a A8N-SLI Motherboard nForce4 SATA + 8187 802.11a/b/g Wireless LAN Card + 8188 Tiger Hybrid TV Capture Device +1044 Adaptec (formerly DPT) + 1012 Domino RAID Engine + a400 SmartCache/Raid I-IV Controller + a500 PCI Bridge + a501 SmartRAID V Controller + 1044 c001 PM1554U2 Ultra2 Single Channel + 1044 c002 PM1654U2 Ultra2 Single Channel + 1044 c003 PM1564U3 Ultra3 Single Channel + 1044 c004 PM1564U3 Ultra3 Dual Channel + 1044 c005 PM1554U2 Ultra2 Single Channel (NON ACPI) + 1044 c00a PM2554U2 Ultra2 Single Channel + 1044 c00b PM2654U2 Ultra2 Single Channel + 1044 c00c PM2664U3 Ultra3 Single Channel + 1044 c00d PM2664U3 Ultra3 Dual Channel + 1044 c00e PM2554U2 Ultra2 Single Channel (NON ACPI) + 1044 c00f PM2654U2 Ultra2 Single Channel (NON ACPI) + 1044 c014 PM3754U2 Ultra2 Single Channel (NON ACPI) + 1044 c015 PM3755U2B Ultra2 Single Channel (NON ACPI) + 1044 c016 PM3755F Fibre Channel (NON ACPI) + 1044 c01e PM3757U2 Ultra2 Single Channel + 1044 c01f PM3757U2 Ultra2 Dual Channel + 1044 c020 PM3767U3 Ultra3 Dual Channel + 1044 c021 PM3767U3 Ultra3 Quad Channel + 1044 c028 PM2865U3 Ultra3 Single Channel + 1044 c029 PM2865U3 Ultra3 Dual Channel + 1044 c02a PM2865F Fibre Channel + 1044 c03c 2000S Ultra3 Single Channel + 1044 c03d 2000S Ultra3 Dual Channel + 1044 c03e 2000F Fibre Channel + 1044 c046 3000S Ultra3 Single Channel + 1044 c047 3000S Ultra3 Dual Channel + 1044 c048 3000F Fibre Channel + 1044 c050 5000S Ultra3 Single Channel + 1044 c051 5000S Ultra3 Dual Channel + 1044 c052 5000F Fibre Channel + 1044 c05a 2400A UDMA Four Channel + 1044 c05b 2400A UDMA Four Channel DAC + 1044 c064 3010S Ultra3 Dual Channel + 1044 c065 3410S Ultra160 Four Channel + 1044 c066 3010S Fibre Channel + a511 SmartRAID V Controller + 1044 c032 ASR-2005S I2O Zero Channel + 1044 c035 ASR-2010S I2O Zero Channel +1045 OPTi Inc. + a0f8 82C750 [Vendetta] USB Controller + c101 92C264 + c178 92C178 + c556 82X556 [Viper] + c557 82C557 [Viper-M] + c558 82C558 [Viper-M ISA+IDE] + c567 82C750 [Vendetta], device 0 + c568 82C750 [Vendetta], device 1 + c569 82C579 [Viper XPress+ Chipset] + c621 82C621 [Viper-M/N+] + c700 82C700 [FireStar] + c701 82C701 [FireStar Plus] + c814 82C814 [Firebridge 1] + c822 82C822 + c824 82C824 + c825 82C825 [Firebridge 2] + c832 82C832 + c861 82C861 + c895 82C895 + c935 EV1935 ECTIVA MachOne PCIAudio + d568 82C825 [Firebridge 2] + d721 IDE [FireStar] +1046 IPC Corporation, Ltd. +1047 Genoa Systems Corp +1048 Elsa AG + 0c60 Gladiac MX + 0d22 Quadro4 900XGL [ELSA GLoria4 900XGL] + 1000 QuickStep 1000 + 3000 QuickStep 3000 + 8901 Gloria XL + 1048 0935 GLoria XL (Virge) +1049 Fountain Technologies, Inc. +# nee SGS Thomson Microelectronics +104a STMicroelectronics + 0008 STG 2000X + 0009 STG 1764X + 0010 STG4000 [3D Prophet Kyro Series] + 0209 STPC Consumer/Industrial North- and Southbridge + 020a STPC Atlas/ConsumerS/Consumer IIA Northbridge + 0210 STPC Atlas ISA Bridge + 021a STPC Consumer S Southbridge + 021b STPC Consumer IIA Southbridge + 0500 ST70137 [Unicorn] ADSL DMT Transceiver + 104a 0500 BeWAN ADSL PCI st + 0564 STPC Client Northbridge + 0981 21x4x DEC-Tulip compatible 10/100 Ethernet + 1746 STG 1764X + 2774 21x4x DEC-Tulip compatible 10/100 Ethernet + 3520 MPEG-II decoder card + 55cc STPC Client Southbridge +104b BusLogic + 0140 BT-946C (old) [multimaster 01] + 1040 BT-946C (BA80C30) [MultiMaster 10] + 8130 Flashpoint LT +104c Texas Instruments + 0500 100 MBit LAN Controller + 0508 TMS380C2X Compressor Interface + 1000 Eagle i/f AS + 104c PCI1510 PC card Cardbus Controller + 3d04 TVP4010 [Permedia] + 3d07 TVP4020 [Permedia 2] + 1011 4d10 Comet + 1040 000f AccelStar II + 1040 0011 AccelStar II + 1048 0a31 WINNER 2000 + 1048 0a32 GLoria Synergy + 1048 0a34 GLoria Synergy + 1048 0a35 GLoria Synergy + 1048 0a36 GLoria Synergy + 1048 0a43 GLoria Synergy + 1048 0a44 GLoria Synergy + 107d 2633 WinFast 3D L2300 + 1092 0127 FIRE GL 1000 PRO + 1092 0136 FIRE GL 1000 PRO + 1092 0141 FIRE GL 1000 PRO + 1092 0146 FIRE GL 1000 PRO + 1092 0148 FIRE GL 1000 PRO + 1092 0149 FIRE GL 1000 PRO + 1092 0152 FIRE GL 1000 PRO + 1092 0154 FIRE GL 1000 PRO + 1092 0155 FIRE GL 1000 PRO + 1092 0156 FIRE GL 1000 PRO + 1092 0157 FIRE GL 1000 PRO + 1097 3d01 Jeronimo Pro + 1102 100f Graphics Blaster Extreme + 3d3d 0100 Reference Permedia 2 3D + 8000 PCILynx/PCILynx2 IEEE 1394 Link Layer Controller + e4bf 1010 CF1-1-SNARE + e4bf 1020 CF1-2-SNARE + 8009 FireWire Controller + 104d 8032 8032 OHCI i.LINK (IEEE 1394) Controller + 8017 PCI4410 FireWire Controller + 8019 TSB12LV23 IEEE-1394 Controller + 11bd 000a Studio DV500-1394 + 11bd 000e Studio DV + e4bf 1010 CF2-1-CYMBAL + 8020 TSB12LV26 IEEE-1394 Controller (Link) + 11bd 000f Studio DV500-1394 + 11bd 001c Excalibur 4.1 + 8021 TSB43AA22 IEEE-1394 Controller (PHY/Link Integrated) + 104d 80df Vaio PCG-FX403 + 104d 80e7 VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP + 8022 TSB43AB22 IEEE-1394a-2000 Controller (PHY/Link) + 8023 TSB43AB22/A IEEE-1394a-2000 Controller (PHY/Link) + 103c 088c NC8000 laptop + 1043 808b K8N4-E Mainboard + 8024 TSB43AB23 IEEE-1394a-2000 Controller (PHY/Link) + 8025 TSB82AA2 IEEE-1394b Link Layer Controller + 1458 1000 GA-K8N Ultra-9 Mainboard + 8026 TSB43AB21 IEEE-1394a-2000 Controller (PHY/Link) + 1025 003c Aspire 2001WLCi (Compaq CL50 motherboard) + 103c 006a NX9500 + 1043 808d A7V333 mainboard. + 8027 PCI4451 IEEE-1394 Controller + 1028 00e6 PCI4451 IEEE-1394 Controller (Dell Inspiron 8100) + 8029 PCI4510 IEEE-1394 Controller + 1028 0163 Latitude D505 + 1028 0196 Inspiron 5160 + 1071 8160 MIM2900 + 802b PCI7410,7510,7610 OHCI-Lynx Controller + 1028 0139 Latitude D400 + 1028 014e PCI7410,7510,7610 OHCI-Lynx Controller (Latitude D800) + 802e PCI7x20 1394a-2000 OHCI Two-Port PHY/Link-Layer Controller + 8031 PCIxx21/x515 Cardbus Controller + 1025 0080 Aspire 5024WLMi + 103c 099c NX6110/NC6120 + 103c 308b MX6125 + 8032 OHCI Compliant IEEE 1394 Host Controller + 1025 0080 Aspire 5024WLMi + 103c 099c NX6110/NC6120 + 103c 308b MX6125 + 8033 PCIxx21 Integrated FlashMedia Controller + 1025 0080 Aspire 5024WLMi + 103c 099c NX6110/NC6120 + 103c 308b MX6125 + 8034 PCI6411/6421/6611/6621/7411/7421/7611/7621 Secure Digital Controller + 1025 0080 Aspire 5024WLMi + 103c 099c NX6110/NC6120 + 103c 308b MX6125 + 8035 PCI6411/6421/6611/6621/7411/7421/7611/7621 Smart Card Controller + 103c 099c NX6110/NC6120 + 8036 PCI6515 Cardbus Controller + 8038 PCI6515 SmartCard Controller + 8039 PCIxx12 Cardbus Controller + 103c 309f nx9420 + 803a PCIxx12 OHCI Compliant IEEE 1394 Host Controller + 103c 309f nx9420 + 803b 5-in-1 Multimedia Card Reader (SD/MMC/MS/MS PRO/xD) + 103c 309f nx9420 + 803c PCIxx12 SDA Standard Compliant SD Host Controller + 103c 309f nx9420 + 803d PCIxx12 GemCore based SmartCard controller + 103c 309f nx9420 + 8201 PCI1620 Firmware Loading Function + 8204 PCI7410,7510,7610 PCI Firmware Loading Function + 1028 0139 Latitude D400 + 1028 014e Latitude D800 + 8231 XIO2000(A)/XIO2200(A) PCI Express-to-PCI Bridge + 8235 XIO2200(A) IEEE-1394a-2000 Controller (PHY/Link) + 8400 ACX 100 22Mbps Wireless Interface + 1186 3b00 DWL-650+ PC Card cardbus 22Mbs Wireless Adapter [AirPlus] + 1186 3b01 DWL-520+ 22Mbps PCI Wireless Adapter + 16ab 8501 WL-8305 IEEE802.11b+ Wireless LAN PCI Adapter + 8401 ACX 100 22Mbps Wireless Interface + 9000 Wireless Interface (of unknown type) + 9065 TMS320DM642 + 9066 ACX 111 54Mbps Wireless Interface + 104c 9066 Trendnet TEW-421PC Wireless PCI Adapter + 1186 3b04 DWL-G520+ Wireless PCI Adapter + 1186 3b05 DWL-G650+ AirPlusG+ CardBus Wireless LAN + 13d1 aba0 SWLMP-54108 108Mbps Wireless mini PCI card 802.11g+ + 1737 0033 WPC54G Ver.2 802.11G PC Card + a001 TDC1570 + a100 TDC1561 + a102 TNETA1575 HyperSAR Plus w/PCI Host i/f & UTOPIA i/f + a106 TMS320C6414 TMS320C6415 TMS320C6416 + 175c 5000 ASI50xx Audio Adapter + 175c 6400 ASI6400 Cobranet series + 175c 8700 ASI87xx Radio Tuner card + ac10 PCI1050 + ac11 PCI1053 + ac12 PCI1130 + ac13 PCI1031 + ac15 PCI1131 + ac16 PCI1250 + 1014 0092 ThinkPad 600 + ac17 PCI1220 + ac18 PCI1260 + ac19 PCI1221 + ac1a PCI1210 + ac1b PCI1450 + 0e11 b113 Armada M700 + 1014 0130 Thinkpad T20/T22/A21m + ac1c PCI1225 + 0e11 b121 Armada E500 + 1028 0088 Latitude CPi A400XT + ac1d PCI1251A + ac1e PCI1211 + ac1f PCI1251B + ac20 TI 2030 + ac21 PCI2031 + ac22 PCI2032 PCI Docking Bridge + ac23 PCI2250 PCI-to-PCI Bridge + ac28 PCI2050 PCI-to-PCI Bridge + ac30 PCI1260 PC card Cardbus Controller + ac40 PCI4450 PC card Cardbus Controller + ac41 PCI4410 PC card Cardbus Controller + ac42 PCI4451 PC card Cardbus Controller + 1028 00e6 PCI4451 PC card CardBus Controller (Inspiron 8100) + ac44 PCI4510 PC card Cardbus Controller + 1028 0163 Latitude D505 + 1028 0196 Inspiron 5160 + 1071 8160 MIM2000 + ac46 PCI4520 PC card Cardbus Controller + ac47 PCI7510 PC card Cardbus Controller + 1028 0139 Latitude D400 + 1028 013f Precision M60 + 1028 014e Latitude D800 + ac4a PCI7510,7610 PC card Cardbus Controller + 1028 0139 Latitude D400 + 1028 014e Latitude D800 + ac50 PCI1410 PC card Cardbus Controller + ac51 PCI1420 + 0e11 004e Evo N600c + 1014 0148 ThinkPad A20m + 1014 023b ThinkPad T23 (2647-4MG) + 1028 00b1 Latitude C600 + 1028 012a Latitude C640 + 1033 80cd Versa Note VXi + 1095 10cf Fujitsu-Siemens LifeBook C Series + 10cf 1095 Lifebook S-4510/C6155 + e4bf 1000 CP2-2-HIPHOP + ac52 PCI1451 PC card Cardbus Controller + ac53 PCI1421 PC card Cardbus Controller + ac54 PCI1620 PC Card Controller + 103c 08b0 tc1100 tablet + ac55 PCI1520 PC card Cardbus Controller + 1014 0512 ThinkPad T30/T40 + ac56 PCI1510 PC card Cardbus Controller + 1014 0512 Thinkpad R50e model 1634 + 1014 0528 ThinkPad R40e (2684-HVG) Cardbus Controller + 17aa 2012 Thinkpad R60e model 0657 + ac60 PCI2040 PCI to DSP Bridge Controller + 175c 5100 ASI51xx Audio Adapter + 175c 6100 ASI61xx Audio Adapter + 175c 6200 ASI62xx Audio Adapter + 175c 8800 ASI88xx Audio Adapter + ac8d PCI 7620 + ac8e PCI7420 CardBus Controller + ac8f PCI7420/7620 Combo CardBus, 1394a-2000 OHCI and SD/MS-Pro Controller + fe00 FireWire Host Controller + fe03 12C01A FireWire Host Controller +104d Sony Corporation + 8004 DTL-H2500 [Playstation development board] + 8009 CXD1947Q i.LINK Controller + 8039 CXD3222 i.LINK Controller + 8056 Rockwell HCF 56K modem + 808a Memory Stick Controller +104e Oak Technology, Inc + 0017 OTI-64017 + 0107 OTI-107 [Spitfire] + 0109 Video Adapter + 0111 OTI-64111 [Spitfire] + 0217 OTI-64217 + 0317 OTI-64317 +104f Co-time Computer Ltd +1050 Winbond Electronics Corp + 0000 NE2000 + 0001 W83769F + 0033 W89C33D 802.11 a/b/g BB/MAC + 0105 W82C105 + 0840 W89C840 + 1050 0001 W89C840 Ethernet Adapter + 1050 0840 W89C840 Ethernet Adapter + 0940 W89C940 + 5a5a W89C940F + 6692 W6692 + 1043 1702 ISDN Adapter (PCI Bus, D, W) + 1043 1703 ISDN Adapter (PCI Bus, DV, W) + 1043 1707 ISDN Adapter (PCI Bus, DV, W) + 144f 1702 ISDN Adapter (PCI Bus, D, W) + 144f 1703 ISDN Adapter (PCI Bus, DV, W) + 144f 1707 ISDN Adapter (PCI Bus, DV, W) + 9921 W99200F MPEG-1 Video Encoder + 9922 W99200F/W9922PF MPEG-1/2 Video Encoder + 9970 W9970CF +1051 Anigma, Inc. +1052 ?Young Micro Systems +1053 Young Micro Systems +1054 Hitachi, Ltd +1055 Efar Microsystems + 9130 SLC90E66 [Victory66] IDE + 9460 SLC90E66 [Victory66] ISA + 9462 SLC90E66 [Victory66] USB + 9463 SLC90E66 [Victory66] ACPI +1056 ICL +# Motorola made a mistake and used 1507 instead of 1057 in some chips. Please look at the 1507 entry as well when updating this. +1057 Motorola + 0001 MPC105 [Eagle] + 0002 MPC106 [Grackle] + 0003 MPC8240 [Kahlua] + 0004 MPC107 + 0006 MPC8245 [Unity] + 0008 MPC8540 + 0009 MPC8560 + 0012 MPC8548 [PowerQUICC III] + 0100 MC145575 [HFC-PCI] + 0431 KTI829c 100VG + 1801 DSP56301 Digital Signal Processor + 14fb 0101 Transas Radar Imitator Board [RIM] + 14fb 0102 Transas Radar Imitator Board [RIM-2] + 14fb 0202 Transas Radar Integrator Board [RIB-2] + 14fb 0611 1 channel CAN bus Controller [CanPci-1] + 14fb 0612 2 channels CAN bus Controller [CanPci-2] + 14fb 0613 3 channels CAN bus Controller [CanPci-3] + 14fb 0614 4 channels CAN bus Controller [CanPci-4] + 14fb 0621 1 channel CAN bus Controller [CanPci2-1] + 14fb 0622 2 channels CAN bus Controller [CanPci2-2] + 14fb 0810 Transas VTS Radar Integrator Board [RIB-4] + 175c 4200 ASI4215 Audio Adapter + 175c 4300 ASI43xx Audio Adapter + 175c 4400 ASI4401 Audio Adapter + ecc0 0010 Darla + ecc0 0020 Gina + ecc0 0030 Layla rev.0 + ecc0 0031 Layla rev.1 + ecc0 0040 Darla24 rev.0 + ecc0 0041 Darla24 rev.1 + ecc0 0050 Gina24 rev.0 + ecc0 0051 Gina24 rev.1 + ecc0 0070 Mona rev.0 + ecc0 0071 Mona rev.1 + ecc0 0072 Mona rev.2 + 18c0 MPC8265A/8266/8272 + 18c1 MPC8271/MPC8272 + 3055 SM56 Data Fax Modem + 3410 DSP56361 Digital Signal Processor + ecc0 0050 Gina24 rev.0 + ecc0 0051 Gina24 rev.1 + ecc0 0060 Layla24 + ecc0 0070 Mona rev.0 + ecc0 0071 Mona rev.1 + ecc0 0072 Mona rev.2 + ecc0 0080 Mia rev.0 + ecc0 0081 Mia rev.1 + ecc0 0090 Indigo + ecc0 00a0 Indigo IO + ecc0 00b0 Indigo DJ + ecc0 0100 3G + 4801 Raven + 4802 Falcon + 4803 Hawk + 4806 CPX8216 + 4d68 20268 + 5600 SM56 PCI Modem + 1057 0300 SM56 PCI Speakerphone Modem + 1057 0301 SM56 PCI Voice Modem + 1057 0302 SM56 PCI Fax Modem + 1057 5600 SM56 PCI Voice modem + 13d2 0300 SM56 PCI Speakerphone Modem + 13d2 0301 SM56 PCI Voice modem + 13d2 0302 SM56 PCI Fax Modem + 1436 0300 SM56 PCI Speakerphone Modem + 1436 0301 SM56 PCI Voice modem + 1436 0302 SM56 PCI Fax Modem + 144f 100c SM56 PCI Fax Modem + 1494 0300 SM56 PCI Speakerphone Modem + 1494 0301 SM56 PCI Voice modem + 14c8 0300 SM56 PCI Speakerphone Modem + 14c8 0302 SM56 PCI Fax Modem + 1668 0300 SM56 PCI Speakerphone Modem + 1668 0302 SM56 PCI Fax Modem + 5608 Wildcard X100P + 5803 MPC5200 + 5806 MCF54 Coldfire + 5808 MPC8220 + 5809 MPC5200B + 6400 MPC190 Security Processor (S1 family, encryption) + 6405 MPC184 Security Processor (S1 family) +1058 Electronics & Telecommunications RSH +1059 Teknor Industrial Computers Inc +105a Promise Technology, Inc. + 0d30 PDC20265 (FastTrak100 Lite/Ultra100) + 105a 4d33 Ultra100 + 0d38 20263 + 105a 4d39 Fasttrak66 + 1275 20275 + 3318 PDC20318 (SATA150 TX4) + 3319 PDC20319 (FastTrak S150 TX4) + 8086 3427 S875WP1-E mainboard + 3371 PDC20371 (FastTrak S150 TX2plus) + 3373 PDC20378 (FastTrak 378/SATA 378) + 1043 80f5 K8V Deluxe/PC-DL Deluxe motherboard + 1462 702e K8T NEO FIS2R motherboard + 3375 PDC20375 (SATA150 TX2plus) + 3376 PDC20376 (FastTrak 376) + 1043 809e A7V8X motherboard + 3515 PDC40719 [FastTrak TX4300/TX4310] + 3519 PDC40519 (FastTrak TX4200) + 3570 20771 (FastTrak TX2300) + 3571 PDC20571 (FastTrak TX2200) + 3574 PDC20579 SATAII 150 IDE Controller + 3577 PDC40779 (SATA 300 779) + 3d17 PDC40718 (SATA 300 TX4) + 3d18 PDC20518/PDC40518 (SATAII 150 TX4) + 3d73 PDC40775 (SATA 300 TX2plus) + 3d75 PDC20575 (SATAII150 TX2plus) + 4302 80333 [SuperTrak EX4350] + 4d30 PDC20267 (FastTrak100/Ultra100) + 105a 4d33 Ultra100 + 105a 4d39 FastTrak100 + 4d33 20246 + 105a 4d33 20246 IDE Controller + 4d38 PDC20262 (FastTrak66/Ultra66) + 105a 4d30 Ultra Device on SuperTrak + 105a 4d33 Ultra66 + 105a 4d39 FastTrak66 + 4d68 PDC20268 (Ultra100 TX2) + 105a 4d68 Ultra100TX2 + 4d69 20269 + 105a 4d68 Ultra133TX2 + 5275 PDC20276 (MBFastTrak133 Lite) + 1043 807e A7V333 motherboard. + 105a 0275 SuperTrak SX6000 IDE + 105a 1275 MBFastTrak133 Lite (tm) Controller (RAID mode) + 1458 b001 MBUltra 133 + 5300 DC5300 + 6268 PDC20270 (FastTrak100 LP/TX2/TX4) + 105a 4d68 FastTrak100 TX2 + 6269 PDC20271 (FastTrak TX2000) + 105a 6269 FastTrak TX2/TX2000 + 6621 PDC20621 (FastTrak S150 SX4/FastTrak SX4000 lite) + 6622 PDC20621 [SATA150 SX4] 4 Channel IDE RAID Controller + 6624 PDC20621 [FastTrak SX4100] + 6626 PDC20618 (Ultra 618) + 6629 PDC20619 (FastTrak TX4000) + 7275 PDC20277 (SBFastTrak133 Lite) + 8002 SATAII150 SX8 + 8350 80333 [SuperTrak EX8350/EX16350], 80331 [SuperTrak EX8300/EX16300] + c350 80333 [SuperTrak EX12350] +105b Foxconn International, Inc. +105c Wipro Infotech Limited +105d Number 9 Computer Company + 2309 Imagine 128 + 2339 Imagine 128-II + 105d 0000 Imagine 128 series 2 4Mb VRAM + 105d 0001 Imagine 128 series 2 4Mb VRAM + 105d 0002 Imagine 128 series 2 4Mb VRAM + 105d 0003 Imagine 128 series 2 4Mb VRAM + 105d 0004 Imagine 128 series 2 4Mb VRAM + 105d 0005 Imagine 128 series 2 4Mb VRAM + 105d 0006 Imagine 128 series 2 4Mb VRAM + 105d 0007 Imagine 128 series 2 4Mb VRAM + 105d 0008 Imagine 128 series 2e 4Mb DRAM + 105d 0009 Imagine 128 series 2e 4Mb DRAM + 105d 000a Imagine 128 series 2 8Mb VRAM + 105d 000b Imagine 128 series 2 8Mb H-VRAM + 11a4 000a Barco Metheus 5 Megapixel + 13cc 0000 Barco Metheus 5 Megapixel + 13cc 0004 Barco Metheus 5 Megapixel + 13cc 0005 Barco Metheus 5 Megapixel + 13cc 0006 Barco Metheus 5 Megapixel + 13cc 0008 Barco Metheus 5 Megapixel + 13cc 0009 Barco Metheus 5 Megapixel + 13cc 000a Barco Metheus 5 Megapixel + 13cc 000c Barco Metheus 5 Megapixel + 493d Imagine 128 T2R [Ticket to Ride] + 11a4 000a Barco Metheus 5 Megapixel, Dual Head + 11a4 000b Barco Metheus 5 Megapixel, Dual Head + 13cc 0002 Barco Metheus 4 Megapixel, Dual Head + 13cc 0003 Barco Metheus 5 Megapixel, Dual Head + 13cc 0007 Barco Metheus 5 Megapixel, Dual Head + 13cc 0008 Barco Metheus 5 Megapixel, Dual Head + 13cc 0009 Barco Metheus 5 Megapixel, Dual Head + 13cc 000a Barco Metheus 5 Megapixel, Dual Head + 5348 Revolution 4 + 105d 0037 Revolution IV-FP AGP (For SGI 1600SW) + 11a4 0028 PVS5600M + 11a4 0038 PVS5600D +105e Vtech Computers Ltd +105f Infotronic America Inc +1060 United Microelectronics [UMC] + 0001 UM82C881 + 0002 UM82C886 + 0101 UM8673F + 0881 UM8881 + 0886 UM8886F + 0891 UM8891A + 1001 UM886A + 673a UM8886BF + 673b EIDE Master/DMA + 8710 UM8710 + 886a UM8886A + 8881 UM8881F + 8886 UM8886F + 888a UM8886A + 8891 UM8891A + 9017 UM9017F + 9018 UM9018 + 9026 UM9026 + e881 UM8881N + e886 UM8886N + e88a UM8886N + e891 UM8891N +1061 I.I.T. + 0001 AGX016 + 0002 IIT3204/3501 +1062 Maspar Computer Corp +1063 Ocean Office Automation +1064 Alcatel +1065 Texas Microsystems +1066 PicoPower Technology + 0000 PT80C826 + 0001 PT86C521 [Vesuvius v1] Host Bridge + 0002 PT86C523 [Vesuvius v3] PCI-ISA Bridge Master + 0003 PT86C524 [Nile] PCI-to-PCI Bridge + 0004 PT86C525 [Nile-II] PCI-to-PCI Bridge + 0005 National PC87550 System Controller + 8002 PT86C523 [Vesuvius v3] PCI-ISA Bridge Slave +1067 Mitsubishi Electric + 0301 AccelGraphics AccelECLIPSE + 0304 AccelGALAXY A2100 [OEM Evans & Sutherland] + 0308 Tornado 3000 [OEM Evans & Sutherland] + 1002 VG500 [VolumePro Volume Rendering Accelerator] +1068 Diversified Technology +1069 Mylex Corporation + 0001 DAC960P + 0002 DAC960PD + 0010 DAC960PG + 0020 DAC960LA + 0050 AcceleRAID 352/170/160 support Device + 1069 0050 AcceleRAID 352 support Device + 1069 0052 AcceleRAID 170 support Device + 1069 0054 AcceleRAID 160 support Device + b166 AcceleRAID 600/500/400/Sapphire support Device + 1014 0242 iSeries 2872 DASD IOA + 1014 0266 Dual Channel PCI-X U320 SCSI Adapter + 1014 0278 Dual Channel PCI-X U320 SCSI RAID Adapter + 1014 02d3 Dual Channel PCI-X U320 SCSI Adapter + 1014 02d4 Dual Channel PCI-X U320 SCSI RAID Adapter + 1069 0200 AcceleRAID 400, Single Channel, PCI-X, U320, SCSI RAID + 1069 0202 AcceleRAID Sapphire, Dual Channel, PCI-X, U320, SCSI RAID + 1069 0204 AcceleRAID 500, Dual Channel, Low-Profile, PCI-X, U320, SCSI RAID + 1069 0206 AcceleRAID 600, Dual Channel, PCI-X, U320, SCSI RAID + ba55 eXtremeRAID 1100 support Device + ba56 eXtremeRAID 2000/3000 support Device + 1069 0030 eXtremeRAID 3000 support Device + 1069 0040 eXtremeRAID 2000 support Device + ba57 eXtremeRAID 4000/5000 support Device + 1069 0072 eXtremeRAID 5000 support Device +106a Aten Research Inc +106b Apple Computer Inc. + 0001 Bandit PowerPC host bridge + 0002 Grand Central I/O + 0003 Control Video + 0004 PlanB Video-In + 0007 O'Hare I/O + 000c DOS on Mac + 000e Hydra Mac I/O + 0010 Heathrow Mac I/O + 0017 Paddington Mac I/O + 0018 UniNorth FireWire + 0019 KeyLargo USB + 001e UniNorth Internal PCI + 001f UniNorth PCI + 0020 UniNorth AGP + 0021 UniNorth GMAC (Sun GEM) + 0022 KeyLargo Mac I/O + 0024 UniNorth/Pangea GMAC (Sun GEM) + 0025 KeyLargo/Pangea Mac I/O + 0026 KeyLargo/Pangea USB + 0027 UniNorth/Pangea AGP + 0028 UniNorth/Pangea PCI + 0029 UniNorth/Pangea Internal PCI + 002d UniNorth 1.5 AGP + 002e UniNorth 1.5 PCI + 002f UniNorth 1.5 Internal PCI + 0030 UniNorth/Pangea FireWire + 0031 UniNorth 2 FireWire + 106b 5811 iBook G4 2004 + 0032 UniNorth 2 GMAC (Sun GEM) + 0033 UniNorth 2 ATA/100 + 0034 UniNorth 2 AGP + 0035 UniNorth 2 PCI + 0036 UniNorth 2 Internal PCI + 003b UniNorth/Intrepid ATA/100 + 003e KeyLargo/Intrepid Mac I/O + 003f KeyLargo/Intrepid USB + 0040 K2 KeyLargo USB + 0041 K2 KeyLargo Mac/IO + 0042 K2 FireWire + 0043 K2 ATA/100 + 0045 K2 HT-PCI Bridge + 0046 K2 HT-PCI Bridge + 0047 K2 HT-PCI Bridge + 0048 K2 HT-PCI Bridge + 0049 K2 HT-PCI Bridge + 004b U3 AGP + 004c K2 GMAC (Sun GEM) + 004f Shasta Mac I/O + 0050 Shasta IDE + 0051 Shasta (Sun GEM) + 0052 Shasta Firewire + 0053 Shasta PCI Bridge + 0054 Shasta PCI Bridge + 0055 Shasta PCI Bridge + 0058 U3L AGP Bridge + 0059 U3H AGP Bridge + 0066 Intrepid2 AGP Bridge + 0067 Intrepid2 PCI Bridge + 0068 Intrepid2 PCI Bridge + 0069 Intrepid2 ATA/100 + 006a Intrepid2 Firewire + 006b Intrepid2 GMAC (Sun GEM) + 1645 Tigon3 Gigabit Ethernet NIC (BCM5701) +106c Hynix Semiconductor + 8801 Dual Pentium ISA/PCI Motherboard + 8802 PowerPC ISA/PCI Motherboard + 8803 Dual Window Graphics Accelerator + 8804 LAN Controller + 8805 100-BaseT LAN +106d Sequent Computer Systems +106e DFI, Inc +106f City Gate Development Ltd +1070 Daewoo Telecom Ltd +1071 Mitac + 8160 Mitac 8060B Mobile Platform +1072 GIT Co Ltd +1073 Yamaha Corporation + 0001 3D GUI Accelerator + 0002 YGV615 [RPA3 3D-Graphics Controller] + 0003 YMF-740 + 0004 YMF-724 + 1073 0004 YMF724-Based PCI Audio Adapter + 0005 DS1 Audio + 1073 0005 DS-XG PCI Audio CODEC + 0006 DS1 Audio + 0008 DS1 Audio + 1073 0008 DS-XG PCI Audio CODEC + 000a DS1L Audio + 1073 0004 DS-XG PCI Audio CODEC + 1073 000a DS-XG PCI Audio CODEC + 000c YMF-740C [DS-1L Audio Controller] + 107a 000c DS-XG PCI Audio CODEC + 000d YMF-724F [DS-1 Audio Controller] + 1073 000d DS-XG PCI Audio CODEC + 0010 YMF-744B [DS-1S Audio Controller] + 1073 0006 DS-XG PCI Audio CODEC + 1073 0010 DS-XG PCI Audio CODEC + 0012 YMF-754 [DS-1E Audio Controller] + 1073 0012 DS-XG PCI Audio Codec + 0020 DS-1 Audio + 2000 DS2416 Digital Mixing Card + 1073 2000 DS2416 Digital Mixing Card +1074 NexGen Microsystems + 4e78 82c500/1 +1075 Advanced Integrations Research +1076 Chaintech Computer Co. Ltd +1077 QLogic Corp. + 1016 ISP10160 Single Channel Ultra3 SCSI Processor + 1020 ISP1020 Fast-wide SCSI + 1022 ISP1022 Fast-wide SCSI + 1080 ISP1080 SCSI Host Adapter + 1216 ISP12160 Dual Channel Ultra3 SCSI Processor + 101e 8471 QLA12160 on AMI MegaRAID + 101e 8493 QLA12160 on AMI MegaRAID + 1240 ISP1240 SCSI Host Adapter + 1280 ISP1280 SCSI Host Adapter + 2020 ISP2020A Fast!SCSI Basic Adapter + 2100 QLA2100 64-bit Fibre Channel Adapter + 1077 0001 QLA2100 64-bit Fibre Channel Adapter + 2200 QLA2200 64-bit Fibre Channel Adapter + 1077 0002 QLA2200 + 2300 QLA2300 64-bit Fibre Channel Adapter + 2312 QLA2312 Fibre Channel Adapter + 103c 0131 2Gb Fibre Channel - Single port [A7538A] + 103c 12ba 2Gb Fibre Channel - Dual port [A6826A] + 2322 QLA2322 Fibre Channel Adapter + 2422 QLA2422 Fibre Channel Adapter + 103c 12d7 4Gb Fibre Channel [AB379A] + 103c 12dd 4Gb Fibre Channel [AB429A] + 2432 QLA2432 Fibre Channel Adapter + 3010 QLA3010 Network Adapter + 3022 QLA3022 Network Adapter + 4010 QLA4010 iSCSI TOE Adapter + 4022 QLA4022 iSCSI TOE Adapter + 6312 QLA6312 Fibre Channel Adapter + 6322 QLA6322 Fibre Channel Adapter +1078 Cyrix Corporation + 0000 5510 [Grappa] + 0001 PCI Master + 0002 5520 [Cognac] + 0100 5530 Legacy [Kahlua] + 0101 5530 SMI [Kahlua] + 0102 5530 IDE [Kahlua] + 0103 5530 Audio [Kahlua] + 0104 5530 Video [Kahlua] + 0400 ZFMicro PCI Bridge + 0401 ZFMicro Chipset SMI + 0402 ZFMicro Chipset IDE + 0403 ZFMicro Expansion Bus +1079 I-Bus +107a NetWorth +107b Gateway 2000 +107c LG Electronics [Lucky Goldstar Co. Ltd] +107d LeadTek Research Inc. + 0000 P86C850 + 204d [GeForce 7800 GTX] Winfast PX7800 GTX TDH + 2134 WinFast 3D S320 II + 2971 [GeForce FX 5900] WinFast A350 TDH MyViVo +107e Interphase Corporation + 0001 5515 ATM Adapter [Flipper] + 0002 100 VG AnyLan Controller + 0004 5526 Fibre Channel Host Adapter + 0005 x526 Fibre Channel Host Adapter + 0008 5525/5575 ATM Adapter (155 Mbit) [Atlantic] + 9003 5535-4P-BRI-ST + 9007 5535-4P-BRI-U + 9008 5535-1P-SR + 900c 5535-1P-SR-ST + 900e 5535-1P-SR-U + 9011 5535-1P-PRI + 9013 5535-2P-PRI + 9023 5536-4P-BRI-ST + 9027 5536-4P-BRI-U + 9031 5536-1P-PRI + 9033 5536-2P-PRI +107f Data Technology Corporation + 0802 SL82C105 +1080 Contaq Microsystems + 0600 82C599 + c691 Cypress CY82C691 + c693 82c693 +1081 Supermac Technology + 0d47 Radius PCI to NuBUS Bridge +1082 EFA Corporation of America +1083 Forex Computer Corporation + 0001 FR710 +1084 Parador +1085 Tulip Computers Int.B.V. +1086 J. Bond Computer Systems +1087 Cache Computer +1088 Microcomputer Systems (M) Son +1089 Data General Corporation +# Formerly Bit3 Computer Corp. +108a SBS Technologies + 0001 VME Bridge Model 617 + 0010 VME Bridge Model 618 + 0040 dataBLIZZARD + 3000 VME Bridge Model 2706 +108c Oakleigh Systems Inc. +108d Olicom + 0001 Token-Ring 16/4 PCI Adapter (3136/3137) + 0002 16/4 Token Ring + 0004 RapidFire 3139 Token-Ring 16/4 PCI Adapter + 108d 0004 OC-3139/3140 RapidFire Token-Ring 16/4 Adapter + 0005 GoCard 3250 Token-Ring 16/4 CardBus PC Card + 0006 OC-3530 RapidFire Token-Ring 100 + 0007 RapidFire 3141 Token-Ring 16/4 PCI Fiber Adapter + 108d 0007 OC-3141 RapidFire Token-Ring 16/4 Adapter + 0008 RapidFire 3540 HSTR 100/16/4 PCI Adapter + 108d 0008 OC-3540 RapidFire HSTR 100/16/4 Adapter + 0011 OC-2315 + 0012 OC-2325 + 0013 OC-2183/2185 + 0014 OC-2326 + 0019 OC-2327/2250 10/100 Ethernet Adapter + 108d 0016 OC-2327 Rapidfire 10/100 Ethernet Adapter + 108d 0017 OC-2250 GoCard 10/100 Ethernet Adapter + 0021 OC-6151/6152 [RapidFire ATM 155] + 0022 ATM Adapter +108e Sun Microsystems Computer Corp. + 0001 EBUS + 1000 EBUS + 1001 Happy Meal + 1100 RIO EBUS + 1101 RIO GEM + 1102 RIO 1394 + 1103 RIO USB + 1648 [bge] Gigabit Ethernet + 2bad GEM + 5000 Simba Advanced PCI Bridge + 5043 SunPCI Co-processor + 8000 Psycho PCI Bus Module + 8001 Schizo PCI Bus Module + 8002 Schizo+ PCI Bus Module + a000 Ultra IIi + a001 Ultra IIe + a801 Tomatillo PCI Bus Module + abba Cassini 10/100/1000 +108f Systemsoft +1090 Compro Computer Services, Inc. +1091 Intergraph Corporation + 0020 3D graphics processor + 0021 3D graphics processor w/Texturing + 0040 3D graphics frame buffer + 0041 3D graphics frame buffer + 0060 Proprietary bus bridge + 00e4 Powerstorm 4D50T + 0720 Motion JPEG codec + 07a0 Sun Expert3D-Lite Graphics Accelerator + 1091 Sun Expert3D Graphics Accelerator +1092 Diamond Multimedia Systems + 00a0 Speedstar Pro SE + 00a8 Speedstar 64 + 0550 Viper V550 + 08d4 Supra 2260 Modem + 094c SupraExpress 56i Pro + 1092 Viper V330 + 6120 Maximum DVD + 8810 Stealth SE + 8811 Stealth 64/SE + 8880 Stealth + 8881 Stealth + 88b0 Stealth 64 + 88b1 Stealth 64 + 88c0 Stealth 64 + 88c1 Stealth 64 + 88d0 Stealth 64 + 88d1 Stealth 64 + 88f0 Stealth 64 + 88f1 Stealth 64 + 9999 DMD-I0928-1 "Monster sound" sound chip +1093 National Instruments + 0160 PCI-DIO-96 + 0162 PCI-MIO-16XE-50 + 1150 PCI-DIO-32HS High Speed Digital I/O Board + 1170 PCI-MIO-16XE-10 + 1180 PCI-MIO-16E-1 + 1190 PCI-MIO-16E-4 + 1310 PCI-6602 + 1330 PCI-6031E + 1350 PCI-6071E + 14e0 PCI-6110 + 14f0 PCI-6111 + 17d0 PCI-6503 + 1870 PCI-6713 + 1880 PCI-6711 + 18b0 PCI-6052E + 2410 PCI-6733 + 2890 PCI-6036E + 2a60 PCI-6023E + 2a70 PCI-6024E + 2a80 PCI-6025E + 2c80 PCI-6035E + 2ca0 PCI-6034E + 70a9 PCI-6528 (Digital I/O at 60V) + 70b8 PCI-6251 [M Series - High Speed Multifunction DAQ] + b001 IMAQ-PCI-1408 + b011 IMAQ-PXI-1408 + b021 IMAQ-PCI-1424 + b031 IMAQ-PCI-1413 + b041 IMAQ-PCI-1407 + b051 IMAQ-PXI-1407 + b061 IMAQ-PCI-1411 + b071 IMAQ-PCI-1422 + b081 IMAQ-PXI-1422 + b091 IMAQ-PXI-1411 + c801 PCI-GPIB + c831 PCI-GPIB bridge +1094 First International Computers [FIC] +# nee CMD Technology Inc +1095 Silicon Image, Inc. + 0240 Adaptec AAR-1210SA SATA HostRAID Controller + 0640 PCI0640 + 0643 PCI0643 + 0646 PCI0646 + 0647 PCI0647 + 0648 PCI0648 + 1043 8025 CUBX motherboard + 0649 SiI 0649 Ultra ATA/100 PCI to ATA Host Controller + 0e11 005d Integrated Ultra ATA-100 Dual Channel Controller + 0e11 007e Integrated Ultra ATA-100 IDE RAID Controller + 101e 0649 AMI MegaRAID IDE 100 Controller + 0650 PBC0650A + 0670 USB0670 + 1095 0670 USB0670 + 0673 USB0673 + 0680 PCI0680 Ultra ATA-133 Host Controller + 1095 3680 Winic W-680 (Silicon Image 680 based) + 3112 SiI 3112 [SATALink/SATARaid] Serial ATA Controller + 1095 3112 SiI 3112 SATALink Controller + 1095 6112 SiI 3112 SATARaid Controller + 9005 0250 SATAConnect 1205SA Host Controller + 3114 SiI 3114 [SATALink/SATARaid] Serial ATA Controller + 1095 3114 SiI 3114 SATALink Controller + 1095 6114 SiI 3114 SATARaid Controller + 3124 SiI 3124 PCI-X Serial ATA Controller + 1095 3124 SiI 3124 PCI-X Serial ATA Controller + 3132 SiI 3132 Serial ATA Raid II Controller + 3512 SiI 3512 [SATALink/SATARaid] Serial ATA Controller + 1095 3512 SiI 3512 SATALink Controller + 1095 6512 SiI 3512 SATARaid Controller +1096 Alacron +1097 Appian Technology +1098 Quantum Designs (H.K.) Ltd + 0001 QD-8500 + 0002 QD-8580 +1099 Samsung Electronics Co., Ltd +109a Packard Bell +109b Gemlight Computer Ltd. +109c Megachips Corporation +109d Zida Technologies Ltd. +109e Brooktree Corporation + 032e Bt878 Video Capture + 0350 Bt848 Video Capture + 0351 Bt849A Video capture + 0369 Bt878 Video Capture + 1002 0001 TV-Wonder + 1002 0003 TV-Wonder/VE + 036c Bt879(??) Video Capture + 13e9 0070 Win/TV (Video Section) + 036e Bt878 Video Capture + 0070 13eb WinTV Series + 0070 ff01 Viewcast Osprey 200 + 0071 0101 DigiTV PCI + 107d 6606 WinFast TV 2000 + 11bd 0012 PCTV pro (TV + FM stereo receiver) + 11bd 001c PCTV Sat (DBC receiver) + 127a 0001 Bt878 Mediastream Controller NTSC + 127a 0002 Bt878 Mediastream Controller PAL BG + 127a 0003 Bt878a Mediastream Controller PAL BG + 127a 0048 Bt878/832 Mediastream Controller + 144f 3000 MagicTView CPH060 - Video + 1461 0002 TV98 Series (TV/No FM/Remote) + 1461 0003 AverMedia UltraTV PCI 350 + 1461 0004 AVerTV WDM Video Capture + 1461 0761 AverTV DVB-T + 1461 0771 AverMedia AVerTV DVB-T 771 + 14f1 0001 Bt878 Mediastream Controller NTSC + 14f1 0002 Bt878 Mediastream Controller PAL BG + 14f1 0003 Bt878a Mediastream Controller PAL BG + 14f1 0048 Bt878/832 Mediastream Controller + 1822 0001 VisionPlus DVB card + 1851 1850 FlyVideo'98 - Video + 1851 1851 FlyVideo II + 1852 1852 FlyVideo'98 - Video (with FM Tuner) + 18ac d500 DViCO FusionHDTV5 Lite + 270f fc00 Digitop DTT-1000 + bd11 1200 PCTV pro (TV + FM stereo receiver) + 036f Bt879 Video Capture + 127a 0044 Bt879 Video Capture NTSC + 127a 0122 Bt879 Video Capture PAL I + 127a 0144 Bt879 Video Capture NTSC + 127a 0222 Bt879 Video Capture PAL BG + 127a 0244 Bt879a Video Capture NTSC + 127a 0322 Bt879 Video Capture NTSC + 127a 0422 Bt879 Video Capture NTSC + 127a 1122 Bt879 Video Capture PAL I + 127a 1222 Bt879 Video Capture PAL BG + 127a 1322 Bt879 Video Capture NTSC + 127a 1522 Bt879a Video Capture PAL I + 127a 1622 Bt879a Video Capture PAL BG + 127a 1722 Bt879a Video Capture NTSC + 14f1 0044 Bt879 Video Capture NTSC + 14f1 0122 Bt879 Video Capture PAL I + 14f1 0144 Bt879 Video Capture NTSC + 14f1 0222 Bt879 Video Capture PAL BG + 14f1 0244 Bt879a Video Capture NTSC + 14f1 0322 Bt879 Video Capture NTSC + 14f1 0422 Bt879 Video Capture NTSC + 14f1 1122 Bt879 Video Capture PAL I + 14f1 1222 Bt879 Video Capture PAL BG + 14f1 1322 Bt879 Video Capture NTSC + 14f1 1522 Bt879a Video Capture PAL I + 14f1 1622 Bt879a Video Capture PAL BG + 14f1 1722 Bt879a Video Capture NTSC + 1851 1850 FlyVideo'98 - Video + 1851 1851 FlyVideo II + 1852 1852 FlyVideo'98 - Video (with FM Tuner) + 0370 Bt880 Video Capture + 1851 1850 FlyVideo'98 + 1851 1851 FlyVideo'98 EZ - video + 1852 1852 FlyVideo'98 (with FM Tuner) + 0878 Bt878 Audio Capture + 0070 13eb WinTV Series + 0070 ff01 Viewcast Osprey 200 + 0071 0101 DigiTV PCI + 1002 0001 TV-Wonder + 1002 0003 TV-Wonder/VE + 11bd 0012 PCTV pro (TV + FM stereo receiver, audio section) + 11bd 001c PCTV Sat (DBC receiver) + 127a 0001 Bt878 Video Capture (Audio Section) + 127a 0002 Bt878 Video Capture (Audio Section) + 127a 0003 Bt878 Video Capture (Audio Section) + 127a 0048 Bt878 Video Capture (Audio Section) + 13e9 0070 Win/TV (Audio Section) + 144f 3000 MagicTView CPH060 - Audio + 1461 0002 Avermedia PCTV98 Audio Capture + 1461 0004 AVerTV WDM Audio Capture + 1461 0761 AVerTV DVB-T + 1461 0771 AverMedia AVerTV DVB-T 771 + 14f1 0001 Bt878 Video Capture (Audio Section) + 14f1 0002 Bt878 Video Capture (Audio Section) + 14f1 0003 Bt878 Video Capture (Audio Section) + 14f1 0048 Bt878 Video Capture (Audio Section) + 1822 0001 VisionPlus DVB Card + 18ac d500 DViCO FusionHDTV5 Lite + 270f fc00 Digitop DTT-1000 + bd11 1200 PCTV pro (TV + FM stereo receiver, audio section) + 0879 Bt879 Audio Capture + 127a 0044 Bt879 Video Capture (Audio Section) + 127a 0122 Bt879 Video Capture (Audio Section) + 127a 0144 Bt879 Video Capture (Audio Section) + 127a 0222 Bt879 Video Capture (Audio Section) + 127a 0244 Bt879 Video Capture (Audio Section) + 127a 0322 Bt879 Video Capture (Audio Section) + 127a 0422 Bt879 Video Capture (Audio Section) + 127a 1122 Bt879 Video Capture (Audio Section) + 127a 1222 Bt879 Video Capture (Audio Section) + 127a 1322 Bt879 Video Capture (Audio Section) + 127a 1522 Bt879 Video Capture (Audio Section) + 127a 1622 Bt879 Video Capture (Audio Section) + 127a 1722 Bt879 Video Capture (Audio Section) + 14f1 0044 Bt879 Video Capture (Audio Section) + 14f1 0122 Bt879 Video Capture (Audio Section) + 14f1 0144 Bt879 Video Capture (Audio Section) + 14f1 0222 Bt879 Video Capture (Audio Section) + 14f1 0244 Bt879 Video Capture (Audio Section) + 14f1 0322 Bt879 Video Capture (Audio Section) + 14f1 0422 Bt879 Video Capture (Audio Section) + 14f1 1122 Bt879 Video Capture (Audio Section) + 14f1 1222 Bt879 Video Capture (Audio Section) + 14f1 1322 Bt879 Video Capture (Audio Section) + 14f1 1522 Bt879 Video Capture (Audio Section) + 14f1 1622 Bt879 Video Capture (Audio Section) + 14f1 1722 Bt879 Video Capture (Audio Section) + 0880 Bt880 Audio Capture + 2115 BtV 2115 Mediastream controller + 2125 BtV 2125 Mediastream controller + 2164 BtV 2164 + 2165 BtV 2165 + 8230 Bt8230 ATM Segment/Reassembly Ctrlr (SRC) + 8472 Bt8472 + 8474 Bt8474 +109f Trigem Computer Inc. +10a0 Meidensha Corporation +10a1 Juko Electronics Ind. Co. Ltd +10a2 Quantum Corporation +10a3 Everex Systems Inc +10a4 Globe Manufacturing Sales +10a5 Smart Link Ltd. + 3052 SmartPCI562 56K Modem + 5449 SmartPCI561 modem +10a6 Informtech Industrial Ltd. +10a7 Benchmarq Microelectronics +10a8 Sierra Semiconductor + 0000 STB Horizon 64 +10a9 Silicon Graphics, Inc. + 0001 Crosstalk to PCI Bridge + 0002 Linc I/O controller + 0003 IOC3 I/O controller + 0004 O2 MACE + 0005 RAD Audio + 0006 HPCEX + 0007 RPCEX + 0008 DiVO VIP + 0009 AceNIC Gigabit Ethernet + 10a9 8002 AceNIC Gigabit Ethernet + 0010 AMP Video I/O + 0011 GRIP + 0012 SGH PSHAC GSN + 1001 Magic Carpet + 1002 Lithium + 1003 Dual JPEG 1 + 1004 Dual JPEG 2 + 1005 Dual JPEG 3 + 1006 Dual JPEG 4 + 1007 Dual JPEG 5 + 1008 Cesium + 100a IOC4 I/O controller + 2001 Fibre Channel + 2002 ASDE + 4001 TIO-CE PCI Express Bridge + 4002 TIO-CE PCI Express Port + 8001 O2 1394 + 8002 G-net NT +10aa ACC Microelectronics + 0000 ACCM 2188 +10ab Digicom +10ac Honeywell IAC +10ad Symphony Labs + 0001 W83769F + 0003 SL82C103 + 0005 SL82C105 + 0103 SL82c103 + 0105 SL82c105 + 0565 W83C553 +10ae Cornerstone Technology +10af Micro Computer Systems Inc +10b0 CardExpert Technology +10b1 Cabletron Systems Inc +10b2 Raytheon Company +10b3 Databook Inc + 3106 DB87144 + b106 DB87144 +10b4 STB Systems Inc + 1b1d Velocity 128 3D + 10b4 237e Velocity 4400 +10b5 PLX Technology, Inc. + 0001 i960 PCI bus interface + 1042 Brandywine / jxi2, Inc. - PMC-SyncClock32, IRIG A & B, Nasa 36 + 1076 VScom 800 8 port serial adaptor + 1077 VScom 400 4 port serial adaptor + 1078 VScom 210 2 port serial and 1 port parallel adaptor + 1103 VScom 200 2 port serial adaptor + 1146 VScom 010 1 port parallel adaptor + 1147 VScom 020 2 port parallel adaptor + 2540 IXXAT CAN-Interface PC-I 04/PCI + 2724 Thales PCSM Security Card + 6540 PCI6540/6466 PCI-PCI bridge (transparent mode) + 4c53 10e0 PSL09 PrPMC + 6541 PCI6540/6466 PCI-PCI bridge (non-transparent mode, primary side) + 4c53 10e0 PSL09 PrPMC + 6542 PCI6540/6466 PCI-PCI bridge (non-transparent mode, secondary side) + 4c53 10e0 PSL09 PrPMC + 8111 PEX 8111 PCI Express-to-PCI Bridge + 8114 PEX 8114 PCI Express-to-PCI/PCI-X Bridge + 8516 PEX 8516 Versatile PCI Express Switch + 8532 PEX 8532 Versatile PCI Express Switch + 9030 PCI <-> IOBus Bridge Hot Swap + 10b5 2862 Alpermann+Velte PCL PCI LV (3V/5V): Timecode Reader Board + 10b5 2906 Alpermann+Velte PCI TS (3V/5V): Time Synchronisation Board + 10b5 2940 Alpermann+Velte PCL PCI D (3V/5V): Timecode Reader Board + 10b5 2977 IXXAT iPC-I XC16/PCI CAN Board + 10b5 2978 SH ARC-PCIu SOHARD ARCNET card + 10b5 3025 Alpermann+Velte PCL PCI L (3V/5V): Timecode Reader Board + 10b5 3068 Alpermann+Velte PCL PCI HD (3V/5V): Timecode Reader Board + 1397 3136 4xS0-ISDN PCI Adapter + 1397 3137 S2M-E1-ISDN PCI Adapter + 1518 0200 Kontron ThinkIO-C + 15ed 1002 MCCS 8-port Serial Hot Swap + 15ed 1003 MCCS 16-port Serial Hot Swap + 9036 9036 + 9050 PCI <-> IOBus Bridge + 10b5 1067 IXXAT CAN i165 + 10b5 1172 IK220 (Heidenhain) + 10b5 2036 SatPak GPS + 10b5 2221 Alpermann+Velte PCL PCI LV: Timecode Reader Board + 10b5 2273 SH ARC-PCI SOHARD ARCNET card + 10b5 2431 Alpermann+Velte PCL PCI D: Timecode Reader Board + 10b5 2905 Alpermann+Velte PCI TS: Time Synchronisation Board + 10b5 9050 PCI-I04 PCI Passive PC/CAN Interface + 1498 0362 TPMC866 8 Channel Serial Card + 1522 0001 RockForce 4 Port V.90 Data/Fax/Voice Modem + 1522 0002 RockForce 2 Port V.90 Data/Fax/Voice Modem + 1522 0003 RockForce 6 Port V.90 Data/Fax/Voice Modem + 1522 0004 RockForce 8 Port V.90 Data/Fax/Voice Modem + 1522 0010 RockForce2000 4 Port V.90 Data/Fax/Voice Modem + 1522 0020 RockForce2000 2 Port V.90 Data/Fax/Voice Modem + 15ed 1000 Macrolink MCCS 8-port Serial + 15ed 1001 Macrolink MCCS 16-port Serial + 15ed 1002 Macrolink MCCS 8-port Serial Hot Swap + 15ed 1003 Macrolink MCCS 16-port Serial Hot Swap + 5654 2036 OpenSwitch 6 Telephony card + 5654 3132 OpenSwitch 12 Telephony card + 5654 5634 OpenLine4 Telephony Card + d531 c002 PCIntelliCAN 2xSJA1000 CAN bus + d84d 4006 EX-4006 1P + d84d 4008 EX-4008 1P EPP/ECP + d84d 4014 EX-4014 2P + d84d 4018 EX-4018 3P EPP/ECP + d84d 4025 EX-4025 1S(16C550) RS-232 + d84d 4027 EX-4027 1S(16C650) RS-232 + d84d 4028 EX-4028 1S(16C850) RS-232 + d84d 4036 EX-4036 2S(16C650) RS-232 + d84d 4037 EX-4037 2S(16C650) RS-232 + d84d 4038 EX-4038 2S(16C850) RS-232 + d84d 4052 EX-4052 1S(16C550) RS-422/485 + d84d 4053 EX-4053 2S(16C550) RS-422/485 + d84d 4055 EX-4055 4S(16C550) RS-232 + d84d 4058 EX-4055 4S(16C650) RS-232 + d84d 4065 EX-4065 8S(16C550) RS-232 + d84d 4068 EX-4068 8S(16C650) RS-232 + d84d 4078 EX-4078 2S(16C552) RS-232+1P + 9054 PCI <-> IOBus Bridge + 10b5 2455 Wessex Techology PHIL-PCI + 10b5 2696 Innes Corp AM Radcap card + 10b5 2717 Innes Corp Auricon card + 10b5 2844 Innes Corp TVS Encoder card + 12c7 4001 Intel Dialogic DM/V960-4T1 PCI + 12d9 0002 PCI Prosody Card rev 1.5 + 16df 0011 PIKA PrimeNet MM PCI + 16df 0012 PIKA PrimeNet MM cPCI 8 + 16df 0013 PIKA PrimeNet MM cPCI 8 (without CAS Signaling) + 16df 0014 PIKA PrimeNet MM cPCI 4 + 16df 0015 PIKA Daytona MM + 16df 0016 PIKA InLine MM + 9056 Francois + 10b5 2979 CellinkBlade 11 - CPCI board VoATM AAL1 + 9060 9060 + 906d 9060SD + 125c 0640 Aries 16000P + 906e 9060ES + 9080 9080 + 103c 10eb (Agilent) E2777B 83K Series Optical Communication Interface + 103c 10ec (Agilent) E6978-66442 PCI CIC + 10b5 1123 Sectra KK631 encryption board + 10b5 9080 9080 [real subsystem ID not set] + 129d 0002 Aculab PCI Prosidy card + 12d9 0002 PCI Prosody Card + 12df 4422 4422PCI ["Do-All" Telemetry Data Aquisition System] + 1517 000b ECSG-1R3ADC-PMC Clock synthesizer + 9656 PCI <-> IOBus Bridge + 1517 000f ECDR-GC314-PMC Receiver + 1885 0700 Tsunami FPGA PMC with Altera Stratix S40 + 1885 0701 Tsunami FPGA PMC with Altera Stratix S30 + bb04 B&B 3PCIOSD1A Isolated PCI Serial + c001 CronyxOmega-PCI (8-port RS232) +10b6 Madge Networks + 0001 Smart 16/4 PCI Ringnode + 0002 Smart 16/4 PCI Ringnode Mk2 + 10b6 0002 Smart 16/4 PCI Ringnode Mk2 + 10b6 0006 16/4 CardBus Adapter + 0003 Smart 16/4 PCI Ringnode Mk3 + 0e11 b0fd Compaq NC4621 PCI, 4/16, WOL + 10b6 0003 Smart 16/4 PCI Ringnode Mk3 + 10b6 0007 Presto PCI Plus Adapter + 0004 Smart 16/4 PCI Ringnode Mk1 + 0006 16/4 Cardbus Adapter + 10b6 0006 16/4 CardBus Adapter + 0007 Presto PCI Adapter + 10b6 0007 Presto PCI + 0009 Smart 100/16/4 PCI-HS Ringnode + 10b6 0009 Smart 100/16/4 PCI-HS Ringnode + 000a Smart 100/16/4 PCI Ringnode + 10b6 000a Smart 100/16/4 PCI Ringnode + 000b 16/4 CardBus Adapter Mk2 + 10b6 0008 16/4 CardBus Adapter Mk2 + 10b6 000b 16/4 Cardbus Adapter Mk2 + 000c RapidFire 3140V2 16/4 TR Adapter + 10b6 000c RapidFire 3140V2 16/4 TR Adapter + 1000 Collage 25/155 ATM Client Adapter + 1001 Collage 155 ATM Server Adapter +10b7 3Com Corporation + 0001 3c985 1000BaseSX (SX/TX) + 0013 AR5212 802.11abg NIC (3CRDAG675) + 10b7 2031 3CRDAG675 11a/b/g Wireless PCI Adapter + 0910 3C910-A01 + 1006 MINI PCI type 3B Data Fax Modem + 1007 Mini PCI 56k Winmodem + 10b7 615c Mini PCI 56K Modem + 1201 3c982-TXM 10/100baseTX Dual Port A [Hydra] + 1202 3c982-TXM 10/100baseTX Dual Port B [Hydra] + 1700 3c940 10/100/1000Base-T [Marvell] + 1043 80eb A7V600/P4P800/K8V motherboard + 10b7 0010 3C940 Gigabit LOM Ethernet Adapter + 10b7 0020 3C941 Gigabit LOM Ethernet Adapter + 147b 1407 KV8-MAX3 motherboard + 3390 3c339 TokenLink Velocity + 3590 3c359 TokenLink Velocity XL + 10b7 3590 TokenLink Velocity XL Adapter (3C359/359B) + 4500 3c450 HomePNA [Tornado] + 5055 3c555 Laptop Hurricane + 5057 3c575 Megahertz 10/100 LAN CardBus [Boomerang] + 10b7 5a57 3C575 Megahertz 10/100 LAN Cardbus PC Card + 5157 3cCFE575BT Megahertz 10/100 LAN CardBus [Cyclone] + 10b7 5b57 3C575 Megahertz 10/100 LAN Cardbus PC Card + 5257 3cCFE575CT CardBus [Cyclone] + 10b7 5c57 FE575C-3Com 10/100 LAN CardBus-Fast Ethernet + 5900 3c590 10BaseT [Vortex] + 5920 3c592 EISA 10mbps Demon/Vortex + 5950 3c595 100BaseTX [Vortex] + 5951 3c595 100BaseT4 [Vortex] + 5952 3c595 100Base-MII [Vortex] + 5970 3c597 EISA Fast Demon/Vortex + 5b57 3c595 Megahertz 10/100 LAN CardBus [Boomerang] + 10b7 5b57 3C575 Megahertz 10/100 LAN Cardbus PC Card + 6000 3CRSHPW796 [OfficeConnect Wireless CardBus] + 6001 3com 3CRWE154G72 [Office Connect Wireless LAN Adapter] + 6055 3c556 Hurricane CardBus [Cyclone] + 6056 3c556B CardBus [Tornado] + 10b7 6556 10/100 Mini PCI Ethernet Adapter + 6560 3cCFE656 CardBus [Cyclone] + 10b7 656a 3CCFEM656 10/100 LAN+56K Modem CardBus + 6561 3cCFEM656 10/100 LAN+56K Modem CardBus + 10b7 656b 3CCFEM656 10/100 LAN+56K Modem CardBus + 6562 3cCFEM656B 10/100 LAN+Winmodem CardBus [Cyclone] + 10b7 656b 3CCFEM656B 10/100 LAN+56K Modem CardBus + 6563 3cCFEM656B 10/100 LAN+56K Modem CardBus + 10b7 656b 3CCFEM656 10/100 LAN+56K Modem CardBus + 6564 3cXFEM656C 10/100 LAN+Winmodem CardBus [Tornado] + 7646 3cSOHO100-TX Hurricane + 7770 3CRWE777 PCI(PLX) Wireless Adaptor [Airconnect] + 7940 3c803 FDDILink UTP Controller + 7980 3c804 FDDILink SAS Controller + 7990 3c805 FDDILink DAS Controller + 80eb 3c940B 10/100/1000Base-T + 8811 Token ring + 9000 3c900 10BaseT [Boomerang] + 9001 3c900 10Mbps Combo [Boomerang] + 9004 3c900B-TPO Etherlink XL [Cyclone] + 10b7 9004 3C900B-TPO Etherlink XL TPO 10Mb + 9005 3c900B-Combo Etherlink XL [Cyclone] + 10b7 9005 3C900B-Combo Etherlink XL Combo + 9006 3c900B-TPC Etherlink XL [Cyclone] + 900a 3c900B-FL 10base-FL [Cyclone] + 9050 3c905 100BaseTX [Boomerang] + 9051 3c905 100BaseT4 [Boomerang] + 9054 3C905B-TX Fast Etherlink XL PCI + 10b7 9054 3C905B-TX Fast Etherlink XL PCI + 9055 3c905B 100BaseTX [Cyclone] + 1028 0080 3C905B Fast Etherlink XL 10/100 + 1028 0081 3C905B Fast Etherlink XL 10/100 + 1028 0082 3C905B Fast Etherlink XL 10/100 + 1028 0083 3C905B Fast Etherlink XL 10/100 + 1028 0084 3C905B Fast Etherlink XL 10/100 + 1028 0085 3C905B Fast Etherlink XL 10/100 + 1028 0086 3C905B Fast Etherlink XL 10/100 + 1028 0087 3C905B Fast Etherlink XL 10/100 + 1028 0088 3C905B Fast Etherlink XL 10/100 + 1028 0089 3C905B Fast Etherlink XL 10/100 + 1028 0090 3C905B Fast Etherlink XL 10/100 + 1028 0091 3C905B Fast Etherlink XL 10/100 + 1028 0092 3C905B Fast Etherlink XL 10/100 + 1028 0093 3C905B Fast Etherlink XL 10/100 + 1028 0094 3C905B Fast Etherlink XL 10/100 + 1028 0095 3C905B Fast Etherlink XL 10/100 + 1028 0096 3C905B Fast Etherlink XL 10/100 + 1028 0097 3C905B Fast Etherlink XL 10/100 + 1028 0098 3C905B Fast Etherlink XL 10/100 + 1028 0099 3C905B Fast Etherlink XL 10/100 + 10b7 9055 3C905B Fast Etherlink XL 10/100 + 9056 3c905B-T4 Fast EtherLink XL [Cyclone] + 9058 3c905B Deluxe Etherlink 10/100/BNC [Cyclone] + 905a 3c905B-FX Fast Etherlink XL FX 100baseFx [Cyclone] + 9200 3c905C-TX/TX-M [Tornado] + 1028 0095 3C920 Integrated Fast Ethernet Controller + 1028 0097 3C920 Integrated Fast Ethernet Controller + 1028 00fe Optiplex GX240 + 1028 012a 3C920 Integrated Fast Ethernet Controller [Latitude C640] + 10b7 1000 3C905C-TX Fast Etherlink for PC Management NIC + 10b7 7000 10/100 Mini PCI Ethernet Adapter + 10f1 2466 Tiger MPX S2466 (3C920 Integrated Fast Ethernet Controller) + 9201 3C920B-EMB Integrated Fast Ethernet Controller [Tornado] + 1043 80ab A7N8X Deluxe onboard 3C920B-EMB Integrated Fast Ethernet Controller + 9202 3Com 3C920B-EMB-WNM Integrated Fast Ethernet Controller + 9210 3C920B-EMB-WNM Integrated Fast Ethernet Controller + 9300 3CSOHO100B-TX 910-A01 [tulip] + 9800 3c980-TX Fast Etherlink XL Server Adapter [Cyclone] + 10b7 9800 3c980-TX Fast Etherlink XL Server Adapter + 9805 3c980-C 10/100baseTX NIC [Python-T] + 10b7 1201 EtherLink Server 10/100 Dual Port A + 10b7 1202 EtherLink Server 10/100 Dual Port B + 10b7 9805 3c980 10/100baseTX NIC [Python-T] + 10f1 2462 Thunder K7 S2462 + 9900 3C990-TX [Typhoon] + 9902 3CR990-TX-95 [Typhoon 56-bit] + 9903 3CR990-TX-97 [Typhoon 168-bit] + 9904 3C990B-TX-M/3C990BSVR [Typhoon2] + 10b7 1000 3CR990B-TX-M [Typhoon2] + 10b7 2000 3CR990BSVR [Typhoon2 Server] + 9905 3CR990-FX-95/97/95 [Typhon Fiber] + 10b7 1101 3CR990-FX-95 [Typhoon Fiber 56-bit] + 10b7 1102 3CR990-FX-97 [Typhoon Fiber 168-bit] + 10b7 2101 3CR990-FX-95 Server [Typhoon Fiber 56-bit] + 10b7 2102 3CR990-FX-97 Server [Typhoon Fiber 168-bit] + 9908 3CR990SVR95 [Typhoon Server 56-bit] + 9909 3CR990SVR97 [Typhoon Server 168-bit] + 990a 3C990SVR [Typhoon Server] + 990b 3C990SVR [Typhoon Server] +10b8 Standard Microsystems Corp [SMC] + 0005 83c170 EPIC/100 Fast Ethernet Adapter + 1055 e000 LANEPIC 10/100 [EVB171Q-PCI] + 1055 e002 LANEPIC 10/100 [EVB171G-PCI] + 10b8 a011 EtherPower II 10/100 + 10b8 a014 EtherPower II 10/100 + 10b8 a015 EtherPower II 10/100 + 10b8 a016 EtherPower II 10/100 + 10b8 a017 EtherPower II 10/100 + 0006 83c175 EPIC/100 Fast Ethernet Adapter + 1055 e100 LANEPIC Cardbus Fast Ethernet Adapter + 1055 e102 LANEPIC Cardbus Fast Ethernet Adapter + 1055 e300 LANEPIC Cardbus Fast Ethernet Adapter + 1055 e302 LANEPIC Cardbus Fast Ethernet Adapter + 10b8 a012 LANEPIC Cardbus Fast Ethernet Adapter + 13a2 8002 LANEPIC Cardbus Fast Ethernet Adapter + 13a2 8006 LANEPIC Cardbus Fast Ethernet Adapter + 1000 FDC 37c665 + 1001 FDC 37C922 + 2802 SMC2802W [EZ Connect g] + a011 83C170QF + b106 SMC34C90 +10b9 ALi Corporation + 0101 CMI8338/C3DX PCI Audio Device + 0111 C-Media CMI8738/C3DX Audio Device (OEM) + 10b9 0111 C-Media CMI8738/C3DX Audio Device (OEM) + 0780 Multi-IO Card + 0782 Multi-IO Card + 1435 M1435 + 1445 M1445 + 1449 M1449 + 1451 M1451 + 1461 M1461 + 1489 M1489 + 1511 M1511 [Aladdin] + 1512 M1512 [Aladdin] + 1513 M1513 [Aladdin] + 1521 M1521 [Aladdin III] + 10b9 1521 ALI M1521 Aladdin III CPU Bridge + 1523 M1523 + 10b9 1523 ALI M1523 ISA Bridge + 1531 M1531 [Aladdin IV] + 1533 M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+] + 1014 053b ThinkPad R40e (2684-HVG) PCI to ISA Bridge + 10b9 1533 ALi M1533 Aladdin IV/V ISA Bridge + 1541 M1541 + 10b9 1541 ALI M1541 Aladdin V/V+ AGP System Controller + 1543 M1543 + 1563 M1563 HyperTransport South Bridge + 1573 PCI to LPC Controller + 1621 M1621 + 1631 ALI M1631 PCI North Bridge Aladdin Pro III + 1632 M1632M Northbridge+Trident + 1641 ALI M1641 PCI North Bridge Aladdin Pro IV + 1644 M1644/M1644T Northbridge+Trident + 1646 M1646 Northbridge+Trident + 1647 M1647 Northbridge [MAGiK 1 / MobileMAGiK 1] + 1651 M1651/M1651T Northbridge [Aladdin-Pro 5/5M,Aladdin-Pro 5T/5TM] + 1671 M1671 Super P4 Northbridge [AGP4X,PCI and SDR/DDR] + 1672 M1672 Northbridge [CyberALADDiN-P4] + 1681 M1681 P4 Northbridge [AGP8X,HyperTransport and SDR/DDR] + 1687 M1687 K8 Northbridge [AGP8X and HyperTransport] + 1689 M1689 K8 Northbridge [Super K8 Single Chip] + 1695 M1695 K8 Northbridge [PCI Express and HyperTransport] + 1697 M1697 HTT Host Bridge + 3141 M3141 + 3143 M3143 + 3145 M3145 + 3147 M3147 + 3149 M3149 + 3151 M3151 + 3307 M3307 + 3309 M3309 + 3323 M3325 Video/Audio Decoder + 5212 M4803 + 5215 MS4803 + 5217 M5217H + 5219 M5219 + 5225 M5225 + 5228 M5228 ALi ATA/RAID Controller + 5229 M5229 IDE + 1014 050f ThinkPad R30 + 1014 053d ThinkPad R40e (2684-HVG) builtin IDE + 103c 0024 Pavilion ze4400 builtin IDE + 1043 8053 A7A266 Motherboard IDE + 1849 5229 ASRock 939Dual-SATA2 Motherboard IDE (PATA) + 5235 M5225 + 5237 USB 1.1 Controller + 1014 0540 ThinkPad R40e (2684-HVG) builtin USB + 103c 0024 Pavilion ze4400 builtin USB + 104d 810f VAIO PCG-U1 USB/OHCI Revision 1.0 + 5239 USB 2.0 Controller + 5243 M1541 PCI to AGP Controller + 5246 AGP8X Controller + 5247 PCI to AGP Controller + 5249 M5249 HTT to PCI Bridge + 524b PCI Express Root Port + 524c PCI Express Root Port + 524d PCI Express Root Port + 524e PCI Express Root Port + 5251 M5251 P1394 OHCI 1.0 Controller + 5253 M5253 P1394 OHCI 1.1 Controller + 5261 M5261 Ethernet Controller + 5263 ULi 1689,1573 integrated ethernet. + 5281 ALi M5281 Serial ATA / RAID Host Controller + 5287 ULi 5287 SATA + 5288 ULi M5288 SATA + 5289 ULi 5289 SATA + 5450 Lucent Technologies Soft Modem AMR + 5451 M5451 PCI AC-Link Controller Audio Device + 1014 0506 ThinkPad R30 + 1014 053e ThinkPad R40e (2684-HVG) builtin Audio + 103c 0024 Pavilion ze4400 builtin Audio + 10b9 5451 HP Compaq nc4010 (DY885AA#ABN) + 5453 M5453 PCI AC-Link Controller Modem Device + 5455 M5455 PCI AC-Link Controller Audio Device + 5457 M5457 AC'97 Modem Controller + 1014 0535 ThinkPad R40e (2684-HVG) builtin modem + 103c 0024 Pavilion ze4400 builtin Modem Device + 5459 SmartLink SmartPCI561 56K Modem + 545a SmartLink SmartPCI563 56K Modem + 5461 High Definition Audio/AC'97 Host Controller + 5471 M5471 Memory Stick Controller + 5473 M5473 SD-MMC Controller + 7101 M7101 Power Management Controller [PMU] + 1014 0510 ThinkPad R30 + 1014 053c ThinkPad R40e (2684-HVG) Power Management Controller + 103c 0024 Pavilion ze4400 +10ba Mitsubishi Electric Corp. + 0301 AccelGraphics AccelECLIPSE + 0304 AccelGALAXY A2100 [OEM Evans & Sutherland] + 0308 Tornado 3000 [OEM Evans & Sutherland] + 1002 VG500 [VolumePro Volume Rendering Accelerator] +10bb Dapha Electronics Corporation +10bc Advanced Logic Research +10bd Surecom Technology + 0e34 NE-34 +10be Tseng Labs International Co. +10bf Most Inc +10c0 Boca Research Inc. +10c1 ICM Co., Ltd. +10c2 Auspex Systems Inc. +10c3 Samsung Semiconductors, Inc. + 1100 Smartether100 SC1100 LAN Adapter (i82557B) +10c4 Award Software International Inc. +10c5 Xerox Corporation +10c6 Rambus Inc. +10c7 Media Vision +10c8 Neomagic Corporation + 0001 NM2070 [MagicGraph 128] + 0002 NM2090 [MagicGraph 128V] + 0003 NM2093 [MagicGraph 128ZV] + 0004 NM2160 [MagicGraph 128XD] + 1014 00ba MagicGraph 128XD + 1025 1007 MagicGraph 128XD + 1028 0074 MagicGraph 128XD + 1028 0075 MagicGraph 128XD + 1028 007d MagicGraph 128XD + 1028 007e MagicGraph 128XD + 1033 802f MagicGraph 128XD + 104d 801b MagicGraph 128XD + 104d 802f MagicGraph 128XD + 104d 830b MagicGraph 128XD + 10ba 0e00 MagicGraph 128XD + 10c8 0004 MagicGraph 128XD + 10cf 1029 MagicGraph 128XD + 10f7 8308 MagicGraph 128XD + 10f7 8309 MagicGraph 128XD + 10f7 830b MagicGraph 128XD + 10f7 830d MagicGraph 128XD + 10f7 8312 MagicGraph 128XD + 0005 NM2200 [MagicGraph 256AV] + 1014 00dd ThinkPad 570 + 1028 0088 Latitude CPi A + 0006 NM2360 [MagicMedia 256ZX] + 0016 NM2380 [MagicMedia 256XL+] + 10c8 0016 MagicMedia 256XL+ + 0025 NM2230 [MagicGraph 256AV+] + 0083 NM2093 [MagicGraph 128ZV+] + 8005 NM2200 [MagicMedia 256AV Audio] + 0e11 b0d1 MagicMedia 256AV Audio Device on Discovery + 0e11 b126 MagicMedia 256AV Audio Device on Durango + 1014 00dd MagicMedia 256AV Audio Device on BlackTip Thinkpad + 1025 1003 MagicMedia 256AV Audio Device on TravelMate 720 + 1028 0088 Latitude CPi A + 1028 008f MagicMedia 256AV Audio Device on Colorado Inspiron + 103c 0007 MagicMedia 256AV Audio Device on Voyager II + 103c 0008 MagicMedia 256AV Audio Device on Voyager III + 103c 000d MagicMedia 256AV Audio Device on Omnibook 900 + 10c8 8005 MagicMedia 256AV Audio Device on FireAnt + 110a 8005 MagicMedia 256AV Audio Device + 14c0 0004 MagicMedia 256AV Audio Device + 8006 NM2360 [MagicMedia 256ZX Audio] + 8016 NM2380 [MagicMedia 256XL+ Audio] +10c9 Dataexpert Corporation +10ca Fujitsu Microelectr., Inc. +10cb Omron Corporation +# nee Mentor ARC Inc +10cc Mai Logic Incorporated + 0660 Articia S Host Bridge + 0661 Articia S PCI Bridge +10cd Advanced System Products, Inc + 1100 ASC1100 + 1200 ASC1200 [(abp940) Fast SCSI-II] + 1300 ABP940-U / ABP960-U + 10cd 1310 ASC1300 SCSI Adapter + 1195 1320 Ultra-SCSI CardBus PC Card REX CB31 + 2300 ABP940-UW + 2500 ABP940-U2W +10ce Radius +# nee Citicorp TTI +10cf Fujitsu Limited. + 2001 mb86605 +10d1 FuturePlus Systems Corp. +10d2 Molex Incorporated +10d3 Jabil Circuit Inc +10d4 Hualon Microelectronics +10d5 Autologic Inc. +10d6 Cetia +10d7 BCM Advanced Research +10d8 Advanced Peripherals Labs +10d9 Macronix, Inc. [MXIC] + 0431 MX98715 + 0512 MX98713 + 0531 MX987x5 + 1186 1200 DFE-540TX ProFAST 10/100 Adapter + 8625 MX86250 + 8626 Macronix MX86251 + 3Dfx Voodoo Rush + 8888 MX86200 +10da Compaq IPG-Austin + 0508 TC4048 Token Ring 4/16 + 3390 Tl3c3x9 +10db Rohm LSI Systems, Inc. +10dc CERN/ECP/EDU + 0001 STAR/RD24 SCI-PCI (PMC) + 0002 TAR/RD24 SCI-PCI (PMC) + 0021 HIPPI destination + 0022 HIPPI source + 10dc ATT2C15-3 FPGA +10dd Evans & Sutherland + 0100 Lightning 1200 +10de nVidia Corporation + 0008 NV1 [EDGE 3D] + 0009 NV1 [EDGE 3D] + 0010 NV2 [Mutara V08] + 0020 NV4 [RIVA TNT] + 1043 0200 V3400 TNT + 1048 0c18 Erazor II SGRAM + 1048 0c19 Erazor II + 1048 0c1b Erazor II + 1048 0c1c Erazor II + 1092 0550 Viper V550 + 1092 0552 Viper V550 + 1092 4804 Viper V550 + 1092 4808 Viper V550 + 1092 4810 Viper V550 + 1092 4812 Viper V550 + 1092 4815 Viper V550 + 1092 4820 Viper V550 with TV out + 1092 4822 Viper V550 + 1092 4904 Viper V550 + 1092 4914 Viper V550 + 1092 8225 Viper V550 + 10b4 273d Velocity 4400 + 10b4 273e Velocity 4400 + 10b4 2740 Velocity 4400 + 10de 0020 Riva TNT + 1102 1015 Graphics Blaster CT6710 + 1102 1016 Graphics Blaster RIVA TNT + 0028 NV5 [RIVA TNT2/TNT2 Pro] + 1043 0200 AGP-V3800 SGRAM + 1043 0201 AGP-V3800 SDRAM + 1043 0205 PCI-V3800 + 1043 4000 AGP-V3800PRO + 1048 0c21 Synergy II + 1048 0c28 Erazor III + 1048 0c29 Erazor III + 1048 0c2a Erazor III + 1048 0c2b Erazor III + 1048 0c31 Erazor III Pro + 1048 0c32 Erazor III Pro + 1048 0c33 Erazor III Pro + 1048 0c34 Erazor III Pro + 107d 2134 WinFast 3D S320 II + TV-Out + 1092 4804 Viper V770 + 1092 4a00 Viper V770 + 1092 4a02 Viper V770 Ultra + 1092 5a00 RIVA TNT2/TNT2 Pro + 1092 6a02 Viper V770 Ultra + 1092 7a02 Viper V770 Ultra + 10de 0005 RIVA TNT2 Pro + 10de 000f Compaq NVIDIA TNT2 Pro + 1102 1020 3D Blaster RIVA TNT2 + 1102 1026 3D Blaster RIVA TNT2 Digital + 14af 5810 Maxi Gamer Xentor + 0029 NV5 [RIVA TNT2 Ultra] + 1043 0200 AGP-V3800 Deluxe + 1043 0201 AGP-V3800 Ultra SDRAM + 1043 0205 PCI-V3800 Ultra + 1048 0c2e Erazor III Ultra + 1048 0c2f Erazor III Ultra + 1048 0c30 Erazor III Ultra + 1102 1021 3D Blaster RIVA TNT2 Ultra + 1102 1029 3D Blaster RIVA TNT2 Ultra + 1102 102f 3D Blaster RIVA TNT2 Ultra + 14af 5820 Maxi Gamer Xentor 32 + 002a NV5 [Riva TnT2] + 002b NV5 [Riva TnT2] + 002c NV6 [Vanta/Vanta LT] + 1043 0200 AGP-V3800 Combat SDRAM + 1043 0201 AGP-V3800 Combat + 1048 0c20 TNT2 Vanta + 1048 0c21 TNT2 Vanta + 1092 6820 Viper V730 + 1102 1031 CT6938 VANTA 8MB + 1102 1034 CT6894 VANTA 16MB + 14af 5008 Maxi Gamer Phoenix 2 + 002d NV5M64 [RIVA TNT2 Model 64/Model 64 Pro] + 1043 0200 AGP-V3800M + 1043 0201 AGP-V3800M + 1048 0c3a Erazor III LT + 1048 0c3b Erazor III LT + 10de 001e M64 AGP4x + 1102 1023 CT6892 RIVA TNT2 Value + 1102 1024 CT6932 RIVA TNT2 Value 32Mb + 1102 102c CT6931 RIVA TNT2 Value [Jumper] + 1462 8808 MSI-8808 + 1554 1041 Pixelview RIVA TNT2 M64 + 1569 002d Palit Microsystems Daytona TNT2 M64 + 002e NV6 [Vanta] + 002f NV6 [Vanta] + 0034 MCP04 SMBus + 0035 MCP04 IDE + 0036 MCP04 Serial ATA Controller + 0037 MCP04 Ethernet Controller + 0038 MCP04 Ethernet Controller + 003a MCP04 AC'97 Audio Controller + 003b MCP04 USB Controller + 003c MCP04 USB Controller + 003d MCP04 PCI Bridge + 003e MCP04 Serial ATA Controller + 0040 NV40 [GeForce 6800 Ultra] + 0041 NV40 [GeForce 6800] + 1043 817b V9999 Gamer Edition + 0042 NV40.2 [GeForce 6800 LE] + 0043 NV40.3 + 0044 NV40 [GeForce 6800 XT] + 0045 NV40 [GeForce 6800 GT] + 0046 NV40 [GeForce 6800 GT] + 0047 NV40 [GeForce 6800 GS] + 1682 2109 GeForce 6800 GS + 0048 NV40 [GeForce 6800 XT] + 0049 NV40GL + 004d NV40GL [Quadro FX 4000] + 004e NV40GL [Quadro FX 4000] + 0050 CK804 ISA Bridge + 1043 815a K8N4-E Mainboard + 1458 0c11 GA-K8N Ultra-9 Mainboard + 1462 7100 MSI K8N Diamond + 147b 1c1a KN8-Ultra Mainboard + 0051 CK804 ISA Bridge + 0052 CK804 SMBus + 1043 815a K8N4-E Mainboard + 1458 0c11 GA-K8N Ultra-9 Mainboard + 1462 7100 MSI K8N Diamond + 147b 1c1a KN8-Ultra Mainboard + 0053 CK804 IDE + 1043 815a K8N4-E Mainboard + 1458 5002 GA-K8N Ultra-9 Mainboard + 1462 7100 MSI K8N Diamond + 147b 1c1a KN8-Ultra Mainboard + 0054 CK804 Serial ATA Controller + 1458 b003 GA-K8N Ultra-9 Mainboard + 1462 7100 MSI K8N Diamond + 147b 1c1a KN8-Ultra Mainboard + 0055 CK804 Serial ATA Controller + 1043 815a K8N4-E Mainboard + 1458 b003 GA-K8N Ultra-9 Mainboard + 147b 1c1a KN8-Ultra Mainboard + 0056 CK804 Ethernet Controller + 0057 CK804 Ethernet Controller + 1043 8141 K8N4-E Mainboard + 1458 e000 GA-K8N Ultra-9 Mainboard + 1462 7100 MSI K8N Diamond + 147b 1c1a KN8-Ultra Mainboard + 0058 CK804 AC'97 Modem + 0059 CK804 AC'97 Audio Controller + 1043 812a K8N4-E Mainboard + 147b 1c1a KN8-Ultra Mainboard + 005a CK804 USB Controller + 1043 815a K8N4-E Mainboard + 1458 5004 GA-K8N Ultra-9 Mainboard + 1462 7100 MSI K8N Diamond + 147b 1c1a KN8-Ultra Mainboard + 005b CK804 USB Controller + 1043 815a K8N4-E Mainboard + 1458 5004 GA-K8N Ultra-9 Mainboard + 1462 7100 MSI K8N Diamond + 147b 1c1a KN8-Ultra Mainboard + 005c CK804 PCI Bridge + 005d CK804 PCIE Bridge + 005e CK804 Memory Controller + 10f1 2891 Thunder K8SRE Mainboard + 1458 5000 GA-K8N Ultra-9 Mainboard + 1462 7100 MSI K8N Diamond + 147b 1c1a KN8-Ultra Mainboard + 005f CK804 Memory Controller + 0060 nForce2 ISA Bridge + 1043 80ad A7N8X Mainboard + a0a0 03ba UK79G-1394 motherboard + 0064 nForce2 SMBus (MCP) + a0a0 03bb UK79G-1394 motherboard + 0065 nForce2 IDE + a0a0 03b2 UK79G-1394 motherboard + 0066 nForce2 Ethernet Controller + 1043 80a7 A7N8X Mainboard onboard nForce2 Ethernet + 0067 nForce2 USB Controller + 1043 0c11 A7N8X Mainboard + 0068 nForce2 USB Controller + 1043 0c11 A7N8X Mainboard + a0a0 03b4 UK79G-1394 motherboard + 006a nForce2 AC97 Audio Controler (MCP) + 1043 8095 nForce2 AC97 Audio Controler (MCP) + a0a0 0304 UK79G-1394 motherboard + 006b nForce Audio Processing Unit + 10de 006b nForce2 MCP Audio Processing Unit + 006c nForce2 External PCI Bridge + 006d nForce2 PCI Bridge + 006e nForce2 FireWire (IEEE 1394) Controller + a0a0 0306 UK79G-1394 motherboard + 0080 MCP2A ISA bridge + 147b 1c09 NV7 Motherboard + 0084 MCP2A SMBus + 147b 1c09 NV7 Motherboard + 0085 MCP2A IDE + 147b 1c09 NV7 Motherboard + 0086 MCP2A Ethernet Controller + 0087 MCP2A USB Controller + 147b 1c09 NV7 Motherboard + 0088 MCP2A USB Controller + 147b 1c09 NV7 Motherboard + 008a MCP2S AC'97 Audio Controller + 147b 1c09 NV7 Motherboard + 008b MCP2A PCI Bridge + 008c MCP2A Ethernet Controller + 008e nForce2 Serial ATA Controller + 0090 G70 [GeForce 7800 GTX] + 0091 G70 [GeForce 7800 GTX] + 0092 G70 [GeForce 7800 GT] + 0093 G70 [GeForce 7800 GS] + 0098 GeForce Go 7800 + 0099 GE Force Go 7800 GTX + 009d G70GL [Quadro FX4500] + 00a0 NV5 [Aladdin TNT2] + 14af 5810 Maxi Gamer Xentor + 00c0 NV41 [GeForce 6800 GS] + 00c1 NV41.1 [GeForce 6800] + 00c2 NV41.2 [GeForce 6800 LE] + 00c3 NV42 [Geforce 6800 XT] + 00c8 NV41.8 [GeForce Go 6800] + 00c9 NV41.9 [GeForce Go 6800 Ultra] + 00cc NV41 [Quadro FX Go1400] + 00cd NV41 [Quadro FX 3450/4000 SDI] + 10de 029b wx4300 Workstation + 00ce NV41GL [Quadro FX 1400] + 00d0 nForce3 LPC Bridge + 00d1 nForce3 Host Bridge + 00d2 nForce3 AGP Bridge + 00d3 CK804 Memory Controller + 00d4 nForce3 SMBus + 00d5 nForce3 IDE + 00d6 nForce3 Ethernet + 00d7 nForce3 USB 1.1 + 00d8 nForce3 USB 2.0 + 00d9 nForce3 Audio + 00da nForce3 Audio + 00dd nForce3 PCI Bridge + 00df CK8S Ethernet Controller + 105b 0c43 Winfast NF3250K8AA + 147b 1c0b NF8 Mainboard + 00e0 nForce3 250Gb LPC Bridge + 10de 0c11 Winfast NF3250K8AA + 1462 7030 K8N Neo-FSR v2.0 + 147b 1c0b NF8 Mainboard + 00e1 nForce3 250Gb Host Bridge + 1462 7030 K8N Neo-FSR v2.0 + 147b 1c0b NF8 Mainboard + 00e2 nForce3 250Gb AGP Host to PCI Bridge + 00e3 CK8S Serial ATA Controller (v2.5) + 105b 0c43 Winfast NF3250K8AA + 147b 1c0b NF8 Mainboard + 00e4 nForce 250Gb PCI System Management + 105b 0c43 Winfast NF3250K8AA + 1462 7030 K8N Neo-FSR v2.0 + 147b 1c0b NF8 Mainboard + 00e5 CK8S Parallel ATA Controller (v2.5) + 105b 0c43 Winfast NF3250K8AA + 1462 7030 K8N Neo-FSR v2.0 + 147b 1c0b NF8 Mainboard + 00e6 CK8S Ethernet Controller + 00e7 CK8S USB Controller + 105b 0c43 Winfast NF3250K8AA + 1462 7030 K8N Neo-FSR v2.0 + 147b 1c0b NF8 Mainboard + 00e8 nForce3 EHCI USB 2.0 Controller + 105b 0c43 Winfast NF3250K8AA + 1462 7030 K8N Neo-FSR v2.0 + 147b 1c0b NF8 Mainboard + 00ea nForce3 250Gb AC'97 Audio Controller + 105b 0c43 Winfast NF3250K8AA + 147b 1c0b NF8 Mainboard + 00ed nForce3 250Gb PCI-to-PCI Bridge + 00ee CK8S Serial ATA Controller (v2.5) + 00f0 NV40 [GeForce 6800/GeForce 6800 Ultra] + 00f1 NV43 [GeForce 6600/GeForce 6600 GT] + 1043 81a6 N6600GT TD 128M AGP + 1682 2119 GeForce 6600 GT AGP 128MB DDR3 DUAL DVI TV + 00f2 NV43 [GeForce 6600/GeForce 6600 GT] + 1682 211c GeForce 6600 256MB DDR DUAL DVI TV + 00f3 NV43 [GeForce 6200] + 00f4 NV43 [GeForce 6600 LE] + 00f5 G70 [GeForce 7800 GS] + 00f6 NV43 [GeForce 6600 GS] + 1682 217e XFX GeForce 6800 XTreme 256MB DDR3 AGP + 00f8 NV45GL [Quadro FX 3400/4400] + 00f9 NV40 [GeForce 6800 Ultra/GeForce 6800 GT] + 1682 2120 GEFORCE 6800 GT PCI-E + 00fa NV36 [GeForce PCX 5750] + 00fb NV35 [GeForce PCX 5900] + 00fc NV37GL [Quadro FX 330/GeForce PCX 5300] + 00fd NV37GL [Quadro FX 330/Quadro NVS280] + 00fe NV38GL [Quadro FX 1300] + 00ff NV18 [GeForce PCX 4300] + 0100 NV10 [GeForce 256 SDR] + 1043 0200 AGP-V6600 SGRAM + 1043 0201 AGP-V6600 SDRAM + 1043 4008 AGP-V6600 SGRAM + 1043 4009 AGP-V6600 SDRAM + 1048 0c41 Erazor X + 1048 0c43 ERAZOR X PCI + 1048 0c48 Synergy Force + 1102 102d CT6941 GeForce 256 + 14af 5022 3D Prophet SE + 0101 NV10DDR [GeForce 256 DDR] + 1043 0202 AGP-V6800 DDR + 1043 400a AGP-V6800 DDR SGRAM + 1043 400b AGP-V6800 DDR SDRAM + 1048 0c42 Erazor X + 107d 2822 WinFast GeForce 256 + 1102 102e CT6971 GeForce 256 DDR + 14af 5021 3D Prophet DDR-DVI + 0103 NV10GL [Quadro] + 1048 0c40 GLoria II-64 + 1048 0c44 GLoria II + 1048 0c45 GLoria II + 1048 0c4a GLoria II-64 Pro + 1048 0c4b GLoria II-64 Pro DVII + 0110 NV11 [GeForce2 MX/MX 400] + 1043 4015 AGP-V7100 Pro + 1043 4031 V7100 Pro with TV output + 1048 0c60 Gladiac MX + 1048 0c61 Gladiac 511PCI + 1048 0c63 Gladiac 511TV-OUT 32MB + 1048 0c64 Gladiac 511TV-OUT 64MB + 1048 0c65 Gladiac 511TWIN + 1048 0c66 Gladiac 311 + 10de 0091 Dell OEM GeForce 2 MX 400 + 10de 00a1 Apple OEM GeForce2 MX + 1462 8817 MSI GeForce2 MX400 Pro32S [MS-8817] + 14af 7102 3D Prophet II MX + 14af 7103 3D Prophet II MX Dual-Display + 0111 NV11DDR [GeForce2 MX 100 DDR/200 DDR] + 0112 NV11 [GeForce2 Go] + 0113 NV11GL [Quadro2 MXR/EX/Go] + 0140 NV43 [GeForce 6600 GT] + 0141 NV43 [GeForce 6600] + 1458 3124 GV-NX66128DP Turbo Force Edition + 0142 NV43 [GeForce 6600 PCIe] + 0144 NV43 [GeForce Go 6600] + 0145 NV43 [GeForce 6610 XL] + 0146 NV43 [Geforce Go 6600TE/6200TE] + 0148 NV43 [GeForce Go 6600] + 0149 NV43 [GeForce Go 6600 GT] + 014a Quadro NVS 440 + 014c Quadro FX 550 + 014d NV18GL [Quadro FX 550] + 014e NV43GL [Quadro FX 540] + 014f NV43 [GeForce 6200] + 0150 NV15 [GeForce2 GTS/Pro] + 1043 4016 V7700 AGP Video Card + 1048 0c50 Gladiac + 1048 0c52 Gladiac-64 + 107d 2840 WinFast GeForce2 GTS with TV output + 107d 2842 WinFast GeForce 2 Pro + 10de 002e GeForce2 GTS + 1462 8831 Creative GeForce2 Pro + 0151 NV15DDR [GeForce2 Ti] + 1043 405f V7700Ti + 1462 5506 Creative 3D Blaster Geforce2 Titanium + 0152 NV15BR [GeForce2 Ultra, Bladerunner] + 1048 0c56 GLADIAC Ultra + 0153 NV15GL [Quadro2 Pro] + 0161 NV44 [GeForce 6200 TurboCache(TM)] + 0162 NV44 [GeForce 6200 SE TurboCache (TM)] + 0163 NV44 [GeForce 6200 LE] + 0164 NV44 [GeForce Go 6200] + 0165 NV44 [Quadro NVS 285] + 0166 NV43 [GeForce Go 6400] + 0167 GeForce Go 6200 TurboCache + 0168 NV43 [GeForce Go 6200 TurboCache] + 0170 NV17 [GeForce4 MX 460] + 0171 NV17 [GeForce4 MX 440] + 10b0 0002 Gainward Pro/600 TV + 10de 0008 Apple OEM GeForce4 MX 440 + 1462 8661 G4MX440-VTP + 1462 8730 MX440SES-T (MS-8873) + 1462 8852 GeForce4 MX440 PCI + 147b 8f00 Abit Siluro GeForce4MX440 + 0172 NV17 [GeForce4 MX 420] + 0173 NV17 [GeForce4 MX 440-SE] + 0174 NV17 [GeForce4 440 Go] + 0175 NV17 [GeForce4 420 Go] + 0176 NV17 [GeForce4 420 Go 32M] + 103c 08b0 tc1100 tablet + 4c53 1090 Cx9 / Vx9 mainboard + 0177 NV17 [GeForce4 460 Go] + 0178 NV17GL [Quadro4 550 XGL] + 0179 NV17 [GeForce4 420 Go 32M] + 10de 0179 GeForce4 MX (Mac) + 017a NV17GL [Quadro4 200/400 NVS] + 017b NV17GL [Quadro4 550 XGL] + 017c NV17GL [Quadro4 500 GoGL] + 017d NV17 [GeForce4 410 Go 16M] + 0181 NV18 [GeForce4 MX 440 AGP 8x] + 1043 8063 GeForce4 MX 440 AGP 8X + 1043 806f V9180 Magic + 1462 8880 MS-StarForce GeForce4 MX 440 with AGP8X + 1462 8900 MS-8890 GeForce 4 MX440 AGP8X + 1462 9350 MSI Geforce4 MX T8X with AGP8X + 147b 8f0d Siluro GF4 MX-8X + 0182 NV18 [GeForce4 MX 440SE AGP 8x] + 0183 NV18 [GeForce4 MX 420 AGP 8x] + 0185 NV18 [GeForce4 MX 4000 AGP 8x] + 0186 NV18M [GeForce4 448 Go] + 0187 NV18M [GeForce4 488 Go] + 0188 NV18GL [Quadro4 580 XGL] + 018a NV18GL [Quadro4 NVS AGP 8x] + 018b NV18GL [Quadro4 380 XGL] + 018c Quadro NVS 50 PCI + 018d NV18M [GeForce4 448 Go] + 01a0 NVCrush11 [GeForce2 MX Integrated Graphics] + 01a4 nForce CPU bridge + 01ab nForce 420 Memory Controller (DDR) + 01ac nForce 220/420 Memory Controller + 01ad nForce 220/420 Memory Controller + 01b0 nForce Audio + 01b1 nForce Audio + 01b2 nForce ISA Bridge + 01b4 nForce PCI System Management + 01b7 nForce AGP to PCI Bridge + 01b8 nForce PCI-to-PCI bridge + 01bc nForce IDE + 01c1 nForce AC'97 Modem Controller + 01c2 nForce USB Controller + 01c3 nForce Ethernet Controller + 01d1 GeForce 7300 LE + 1462 0345 7300LE PCI Express Graphics Adapter + 01d6 GeForce Go 7200 + 01d7 Quadro NVS 110M / GeForce Go 7300 + 01d8 GeForce Go 7400 + 01da Quadro NVS 110M + 01de Quadro FX 350 + 10de 01dc Quadro FX Go350M + 01df GeForce 7300 GS + 01e0 nForce2 AGP (different version?) + 147b 1c09 NV7 Motherboard + 01e8 nForce2 AGP + 01ea nForce2 Memory Controller 0 + a0a0 03b9 UK79G-1394 motherboard + 01eb nForce2 Memory Controller 1 + a0a0 03b9 UK79G-1394 motherboard + 01ec nForce2 Memory Controller 2 + a0a0 03b9 UK79G-1394 motherboard + 01ed nForce2 Memory Controller 3 + a0a0 03b9 UK79G-1394 motherboard + 01ee nForce2 Memory Controller 4 + a0a0 03b9 UK79G-1394 motherboard + 01ef nForce2 Memory Controller 5 + a0a0 03b9 UK79G-1394 motherboard + 01f0 NV18 [GeForce4 MX - nForce GPU] + a0a0 03b5 UK79G-1394 motherboard + 0200 NV20 [GeForce3] + 1043 402f AGP-V8200 DDR + 1048 0c70 GLADIAC 920 + 0201 NV20 [GeForce3 Ti 200] + 0202 NV20 [GeForce3 Ti 500] + 1043 405b V8200 T5 + 1545 002f Xtasy 6964 + 0203 NV20DCC [Quadro DCC] + 0211 NV40 [GeForce 6800] + 0212 NV40 [GeForce 6800 LE] + 0215 NV40 [GeForce 6800 GT] + 0218 NV40 [GeForce 6800 XT] + 0221 NV44A [GeForce 6200] + 0240 C51PV [GeForce 6150] + 1462 7207 K8NGM2 series + 0241 C51 PCI Express Bridge + 0242 C51G [GeForce 6100] + 0243 C51 PCI Express Bridge + 0244 C51 PCI Express Bridge + 0245 C51 PCI Express Bridge + 0246 C51 PCI Express Bridge + 0247 C51 PCI Express Bridge + 0248 C51 PCI Express Bridge + 0249 C51 PCI Express Bridge + 024a C51 PCI Express Bridge + 024b C51 PCI Express Bridge + 024c C51 PCI Express Bridge + 024d C51 PCI Express Bridge + 024e C51 PCI Express Bridge + 024f C51 PCI Express Bridge + 0250 NV25 [GeForce4 Ti 4600] + 0251 NV25 [GeForce4 Ti 4400] + 1043 8023 v8440 GeForce 4 Ti4400 + 0252 NV25 [GeForce4 Ti] + 0253 NV25 [GeForce4 Ti 4200] + 107d 2896 WinFast A250 LE TD (Dual VGA/TV-out/DVI) + 147b 8f09 Siluro (Dual VGA/TV-out/DVI) + 0258 NV25GL [Quadro4 900 XGL] + 0259 NV25GL [Quadro4 750 XGL] + 025b NV25GL [Quadro4 700 XGL] + 0260 MCP51 LPC Bridge + 1462 7207 K8NGM2 series + 0261 MCP51 LPC Bridge + 0262 MCP51 LPC Bridge + 0263 MCP51 LPC Bridge + 0264 MCP51 SMBus + 1462 7207 K8NGM2 series + 0265 MCP51 IDE + 1462 7207 K8NGM2 series + 0266 MCP51 Serial ATA Controller + 1462 7207 K8NGM2 series + 0267 MCP51 Serial ATA Controller + 1462 7207 K8NGM2 series + 0268 MCP51 Ethernet Controller + 0269 MCP51 Ethernet Controller + 1462 7207 K8NGM2 series + 026a MCP51 MCI + 026b MCP51 AC97 Audio Controller + 026c MCP51 High Definition Audio + 1462 7207 K8NGM2 series + 026d MCP51 USB Controller + 1462 7207 K8NGM2 series + 026e MCP51 USB Controller + 1462 7207 K8NGM2 series + 026f MCP51 PCI Bridge + 0270 MCP51 Host Bridge + 1462 7207 K8NGM2 series + 0271 MCP51 PMU + 0272 MCP51 Memory Controller 0 + 027e C51 Memory Controller 2 + 1462 7207 K8NGM2 series + 027f C51 Memory Controller 3 + 1462 7207 K8NGM2 series + 0280 NV28 [GeForce4 Ti 4800] + 0281 NV28 [GeForce4 Ti 4200 AGP 8x] + 0282 NV28 [GeForce4 Ti 4800 SE] + 0286 NV28 [GeForce4 Ti 4200 Go AGP 8x] + 0288 NV28GL [Quadro4 980 XGL] + 0289 NV28GL [Quadro4 780 XGL] + 028c NV28GLM [Quadro4 700 GoGL] + 0290 GeForce 7900 GTX + 0291 GeForce 7900 GT + 0292 GeForce 7900 GS + 0298 GeForce Go 7900 GS + 0299 GeForce Go 7900 GTX + 029a G71 [Quadro FX 2500M] + 029b G71 [Quadro FX 1500M] + 029c Quadro FX 5500 + 029d Quadro FX 3500 + 029e Quadro FX 1500 + 029f Quadro FX 4500 X2 +# Xbox Graphics Processing Unit (Integrated). GeForce3 derivative (NV20 < NV2A < NV25). + 02a0 NV2A [XGPU] + 02e1 GeForce 7600 GS + 02f0 C51 Host Bridge + 1462 7207 K8NGM2 series + 02f1 C51 Host Bridge + 02f2 C51 Host Bridge + 02f3 C51 Host Bridge + 02f4 C51 Host Bridge + 02f5 C51 Host Bridge + 02f6 C51 Host Bridge + 02f7 C51 Host Bridge + 02f8 C51 Memory Controller 5 + 1462 7207 K8NGM2 series + 02f9 C51 Memory Controller 4 + 1462 7207 K8NGM2 series + 02fa C51 Memory Controller 0 + 1462 7207 K8NGM2 series + 02fb C51 PCI Express Bridge + 02fc C51 PCI Express Bridge + 02fd C51 PCI Express Bridge + 02fe C51 Memory Controller 1 + 1462 7207 K8NGM2 series + 02ff C51 Host Bridge + 1462 7207 K8NGM2 series + 0300 NV30 [GeForce FX] + 0301 NV30 [GeForce FX 5800 Ultra] + 0302 NV30 [GeForce FX 5800] + 0308 NV30GL [Quadro FX 2000] + 0309 NV30GL [Quadro FX 1000] + 0311 NV31 [GeForce FX 5600 Ultra] + 0312 NV31 [GeForce FX 5600] + 0313 NV31 + 0314 NV31 [GeForce FX 5600XT] + 1043 814a V9560XT/TD + 0316 NV31M + 0317 NV31M Pro + 031a NV31M [GeForce FX Go5600] + 031b NV31M [GeForce FX Go5650] + 031c NVIDIA Quadro FX Go700 + 031d NV31GLM + 031e NV31GLM Pro + 031f NV31GLM Pro + 0320 NV34 [GeForce FX 5200] + 0321 NV34 [GeForce FX 5200 Ultra] + 0322 NV34 [GeForce FX 5200] + 1462 9171 MS-8917 (FX5200-T128) + 1462 9360 MS-8936 (FX5200-T128) + 0323 NV34 [GeForce FX 5200LE] + 0324 NV34M [GeForce FX Go5200] + 1028 0196 Inspiron 5160 + 1071 8160 MIM2000 + 0325 NV34M [GeForce FX Go5250] + 0326 NV34 [GeForce FX 5500] + 0327 NV34 [GeForce FX 5100] + 0328 NV34M [GeForce FX Go5200 32M/64M] + 0329 NV34M [GeForce FX Go5200] + 032a NV34GL [Quadro NVS 280 PCI] + 032b NV34GL [Quadro FX 500/600 PCI] + 032c NV34GLM [GeForce FX Go 5300] + 032d NV34 [GeForce FX Go5100] + 032f NV34GL + 0330 NV35 [GeForce FX 5900 Ultra] + 0331 NV35 [GeForce FX 5900] + 1043 8145 V9950GE + 0332 NV35 [GeForce FX 5900XT] + 0333 NV38 [GeForce FX 5950 Ultra] + 0334 NV35 [GeForce FX 5900ZT] + 0338 NV35GL [Quadro FX 3000] + 033f NV35GL [Quadro FX 700] + 0341 NV36.1 [GeForce FX 5700 Ultra] + 0342 NV36.2 [GeForce FX 5700] + 0343 NV36 [GeForce FX 5700LE] + 0344 NV36.4 [GeForce FX 5700VE] + 0345 NV36.5 + 0347 NV36 [GeForce FX Go5700] + 103c 006a NX9500 + 0348 NV36 [GeForce FX Go5700] + 0349 NV36M Pro + 034b NV36MAP + 034c NV36 [Quadro FX Go1000] + 034e NV36GL [Quadro FX 1100] + 034f NV36GL + 0360 MCP55 LPC Bridge + 0361 MCP55 LPC Bridge + 0362 MCP55 LPC Bridge + 0363 MCP55 LPC Bridge + 0364 MCP55 LPC Bridge + 0365 MCP55 LPC Bridge + 0366 MCP55 LPC Bridge + 0367 MCP55 LPC Bridge + 0368 MCP55 SMBus + 0369 MCP55 Memory Controller + 036a MCP55 Memory Controller + 036b MCP55 SMU + 036c MCP55 USB Controller + 036d MCP55 USB Controller + 036e MCP55 IDE + 0370 MCP55 PCI bridge + 0371 MCP55 High Definition Audio + 0372 MCP55 Ethernet + 0373 MCP55 Ethernet + 0374 MCP55 PCI Express bridge + 0375 MCP55 PCI Express bridge + 0376 MCP55 PCI Express bridge + 0377 MCP55 PCI Express bridge + 0378 MCP55 PCI Express bridge + 037a MCP55 Memory Controller + 037e MCP55 SATA Controller + 037f MCP55 SATA Controller + 0391 G70 [GeForce 7600 GT] + 0392 G70 [GeForce 7600 GS] + 1462 0622 NX7600GS-T2D256EH + 0393 G70 [GeForce 7300 GT] + 0398 G70 [GeForce Go 7600] + 039e Quadro FX 560 + 03a0 C55 Host Bridge + 03a1 C55 Host Bridge + 03a2 C55 Host Bridge + 03a3 C55 Host Bridge + 03a4 C55 Host Bridge + 03a5 C55 Host Bridge + 03a6 C55 Host Bridge + 03a7 C55 Host Bridge + 03a8 C55 Memory Controller + 03a9 C55 Memory Controller + 03aa C55 Memory Controller + 03ab C55 Memory Controller + 03ac C55 Memory Controller + 03ad C55 Memory Controller + 03ae C55 Memory Controller + 03af C55 Memory Controller + 03b0 C55 Memory Controller + 03b1 C55 Memory Controller + 03b2 C55 Memory Controller + 03b3 C55 Memory Controller + 03b4 C55 Memory Controller + 03b5 C55 Memory Controller + 03b6 C55 Memory Controller + 03b7 C55 PCI Express bridge + 03b8 C55 PCI Express bridge + 03b9 C55 PCI Express bridge + 03ba C55 Memory Controller + 03bb C55 PCI Express bridge + 03d0 GeForce 6100 nForce 430 + 03d1 GeForce 6100 nForce 405 + 03d2 GeForce 6100 nForce 400 + 03d5 GeForce 6100 nForce 420 + 03e0 MCP61 LPC Bridge + 03e1 MCP61 LPC Bridge + 03e2 MCP61 LPC Bridge + 03e3 MCP61 LPC Bridge + 03e4 MCP61 High Definition Audio + 03e5 MCP61 Ethernet + 03e6 MCP61 Ethernet + 03e7 MCP61 SATA Controller + 03e8 MCP61 PCI Express bridge + 03e9 MCP61 PCI Express bridge + 03ea MCP61 Memory Controller + 03eb MCP61 SMBus + 03ec MCP61 IDE + 03ee MCP61 Ethernet + 03ef MCP61 Ethernet + 03f0 MCP61 High Definition Audio + 03f1 MCP61 USB Controller + 03f2 MCP61 USB Controller + 03f3 MCP61 PCI bridge + 03f4 MCP61 SMU + 03f5 MCP61 Memory Controller + 03f6 MCP61 SATA Controller + 03f7 MCP61 SATA Controller + 0440 MCP65 LPC Bridge + 0441 MCP65 LPC Bridge + 0442 MCP65 LPC Bridge + 0443 MCP65 LPC Bridge + 0444 MCP65 Memory Controller + 0445 MCP65 Memory Controller + 0446 MCP65 SMBus + 0447 MCP65 SMU + 0448 MCP65 IDE + 0449 MCP65 PCI bridge + 044a MCP65 High Definition Audio + 044b MCP65 High Definition Audio + 044c MCP65 AHCI Controller + 044d MCP65 AHCI Controller + 044e MCP65 AHCI Controller + 044f MCP65 AHCI Controller + 0450 MCP65 Ethernet + 0451 MCP65 Ethernet + 0452 MCP65 Ethernet + 0453 MCP65 Ethernet + 0454 MCP65 USB Controller + 0455 MCP65 USB Controller + 0456 MCP65 USB Controller + 0457 MCP65 USB Controller + 0458 MCP65 PCI Express bridge + 0459 MCP65 PCI Express bridge + 045a MCP65 PCI Express bridge + 045c MCP65 SATA Controller + 045d MCP65 SATA Controller + 045e MCP65 SATA Controller + 045f MCP65 SATA Controller +10df Emulex Corporation + 1ae5 LP6000 Fibre Channel Host Adapter + f085 LP850 Fibre Channel Host Adapter + f095 LP952 Fibre Channel Host Adapter + f098 LP982 Fibre Channel Host Adapter + f0a1 Thor LightPulse Fibre Channel Host Adapter + f0a5 Thor LightPulse Fibre Channel Host Adapter + f0b5 Viper LightPulse Fibre Channel Host Adapter + f0d1 Helios LightPulse Fibre Channel Host Adapter + f0d5 Helios LightPulse Fibre Channel Host Adapter + f0e1 Zephyr LightPulse Fibre Channel Host Adapter + f0e5 Zephyr LightPulse Fibre Channel Host Adapter + f0f5 Neptune LightPulse Fibre Channel Host Adapter + f700 LP7000 Fibre Channel Host Adapter + f701 LP7000 Fibre Channel Host Adapter Alternate ID (JX1:2-3, JX2:1-2) + f800 LP8000 Fibre Channel Host Adapter + f801 LP8000 Fibre Channel Host Adapter Alternate ID (JX1:2-3, JX2:1-2) + f900 LP9000 Fibre Channel Host Adapter + f901 LP9000 Fibre Channel Host Adapter Alternate ID (JX1:2-3, JX2:1-2) + f980 LP9802 Fibre Channel Host Adapter + f981 LP9802 Fibre Channel Host Adapter Alternate ID + f982 LP9802 Fibre Channel Host Adapter Alternate ID + fa00 Thor-X LightPulse Fibre Channel Host Adapter + fb00 Viper LightPulse Fibre Channel Host Adapter + fc00 Thor-X LightPulse Fibre Channel Host Adapter + fc10 Helios-X LightPulse Fibre Channel Host Adapter + fc20 Zephyr-X LightPulse Fibre Channel Host Adapter + fd00 Helios-X LightPulse Fibre Channel Host Adapter + fe00 Zephyr-X LightPulse Fibre Channel Host Adapter + ff00 Neptune LightPulse Fibre Channel Host Adapter +10e0 Integrated Micro Solutions Inc. + 5026 IMS5026/27/28 + 5027 IMS5027 + 5028 IMS5028 + 8849 IMS8849 + 8853 IMS8853 + 9128 IMS9128 [Twin turbo 128] +10e1 Tekram Technology Co.,Ltd. + 0391 TRM-S1040 + 10e1 0391 DC-315U SCSI-3 Host Adapter + 690c DC-690c + dc29 DC-290 +10e2 Aptix Corporation +10e3 Tundra Semiconductor Corp. + 0000 CA91C042 [Universe] + 0108 Tsi108 Host Bridge for Single PowerPC + 0148 Tsi148 [Tempe] + 0860 CA91C860 [QSpan] + 0862 CA91C862A [QSpan-II] + 8260 CA91L8200B [Dual PCI PowerSpan II] + 8261 CA91L8260B [Single PCI PowerSpan II] + a108 Tsi109 Host Bridge for Dual PowerPC +10e4 Tandem Computers + 8029 Realtek 8029 Network Card +10e5 Micro Industries Corporation +10e6 Gainbery Computer Products Inc. +10e7 Vadem +10e8 Applied Micro Circuits Corp. + 1072 INES GPIB-PCI (AMCC5920 based) + 2011 Q-Motion Video Capture/Edit board + 4750 S5930 [Matchmaker] + 5920 S5920 + 8043 LANai4.x [Myrinet LANai interface chip] + 8062 S5933_PARASTATION + 807d S5933 [Matchmaker] + 8088 Kongsberg Spacetec Format Synchronizer + 8089 Kongsberg Spacetec Serial Output Board + 809c S5933_HEPC3 + 80d7 PCI-9112 + 80d9 PCI-9118 + 80da PCI-9812 + 811a PCI-IEEE1355-DS-DE Interface + 814c Fastcom ESCC-PCI (Commtech, Inc.) + 8170 S5933 [Matchmaker] (Chipset Development Tool) + 81e6 Multimedia video controller + 8291 Fastcom 232/8-PCI (Commtech, Inc.) + 82c4 Fastcom 422/4-PCI (Commtech, Inc.) + 82c5 Fastcom 422/2-PCI (Commtech, Inc.) + 82c6 Fastcom IG422/1-PCI (Commtech, Inc.) + 82c7 Fastcom IG232/2-PCI (Commtech, Inc.) + 82ca Fastcom 232/4-PCI (Commtech, Inc.) + 82db AJA HDNTV HD SDI Framestore + 82e2 Fastcom DIO24H-PCI (Commtech, Inc.) + 8851 S5933 on Innes Corp FM Radio Capture card +10e9 Alps Electric Co., Ltd. +10ea Intergraphics Systems + 1680 IGA-1680 + 1682 IGA-1682 + 1683 IGA-1683 + 2000 CyberPro 2000 + 2010 CyberPro 2000A + 5000 CyberPro 5000 + 5050 CyberPro 5050 + 5202 CyberPro 5202 +# CyberPro5202 Audio Function + 5252 CyberPro5252 +10eb Artists Graphics + 0101 3GA + 8111 Twist3 Frame Grabber +10ec Realtek Semiconductor Co., Ltd. + 0139 Zonet Zen3200 + 0883 High Definition Audio + 1025 1605 TravelMate 5600 series + 8029 RTL-8029(AS) + 10b8 2011 EZ-Card (SMC1208) + 10ec 8029 RTL-8029(AS) + 1113 1208 EN1208 + 1186 0300 DE-528 + 1259 2400 AT-2400 + 8129 RTL-8129 + 10ec 8129 RT8129 Fast Ethernet Adapter + 8136 RTL8101E PCI Express Fast Ethernet controller + 8138 RT8139 (B/C) Cardbus Fast Ethernet Adapter + 10ec 8138 RT8139 (B/C) Fast Ethernet Adapter + 8139 RTL-8139/8139C/8139C+ + 0357 000a TTP-Monitoring Card V2.0 + 1025 005a TravelMate 290 + 1025 8920 ALN-325 + 1025 8921 ALN-325 + 103c 006a NX9500 + 1043 8109 P5P800-MX Mainboard + 1071 8160 MIM2000 + 10bd 0320 EP-320X-R + 10ec 8139 RT8139 + 1113 ec01 FNC-0107TX + 1186 1300 DFE-538TX + 1186 1320 SN5200 + 1186 8139 DRN-32TX + 11f6 8139 FN22-3(A) LinxPRO Ethernet Adapter + 1259 2500 AT-2500TX + 1259 2503 AT-2500TX/ACPI + 1429 d010 ND010 + 1432 9130 EN-9130TX + 1436 8139 RT8139 + 1458 e000 GA-7VM400M/7VT600 Motherboard + 1462 788c 865PE Neo2-V Mainboard + 146c 1439 FE-1439TX + 1489 6001 GF100TXRII + 1489 6002 GF100TXRA + 149c 139a LFE-8139ATX + 149c 8139 LFE-8139TX + 14cb 0200 LNR-100 Family 10/100 Base-TX Ethernet + 1695 9001 Onboard RTL8101L 10/100 MBit + 1799 5000 F5D5000 PCI Card/Desktop Network PCI Card + 1904 8139 RTL8139D Fast Ethernet Adapter + 2646 0001 EtheRx + 8e2e 7000 KF-230TX + 8e2e 7100 KF-230TX/2 + a0a0 0007 ALN-325C + 8167 RTL-8169SC Gigabit Ethernet + 8168 RTL8111/8168B PCI Express Gigabit Ethernet controller + 8169 RTL-8169 Gigabit Ethernet + 1025 0079 Aspire 5024WLMi + 1259 c107 CG-LAPCIGT + 1371 434e ProG-2000L + 1458 e000 GA-8I915ME-G Mainboard + 1462 702c K8T NEO 2 motherboard + 8180 RTL8180L 802.11b MAC + 8185 RTL-8185 IEEE 802.11a/b/g Wireless LAN Controller + 8197 SmartLAN56 56K Modem +10ed Ascii Corporation + 7310 V7310 +10ee Xilinx Corporation + 0205 Wildcard TE205P + 0210 Wildcard TE210P + 0314 Wildcard TE405P/TE410P (1st Gen) + 0405 Wildcard TE405P (2nd Gen) + 0410 Wildcard TE410P (2nd Gen) + 3fc0 RME Digi96 + 3fc1 RME Digi96/8 + 3fc2 RME Digi96/8 Pro + 3fc3 RME Digi96/8 Pad + 3fc4 RME Digi9652 (Hammerfall) + 3fc5 RME Hammerfall DSP + 3fc6 RME Hammerfall DSP MADI + 8381 Ellips Santos Frame Grabber + d154 Copley Controls CAN card (PCI-CAN-02) +10ef Racore Computer Products, Inc. + 8154 M815x Token Ring Adapter +10f0 Peritek Corporation +10f1 Tyan Computer + 2865 Tyan Thunder K8E S2865 +10f2 Achme Computer, Inc. +10f3 Alaris, Inc. +10f4 S-MOS Systems, Inc. +10f5 NKK Corporation + a001 NDR4000 [NR4600 Bridge] +10f6 Creative Electronic Systems SA +10f7 Matsushita Electric Industrial Co., Ltd. +10f8 Altos India Ltd +10f9 PC Direct +10fa Truevision + 000c TARGA 1000 +10fb Thesys Gesellschaft fuer Mikroelektronik mbH + 186f TH 6255 +10fc I-O Data Device, Inc. +# What's in the cardbus end of a Sony ACR-A01 card, comes with newer Vaio CD-RW drives + 0003 Cardbus IDE Controller + 0005 Cardbus SCSI CBSC II +10fd Soyo Computer, Inc +10fe Fast Multimedia AG +10ff NCube +1100 Jazz Multimedia +1101 Initio Corporation + 1060 INI-A100U2W + 1622 INI-1623 PCI SATA-II Controller + 9100 INI-9100/9100W + 9400 INI-940 + 9401 INI-950 + 9500 360P + 9502 Initio INI-9100UW Ultra Wide SCSI Controller INIC-950P chip +1102 Creative Labs + 0002 SB Live! EMU10k1 + 1102 0020 CT4850 SBLive! Value + 1102 0021 CT4620 SBLive! + 1102 002f SBLive! mainboard implementation + 1102 100a SB Live! 5.1 Digital OEM [SB0220] + 1102 4001 E-mu APS + 1102 8022 CT4780 SBLive! Value + 1102 8023 CT4790 SoundBlaster PCI512 + 1102 8024 CT4760 SBLive! + 1102 8025 SBLive! Mainboard Implementation + 1102 8026 CT4830 SBLive! Value + 1102 8027 CT4832 SBLive! Value + 1102 8028 CT4760 SBLive! OEM version + 1102 8031 CT4831 SBLive! Value + 1102 8040 CT4760 SBLive! + 1102 8051 CT4850 SBLive! Value + 1102 8061 SBLive! Player 5.1 + 1102 8064 SBLive! 5.1 Model SB0100 + 1102 8065 SBLive! 5.1 Digital Model SB0220 + 1102 8067 SBLive! 5.1 eMicro 28028 + 0004 SB Audigy + 1102 0051 SB0090 Audigy Player + 1102 0053 SB0090 Audigy Player/OEM + 1102 0058 SB0090 Audigy Player/OEM + 1102 1007 SB0240 Audigy 2 Platinum 6.1 + 1102 2002 SB Audigy 2 ZS (SB0350) + 0005 SB X-Fi + 1102 0021 X-Fi Platinum + 1102 1003 X-Fi XtremeMusic + 0006 [SB Live! Value] EMU10k1X + 0007 SB Audigy LS + 1102 0007 SBLive! 24bit + 1102 1001 SB0310 Audigy LS + 1102 1002 SB0312 Audigy LS + 1102 1006 SB0410 SBLive! 24-bit + 1462 1009 K8N Diamond + 0008 SB0400 Audigy2 Value + 1102 0008 EMU0404 Digital Audio System + 4001 SB Audigy FireWire Port + 1102 0010 SB Audigy FireWire Port + 7002 SB Live! Game Port + 1102 0020 Gameport Joystick + 7003 SB Audigy Game Port + 1102 0040 SB Audigy MIDI/Game Port + 7004 [SB Live! Value] Input device controller + 7005 SB Audigy LS Game Port + 1102 1001 SB0310 Audigy LS MIDI/Game port + 1102 1002 SB0312 Audigy LS MIDI/Game port + 8064 SB0100 [SBLive! 5.1 OEM] + 8938 Ectiva EV1938 + 1033 80e5 SlimTower-Jim (NEC) + 1071 7150 Mitac 7150 + 110a 5938 Siemens Scenic Mobile 510PIII + 13bd 100c Ceres-C (Sharp, Intel BX) + 13bd 100d Sharp, Intel Banister + 13bd 100e TwinHead P09S/P09S3 (Sharp) + 13bd f6f1 Marlin (Sharp) + 14ff 0e70 P88TE (TWINHEAD INTERNATIONAL Corp) + 14ff c401 Notebook 9100/9200/2000 (TWINHEAD INTERNATIONAL Corp) + 156d b400 G400 - Geo (AlphaTop (Taiwan)) + 156d b550 G560 (AlphaTop (Taiwan)) + 156d b560 G560 (AlphaTop (Taiwan)) + 156d b700 G700/U700 (AlphaTop (Taiwan)) + 156d b795 G795 (AlphaTop (Taiwan)) + 156d b797 G797 (AlphaTop (Taiwan)) +1103 Triones Technologies, Inc. + 0003 HPT343/345/346/363 + 0004 HPT366/368/370/370A/372/372N + 1103 0001 HPT370A + 1103 0004 HPT366 UDMA66 (r1) / HPT368 UDMA66 (r2) / HPT370 UDMA100 (r3) / HPT370 UDMA100 RAID (r4) + 1103 0005 HPT370 UDMA100 + 0005 HPT372A/372N + 0006 HPT302/302N + 0007 HPT371/371N + 0008 HPT374 + 0009 HPT372N +1104 RasterOps Corp. +1105 Sigma Designs, Inc. + 1105 REALmagic Xcard MPEG 1/2/3/4 DVD Decoder + 8300 REALmagic Hollywood Plus DVD Decoder + 8400 EM840x REALmagic DVD/MPEG-2 Audio/Video Decoder + 8401 EM8401 REALmagic DVD/MPEG-2 A/V Decoder + 8470 EM8470 REALmagic DVD/MPEG-4 A/V Decoder + 8471 EM8471 REALmagic DVD/MPEG-4 A/V Decoder + 8475 EM8475 REALmagic DVD/MPEG-4 A/V Decoder + 1105 0001 REALmagic X-Card + 8476 EM8476 REALmagic DVD/MPEG-4 A/V Decoder + 127d 0000 CineView II + 8485 EM8485 REALmagic DVD/MPEG-4 A/V Decoder + 8486 EM8486 REALmagic DVD/MPEG-4 A/V Decoder +1106 VIA Technologies, Inc. + 0102 Embedded VIA Ethernet Controller + 0130 VT6305 1394.A Controller +# Wrong ID found on Jetway K8M8MS + 0204 K8M800 Host Bridge + 0208 PT890 Host Bridge + 0238 K8T890 Host Bridge + 0258 PT880 Host Bridge + 0259 CN400/PM880 Host Bridge + 0269 KT880 Host Bridge + 0282 K8T800Pro Host Bridge + 1043 80a3 A8V Deluxe + 0290 K8M890 Host Bridge + 0293 PM896 Host Bridge + 0296 P4M800 Host Bridge + 0305 VT8363/8365 [KT133/KM133] + 1019 0987 K7VZA Mainboard + 1043 8033 A7V Mainboard + 1043 803e A7V-E Mainboard + 1043 8042 A7V133/A7V133-C Mainboard + 147b a401 KT7/KT7-RAID/KT7A/KT7A-RAID Mainboard + 0308 PT894 Host Bridge + 0314 CN700/VN800/P4M800CE/Pro Host Bridge + 0324 CX700 Host Bridge + 0327 P4M890 Host Bridge + 0336 K8M890CE Host Bridge + 0340 PT900 Host Bridge + 0351 VT3351 Host Bridge + 0364 P4M900 Host Bridge + 0391 VT8371 [KX133] + 0501 VT8501 [Apollo MVP4] + 0505 VT82C505 +# Shares chip with :0576. The VT82C576M has :1571 instead of :0561. + 0561 VT82C576MV + 0571 VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE + 1019 0985 P6VXA Motherboard + 1019 0a81 L7VTA v1.0 Motherboard (KT400-8235) + 1043 8052 VT8233A Bus Master ATA100/66/33 IDE + 1043 808c A7V8X / A7V333 motherboard + 1043 80a1 A7V8X-X motherboard rev. 1.01 + 1043 80ed A7V600/K8V-X/A8V Deluxe motherboard + 1106 0571 VT82C586/B/VT82C686/A/B/VT8233/A/C/VT8235 PIPC Bus Master IDE + 1179 0001 Magnia Z310 + 1297 f641 FX41 motherboard + 1458 5002 GA-7VAX Mainboard + 1462 7020 K8T NEO 2 motherboard + 147b 1407 KV8-MAX3 motherboard + 1849 0571 K7VT2/K7VT6 motherboard + 0576 VT82C576 3V [Apollo Master] + 0585 VT82C585VP [Apollo VP1/VPX] + 0586 VT82C586/A/B PCI-to-ISA [Apollo VP] + 1106 0000 MVP3 ISA Bridge + 0591 VT8237A SATA 2-Port Controller + 0595 VT82C595 [Apollo VP2] + 0596 VT82C596 ISA [Mobile South] + 1106 0000 VT82C596/A/B PCI to ISA Bridge + 1458 0596 VT82C596/A/B PCI to ISA Bridge + 0597 VT82C597 [Apollo VP3] + 0598 VT82C598 [Apollo MVP3] + 0601 VT8601 [Apollo ProMedia] + 0605 VT8605 [ProSavage PM133] + 1043 802c CUV4X mainboard + 0680 VT82C680 [Apollo P6] + 0686 VT82C686 [Apollo Super South] + 1019 0985 P6VXA Motherboard + 1043 802c CUV4X mainboard + 1043 8033 A7V Mainboard + 1043 803e A7V-E Mainboard + 1043 8040 A7M266 Mainboard + 1043 8042 A7V133/A7V133-C Mainboard + 1106 0000 VT82C686/A PCI to ISA Bridge + 1106 0686 VT82C686/A PCI to ISA Bridge + 1179 0001 Magnia Z310 + 147b a702 KG7-Lite Mainboard + 0691 VT82C693A/694x [Apollo PRO133x] + 1019 0985 P6VXA Motherboard + 1179 0001 Magnia Z310 + 1458 0691 VT82C691 Apollo Pro System Controller + 0693 VT82C693 [Apollo Pro Plus] + 0698 VT82C693A [Apollo Pro133 AGP] + 0926 VT82C926 [Amazon] + 1000 VT82C570MV + 1106 VT82C570MV + 1204 K8M800 Host Bridge + 1208 PT890 Host Bridge + 1238 K8T890 Host Bridge + 1258 PT880 Host Bridge + 1259 CN400/PM880 Host Bridge + 1269 KT880 Host Bridge + 1282 K8T800Pro Host Bridge + 1290 K8M890 Host Bridge + 1293 PM896 Host Bridge + 1296 P4M800 Host Bridge + 1308 PT894 Host Bridge + 1314 CN700/VN800/P4M800CE/Pro Host Bridge + 1324 CX700 Host Bridge + 1327 P4M890 Host Bridge + 1336 K8M890CE Host Bridge + 1340 PT900 Host Bridge + 1351 VT3351 Host Bridge + 1364 P4M900 Host Bridge + 1571 VT82C576M/VT82C586 + 1595 VT82C595/97 [Apollo VP2/97] + 2204 K8M800 Host Bridge + 2208 PT890 Host Bridge + 2238 K8T890 Host Bridge + 2258 PT880 Host Bridge + 2259 CN400/PM880 Host Bridge + 2269 KT880 Host Bridge + 2282 K8T800Pro Host Bridge + 2290 K8M890 Host Bridge + 2293 PM896 Host Bridge + 2296 P4M800 Host Bridge + 2308 PT894 Host Bridge + 2314 CN700/VN800/P4M800CE/Pro Host Bridge + 2324 CX700 Host Bridge + 2327 P4M890 Host Bridge + 2336 K8M890CE Host Bridge + 2340 PT900 Host Bridge + 2351 VT3351 Host Bridge + 2364 P4M900 Host Bridge + 287a VT8251 PCI to PCI Bridge + 287b VT8251 Host Bridge + 287c VT8251 PCIE Root Port + 287d VT8251 PCIE Root Port + 287e VT8251 Ultra VLINK Controller + 3022 CLE266 + 3038 VT82xxxxx UHCI USB 1.1 Controller + 0925 1234 USB Controller + 1019 0985 P6VXA Motherboard + 1019 0a81 L7VTA v1.0 Motherboard (KT400-8235) + 1043 8080 A7V333 motherboard + 1043 808c VT6202 USB2.0 4 port controller + 1043 80a1 A7V8X-X motherboard + 1043 80ed A7V600/K8V-X/A8V Deluxe motherboard + 1179 0001 Magnia Z310 + 1458 5004 GA-7VAX Mainboard + 1462 7020 K8T NEO 2 motherboard + 147b 1407 KV8-MAX3 motherboard + 182d 201d CN-029 USB2.0 4 port PCI Card + 1849 3038 K7VT6 + 3040 VT82C586B ACPI + 3043 VT86C100A [Rhine] + 10bd 0000 VT86C100A Fast Ethernet Adapter + 1106 0100 VT86C100A Fast Ethernet Adapter + 1186 1400 DFE-530TX rev A + 3044 IEEE 1394 Host Controller + 1025 005a TravelMate 290 + 1043 808a A8V Deluxe + 1458 1000 GA-7VT600-1394 Motherboard + 1462 207d K8NGM2 series motherboard + 1462 702d K8T NEO 2 motherboard + 1462 971d MS-6917 + 3050 VT82C596 Power Management + 3051 VT82C596 Power Management + 3053 VT6105M [Rhine-III] + 3057 VT82C686 [Apollo Super ACPI] + 1019 0985 P6VXA Motherboard + 1019 0987 K7VZA Motherboard + 1043 8033 A7V Mainboard + 1043 803e A7V-E Mainboard + 1043 8040 A7M266 Mainboard + 1043 8042 A7V133/A7V133-C Mainboard + 1179 0001 Magnia Z310 + 3058 VT82C686 AC97 Audio Controller + 0e11 0097 SoundMax Digital Integrated Audio + 0e11 b194 Soundmax integrated digital audio + 1019 0985 P6VXA Motherboard + 1019 0987 K7VZA Motherboard + 1043 1106 A7V133/A7V133-C Mainboard + 1106 4511 Onboard Audio on EP7KXA + 1458 7600 Onboard Audio + 1462 3091 MS-6309 Onboard Audio + 1462 3300 MS-6330 Onboard Audio + 15dd 7609 Onboard Audio + 3059 VT8233/A/8235/8237 AC97 Audio Controller + 1019 0a81 L7VTA v1.0 Motherboard (KT400-8235) + 1043 8095 A7V8X Motherboard (Realtek ALC650 codec) + 1043 80a1 A7V8X-X Motherboard + 1043 80b0 A7V600/K8V-X/K8V Deluxe motherboard (ADI AD1980 codec [SoundMAX]) + 1043 812a A8V Deluxe motherboard (Realtek ALC850 codec) + 1106 3059 L7VMM2 Motherboard + 1106 4161 K7VT2 motherboard + 1106 4170 PCPartner P4M800-8237R Motherboard + 1106 4552 Soyo KT-600 Dragon Plus (Realtek ALC 650) + 1297 c160 FX41 motherboard (Realtek ALC650 codec) + 1458 a002 GA-7VAX Onboard Audio (Realtek ALC650) + 1462 0080 K8T NEO 2 motherboard + 1462 3800 KT266 onboard audio + 147b 1407 KV8-MAX3 motherboard + 1849 9761 K7VT6 motherboard + 4005 4710 MSI K7T266 Pro2-RU (MSI-6380 v2) onboard audio (Realtek/ALC 200/200P) + a0a0 01b6 AK77-8XN onboard audio + 3065 VT6102 [Rhine-II] + 1043 80a1 A7V8X-X Motherboard + 1106 0102 VT6102 [Rhine II] Embeded Ethernet Controller on VT8235 + 1186 1400 DFE-530TX rev A + 1186 1401 DFE-530TX rev B + 13b9 1421 LD-10/100AL PCI Fast Ethernet Adapter (rev.B) + 147b 1c09 NV7 Motherboard + 1695 3005 VT6103 + 1695 300c Realtek ALC655 sound chip + 1849 3065 K7VT6 motherboard +# This hosts more than just the Intel 537 codec, it also hosts PCtel (SIL33) and SmartLink (SIL34) codecs + 3068 AC'97 Modem Controller + 1462 309e MS-6309 Saturn Motherboard + 3074 VT8233 PCI to ISA Bridge + 1043 8052 VT8233A + 3091 VT8633 [Apollo Pro266] + 3099 VT8366/A/7 [Apollo KT266/A/333] + 1043 8064 A7V266-E Mainboard + 1043 807f A7V333 Mainboard + 1849 3099 K7VT2 motherboard + 3101 VT8653 Host Bridge + 3102 VT8662 Host Bridge + 3103 VT8615 Host Bridge + 3104 USB 2.0 + 1019 0a81 L7VTA v1.0 Motherboard (KT400-8235) + 1043 808c A7V8X motherboard + 1043 80a1 A7V8X-X motherboard rev 1.01 + 1043 80ed A7V600/K8V-X/A8V Deluxe motherboard + 1297 f641 FX41 motherboard + 1458 5004 GA-7VAX Mainboard + 1462 7020 K8T NEO 2 motherboard + 147b 1407 KV8-MAX3 motherboard + 182d 201d CN-029 USB 2.0 4 port PCI Card + 1849 3104 K7VT6 motherboard + 3106 VT6105 [Rhine-III] + 1186 1403 DFE-530TX rev C + 3108 S3 Unichrome Pro VGA Adapter + 3109 VT8233C PCI to ISA Bridge + 3112 VT8361 [KLE133] Host Bridge + 3113 VPX/VPX2 PCI to PCI Bridge Controller + 3116 VT8375 [KM266/KL266] Host Bridge + 1297 f641 FX41 motherboard + 3118 S3 Unichrome Pro VGA Adapter + 3119 VT6120/VT6121/VT6122 Gigabit Ethernet Adapter + 3122 VT8623 [Apollo CLE266] integrated CastleRock graphics + 3123 VT8623 [Apollo CLE266] + 3128 VT8753 [P4X266 AGP] + 3133 VT3133 Host Bridge + 3147 VT8233A ISA Bridge + 1043 808c A7V333 motherboard + 3148 P4M266 Host Bridge + 3149 VIA VT6420 SATA RAID Controller + 1043 80ed A7V600/K8V Deluxe/K8V-X/A8V Deluxe motherboard + 1458 b003 GA-7VM400AM(F) Motherboard + 1462 7020 K8T Neo 2 Motherboard + 147b 1407 KV8-MAX3 motherboard + 147b 1408 KV7 + 1849 3149 K7VT6 motherboard + 3156 P/KN266 Host Bridge + 3164 VT6410 ATA133 RAID controller + 1043 80f4 P4P800 Mainboard Deluxe ATX + 1462 7028 915P/G Neo2 + 3168 VT8374 P4X400 Host Controller/AGP Bridge + 3177 VT8235 ISA Bridge + 1019 0a81 L7VTA v1.0 Motherboard (KT400-8235) + 1043 808c A7V8X motherboard + 1043 80a1 A7V8X-X motherboard + 1297 f641 FX41 motherboard + 1458 5001 GA-7VAX Mainboard + 1849 3177 K7VT2 motherboard + 3178 ProSavageDDR P4N333 Host Bridge + 3188 VT8385 [K8T800 AGP] Host Bridge + 1043 80a3 K8V Deluxe/K8V-X motherboard + 147b 1407 KV8-MAX3 motherboard + 3189 VT8377 [KT400/KT600 AGP] Host Bridge + 1043 807f A7V8X motherboard + 1458 5000 GA-7VAX Mainboard + 1849 3189 K7VT6 motherboard + 3204 K8M800 Host Bridge + 3205 VT8378 [KM400/A] Chipset Host Bridge + 1458 5000 GA-7VM400M Motherboard + 3208 PT890 Host Bridge + 3213 VPX/VPX2 PCI to PCI Bridge Controller + 3218 K8T800M Host Bridge + 3227 VT8237 ISA bridge [KT600/K8T800/K8T890 South] + 1043 80ed A7V600/K8V-X/A8V Deluxe motherboard + 1106 3227 DFI KT600-AL Motherboard + 1458 5001 GA-7VT600 Motherboard + 147b 1407 KV8-MAX3 motherboard + 1849 3227 K7VT4 motherboard + 3238 K8T890 Host Bridge + 3249 VT6421 IDE RAID Controller + 324a CX700 PCI to PCI Bridge + 324b CX700 Host Bridge + 324e CX700 Internal Module Bus + 3258 PT880 Host Bridge + 3259 CN400/PM880 Host Bridge + 3269 KT880 Host Bridge + 3282 K8T800Pro Host Bridge + 3287 VT8251 PCI to ISA Bridge + 3288 VIA High Definition Audio Controller + 3290 K8M890 Host Bridge + 3296 P4M800 Host Bridge + 3324 CX700 Host Bridge + 3327 P4M890 Host Bridge + 3336 K8M890CE Host Bridge + 3337 VT8237A PCI to ISA Bridge + 3340 PT900 Host Bridge + 3344 UniChrome Pro IGP + 3349 VT8251 AHCI/SATA 4-Port Controller + 3351 VT3351 Host Bridge + 3364 P4M900 Host Bridge + 337a VT8237A PCI to PCI Bridge + 337b VT8237A Host Bridge + 4149 VIA VT6420 (ATA133) Controller + 4204 K8M800 Host Bridge + 4208 PT890 Host Bridge + 4238 K8T890 Host Bridge + 4258 PT880 Host Bridge + 4259 CN400/PM880 Host Bridge + 4269 KT880 Host Bridge + 4282 K8T800Pro Host Bridge + 4290 K8M890 Host Bridge + 4293 PM896 Host Bridge + 4296 P4M800 Host Bridge + 4308 PT894 Host Bridge + 4314 CN700/VN800/P4M800CE/Pro Host Bridge + 4324 CX700 Host Bridge + 4327 P4M890 Host Bridge + 4336 K8M890CE Host Bridge + 4340 PT900 Host Bridge + 4351 VT3351 Host Bridge + 4364 P4M900 Host Bridge + 5030 VT82C596 ACPI [Apollo PRO] + 5208 PT890 I/O APIC Interrupt Controller + 5238 K8T890 I/O APIC Interrupt Controller + 5290 K8M890 I/O APIC Interrupt Controller + 5308 PT894 I/O APIC Interrupt Controller + 5327 P4M890 I/O APIC Interrupt Controller + 5336 K8M890CE I/O APIC Interrupt Controller + 5340 PT900 I/O APIC Interrupt Controller + 5351 VT3351 I/O APIC Interrupt Controller + 5364 P4M900 I/O APIC Interrupt Controller + 6100 VT85C100A [Rhine II] + 6327 P4M890 Security Device + 7204 K8M800 Host Bridge + 7205 VT8378 [S3 UniChrome] Integrated Video + 1458 d000 Gigabyte GA-7VM400(A)M(F) Motherboard + 7208 PT890 Host Bridge + 7238 K8T890 Host Bridge + 7258 PT880 Host Bridge + 7259 CN400/PM880 Host Bridge + 7269 KT880 Host Bridge + 7282 K8T800Pro Host Bridge + 7290 K8M890 Host Bridge + 7293 PM896 Host Bridge + 7296 P4M800 Host Bridge + 7308 PT894 Host Bridge + 7314 CN700/VN800/P4M800CE/Pro Host Bridge + 7324 CX700 Host Bridge + 7327 P4M890 Host Bridge + 7336 K8M890CE Host Bridge + 7340 PT900 Host Bridge + 7351 VT3351 Host Bridge + 7364 P4M900 Host Bridge + 8231 VT8231 [PCI-to-ISA Bridge] + 8235 VT8235 ACPI + 8305 VT8363/8365 [KT133/KM133 AGP] + 8324 CX700 PCI to ISA Bridge + 8391 VT8371 [KX133 AGP] + 8501 VT8501 [Apollo MVP4 AGP] + 8596 VT82C596 [Apollo PRO AGP] + 8597 VT82C597 [Apollo VP3 AGP] + 8598 VT82C598/694x [Apollo MVP3/Pro133x AGP] + 1019 0985 P6VXA Motherboard + 8601 VT8601 [Apollo ProMedia AGP] + 8605 VT8605 [PM133 AGP] + 8691 VT82C691 [Apollo Pro] + 8693 VT82C693 [Apollo Pro Plus] PCI Bridge + a208 PT890 PCI to PCI Bridge Controller + a238 K8T890 PCI to PCI Bridge Controller + a327 P4M890 PCI to PCI Bridge Controller + a364 P4M900 PCI to PCI Bridge Controller + b091 VT8633 [Apollo Pro266 AGP] + b099 VT8366/A/7 [Apollo KT266/A/333 AGP] + b101 VT8653 AGP Bridge + b102 VT8362 AGP Bridge + b103 VT8615 AGP Bridge + b112 VT8361 [KLE133] AGP Bridge + b113 VPX/VPX2 I/O APIC Interrupt Controller + b115 VT8363/8365 [KT133/KM133] PCI Bridge + b168 VT8235 PCI Bridge + b188 VT8237 PCI bridge [K8T800/K8T890 South] + 147b 1407 KV8-MAX3 motherboard + b198 VT8237 PCI Bridge + b213 VPX/VPX2 I/O APIC Interrupt Controller + b999 [K8T890 North / VT8237 South] PCI Bridge + c208 PT890 PCI to PCI Bridge Controller + c238 K8T890 PCI to PCI Bridge Controller + c327 P4M890 PCI to PCI Bridge Controller + c340 PT900 PCI to PCI Bridge Controller + c364 P4M900 PCI to PCI Bridge Controller + d104 VT8237 Integrated Fast Ethernet Controller + d208 PT890 PCI to PCI Bridge Controller + d213 VPX/VPX2 PCI to PCI Bridge Controller + d238 K8T890 PCI to PCI Bridge Controller + d340 PT900 PCI to PCI Bridge Controller + e208 PT890 PCI to PCI Bridge Controller + e238 K8T890 PCI to PCI Bridge Controller + e340 PT900 PCI to PCI Bridge Controller + f208 PT890 PCI to PCI Bridge Controller + f238 K8T890 PCI to PCI Bridge Controller + f340 PT900 PCI to PCI Bridge Controller +1107 Stratus Computers + 0576 VIA VT82C570MV [Apollo] (Wrong vendor ID!) +1108 Proteon, Inc. + 0100 p1690plus_AA + 0101 p1690plus_AB + 0105 P1690Plus + 0108 P1690Plus + 0138 P1690Plus + 0139 P1690Plus + 013c P1690Plus + 013d P1690Plus +1109 Cogent Data Technologies, Inc. + 1400 EM110TX [EX110TX] +110a Siemens Nixdorf AG + 0002 Pirahna 2-port + 0005 Tulip controller, power management, switch extender + 0006 FSC PINC (I/O-APIC) + 0015 FSC Multiprocessor Interrupt Controller + 001d FSC Copernicus Management Controller + 007b FSC Remote Service Controller, mailbox device + 007c FSC Remote Service Controller, shared memory device + 007d FSC Remote Service Controller, SMIC device + 2101 HST SAPHIR V Primary PCI (ISDN/PMx) +# Superfastcom-PCI (Commtech, Inc.) or DSCC4 WAN Adapter + 2102 DSCC4 PEB/PEF 20534 DMA Supported Serial Communication Controller with 4 Channels + 2104 Eicon Diva 2.02 compatible passive ISDN card + 3142 SIMATIC NET CP 5613A1 (Profibus Adapter) + 4021 SIMATIC NET CP 5512 (Profibus and MPI Cardbus Adapter) + 4029 SIMATIC NET CP 5613A2 (Profibus Adapter) + 4942 FPGA I-Bus Tracer for MBD + 6120 SZB6120 +110b Chromatic Research Inc. + 0001 Mpact Media Processor + 0004 Mpact 2 +110c Mini-Max Technology, Inc. +110d Znyx Advanced Systems +110e CPU Technology +110f Ross Technology +1110 Powerhouse Systems + 6037 Firepower Powerized SMP I/O ASIC + 6073 Firepower Powerized SMP I/O ASIC +1111 Santa Cruz Operation +# Also claimed to be RNS or Rockwell International, current PCISIG records list Osicom +1112 Osicom Technologies Inc + 2200 FDDI Adapter + 2300 Fast Ethernet Adapter + 2340 4 Port Fast Ethernet Adapter + 2400 ATM Adapter +1113 Accton Technology Corporation + 1211 SMC2-1211TX + 103c 1207 EN-1207D Fast Ethernet Adapter + 1113 1211 EN-1207D Fast Ethernet Adapter + 1216 EN-1216 Ethernet Adapter + 1113 2242 EN2242 10/100 Ethernet Mini-PCI Card + 111a 1020 SpeedStream 1020 PCI 10/100 Ethernet Adaptor [EN-1207F-TX ?] + 1217 EN-1217 Ethernet Adapter + 5105 10Mbps Network card + 9211 EN-1207D Fast Ethernet Adapter + 1113 9211 EN-1207D Fast Ethernet Adapter + 9511 21x4x DEC-Tulip compatible Fast Ethernet + d301 CPWNA100 (Philips wireless PCMCIA) + ec02 SMC 1244TX v3 +1114 Atmel Corporation + 0506 at76c506 802.11b Wireless Network Adaptor +1115 3D Labs +1116 Data Translation + 0022 DT3001 + 0023 DT3002 + 0024 DT3003 + 0025 DT3004 + 0026 DT3005 + 0027 DT3001-PGL + 0028 DT3003-PGL +1117 Datacube, Inc + 9500 Max-1C SVGA card + 9501 Max-1C image processing +1118 Berg Electronics +1119 ICP Vortex Computersysteme GmbH + 0000 GDT 6000/6020/6050 + 0001 GDT 6000B/6010 + 0002 GDT 6110/6510 + 0003 GDT 6120/6520 + 0004 GDT 6530 + 0005 GDT 6550 + 0006 GDT 6117/6517 + 0007 GDT 6127/6527 + 0008 GDT 6537 + 0009 GDT 6557/6557-ECC + 000a GDT 6115/6515 + 000b GDT 6125/6525 + 000c GDT 6535 + 000d GDT 6555 + 0010 GDT 6115/6515 + 0011 GDT 6125/6525 + 0012 GDT 6535 + 0013 GDT 6555/6555-ECC + 0100 GDT 6117RP/6517RP + 0101 GDT 6127RP/6527RP + 0102 GDT 6537RP + 0103 GDT 6557RP + 0104 GDT 6111RP/6511RP + 0105 GDT 6121RP/6521RP + 0110 GDT 6117RD/6517RD + 0111 GDT 6127RD/6527RD + 0112 GDT 6537RD + 0113 GDT 6557RD + 0114 GDT 6111RD/6511RD + 0115 GDT 6121RD/6521RD + 0118 GDT 6118RD/6518RD/6618RD + 0119 GDT 6128RD/6528RD/6628RD + 011a GDT 6538RD/6638RD + 011b GDT 6558RD/6658RD + 0120 GDT 6117RP2/6517RP2 + 0121 GDT 6127RP2/6527RP2 + 0122 GDT 6537RP2 + 0123 GDT 6557RP2 + 0124 GDT 6111RP2/6511RP2 + 0125 GDT 6121RP2/6521RP2 + 0136 GDT 6113RS/6513RS + 0137 GDT 6123RS/6523RS + 0138 GDT 6118RS/6518RS/6618RS + 0139 GDT 6128RS/6528RS/6628RS + 013a GDT 6538RS/6638RS + 013b GDT 6558RS/6658RS + 013c GDT 6533RS/6633RS + 013d GDT 6543RS/6643RS + 013e GDT 6553RS/6653RS + 013f GDT 6563RS/6663RS + 0166 GDT 7113RN/7513RN/7613RN + 0167 GDT 7123RN/7523RN/7623RN + 0168 GDT 7118RN/7518RN/7518RN + 0169 GDT 7128RN/7528RN/7628RN + 016a GDT 7538RN/7638RN + 016b GDT 7558RN/7658RN + 016c GDT 7533RN/7633RN + 016d GDT 7543RN/7643RN + 016e GDT 7553RN/7653RN + 016f GDT 7563RN/7663RN + 01d6 GDT 4x13RZ + 01d7 GDT 4x23RZ + 01f6 GDT 8x13RZ + 01f7 GDT 8x23RZ + 01fc GDT 8x33RZ + 01fd GDT 8x43RZ + 01fe GDT 8x53RZ + 01ff GDT 8x63RZ + 0210 GDT 6519RD/6619RD + 0211 GDT 6529RD/6629RD + 0260 GDT 7519RN/7619RN + 0261 GDT 7529RN/7629RN + 02ff GDT MAXRP + 0300 GDT NEWRX +111a Efficient Networks, Inc + 0000 155P-MF1 (FPGA) + 0002 155P-MF1 (ASIC) + 0003 ENI-25P ATM + 111a 0000 ENI-25p Miniport ATM Adapter + 0005 SpeedStream (LANAI) + 111a 0001 ENI-3010 ATM + 111a 0009 ENI-3060 ADSL (VPI=0) + 111a 0101 ENI-3010 ATM + 111a 0109 ENI-3060CO ADSL (VPI=0) + 111a 0809 ENI-3060 ADSL (VPI=0 or 8) + 111a 0909 ENI-3060CO ADSL (VPI=0 or 8) + 111a 0a09 ENI-3060 ADSL (VPI=<0..15>) + 0007 SpeedStream ADSL + 111a 1001 ENI-3061 ADSL [ASIC] + 1203 SpeedStream 1023 Wireless PCI Adapter +111b Teledyne Electronic Systems +111c Tricord Systems Inc. + 0001 Powerbis Bridge +111d Integrated Device Technology, Inc. + 0001 IDT77201/77211 155Mbps ATM SAR Controller [NICStAR] + 0003 IDT77222/77252 155Mbps ATM MICRO ABR SAR Controller + 0004 IDT77V252 155Mbps ATM MICRO ABR SAR Controller + 0005 IDT77V222 155Mbps ATM MICRO ABR SAR Controller +111e Eldec +111f Precision Digital Images + 4a47 Precision MX Video engine interface + 5243 Frame capture bus interface +1120 EMC Corporation +1121 Zilog +1122 Multi-tech Systems, Inc. +1123 Excellent Design, Inc. +1124 Leutron Vision AG + 2581 Picport Monochrome +1125 Eurocore +1126 Vigra +1127 FORE Systems Inc + 0200 ForeRunner PCA-200 ATM + 0210 PCA-200PC + 0250 ATM + 0300 ForeRunner PCA-200EPC ATM + 0310 ATM + 0400 ForeRunnerHE ATM Adapter + 1127 0400 ForeRunnerHE ATM +1129 Firmworks +112a Hermes Electronics Company, Ltd. +112b Linotype - Hell AG +112c Zenith Data Systems +112d Ravicad +112e Infomedia Microelectronics Inc. +112f Imaging Technology Inc + 0000 MVC IC-PCI + 0001 MVC IM-PCI Video frame grabber/processor + 0008 PC-CamLink PCI framegrabber +1130 Computervision +1131 Philips Semiconductors + 1561 USB 1.1 Host Controller + 1562 USB 2.0 Host Controller + 3400 SmartPCI56(UCB1500) 56K Modem + 5400 TriMedia TM1000/1100 + 5402 TriMedia TM-1300 + 1244 0f00 Fritz!Card DSL + 5405 TriMedia TM1500 + 5406 TriMedia TM1700 + 7130 SAA7130 Video Broadcast Decoder + 102b 48d0 Matrox CronosPlus + 1048 226b ELSA EX-VISION 300TV + 1131 2001 10MOONS PCI TV CAPTURE CARD + 1131 2005 Techcom (India) TV Tuner Card (SSD-TV-670) + 1461 050c Nagase Sangyo TransGear 3000TV + 1461 10ff AVerMedia DVD EZMaker + 1461 2108 AverMedia AverTV/305 + 1461 2115 AverMedia AverTV Studio 305 + 153b 1152 Terratec Cinergy 200 TV + 185b c100 Compro VideoMate TV PVR/FM + 185b c901 Videomate DVB-T200 + 5168 0138 LifeView FlyVIDEO2000 + 7133 SAA7133/SAA7135 Video Broadcast Decoder + 0000 4091 Beholder BeholdTV 409 FM + 1019 4cb5 Elitegroup ECS TVP3XP FM1236 Tuner Card (NTSC,FM) + 1043 0210 FlyTV mini Asus Digimatrix + 1043 4843 ASUS TV-FM 7133 + 1043 4845 TV-FM 7135 + 1043 4862 P7131 Dual + 1131 2001 Proteus Pro [philips reference design] + 1131 2018 Tiger reference design + 1131 4ee9 MonsterTV Mobile + 11bd 002b PCTV Stereo + 11bd 002e PCTV 110i (saa7133) + 12ab 0800 PURPLE TV + 1421 0335 Instant TV DVB-T Cardbus + 1421 1370 Instant TV (saa7135) + 1435 7330 VFG7330 + 1435 7350 VFG7350 + 1461 1044 AVerTVHD MCE A180 + 1461 f31f Avermedia AVerTV GO 007 FM + 1462 6231 TV@Anywhere plus + 1489 0214 LifeView FlyTV Platinum FM + 14c0 1212 LifeView FlyTV Platinum Mini2 + 153b 1160 Cinergy 250 PCI TV + 153b 1162 Terratec Cinergy 400 mobile + 185b c100 VideoMate TV + 5168 0306 LifeView FlyDVB-T DUO + 5168 0319 LifeView FlyDVB Trio + 5168 0502 LifeView FlyDVB-T Duo CardBus + 5168 0520 LifeView FlyDVB Trio CardBus + 5168 1502 LifeView FlyTV CardBus + 5168 2502 LifeView FlyDVB-T CardBus + 5168 2520 LifeView FlyDVB-S Duo CardBus + 5168 3502 LifeView FlyDVB-T Hybrid CardBus + 5168 3520 LifeView FlyDVB Trio N CardBus + 7134 SAA7134/SAA7135HL Video Broadcast Decoder + 1019 4cb4 Elitegroup ECS TVP3XP FM1216 Tuner Card(PAL-BG,FM) + 1043 0210 Digimatrix TV + 1043 4840 ASUS TV-FM 7134 + 1043 4842 TV-FM 7134 + 1131 2004 EUROPA V3 reference design + 1131 4e85 SKNet Monster TV + 1131 6752 EMPRESS + 11bd 002b PCTV Stereo + 11bd 002d PCTV 300i DVB-T + PAL + 1461 2c00 AverTV Hybrid+FM PCI + 1461 9715 AVerTV Studio 307 + 1461 a70a Avermedia AVerTV 307 + 1461 a70b AverMedia M156 / Medion 2819 + 1461 d6ee Cardbus TV/Radio (E500) + 1471 b7e9 AVerTV Cardbus plus + 153b 1142 Terratec Cinergy 400 TV + 153b 1143 Terratec Cinergy 600 TV + 153b 1158 Terratec Cinergy 600 TV MK3 + 1540 9524 ProVideo PV952 + 16be 0003 Medion 7134 + 185b c200 Compro VideoMate Gold+ Pal + 185b c900 Videomate DVB-T300 + 1894 a006 KNC One TV-Station DVR + 1894 fe01 KNC One TV-Station RDS / Typhoon TV Tuner RDS + 7145 SAA7145 + 7146 SAA7146 + 110a 0000 Fujitsu/Siemens DVB-C card rev1.5 + 110a ffff Fujitsu/Siemens DVB-C card rev1.5 + 1131 4f56 KNC1 DVB-S Budget + 1131 4f60 Fujitsu-Siemens Activy DVB-S Budget Rev AL + 1131 4f61 Activy DVB-S Budget Rev GR + 1131 5f61 Activy DVB-T Budget + 114b 2003 DVRaptor Video Edit/Capture Card + 11bd 0006 DV500 Overlay + 11bd 000a DV500 Overlay + 11bd 000f DV500 Overlay + 13c2 0000 Siemens/Technotrend/Hauppauge DVB card rev1.3 or rev1.5 + 13c2 0001 Technotrend/Hauppauge DVB card rev1.3 or rev1.6 + 13c2 0002 Technotrend/Hauppauge DVB card rev2.1 + 13c2 0003 Technotrend/Hauppauge DVB card rev2.1 + 13c2 0004 Technotrend/Hauppauge DVB card rev2.1 + 13c2 0006 Technotrend/Hauppauge DVB card rev1.3 or rev1.6 + 13c2 0008 Technotrend/Hauppauge DVB-T + 13c2 000a Octal/Technotrend DVB-C for iTV + 13c2 1003 Technotrend-Budget/Hauppauge WinTV-NOVA-S DVB card + 13c2 1004 Technotrend-Budget/Hauppauge WinTV-NOVA-C DVB card + 13c2 1005 Technotrend-Budget/Hauppauge WinTV-NOVA-T DVB card + 13c2 100c Technotrend-Budget/Hauppauge WinTV-NOVA-CI DVB card + 13c2 100f Technotrend-Budget/Hauppauge WinTV-NOVA-CI DVB card + 13c2 1011 Technotrend-Budget/Hauppauge WinTV-NOVA-T DVB card + 13c2 1013 SATELCO Multimedia DVB + 13c2 1016 WinTV-NOVA-SE DVB card + 13c2 1102 Technotrend/Hauppauge DVB card rev2.1 + 153b 1156 Terratec Cynergy 1200C + 9730 SAA9730 Integrated Multimedia and Peripheral Controller + 1131 0000 Integrated Multimedia and Peripheral Controller +1132 Mitel Corp. +1133 Eicon Networks Corporation + 7901 EiconCard S90 + 7902 EiconCard S90 + 7911 EiconCard S91 + 7912 EiconCard S91 + 7941 EiconCard S94 + 7942 EiconCard S94 + 7943 EiconCard S94 + 7944 EiconCard S94 + b921 EiconCard P92 + b922 EiconCard P92 + b923 EiconCard P92 + e001 Diva Pro 2.0 S/T + e002 Diva 2.0 S/T PCI + e003 Diva Pro 2.0 U + e004 Diva 2.0 U PCI + e005 Diva 2.01 S/T PCI + e006 Diva CT S/T PCI + e007 Diva CT U PCI + e008 Diva CT Lite S/T PCI + e009 Diva CT Lite U PCI + e00a Diva ISDN+V.90 PCI + e00b Diva 2.02 PCI S/T + e00c Diva 2.02 PCI U + e00d Diva ISDN Pro 3.0 PCI + e00e Diva ISDN+CT S/T PCI Rev 2 + e010 Diva Server BRI-2M PCI + 110a 0021 Fujitsu Siemens ISDN S0 + e011 Diva Server BRI S/T Rev 2 + e012 Diva Server 4BRI-8M PCI + e013 Diva Server 4BRI Rev 2 + 1133 1300 Diva Server V-4BRI-8 + 1133 e013 Diva Server 4BRI-8M 2.0 PCI + e014 Diva Server PRI-30M PCI + e015 DIVA Server PRI Rev 2 + 1133 e015 Diva Server PRI 2.0 PCI + e016 Diva Server Voice 4BRI PCI + e017 Diva Server Voice 4BRI Rev 2 + 1133 e017 Diva Server Voice 4BRI-8M 2.0 PCI + e018 Diva Server BRI-2M 2.0 PCI + 1133 1800 Diva Server V-BRI-2 + 1133 e018 Diva Server BRI-2M 2.0 PCI + e019 Diva Server Voice PRI Rev 2 + 1133 e019 Diva Server Voice PRI 2.0 PCI + e01a Diva Server 2FX + e01b Diva Server Voice BRI-2M 2.0 PCI + 1133 e01b Diva Server Voice BRI-2M 2.0 PCI + e01c Diva Server PRI Rev 3 + 1133 1c01 Diva Server PRI/E1/T1-8 + 1133 1c02 Diva Server PRI/T1-24 + 1133 1c03 Diva Server PRI/E1-30 + 1133 1c04 Diva Server PRI/E1/T1 + 1133 1c05 Diva Server V-PRI/T1-24 + 1133 1c06 Diva Server V-PRI/E1-30 + 1133 1c07 Diva Server PRI/E1/T1-8 Cornet NQ + 1133 1c08 Diva Server PRI/T1-24 Cornet NQ + 1133 1c09 Diva Server PRI/E1-30 Cornet NQ + 1133 1c0a Diva Server PRI/E1/T1 Cornet NQ + 1133 1c0b Diva Server V-PRI/T1-24 Cornet NQ + 1133 1c0c Diva Server V-PRI/E1-30 Cornet NQ + e01e Diva Server 2PRI + e020 Diva Server 4PRI + e022 Diva Server Analog-2P + e024 Diva Server Analog-4P + 1133 2400 Diva Server V-Analog-4P + 1133 e024 Diva Server Analog-4P + e028 Diva Server Analog-8P + 1133 2800 Diva Server V-Analog-8P + 1133 e028 Diva Server Analog-8P + e02a Diva Server IPM-300 + e02c Diva Server IPM-600 +1134 Mercury Computer Systems + 0001 Raceway Bridge + 0002 Dual PCI to RapidIO Bridge +1135 Fuji Xerox Co Ltd + 0001 Printer controller +1136 Momentum Data Systems +1137 Cisco Systems Inc +1138 Ziatech Corporation + 8905 8905 [STD 32 Bridge] +1139 Dynamic Pictures, Inc + 0001 VGA Compatable 3D Graphics +113a FWB Inc +113b Network Computing Devices +113c Cyclone Microsystems, Inc. + 0000 PCI-9060 i960 Bridge + 0001 PCI-SDK [PCI i960 Evaluation Platform] + 0911 PCI-911 [i960Jx-based Intelligent I/O Controller] + 0912 PCI-912 [i960CF-based Intelligent I/O Controller] + 0913 PCI-913 + 0914 PCI-914 [I/O Controller w/ secondary PCI bus] +113d Leading Edge Products Inc +113e Sanyo Electric Co - Computer Engineering Dept +113f Equinox Systems, Inc. + 0808 SST-64P Adapter + 1010 SST-128P Adapter + 80c0 SST-16P DB Adapter + 80c4 SST-16P RJ Adapter + 80c8 SST-16P Adapter + 8888 SST-4P Adapter + 9090 SST-8P Adapter +1140 Intervoice Inc +1141 Crest Microsystem Inc +1142 Alliance Semiconductor Corporation + 3210 AP6410 + 6422 ProVideo 6422 + 6424 ProVideo 6424 + 6425 ProMotion AT25 + 643d ProMotion AT3D +1143 NetPower, Inc +1144 Cincinnati Milacron + 0001 Noservo controller +1145 Workbit Corporation + 8007 NinjaSCSI-32 Workbit + f007 NinjaSCSI-32 KME + f010 NinjaSCSI-32 Workbit + f012 NinjaSCSI-32 Logitec + f013 NinjaSCSI-32 Logitec + f015 NinjaSCSI-32 Melco + f020 NinjaSCSI-32 Sony PCGA-DVD51 +1146 Force Computers +1147 Interface Corp +# Nee Schneider & Koch +1148 SysKonnect + 4000 FDDI Adapter + 0e11 b03b Netelligent 100 FDDI DAS Fibre SC + 0e11 b03c Netelligent 100 FDDI SAS Fibre SC + 0e11 b03d Netelligent 100 FDDI DAS UTP + 0e11 b03e Netelligent 100 FDDI SAS UTP + 0e11 b03f Netelligent 100 FDDI SAS Fibre MIC + 1148 5521 FDDI SK-5521 (SK-NET FDDI-UP) + 1148 5522 FDDI SK-5522 (SK-NET FDDI-UP DAS) + 1148 5541 FDDI SK-5541 (SK-NET FDDI-FP) + 1148 5543 FDDI SK-5543 (SK-NET FDDI-LP) + 1148 5544 FDDI SK-5544 (SK-NET FDDI-LP DAS) + 1148 5821 FDDI SK-5821 (SK-NET FDDI-UP64) + 1148 5822 FDDI SK-5822 (SK-NET FDDI-UP64 DAS) + 1148 5841 FDDI SK-5841 (SK-NET FDDI-FP64) + 1148 5843 FDDI SK-5843 (SK-NET FDDI-LP64) + 1148 5844 FDDI SK-5844 (SK-NET FDDI-LP64 DAS) + 4200 Token Ring adapter + 4300 SK-9872 Gigabit Ethernet Server Adapter (SK-NET GE-ZX dual link) + 1148 9821 SK-9821 Gigabit Ethernet Server Adapter (SK-NET GE-T) + 1148 9822 SK-9822 Gigabit Ethernet Server Adapter (SK-NET GE-T dual link) + 1148 9841 SK-9841 Gigabit Ethernet Server Adapter (SK-NET GE-LX) + 1148 9842 SK-9842 Gigabit Ethernet Server Adapter (SK-NET GE-LX dual link) + 1148 9843 SK-9843 Gigabit Ethernet Server Adapter (SK-NET GE-SX) + 1148 9844 SK-9844 Gigabit Ethernet Server Adapter (SK-NET GE-SX dual link) + 1148 9861 SK-9861 Gigabit Ethernet Server Adapter (SK-NET GE-SX Volition) + 1148 9862 SK-9862 Gigabit Ethernet Server Adapter (SK-NET GE-SX Volition dual link) + 1148 9871 SK-9871 Gigabit Ethernet Server Adapter (SK-NET GE-ZX) + 1148 9872 SK-9872 Gigabit Ethernet Server Adapter (SK-NET GE-ZX dual link) + 1259 2970 AT-2970SX Gigabit Ethernet Adapter + 1259 2971 AT-2970LX Gigabit Ethernet Adapter + 1259 2972 AT-2970TX Gigabit Ethernet Adapter + 1259 2973 AT-2971SX Gigabit Ethernet Adapter + 1259 2974 AT-2971T Gigabit Ethernet Adapter + 1259 2975 AT-2970SX/2SC Gigabit Ethernet Adapter + 1259 2976 AT-2970LX/2SC Gigabit Ethernet Adapter + 1259 2977 AT-2970TX/2TX Gigabit Ethernet Adapter + 4320 SK-9871 V2.0 Gigabit Ethernet 1000Base-ZX Adapter, PCI64, Fiber ZX/SC + 1148 0121 Marvell RDK-8001 Adapter + 1148 0221 Marvell RDK-8002 Adapter + 1148 0321 Marvell RDK-8003 Adapter + 1148 0421 Marvell RDK-8004 Adapter + 1148 0621 Marvell RDK-8006 Adapter + 1148 0721 Marvell RDK-8007 Adapter + 1148 0821 Marvell RDK-8008 Adapter + 1148 0921 Marvell RDK-8009 Adapter + 1148 1121 Marvell RDK-8011 Adapter + 1148 1221 Marvell RDK-8012 Adapter + 1148 3221 SK-9521 V2.0 10/100/1000Base-T Adapter + 1148 5021 SK-9821 V2.0 Gigabit Ethernet 10/100/1000Base-T Adapter + 1148 5041 SK-9841 V2.0 Gigabit Ethernet 1000Base-LX Adapter + 1148 5043 SK-9843 V2.0 Gigabit Ethernet 1000Base-SX Adapter + 1148 5051 SK-9851 V2.0 Gigabit Ethernet 1000Base-SX Adapter + 1148 5061 SK-9861 V2.0 Gigabit Ethernet 1000Base-SX Adapter + 1148 5071 SK-9871 V2.0 Gigabit Ethernet 1000Base-ZX Adapter + 1148 9521 SK-9521 10/100/1000Base-T Adapter + 4400 SK-9Dxx Gigabit Ethernet Adapter + 4500 SK-9Mxx Gigabit Ethernet Adapter + 9000 SK-9S21 10/100/1000Base-T Server Adapter, PCI-X, Copper RJ-45 + 9843 [Fujitsu] Gigabit Ethernet + 9e00 SK-9E21D 10/100/1000Base-T Adapter, Copper RJ-45 + 1148 2100 SK-9E21 Server Adapter + 1148 21d0 SK-9E21D 10/100/1000Base-T Adapter + 1148 2200 SK-9E22 Server Adapter + 1148 8100 SK-9E81 Server Adapter + 1148 8200 SK-9E82 Server Adapter + 1148 9100 SK-9E91 Server Adapter + 1148 9200 SK-9E92 Server Adapter +1149 Win System Corporation +114a VMIC + 5579 VMIPCI-5579 (Reflective Memory Card) + 5587 VMIPCI-5587 (Reflective Memory Card) + 6504 VMIC PCI 7755 FPGA + 7587 VMIVME-7587 +114b Canopus Co., Ltd +114c Annabooks +114d IC Corporation +114e Nikon Systems Inc +114f Digi International + 0002 AccelePort EPC + 0003 RightSwitch SE-6 + 0004 AccelePort Xem + 0005 AccelePort Xr + 0006 AccelePort Xr,C/X + 0009 AccelePort Xr/J + 000a AccelePort EPC/J + 000c DataFirePRIme T1 (1-port) + 000d SyncPort 2-Port (x.25/FR) + 0011 AccelePort 8r EIA-232 (IBM) + 0012 AccelePort 8r EIA-422 + 0014 AccelePort 8r EIA-422 + 0015 AccelePort Xem + 0016 AccelePort EPC/X + 0017 AccelePort C/X + 001a DataFirePRIme E1 (1-port) + 001b AccelePort C/X (IBM) + 001d DataFire RAS T1/E1/PRI + 114f 0050 DataFire RAS E1 Adapter + 114f 0051 DataFire RAS Dual E1 Adapter + 114f 0052 DataFire RAS T1 Adapter + 114f 0053 DataFire RAS Dual T1 Adapter + 0023 AccelePort RAS + 0024 DataFire RAS B4 ST/U + 114f 0030 DataFire RAS BRI U Adapter + 114f 0031 DataFire RAS BRI S/T Adapter + 0026 AccelePort 4r 920 + 0027 AccelePort Xr 920 + 0028 ClassicBoard 4 + 0029 ClassicBoard 8 + 0034 AccelePort 2r 920 + 0035 DataFire DSP T1/E1/PRI cPCI + 0040 AccelePort Xp + 0042 AccelePort 2p + 0043 AccelePort 4p + 0044 AccelePort 8p + 0045 AccelePort 16p + 004e AccelePort 32p + 0070 Datafire Micro V IOM2 (Europe) + 0071 Datafire Micro V (Europe) + 0072 Datafire Micro V IOM2 (North America) + 0073 Datafire Micro V (North America) + 00b0 Digi Neo 4 + 00b1 Digi Neo 8 + 00c8 Digi Neo 2 DB9 + 00c9 Digi Neo 2 DB9 PRI + 00ca Digi Neo 2 RJ45 + 00cb Digi Neo 2 RJ45 PRI + 00d0 ClassicBoard 4 422 + 00d1 ClassicBoard 8 422 + 6001 Avanstar +1150 Thinking Machines Corp +1151 JAE Electronics Inc. +1152 Megatek +1153 Land Win Electronic Corp +1154 Melco Inc +1155 Pine Technology Ltd +1156 Periscope Engineering +1157 Avsys Corporation +1158 Voarx R & D Inc + 3011 Tokenet/vg 1001/10m anylan + 9050 Lanfleet/Truevalue + 9051 Lanfleet/Truevalue +1159 Mutech Corp + 0001 MV-1000 +115a Harlequin Ltd +115b Parallax Graphics +115c Photron Ltd. +115d Xircom + 0003 Cardbus Ethernet 10/100 + 1014 0181 10/100 EtherJet Cardbus Adapter + 1014 1181 10/100 EtherJet Cardbus Adapter + 1014 8181 10/100 EtherJet Cardbus Adapter + 1014 9181 10/100 EtherJet Cardbus Adapter + 115d 0181 Cardbus Ethernet 10/100 + 115d 0182 RealPort2 CardBus Ethernet 10/100 (R2BE-100) + 115d 1181 Cardbus Ethernet 10/100 + 1179 0181 Cardbus Ethernet 10/100 + 8086 8181 EtherExpress PRO/100 Mobile CardBus 32 Adapter + 8086 9181 EtherExpress PRO/100 Mobile CardBus 32 Adapter + 0005 Cardbus Ethernet 10/100 + 1014 0182 10/100 EtherJet Cardbus Adapter + 1014 1182 10/100 EtherJet Cardbus Adapter + 115d 0182 Cardbus Ethernet 10/100 + 115d 1182 Cardbus Ethernet 10/100 + 0007 Cardbus Ethernet 10/100 + 1014 0182 10/100 EtherJet Cardbus Adapter + 1014 1182 10/100 EtherJet Cardbus Adapter + 115d 0182 Cardbus Ethernet 10/100 + 115d 1182 Cardbus Ethernet 10/100 + 000b Cardbus Ethernet 10/100 + 1014 0183 10/100 EtherJet Cardbus Adapter + 115d 0183 Cardbus Ethernet 10/100 + 000c Mini-PCI V.90 56k Modem + 000f Cardbus Ethernet 10/100 + 1014 0183 10/100 EtherJet Cardbus Adapter + 115d 0183 Cardbus Ethernet 10/100 + 00d4 Mini-PCI K56Flex Modem + 0101 Cardbus 56k modem + 115d 1081 Cardbus 56k Modem + 0103 Cardbus Ethernet + 56k Modem + 1014 9181 Cardbus 56k Modem + 1115 1181 Cardbus Ethernet 100 + 56k Modem + 115d 1181 CBEM56G-100 Ethernet + 56k Modem + 8086 9181 PRO/100 LAN + Modem56 CardBus +115e Peer Protocols Inc +115f Maxtor Corporation +1160 Megasoft Inc +1161 PFU Limited +1162 OA Laboratory Co Ltd +1163 Rendition + 0001 Verite 1000 + 2000 Verite V2000/V2100/V2200 + 1092 2000 Stealth II S220 +1164 Advanced Peripherals Technologies +1165 Imagraph Corporation + 0001 Motion TPEG Recorder/Player with audio +# nee ServerWorks +1166 Broadcom + 0000 CMIC-LE + 0005 CNB20-LE Host Bridge + 0006 CNB20HE Host Bridge + 0007 CNB20-LE Host Bridge + 0008 CNB20HE Host Bridge + 0009 CNB20LE Host Bridge + 0010 CIOB30 + 0011 CMIC-HE + 0012 CMIC-WS Host Bridge (GC-LE chipset) + 0013 CNB20-HE Host Bridge + 0014 CMIC-LE Host Bridge (GC-LE chipset) + 0015 CMIC-GC Host Bridge + 0016 CMIC-GC Host Bridge + 0017 GCNB-LE Host Bridge + 0036 HT1000 PCI/PCI-X bridge + 0101 CIOB-X2 PCI-X I/O Bridge + 0103 EPB PCI-Express to PCI-X Bridge + 0104 HT1000 PCI/PCI-X bridge + 0110 CIOB-E I/O Bridge with Gigabit Ethernet + 0130 HT2000 PCI-X bridge + 0132 HT2000 PCI-Express bridge + 1166 0132 HT2000 PCI-Express bridge + 0140 HT2100 PCI-Express Bridge + 0141 HT2100 PCI-Express Bridge + 0142 HT2100 PCI-Express Bridge + 0200 OSB4 South Bridge + 0201 CSB5 South Bridge + 4c53 1080 CT8 mainboard + 0203 CSB6 South Bridge + 1734 1012 Primergy RX300 + 0205 HT1000 Legacy South Bridge + 0211 OSB4 IDE Controller + 0212 CSB5 IDE Controller + 4c53 1080 CT8 mainboard + 0213 CSB6 RAID/IDE Controller + 1028 4134 PowerEdge 600SC + 1028 c134 Poweredge SC600 + 1734 1012 Primergy RX300 + 0214 HT1000 Legacy IDE controller + 0217 CSB6 IDE Controller + 1028 4134 Poweredge SC600 + 0220 OSB4/CSB5 OHCI USB Controller + 4c53 1080 CT8 mainboard + 0221 CSB6 OHCI USB Controller + 1734 1012 Primergy RX300 + 0223 HT1000 USB Controller + 0225 CSB5 LPC bridge + 0227 GCLE-2 Host Bridge + 1734 1012 Primergy RX300 + 0230 CSB5 LPC bridge + 4c53 1080 CT8 mainboard + 0234 HT1000 LPC Bridge + 0240 K2 SATA + 0241 RAIDCore RC4000 + 0242 RAIDCore BC4000 + 024a BCM5785 (HT1000) SATA Native SATA Mode +# The device starts as 024a, and changes to 024b if set to PATA mode in BIOS + 024b BCM5785 (HT1000) PATA/IDE Mode +1167 Mutoh Industries Inc +1168 Thine Electronics Inc +1169 Centre for Development of Advanced Computing +116a Polaris Communications + 6100 Bus/Tag Channel + 6800 Escon Channel + 7100 Bus/Tag Channel + 7800 Escon Channel +116b Connectware Inc +116c Intelligent Resources Integrated Systems +116d Martin-Marietta +116e Electronics for Imaging +116f Workstation Technology +1170 Inventec Corporation +1171 Loughborough Sound Images Plc +1172 Altera Corporation +1173 Adobe Systems, Inc +1174 Bridgeport Machines +1175 Mitron Computer Inc. +1176 SBE Incorporated +1177 Silicon Engineering +1178 Alfa, Inc. + afa1 Fast Ethernet Adapter +1179 Toshiba America Info Systems + 0102 Extended IDE Controller + 0103 EX-IDE Type-B + 0404 DVD Decoder card + 0406 Tecra Video Capture device + 0407 DVD Decoder card (Version 2) + 0601 CPU to PCI bridge + 1179 0001 Satellite Pro + 0603 ToPIC95 PCI to CardBus Bridge for Notebooks + 060a ToPIC95 + 1179 0001 Satellite Pro + 060f ToPIC97 + 0617 ToPIC100 PCI to Cardbus Bridge with ZV Support + 0618 CPU to PCI and PCI to ISA bridge +# Claimed to be Lucent DSP1645 [Mars], but that's apparently incorrect. Does anyone know the correct ID? + 0701 FIR Port + 0804 TC6371AF SmartMedia Controller + 0805 SD TypA Controller + 0d01 FIR Port Type-DO + 1179 0001 FIR Port Type-DO +117a A-Trend Technology +117b L G Electronics, Inc. +117c Atto Technology + 0030 Ultra320 SCSI Host Adapter + 117c 8013 ExpressPCI UL4D + 117c 8014 ExpressPCI UL4S +117d Becton & Dickinson +117e T/R Systems +117f Integrated Circuit Systems +1180 Ricoh Co Ltd + 0465 RL5c465 + 0466 RL5c466 + 0475 RL5c475 + 144d c006 vpr Matrix 170B4 CardBus bridge + 0476 RL5c476 II + 1014 0185 ThinkPad A/T/X Series + 1028 0188 Inspiron 6000 laptop + 1043 1967 V6800V + 1043 1987 Asus A4K and Z81K notebooks, possibly others ( mid-2005 machines ) + 104d 80df Vaio PCG-FX403 + 104d 80e7 VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP + 144d c00c P35 notebook + 14ef 0220 PCD-RP-220S + 17aa 201c Thinkpad X60s + 0477 RL5c477 + 0478 RL5c478 + 1014 0184 ThinkPad A30p (2653-64G) + 0511 R5C511 + 0522 R5C522 IEEE 1394 Controller + 1014 01cf ThinkPad A30p (2653-64G) + 1043 1967 V6800V + 0551 R5C551 IEEE 1394 Controller + 144d c006 vpr Matrix 170B4 + 0552 R5C552 IEEE 1394 Controller + 1014 0511 ThinkPad A/T/X Series + 1028 0188 Inspiron 6000 laptop + 144d c00c P35 notebook + 17aa 201e Thinkpad X60s + 0554 R5C554 + 0575 R5C575 SD Bus Host Adapter + 0576 R5C576 SD Bus Host Adapter + 0592 R5C592 Memory Stick Bus Host Adapter + 1043 1967 V6800V + 144d c018 X20 IV + 0811 R5C811 + 0822 R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter + 1014 0556 Thinkpad X40 + 1014 0598 Thinkpad Z60m + 1028 0188 Inspiron 6000 laptop + 1028 01a2 Inspiron 9200 + 1043 1967 ASUS V6800V + 144d c018 X20 IV + 17aa 201d Thinkpad X60s + 0841 R5C841 CardBus/SD/SDIO/MMC/MS/MSPro/xD/IEEE1394 + 0852 xD-Picture Card Controller + 1043 1967 V6800V +1181 Telmatics International +1183 Fujikura Ltd +1184 Forks Inc +1185 Dataworld International Ltd +1186 D-Link System Inc + 0100 DC21041 + 1002 DL10050 Sundance Ethernet + 1186 1002 DFE-550TX + 1186 1012 DFE-580TX + 1025 AirPlus Xtreme G DWL-G650 Adapter + 1026 AirXpert DWL-AG650 Wireless Cardbus Adapter + 1043 AirXpert DWL-AG650 Wireless Cardbus Adapter + 1300 RTL8139 Ethernet + 1186 1300 DFE-538TX 10/100 Ethernet Adapter + 1186 1301 DFE-530TX+ 10/100 Ethernet Adapter + 1186 1303 DFE-528TX 10/100 Fast Ethernet PCI Adapter + 1340 DFE-690TXD CardBus PC Card + 1405 DFE-520TX Fast Ethernet PCI Adapter + 1541 DFE-680TXD CardBus PC Card + 1561 DRP-32TXD Cardbus PC Card + 2027 AirPlus Xtreme G DWL-G520 Adapter + 3203 AirPlus Xtreme G DWL-G520 Adapter + 3300 DWL-510 2.4GHz Wireless PCI Adapter + 3a03 AirPro DWL-A650 Wireless Cardbus Adapter(rev.B) + 3a04 AirPro DWL-AB650 Multimode Wireless Cardbus Adapter + 3a05 AirPro DWL-AB520 Multimode Wireless PCI Adapter + 3a07 AirXpert DWL-AG650 Wireless Cardbus Adapter + 3a08 AirXpert DWL-AG520 Wireless PCI Adapter + 3a10 AirXpert DWL-AG650 Wireless Cardbus Adapter(rev.B) + 3a11 AirXpert DWL-AG520 Wireless PCI Adapter(rev.B) + 3a12 AirPlus DWL-G650 Wireless Cardbus Adapter(rev.C) + 3a13 AirPlus DWL-G520 Wireless PCI Adapter(rev.B) + 3a14 AirPremier DWL-AG530 Wireless PCI Adapter + 3a63 AirXpert DWL-AG660 Wireless Cardbus Adapter + 4000 DL2000-based Gigabit Ethernet + 4300 DGE-528T Gigabit Ethernet Adapter +# There are at least 3 revisions of this adapter; 4800 is board revision A1 as far as I can tell, revision B1 is 4c00. + 4800 DGE-530T Gigabit Ethernet Adapter (rev 11) + 4b01 DGE-530T Gigabit Ethernet Adapter (rev 11) + 4c00 Gigabit Ethernet Adapter + 1186 4c00 DGE-530T Gigabit Ethernet Adapter + 8400 D-Link DWL-650+ CardBus PC Card +1187 Advanced Technology Laboratories, Inc. +1188 Shima Seiki Manufacturing Ltd. +1189 Matsushita Electronics Co Ltd +118a Hilevel Technology +118b Hypertec Pty Limited +118c Corollary, Inc + 0014 PCIB [C-bus II to PCI bus host bridge chip] + 1117 Intel 8-way XEON Profusion Chipset [Cache Coherency Filter] +118d BitFlow Inc + 0001 Raptor-PCI framegrabber + 0012 Model 12 Road Runner Frame Grabber + 0014 Model 14 Road Runner Frame Grabber + 0024 Model 24 Road Runner Frame Grabber + 0044 Model 44 Road Runner Frame Grabber + 0112 Model 12 Road Runner Frame Grabber + 0114 Model 14 Road Runner Frame Grabber + 0124 Model 24 Road Runner Frame Grabber + 0144 Model 44 Road Runner Frame Grabber + 0212 Model 12 Road Runner Frame Grabber + 0214 Model 14 Road Runner Frame Grabber + 0224 Model 24 Road Runner Frame Grabber + 0244 Model 44 Road Runner Frame Grabber + 0312 Model 12 Road Runner Frame Grabber + 0314 Model 14 Road Runner Frame Grabber + 0324 Model 24 Road Runner Frame Grabber + 0344 Model 44 Road Runner Frame Grabber +118e Hermstedt GmbH +118f Green Logic +1190 Tripace + c731 TP-910/920/940 PCI Ultra(Wide) SCSI Adapter +1191 Artop Electronic Corp + 0003 SCSI Cache Host Adapter + 0004 ATP8400 + 0005 ATP850UF + 0006 ATP860 NO-BIOS + 0007 ATP860 + 0008 ATP865 NO-ROM + 0009 ATP865 + 8002 AEC6710 SCSI-2 Host Adapter + 8010 AEC6712UW SCSI + 8020 AEC6712U SCSI + 8030 AEC6712S SCSI + 8040 AEC6712D SCSI + 8050 AEC6712SUW SCSI + 8060 AEC6712 SCSI + 8080 AEC67160 SCSI + 8081 AEC67160S SCSI + 808a AEC67162 2-ch. LVD SCSI +1192 Densan Company Ltd +1193 Zeitnet Inc. + 0001 1221 + 0002 1225 +1194 Toucan Technology +1195 Ratoc System Inc +1196 Hytec Electronics Ltd +1197 Gage Applied Sciences, Inc. + 010c CompuScope 82G 8bit 2GS/s Analog Input Card +1198 Lambda Systems Inc +1199 Attachmate Corporation +119a Mind Share, Inc. +119b Omega Micro Inc. + 1221 82C092G +119c Information Technology Inst. +119d Bug, Inc. Sapporo Japan +119e Fujitsu Microelectronics Ltd. + 0001 FireStream 155 + 0003 FireStream 50 +119f Bull HN Information Systems +11a0 Convex Computer Corporation +11a1 Hamamatsu Photonics K.K. +11a2 Sierra Research and Technology +11a3 Deuretzbacher GmbH & Co. Eng. KG +11a4 Barco Graphics NV +11a5 Microunity Systems Eng. Inc +11a6 Pure Data Ltd. +11a7 Power Computing Corp. +11a8 Systech Corp. +11a9 InnoSys Inc. + 4240 AMCC S933Q Intelligent Serial Card +11aa Actel +# Nee Galileo Technology, Inc. +11ab Marvell Technology Group Ltd. + 0146 GT-64010/64010A System Controller + 138f W8300 802.11 Adapter (rev 07) + 1fa6 Marvell W8300 802.11 Adapter + 1fa7 88W8310 and 88W8000G [Libertas] 802.11g client chipset + 1faa 88w8335 [Libertas] 802.11b/g Wireless + 1385 4e00 WG511 v2 54MBit/ Wireless PC-Card + 4320 88E8001 Gigabit Ethernet Controller + 1019 0f38 Marvell 88E8001 Gigabit Ethernet Controller (ECS) + 1019 8001 Marvell 88E8001 Gigabit Ethernet Controller (ECS) + 1043 173c Marvell 88E8001 Gigabit Ethernet Controller (Asus) + 1043 811a Marvell 88E8001 Gigabit Ethernet Controller (Asus) + 105b 0c19 Marvell 88E8001 Gigabit Ethernet Controller (Foxconn) + 10b8 b452 EZ Card 1000 (SMC9452TXV.2) + 11ab 0121 Marvell RDK-8001 + 11ab 0321 Marvell RDK-8003 + 11ab 1021 Marvell RDK-8010 + 11ab 4320 Marvell Yukon Gigabit Ethernet 10/100/1000Baset-T Constroller (Asus) + 11ab 5021 Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Controller (64 bit) + 11ab 9521 Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Controller (32 bit) + 1458 e000 Marvell 88E8001 Gigabit Ethernet Controller (Gigabyte) + 147b 1406 Marvell 88E8001 Gigabit Ethernet Controller (Abit) + 15d4 0047 Marvell 88E8001 Gigabit Ethernet Controller (Iwill) + 1695 9025 Marvell 88E8001 Gigabit Ethernet Controller (Epox) + 17f2 1c03 Marvell 88E8001 Gigabit Ethernet Controller (Albatron) + 270f 2803 Marvell 88E8001 Gigabit Ethernet Controller (Chaintech) + 4340 88E8021 PCI-X IPMI Gigabit Ethernet Controller + 4341 88E8022 PCI-X IPMI Gigabit Ethernet Controller + 4342 88E8061 PCI-E IPMI Gigabit Ethernet Controller + 4343 88E8062 PCI-E IPMI Gigabit Ethernet Controller + 4344 88E8021 PCI-X IPMI Gigabit Ethernet Controller + 4345 88E8022 PCI-X IPMI Gigabit Ethernet Controller + 4346 88E8061 PCI-E IPMI Gigabit Ethernet Controller + 4347 88E8062 PCI-E IPMI Gigabit Ethernet Controller + 4350 88E8035 PCI-E Fast Ethernet Controller + 1179 0001 Marvell 88E8035 Fast Ethernet Controller (Toshiba) + 11ab 3521 Marvell RDK-8035 + 1854 000d Marvell 88E8035 Fast Ethernet Controller (LGE) + 1854 000e Marvell 88E8035 Fast Ethernet Controller (LGE) + 1854 000f Marvell 88E8035 Fast Ethernet Controller (LGE) + 1854 0011 Marvell 88E8035 Fast Ethernet Controller (LGE) + 1854 0012 Marvell 88E8035 Fast Ethernet Controller (LGE) + 1854 0016 Marvell 88E8035 Fast Ethernet Controller (LGE) + 1854 0017 Marvell 88E8035 Fast Ethernet Controller (LGE) + 1854 0018 Marvell 88E8035 Fast Ethernet Controller (LGE) + 1854 0019 Marvell 88E8035 Fast Ethernet Controller (LGE) + 1854 001c Marvell 88E8035 Fast Ethernet Controller (LGE) + 1854 001e Marvell 88E8035 Fast Ethernet Controller (LGE) + 1854 0020 Marvell 88E8035 Fast Ethernet Controller (LGE) + 4351 88E8036 PCI-E Fast Ethernet Controller + 107b 4009 Marvell 88E8036 Fast Ethernet Controller (Wistron) + 10f7 8338 Marvell 88E8036 Fast Ethernet Controller (Panasonic) + 1179 0001 Marvell 88E8036 Fast Ethernet Controller (Toshiba) + 1179 ff00 Marvell 88E8036 Fast Ethernet Controller (Compal) + 1179 ff10 Marvell 88E8036 Fast Ethernet Controller (Inventec) + 11ab 3621 Marvell RDK-8036 + 13d1 ac12 Abocom EFE3K - 10/100 Ethernet Expresscard + 161f 203d Marvell 88E8036 Fast Ethernet Controller (Arima) + 1854 000d Marvell 88E8036 Fast Ethernet Controller (LGE) + 1854 000e Marvell 88E8036 Fast Ethernet Controller (LGE) + 1854 000f Marvell 88E8036 Fast Ethernet Controller (LGE) + 1854 0011 Marvell 88E8036 Fast Ethernet Controller (LGE) + 1854 0012 Marvell 88E8036 Fast Ethernet Controller (LGE) + 1854 0016 Marvell 88E8036 Fast Ethernet Controller (LGE) + 1854 0017 Marvell 88E8036 Fast Ethernet Controller (LGE) + 1854 0018 Marvell 88E8036 Fast Ethernet Controller (LGE) + 1854 0019 Marvell 88E8036 Fast Ethernet Controller (LGE) + 1854 001c Marvell 88E8036 Fast Ethernet Controller (LGE) + 1854 001e Marvell 88E8036 Fast Ethernet Controller (LGE) + 1854 0020 Marvell 88E8036 Fast Ethernet Controller (LGE) + 4352 88E8038 PCI-E Fast Ethernet Controller + 4360 88E8052 PCI-E ASF Gigabit Ethernet Controller + 1043 8134 Marvell 88E8052 Gigabit Ethernet Controller (Asus) + 107b 4009 Marvell 88E8052 Gigabit Ethernet Controller (Wistron) + 11ab 5221 Marvell RDK-8052 + 1458 e000 Marvell 88E8052 Gigabit Ethernet Controller (Gigabyte) + 1462 052c Marvell 88E8052 Gigabit Ethernet Controller (MSI) + 1849 8052 Marvell 88E8052 Gigabit Ethernet Controller (ASRock) + a0a0 0509 Marvell 88E8052 Gigabit Ethernet Controller (Aopen) + 4361 88E8050 PCI-E ASF Gigabit Ethernet Controller + 107b 3015 Marvell 88E8050 Gigabit Ethernet Controller (Gateway) + 11ab 5021 Marvell 88E8050 Gigabit Ethernet Controller (Intel) + 8086 3063 D925XCVLK mainboard + 8086 3439 Marvell 88E8050 Gigabit Ethernet Controller (Intel) + 4362 88E8053 PCI-E Gigabit Ethernet Controller + 103c 2a0d Marvell 88E8053 Gigabit Ethernet Controller (Asus) + 1043 8142 Marvell 88E8053 Gigabit Ethernet controller PCIe (Asus) + 109f 3197 Marvell 88E8053 Gigabit Ethernet Controller (Trigem) + 10f7 8338 Marvell 88E8053 Gigabit Ethernet Controller (Panasonic) + 10fd a430 Marvell 88E8053 Gigabit Ethernet Controller (SOYO) + 1179 0001 Marvell 88E8053 Gigabit Ethernet Controller (Toshiba) + 1179 ff00 Marvell 88E8053 Gigabit Ethernet Controller (Compal) + 1179 ff10 Marvell 88E8053 Gigabit Ethernet Controller (Inventec) + 11ab 5321 Marvell RDK-8053 + 1297 c240 Marvell 88E8053 Gigabit Ethernet Controller (Shuttle) + 1297 c241 Marvell 88E8053 Gigabit Ethernet Controller (Shuttle) + 1297 c242 Marvell 88E8053 Gigabit Ethernet Controller (Shuttle) + 1297 c243 Marvell 88E8053 Gigabit Ethernet Controller (Shuttle) + 1297 c244 Marvell 88E8053 Gigabit Ethernet Controller (Shuttle) + 13d1 ac11 EGE5K - Giga Ethernet Expresscard + 1458 e000 Marvell 88E8053 Gigabit Ethernet Controller (Gigabyte) + 1462 058c Marvell 88E8053 Gigabit Ethernet Controller (MSI) + 14c0 0012 Marvell 88E8053 Gigabit Ethernet Controller (Compal) + 1558 04a0 Marvell 88E8053 Gigabit Ethernet Controller (Clevo) + 15bd 1003 Marvell 88E8053 Gigabit Ethernet Controller (DFI) + 161f 203c Marvell 88E8053 Gigabit Ethernet Controller (Arima) + 161f 203d Marvell 88E8053 Gigabit Ethernet Controller (Arima) + 1695 9029 Marvell 88E8053 Gigabit Ethernet Controller (Epox) + 17f2 2c08 Marvell 88E8053 Gigabit Ethernet Controller (Albatron) + 17ff 0585 Marvell 88E8053 Gigabit Ethernet Controller (Quanta) + 1849 8053 Marvell 88E8053 Gigabit Ethernet Controller (ASRock) + 1854 000b Marvell 88E8053 Gigabit Ethernet Controller (LGE) + 1854 000c Marvell 88E8053 Gigabit Ethernet Controller (LGE) + 1854 0010 Marvell 88E8053 Gigabit Ethernet Controller (LGE) + 1854 0013 Marvell 88E8053 Gigabit Ethernet Controller (LGE) + 1854 0014 Marvell 88E8053 Gigabit Ethernet Controller (LGE) + 1854 0015 Marvell 88E8053 Gigabit Ethernet Controller (LGE) + 1854 001a Marvell 88E8053 Gigabit Ethernet Controller (LGE) + 1854 001b Marvell 88E8053 Gigabit Ethernet Controller (LGE) + 1854 001d Marvell 88E8053 Gigabit Ethernet Controller (LGE) + 1854 001f Marvell 88E8053 Gigabit Ethernet Controller (LGE) + 1854 0021 Marvell 88E8053 Gigabit Ethernet Controller (LGE) + 1854 0022 Marvell 88E8053 Gigabit Ethernet Controller (LGE) + 270f 2801 Marvell 88E8053 Gigabit Ethernet Controller (Chaintech) + a0a0 0506 Marvell 88E8053 Gigabit Ethernet Controller (Aopen) + 4363 88E8055 PCI-E Gigabit Ethernet Controller + 4611 GT-64115 System Controller + 4620 GT-64120/64120A/64121A System Controller + 4801 GT-48001 + 5005 Belkin F5D5005 Gigabit Desktop Network PCI Card + 5040 MV88SX5040 4-port SATA I PCI-X Controller + 5041 MV88SX5041 4-port SATA I PCI-X Controller + 5080 MV88SX5080 8-port SATA I PCI-X Controller + 5081 MV88SX5081 8-port SATA I PCI-X Controller + 6041 MV88SX6041 4-port SATA II PCI-X Controller + 6081 MV88SX6081 8-port SATA II PCI-X Controller + 6460 MV64360/64361/64362 System Controller + 6480 MV64460/64461/64462 System Controller + 6485 MV64460/64461/64462 System Controller, Revision B + f003 GT-64010 Primary Image Piranha Image Generator +11ac Canon Information Systems Research Aust. +11ad Lite-On Communications Inc + 0002 LNE100TX + 11ad 0002 LNE100TX + 11ad 0003 LNE100TX + 11ad f003 LNE100TX + 11ad ffff LNE100TX + 1385 f004 FA310TX + c115 LNE100TX [Linksys EtherFast 10/100] + 11ad c001 LNE100TX [ver 2.0] +11ae Aztech System Ltd +11af Avid Technology Inc. + 0001 Cinema + ee40 Digidesign Audiomedia III +11b0 V3 Semiconductor Inc. + 0002 V300PSC + 0292 V292PBC [Am29030/40 Bridge] + 0960 V96xPBC + c960 V96DPC +11b1 Apricot Computers +11b2 Eastman Kodak +11b3 Barr Systems Inc. +11b4 Leitch Technology International +11b5 Radstone Technology Plc +11b6 United Video Corp +11b7 Motorola +11b8 XPoint Technologies, Inc + 0001 Quad PeerMaster +11b9 Pathlight Technology Inc. + c0ed SSA Controller +11ba Videotron Corp +11bb Pyramid Technology +11bc Network Peripherals Inc + 0001 NP-PCI +11bd Pinnacle Systems Inc. + 002e PCTV 40i + bede AV/DV Studio Capture Card +11be International Microcircuits Inc +11bf Astrodesign, Inc. +11c0 Hewlett Packard +# Nee Lucent Microelectronics +11c1 Agere Systems + 0440 56k WinModem + 1033 8015 LT WinModem 56k Data+Fax+Voice+Dsvd + 1033 8047 LT WinModem 56k Data+Fax+Voice+Dsvd + 1033 804f LT WinModem 56k Data+Fax+Voice+Dsvd + 10cf 102c LB LT Modem V.90 56k + 10cf 104a BIBLO LT Modem 56k + 10cf 105f LB2 LT Modem V.90 56k + 1179 0001 Internal V.90 Modem + 11c1 0440 LT WinModem 56k Data+Fax+Voice+Dsvd + 122d 4101 MDP7800-U Modem + 122d 4102 MDP7800SP-U Modem + 13e0 0040 LT WinModem 56k Data+Fax+Voice+Dsvd + 13e0 0440 LT WinModem 56k Data+Fax+Voice+Dsvd + 13e0 0441 LT WinModem 56k Data+Fax+Voice+Dsvd + 13e0 0450 LT WinModem 56k Data+Fax+Voice+Dsvd + 13e0 f100 LT WinModem 56k Data+Fax+Voice+Dsvd + 13e0 f101 LT WinModem 56k Data+Fax+Voice+Dsvd + 144d 2101 LT56PV Modem + 149f 0440 LT WinModem 56k Data+Fax+Voice+Dsvd + 0441 56k WinModem + 1033 804d LT WinModem 56k Data+Fax + 1033 8065 LT WinModem 56k Data+Fax + 1092 0440 Supra 56i + 1179 0001 Internal V.90 Modem + 11c1 0440 LT WinModem 56k Data+Fax + 11c1 0441 LT WinModem 56k Data+Fax + 122d 4100 MDP7800-U Modem + 13e0 0040 LT WinModem 56k Data+Fax + 13e0 0100 LT WinModem 56k Data+Fax + 13e0 0410 LT WinModem 56k Data+Fax + 13e0 0420 TelePath Internet 56k WinModem + 13e0 0440 LT WinModem 56k Data+Fax + 13e0 0443 LT WinModem 56k Data+Fax + 13e0 f102 LT WinModem 56k Data+Fax + 1416 9804 CommWave 56k Modem + 141d 0440 LT WinModem 56k Data+Fax + 144f 0441 Lucent 56k V.90 DF Modem + 144f 0449 Lucent 56k V.90 DF Modem + 144f 110d Lucent Win Modem + 1468 0441 Presario 56k V.90 DF Modem + 1668 0440 Lucent Win Modem + 0442 56k WinModem + 11c1 0440 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd + 11c1 0442 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd + 13e0 0412 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd + 13e0 0442 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd + 13fc 2471 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd + 144d 2104 LT56PT Modem + 144f 1104 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd + 149f 0440 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd + 1668 0440 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd + 0443 LT WinModem + 0444 LT WinModem + 0445 LT WinModem + 8086 2203 PRO/100+ MiniPCI (probably an Ambit U98.003.C.00 combo card) + 8086 2204 PRO/100+ MiniPCI on Armada E500 + 0446 LT WinModem + 0447 LT WinModem + 0448 WinModem 56k + 1014 0131 Lucent Win Modem + 1033 8066 LT WinModem 56k Data+Fax+Voice+Dsvd + 13e0 0030 56k Voice Modem + 13e0 0040 LT WinModem 56k Data+Fax+Voice+Dsvd +# Actiontech eth+modem card as used by Dell &c. + 1668 2400 LT WinModem 56k (MiniPCI Ethernet+Modem) + 0449 WinModem 56k + 0e11 b14d 56k V.90 Modem + 13e0 0020 LT WinModem 56k Data+Fax + 13e0 0041 TelePath Internet 56k WinModem + 1436 0440 Lucent Win Modem + 144f 0449 Lucent 56k V.90 DFi Modem + 1468 0410 IBM ThinkPad T23 (2647-4MG) + 1468 0440 Lucent Win Modem + 1468 0449 Presario 56k V.90 DFi Modem + 044a F-1156IV WinModem (V90, 56KFlex) + 10cf 1072 LB Global LT Modem + 13e0 0012 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd + 13e0 0042 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd + 144f 1005 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd + 044b LT WinModem + 044c LT WinModem + 044d LT WinModem + 044e LT WinModem + 044f V90 WildWire Modem + 0450 LT WinModem + 1033 80a8 Versa Note Vxi + 144f 4005 Magnia SG20 + 1468 0450 Evo N600c + 4005 144f LifeBook C Series + 0451 LT WinModem + 0452 LT WinModem + 0453 LT WinModem + 0454 LT WinModem + 0455 LT WinModem + 0456 LT WinModem + 0457 LT WinModem + 0458 LT WinModem + 0459 LT WinModem + 045a LT WinModem + 045c LT WinModem + 0461 V90 WildWire Modem + 0462 V90 WildWire Modem + 0480 Venus Modem (V90, 56KFlex) + 048c V.92 56K WinModem +# InPorte Home Internal 56k Modem/fax/answering machine/SMS Features + 048f V.92 56k WinModem + 5801 USB + 5802 USS-312 USB Controller + 5803 USS-344S USB Controller + 5811 FW323 + 8086 524c D865PERL mainboard + dead 0800 FireWire Host Bus Adapter + 8110 T8110 H.100/H.110 TDM switch + 12d9 000c E1/T1 PMXc cPCI carrier card + ab10 WL60010 Wireless LAN MAC + ab11 WL60040 Multimode Wireles LAN MAC + 11c1 ab12 WaveLAN 11abg Cardbus card (Model 1102) + 11c1 ab13 WaveLAN 11abg MiniPCI card (Model 0512) + 11c1 ab15 WaveLAN 11abg Cardbus card (Model 1106) + 11c1 ab16 WaveLAN 11abg MiniPCI card (Model 0516) + ab20 ORiNOCO PCI Adapter + ab21 Agere Wireless PCI Adapter + ab30 Hermes2 Mini-PCI WaveLAN a/b/g + 14cd 2012 Hermes2 Mini-PCI WaveLAN a/b/g + ed00 ET-131x PCI-E Ethernet Controller + ed01 ET-131x PCI-E Ethernet Controller +11c2 Sand Microelectronics +11c3 NEC Corporation +11c4 Document Technologies, Inc +11c5 Shiva Corporation +11c6 Dainippon Screen Mfg. Co. Ltd +11c7 D.C.M. Data Systems +11c8 Dolphin Interconnect Solutions AS + 0658 PSB32 SCI-Adapter D31x + d665 PSB64 SCI-Adapter D32x + d667 PSB66 SCI-Adapter D33x +11c9 Magma + 0010 16-line serial port w/- DMA + 0011 4-line serial port w/- DMA +11ca LSI Systems, Inc +11cb Specialix Research Ltd. + 2000 PCI_9050 + 11cb 0200 SX + 11cb b008 I/O8+ + 4000 SUPI_1 + 8000 T225 +11cc Michels & Kleberhoff Computer GmbH +11cd HAL Computer Systems, Inc. +11ce Netaccess +11cf Pioneer Electronic Corporation +11d0 Lockheed Martin Federal Systems-Manassas +11d1 Auravision + 01f7 VxP524 +11d2 Intercom Inc. +11d3 Trancell Systems Inc +11d4 Analog Devices + 1535 Blackfin BF535 processor + 1805 SM56 PCI modem + 1889 AD1889 sound chip + 1986 AD1986A sound chip + 5340 AD1881 sound chip +11d5 Ikon Corporation + 0115 10115 + 0117 10117 +11d6 Tekelec Telecom +11d7 Trenton Technology, Inc. +11d8 Image Technologies Development +11d9 TEC Corporation +11da Novell +11db Sega Enterprises Ltd +11dc Questra Corporation +11dd Crosfield Electronics Limited +11de Zoran Corporation + 6057 ZR36057PQC Video cutting chipset + 1031 7efe DC10 Plus + 1031 fc00 MiroVIDEO DC50, Motion JPEG Capture/CODEC Board + 12f8 8a02 Tekram Video Kit + 13ca 4231 JPEG/TV Card + 6120 ZR36120 + 1328 f001 Cinemaster C DVD Decoder + 13c2 0000 MediaFocus Satellite TV Card + 1de1 9fff Video Kit C210 +11df New Wave PDG +11e0 Cray Communications A/S +11e1 GEC Plessey Semi Inc. +11e2 Samsung Information Systems America +11e3 Quicklogic Corporation + 0001 COM-ON-AIR Dosch&Amand DECT + 5030 PC Watchdog +11e4 Second Wave Inc +11e5 IIX Consulting +11e6 Mitsui-Zosen System Research +11e7 Toshiba America, Elec. Company +11e8 Digital Processing Systems Inc. +11e9 Highwater Designs Ltd. +11ea Elsag Bailey +11eb Formation Inc. +11ec Coreco Inc +11ed Mediamatics +11ee Dome Imaging Systems Inc +11ef Nicolet Technologies B.V. +11f0 Compu-Shack + 4231 FDDI + 4232 FASTline UTP Quattro + 4233 FASTline FO + 4234 FASTline UTP + 4235 FASTline-II UTP + 4236 FASTline-II FO + 4731 GIGAline +11f1 Symbios Logic Inc +11f2 Picture Tel Japan K.K. +11f3 Keithley Metrabyte +11f4 Kinetic Systems Corporation + 2915 CAMAC controller +11f5 Computing Devices International +11f6 Compex + 0112 ENet100VG4 + 0113 FreedomLine 100 + 1401 ReadyLink 2000 + 2011 RL100-ATX 10/100 + 11f6 2011 RL100-ATX + 2201 ReadyLink 100TX (Winbond W89C840) + 11f6 2011 ReadyLink 100TX + 9881 RL100TX Fast Ethernet +11f7 Scientific Atlanta +11f8 PMC-Sierra Inc. + 7375 PM7375 [LASAR-155 ATM SAR] +11f9 I-Cube Inc +11fa Kasan Electronics Company, Ltd. +11fb Datel Inc +11fc Silicon Magic +11fd High Street Consultants +11fe Comtrol Corporation + 0001 RocketPort 32 port w/external I/F + 0002 RocketPort 8 port w/external I/F + 0003 RocketPort 16 port w/external I/F + 0004 RocketPort 4 port w/quad cable + 0005 RocketPort 8 port w/octa cable + 0006 RocketPort 8 port w/RJ11 connectors + 0007 RocketPort 4 port w/RJ11 connectors + 0008 RocketPort 8 port w/ DB78 SNI (Siemens) connector + 0009 RocketPort 16 port w/ DB78 SNI (Siemens) connector + 000a RocketPort Plus 4 port + 000b RocketPort Plus 8 port + 000c RocketModem 6 port + 000d RocketModem 4-port + 000e RocketPort Plus 2 port RS232 + 000f RocketPort Plus 2 port RS422 + 0801 RocketPort UPCI 32 port w/external I/F + 0802 RocketPort UPCI 8 port w/external I/F + 0803 RocketPort UPCI 16 port w/external I/F + 0805 RocketPort UPCI 8 port w/octa cable + 080c RocketModem III 8 port + 080d RocketModem III 4 port + 0812 RocketPort UPCI Plus 8 port RS422 + 0903 RocketPort Compact PCI 16 port w/external I/F + 8015 RocketPort 4-port UART 16954 +11ff Scion Corporation + 0003 AG-5 +1200 CSS Corporation +1201 Vista Controls Corp +1202 Network General Corp. + 4300 Gigabit Ethernet Adapter + 1202 9841 SK-9841 LX + 1202 9842 SK-9841 LX dual link + 1202 9843 SK-9843 SX + 1202 9844 SK-9843 SX dual link +1203 Bayer Corporation, Agfa Division +1204 Lattice Semiconductor Corporation +1205 Array Corporation +1206 Amdahl Corporation +1208 Parsytec GmbH + 4853 HS-Link Device +1209 SCI Systems Inc +120a Synaptel +120b Adaptive Solutions +120c Technical Corp. +120d Compression Labs, Inc. +120e Cyclades Corporation + 0100 Cyclom-Y below first megabyte + 0101 Cyclom-Y above first megabyte + 0102 Cyclom-4Y below first megabyte + 0103 Cyclom-4Y above first megabyte + 0104 Cyclom-8Y below first megabyte + 0105 Cyclom-8Y above first megabyte + 0200 Cyclades-Z below first megabyte + 0201 Cyclades-Z above first megabyte + 0300 PC300/RSV or /X21 (2 ports) + 0301 PC300/RSV or /X21 (1 port) + 0310 PC300/TE (2 ports) + 0311 PC300/TE (1 port) + 0320 PC300/TE-M (2 ports) + 0321 PC300/TE-M (1 port) + 0400 PC400 +120f Essential Communications + 0001 Roadrunner serial HIPPI +1210 Hyperparallel Technologies +1211 Braintech Inc +1212 Kingston Technology Corp. +1213 Applied Intelligent Systems, Inc. +1214 Performance Technologies, Inc. +1215 Interware Co., Ltd +1216 Purup Prepress A/S +1217 O2 Micro, Inc. + 00f7 Firewire (IEEE 1394) + 6729 OZ6729 + 673a OZ6730 + 6832 OZ6832/6833 CardBus Controller + 6836 OZ6836/6860 CardBus Controller + 6872 OZ6812 CardBus Controller + 6925 OZ6922 CardBus Controller + 6933 OZ6933/711E1 CardBus/SmartCardBus Controller + 1025 1016 Travelmate 612 TX + 6972 OZ601/6912/711E0 CardBus/SmartCardBus Controller + 1014 020c ThinkPad R30 + 1179 0001 Magnia Z310 + 7110 OZ711Mx 4-in-1 MemoryCardBus Accelerator + 103c 088c NC8000 laptop + 103c 0890 NC6000 laptop + 1734 106c Amilo A1645 + 7112 OZ711EC1/M1 SmartCardBus/MemoryCardBus Controller + 7113 OZ711EC1 SmartCardBus Controller + 7114 OZ711M1/MC1 4-in-1 MemoryCardBus Controller + 7120 Integrated MMC/SD Controller + 7130 Integrated MS/xD Controller + 7134 OZ711MP1/MS1 MemoryCardBus Controller + 7135 Cardbus bridge + 71e2 OZ711E2 SmartCardBus Controller + 7212 OZ711M2 4-in-1 MemoryCardBus Controller + 7213 OZ6933E CardBus Controller + 7223 OZ711M3/MC3 4-in-1 MemoryCardBus Controller + 103c 088c NC8000 laptop + 103c 0890 NC6000 laptop + 7233 OZ711MP3/MS3 4-in-1 MemoryCardBus Controller +1218 Hybricon Corp. +1219 First Virtual Corporation +121a 3Dfx Interactive, Inc. + 0001 Voodoo + 0002 Voodoo 2 + 0003 Voodoo Banshee + 1092 0003 Monster Fusion + 1092 4000 Monster Fusion + 1092 4002 Monster Fusion + 1092 4801 Monster Fusion AGP + 1092 4803 Monster Fusion AGP + 1092 8030 Monster Fusion + 1092 8035 Monster Fusion AGP + 10b0 0001 Dragon 4000 + 1102 1018 3D Blaster Banshee VE + 121a 0001 Voodoo Banshee AGP + 121a 0003 Voodoo Banshee AGP SGRAM + 121a 0004 Voodoo Banshee + 139c 0016 Raven + 139c 0017 Raven + 14af 0002 Maxi Gamer Phoenix + 0004 Voodoo Banshee [Velocity 100] + 0005 Voodoo 3 + 121a 0004 Voodoo3 AGP + 121a 0030 Voodoo3 AGP + 121a 0031 Voodoo3 AGP + 121a 0034 Voodoo3 AGP + 121a 0036 Voodoo3 2000 PCI + 121a 0037 Voodoo3 AGP + 121a 0038 Voodoo3 AGP + 121a 003a Voodoo3 AGP + 121a 0044 Voodoo3 + 121a 004b Velocity 100 + 121a 004c Velocity 200 + 121a 004d Voodoo3 AGP + 121a 004e Voodoo3 AGP + 121a 0051 Voodoo3 AGP + 121a 0052 Voodoo3 AGP + 121a 0057 Voodoo3 3000 PCI + 121a 0060 Voodoo3 3500 TV (NTSC) + 121a 0061 Voodoo3 3500 TV (PAL) + 121a 0062 Voodoo3 3500 TV (SECAM) + 0009 Voodoo 4 / Voodoo 5 + 121a 0003 Voodoo5 PCI 5500 + 121a 0009 Voodoo5 AGP 5500/6000 + 0057 Voodoo 3/3000 [Avenger] +121b Advanced Telecommunications Modules +121c Nippon Texaco., Ltd +121d Lippert Automationstechnik GmbH +121e CSPI + 0201 Myrinet 2000 Scalable Cluster Interconnect +121f Arcus Technology, Inc. +1220 Ariel Corporation + 1220 AMCC 5933 TMS320C80 DSP/Imaging board +1221 Contec Co., Ltd +1222 Ancor Communications, Inc. +1223 Artesyn Communication Products + 0003 PM/Link + 0004 PM/T1 + 0005 PM/E1 + 0008 PM/SLS + 0009 BajaSpan Resource Target + 000a BajaSpan Section 0 + 000b BajaSpan Section 1 + 000c BajaSpan Section 2 + 000d BajaSpan Section 3 + 000e PM/PPC +1224 Interactive Images +1225 Power I/O, Inc. +1227 Tech-Source + 0006 Raptor GFX 8P + 0023 Raptor GFX [1100T] +1228 Norsk Elektro Optikk A/S +1229 Data Kinesis Inc. +122a Integrated Telecom +122b LG Industrial Systems Co., Ltd +122c Sican GmbH +122d Aztech System Ltd + 1206 368DSP + 1400 Trident PCI288-Q3DII (NX) + 50dc 3328 Audio + 122d 0001 3328 Audio + 80da 3328 Audio + 122d 0001 3328 Audio +122e Xyratex +122f Andrew Corporation +1230 Fishcamp Engineering +1231 Woodward McCoach, Inc. +1232 GPT Limited +1233 Bus-Tech, Inc. +# Also Bochs uses this for virtual VGA... +1234 Technical Corp. +1235 Risq Modular Systems, Inc. +1236 Sigma Designs Corporation + 0000 RealMagic64/GX + 6401 REALmagic 64/GX (SD 6425) +1237 Alta Technology Corporation +1238 Adtran +1239 3DO Company +123a Visicom Laboratories, Inc. +123b Seeq Technology, Inc. +123c Century Systems, Inc. +123d Engineering Design Team, Inc. + 0000 EasyConnect 8/32 + 0002 EasyConnect 8/64 + 0003 EasyIO +123e Simutech, Inc. +123f C-Cube Microsystems + 00e4 MPEG + 8120 E4? + 11bd 0006 DV500 E4 + 11bd 000a DV500 E4 + 11bd 000f DV500 E4 + 1809 0016 Emuzed MAUI-III PCI PVR FM TV + 8888 Cinemaster C 3.0 DVD Decoder + 1002 0001 Cinemaster C 3.0 DVD Decoder + 1002 0002 Cinemaster C 3.0 DVD Decoder + 1328 0001 Cinemaster C 3.0 DVD Decoder +1240 Marathon Technologies Corp. +1241 DSC Communications +# Formerly Jaycor Networks, Inc. +1242 JNI Corporation + 1560 JNIC-1560 PCI-X Fibre Channel Controller + 1242 6562 FCX2-6562 Dual Channel PCI-X Fibre Channel Adapter + 1242 656a FCX-6562 PCI-X Fibre Channel Adapter + 4643 FCI-1063 Fibre Channel Adapter + 6562 FCX2-6562 Dual Channel PCI-X Fibre Channel Adapter + 656a FCX-6562 PCI-X Fibre Channel Adapter +1243 Delphax +1244 AVM Audiovisuelles MKTG & Computer System GmbH + 0700 B1 ISDN + 0800 C4 ISDN + 0a00 A1 ISDN [Fritz] + 1244 0a00 FRITZ!Card ISDN Controller + 0e00 Fritz!PCI v2.0 ISDN + 1100 C2 ISDN + 1200 T1 ISDN + 2700 Fritz!Card DSL SL + 2900 Fritz!Card DSL v2.0 +1245 A.P.D., S.A. +1246 Dipix Technologies, Inc. +1247 Xylon Research, Inc. +1248 Central Data Corporation +1249 Samsung Electronics Co., Ltd. +124a AEG Electrocom GmbH +124b SBS/Greenspring Modular I/O + 0040 PCI-40A or cPCI-200 Quad IndustryPack carrier + 124b 9080 PCI9080 Bridge +124c Solitron Technologies, Inc. +124d Stallion Technologies, Inc. + 0000 EasyConnection 8/32 + 0002 EasyConnection 8/64 + 0003 EasyIO + 0004 EasyConnection/RA +124e Cylink +124f Infortrend Technology, Inc. + 0041 IFT-2000 Series RAID Controller +1250 Hitachi Microcomputer System Ltd +1251 VLSI Solutions Oy +1253 Guzik Technical Enterprises +1254 Linear Systems Ltd. +1255 Optibase Ltd + 1110 MPEG Forge + 1210 MPEG Fusion + 2110 VideoPlex + 2120 VideoPlex CC + 2130 VideoQuest +1256 Perceptive Solutions, Inc. + 4201 PCI-2220I + 4401 PCI-2240I + 5201 PCI-2000 +1257 Vertex Networks, Inc. +1258 Gilbarco, Inc. +1259 Allied Telesyn International + 2560 AT-2560 Fast Ethernet Adapter (i82557B) + a117 RTL81xx Fast Ethernet + a11e RTL81xx Fast Ethernet + a120 21x4x DEC-Tulip compatible 10/100 Ethernet +125a ABB Power Systems +125b Asix Electronics Corporation + 1400 ALFA GFC2204 Fast Ethernet + 1186 1100 AX8814X Based PCI Fast Ethernet Adapter +125c Aurora Technologies, Inc. + 0101 Saturn 4520P + 0640 Aries 16000P +125d ESS Technology + 0000 ES336H Fax Modem (Early Model) + 1948 Solo? + 1968 ES1968 Maestro 2 + 1028 0085 ES1968 Maestro-2 PCI + 1033 8051 ES1968 Maestro-2 Audiodrive + 1969 ES1969 Solo-1 Audiodrive + 1014 0166 ES1969 SOLO-1 AudioDrive on IBM Aptiva Mainboard + 125d 8888 Solo-1 Audio Adapter + 153b 111b Terratec 128i PCI + 1978 ES1978 Maestro 2E + 0e11 b112 Armada M700/E500 + 1033 803c ES1978 Maestro-2E Audiodrive + 1033 8058 ES1978 Maestro-2E Audiodrive + 1092 4000 Monster Sound MX400 + 1179 0001 ES1978 Maestro-2E Audiodrive + 1988 ES1988 Allegro-1 + 0e11 0098 Evo N600c + 1092 4100 Sonic Impact S100 + 125d 1988 ESS Allegro-1 Audiodrive + 1989 ESS Modem + 125d 1989 ESS Modem + 1998 ES1983S Maestro-3i PCI Audio Accelerator + 1028 00b1 Latitude C600 + 1028 00e6 ES1983S Maestro-3i (Dell Inspiron 8100) + 1999 ES1983S Maestro-3i PCI Modem Accelerator + 199a ES1983S Maestro-3i PCI Audio Accelerator + 199b ES1983S Maestro-3i PCI Modem Accelerator + 2808 ES336H Fax Modem (Later Model) + 2838 ES2838/2839 SuperLink Modem + 2898 ES2898 Modem + 125d 0424 ES56-PI Data Fax Modem + 125d 0425 ES56T-PI Data Fax Modem + 125d 0426 ES56V-PI Data Fax Modem + 125d 0427 VW-PI Data Fax Modem + 125d 0428 ES56ST-PI Data Fax Modem + 125d 0429 ES56SV-PI Data Fax Modem + 147a c001 ES56-PI Data Fax Modem + 14fe 0428 ES56-PI Data Fax Modem + 14fe 0429 ES56-PI Data Fax Modem +125e Specialvideo Engineering SRL +125f Concurrent Technologies, Inc. +1260 Intersil Corporation + 3872 Prism 2.5 Wavelan chipset + 1468 0202 LAN-Express IEEE 802.11b Wireless LAN + 3873 Prism 2.5 Wavelan chipset + 1186 3501 DWL-520 Wireless PCI Adapter + 1186 3700 DWL-520 Wireless PCI Adapter, Rev E1 + 1385 4105 MA311 802.11b wireless adapter + 1668 0414 HWP01170-01 802.11b PCI Wireless Adapter + 16a5 1601 AIR.mate PC-400 PCI Wireless LAN Adapter + 1737 3874 WMP11 Wireless 802.11b PCI Adapter + 8086 2513 Wireless 802.11b MiniPCI Adapter + 3886 ISL3886 [Prism Javelin/Prism Xbow] + 17cf 0037 XG-901 and clones Wireless Adapter + 3890 ISL3890 [Prism GT/Prism Duette]/ISL3886 [Prism Javelin/Prism Xbow] + 10b8 2802 SMC2802W Wireless PCI Adapter + 10b8 2835 SMC2835W Wireless Cardbus Adapter + 10b8 a835 SMC2835W V2 Wireless Cardbus Adapter + 1113 4203 WN4201B + 1113 ee03 SMC2802W V2 Wireless PCI Adapter [ISL3886] + 1113 ee08 SMC2835W V3 EU Wireless Cardbus Adapter + 1186 3202 DWL-G650 A1 Wireless Adapter + 1259 c104 CG-WLCB54GT Wireless Adapter + 1260 0000 WG511 Wireless Adapter + 1385 4800 WG511 Wireless Adapter + 16a5 1605 ALLNET ALL0271 Wireless PCI Adapter + 17cf 0014 XG-600 and clones Wireless Adapter + 17cf 0020 XG-900 and clones Wireless Adapter + 8130 HMP8130 NTSC/PAL Video Decoder + 8131 HMP8131 NTSC/PAL Video Decoder +# This is probably more likely a HW fault, but I am keeping it for now --mj + ffff ISL3886IK + 1260 0000 Senao 3054MP+ (J) mini-PCI WLAN 802.11g adapter +1261 Matsushita-Kotobuki Electronics Industries, Ltd. +1262 ES Computer Company, Ltd. +1263 Sonic Solutions +1264 Aval Nagasaki Corporation +1265 Casio Computer Co., Ltd. +1266 Microdyne Corporation + 0001 NE10/100 Adapter (i82557B) + 1910 NE2000Plus (RT8029) Ethernet Adapter + 1266 1910 NE2000Plus Ethernet Adapter +1267 S. A. Telecommunications + 5352 PCR2101 + 5a4b Telsat Turbo +1268 Tektronix +1269 Thomson-CSF/TTM +126a Lexmark International, Inc. +126b Adax, Inc. +126c Northern Telecom + 1211 10/100BaseTX [RTL81xx] + 126c 802.11b Wireless Ethernet Adapter +126d Splash Technology, Inc. +126e Sumitomo Metal Industries, Ltd. +126f Silicon Motion, Inc. + 0501 SM501 VoyagerGX Rev. AA + 0510 SM501 VoyagerGX Rev. B + 0710 SM710 LynxEM + 0712 SM712 LynxEM+ + 0720 SM720 Lynx3DM + 0730 SM731 Cougar3DR + 0810 SM810 LynxE + 0811 SM811 LynxE + 0820 SM820 Lynx3D + 0910 SM910 +1270 Olympus Optical Co., Ltd. +1271 GW Instruments +1272 Telematics International +1273 Hughes Network Systems + 0002 DirecPC +1274 Ensoniq + 1171 ES1373 [AudioPCI] (also Creative Labs CT5803) + 1371 ES1371 [AudioPCI-97] + 0e11 0024 AudioPCI on Motherboard Compaq Deskpro + 0e11 b1a7 ES1371, ES1373 AudioPCI + 1033 80ac ES1371, ES1373 AudioPCI + 1042 1854 Tazer + 107b 8054 Tabor2 + 1274 1371 Creative Sound Blaster AudioPCI64V, AudioPCI128 + 1274 8001 CT4751 board + 1462 6470 ES1371, ES1373 AudioPCI On Motherboard MS-6147 1.1A + 1462 6560 ES1371, ES1373 AudioPCI On Motherboard MS-6156 1.10 + 1462 6630 ES1371, ES1373 AudioPCI On Motherboard MS-6163BX 1.0A + 1462 6631 ES1371, ES1373 AudioPCI On Motherboard MS-6163VIA 1.0A + 1462 6632 ES1371, ES1373 AudioPCI On Motherboard MS-6163BX 2.0A + 1462 6633 ES1371, ES1373 AudioPCI On Motherboard MS-6163VIA 2.0A + 1462 6820 ES1371, ES1373 AudioPCI On Motherboard MS-6182 1.00 + 1462 6822 ES1371, ES1373 AudioPCI On Motherboard MS-6182 1.00A + 1462 6830 ES1371, ES1373 AudioPCI On Motherboard MS-6183 1.00 + 1462 6880 ES1371, ES1373 AudioPCI On Motherboard MS-6188 1.00 + 1462 6900 ES1371, ES1373 AudioPCI On Motherboard MS-6190 1.00 + 1462 6910 ES1371, ES1373 AudioPCI On Motherboard MS-6191 + 1462 6930 ES1371, ES1373 AudioPCI On Motherboard MS-6193 + 1462 6990 ES1371, ES1373 AudioPCI On Motherboard MS-6199BX 2.0A + 1462 6991 ES1371, ES1373 AudioPCI On Motherboard MS-6199VIA 2.0A + 14a4 2077 ES1371, ES1373 AudioPCI On Motherboard KR639 + 14a4 2105 ES1371, ES1373 AudioPCI On Motherboard MR800 + 14a4 2107 ES1371, ES1373 AudioPCI On Motherboard MR801 + 14a4 2172 ES1371, ES1373 AudioPCI On Motherboard DR739 + 1509 9902 ES1371, ES1373 AudioPCI On Motherboard KW11 + 1509 9903 ES1371, ES1373 AudioPCI On Motherboard KW31 + 1509 9904 ES1371, ES1373 AudioPCI On Motherboard KA11 + 1509 9905 ES1371, ES1373 AudioPCI On Motherboard KC13 + 152d 8801 ES1371, ES1373 AudioPCI On Motherboard CP810E + 152d 8802 ES1371, ES1373 AudioPCI On Motherboard CP810 + 152d 8803 ES1371, ES1373 AudioPCI On Motherboard P3810E + 152d 8804 ES1371, ES1373 AudioPCI On Motherboard P3810-S + 152d 8805 ES1371, ES1373 AudioPCI On Motherboard P3820-S + 270f 2001 ES1371, ES1373 AudioPCI On Motherboard 6CTR + 270f 2200 ES1371, ES1373 AudioPCI On Motherboard 6WTX + 270f 3000 ES1371, ES1373 AudioPCI On Motherboard 6WSV + 270f 3100 ES1371, ES1373 AudioPCI On Motherboard 6WIV2 + 270f 3102 ES1371, ES1373 AudioPCI On Motherboard 6WIV + 270f 7060 ES1371, ES1373 AudioPCI On Motherboard 6ASA2 + 8086 4249 ES1371, ES1373 AudioPCI On Motherboard BI440ZX + 8086 424c ES1371, ES1373 AudioPCI On Motherboard BL440ZX + 8086 425a ES1371, ES1373 AudioPCI On Motherboard BZ440ZX + 8086 4341 ES1371, ES1373 AudioPCI On Motherboard Cayman + 8086 4343 ES1371, ES1373 AudioPCI On Motherboard Cape Cod + 8086 4541 D815EEA Motherboard + 8086 4649 ES1371, ES1373 AudioPCI On Motherboard Fire Island + 8086 464a ES1371, ES1373 AudioPCI On Motherboard FJ440ZX + 8086 4d4f ES1371, ES1373 AudioPCI On Motherboard Montreal + 8086 4f43 ES1371, ES1373 AudioPCI On Motherboard OC440LX + 8086 5243 ES1371, ES1373 AudioPCI On Motherboard RC440BX + 8086 5352 ES1371, ES1373 AudioPCI On Motherboard SunRiver + 8086 5643 ES1371, ES1373 AudioPCI On Motherboard Vancouver + 8086 5753 ES1371, ES1373 AudioPCI On Motherboard WS440BX + 5000 ES1370 [AudioPCI] + 5880 5880 AudioPCI + 1274 2000 Creative Sound Blaster AudioPCI128 + 1274 2003 Creative SoundBlaster AudioPCI 128 + 1274 5880 Creative Sound Blaster AudioPCI128 + 1274 8001 Sound Blaster 16PCI 4.1ch + 1458 a000 5880 AudioPCI On Motherboard 6OXET + 1462 6880 5880 AudioPCI On Motherboard MS-6188 1.00 + 270f 2001 5880 AudioPCI On Motherboard 6CTR + 270f 2200 5880 AudioPCI On Motherboard 6WTX + 270f 7040 5880 AudioPCI On Motherboard 6ATA4 +1275 Network Appliance Corporation +1276 Switched Network Technologies, Inc. +1277 Comstream +1278 Transtech Parallel Systems Ltd. + 0701 TPE3/TM3 PowerPC Node + 0710 TPE5 PowerPC PCI board +1279 Transmeta Corporation + 0060 TM8000 Northbridge + 0061 TM8000 AGP bridge + 0295 Northbridge + 0395 LongRun Northbridge + 0396 SDRAM controller + 0397 BIOS scratchpad +127a Rockwell International + 1002 HCF 56k Data/Fax Modem + 1092 094c SupraExpress 56i PRO [Diamond SUP2380] + 122d 4002 HPG / MDP3858-U + 122d 4005 MDP3858-E + 122d 4007 MDP3858-A/-NZ + 122d 4012 MDP3858-SA + 122d 4017 MDP3858-W + 122d 4018 MDP3858-W + 127a 1002 Rockwell 56K D/F HCF Modem + 1003 HCF 56k Data/Fax Modem + 0e11 b0bc 229-DF Zephyr + 0e11 b114 229-DF Cheetah + 1033 802b 229-DF + 13df 1003 PCI56RX Modem + 13e0 0117 IBM + 13e0 0147 IBM F-1156IV+/R3 Spain V.90 Modem + 13e0 0197 IBM + 13e0 01c7 IBM F-1156IV+/R3 WW V.90 Modem + 13e0 01f7 IBM + 1436 1003 IBM + 1436 1103 IBM 5614PM3G V.90 Modem + 1436 1602 Compaq 229-DF Ducati + 1004 HCF 56k Data/Fax/Voice Modem + 1048 1500 MicroLink 56k Modem + 10cf 1059 Fujitsu 229-DFRT + 1005 HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem + 1005 127a AOpen FM56-P + 1033 8029 229-DFSV + 1033 8054 Modem + 10cf 103c Fujitsu + 10cf 1055 Fujitsu 229-DFSV + 10cf 1056 Fujitsu 229-DFSV + 122d 4003 MDP3858SP-U + 122d 4006 Packard Bell MDP3858V-E + 122d 4008 MDP3858SP-A/SP-NZ + 122d 4009 MDP3858SP-E + 122d 4010 MDP3858V-U + 122d 4011 MDP3858SP-SA + 122d 4013 MDP3858V-A/V-NZ + 122d 4015 MDP3858SP-W + 122d 4016 MDP3858V-W + 122d 4019 MDP3858V-SA + 13df 1005 PCI56RVP Modem + 13e0 0187 IBM + 13e0 01a7 IBM + 13e0 01b7 IBM DF-1156IV+/R3 Spain V.90 Modem + 13e0 01d7 IBM DF-1156IV+/R3 WW V.90 Modem + 1436 1005 IBM + 1436 1105 IBM + 1437 1105 IBM 5614PS3G V.90 Modem + 1022 HCF 56k Modem + 1436 1303 M3-5614PM3G V.90 Modem + 1023 HCF 56k Data/Fax Modem + 122d 4020 Packard Bell MDP3858-WE + 122d 4023 MDP3858-UE + 13e0 0247 IBM F-1156IV+/R6 Spain V.90 Modem + 13e0 0297 IBM + 13e0 02c7 IBM F-1156IV+/R6 WW V.90 Modem + 1436 1203 IBM + 1436 1303 IBM + 1024 HCF 56k Data/Fax/Voice Modem + 1025 HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem + 10cf 106a Fujitsu 235-DFSV + 122d 4021 Packard Bell MDP3858V-WE + 122d 4022 MDP3858SP-WE + 122d 4024 MDP3858V-UE + 122d 4025 MDP3858SP-UE + 1026 HCF 56k PCI Speakerphone Modem + 1032 HCF 56k Modem + 1033 HCF 56k Modem + 1034 HCF 56k Modem + 1035 HCF 56k PCI Speakerphone Modem + 1036 HCF 56k Modem + 1085 HCF 56k Volcano PCI Modem + 2005 HCF 56k Data/Fax Modem + 104d 8044 229-DFSV + 104d 8045 229-DFSV + 104d 8055 PBE/Aztech 235W-DFSV + 104d 8056 235-DFSV + 104d 805a Modem + 104d 805f Modem + 104d 8074 Modem + 2013 HSF 56k Data/Fax Modem + 1179 0001 Modem + 1179 ff00 Modem + 2014 HSF 56k Data/Fax/Voice Modem + 10cf 1057 Fujitsu Citicorp III + 122d 4050 MSP3880-U + 122d 4055 MSP3880-W + 2015 HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem + 10cf 1063 Fujitsu + 10cf 1064 Fujitsu + 1468 2015 Fujitsu + 2016 HSF 56k Data/Fax/Voice/Spkp Modem + 122d 4051 MSP3880V-W + 122d 4052 MSP3880SP-W + 122d 4054 MSP3880V-U + 122d 4056 MSP3880SP-U + 122d 4057 MSP3880SP-A + 4311 Riptide HSF 56k PCI Modem + 127a 4311 Ring Modular? Riptide HSF RT HP Dom + 13e0 0210 HP-GVC + 4320 Riptide PCI Audio Controller + 1235 4320 Riptide PCI Audio Controller + 4321 Riptide HCF 56k PCI Modem + 1235 4321 Hewlett Packard DF + 1235 4324 Hewlett Packard DF + 13e0 0210 Hewlett Packard DF + 144d 2321 Riptide + 4322 Riptide PCI Game Controller + 1235 4322 Riptide PCI Game Controller + 8234 RapidFire 616X ATM155 Adapter + 108d 0022 RapidFire 616X ATM155 Adapter + 108d 0027 RapidFire 616X ATM155 Adapter +127b Pixera Corporation +127c Crosspoint Solutions, Inc. +127d Vela Research +127e Winnov, L.P. +127f Fujifilm +1280 Photoscript Group Ltd. +1281 Yokogawa Electric Corporation +1282 Davicom Semiconductor, Inc. + 9009 Ethernet 100/10 MBit + 9100 21x4x DEC-Tulip compatible 10/100 Ethernet + 9102 21x4x DEC-Tulip compatible 10/100 Ethernet + 9132 Ethernet 100/10 MBit +1283 Integrated Technology Express, Inc. + 673a IT8330G + 8211 ITE 8211F Single Channel UDMA 133 (ASUS 8211 (ITE IT8212 ATA RAID Controller)) + 1043 8138 P5GD1-VW Mainboard + 8212 IT/ITE8212 Dual channel ATA RAID controller (PCI version seems to be IT8212, embedded seems to be ITE8212) + 1283 0001 IT/ITE8212 Dual channel ATA RAID controller + 8330 IT8330G + 8872 IT8874F PCI Dual Serial Port Controller + 8888 IT8888F PCI to ISA Bridge with SMB + 8889 IT8889F PCI to ISA Bridge + e886 IT8330G +1284 Sahara Networks, Inc. +1285 Platform Technologies, Inc. + 0100 AGOGO sound chip (aka ESS Maestro 1) +1286 Mazet GmbH +1287 M-Pact, Inc. + 001e LS220D DVD Decoder + 001f LS220C DVD Decoder +1288 Timestep Corporation +1289 AVC Technology, Inc. +128a Asante Technologies, Inc. +128b Transwitch Corporation +128c Retix Corporation +128d G2 Networks, Inc. + 0021 ATM155 Adapter +128e Hoontech Corporation/Samho Multi Tech Ltd. + 0008 ST128 WSS/SB + 0009 ST128 SAM9407 + 000a ST128 Game Port + 000b ST128 MPU Port + 000c ST128 Ctrl Port +128f Tateno Dennou, Inc. +1290 Sord Computer Corporation +1291 NCS Computer Italia +1292 Tritech Microelectronics Inc +1293 Media Reality Technology +1294 Rhetorex, Inc. +1295 Imagenation Corporation +1296 Kofax Image Products +1297 Holco Enterprise Co, Ltd/Shuttle Computer +1298 Spellcaster Telecommunications Inc. +1299 Knowledge Technology Lab. +129a VMetro, inc. + 0615 PBT-615 PCI-X Bus Analyzer +129b Image Access +129c Jaycor +129d Compcore Multimedia, Inc. +129e Victor Company of Japan, Ltd. +129f OEC Medical Systems, Inc. +12a0 Allen-Bradley Company +12a1 Simpact Associates, Inc. +12a2 Newgen Systems Corporation +12a3 Lucent Technologies + 8105 T8105 H100 Digital Switch +12a4 NTT Electronics Technology Company +12a5 Vision Dynamics Ltd. +12a6 Scalable Networks, Inc. +12a7 AMO GmbH +12a8 News Datacom +12a9 Xiotech Corporation +12aa SDL Communications, Inc. +12ab Yuan Yuan Enterprise Co., Ltd. + 0002 AU8830 [Vortex2] Based Sound Card With A3D Support + 3000 MPG-200C PCI DVD Decoder Card +12ac Measurex Corporation +12ad Multidata GmbH +12ae Alteon Networks Inc. + 0001 AceNIC Gigabit Ethernet + 1014 0104 Gigabit Ethernet-SX PCI Adapter + 12ae 0001 Gigabit Ethernet-SX (Universal) + 1410 0104 Gigabit Ethernet-SX PCI Adapter + 0002 AceNIC Gigabit Ethernet (Copper) + 10a9 8002 Acenic Gigabit Ethernet + 12ae 0002 Gigabit Ethernet-T (3C986-T) + 00fa Farallon PN9100-T Gigabit Ethernet +12af TDK USA Corp +12b0 Jorge Scientific Corp +12b1 GammaLink +12b2 General Signal Networks +12b3 Inter-Face Co Ltd +12b4 FutureTel Inc +12b5 Granite Systems Inc. +12b6 Natural Microsystems +12b7 Cognex Modular Vision Systems Div. - Acumen Inc. +12b8 Korg +# Nee US Robotics +12b9 3Com Corp, Modem Division + 1006 WinModem + 12b9 005c USR 56k Internal Voice WinModem (Model 3472) + 12b9 005e USR 56k Internal WinModem (Models 662975) + 12b9 0062 USR 56k Internal Voice WinModem (Model 662978) + 12b9 0068 USR 56k Internal Voice WinModem (Model 5690) + 12b9 007a USR 56k Internal Voice WinModem (Model 662974) + 12b9 007f USR 56k Internal WinModem (Models 5698, 5699) + 12b9 0080 USR 56k Internal WinModem (Models 2975, 3528) + 12b9 0081 USR 56k Internal Voice WinModem (Models 2974, 3529) + 12b9 0091 USR 56k Internal Voice WinModem (Model 2978) + 1007 USR 56k Internal WinModem + 12b9 00a3 USR 56k Internal WinModem (Model 3595) + 12b9 00c4 U.S. Robotics 56K Voice Win Int (2884a) + 1008 56K FaxModem Model 5610 + 12b9 00a2 USR 56k Internal FAX Modem (Model 2977) + 12b9 00aa USR 56k Internal Voice Modem (Model 2976) + 12b9 00ab USR 56k Internal Voice Modem (Model 5609) + 12b9 00ac USR 56k Internal Voice Modem (Model 3298) + 12b9 00ad USR 56k Internal FAX Modem (Model 5610) +12ba BittWare, Inc. +12bb Nippon Unisoft Corporation +12bc Array Microsystems +12bd Computerm Corp. +12be Anchor Chips Inc. + 3041 AN3041Q CO-MEM + 3042 AN3042Q CO-MEM Lite + 12be 3042 Anchor Chips Lite Evaluation Board +12bf Fujifilm Microdevices +12c0 Infimed +12c1 GMM Research Corp +12c2 Mentec Limited +12c3 Holtek Microelectronics Inc + 0058 PCI NE2K Ethernet + 5598 PCI NE2K Ethernet +12c4 Connect Tech Inc + 0001 Blue HEAT/PCI 8 (RS232/CL/RJ11) + 0002 Blue HEAT/PCI 4 (RS232) + 0003 Blue HEAT/PCI 2 (RS232) + 0004 Blue HEAT/PCI 8 (UNIV, RS485) + 0005 Blue HEAT/PCI 4+4/6+2 (UNIV, RS232/485) + 0006 Blue HEAT/PCI 4 (OPTO, RS485) + 0007 Blue HEAT/PCI 2+2 (RS232/485) + 0008 Blue HEAT/PCI 2 (OPTO, Tx, RS485) + 0009 Blue HEAT/PCI 2+6 (RS232/485) + 000a Blue HEAT/PCI 8 (Tx, RS485) + 000b Blue HEAT/PCI 4 (Tx, RS485) + 000c Blue HEAT/PCI 2 (20 MHz, RS485) + 000d Blue HEAT/PCI 2 PTM + 0100 NT960/PCI + 0201 cPCI Titan - 2 Port + 0202 cPCI Titan - 4 Port + 0300 CTI PCI UART 2 (RS232) + 0301 CTI PCI UART 4 (RS232) + 0302 CTI PCI UART 8 (RS232) + 0310 CTI PCI UART 1+1 (RS232/485) + 0311 CTI PCI UART 2+2 (RS232/485) + 0312 CTI PCI UART 4+4 (RS232/485) + 0320 CTI PCI UART 2 + 0321 CTI PCI UART 4 + 0322 CTI PCI UART 8 + 0330 CTI PCI UART 2 (RS485) + 0331 CTI PCI UART 4 (RS485) + 0332 CTI PCI UART 8 (RS485) +12c5 Picture Elements Incorporated + 007e Imaging/Scanning Subsystem Engine + 007f Imaging/Scanning Subsystem Engine + 0081 PCIVST [Grayscale Thresholding Engine] + 0085 Video Simulator/Sender + 0086 THR2 Multi-scale Thresholder +12c6 Mitani Corporation +12c7 Dialogic Corp +12c8 G Force Co, Ltd +12c9 Gigi Operations +12ca Integrated Computing Engines +12cb Antex Electronics Corporation +12cc Pluto Technologies International +12cd Aims Lab +12ce Netspeed Inc. +12cf Prophet Systems, Inc. +12d0 GDE Systems, Inc. +12d1 PSITech +12d2 NVidia / SGS Thomson (Joint Venture) + 0008 NV1 + 0009 DAC64 + 0018 Riva128 + 1048 0c10 VICTORY Erazor + 107b 8030 STB Velocity 128 + 1092 0350 Viper V330 + 1092 1092 Viper V330 + 10b4 1b1b STB Velocity 128 + 10b4 1b1d STB Velocity 128 + 10b4 1b1e STB Velocity 128, PAL TV-Out + 10b4 1b20 STB Velocity 128 Sapphire + 10b4 1b21 STB Velocity 128 + 10b4 1b22 STB Velocity 128 AGP, NTSC TV-Out + 10b4 1b23 STB Velocity 128 AGP, PAL TV-Out + 10b4 1b27 STB Velocity 128 DVD + 10b4 1b88 MVP Pro 128 + 10b4 222a STB Velocity 128 AGP + 10b4 2230 STB Velocity 128 + 10b4 2232 STB Velocity 128 + 10b4 2235 STB Velocity 128 AGP + 2a15 54a3 3DVision-SAGP / 3DexPlorer 3000 + 0019 Riva128ZX + 0020 TNT + 0028 TNT2 + 0029 UTNT2 + 002c VTNT2 + 00a0 ITNT2 +12d3 Vingmed Sound A/S +12d4 Ulticom (Formerly DGM&S) + 0200 T1 Card +12d5 Equator Technologies Inc + 0003 BSP16 + 1000 BSP15 +12d6 Analogic Corp +12d7 Biotronic SRL +12d8 Pericom Semiconductor + 8150 PCI to PCI Bridge +12d9 Aculab PLC + 0002 PCI Prosody + 0004 cPCI Prosody + 0005 Aculab E1/T1 PCI card + 1078 Prosody X class e1000 device + 12d9 000d Prosody X PCI +12da True Time Inc. +12db Annapolis Micro Systems, Inc +12dc Symicron Computer Communication Ltd. +12dd Management Graphics +12de Rainbow Technologies + 0200 CryptoSwift CS200 +12df SBS Technologies Inc +12e0 Chase Research + 0010 ST16C654 Quad UART + 0020 ST16C654 Quad UART + 0030 ST16C654 Quad UART +12e1 Nintendo Co, Ltd +12e2 Datum Inc. Bancomm-Timing Division +12e3 Imation Corp - Medical Imaging Systems +12e4 Brooktrout Technology Inc +12e5 Apex Semiconductor Inc +12e6 Cirel Systems +12e7 Sunsgroup Corporation +12e8 Crisc Corp +12e9 GE Spacenet +12ea Zuken +12eb Aureal Semiconductor + 0001 Vortex 1 + 104d 8036 AU8820 Vortex Digital Audio Processor + 1092 2000 Sonic Impact A3D + 1092 2100 Sonic Impact A3D + 1092 2110 Sonic Impact A3D + 1092 2200 Sonic Impact A3D + 122d 1002 AU8820 Vortex Digital Audio Processor + 12eb 0001 AU8820 Vortex Digital Audio Processor + 5053 3355 Montego + 0002 Vortex 2 + 104d 8049 AU8830 Vortex 3D Digital Audio Processor + 104d 807b AU8830 Vortex 3D Digital Audio Processor + 1092 3000 Monster Sound II + 1092 3001 Monster Sound II + 1092 3002 Monster Sound II + 1092 3003 Monster Sound II + 1092 3004 Monster Sound II + 12eb 0002 AU8830 Vortex 3D Digital Audio Processor + 12eb 0088 AU8830 Vortex 3D Digital Audio Processor + 144d 3510 AU8830 Vortex 3D Digital Audio Processor + 5053 3356 Montego II + 0003 AU8810 Vortex Digital Audio Processor + 104d 8049 AU8810 Vortex Digital Audio Processor + 104d 8077 AU8810 Vortex Digital Audio Processor + 109f 1000 AU8810 Vortex Digital Audio Processor + 12eb 0003 AU8810 Vortex Digital Audio Processor + 1462 6780 AU8810 Vortex Digital Audio Processor + 14a4 2073 AU8810 Vortex Digital Audio Processor + 14a4 2091 AU8810 Vortex Digital Audio Processor + 14a4 2104 AU8810 Vortex Digital Audio Processor + 14a4 2106 AU8810 Vortex Digital Audio Processor + 8803 Vortex 56k Software Modem + 12eb 8803 Vortex 56k Software Modem +12ec 3A International, Inc. +12ed Optivision Inc. +12ee Orange Micro +12ef Vienna Systems +12f0 Pentek +12f1 Sorenson Vision Inc +12f2 Gammagraphx, Inc. +12f3 Radstone Technology +12f4 Megatel +12f5 Forks +12f6 Dawson France +12f7 Cognex +12f8 Electronic Design GmbH + 0002 VideoMaker +12f9 Four Fold Ltd +12fb Spectrum Signal Processing + 0001 PMC-MAI + 00f5 F5 Dakar + 02ad PMC-2MAI + 2adc ePMC-2ADC + 3100 PRO-3100 + 3500 PRO-3500 + 4d4f Modena + 8120 ePMC-8120 + da62 Daytona C6201 PCI (Hurricane) + db62 Ingliston XBIF + dc62 Ingliston PLX9054 + dd62 Ingliston JTAG/ISP + eddc ePMC-MSDDC + fa01 ePMC-FPGA +12fc Capital Equipment Corp +12fd I2S +12fe ESD Electronic System Design GmbH +12ff Lexicon +1300 Harman International Industries Inc +1302 Computer Sciences Corp +1303 Innovative Integration +1304 Juniper Networks +1305 Netphone, Inc +1306 Duet Technologies +# Nee ComputerBoards +1307 Measurement Computing + 0001 PCI-DAS1602/16 + 000b PCI-DIO48H + 000c PCI-PDISO8 + 000d PCI-PDISO16 + 000f PCI-DAS1200 + 0010 PCI-DAS1602/12 + 0014 PCI-DIO24H + 0015 PCI-DIO24H/CTR3 + 0016 PCI-DIO48H/CTR15 + 0017 PCI-DIO96H + 0018 PCI-CTR05 + 0019 PCI-DAS1200/JR + 001a PCI-DAS1001 + 001b PCI-DAS1002 + 001c PCI-DAS1602JR/16 + 001d PCI-DAS6402/16 + 001e PCI-DAS6402/12 + 001f PCI-DAS16/M1 + 0020 PCI-DDA02/12 + 0021 PCI-DDA04/12 + 0022 PCI-DDA08/12 + 0023 PCI-DDA02/16 + 0024 PCI-DDA04/16 + 0025 PCI-DDA08/16 + 0026 PCI-DAC04/12-HS + 0027 PCI-DAC04/16-HS + 0028 PCI-DIO24 + 0029 PCI-DAS08 + 002c PCI-INT32 + 0033 PCI-DUAL-AC5 + 0034 PCI-DAS-TC + 0035 PCI-DAS64/M1/16 + 0036 PCI-DAS64/M2/16 + 0037 PCI-DAS64/M3/16 + 004c PCI-DAS1000 + 004d PCI-QUAD04 + 0052 PCI-DAS4020/12 + 0054 PCI-DIO96 + 005e PCI-DAS6025 +1308 Jato Technologies Inc. + 0001 NetCelerator Adapter + 1308 0001 NetCelerator Adapter +1309 AB Semiconductor Ltd +130a Mitsubishi Electric Microcomputer +130b Colorgraphic Communications Corp +130c Ambex Technologies, Inc +130d Accelerix Inc +130e Yamatake-Honeywell Co. Ltd +130f Advanet Inc +1310 Gespac +1311 Videoserver, Inc +1312 Acuity Imaging, Inc +1313 Yaskawa Electric Co. +1316 Teradyne Inc +1317 ADMtek + 0981 21x4x DEC-Tulip compatible 10/100 Ethernet + 0985 NC100 Network Everywhere Fast Ethernet 10/100 + 1734 100c Scenic N300 ADMtek AN983 10/100 Mbps PCI Adapter + 1985 21x4x DEC-Tulip compatible 10/100 Ethernet + 2850 HSP MicroModem 56 + 5120 ADM5120 OpenGate System-on-Chip + 8201 ADM8211 802.11b Wireless Interface + 10b8 2635 SMC2635W 802.11b (11Mbps) wireless lan pcmcia (cardbus) card + 1317 8201 SMC2635W 802.11b (11mbps) wireless lan pcmcia (cardbus) card + 8211 ADM8211 802.11b Wireless Interface + 9511 21x4x DEC-Tulip compatible 10/100 Ethernet +1318 Packet Engines Inc. + 0911 GNIC-II PCI Gigabit Ethernet [Hamachi] +1319 Fortemedia, Inc + 0801 Xwave QS3000A [FM801] + 1319 1319 FM801 PCI Audio + 0802 Xwave QS3000A [FM801 game port] + 1319 1319 FM801 PCI Joystick + 1000 FM801 PCI Audio + 1001 FM801 PCI Joystick +131a Finisar Corp. +131c Nippon Electro-Sensory Devices Corp +131d Sysmic, Inc. +131e Xinex Networks Inc +131f Siig Inc + 1000 CyberSerial (1-port) 16550 + 1001 CyberSerial (1-port) 16650 + 1002 CyberSerial (1-port) 16850 + 1010 Duet 1S(16550)+1P + 1011 Duet 1S(16650)+1P + 1012 Duet 1S(16850)+1P + 1020 CyberParallel (1-port) + 1021 CyberParallel (2-port) + 1030 CyberSerial (2-port) 16550 + 1031 CyberSerial (2-port) 16650 + 1032 CyberSerial (2-port) 16850 + 1034 Trio 2S(16550)+1P + 1035 Trio 2S(16650)+1P + 1036 Trio 2S(16850)+1P + 1050 CyberSerial (4-port) 16550 + 1051 CyberSerial (4-port) 16650 + 1052 CyberSerial (4-port) 16850 + 2000 CyberSerial (1-port) 16550 + 2001 CyberSerial (1-port) 16650 + 2002 CyberSerial (1-port) 16850 + 2010 Duet 1S(16550)+1P + 2011 Duet 1S(16650)+1P + 2012 Duet 1S(16850)+1P + 2020 CyberParallel (1-port) + 2021 CyberParallel (2-port) + 2030 CyberSerial (2-port) 16550 + 131f 2030 PCI Serial Card + 2031 CyberSerial (2-port) 16650 + 2032 CyberSerial (2-port) 16850 + 2040 Trio 1S(16550)+2P + 2041 Trio 1S(16650)+2P + 2042 Trio 1S(16850)+2P + 2050 CyberSerial (4-port) 16550 + 2051 CyberSerial (4-port) 16650 + 2052 CyberSerial (4-port) 16850 + 2060 Trio 2S(16550)+1P + 2061 Trio 2S(16650)+1P + 2062 Trio 2S(16850)+1P + 2081 CyberSerial (8-port) ST16654 +1320 Crypto AG +1321 Arcobel Graphics BV +1322 MTT Co., Ltd +1323 Dome Inc +1324 Sphere Communications +1325 Salix Technologies, Inc +1326 Seachange international +1327 Voss scientific +1328 quadrant international +1329 Productivity Enhancement +132a Microcom Inc. +132b Broadband Technologies +132c Micrel Inc +132d Integrated Silicon Solution, Inc. +1330 MMC Networks +1331 Radisys Corp. + 0030 ENP-2611 + 8200 82600 Host Bridge + 8201 82600 IDE + 8202 82600 USB + 8210 82600 PCI Bridge +1332 Micro Memory + 5415 MM-5415CN PCI Memory Module with Battery Backup + 5425 MM-5425CN PCI 64/66 Memory Module with Battery Backup + 6140 MM-6140D +1334 Redcreek Communications, Inc +1335 Videomail, Inc +1337 Third Planet Publishing +1338 BT Electronics +133a Vtel Corp +133b Softcom Microsystems +133c Holontech Corp +133d SS Technologies +133e Virtual Computer Corp +133f SCM Microsystems +1340 Atalla Corp +1341 Kyoto Microcomputer Co +1342 Promax Systems Inc +1343 Phylon Communications Inc +1344 Crucial Technology +1345 Arescom Inc +1347 Odetics +1349 Sumitomo Electric Industries, Ltd. +134a DTC Technology Corp. + 0001 Domex 536 + 0002 Domex DMX3194UP SCSI Adapter +134b ARK Research Corp. +134c Chori Joho System Co. Ltd +134d PCTel Inc + 2189 HSP56 MicroModem + 2486 2304WT V.92 MDC Modem + 7890 HSP MicroModem 56 + 134d 0001 PCT789 adapter + 7891 HSP MicroModem 56 + 134d 0001 HSP MicroModem 56 + 7892 HSP MicroModem 56 + 7893 HSP MicroModem 56 + 7894 HSP MicroModem 56 + 7895 HSP MicroModem 56 + 7896 HSP MicroModem 56 + 7897 HSP MicroModem 56 +134e CSTI +134f Algo System Co Ltd +1350 Systec Co. Ltd +1351 Sonix Inc +1353 Thales Idatys + 0002 Proserver + 0003 PCI-FUT + 0004 PCI-S0 + 0005 PCI-FUT-S0 +1354 Dwave System Inc +1355 Kratos Analytical Ltd +1356 The Logical Co +1359 Prisa Networks +135a Brain Boxes +135b Giganet Inc +135c Quatech Inc + 0010 QSC-100 + 0020 DSC-100 + 0030 DSC-200/300 + 0040 QSC-200/300 + 0050 ESC-100D + 0060 ESC-100M + 00f0 MPAC-100 Syncronous Serial Card (Zilog 85230) + 0170 QSCLP-100 + 0180 DSCLP-100 + 0190 SSCLP-100 + 01a0 QSCLP-200/300 + 01b0 DSCLP-200/300 + 01c0 SSCLP-200/300 +135d ABB Network Partner AB +135e Sealevel Systems Inc + 5101 Route 56.PCI - Multi-Protocol Serial Interface (Zilog Z16C32) + 7101 Single Port RS-232/422/485/530 + 7201 Dual Port RS-232/422/485 Interface + 7202 Dual Port RS-232 Interface + 7401 Four Port RS-232 Interface + 7402 Four Port RS-422/485 Interface + 7801 Eight Port RS-232 Interface + 7804 Eight Port RS-232/422/485 Interface + 8001 8001 Digital I/O Adapter +135f I-Data International A-S +1360 Meinberg Funkuhren + 0101 PCI32 DCF77 Radio Clock + 0102 PCI509 DCF77 Radio Clock + 0103 PCI510 DCF77 Radio Clock + 0104 PCI511 DCF77 Radio Clock + 0201 GPS167PCI GPS Receiver + 0202 GPS168PCI GPS Receiver + 0203 GPS169PCI GPS Receiver + 0204 GPS170PCI GPS Receiver + 0301 TCR510PCI IRIG Timecode Reader + 0302 TCR167PCI IRIG Timecode Reader + 0303 TCR511PCI IRIG Timecode Reader +1361 Soliton Systems K.K. +1362 Fujifacom Corporation +1363 Phoenix Technology Ltd +1364 ATM Communications Inc +1365 Hypercope GmbH +1366 Teijin Seiki Co. Ltd +1367 Hitachi Zosen Corporation +1368 Skyware Corporation +1369 Digigram +136a High Soft Tech + 0004 HST Saphir VII mini PCI + 0007 HST Saphir III E MultiLink 4 + 0008 HST Saphir III E MultiLink 8 + 000a HST Saphir III E MultiLink 2 +136b Kawasaki Steel Corporation + ff01 KL5A72002 Motion JPEG +136c Adtek System Science Co Ltd +136d Gigalabs Inc +136f Applied Magic Inc +1370 ATL Products +1371 CNet Technology Inc + 434e GigaCard Network Adapter + 1371 434e N-Way PCI-Bus Giga-Card 1000/100/10Mbps(L) +1373 Silicon Vision Inc +1374 Silicom Ltd. + 0024 Silicom Dual port Giga Ethernet BGE Bypass Server Adapter + 0025 Silicom Quad port Giga Ethernet BGE Bypass Server Adapter + 0026 Silicom Dual port Fiber Giga Ethernet 546 Bypass Server Adapter + 0027 Silicom Dual port Fiber LX Giga Ethernet 546 Bypass Server Adapter + 0029 Silicom Dual port Copper Giga Ethernet 546GB Bypass Server Adapter + 002a Silicom Dual port Fiber Giga Ethernet 546 TAP/Bypass Server Adapter + 002b Silicom Dual port Copper Fast Ethernet 546 TAP/Bypass Server Adapter (PXE2TBI) + 002c Silicom Quad port Copper Giga Ethernet 546GB Bypass Server Adapter (PXG4BPI) + 002d Silicom Quad port Fiber-SX Giga Ethernet 546GB Bypass Server Adapter (PXG4BPFI) + 002e Silicom Quad port Fiber-LX Giga Ethernet 546GB Bypass Server Adapter (PXG4BPFI-LX) + 002f Silicom Dual port Fiber-SX Giga Ethernet 546GB Low profile Bypass Server Adapter (PXG2BPFIL) + 0030 Silicom Dual port Fiber-LX Giga Ethernet 546GB Low profile Bypass Server Adapter + 0031 Silicom Quad port Copper Giga Ethernet PCI-E Bypass Server Adapter + 0032 Silicom Dual port Copper Fast Ethernet 546 TAP/Bypass Server Adapter + 0034 Silicom Dual port Copper Giga Ethernet PCI-E BGE Bypass Server Adapter + 0035 Silicom Quad port Copper Giga Ethernet PCI-E BGE Bypass Server Adapter + 0036 Silicom Dual port Fiber Giga Ethernet PCI-E BGE Bypass Server Adapter + 0037 Silicom Quad port Copper Ethernet PCI-E Intel based Bypass Server Adapter + 0038 Silicom Quad port Copper Ethernet PCI-E Intel based Bypass Server Adapter + 0039 Silicom Dual port Fiber-SX Ethernet PCI-E Intel based Bypass Server Adapter + 003a Silicom Dual port Fiber-LX Ethernet PCI-E Intel based Bypass Server Adapter +1375 Argosystems Inc +1376 LMC +1377 Electronic Equipment Production & Distribution GmbH +1378 Telemann Co. Ltd +1379 Asahi Kasei Microsystems Co Ltd +137a Mark of the Unicorn Inc + 0001 PCI-324 Audiowire Interface +137b PPT Vision +137c Iwatsu Electric Co Ltd +137d Dynachip Corporation +137e Patriot Scientific Corporation +137f Japan Satellite Systems Inc +1380 Sanritz Automation Co Ltd +1381 Brains Co. Ltd +1382 Marian - Electronic & Software + 0001 ARC88 audio recording card + 2008 Prodif 96 Pro sound system + 2048 Prodif Plus sound system + 2088 Marc 8 Midi sound system + 20c8 Marc A sound system + 4008 Marc 2 sound system + 4010 Marc 2 Pro sound system + 4048 Marc 4 MIDI sound system + 4088 Marc 4 Digi sound system + 4248 Marc X sound system + 4424 TRACE D4 Sound System +1383 Controlnet Inc +1384 Reality Simulation Systems Inc +1385 Netgear + 0013 WG311T 108 Mbps Wireless PCI Adapter + 311a GA511 Gigabit Ethernet + 4100 802.11b Wireless Adapter (MA301) + 4105 MA311 802.11b wireless adapter + 4251 WG111T 108 Mbps Wireless USB 2.0 Adapter + 4400 WAG511 802.11a/b/g Dual Band Wireless PC Card + 4600 WAG511 802.11a/b/g Dual Band Wireless PC Card + 4601 WAG511 802.11a/b/g Dual Band Wireless PC Card + 4610 WAG511 802.11a/b/g Dual Band Wireless PC Card + 4800 WG511(v1) 54 Mbps Wireless PC Card + 4900 WG311v1 54 Mbps Wireless PCI Adapter + 4a00 WAG311 802.11a/g Wireless PCI Adapter + 4b00 WG511T 108 Mbps Wireless PC Card + 4c00 WG311v2 54 Mbps Wireless PCI Adapter + 4d00 WG311T 108 Mbps Wireless PCI Adapter + 4e00 WG511v2 54 Mbps Wireless PC Card + 4f00 WG511U Double 108 Mbps Wireless PC Card + 5200 GA511 Gigabit PC Card + 620a GA620 Gigabit Ethernet + 622a GA622 + 630a GA630 Gigabit Ethernet + 6b00 WG311v3 54 Mbps Wireless PCI Adapter + 6d00 WPNT511 RangeMax 240 Mbps Wireless PC Card + 7b00 WN511B RangeMax Next 280 Mbps Wireless PC Card + 7c00 WN511T RangeMax Next 300 Mbps Wireless PC Card + 7d00 WN311B RangeMax Next 270 Mbps Wireless PCI Adapter + 7e00 WN311T RangeMax Next 300 Mbps Wireless PCI Adapter + f004 FA310TX +1386 Video Domain Technologies +1387 Systran Corp +1388 Hitachi Information Technology Co Ltd +1389 Applicom International + 0001 PCI1500PFB [Intelligent fieldbus adaptor] +138a Fusion Micromedia Corp +138b Tokimec Inc +138c Silicon Reality +138d Future Techno Designs pte Ltd +138e Basler GmbH +138f Patapsco Designs Inc +1390 Concept Development Inc +1391 Development Concepts Inc +1392 Medialight Inc +1393 Moxa Technologies Co Ltd + 1040 Smartio C104H/PCI + 1141 Industrio CP-114 + 1680 Smartio C168H/PCI + 2040 Intellio CP-204J + 2180 Intellio C218 Turbo PCI + 3200 Intellio C320 Turbo PCI +1394 Level One Communications + 0001 LXT1001 Gigabit Ethernet + 1394 0001 NetCelerator Adapter +1395 Ambicom Inc +1396 Cipher Systems Inc +1397 Cologne Chip Designs GmbH + 08b4 ISDN network Controller [HFC-4S] + 1397 b520 HFC-4S [IOB4ST] + 1397 b540 HFC-4S [Swyx 4xS0 SX2 QuadBri] + 16b8 ISDN network Controller [HFC-8S] + 2bd0 ISDN network controller [HFC-PCI] + 0675 1704 ISDN Adapter (PCI Bus, D, C) + 0675 1708 ISDN Adapter (PCI Bus, D, C, ACPI) + 1397 2bd0 ISDN Board + e4bf 1000 CI1-1-Harp +1398 Clarion co. Ltd +1399 Rios systems Co Ltd +139a Alacritech Inc + 0001 Quad Port 10/100 Server Accelerator + 0003 Single Port 10/100 Server Accelerator + 0005 Single Port Gigabit Server Accelerator +139b Mediasonic Multimedia Systems Ltd +139c Quantum 3d Inc +139d EPL limited +139e Media4 +139f Aethra s.r.l. +13a0 Crystal Group Inc +13a1 Kawasaki Heavy Industries Ltd +13a2 Ositech Communications Inc +13a3 Hifn Inc. + 0005 7751 Security Processor + 0006 6500 Public Key Processor + 0007 7811 Security Processor + 0012 7951 Security Processor + 0014 78XX Security Processor + 0016 8065 Security Processor + 0017 8165 Security Processor + 0018 8154 Security Processor + 001d 7956 Security Processor + 0020 7955 Security Processor + 0026 8155 Security Processor +13a4 Rascom Inc +13a5 Audio Digital Imaging Inc +13a6 Videonics Inc +13a7 Teles AG +13a8 Exar Corp. + 0152 XR17C/D152 Dual PCI UART + 0154 XR17C154 Quad UART + 0158 XR17C158 Octal UART +13a9 Siemens Medical Systems, Ultrasound Group +13aa Broadband Networks Inc +13ab Arcom Control Systems Ltd +13ac Motion Media Technology Ltd +13ad Nexus Inc +13ae ALD Technology Ltd +13af T.Sqware +13b0 Maxspeed Corp +13b1 Tamura corporation +13b2 Techno Chips Co. Ltd +13b3 Lanart Corporation +13b4 Wellbean Co Inc +13b5 ARM +13b6 Dlog GmbH +13b7 Logic Devices Inc +13b8 Nokia Telecommunications oy +13b9 Elecom Co Ltd +13ba Oxford Instruments +13bb Sanyo Technosound Co Ltd +13bc Bitran Corporation +13bd Sharp corporation +13be Miroku Jyoho Service Co. Ltd +13bf Sharewave Inc +13c0 Microgate Corporation + 0010 SyncLink Adapter v1 + 0020 SyncLink SCC Adapter + 0030 SyncLink Multiport Adapter + 0210 SyncLink Adapter v2 +13c1 3ware Inc + 1000 5xxx/6xxx-series PATA-RAID + 1001 7xxx/8xxx-series PATA/SATA-RAID + 13c1 1001 7xxx/8xxx-series PATA/SATA-RAID + 1002 9xxx-series SATA-RAID + 1003 9550SX SATA-RAID +13c2 Technotrend Systemtechnik GmbH + 000e Technotrend/Hauppauge DVB card rev2.3 +13c3 Janz Computer AG +13c4 Phase Metrics +13c5 Alphi Technology Corp +13c6 Condor Engineering Inc + 0520 CEI-520 A429 Card + 0620 CEI-620 A429 Card + 0820 CEI-820 A429 Card +13c7 Blue Chip Technology Ltd +13c8 Apptech Inc +13c9 Eaton Corporation +13ca Iomega Corporation +13cb Yano Electric Co Ltd +13cc Metheus Corporation +13cd Compatible Systems Corporation +13ce Cocom A/S +13cf Studio Audio & Video Ltd +13d0 Techsan Electronics Co Ltd + 2103 B2C2 FlexCopII DVB chip / Technisat SkyStar2 DVB card + 2200 B2C2 FlexCopIII DVB chip / Technisat SkyStar2 DVB card +13d1 Abocom Systems Inc + ab02 ADMtek Centaur-C rev 17 [D-Link DFE-680TX] CardBus Fast Ethernet Adapter + ab03 21x4x DEC-Tulip compatible 10/100 Ethernet + ab06 RTL8139 [FE2000VX] CardBus Fast Ethernet Attached Port Adapter + ab08 21x4x DEC-Tulip compatible 10/100 Ethernet +13d2 Shark Multimedia Inc +13d3 IMC Networks +13d4 Graphics Microsystems Inc +13d5 Media 100 Inc +13d6 K.I. Technology Co Ltd +13d7 Toshiba Engineering Corporation +13d8 Phobos corporation +13d9 Apex PC Solutions Inc +13da Intresource Systems pte Ltd +13db Janich & Klass Computertechnik GmbH +13dc Netboost Corporation +13dd Multimedia Bundle Inc +13de ABB Robotics Products AB +13df E-Tech Inc + 0001 PCI56RVP Modem + 13df 0001 PCI56RVP Modem +13e0 GVC Corporation +13e1 Silicom Multimedia Systems Inc +13e2 Dynamics Research Corporation +13e3 Nest Inc +13e4 Calculex Inc +13e5 Telesoft Design Ltd +13e6 Argosy research Inc +13e7 NAC Incorporated +13e8 Chip Express Corporation +13e9 Intraserver Technology Inc +13ea Dallas Semiconductor +13eb Hauppauge Computer Works Inc +13ec Zydacron Inc + 000a NPC-RC01 Remote control receiver +13ed Raytheion E-Systems +13ee Hayes Microcomputer Products Inc +13ef Coppercom Inc +13f0 Sundance Technology Inc / IC Plus Corp + 0200 IC Plus IP100A Integrated 10/100 Ethernet MAC + PHY + 0201 ST201 Sundance Ethernet + 1023 IC Plus IP1000 Family Gigabit Ethernet +13f1 Oce' - Technologies B.V. +13f2 Ford Microelectronics Inc +13f3 Mcdata Corporation +13f4 Troika Networks, Inc. + 1401 Zentai Fibre Channel Adapter +13f5 Kansai Electric Co. Ltd +13f6 C-Media Electronics Inc + 0011 CMI8738 + 0100 CM8338A + 13f6 ffff CMI8338/C3DX PCI Audio Device + 0101 CM8338B + 13f6 0101 CMI8338-031 PCI Audio Device + 0111 CM8738 + 1019 0970 P6STP-FL motherboard + 1043 8035 CUSI-FX motherboard + 1043 8077 CMI8738 6-channel audio controller + 1043 80e2 CMI8738 6ch-MX + 13f6 0111 CMI8738/C3DX PCI Audio Device + 1681 a000 Gamesurround MUSE XL + 0211 CM8738 +13f7 Wildfire Communications +13f8 Ad Lib Multimedia Inc +13f9 NTT Advanced Technology Corp. +13fa Pentland Systems Ltd +13fb Aydin Corp +13fc Computer Peripherals International +13fd Micro Science Inc +13fe Advantech Co. Ltd + 1240 PCI-1240 4-channel stepper motor controller card + 1600 PCI-16xx series PCI multiport serial board (function 0) +# This board has two PCI functions, appears as two PCI devices + 1601 0002 PCI-1601 2-port unisolated RS-422/485 +# This board has two PCI functions, appears as two PCI devices + 1602 0002 PCI-1602 2-port isolated RS-422/485 + 1612 0004 PCI-1612 4-port RS-232/422/485 + 16ff PCI-16xx series PCI multiport serial board (function 1: RX/TX steering CPLD) + 1601 0000 PCI-1601 2-port unisolated RS-422/485 PCI communications card + 1602 0000 PCI-1602 2-port isolated RS-422/485 + 1612 0000 PCI-1612 4-port RS-232/422/485 + 1733 PCI-1733 32-channel isolated digital input card + 1752 PCI-1752 + 1754 PCI-1754 + 1756 PCI-1756 +13ff Silicon Spice Inc +1400 Artx Inc + 1401 9432 TX +1401 CR-Systems A/S +1402 Meilhaus Electronic GmbH +1403 Ascor Inc +1404 Fundamental Software Inc +1405 Excalibur Systems Inc +1406 Oce' Printing Systems GmbH +1407 Lava Computer mfg Inc + 0100 Lava Dual Serial + 0101 Lava Quatro A + 0102 Lava Quatro B + 0110 Lava DSerial-PCI Port A + 0111 Lava DSerial-PCI Port B + 0120 Quattro-PCI A + 0121 Quattro-PCI B + 0180 Lava Octo A + 0181 Lava Octo B + 0200 Lava Port Plus + 0201 Lava Quad A + 0202 Lava Quad B + 0220 Lava Quattro PCI Ports A/B + 0221 Lava Quattro PCI Ports C/D + 0500 Lava Single Serial + 0600 Lava Port 650 + 8000 Lava Parallel + 8001 Dual parallel port controller A + 8002 Lava Dual Parallel port A + 8003 Lava Dual Parallel port B + 8800 BOCA Research IOPPAR +1408 Aloka Co. Ltd +1409 Timedia Technology Co Ltd + 7168 PCI2S550 (Dual 16550 UART) +140a DSP Research Inc +140b Ramix Inc +140c Elmic Systems Inc +140d Matsushita Electric Works Ltd +140e Goepel Electronic GmbH +140f Salient Systems Corp +1410 Midas lab Inc +1411 Ikos Systems Inc +# Nee IC Ensemble Inc. +1412 VIA Technologies Inc. + 1712 ICE1712 [Envy24] PCI Multi-Channel I/O Controller + 1412 1712 Hoontech ST Audio DSP 24 + 1412 d630 M-Audio Delta 1010 + 1412 d631 M-Audio Delta DiO + 1412 d632 M-Audio Delta 66 + 1412 d633 M-Audio Delta 44 + 1412 d634 M-Audio Delta Audiophile + 1412 d635 M-Audio Delta TDIF + 1412 d637 M-Audio Delta RBUS + 1412 d638 M-Audio Delta 410 + 1412 d63b M-Audio Delta 1010LT + 1412 d63c Digigram VX442 + 1416 1712 Hoontech ST Audio DSP 24 Media 7.1 + 153b 1115 EWS88 MT + 153b 1125 EWS88 MT (Master) + 153b 112b EWS88 D + 153b 112c EWS88 D (Master) + 153b 1130 EWX 24/96 + 153b 1138 DMX 6fire 24/96 + 153b 1151 PHASE88 + 16ce 1040 Edirol DA-2496 + 1724 VT1720/24 [Envy24PT/HT] PCI Multi-Channel Audio Controller + 1412 1724 Albatron PX865PE 7.1 + 1412 3630 M-Audio Revolution 7.1 + 1412 3631 M-Audio Revolution 5.1 + 153b 1145 Aureon 7.1 Space + 153b 1147 Aureon 5.1 Sky + 153b 1153 Aureon 7.1 Universe + 270f f641 ZNF3-150 + 270f f645 ZNF3-250 +1413 Addonics +1414 Microsoft Corporation +1415 Oxford Semiconductor Ltd + 8403 VScom 011H-EP1 1 port parallel adaptor + 9500 OX16PCI954 (Quad 16950 UART) function 0 (Disabled) + 9501 OX16PCI954 (Quad 16950 UART) function 0 (Uart) + 12c4 0201 Titan/cPCI (2 port) + 12c4 0202 Titan/cPCI (4 port) + 12c4 0203 Titan/cPCI (8 port) + 12c4 0210 Titan/104-Plus (8 port, p1-4) + 131f 2050 CyberPro (4-port) +# Model IO1085, Part No: JJ-P46012 + 131f 2051 CyberSerial 4S Plus + 15ed 2000 MCCR Serial p0-3 of 8 + 15ed 2001 MCCR Serial p0-3 of 16 + 950a EXSYS EX-41092 Dual 16950 Serial adapter + 950b OXCB950 Cardbus 16950 UART + 9510 OX16PCI954 (Quad 16950 UART) function 1 (Disabled) + 12c4 0200 Titan/cPCI (Unused) + 9511 OX16PCI954 (Quad 16950 UART) function 1 (8bit bus) + 12c4 0211 Titan/104-Plus (8 port, p5-8) + 15ed 2000 MCCR Serial p4-7 of 8 + 15ed 2001 MCCR Serial p4-15 of 16 + 9512 OX16PCI954 (Quad 16950 UART) function 1 (32bit bus) + 9513 OX16PCI954 (Quad 16950 UART) function 1 (parallel port) + 9521 OX16PCI952 (Dual 16950 UART) + 9523 OX16PCI952 Integrated Parallel Port +1416 Multiwave Innovation pte Ltd +1417 Convergenet Technologies Inc +1418 Kyushu electronics systems Inc +1419 Excel Switching Corp +141a Apache Micro Peripherals Inc +141b Zoom Telephonics Inc +141d Digitan Systems Inc +141e Fanuc Ltd +141f Visiontech Ltd +1420 Psion Dacom plc + 8002 Gold Card NetGlobal 56k+10/100Mb CardBus (Ethernet part) + 8003 Gold Card NetGlobal 56k+10/100Mb CardBus (Modem part) +1421 Ads Technologies Inc +1422 Ygrec Systems Co Ltd +1423 Custom Technology Corp. +1424 Videoserver Connections +1425 Chelsio Communications Inc + 000b T210 Protocol Engine +1426 Storage Technology Corp. +1427 Better On-Line Solutions +1428 Edec Co Ltd +1429 Unex Technology Corp. +142a Kingmax Technology Inc +142b Radiolan +142c Minton Optic Industry Co Ltd +142d Pix stream Inc +142e Vitec Multimedia + 4020 VM2-2 [Video Maker 2] MPEG1/2 Encoder + 4337 VM2-2-C7 [Video Maker 2 rev. C7] MPEG1/2 Encoder +142f Radicom Research Inc +1430 ITT Aerospace/Communications Division +1431 Gilat Satellite Networks +1432 Edimax Computer Co. + 9130 RTL81xx Fast Ethernet +1433 Eltec Elektronik GmbH +# Nee Real Time Devices US Inc. +1435 RTD Embedded Technologies, Inc. + 4520 PCI4520 + 6020 SPM6020 + 6030 SPM6030 + 6420 SPM186420 + 6430 SPM176430 + 7520 DM7520 + 7820 DM7820 +1436 CIS Technology Inc +1437 Nissin Inc Co +1438 Atmel-dream +1439 Outsource Engineering & Mfg. Inc +143a Stargate Solutions Inc +143b Canon Research Center, America +143c Amlogic Inc +143d Tamarack Microelectronics Inc +143e Jones Futurex Inc +143f Lightwell Co Ltd - Zax Division +1440 ALGOL Corp. +1441 AGIE Ltd +1442 Phoenix Contact GmbH & Co. +1443 Unibrain S.A. +1444 TRW +1445 Logical DO Ltd +1446 Graphin Co Ltd +1447 AIM GmBH +1448 Alesis Studio Electronics +1449 TUT Systems Inc +144a Adlink Technology + 7296 PCI-7296 + 7432 PCI-7432 + 7433 PCI-7433 + 7434 PCI-7434 + 7841 PCI-7841 + 8133 PCI-8133 + 8164 PCI-8164 + 8554 PCI-8554 + 9111 PCI-9111 + 9113 PCI-9113 + 9114 PCI-9114 +144b Loronix Information Systems Inc +144c Catalina Research Inc +144d Samsung Electronics Co Ltd + c00c P35 laptop +144e OLITEC +144f Askey Computer Corp. +1450 Octave Communications Ind. +1451 SP3D Chip Design GmBH +1453 MYCOM Inc +1454 Altiga Networks +1455 Logic Plus Plus Inc +1456 Advanced Hardware Architectures +1457 Nuera Communications Inc +1458 Giga-byte Technology + 0c11 K8NS Pro Mainboard + e911 GN-WIAG02 +1459 DOOIN Electronics +145a Escalate Networks Inc +145b PRAIM SRL +145c Cryptek +145d Gallant Computer Inc +145e Aashima Technology B.V. +145f Baldor Electric Company + 0001 NextMove PCI +1460 DYNARC INC +1461 Avermedia Technologies Inc + f436 AVerTV Hybrid+FM +1462 Micro-Star International Co., Ltd. + 5501 nVidia NV15DDR [GeForce2 Ti] + 6819 Broadcom Corporation BCM4306 802.11b/g Wireless LAN Controller [MSI CB54G] + 6825 PCI Card wireless 11g [PC54G] + 6834 RaLink RT2500 802.11g [PC54G2] + 7125 K8N motherboard + 8725 NVIDIA NV25 [GeForce4 Ti 4600] VGA Adapter + 9000 NVIDIA NV28 [GeForce4 Ti 4800] VGA Adapter + 9110 GeFORCE FX5200 + 9119 NVIDIA NV31 [GeForce FX 5600XT] VGA Adapter + 9123 NVIDIA NV31 [GeForce FX 5600] FX5600-VTDR128 [MS-8912] + 9510 Radeon 9600XT + 9511 Radeon 9600XT + 9591 nVidia Corporation NV36 [GeForce FX 5700LE] +1463 Fast Corporation +1464 Interactive Circuits & Systems Ltd +1465 GN NETTEST Telecom DIV. +1466 Designpro Inc. +1467 DIGICOM SPA +1468 AMBIT Microsystem Corp. +1469 Cleveland Motion Controls +146a IFR +146b Parascan Technologies Ltd +146c Ruby Tech Corp. + 1430 FE-1430TX Fast Ethernet PCI Adapter +146d Tachyon, INC. +146e Williams Electronics Games, Inc. +146f Multi Dimensional Consulting Inc +1470 Bay Networks +1471 Integrated Telecom Express Inc +1472 DAIKIN Industries, Ltd +1473 ZAPEX Technologies Inc +1474 Doug Carson & Associates +1475 PICAZO Communications +1476 MORTARA Instrument Inc +1477 Net Insight +1478 DIATREND Corporation +1479 TORAY Industries Inc +147a FORMOSA Industrial Computing +147b ABIT Computer Corp. +147c AWARE, Inc. +147d Interworks Computer Products +147e Matsushita Graphic Communication Systems, Inc. +147f NIHON UNISYS, Ltd. +1480 SCII Telecom +1481 BIOPAC Systems Inc +1482 ISYTEC - Integrierte Systemtechnik GmBH +1483 LABWAY Corporation +1484 Logic Corporation +1485 ERMA - Electronic GmBH +1486 L3 Communications Telemetry & Instrumentation +1487 MARQUETTE Medical Systems +1488 KONTRON Electronik GmBH +1489 KYE Systems Corporation +148a OPTO +148b INNOMEDIALOGIC Inc. +148c C.P. Technology Co. Ltd +148d DIGICOM Systems, Inc. + 1003 HCF 56k Data/Fax Modem +148e OSI Plus Corporation +148f Plant Equipment, Inc. +1490 Stone Microsystems PTY Ltd. +1491 ZEAL Corporation +1492 Time Logic Corporation +1493 MAKER Communications +1494 WINTOP Technology, Inc. +1495 TOKAI Communications Industry Co. Ltd +1496 JOYTECH Computer Co., Ltd. +1497 SMA Regelsysteme GmBH + 1497 SMA Technologie AG +1498 TEWS Datentechnik GmBH + 0330 TPMC816 2 Channel CAN bus controller. + 0385 TPMC901 Extended CAN bus with 2/4/6 CAN controller + 21cc TCP460 CompactPCI 16 Channel Serial Interface RS232/RS422 + 21cd TCP461 CompactPCI 8 Channel Serial Interface RS232/RS422 + 30c8 TPCI200 +1499 EMTEC CO., Ltd +149a ANDOR Technology Ltd +149b SEIKO Instruments Inc +149c OVISLINK Corp. +149d NEWTEK Inc + 0001 Video Toaster for PC +149e Mapletree Networks Inc. +149f LECTRON Co Ltd +14a0 SOFTING GmBH +14a1 Systembase Co Ltd +14a2 Millennium Engineering Inc +14a3 Maverick Networks +14a4 GVC/BCM Advanced Research +14a5 XIONICS Document Technologies Inc +14a6 INOVA Computers GmBH & Co KG +14a7 MYTHOS Systems Inc +14a8 FEATRON Technologies Corporation +14a9 HIVERTEC Inc +14aa Advanced MOS Technology Inc +14ab Mentor Graphics Corp. +14ac Novaweb Technologies Inc +14ad Time Space Radio AB +14ae CTI, Inc +14af Guillemot Corporation + 7102 3D Prophet II MX +14b0 BST Communication Technology Ltd +14b1 Nextcom K.K. +14b2 ENNOVATE Networks Inc +14b3 XPEED Inc + 0000 DSL NIC +14b4 PHILIPS Business Electronics B.V. +14b5 Creamware GmBH + 0200 Scope + 0300 Pulsar + 0400 PulsarSRB + 0600 Pulsar2 + 0800 DSP-Board + 0900 DSP-Board + 0a00 DSP-Board + 0b00 DSP-Board +14b6 Quantum Data Corp. +14b7 PROXIM Inc + 0001 Symphony 4110 +14b8 Techsoft Technology Co Ltd +14b9 AIRONET Wireless Communications + 0001 PC4800 + 0340 PC4800 + 0350 PC4800 + 4500 PC4500 + 4800 Cisco Aironet 340 802.11b Wireless LAN Adapter/Aironet PC4800 + a504 Cisco Aironet Wireless 802.11b + a505 Cisco Aironet CB20a 802.11a Wireless LAN Adapter + a506 Cisco Aironet Mini PCI b/g +14ba INTERNIX Inc. +14bb SEMTECH Corporation +14bc Globespan Semiconductor Inc. + d002 Pulsar [PCI ADSL Card] + d00f Pulsar [PCI ADSL Card] +14bd CARDIO Control N.V. +14be L3 Communications +14bf SPIDER Communications Inc. +14c0 COMPAL Electronics Inc +14c1 MYRICOM Inc. + 0008 Myri-10G Dual-Protocol NIC (10G-PCIE-8A) + 8043 Myrinet 2000 Scalable Cluster Interconnect + 103c 1240 Myrinet M2L-PCI64/2-3.0 LANai 7.4 (HP OEM) +14c2 DTK Computer +14c3 MEDIATEK Corp. +14c4 IWASAKI Information Systems Co Ltd +14c5 Automation Products AB +14c6 Data Race Inc +14c7 Modular Technology Holdings Ltd +14c8 Turbocomm Tech. Inc. +14c9 ODIN Telesystems Inc +14ca PE Logic Corp. +14cb Billionton Systems Inc +14cc NAKAYO Telecommunications Inc +14cd Universal Scientific Ind. +14ce Whistle Communications +14cf TEK Microsystems Inc. +14d0 Ericsson Axe R & D +14d1 Computer Hi-Tech Co Ltd +14d2 Titan Electronics Inc + 8001 VScom 010L 1 port parallel adaptor + 8002 VScom 020L 2 port parallel adaptor + 8010 VScom 100L 1 port serial adaptor + 8011 VScom 110L 1 port serial and 1 port parallel adaptor + 8020 VScom 200L 1 port serial adaptor + 8021 VScom 210L 2 port serial and 1 port parallel adaptor + 8040 VScom 400L 4 port serial adaptor + 8080 VScom 800L 8 port serial adaptor + a000 VScom 010H 1 port parallel adaptor + a001 VScom 100H 1 port serial adaptor + a003 VScom 400H 4 port serial adaptor + a004 VScom 400HF1 4 port serial adaptor + a005 VScom 200H 2 port serial adaptor + e001 VScom 010HV2 1 port parallel adaptor + e010 VScom 100HV2 1 port serial adaptor + e020 VScom 200HV2 2 port serial adaptor +14d3 CIRTECH (UK) Ltd +14d4 Panacom Technology Corp +14d5 Nitsuko Corporation +14d6 Accusys Inc +14d7 Hirakawa Hewtech Corp +14d8 HOPF Elektronik GmBH +# Formerly SiPackets, Inc., formerly API NetWorks, Inc., formerly Alpha Processor, Inc. +14d9 Alliance Semiconductor Corporation + 0010 AP1011/SP1011 HyperTransport-PCI Bridge [Sturgeon] + 9000 AS90L10204/10208 HyperTransport to PCI-X Bridge +14da National Aerospace Laboratories +14db AFAVLAB Technology Inc + 2120 TK9902 + 2182 AFAVLAB Technology Inc. 8-port serial card +14dc Amplicon Liveline Ltd + 0000 PCI230 + 0001 PCI242 + 0002 PCI244 + 0003 PCI247 + 0004 PCI248 + 0005 PCI249 + 0006 PCI260 + 0007 PCI224 + 0008 PCI234 + 0009 PCI236 + 000a PCI272 + 000b PCI215 +14dd Boulder Design Labs Inc +14de Applied Integration Corporation +14df ASIC Communications Corp +14e1 INVERTEX +14e2 INFOLIBRIA +14e3 AMTELCO +14e4 Broadcom Corporation + 0800 Sentry5 Chipcommon I/O Controller + 0804 Sentry5 PCI Bridge + 0805 Sentry5 MIPS32 CPU + 0806 Sentry5 Ethernet Controller + 080b Sentry5 Crypto Accelerator + 080f Sentry5 DDR/SDR RAM Controller + 0811 Sentry5 External Interface Core + 0816 BCM3302 Sentry5 MIPS32 CPU + 1600 NetXtreme BCM5752 Gigabit Ethernet PCI Express + 107b 5048 E4500 Onboard + 1601 NetXtreme BCM5752M Gigabit Ethernet PCI Express + 1644 NetXtreme BCM5700 Gigabit Ethernet + 1014 0277 Broadcom Vigil B5700 1000Base-T + 1028 00d1 Broadcom BCM5700 + 1028 0106 Broadcom BCM5700 + 1028 0109 Broadcom BCM5700 1000Base-T + 1028 010a Broadcom BCM5700 1000BaseTX + 10b7 1000 3C996-T 1000Base-T + 10b7 1001 3C996B-T 1000Base-T + 10b7 1002 3C996C-T 1000Base-T + 10b7 1003 3C997-T 1000Base-T Dual Port + 10b7 1004 3C996-SX 1000Base-SX + 10b7 1005 3C997-SX 1000Base-SX Dual Port + 10b7 1008 3C942 Gigabit LOM (31X31) + 14e4 0002 NetXtreme 1000Base-SX + 14e4 0003 NetXtreme 1000Base-SX + 14e4 0004 NetXtreme 1000Base-T + 14e4 1028 NetXtreme 1000BaseTX + 14e4 1644 BCM5700 1000Base-T + 1645 NetXtreme BCM5701 Gigabit Ethernet + 0e11 007c NC7770 Gigabit Server Adapter (PCI-X, 10/100/1000-T) + 0e11 007d NC6770 Gigabit Server Adapter (PCI-X, 1000-SX) + 0e11 0085 NC7780 Gigabit Server Adapter (embedded, WOL) + 0e11 0099 NC7780 Gigabit Server Adapter (embedded, WOL) + 0e11 009a NC7770 Gigabit Server Adapter (PCI-X, 10/100/1000-T) + 0e11 00c1 NC6770 Gigabit Server Adapter (PCI-X, 1000-SX) + 1028 0121 Broadcom BCM5701 1000Base-T + 103c 128a 1000Base-T (PCI) [A7061A] + 103c 128b 1000Base-SX (PCI) [A7073A] + 103c 12a4 Core Lan 1000Base-T + 103c 12c1 IOX Core Lan 1000Base-T [A7109AX] + 103c 1300 Core LAN/SCSI Combo [A6794A] + 10a9 8010 IO9/IO10 Gigabit Ethernet (Copper) + 10a9 8011 Gigabit Ethernet (Copper) + 10a9 8012 Gigabit Ethernet (Fiber) + 10b7 1004 3C996-SX 1000Base-SX + 10b7 1006 3C996B-T 1000Base-T + 10b7 1007 3C1000-T 1000Base-T + 10b7 1008 3C940-BR01 1000Base-T + 14e4 0001 BCM5701 1000Base-T + 14e4 0005 BCM5701 1000Base-T + 14e4 0006 BCM5701 1000Base-T + 14e4 0007 BCM5701 1000Base-SX + 14e4 0008 BCM5701 1000Base-T + 14e4 8008 BCM5701 1000Base-T + 1646 NetXtreme BCM5702 Gigabit Ethernet + 0e11 00bb NC7760 1000BaseTX + 1028 0126 Broadcom BCM5702 1000BaseTX + 14e4 8009 BCM5702 1000BaseTX + 1647 NetXtreme BCM5703 Gigabit Ethernet + 0e11 0099 NC7780 1000BaseTX + 0e11 009a NC7770 1000BaseTX + 10a9 8010 SGI IO9 Gigabit Ethernet (Copper) + 14e4 0009 BCM5703 1000BaseTX + 14e4 000a BCM5703 1000BaseSX + 14e4 000b BCM5703 1000BaseTX + 14e4 8009 BCM5703 1000BaseTX + 14e4 800a BCM5703 1000BaseTX + 1648 NetXtreme BCM5704 Gigabit Ethernet + 0e11 00cf NC7772 Gigabit Server Adapter (PCI-X, 10,100,1000-T) + 0e11 00d0 NC7782 Gigabit Server Adapter (PCI-X, 10,100,1000-T) + 0e11 00d1 NC7783 Gigabit Server Adapter (PCI-X, 10,100,1000-T) + 10a9 8013 Dual Port Gigabit Ethernet (PCI-X,Copper) + 10a9 8018 Dual Port Gigabit Ethernet (A330) + 10a9 801a Dual Port Gigabit Ethernet (IA-blade) + 10a9 801b Quad Port Gigabit Ethernet (PCI-E,Copper) + 10b7 2000 3C998-T Dual Port 10/100/1000 PCI-X + 10b7 3000 3C999-T Quad Port 10/100/1000 PCI-X + 1166 1648 NetXtreme CIOB-E 1000Base-T + 1734 100b Primergy RX300 + 164a NetXtreme II BCM5706 Gigabit Ethernet + 103c 3070 NC380T PCI Express Dual Port Multifunction Gigabit Server Adapter + 103c 3101 NC370T MultifuNCtion Gigabit Server Adapter + 164c NetXtreme II BCM5708 Gigabit Ethernet + 103c 7037 NC373T PCI Express Multifunction Gigabit Server Adapter + 103c 7038 NC373i Integrated Multifunction Gigabit Server Adapter + 164d NetXtreme BCM5702FE Gigabit Ethernet + 1653 NetXtreme BCM5705 Gigabit Ethernet + 0e11 00e3 NC7761 Gigabit Server Adapter + 1654 NetXtreme BCM5705_2 Gigabit Ethernet + 0e11 00e3 NC7761 Gigabit Server Adapter + 103c 3100 NC1020 ProLiant Gigabit Server Adapter 32 PCI + 103c 3226 NC150T 4-port Gigabit Combo Switch & Adapter + 1659 NetXtreme BCM5721 Gigabit Ethernet PCI Express + 1014 02c6 eServer xSeries server mainboard + 103c 7031 NC320T PCIe Gigabit Server Adapter + 103c 7032 NC320i PCIe Gigabit Server Adapter + 1734 1061 Primergy RX300 S2 + 165d NetXtreme BCM5705M Gigabit Ethernet + 1028 865d Latitude D400 + 165e NetXtreme BCM5705M_2 Gigabit Ethernet + 103c 088c NC8000 laptop + 103c 0890 NC6000 laptop + 103c 099c NX6110/NC6120 + 1668 NetXtreme BCM5714 Gigabit Ethernet + 103c 7039 NC324i PCIe Dual Port Gigabit Server Adapter + 1669 NetXtreme 5714S Gigabit Ethernet + 166a NetXtreme BCM5780 Gigabit Ethernet + 166b NetXtreme BCM5780S Gigabit Ethernet + 166e 570x 10/100 Integrated Controller + 1672 NetXtreme BCM5754M Gigabit Ethernet PCI Express + 1673 NetXtreme BCM5755M Gigabit Ethernet PCI Express + 1677 NetXtreme BCM5751 Gigabit Ethernet PCI Express + 1028 0179 Optiplex GX280 + 1028 0182 Latitude D610 + 1028 0187 Precision M70 + 1028 01ad Optiplex GX620 + 103c 3006 DC7100 SFF(DX878AV) + 1734 105d Scenic W620 + 1678 NetXtreme BCM5715 Gigabit Ethernet + 1679 NetXtreme BCM5715S Gigabit Ethernet + 103c 1707 NC326m PCIe Dual Port Adapter + 103c 170c NC325m PCIe Quad Port Adapter + 103c 703c NC326i PCIe Dual Port Gigabit Server Adapter + 167a NetXtreme BCM5754 Gigabit Ethernet PCI Express + 167b NetXtreme BCM5755 Gigabit Ethernet PCI Express + 167d NetXtreme BCM5751M Gigabit Ethernet PCI Express + 17aa 2081 Thinkpad R60e model 0657 + 167e NetXtreme BCM5751F Fast Ethernet PCI Express + 1693 NetLink BCM5787M Gigabit Ethernet PCI Express + 1696 NetXtreme BCM5782 Gigabit Ethernet + 103c 12bc d530 CMT (DG746A) + 14e4 000d NetXtreme BCM5782 1000Base-T + 169a NetLink BCM5786 Gigabit Ethernet PCI Express + 169b NetLink BCM5787 Gigabit Ethernet PCI Express + 169c NetXtreme BCM5788 Gigabit Ethernet + 103c 308b MX6125 + 169d NetLink BCM5789 Gigabit Ethernet PCI Express + 16a6 NetXtreme BCM5702X Gigabit Ethernet + 0e11 00bb NC7760 Gigabit Server Adapter (PCI-X, 10/100/1000-T) + 1028 0126 BCM5702 1000Base-T + 14e4 000c BCM5702 1000Base-T + 14e4 8009 BCM5702 1000Base-T + 16a7 NetXtreme BCM5703X Gigabit Ethernet + 0e11 00ca NC7771 Gigabit Server Adapter (PCI-X, 10,100,1000-T) + 0e11 00cb NC7781 Gigabit Server Adapter (PCI-X, 10,100,1000-T) + 14e4 0009 NetXtreme BCM5703 1000Base-T + 14e4 000a NetXtreme BCM5703 1000Base-SX + 14e4 000b NetXtreme BCM5703 1000Base-T + 14e4 800a NetXtreme BCM5703 1000Base-T + 16a8 NetXtreme BCM5704S Gigabit Ethernet + 10a9 8014 Dual Port Gigabit Ethernet (PCI-X,Fiber) + 10a9 801c Quad Port Gigabit Ethernet (PCI-E,Fiber) + 10b7 2001 3C998-SX Dual Port 1000-SX PCI-X + 16aa NetXtreme II BCM5706S Gigabit Ethernet + 103c 3102 NC370F MultifuNCtion Gigabit Server Adapter + 16ac NetXtreme II BCM5708S Gigabit Ethernet + 103c 1706 NC373m Multifunction Gigabit Server Adapter + 103c 703b NC373i Integrated Multifunction Gigabit Server Adapter + 103c 703d NC373F PCI Express Multifunction Gigabit Server Adapter + 16c6 NetXtreme BCM5702A3 Gigabit Ethernet + 10b7 1100 3C1000B-T 10/100/1000 PCI + 14e4 000c BCM5702 1000Base-T + 14e4 8009 BCM5702 1000Base-T + 16c7 NetXtreme BCM5703 Gigabit Ethernet + 0e11 00ca NC7771 Gigabit Server Adapter (PCI-X, 10,100,1000-T) + 0e11 00cb NC7781 Gigabit Server Adapter (PCI-X, 10,100,1000-T) + 103c 12c3 Combo FC/GigE-SX [A9782A] + 103c 12ca Combo FC/GigE-T [A9784A] + 14e4 0009 NetXtreme BCM5703 1000Base-T + 14e4 000a NetXtreme BCM5703 1000Base-SX + 16dd NetLink BCM5781 Gigabit Ethernet PCI Express + 16f7 NetXtreme BCM5753 Gigabit Ethernet PCI Express + 16fd NetXtreme BCM5753M Gigabit Ethernet PCI Express + 16fe NetXtreme BCM5753F Fast Ethernet PCI Express + 170c BCM4401-B0 100Base-TX + 1028 0188 Inspiron 6000 laptop + 1028 0196 Inspiron 5160 + 103c 099c NX6110/NC6120 + 170d NetXtreme BCM5901 100Base-TX + 1014 0545 ThinkPad R40e (2684-HVG) builtin ethernet controller + 170e NetXtreme BCM5901 100Base-TX + 3352 BCM3352 + 3360 BCM3360 + 4210 BCM4210 iLine10 HomePNA 2.0 + 4211 BCM4211 iLine10 HomePNA 2.0 + V.90 56k modem + 4212 BCM4212 v.90 56k modem + 4301 BCM4303 802.11b Wireless LAN Controller + 1028 0407 TrueMobile 1180 Onboard WLAN + 1043 0120 WL-103b Wireless LAN PC Card + 4305 BCM4307 V.90 56k Modem + 4306 BCM4307 Ethernet Controller + 4307 BCM4307 802.11b Wireless LAN Controller + 4310 BCM4310 Chipcommon I/OController + 4311 Dell Wireless 1390 WLAN Mini-PCI Card + 4312 BCM4310 UART + 4313 BCM4310 Ethernet Controller + 4315 BCM4310 USB Controller + 4318 BCM4318 [AirForce One 54g] 802.11g Wireless LAN Controller + 103c 1356 MX6125 + 1043 120f A6U notebook embedded card + 1468 0311 Aspire 3022WLMi, 5024WLMi + 1468 0312 TravelMate 2410 + 14e4 0449 Gateway 7510GX + 14e4 4318 WPC54G version 3 [Wireless-G Notebook Adapter] 802.11g Wireless Lan Controller + 16ec 0119 U.S.Robotics Wireless MAXg PC Card + 1737 0048 WPC54G-EU version 3 [Wireless-G Notebook Adapter] + 4319 BCM4311 [AirForce 54g] 802.11a/b/g PCI Express Transceiver + 4320 BCM4306 802.11b/g Wireless LAN Controller + 1028 0001 TrueMobile 1300 WLAN Mini-PCI Card + 1028 0003 Wireless 1350 WLAN Mini-PCI Card + 103c 12f4 NX9500 Built-in Wireless + 103c 12fa Presario R3000 802.11b/g + 1043 100f WL-100G + 1057 7025 WN825G + 106b 004e AirPort Extreme + 1154 0330 Buffalo WLI2-PCI-G54S High Speed Mode Wireless Desktop Adapter + 144f 7050 eMachines M6805 802.11g Built-in Wireless + 14e4 4320 Linksys WMP54G PCI + 1737 4320 WPC54G + 1799 7001 Belkin F5D7001 High-Speed Mode Wireless G Network Card + 1799 7010 Belkin F5D7010 54g Wireless Network card + 1799 7011 F5D7011 54g+ Wireless Network card + 185f 1220 TravelMate 290E WLAN Mini-PCI Card + 4321 BCM4306 802.11a Wireless LAN Controller + 4322 BCM4306 UART + 4324 BCM4309 802.11a/b/g + 1028 0001 Truemobile 1400 + 1028 0003 Truemobile 1450 MiniPCI + 4325 BCM43xG 802.11b/g + 1414 0003 Wireless Notebook Adapter MN-720 + 1414 0004 Wireless PCI Adapter MN-730 + 4326 BCM4307 Chipcommon I/O Controller? + 4329 BCM43XG + 4401 BCM4401 100Base-T + 103c 08b0 tc1100 tablet + 1043 80a8 A7V8X motherboard + 4402 BCM4402 Integrated 10/100BaseT + 4403 BCM4402 V.90 56k Modem + 4410 BCM4413 iLine32 HomePNA 2.0 + 4411 BCM4413 V.90 56k modem + 4412 BCM4412 10/100BaseT + 4430 BCM44xx CardBus iLine32 HomePNA 2.0 + 4432 BCM4432 CardBus 10/100BaseT + 4610 BCM4610 Sentry5 PCI to SB Bridge + 4611 BCM4610 Sentry5 iLine32 HomePNA 1.0 + 4612 BCM4610 Sentry5 V.90 56k Modem + 4613 BCM4610 Sentry5 Ethernet Controller + 4614 BCM4610 Sentry5 External Interface + 4615 BCM4610 Sentry5 USB Controller + 4704 BCM4704 PCI to SB Bridge + 4705 BCM4704 Sentry5 802.11b Wireless LAN Controller + 4706 BCM4704 Sentry5 Ethernet Controller + 4707 BCM4704 Sentry5 USB Controller + 4708 BCM4704 Crypto Accelerator + 4710 BCM4710 Sentry5 PCI to SB Bridge + 4711 BCM47xx Sentry5 iLine32 HomePNA 2.0 + 4712 BCM47xx V.92 56k modem + 4713 Sentry5 Ethernet Controller + 4714 BCM47xx Sentry5 External Interface + 4715 Sentry5 USB Controller + 4716 BCM47xx Sentry5 USB Host Controller + 4717 BCM47xx Sentry5 USB Device Controller + 4718 Sentry5 Crypto Accelerator + 4719 BCM47xx/53xx RoboSwitch Core + 4720 BCM4712 MIPS CPU + 5365 BCM5365P Sentry5 Host Bridge + 5600 BCM5600 StrataSwitch 24+2 Ethernet Switch Controller + 5605 BCM5605 StrataSwitch 24+2 Ethernet Switch Controller + 5615 BCM5615 StrataSwitch 24+2 Ethernet Switch Controller + 5625 BCM5625 StrataSwitch 24+2 Ethernet Switch Controller + 5645 BCM5645 StrataSwitch 24+2 Ethernet Switch Controller + 5670 BCM5670 8-Port 10GE Ethernet Switch Fabric + 5680 BCM5680 G-Switch 8 Port Gigabit Ethernet Switch Controller + 5690 BCM5690 12-port Multi-Layer Gigabit Ethernet Switch + 5691 BCM5691 GE/10GE 8+2 Gigabit Ethernet Switch Controller + 5692 BCM5692 12-port Multi-Layer Gigabit Ethernet Switch + 5820 BCM5820 Crypto Accelerator + 5821 BCM5821 Crypto Accelerator + 5822 BCM5822 Crypto Accelerator + 5823 BCM5823 Crypto Accelerator + 5824 BCM5824 Crypto Accelerator + 5840 BCM5840 Crypto Accelerator + 5841 BCM5841 Crypto Accelerator + 5850 BCM5850 Crypto Accelerator +14e5 Pixelfusion Ltd +14e6 SHINING Technology Inc +14e7 3CX +14e8 RAYCER Inc +14e9 GARNETS System CO Ltd +14ea Planex Communications, Inc + ab06 FNW-3603-TX CardBus Fast Ethernet + ab07 RTL81xx RealTek Ethernet + ab08 FNW-3602-TX CardBus Fast Ethernet +14eb SEIKO EPSON Corp +14ec ACQIRIS +14ed DATAKINETICS Ltd +14ee MASPRO KENKOH Corp +14ef CARRY Computer ENG. CO Ltd +14f0 CANON RESEACH CENTRE FRANCE +14f1 Conexant + 1002 HCF 56k Modem + 1003 HCF 56k Modem + 1004 HCF 56k Modem + 1005 HCF 56k Modem + 1006 HCF 56k Modem + 1022 HCF 56k Modem + 1023 HCF 56k Modem + 1024 HCF 56k Modem + 1025 HCF 56k Modem + 1026 HCF 56k Modem + 1032 HCF 56k Modem + 1033 HCF 56k Data/Fax Modem + 1033 8077 NEC + 122d 4027 Dell Zeus - MDP3880-W(B) Data Fax Modem + 122d 4030 Dell Mercury - MDP3880-U(B) Data Fax Modem + 122d 4034 Dell Thor - MDP3880-W(U) Data Fax Modem + 13e0 020d Dell Copper + 13e0 020e Dell Silver + 13e0 0261 IBM + 13e0 0290 Compaq Goldwing + 13e0 02a0 IBM + 13e0 02b0 IBM + 13e0 02c0 Compaq Scooter + 13e0 02d0 IBM + 144f 1500 IBM P85-DF (1) + 144f 1501 IBM P85-DF (2) + 144f 150a IBM P85-DF (3) + 144f 150b IBM P85-DF Low Profile (1) + 144f 1510 IBM P85-DF Low Profile (2) + 1034 HCF 56k Data/Fax/Voice Modem + 1035 HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem + 10cf 1098 Fujitsu P85-DFSV + 1036 HCF 56k Data/Fax/Voice/Spkp Modem + 104d 8067 HCF 56k Modem + 122d 4029 MDP3880SP-W + 122d 4031 MDP3880SP-U + 13e0 0209 Dell Titanium + 13e0 020a Dell Graphite + 13e0 0260 Gateway Red Owl + 13e0 0270 Gateway White Horse + 1052 HCF 56k Data/Fax Modem (Worldwide) + 1053 HCF 56k Data/Fax Modem (Worldwide) + 1054 HCF 56k Data/Fax/Voice Modem (Worldwide) + 1055 HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem (Worldwide) + 1056 HCF 56k Data/Fax/Voice/Spkp Modem (Worldwide) + 1057 HCF 56k Data/Fax/Voice/Spkp Modem (Worldwide) + 1059 HCF 56k Data/Fax/Voice Modem (Worldwide) + 1063 HCF 56k Data/Fax Modem + 1064 HCF 56k Data/Fax/Voice Modem + 1065 HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem + 1066 HCF 56k Data/Fax/Voice/Spkp Modem + 122d 4033 Dell Athena - MDP3900V-U + 1085 HCF V90 56k Data/Fax/Voice/Spkp PCI Modem + 1433 HCF 56k Data/Fax Modem + 1434 HCF 56k Data/Fax/Voice Modem + 1435 HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem + 1436 HCF 56k Data/Fax Modem + 1453 HCF 56k Data/Fax Modem + 13e0 0240 IBM + 13e0 0250 IBM + 144f 1502 IBM P95-DF (1) + 144f 1503 IBM P95-DF (2) + 1454 HCF 56k Data/Fax/Voice Modem + 1455 HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem + 1456 HCF 56k Data/Fax/Voice/Spkp Modem + 122d 4035 Dell Europa - MDP3900V-W + 122d 4302 Dell MP3930V-W(C) MiniPCI + 1610 ADSL AccessRunner PCI Arbitration Device + 1611 AccessRunner PCI ADSL Interface Device + 1620 AccessRunner V2 PCI ADSL Arbitration Device + 1621 AccessRunner V2 PCI ADSL Interface Device + 1622 AccessRunner V2 PCI ADSL Yukon WAN Adapter + 1803 HCF 56k Modem + 0e11 0023 623-LAN Grizzly + 0e11 0043 623-LAN Yogi + 1811 Conextant MiniPCI Network Adapter + 1815 HCF 56k Modem + 0e11 0022 Grizzly + 0e11 0042 Yogi + 2003 HSF 56k Data/Fax Modem + 2004 HSF 56k Data/Fax/Voice Modem + 2005 HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem + 2006 HSF 56k Data/Fax/Voice/Spkp Modem + 2013 HSF 56k Data/Fax Modem + 0e11 b195 Bear + 0e11 b196 Seminole 1 + 0e11 b1be Seminole 2 + 1025 8013 Acer + 1033 809d NEC + 1033 80bc NEC + 155d 6793 HP + 155d 8850 E Machines + 2014 HSF 56k Data/Fax/Voice Modem + 2015 HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem + 2016 HSF 56k Data/Fax/Voice/Spkp Modem + 2043 HSF 56k Data/Fax Modem (WorldW SmartDAA) + 2044 HSF 56k Data/Fax/Voice Modem (WorldW SmartDAA) + 2045 HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem (WorldW SmartDAA) + 14f1 2045 Generic SoftK56 + 2046 HSF 56k Data/Fax/Voice/Spkp Modem (WorldW SmartDAA) + 2063 HSF 56k Data/Fax Modem (SmartDAA) + 2064 HSF 56k Data/Fax/Voice Modem (SmartDAA) + 2065 HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem (SmartDAA) + 2066 HSF 56k Data/Fax/Voice/Spkp Modem (SmartDAA) + 2093 HSF 56k Modem + 155d 2f07 Legend + 2143 HSF 56k Data/Fax/Cell Modem (Mob WorldW SmartDAA) + 2144 HSF 56k Data/Fax/Voice/Cell Modem (Mob WorldW SmartDAA) + 2145 HSF 56k Data/Fax/Voice/Spkp (w/HS)/Cell Modem (Mob WorldW SmartDAA) + 2146 HSF 56k Data/Fax/Voice/Spkp/Cell Modem (Mob WorldW SmartDAA) + 2163 HSF 56k Data/Fax/Cell Modem (Mob SmartDAA) + 2164 HSF 56k Data/Fax/Voice/Cell Modem (Mob SmartDAA) + 2165 HSF 56k Data/Fax/Voice/Spkp (w/HS)/Cell Modem (Mob SmartDAA) + 2166 HSF 56k Data/Fax/Voice/Spkp/Cell Modem (Mob SmartDAA) + 2343 HSF 56k Data/Fax CardBus Modem (Mob WorldW SmartDAA) + 2344 HSF 56k Data/Fax/Voice CardBus Modem (Mob WorldW SmartDAA) + 2345 HSF 56k Data/Fax/Voice/Spkp (w/HS) CardBus Modem (Mob WorldW SmartDAA) + 2346 HSF 56k Data/Fax/Voice/Spkp CardBus Modem (Mob WorldW SmartDAA) + 2363 HSF 56k Data/Fax CardBus Modem (Mob SmartDAA) + 2364 HSF 56k Data/Fax/Voice CardBus Modem (Mob SmartDAA) + 2365 HSF 56k Data/Fax/Voice/Spkp (w/HS) CardBus Modem (Mob SmartDAA) + 2366 HSF 56k Data/Fax/Voice/Spkp CardBus Modem (Mob SmartDAA) + 2443 HSF 56k Data/Fax Modem (Mob WorldW SmartDAA) + 104d 8075 Modem + 104d 8083 Modem + 104d 8097 Modem + 2444 HSF 56k Data/Fax/Voice Modem (Mob WorldW SmartDAA) + 2445 HSF 56k Data/Fax/Voice/Spkp (w/HS) Modem (Mob WorldW SmartDAA) + 2446 HSF 56k Data/Fax/Voice/Spkp Modem (Mob WorldW SmartDAA) + 2463 HSF 56k Data/Fax Modem (Mob SmartDAA) + 2464 HSF 56k Data/Fax/Voice Modem (Mob SmartDAA) + 2465 HSF 56k Data/Fax/Voice/Spkp (w/HS) Modem (Mob SmartDAA) + 2466 HSF 56k Data/Fax/Voice/Spkp Modem (Mob SmartDAA) + 2bfa HDAudio Soft Data Fax Modem with SmartCP + 2f00 HSF 56k HSFi Modem + 13e0 8d84 IBM HSFi V.90 + 13e0 8d85 Compaq Stinger + 14f1 2004 Dynalink 56PMi + 2f02 HSF 56k HSFi Data/Fax + 2f11 HSF 56k HSFi Modem + 2f20 HSF 56k Data/Fax Modem + 8234 RS8234 ATM SAR Controller [ServiceSAR Plus] + 8800 CX23880/1/2/3 PCI Video and Audio Decoder + 0070 2801 Hauppauge WinTV 28xxx (Roslyn) models + 0070 3401 Hauppauge WinTV 34xxx models + 0070 9001 Nova-T DVB-T + 0070 9200 Nova-SE2 DVB-S + 0070 9202 Nova-S-Plus DVB-S + 0070 9402 WinTV-HVR1100 DVB-T/Hybrid + 0070 9802 WinTV-HVR1100 DVB-T/Hybrid (Low Profile) + 1002 00f8 ATI TV Wonder Pro + 1002 a101 HDTV Wonder + 1043 4823 ASUS PVR-416 + 107d 6613 Leadtek Winfast 2000XP Expert + 107d 6620 Leadtek Winfast DV2000 + 107d 663c Leadtek PVR 2000 + 107d 665f WinFast DTV1000-T + 10fc d003 IODATA GV-VCP3/PCI + 10fc d035 IODATA GV/BCTV7E + 1421 0334 Instant TV DVB-T PCI + 1461 000a AVerTV 303 (M126) + 1461 000b AverTV Studio 303 (M126) + 1461 8011 UltraTV Media Center PCI 550 + 1462 8606 MSI TV-@nywhere Master + 14c7 0107 GDI Black Gold + 14f1 0187 Conexant DVB-T reference design + 14f1 0342 Digital-Logic MICROSPACE Entertainment Center (MEC) + 153b 1166 Cinergy 1400 DVB-T + 1540 2580 Provideo PV259 + 1554 4811 PixelView + 1554 4813 Club 3D ZAP1000 MCE Edition + 17de 08a1 KWorld/VStream XPert DVB-T with cx22702 + 17de 08a6 KWorld/VStream XPert DVB-T + 17de 08b2 KWorld DVB-S 100 + 17de a8a6 digitalnow DNTV Live! DVB-T + 1822 0025 digitalnow DNTV Live! DVB-T Pro + 18ac d500 FusionHDTV 5 Gold + 18ac d810 FusionHDTV 3 Gold-Q + 18ac d820 FusionHDTV 3 Gold-T + 18ac db00 FusionHDTV DVB-T1 + 18ac db11 FusionHDTV DVB-T Plus + 18ac db50 FusionHDTV DVB-T Dual Digital + 7063 3000 pcHDTV HD3000 HDTV + 8801 CX23880/1/2/3 PCI Video and Audio Decoder [Audio Port] + 0070 2801 Hauppauge WinTV 28xxx (Roslyn) models + 8802 CX23880/1/2/3 PCI Video and Audio Decoder [MPEG Port] + 0070 2801 Hauppauge WinTV 28xxx (Roslyn) models + 0070 9002 Nova-T DVB-T Model 909 + 1043 4823 ASUS PVR-416 + 107d 663c Leadtek PVR 2000 + 14f1 0187 Conexant DVB-T reference design + 17de 08a1 XPert DVB-T PCI BDA DVBT 23880 Transport Stream Capture + 17de 08a6 KWorld/VStream XPert DVB-T + 18ac d500 DViCO FusionHDTV5 Gold + 18ac d810 DViCO FusionHDTV3 Gold-Q + 18ac d820 DViCO FusionHDTV3 Gold-T + 18ac db00 DVICO FusionHDTV DVB-T1 + 18ac db10 DVICO FusionHDTV DVB-T Plus + 7063 3000 pcHDTV HD3000 HDTV + 8804 CX23880/1/2/3 PCI Video and Audio Decoder [IR Port] + 0070 9002 Nova-T DVB-T Model 909 + 8811 CX23880/1/2/3 PCI Video and Audio Decoder [Audio Port] + 0070 3401 Hauppauge WinTV 34xxx models + 1462 8606 MSI TV-@nywhere Master + 18ac d500 DViCO FusionHDTV5 Gold + 18ac d810 DViCO FusionHDTV3 Gold-Q + 18ac d820 DViCO FusionHDTV3 Gold-T + 18ac db00 DVICO FusionHDTV DVB-T1 +14f2 MOBILITY Electronics + 0120 EV1000 bridge + 0121 EV1000 Parallel port + 0122 EV1000 Serial port + 0123 EV1000 Keyboard controller + 0124 EV1000 Mouse controller +14f3 BroadLogic + 2030 2030 DVB-S Satellite Reciever + 2050 2050 DVB-T Terrestrial (Cable) Reciever + 2060 2060 ATSC Terrestrial (Cable) Reciever +14f4 TOKYO Electronic Industry CO Ltd +14f5 SOPAC Ltd +14f6 COYOTE Technologies LLC +14f7 WOLF Technology Inc +14f8 AUDIOCODES Inc + 2077 TP-240 dual span E1 VoIP PCI card +14f9 AG COMMUNICATIONS +14fa WANDEL & GOLTERMANN +14fb TRANSAS MARINE (UK) Ltd +14fc Quadrics Ltd + 0000 QsNet Elan3 Network Adapter + 0001 QsNetII Elan4 Network Adapter + 0002 QsNetIII Elan5 Network Adapter +14fd JAPAN Computer Industry Inc +14fe ARCHTEK TELECOM Corp +14ff TWINHEAD INTERNATIONAL Corp +1500 DELTA Electronics, Inc + 1360 RTL81xx RealTek Ethernet +1501 BANKSOFT CANADA Ltd +1502 MITSUBISHI ELECTRIC LOGISTICS SUPPORT Co Ltd +1503 KAWASAKI LSI USA Inc +1504 KAISER Electronics +1505 ITA INGENIEURBURO FUR TESTAUFGABEN GmbH +1506 CHAMELEON Systems Inc +# Should be HTEC Ltd, but there are no known HTEC chips and 1507 is already used by mistake by Motorola (see vendor ID 1057). +1507 Motorola ?? / HTEC + 0001 MPC105 [Eagle] + 0002 MPC106 [Grackle] + 0003 MPC8240 [Kahlua] + 0100 MC145575 [HFC-PCI] + 0431 KTI829c 100VG + 4801 Raven + 4802 Falcon + 4803 Hawk + 4806 CPX8216 +1508 HONDA CONNECTORS/MHOTRONICS Inc +1509 FIRST INTERNATIONAL Computer Inc +150a FORVUS RESEARCH Inc +150b YAMASHITA Systems Corp +150c KYOPAL CO Ltd +150d WARPSPPED Inc +150e C-PORT Corp +150f INTEC GmbH +1510 BEHAVIOR TECH Computer Corp +1511 CENTILLIUM Technology Corp +1512 ROSUN Technologies Inc +1513 Raychem +1514 TFL LAN Inc +1515 Advent design +1516 MYSON Technology Inc + 0800 MTD-8xx 100/10M Ethernet PCI Adapter + 0803 SURECOM EP-320X-S 100/10M Ethernet PCI Adapter + 1320 10bd SURECOM EP-320X-S 100/10M Ethernet PCI Adapter + 0891 MTD-8xx 100/10M Ethernet PCI Adapter +1517 ECHOTEK Corp +1518 PEP MODULAR Computers GmbH +1519 TELEFON AKTIEBOLAGET LM Ericsson +151a Globetek + 1002 PCI-1002 + 1004 PCI-1004 + 1008 PCI-1008 +151b COMBOX Ltd +151c DIGITAL AUDIO LABS Inc + 0003 Prodif T 2496 + 4000 Prodif 88 +151d Fujitsu Computer Products Of America +151e MATRIX Corp +151f TOPIC SEMICONDUCTOR Corp + 0000 TP560 Data/Fax/Voice 56k modem +1520 CHAPLET System Inc +1521 BELL Corp +1522 MainPine Ltd + 0100 PCI <-> IOBus Bridge + 1522 0200 RockForceDUO 2 Port V.92/V.44 Data/Fax/Voice Modem + 1522 0300 RockForceQUATRO 4 Port V.92/V.44 Data/Fax/Voice Modem + 1522 0400 RockForceDUO+ 2 Port V.92/V.44 Data/Fax/Voice Modem + 1522 0500 RockForceQUATRO+ 4 Port V.92/V.44 Data/Fax/Voice Modem + 1522 0600 RockForce+ 2 Port V.90 Data/Fax/Voice Modem + 1522 0700 RockForce+ 4 Port V.90 Data/Fax/Voice Modem + 1522 0800 RockForceOCTO+ 8 Port V.92/V.44 Data/Fax/Voice Modem + 1522 0c00 RockForceDUO+ 2 Port V.92/V.44 Data, V.34 Super-G3 Fax, Voice Modem + 1522 0d00 RockForceQUATRO+ 4 Port V.92/V.44 Data, V.34 Super-G3 Fax, Voice Modem + 1522 1d00 RockForceOCTO+ 8 Port V.92/V.44 Data, V.34 Super-G3 Fax, Voice Modem + 1522 2000 RockForceD1 1 Port V.90 Data Modem + 1522 2100 RockForceF1 1 Port V.34 Super-G3 Fax Modem + 1522 2200 RockForceD2 2 Port V.90 Data Modem + 1522 2300 RockForceF2 2 Port V.34 Super-G3 Fax Modem + 1522 2400 RockForceD4 4 Port V.90 Data Modem + 1522 2500 RockForceF4 4 Port V.34 Super-G3 Fax Modem + 1522 2600 RockForceD8 8 Port V.90 Data Modem + 1522 2700 RockForceF8 8 Port V.34 Super-G3 Fax Modem +1523 MUSIC Semiconductors +1524 ENE Technology Inc + 0510 CB710 Memory Card Reader Controller + 103c 006a NX9500 + 0520 FLASH memory: ENE Technology Inc: + 0530 ENE PCI Memory Stick Card Reader Controller + 0550 ENE PCI Secure Digital Card Reader Controller + 0610 PCI Smart Card Reader Controller + 1211 CB1211 Cardbus Controller + 1225 CB1225 Cardbus Controller + 1410 CB1410 Cardbus Controller + 1025 003c CL50 motherboard + 1025 005a TravelMate 290 + 1411 CB-710/2/4 Cardbus Controller + 103c 006a NX9500 + 1412 CB-712/4 Cardbus Controller + 1420 CB1420 Cardbus Controller + 1421 CB-720/2/4 Cardbus Controller + 1422 CB-722/4 Cardbus Controller +1525 IMPACT Technologies +1526 ISS, Inc +1527 SOLECTRON +1528 ACKSYS +1529 AMERICAN MICROSystems Inc +152a QUICKTURN DESIGN Systems +152b FLYTECH Technology CO Ltd +152c MACRAIGOR Systems LLC +152d QUANTA Computer Inc +152e MELEC Inc +152f PHILIPS - CRYPTO +1530 ACQIS Technology Inc +1531 CHRYON Corp +1532 ECHELON Corp + 0020 LonWorks PCLTA-20 PCI LonTalk Adapter +1533 BALTIMORE +1534 ROAD Corp +1535 EVERGREEN Technologies Inc +1537 DATALEX COMMUNCATIONS +1538 ARALION Inc + 0303 ARS106S Ultra ATA 133/100/66 Host Controller +1539 ATELIER INFORMATIQUES et ELECTRONIQUE ETUDES S.A. +153a ONO SOKKI +153b TERRATEC Electronic GmbH + 1144 Aureon 5.1 +# Terratec seems to use several IDs for the same card. + 1147 Aureon 5.1 Sky + 1158 Philips Semiconductors SAA7134 (rev 01) [Terratec Cinergy 600 TV] +153c ANTAL Electronic +153d FILANET Corp +153e TECHWELL Inc +153f MIPS Technologies, Inc. + 0001 SOC-it 101 System Controller +1540 PROVIDEO MULTIMEDIA Co Ltd +1541 MACHONE Communications +1542 Concurrent Computer Corporation + 9260 RCIM-II Real-Time Clock & Interrupt Module +1543 SILICON Laboratories + 3052 Intel 537 [Winmodem] + 4c22 Si3036 MC'97 DAA +1544 DCM DATA Systems +1545 VISIONTEK +1546 IOI Technology Corp +1547 MITUTOYO Corp +1548 JET PROPULSION Laboratory +1549 INTERCONNECT Systems Solutions +154a MAX Technologies Inc +154b COMPUTEX Co Ltd +154c VISUAL Technology Inc +154d PAN INTERNATIONAL Industrial Corp +154e SERVOTEST Ltd +154f STRATABEAM Technology +1550 OPEN NETWORK Co Ltd +1551 SMART Electronic DEVELOPMENT GmBH +1552 RACAL AIRTECH Ltd +1553 CHICONY Electronics Co Ltd +1554 PROLINK Microsystems Corp +1555 GESYTEC GmBH +1556 PLD APPLICATIONS +1557 MEDIASTAR Co Ltd +1558 CLEVO/KAPOK Computer +1559 SI LOGIC Ltd +155a INNOMEDIA Inc +155b PROTAC INTERNATIONAL Corp +155c Cemax-Icon Inc +155d Mac System Co Ltd +155e LP Elektronik GmbH +155f Perle Systems Ltd +1560 Terayon Communications Systems +1561 Viewgraphics Inc +1562 Symbol Technologies +1563 A-Trend Technology Co Ltd +1564 Yamakatsu Electronics Industry Co Ltd +1565 Biostar Microtech Int'l Corp +1566 Ardent Technologies Inc +1567 Jungsoft +1568 DDK Electronics Inc +1569 Palit Microsystems Inc. +156a Avtec Systems +156b 2wire Inc +156c Vidac Electronics GmbH +156d Alpha-Top Corp +156e Alfa Inc +156f M-Systems Flash Disk Pioneers Ltd +1570 Lecroy Corp +1571 Contemporary Controls + a001 CCSI PCI20-485 ARCnet + a002 CCSI PCI20-485D ARCnet + a003 CCSI PCI20-485X ARCnet + a004 CCSI PCI20-CXB ARCnet + a005 CCSI PCI20-CXS ARCnet + a006 CCSI PCI20-FOG-SMA ARCnet + a007 CCSI PCI20-FOG-ST ARCnet + a008 CCSI PCI20-TB5 ARCnet + a009 CCSI PCI20-5-485 5Mbit ARCnet + a00a CCSI PCI20-5-485D 5Mbit ARCnet + a00b CCSI PCI20-5-485X 5Mbit ARCnet + a00c CCSI PCI20-5-FOG-ST 5Mbit ARCnet + a00d CCSI PCI20-5-FOG-SMA 5Mbit ARCnet + a201 CCSI PCI22-485 10Mbit ARCnet + a202 CCSI PCI22-485D 10Mbit ARCnet + a203 CCSI PCI22-485X 10Mbit ARCnet + a204 CCSI PCI22-CHB 10Mbit ARCnet + a205 CCSI PCI22-FOG_ST 10Mbit ARCnet + a206 CCSI PCI22-THB 10Mbit ARCnet +1572 Otis Elevator Company +1573 Lattice - Vantis +1574 Fairchild Semiconductor +1575 Voltaire Advanced Data Security Ltd +1576 Viewcast COM +1578 HITT + 5615 VPMK3 [Video Processor Mk III] +1579 Dual Technology Corp +157a Japan Elecronics Ind Inc +157b Star Multimedia Corp +157c Eurosoft (UK) + 8001 Fix2000 PCI Y2K Compliance Card +157d Gemflex Networks +157e Transition Networks +157f PX Instruments Technology Ltd +1580 Primex Aerospace Co +1581 SEH Computertechnik GmbH +1582 Cytec Corp +1583 Inet Technologies Inc +1584 Uniwill Computer Corp +1585 Logitron +1586 Lancast Inc +1587 Konica Corp +1588 Solidum Systems Corp +1589 Atlantek Microsystems Pty Ltd +158a Digalog Systems Inc +158b Allied Data Technologies +158c Hitachi Semiconductor & Devices Sales Co Ltd +158d Point Multimedia Systems +158e Lara Technology Inc +158f Ditect Coop +1590 3pardata Inc +1591 ARN +1592 Syba Tech Ltd + 0781 Multi-IO Card + 0782 Parallel Port Card 2xEPP + 0783 Multi-IO Card + 0785 Multi-IO Card + 0786 Multi-IO Card + 0787 Multi-IO Card + 0788 Multi-IO Card + 078a Multi-IO Card +1593 Bops Inc +1594 Netgame Ltd +1595 Diva Systems Corp +1596 Folsom Research Inc +1597 Memec Design Services +1598 Granite Microsystems +1599 Delta Electronics Inc +159a General Instrument +159b Faraday Technology Corp +159c Stratus Computer Systems +159d Ningbo Harrison Electronics Co Ltd +159e A-Max Technology Co Ltd +159f Galea Network Security +15a0 Compumaster SRL +15a1 Geocast Network Systems +15a2 Catalyst Enterprises Inc + 0001 TA700 PCI Bus Analyzer/Exerciser +15a3 Italtel +15a4 X-Net OY +15a5 Toyota Macs Inc +15a6 Sunlight Ultrasound Technologies Ltd +15a7 SSE Telecom Inc +15a8 Shanghai Communications Technologies Center +15aa Moreton Bay +15ab Bluesteel Networks Inc +15ac North Atlantic Instruments +15ad VMware Inc + 0405 [VMware SVGA II] PCI Display Adapter + 0710 Virtual SVGA + 0720 VMware High-Speed Virtual NIC [vmxnet] +15ae Amersham Pharmacia Biotech +15b0 Zoltrix International Ltd +15b1 Source Technology Inc +15b2 Mosaid Technologies Inc +15b3 Mellanox Technologies + 5274 MT21108 InfiniBridge + 5a44 MT23108 InfiniHost + 5a45 MT23108 [Infinihost HCA Flash Recovery] + 5a46 MT23108 PCI Bridge + 5e8d MT25204 [InfiniHost III Lx HCA Flash Recovery] + 6274 MT25204 [InfiniHost III Lx HCA] + 6278 MT25208 InfiniHost III Ex (Tavor compatibility mode) + 6279 MT25208 [InfiniHost III Ex HCA Flash Recovery] + 6282 MT25208 InfiniHost III Ex +15b4 CCI/TRIAD +15b5 Cimetrics Inc +15b6 Texas Memory Systems Inc +15b7 Sandisk Corp +15b8 ADDI-DATA GmbH +15b9 Maestro Digital Communications +15ba Impacct Technology Corp +15bb Portwell Inc +15bc Agilent Technologies + 1100 E8001-66442 PCI Express CIC + 2922 64 Bit, 133MHz PCI-X Exerciser & Protocol Checker + 2928 64 Bit, 66MHz PCI Exerciser & Analyzer + 2929 64 Bit, 133MHz PCI-X Analyzer & Exerciser +15bd DFI Inc +15be Sola Electronics +15bf High Tech Computer Corp (HTC) +15c0 BVM Ltd +15c1 Quantel +15c2 Newer Technology Inc +15c3 Taiwan Mycomp Co Ltd +15c4 EVSX Inc +15c5 Procomp Informatics Ltd + 8010 1394b - 1394 Firewire 3-Port Host Adapter Card +15c6 Technical University of Budapest +15c7 Tateyama System Laboratory Co Ltd + 0349 Tateyama C-PCI PLC/NC card Rev.01A +15c8 Penta Media Co Ltd +15c9 Serome Technology Inc +15ca Bitboys OY +15cb AG Electronics Ltd +15cc Hotrail Inc +15cd Dreamtech Co Ltd +15ce Genrad Inc +15cf Hilscher GmbH +15d1 Infineon Technologies AG +15d2 FIC (First International Computer Inc) +15d3 NDS Technologies Israel Ltd +15d4 Iwill Corp +15d5 Tatung Co +15d6 Entridia Corp +15d7 Rockwell-Collins Inc +15d8 Cybernetics Technology Co Ltd +15d9 Super Micro Computer Inc +15da Cyberfirm Inc +15db Applied Computing Systems Inc +15dc Litronic Inc + 0001 Argus 300 PCI Cryptography Module +15dd Sigmatel Inc +15de Malleable Technologies Inc +15df Infinilink Corp +15e0 Cacheflow Inc +15e1 Voice Technologies Group Inc +15e2 Quicknet Technologies Inc +15e3 Networth Technologies Inc +15e4 VSN Systemen BV +15e5 Valley technologies Inc +15e6 Agere Inc +15e7 Get Engineering Corp +15e8 National Datacomm Corp + 0130 Wireless PCI Card +15e9 Pacific Digital Corp + 1841 ADMA-100 DiscStaQ ATA Controller +15ea Tokyo Denshi Sekei K.K. +15eb Drsearch GmbH +15ec Beckhoff GmbH + 3101 FC3101 Profibus DP 1 Channel PCI + 5102 FC5102 +15ed Macrolink Inc +15ee In Win Development Inc +15ef Intelligent Paradigm Inc +15f0 B-Tree Systems Inc +15f1 Times N Systems Inc +15f2 Diagnostic Instruments Inc +15f3 Digitmedia Corp +15f4 Valuesoft +15f5 Power Micro Research +15f6 Extreme Packet Device Inc +15f7 Banctec +15f8 Koga Electronics Co +15f9 Zenith Electronics Corp +15fa J.P. Axzam Corp +15fb Zilog Inc +15fc Techsan Electronics Co Ltd +15fd N-CUBED.NET +15fe Kinpo Electronics Inc +15ff Fastpoint Technologies Inc +1600 Northrop Grumman - Canada Ltd +1601 Tenta Technology +1602 Prosys-tec Inc +1603 Nokia Wireless Communications +1604 Central System Research Co Ltd +1605 Pairgain Technologies +1606 Europop AG +1607 Lava Semiconductor Manufacturing Inc +1608 Automated Wagering International +1609 Scimetric Instruments Inc +1612 Telesynergy Research Inc. +1619 FarSite Communications Ltd + 0400 FarSync T2P (2 port X.21/V.35/V.24) + 0440 FarSync T4P (4 port X.21/V.35/V.24) + 0610 FarSync T1U (1 port X.21/V.35/V.24) + 0620 FarSync T2U (2 port X.21/V.35/V.24) + 0640 FarSync T4U (4 port X.21/V.35/V.24) + 1610 FarSync TE1 (T1,E1) + 2610 FarSync DSL-S1 (SHDSL) +161f Rioworks +1626 TDK Semiconductor Corp. + 8410 RTL81xx Fast Ethernet +1629 Kongsberg Spacetec AS + 1003 Format synchronizer v3.0 + 2002 Fast Universal Data Output +# This seems to occur on their 802.11b Wireless card WMP-11 +1637 Linksys + 3874 Linksys 802.11b WMP11 PCI Wireless card +1638 Standard Microsystems Corp [SMC] + 1100 SMC2602W EZConnect / Addtron AWA-100 / Eumitcom PCI WL11000 +163c Smart Link Ltd. + 3052 SmartLink SmartPCI562 56K Modem + 5449 SmartPCI561 Modem +1657 Brocade Communications Systems, Inc. +165a Epix Inc + c100 PIXCI(R) CL1 Camera Link Video Capture Board [custom QL5232] + d200 PIXCI(R) D2X Digital Video Capture Board [custom QL5232] + d300 PIXCI(R) D3X Digital Video Capture Board [custom QL5232] +165d Hsing Tech. Enterprise Co., Ltd. +165f Linux Media Labs, LLC + 1020 LMLM4 MPEG-4 encoder +1661 Worldspace Corp. +1668 Actiontec Electronics Inc + 0100 Mini-PCI bridge +# Formerly SiByte, Inc. +166d Broadcom Corporation + 0001 SiByte BCM1125/1125H/1250 System-on-a-Chip PCI + 0002 SiByte BCM1125H/1250 System-on-a-Chip HyperTransport +1677 Bernecker + Rainer + 104e 5LS172.6 B&R Dual CAN Interface Card + 12d7 5LS172.61 B&R Dual CAN Interface Card + 20ad 5ACPCI.MFIO-K01 Profibus DP / K-Feldbus / COM +167b ZyDAS Technology Corp. + 2102 ZyDAS ZD1202 + 187e 3406 ZyAIR B-122 CardBus 11Mbs Wireless LAN Card +167d Samsung Electro-Mechanics Co., Ltd. + a000 IPW2200 miniPCI Wireless +1681 Hercules + 0010 Hercules 3d Prophet II Ultra 64MB (350 MHz NV15BR core) +1682 XFX Pine Group Inc. +1688 CastleNet Technology Inc. + 1170 WLAN 802.11b card +168c Atheros Communications, Inc. + 0007 AR5000 802.11a Wireless Adapter + 0011 AR5210 802.11a NIC + 0012 AR5211 802.11ab NIC + 0013 AR5212 802.11abg NIC + 1113 d301 Philips CPWNA100 Wireless CardBus adapter + 1186 3202 D-link DWL-G650 (Rev B3,B5) Wireless cardbus adapter + 1186 3203 DWL-G520 Wireless PCI Adapter + 1186 3a12 D-Link AirPlus DWL-G650 Wireless Cardbus Adapter(rev.C) + 1186 3a13 D-Link AirPlus DWL-G520 Wireless PCI Adapter(rev.B) + 1186 3a14 D-Link AirPremier DWL-AG530 Wireless PCI Adapter + 1186 3a17 D-Link AirPremier DWL-G680 Wireless Cardbus Adapter + 1186 3a18 D-Link AirPremier DWL-G550 Wireless PCI Adapter + 1186 3a63 D-Link AirPremier DWL-AG660 Wireless Cardbus Adapter + 1186 3a93 Conceptronic C54I Wireless 801.11g PCI card + 1186 3a94 C54C Wireless 801.11g cardbus + 1186 3ab0 Allnet ALL0281 Wireless PCI Card + 1385 4d00 Netgear WG311T Wireless PCI Adapter + 1458 e911 Gigabyte GN-WIAG02 + 14b7 0a60 8482-WD ORiNOCO 11a/b/g Wireless PCI Adapter + 1668 1026 IBM HighRate 11 a/b/g Wireless CardBus Adapter + 168c 0013 AirPlus XtremeG DWL-G650 Wireless PCMCIA Adapter + 168c 1025 DWL-G650B2 Wireless CardBus Adapter + 168c 1027 Engenius NL-3054CB ARIES b/g CardBus Adapter + 168c 1042 Ubiquiti Networks SuperRange a/b/g Cardbus Adapter + 168c 2026 Netgate 5354MP ARIES a(108Mb turbo)/b/g MiniPCI Adapter + 168c 2041 Engenius 5354MP Plus ARIES2 b/g MiniPCI Adapter + 168c 2042 Engenius 5354MP Plus ARIES2 a/b/g MiniPCI Adapter + 168c 2051 TRENDnet TEW-443PI Wireless PCI Adapter + 16ab 7302 Trust Speedshare Turbo Pro Wireless PCI Adapter + 185f 2012 Wistron NeWeb WLAN a+b+g model CB9 + 001a AR5005G 802.11abg NIC + 1113 ee20 SMC Wireless CardBus Adapter 802.11g (SMCWCB-G EU) + 1113 ee24 SMC Wireless PCI Card WPCI-G + 1186 3a15 D-Link AirPlus G DWL-G630 Wireless Cardbus Adapter(rev.D) + 1186 3a16 D-Link AirPlus G DWL-G510 Wireless PCI Adapter(rev.B) + 1186 3a23 D-Link AirPlus G DWL-G520+A Wireless PCI Adapter + 1186 3a24 D-Link AirPlus G DWL-G650+A Wireless Cardbus Adapter + 168c 001a Belkin FD7000 + 168c 1052 TP-Link TL-WN510G Wireless CardBus Adapter + 001b AR5006X 802.11abg NIC + 1186 3a19 D-Link AirPremier AG DWL-AG660 Wireless Cardbus Adapter + 1186 3a22 D-Link AirPremier AG DWL-AG530 Wireless PCI Adapter + 168c 2062 EnGenius EMP-8602 (400mw) or Compex WLM54AG (SuperAG) + 168c 2063 EnGenius EMP-8602 (400mw) or Compex WLM54AG + 0020 AR5005VL 802.11bg Wireless NIC + 1014 AR5212 802.11abg NIC + 1014 058a ThinkPad 11a/b/g Wireless LAN Mini Express Adapter (AR5BXB6) +1695 EPoX Computer Co., Ltd. +169c Netcell Corporation + 0044 Revolution Storage Processing Card +16a5 Tekram Technology Co.,Ltd. +16ab Global Sun Technology Inc + 1100 GL24110P + 1101 PLX9052 PCMCIA-to-PCI Wireless LAN + 1102 PCMCIA-to-PCI Wireless Network Bridge + 8501 WL-8305 Wireless LAN PCI Adapter +16ae Safenet Inc + 1141 SafeXcel-1141 +16af SparkLAN Communications, Inc. +16b4 Aspex Semiconductor Ltd +16b8 Sonnet Technologies, Inc. +16be Creatix Polymedia GmbH +16c6 Micrel-Kendin + 8695 Centaur KS8695 ARM processor +16c8 Octasic Inc. +16c9 EONIC B.V. The Netherlands +16ca CENATEK Inc + 0001 Rocket Drive DL +16cd Densitron Technologies +16ce Roland Corp. +16d5 Acromag, Inc. + 4d4e PMC482, APC482, AcPC482 Counter Timer Board +16df PIKA Technologies Inc. +16e3 European Space Agency + 1e0f LEON2FT Processor +16e5 Intellon Corp. + 6000 INT6000 Ethernet-to-Powerline Bridge [HomePlug AV] +16ec U.S. Robotics + 00ff USR997900 10/100 Mbps PCI Network Card + 0116 USR997902 10/100/1000 Mbps PCI Network Card + 2f00 USR5660A (USR265660A, USR5660A-BP) 56K PCI Faxmodem + 3685 Wireless Access PCI Adapter Model 022415 +16ed Sycron N. V. + 1001 UMIO communication card +16f3 Jetway Information Co., Ltd. +16f4 Vweb Corp + 8000 VW2010 +16f6 VideoTele.com, Inc. +1702 Internet Machines Corporation (IMC) +1705 Digital First, Inc. +170b NetOctave + 0100 NSP2000-SSL crypto accelerator +170c YottaYotta Inc. +# Seems to be a 2nd ID for Vitesse Semiconductor +1725 Vitesse Semiconductor + 7174 VSC7174 PCI/PCI-X Serial ATA Host Bus Controller +172a Accelerated Encryption + 13c8 AEP SureWare Runner 1000V3 +1734 Fujitsu Siemens Computer GmbH + 1078 Amilo Pro v2010 +1737 Linksys + 0013 WMP54G Wireless Pci Card + 0015 WMP54GS Wireless Pci Card + 1032 Gigabit Network Adapter + 1737 0015 EG1032 v2 Instant Gigabit Network Adapter + 1737 0024 EG1032 v3 Instant Gigabit Network Adapter + 1064 Gigabit Network Adapter + 1737 0016 EG1064 v2 Instant Gigabit Network Adapter + ab08 21x4x DEC-Tulip compatible 10/100 Ethernet + ab09 21x4x DEC-Tulip compatible 10/100 Ethernet +173b Altima (nee Broadcom) + 03e8 AC1000 Gigabit Ethernet + 03e9 AC1001 Gigabit Ethernet + 03ea AC9100 Gigabit Ethernet + 173b 0001 AC1002 + 03eb AC1003 Gigabit Ethernet +1743 Peppercon AG + 8139 ROL/F-100 Fast Ethernet Adapter with ROL +1749 RLX Technologies +174b PC Partner Limited +174d WellX Telecom SA +175c AudioScience Inc +175e Sanera Systems, Inc. +1775 SBS Technologies +1787 Hightech Information System Ltd. +# also used by Struck Innovative Systeme for joint developments +1796 Research Centre Juelich + 0001 SIS1100 [Gigabit link] + 0002 HOTlink + 0003 Counter Timer + 0004 CAMAC Controller + 0005 PROFIBUS + 0006 AMCC HOTlink +1797 JumpTec h, GMBH +1799 Belkin + 6001 Wireless PCI Card - F5D6001 + 6020 Wireless PCMCIA Card - F5D6020 + 6060 Wireless PDA Card - F5D6060 + 7000 Wireless PCI Card - F5D7000 + 700a Wireless PCI Card - F5D7000UK + 7010 BCM4306 802.11b/g Wireless Lan Controller F5D7010 +179c Data Patterns + 0557 DP-PCI-557 [PCI 1553B] + 0566 DP-PCI-566 [Intelligent PCI 1553B] + 5031 DP-CPCI-5031-Synchro Module + 5121 DP-CPCI-5121-IP Carrier + 5211 DP-CPCI-5211-IP Carrier + 5679 AGE Display Module +17a0 Genesys Logic, Inc + 8033 GL880S USB 1.1 controller + 8034 GL880S USB 2.0 controller +17aa Lenovo +17af Hightech Information System Ltd. +17b3 Hawking Technologies + ab08 PN672TX 10/100 Ethernet +17b4 Indra Networks, Inc. + 0011 WebEnhance 100 GZIP Compression Card +17c0 Wistron Corp. +17c2 Newisys, Inc. +17cb Airgo Networks Inc + 0001 AGN100 802.11 a/b/g True MIMO Wireless Card + 0002 AGN300 802.11 a/b/g True MIMO Wireless Card +17cc NetChip Technology, Inc + 2280 USB 2.0 +17cf Z-Com, Inc. +17d3 Areca Technology Corp. + 1110 ARC-1110 4-Port PCI-X to SATA RAID Controller + 1120 ARC-1120 8-Port PCI-X to SATA RAID Controller + 1130 ARC-1130 12-Port PCI-X to SATA RAID Controller + 1160 ARC-1160 16-Port PCI-X to SATA RAID Controller + 1210 ARC-1210 4-Port PCI-Express to SATA RAID Controller + 1220 ARC-1220 8-Port PCI-Express to SATA RAID Controller + 1230 ARC-1230 12-Port PCI-Express to SATA RAID Controller + 1260 ARC-1260 16-Port PCI-Express to SATA RAID Controller +17d5 S2io Inc. + 5831 Xframe 10 Gigabit Ethernet PCI-X + 103c 12d5 PCI-X 133MHz 10GbE SR Fiber + 10a9 8020 Single Port 10 Gigabit Ethernet (PCI-X, Fiber) + 10a9 8024 Single Port 10 Gigabit Ethernet (PCI-X, Fiber) + 5832 Xframe II 10Gbps Ethernet + 10a9 8021 Single Port 10 Gigabit Ethernet II (PCI-X, Fiber) +17db Cray Inc +17de KWorld Computer Co. Ltd. +17e4 Sectra AB + 0001 KK671 Cardbus encryption board + 0002 KK672 Cardbus encryption board +17e6 Entropic Communications Inc. + 0010 EN2010 [c.Link] MoCA Network Controller (Coax, PCI interface) + 0011 EN2010 [c.Link] MoCA Network Controller (Coax, MPEG interface) + 0021 EN2210 [c.Link] MoCA Network Controller (Coax) +17ee Connect Components Ltd +17f2 Albatron Corp. +17fe Linksys, A Division of Cisco Systems + 2120 WMP11v4 802.11b PCI card + 2220 [AirConn] INPROCOMM IPN 2220 Wireless LAN Adapter (rev 01) + 17fe 2220 WPC54G ver. 4 +17ff Benq Corporation +1809 Lumanate, Inc. +1813 Ambient Technologies Inc + 4000 HaM controllerless modem + 16be 0001 V9x HAM Data Fax Modem + 4100 HaM plus Data Fax Modem + 16be 0002 V9x HAM 1394 +1814 RaLink + 0101 Wireless PCI Adapter RT2400 / RT2460 + 1043 0127 WiFi-b add-on Card + 1462 6828 PC11B2 (MS-6828) Wireless 11b PCI Card + 0200 RT2500 802.11g PCI [PC54G2] + 0201 RT2500 802.11g Cardbus/mini-PCI + 1043 130f WL-130g + 1371 001e CWC-854 Wireless-G CardBus Adapter + 1371 001f CWM-854 Wireless-G Mini PCI Adapter + 1371 0020 CWP-854 Wireless-G PCI Adapter + 1458 e381 GN-WMKG 802.11b/g Wireless CardBus Adapter + 1458 e931 GN-WIKG 802.11b/g mini-PCI Adapter + 1462 6835 Wireless 11G CardBus CB54G2 + 1737 0032 WMP54G 2.0 PCI Adapter + 1799 700a F5D7000 Wireless G Desktop Network Card + 1799 701a F5D7010 Wireless G Notebook Network Card + 185f 22a0 CN-WF513 Wireless Cardbus Adapter + 0301 RT2561/RT61 802.11g PCI + 1186 3c08 DWL-G630 Rev E + 1186 3c09 DWL-G510 Rev C + 1737 0055 WMP54G ver 4.1 + 0302 RT2561/RT61 rev B 802.11g + 1186 3c08 DWL-G630 Rev E + 1186 3c09 DWL-G510 Rev C + 0401 Ralink RT2600 802.11 MIMO +1820 InfiniCon Systems Inc. +1822 Twinhan Technology Co. Ltd + 4e35 Mantis DTV PCI Bridge Controller [Ver 1.0] +182d SiteCom Europe BV +# HFC-based ISDN card + 3069 ISDN PCI DC-105V2 + 9790 WL-121 Wireless Network Adapter 100g+ [Ver.3] +182e Raza Microelectronics, Inc. + 0008 XLR516 Processor +1830 Credence Systems Corporation +183b MikroM GmbH + 08a7 MVC100 DVI + 08a8 MVC101 SDI + 08a9 MVC102 DVI+Audio + 08b0 MVC200-DC +1849 ASRock Incorporation +184a Thales Computers +1851 Microtune, Inc. +1852 Anritsu Corp. +1853 SMSC Automotive Infotainment System Group +1854 LG Electronics, Inc. +185b Compro Technology, Inc. +185f Wistron NeWeb Corp. +1864 SilverBack + 2110 ISNAP 2110 +1867 Topspin Communications + 5a44 MT23108 InfiniHost HCA + 5a45 MT23108 InfiniHost HCA flash recovery + 5a46 MT23108 InfiniHost HCA bridge + 6278 MT25208 InfiniHost III Ex (Tavor compatibility mode) + 6282 MT25208 InfiniHost III Ex +187e ZyXEL Communication Corporation + 3403 ZyAir G-110 802.11g + 340e M-302 802.11g XtremeMIMO +1885 Avvida Systems Inc. +1888 Varisys Ltd + 0301 VMFX1 FPGA PMC module + 0601 VSM2 dual PMC carrier + 0710 VS14x series PowerPC PCI board + 0720 VS24x series PowerPC PCI board +188a Ample Communications, Inc +1890 Egenera, Inc. +1894 KNC One +1896 B&B Electronics Manufacturing Company, Inc. +18a1 Astute Networks Inc. +18ac DViCO Corporation + d500 FusionHDTV 5 + d800 FusionHDTV 3 Gold + d810 FusionHDTV 3 Gold-Q + d820 FusionHDTV 3 Gold-T +18b8 Ammasso + b001 AMSO 1100 iWARP/RDMA Gigabit Ethernet Coprocessor +18bc Info-Tek Corp. +18c3 Micronas Semiconductor Holding AG +# Nee Octigabay System +18c8 Cray Inc +18c9 ARVOO Engineering BV +18ca XGI - Xabre Graphics Inc + 0020 Volari Z7 + 0040 Volari V3XT/V5/V8 +18d2 Sitecom +# Sitecom HFC-S based ISDN controller card DC-105v2 + 3069 DC-105v2 ISDN controller +18dd Artimi Inc + 4c6f Artimi RTMI-100 UWB adapter +18e6 MPL AG + 0001 OSCI [Octal Serial Communication Interface] +18ec Cesnet, z.s.p.o. + c006 COMBO6 + 18ec d001 COMBO-4MTX + 18ec d002 COMBO-4SFP + 18ec d003 COMBO-4SFPRO + 18ec d004 COMBO-2XFP + c045 COMBO6E + c050 COMBO-PTM + c058 COMBO6X + 18ec d001 COMBO-4MTX + 18ec d002 COMBO-4SFP + 18ec d003 COMBO-4SFPRO + 18ec d004 COMBO-2XFP +18f6 NextIO + 1000 [Nexsis] Switch Virtual P2P PCIe Bridge + 1050 [Nexsis] Switch Virtual P2P PCI Bridge + 2000 [Nexsis] Switch Integrated Mgmt. Endpoint +18f7 Commtech, Inc. + 0001 Fastcom ESCC-PCI-335 + 0002 Fastcom 422/4-PCI-335 + 0004 Fastcom 422/2-PCI-335 + 0005 Fastcom IGESCC-PCI-ISO/1 + 000a Fastcom 232/4-PCI-335 +18fb Resilience Corporation +1904 Hangzhou Silan Microelectronics Co., Ltd. + 8139 RTL8139D [Realtek] PCI 10/100BaseTX ethernet adaptor +1923 Sangoma Technologies Corp. + 0040 A200/Remora FXO/FXS Analog AFT card + 0100 A104d QUAD T1/E1 AFT card + 0300 A101 single-port T1/E1 + 0400 A104u Quad T1/E1 AFT +1924 Level 5 Networks Inc. +192e TransDimension +1931 Option N.V. + 000c Qualcomm MSM6275 UMTS chip +1942 ClearSpeed Technology plc + e511 CSX600 Advance Accelerator Board +194a DapTechnology B.V. + 1111 FireSpy3850 + 1112 FireSpy450b + 1113 FireSpy450bT + 1114 FireSpy850 + 1115 FireSpy850bT +1957 Freescale Semiconductor Inc + 0012 MPC8548 [PowerQUICC III] + 0080 MPC8349E + 0081 MPC8349 + 0082 MPC8347E TBGA + 0083 MPC8347 TBGA + 0084 MPC8347E PBGA + 0085 MPC8347 PBGA + 0086 MPC8343E + 0087 MPC8343 +1958 Faster Technology, LLC. +1966 Orad Hi-Tec Systems + 1975 DVG64 family +1969 Attansic Technology Corp. + 1048 L1 Gigabit Ethernet Adapter +196a Sensory Networks Inc. + 0101 NodalCore C-1000 Content Classification Accelerator + 0102 NodalCore C-2000 Content Classification Accelerator +196d Club-3D BV +197b JMicron Technologies, Inc. + 2360 JMicron 20360/20363 AHCI Controller + 2361 JMB361 AHCI/IDE + 2363 JMicron 20360/20363 AHCI Controller + 2365 JMB365 AHCI/IDE + 2366 JMB366 AHCI/IDE +1989 Montilio Inc. + 0001 RapidFile Bridge + 8001 RapidFile +1993 Innominate Security Technologies AG +199a Pulse-LINK, Inc. +19a8 DAQDATA GmbH +19ac Kasten Chase Applied Research + 0001 ACA2400 Crypto Accelerator +19ae Progeny Systems Corporation + 0520 4135 HFT Interface Controller +19d4 Quixant Limited +19e2 Vector Informatik GmbH +19e7 NET (Network Equipment Technologies) + 1001 STIX DSP Card + 1002 STIX - 1 Port T1/E1 Card + 1003 STIX - 2 Port T1/E1 Card + 1004 STIX - 4 Port T1/E1 Card + 1005 STIX - 4 Port FXS Card +1a03 ASPEED Technology, Inc. + 2000 AST2000 +1a08 Sierra semiconductor + 0000 SC15064 +1a1d GFaI e.V. +1a29 Fortinet, Inc. +1a51 Hectronic AB +1b13 Jaton Corp +1c1c Symphony + 0001 82C101 +1d44 DPT + a400 PM2x24/PM3224 +1de1 Tekram Technology Co.,Ltd. + 0391 TRM-S1040 + 2020 DC-390 + 690c 690c + dc29 DC290 +1fc0 Tumsan Oy + 0300 E2200 Dual E1/Rawpipe Card +1fc1 PathScale, Inc + 000d InfiniPath HT-400 + 0010 InfiniPath PE-800 +1fce Cognio Inc. + 0001 Spectrum Analyzer PC Card (SAgE) +2000 Smart Link Ltd. +2001 Temporal Research Ltd +2003 Smart Link Ltd. +2004 Smart Link Ltd. +21c3 21st Century Computer Corp. +# (Probably only the Mobile Phone Division) +22b8 Motorola, Inc. +2348 Racore + 2010 8142 100VG/AnyLAN +2646 Kingston Technologies +270b Xantel Corporation +270f Chaintech Computer Co. Ltd +2711 AVID Technology Inc. +2a15 3D Vision(???) +3000 Hansol Electronics Inc. +3142 Post Impression Systems. +3388 Hint Corp + 0013 HiNT HC4 PCI to ISDN bridge, Multimedia audio controller + 0014 HiNT HC4 PCI to ISDN bridge, Network controller + 0020 HB6 Universal PCI-PCI bridge (transparent mode) + 0021 HB6 Universal PCI-PCI bridge (non-transparent mode) + 1775 ce90 CE9 + 4c53 1050 CT7 mainboard + 4c53 1080 CT8 mainboard + 4c53 1090 Cx9 mainboard + 4c53 10a0 CA3/CR3 mainboard + 4c53 3010 PPCI mezzanine (32-bit PMC) + 4c53 3011 PPCI mezzanine (64-bit PMC) + 4c53 4000 PMCCARR1 carrier board + 0022 HiNT HB4 PCI-PCI Bridge (PCI6150) + 0026 HB2 PCI-PCI Bridge + 101a E.Band [AudioTrak Inca88] + 101b E.Band [AudioTrak Inca88] + 8011 VXPro II Chipset + 3388 8011 VXPro II Chipset CPU to PCI Bridge + 8012 VXPro II Chipset + 3388 8012 VXPro II Chipset PCI to ISA Bridge + 8013 VXPro II IDE + 3388 8013 VXPro II Chipset EIDE Controller +3411 Quantum Designs (H.K.) Inc +3513 ARCOM Control Systems Ltd +3842 eVga.com. Corp. + c370 e-GeFORCE 6600 256 DDR PCI-e +38ef 4Links +3d3d 3DLabs + 0001 GLINT 300SX + 0002 GLINT 500TX + 0000 0000 GLoria L + 0003 GLINT Delta + 0000 0000 GLoria XL + 0004 Permedia + 0005 Permedia + 0006 GLINT MX + 0000 0000 GLoria XL + 1048 0a42 GLoria XXL + 0007 3D Extreme + 0008 GLINT Gamma G1 + 1048 0a42 GLoria XXL + 0009 Permedia II 2D+3D + 1040 0011 AccelStar II + 1048 0a42 GLoria XXL + 13e9 1000 6221L-4U + 3d3d 0100 AccelStar II 3D Accelerator + 3d3d 0111 Permedia 3:16 + 3d3d 0114 Santa Ana + 3d3d 0116 Oxygen GVX1 + 3d3d 0119 Scirocco + 3d3d 0120 Santa Ana PCL + 3d3d 0125 Oxygen VX1 + 3d3d 0127 Permedia3 Create! + 000a GLINT R3 + 3d3d 0121 Oxygen VX1 + 000c GLINT R3 [Oxygen VX1] + 3d3d 0144 Oxygen VX1-4X AGP [Permedia 4] + 000d GLint R4 rev A + 0011 GLint R4 rev B + 0012 GLint R5 rev A + 0013 GLint R5 rev B + 0020 VP10 visual processor + 0022 VP10 visual processor + 0024 VP9 visual processor + 0100 Permedia II 2D+3D + 07a1 Wildcat III 6210 + 07a2 Sun XVR-500 Graphics Accelerator + 07a3 Wildcat IV 7210 + 1004 Permedia + 3d04 Permedia + ffff Glint VGA +4005 Avance Logic Inc. + 0300 ALS300 PCI Audio Device + 0308 ALS300+ PCI Audio Device + 0309 PCI Input Controller + 1064 ALG-2064 + 2064 ALG-2064i + 2128 ALG-2364A GUI Accelerator + 2301 ALG-2301 + 2302 ALG-2302 + 2303 AVG-2302 GUI Accelerator + 2364 ALG-2364A + 2464 ALG-2464 + 2501 ALG-2564A/25128A + 4000 ALS4000 Audio Chipset + 4005 4000 ALS4000 Audio Chipset + 4710 ALC200/200P +4033 Addtron Technology Co, Inc. + 1360 RTL8139 Ethernet +4143 Digital Equipment Corp +4144 Alpha Data + 0044 ADM-XRCIIPro +416c Aladdin Knowledge Systems + 0100 AladdinCARD + 0200 CPC +4321 Tata Power Strategic Electronics Division +4444 Internext Compression Inc + 0016 iTVC16 (CX23416) MPEG-2 Encoder + 0070 0003 WinTV PVR 250 + 0070 0009 WinTV PVR 150 + 0070 0801 WinTV PVR 150 + 0070 0807 WinTV PVR 150 + 0070 4001 WinTV PVR 250 + 0070 4009 WinTV PVR 250 + 0070 4801 WinTV PVR 250 + 0070 4803 WinTV PVR 250 + 0070 8003 WinTV PVR 150 + 0070 8801 WinTV PVR 150 + 0070 c801 WinTV PVR 150 + 0070 e807 WinTV PVR 500 (1st unit) + 0070 e817 WinTV PVR 500 (2nd unit) + 0070 ff92 WiNTV PVR-550 + 0270 0801 WinTV PVR 150 + 10fc d038 GV-MVP/RX2W (1st unit) + 10fc d039 GV-MVP/RX2W (2nd unit) + 12ab fff3 MPG600 + 12ab ffff MPG600 + 1461 c019 UltraTV 1500 MCE + 9005 0092 VideOh! AVC-2010 + 9005 0093 VideOh! AVC-2410 + 0803 iTVC15 MPEG-2 Encoder + 0070 4000 WinTV PVR-350 + 0070 4001 WinTV PVR-250 + 0070 4800 WinTV PVR-350 (V1) + 12ab 0000 MPG160 + 1461 a3ce M179 + 1461 a3cf M179 +4468 Bridgeport machines +4594 Cogetec Informatique Inc +45fb Baldor Electric Company +4680 Umax Computer Corp +4843 Hercules Computer Technology Inc +4916 RedCreek Communications Inc + 1960 RedCreek PCI adapter +4943 Growth Networks +494f ACCES I/O Products, Inc. + 10e8 LPCI-COM-8SM +4978 Axil Computer Inc +4a14 NetVin + 5000 NV5000SC + 4a14 5000 RT8029-Based Ethernet Adapter +4b10 Buslogic Inc. +4c48 LUNG HWA Electronics +4c53 SBS Technologies + 0000 PLUSTEST device + 4c53 3000 PLUSTEST card (PC104+) + 4c53 3001 PLUSTEST card (PMC) + 0001 PLUSTEST-MM device + 4c53 3002 PLUSTEST-MM card (PMC) +4ca1 Seanix Technology Inc +4d51 MediaQ Inc. + 0200 MQ-200 +4d54 Microtechnica Co Ltd +4ddc ILC Data Device Corp + 0100 DD-42924I5-300 (ARINC 429 Data Bus) + 0801 BU-65570I1 MIL-STD-1553 Test and Simulation + 0802 BU-65570I2 MIL-STD-1553 Test and Simulation + 0811 BU-65572I1 MIL-STD-1553 Test and Simulation + 0812 BU-65572I2 MIL-STD-1553 Test and Simulation + 0881 BU-65570T1 MIL-STD-1553 Test and Simulation + 0882 BU-65570T2 MIL-STD-1553 Test and Simulation + 0891 BU-65572T1 MIL-STD-1553 Test and Simulation + 0892 BU-65572T2 MIL-STD-1553 Test and Simulation + 0901 BU-65565C1 MIL-STD-1553 Data Bus + 0902 BU-65565C2 MIL-STD-1553 Data Bus + 0903 BU-65565C3 MIL-STD-1553 Data Bus + 0904 BU-65565C4 MIL-STD-1553 Data Bus + 0b01 BU-65569I1 MIL-STD-1553 Data Bus + 0b02 BU-65569I2 MIL-STD-1553 Data Bus + 0b03 BU-65569I3 MIL-STD-1553 Data Bus + 0b04 BU-65569I4 MIL-STD-1553 Data Bus +5046 GemTek Technology Corporation + 1001 PCI Radio +5053 Voyetra Technologies + 2010 Daytona Audio Adapter +5136 S S Technologies +5143 Qualcomm Inc +5145 Ensoniq (Old) + 3031 Concert AudioPCI +5168 Animation Technologies Inc. + 0300 FlyDVB-S + 0301 FlyDVB-T +5301 Alliance Semiconductor Corp. + 0001 ProMotion aT3D +5333 S3 Inc. + 0551 Plato/PX (system) + 5631 86c325 [ViRGE] + 8800 86c866 [Vision 866] + 8801 86c964 [Vision 964] + 8810 86c764_0 [Trio 32 vers 0] + 8811 86c764/765 [Trio32/64/64V+] + 8812 86cM65 [Aurora64V+] + 8813 86c764_3 [Trio 32/64 vers 3] + 8814 86c767 [Trio 64UV+] + 8815 86cM65 [Aurora 128] + 883d 86c988 [ViRGE/VX] + 8870 FireGL + 8880 86c868 [Vision 868 VRAM] vers 0 + 8881 86c868 [Vision 868 VRAM] vers 1 + 8882 86c868 [Vision 868 VRAM] vers 2 + 8883 86c868 [Vision 868 VRAM] vers 3 + 88b0 86c928 [Vision 928 VRAM] vers 0 + 88b1 86c928 [Vision 928 VRAM] vers 1 + 88b2 86c928 [Vision 928 VRAM] vers 2 + 88b3 86c928 [Vision 928 VRAM] vers 3 + 88c0 86c864 [Vision 864 DRAM] vers 0 + 88c1 86c864 [Vision 864 DRAM] vers 1 + 88c2 86c864 [Vision 864-P DRAM] vers 2 + 88c3 86c864 [Vision 864-P DRAM] vers 3 + 88d0 86c964 [Vision 964 VRAM] vers 0 + 88d1 86c964 [Vision 964 VRAM] vers 1 + 88d2 86c964 [Vision 964-P VRAM] vers 2 + 88d3 86c964 [Vision 964-P VRAM] vers 3 + 88f0 86c968 [Vision 968 VRAM] rev 0 + 88f1 86c968 [Vision 968 VRAM] rev 1 + 88f2 86c968 [Vision 968 VRAM] rev 2 + 88f3 86c968 [Vision 968 VRAM] rev 3 + 8900 86c755 [Trio 64V2/DX] + 5333 8900 86C775 Trio64V2/DX + 8901 86c775/86c785 [Trio 64V2/DX or /GX] + 5333 8901 86C775 Trio64V2/DX, 86C785 Trio64V2/GX + 8902 Plato/PX + 8903 Trio 3D business multimedia + 8904 Trio 64 3D + 1014 00db Integrated Trio3D + 5333 8904 86C365 Trio3D AGP + 8905 Trio 64V+ family + 8906 Trio 64V+ family + 8907 Trio 64V+ family + 8908 Trio 64V+ family + 8909 Trio 64V+ family + 890a Trio 64V+ family + 890b Trio 64V+ family + 890c Trio 64V+ family + 890d Trio 64V+ family + 890e Trio 64V+ family + 890f Trio 64V+ family + 8a01 ViRGE/DX or /GX + 0e11 b032 ViRGE/GX + 10b4 1617 Nitro 3D + 10b4 1717 Nitro 3D + 5333 8a01 ViRGE/DX + 8a10 ViRGE/GX2 + 1092 8a10 Stealth 3D 4000 + 8a13 86c368 [Trio 3D/2X] + 5333 8a13 Trio3D/2X + 8a20 86c794 [Savage 3D] + 5333 8a20 86C391 Savage3D + 8a21 86c390 [Savage 3D/MV] + 5333 8a21 86C390 Savage3D/MV + 8a22 Savage 4 + 1033 8068 Savage 4 + 1033 8069 Savage 4 + 1033 8110 Savage 4 LT + 105d 0018 SR9 8Mb SDRAM + 105d 002a SR9 Pro 16Mb SDRAM + 105d 003a SR9 Pro 32Mb SDRAM + 105d 092f SR9 Pro+ 16Mb SGRAM + 1092 4207 Stealth III S540 + 1092 4800 Stealth III S540 + 1092 4807 SpeedStar A90 + 1092 4808 Stealth III S540 + 1092 4809 Stealth III S540 + 1092 480e Stealth III S540 + 1092 4904 Stealth III S520 + 1092 4905 SpeedStar A200 + 1092 4a09 Stealth III S540 + 1092 4a0b Stealth III S540 Xtreme + 1092 4a0f Stealth III S540 + 1092 4e01 Stealth III S540 + 1102 101d 3d Blaster Savage 4 + 1102 101e 3d Blaster Savage 4 + 5333 8100 86C394-397 Savage4 SDRAM 100 + 5333 8110 86C394-397 Savage4 SDRAM 110 + 5333 8125 86C394-397 Savage4 SDRAM 125 + 5333 8143 86C394-397 Savage4 SDRAM 143 + 5333 8a22 86C394-397 Savage4 + 5333 8a2e 86C394-397 Savage4 32bit + 5333 9125 86C394-397 Savage4 SGRAM 125 + 5333 9143 86C394-397 Savage4 SGRAM 143 + 8a23 Savage 4 + 8a25 ProSavage PM133 + 8a26 ProSavage KM133 + 8c00 ViRGE/M3 + 8c01 ViRGE/MX + 1179 0001 ViRGE/MX + 8c02 ViRGE/MX+ + 8c03 ViRGE/MX+MV + 8c10 86C270-294 Savage/MX-MV + 8c11 82C270-294 Savage/MX + 8c12 86C270-294 Savage/IX-MV + 1014 017f Thinkpad T20/T22 + 1179 0001 86C584 SuperSavage/IXC Toshiba + 8c13 86C270-294 Savage/IX + 1179 0001 Magnia Z310 + 8c22 SuperSavage MX/128 + 8c24 SuperSavage MX/64 + 8c26 SuperSavage MX/64C + 8c2a SuperSavage IX/128 SDR + 8c2b SuperSavage IX/128 DDR + 8c2c SuperSavage IX/64 SDR + 8c2d SuperSavage IX/64 DDR + 8c2e SuperSavage IX/C SDR + 1014 01fc ThinkPad T23 (2647-4MG) + 8c2f SuperSavage IX/C DDR + 8d01 86C380 [ProSavageDDR K4M266] + 8d02 VT8636A [ProSavage KN133] AGP4X VGA Controller (TwisterK) + 8d03 VT8751 [ProSavageDDR P4M266] + 8d04 VT8375 [ProSavage8 KM266/KL266] + 9102 86C410 Savage 2000 + 1092 5932 Viper II Z200 + 1092 5934 Viper II Z200 + 1092 5952 Viper II Z200 + 1092 5954 Viper II Z200 + 1092 5a35 Viper II Z200 + 1092 5a37 Viper II Z200 + 1092 5a55 Viper II Z200 + 1092 5a57 Viper II Z200 + ca00 SonicVibes +544c Teralogic Inc + 0350 TL880-based HDTV/ATSC tuner +5455 Technische University Berlin + 4458 S5933 +5519 Cnet Technologies, Inc. +5544 Dunord Technologies + 0001 I-30xx Scanner Interface +5555 Genroco, Inc + 0003 TURBOstor HFP-832 [HiPPI NIC] +5654 VoiceTronix Pty Ltd + 3132 OpenSwitch12 +5700 Netpower +5851 Exacq Technologies +6356 UltraStor +6374 c't Magazin fuer Computertechnik + 6773 GPPCI +6409 Logitec Corp. +6666 Decision Computer International Co. + 0001 PCCOM4 + 0002 PCCOM8 + 0004 PCCOM2 + 0101 PCI 8255/8254 I/O Card +7063 pcHDTV + 2000 HD-2000 + 3000 HD-3000 + 5500 HD5500 HDTV +7604 O.N. Electronic Co Ltd. +7bde MIDAC Corporation +7fed PowerTV +8008 Quancom Electronic GmbH + 0010 WDOG1 [PCI-Watchdog 1] + 0011 PWDOG2 [PCI-Watchdog 2] +# Wrong ID used in subsystem ID of AsusTek PCI-USB2 PCI card. +807d Asustek Computer, Inc. +8086 Intel Corporation + 0007 82379AB + 0008 Extended Express System Support Controller + 0039 21145 Fast Ethernet + 0122 82437FX + 0309 80303 I/O Processor PCI-to-PCI Bridge + 030d 80312 I/O Companion Chip PCI-to-PCI Bridge + 0326 6700/6702PXH I/OxAPIC Interrupt Controller A + 0327 6700PXH I/OxAPIC Interrupt Controller B + 0329 6700PXH PCI Express-to-PCI Bridge A + 032a 6700PXH PCI Express-to-PCI Bridge B + 032c 6702PXH PCI Express-to-PCI Bridge A + 0330 80332 [Dobson] I/O processor (A-Segment Bridge) + 0331 80332 [Dobson] I/O processor (A-Segment IOAPIC) + 0332 80332 [Dobson] I/O processor (B-Segment Bridge) + 0333 80332 [Dobson] I/O processor (B-Segment IOAPIC) + 0334 80332 [Dobson] I/O processor (ATU) + 0335 80331 [Lindsay] I/O processor (PCI-X Bridge) + 0336 80331 [Lindsay] I/O processor (ATU) + 0340 41210 [Lanai] Serial to Parallel PCI Bridge (A-Segment Bridge) + 0341 41210 [Lanai] Serial to Parallel PCI Bridge (B-Segment Bridge) + 0370 80333 Segment-A PCI Express-to-PCI Express Bridge + 0371 80333 A-Bus IOAPIC + 0372 80333 Segment-B PCI Express-to-PCI Express Bridge + 0373 80333 B-Bus IOAPIC + 0374 80333 Address Translation Unit + 0482 82375EB/SB PCI to EISA Bridge + 0483 82424TX/ZX [Saturn] CPU to PCI bridge + 0484 82378ZB/IB, 82379AB (SIO, SIO.A) PCI to ISA Bridge + 0486 82425EX/ZX [Aries] PCIset with ISA bridge + 04a3 82434LX/NX [Mercury/Neptune] Processor to PCI bridge + 04d0 82437FX [Triton FX] + 0500 E8870 Processor bus control + 0501 E8870 Memory controller +# and registers common to both SPs + 0502 E8870 Scalability Port 0 +# and global performance monitoring + 0503 E8870 Scalability Port 1 + 0510 E8870IO Hub Interface Port 0 registers (8-bit compatibility port) + 0511 E8870IO Hub Interface Port 1 registers + 0512 E8870IO Hub Interface Port 2 registers + 0513 E8870IO Hub Interface Port 3 registers + 0514 E8870IO Hub Interface Port 4 registers + 0515 E8870IO General SIOH registers + 0516 E8870IO RAS registers + 0530 E8870SP Scalability Port 0 registers + 0531 E8870SP Scalability Port 1 registers + 0532 E8870SP Scalability Port 2 registers + 0533 E8870SP Scalability Port 3 registers + 0534 E8870SP Scalability Port 4 registers + 0535 E8870SP Scalability Port 5 registers +# (bi-interleave 0) and global registers that are neither per-port nor per-interleave + 0536 E8870SP Interleave registers 0 and 1 +# (bi-interleave 1) + 0537 E8870SP Interleave registers 2 and 3 + 0600 RAID Controller + 8086 01af SRCZCR + 8086 01c1 ICP Vortex GDT8546RZ + 8086 01f7 SCRU32 +# uninitialized SRCU32 RAID Controller + 061f 80303 I/O Processor + 0960 80960RP [i960 RP Microprocessor/Bridge] + 0962 80960RM [i960RM Bridge] + 0964 80960RP [i960 RP Microprocessor/Bridge] + 1000 82542 Gigabit Ethernet Controller + 0e11 b0df NC1632 Gigabit Ethernet Adapter (1000-SX) + 0e11 b0e0 NC1633 Gigabit Ethernet Adapter (1000-LX) + 0e11 b123 NC1634 Gigabit Ethernet Adapter (1000-SX) + 1014 0119 Netfinity Gigabit Ethernet SX Adapter + 8086 1000 PRO/1000 Gigabit Server Adapter + 1001 82543GC Gigabit Ethernet Controller (Fiber) + 0e11 004a NC6136 Gigabit Server Adapter + 1014 01ea Netfinity Gigabit Ethernet SX Adapter + 8086 1002 PRO/1000 F Server Adapter + 8086 1003 PRO/1000 F Server Adapter + 1002 Pro 100 LAN+Modem 56 Cardbus II + 8086 200e Pro 100 LAN+Modem 56 Cardbus II + 8086 2013 Pro 100 SR Mobile Combo Adapter + 8086 2017 Pro 100 S Combo Mobile Adapter + 1004 82543GC Gigabit Ethernet Controller (Copper) + 0e11 0049 NC7132 Gigabit Upgrade Module + 0e11 b1a4 NC7131 Gigabit Server Adapter + 1014 10f2 Gigabit Ethernet Server Adapter + 8086 1004 PRO/1000 T Server Adapter + 8086 2004 PRO/1000 T Server Adapter + 1008 82544EI Gigabit Ethernet Controller (Copper) + 1014 0269 iSeries 1000/100/10 Ethernet Adapter + 1028 011c PRO/1000 XT Network Connection + 8086 1107 PRO/1000 XT Server Adapter + 8086 2107 PRO/1000 XT Server Adapter + 8086 2110 PRO/1000 XT Desktop Adapter + 8086 3108 PRO/1000 XT Network Connection + 1009 82544EI Gigabit Ethernet Controller (Fiber) + 1014 0268 iSeries Gigabit Ethernet Adapter + 8086 1109 PRO/1000 XF Server Adapter + 8086 2109 PRO/1000 XF Server Adapter + 100a 82540EM Gigabit Ethernet Controller + 100c 82544GC Gigabit Ethernet Controller (Copper) + 8086 1112 PRO/1000 T Desktop Adapter + 8086 2112 PRO/1000 T Desktop Adapter + 100d 82544GC Gigabit Ethernet Controller (LOM) + 1028 0123 PRO/1000 XT Network Connection + 1079 891f 82544GC Based Network Connection + 4c53 1080 CT8 mainboard + 8086 110d 82544GC Based Network Connection + 100e 82540EM Gigabit Ethernet Controller + 1014 0265 PRO/1000 MT Network Connection + 1014 0267 PRO/1000 MT Network Connection + 1014 026a PRO/1000 MT Network Connection + 1028 002e Optiplex GX260 + 1028 0134 PowerEdge 600SC + 1028 0151 PRO/1000 MT Network Connection + 107b 8920 PRO/1000 MT Desktop Adapter + 8086 001e PRO/1000 MT Desktop Adapter + 8086 002e PRO/1000 MT Desktop Adapter + 8086 1376 PRO/1000 GT Desktop Adapter + 8086 1476 PRO/1000 GT Desktop Adapter + 100f 82545EM Gigabit Ethernet Controller (Copper) + 1014 0269 iSeries 1000/100/10 Ethernet Adapter + 1014 028e PRO/1000 MT Network Connection + 8086 1000 PRO/1000 MT Network Connection + 8086 1001 PRO/1000 MT Server Adapter + 1010 82546EB Gigabit Ethernet Controller (Copper) + 0e11 00db NC7170 Gigabit Server Adapter + 1014 027c PRO/1000 MT Dual Port Network Adapter + 18fb 7872 RESlink-X + 1fc1 0026 Niagara 2260 Bypass Card + 4c53 1080 CT8 mainboard + 4c53 10a0 CA3/CR3 mainboard + 8086 1011 PRO/1000 MT Dual Port Server Adapter + 8086 1012 PRO/1000 MT Dual Port Server Adapter + 8086 101a PRO/1000 MT Dual Port Network Connection + 8086 3424 SE7501HG2 Mainboard + 1011 82545EM Gigabit Ethernet Controller (Fiber) + 1014 0268 iSeries Gigabit Ethernet Adapter + 8086 1002 PRO/1000 MF Server Adapter + 8086 1003 PRO/1000 MF Server Adapter (LX) + 1012 82546EB Gigabit Ethernet Controller (Fiber) + 0e11 00dc NC6170 Gigabit Server Adapter + 8086 1012 PRO/1000 MF Dual Port Server Adapter + 1013 82541EI Gigabit Ethernet Controller + 8086 0013 PRO/1000 MT Network Connection + 8086 1013 PRO/1000 MT Network Connection + 8086 1113 PRO/1000 MT Desktop Adapter + 1014 82541ER Gigabit Ethernet Controller + 8086 0014 PRO/1000 MT Desktop Connection + 8086 1014 PRO/1000 MT Network Connection + 1015 82540EM Gigabit Ethernet Controller (LOM) + 8086 1015 PRO/1000 MT Mobile Connection + 1016 82540EP Gigabit Ethernet Controller (Mobile) + 1014 052c PRO/1000 MT Mobile Connection + 1179 0001 PRO/1000 MT Mobile Connection + 8086 1016 PRO/1000 MT Mobile Connection + 1017 82540EP Gigabit Ethernet Controller + 8086 1017 PR0/1000 MT Desktop Connection + 1018 82541EI Gigabit Ethernet Controller + 8086 1018 PRO/1000 MT Mobile Connection + 1019 82547EI Gigabit Ethernet Controller + 1458 1019 GA-8IPE1000 Pro2 motherboard (865PE) + 1458 e000 Intel Gigabit Ethernet (Kenai II) + 8086 1019 PRO/1000 CT Desktop Connection + 8086 301f D865PERL mainboard + 8086 302c Intel 82865G Mainboard (D865GBF) + 8086 3427 S875WP1-E mainboard + 101a 82547EI Gigabit Ethernet Controller (Mobile) + 8086 101a PRO/1000 CT Mobile Connection + 101d 82546EB Gigabit Ethernet Controller + 8086 1000 PRO/1000 MT Quad Port Server Adapter + 101e 82540EP Gigabit Ethernet Controller (Mobile) + 1014 0549 PRO/1000 MT Mobile Connection + 1179 0001 PRO/1000 MT Mobile Connection + 8086 101e PRO/1000 MT Mobile Connection + 1026 82545GM Gigabit Ethernet Controller + 1028 0169 Precision 470 + 8086 1000 PRO/1000 MT Server Connection + 8086 1001 PRO/1000 MT Server Adapter + 8086 1002 PRO/1000 MT Server Adapter + 8086 1003 PRO/1000 GT Server Adapter + 8086 1026 PRO/1000 MT Server Connection + 1027 82545GM Gigabit Ethernet Controller + 103c 3103 NC310F PCI-X Gigabit Server Adapter + 8086 1001 PRO/1000 MF Server Adapter(LX) + 8086 1002 PRO/1000 MF Server Adapter(LX) + 8086 1003 PRO/1000 MF Server Adapter(LX) + 8086 1027 PRO/1000 MF Server Adapter + 1028 82545GM Gigabit Ethernet Controller + 8086 1028 PRO/1000 MB Server Connection + 1029 82559 Ethernet Controller + 1030 82559 InBusiness 10/100 + 1031 82801CAM (ICH3) PRO/100 VE (LOM) Ethernet Controller + 1014 0209 ThinkPad A/T/X Series + 104d 80e7 Vaio PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP + 104d 813c Vaio PCG-GRV616G + 107b 5350 EtherExpress PRO/100 VE + 1179 0001 EtherExpress PRO/100 VE + 144d c000 EtherExpress PRO/100 VE + 144d c001 EtherExpress PRO/100 VE + 144d c003 EtherExpress PRO/100 VE + 144d c006 vpr Matrix 170B4 + 1032 82801CAM (ICH3) PRO/100 VE Ethernet Controller + 1033 82801CAM (ICH3) PRO/100 VM (LOM) Ethernet Controller + 1034 82801CAM (ICH3) PRO/100 VM Ethernet Controller + 1035 82801CAM (ICH3)/82562EH (LOM) Ethernet Controller + 1036 82801CAM (ICH3) 82562EH Ethernet Controller + 1037 82801CAM (ICH3) Chipset Ethernet Controller + 1038 82801CAM (ICH3) PRO/100 VM (KM) Ethernet Controller + 0e11 0098 Evo N600c + 1039 82801DB PRO/100 VE (LOM) Ethernet Controller + 1014 0267 NetVista A30p + 103a 82801DB PRO/100 VE (CNR) Ethernet Controller + 103b 82801DB PRO/100 VM (LOM) Ethernet Controller + 103c 82801DB PRO/100 VM (CNR) Ethernet Controller + 103d 82801DB PRO/100 VE (MOB) Ethernet Controller + 1014 0522 Thinkpad R50e model 1634 + 103e 82801DB PRO/100 VM (MOB) Ethernet Controller + 1040 536EP Data Fax Modem + 16be 1040 V.9X DSP Data Fax Modem + 1043 PRO/Wireless LAN 2100 3B Mini PCI Adapter + 103c 08b0 tc1100 tablet + 8086 2527 MIM2000/Centrino + 1048 PRO/10GbE LR Server Adapter + 8086 a01f PRO/10GbE LR Server Adapter + 8086 a11f PRO/10GbE LR Server Adapter + 1049 82566MM Gigabit Network Connection + 104a 82566DM Gigabit Network Connection + 104b 82566DC Gigabit Network Connection + 104c 82562V 10/100 Network Connection + 104d 82566MC Gigabit Network Connection + 1050 82562EZ 10/100 Ethernet Controller + 1462 728c 865PE Neo2 (MS-6728) + 1462 758c MS-6758 (875P Neo) + 8086 3020 D865PERL mainboard + 8086 302f Desktop Board D865GBF + 8086 3427 S875WP1-E mainboard + 1051 82801EB/ER (ICH5/ICH5R) integrated LAN Controller + 1052 PRO/100 VM Network Connection + 1053 PRO/100 VM Network Connection + 1059 82551QM Ethernet Controller + 105b 82546GB Gigabit Ethernet Controller (Copper) + 105e 82571EB Gigabit Ethernet Controller + 103c 7044 NC360T PCI Express Dual Port Gigabit Server Adapter + 1775 6003 Telum GE-QT + 8086 005e PRO/1000 PT Dual Port Server Connection + 8086 105e PRO/1000 PT Dual Port Network Connection + 8086 115e PRO/1000 PT Dual Port Server Adapter + 8086 116e PRO/1000 PT Dual Port Server Adapter + 8086 125e PRO/1000 PT Dual Port Server Adapter + 8086 135e PRO/1000 PT Dual Port Server Adapter + 105f 82571EB Gigabit Ethernet Controller + 8086 115f PRO/1000 PF Dual Port Server Adapter + 8086 116f PRO/1000 PF Dual Port Server Adapter + 8086 125f PRO/1000 PF Dual Port Server Adapter + 8086 135f PRO/1000 PF Dual Port Server Adapter + 1060 82571EB Gigabit Ethernet Controller + 8086 0060 PRO/1000 PB Dual Port Server Connection + 8086 1060 PRO/1000 PB Dual Port Server Connection + 1064 82562ET/EZ/GT/GZ - PRO/100 VE (LOM) Ethernet Controller + 1043 80f8 P5GD1-VW Mainboard + 1065 82562ET/EZ/GT/GZ - PRO/100 VE Ethernet Controller + 1066 82562 EM/EX/GX - PRO/100 VM (LOM) Ethernet Controller + 1067 82562 EM/EX/GX - PRO/100 VM Ethernet Controller + 1068 82562ET/EZ/GT/GZ - PRO/100 VE (LOM) Ethernet Controller Mobile + 1069 82562EM/EX/GX - PRO/100 VM (LOM) Ethernet Controller Mobile + 106a 82562G - PRO/100 VE (LOM) Ethernet Controller + 106b 82562G - PRO/100 VE Ethernet Controller Mobile + 1075 82547GI Gigabit Ethernet Controller + 1028 0165 PowerEdge 750 + 8086 0075 PRO/1000 CT Network Connection + 8086 1075 PRO/1000 CT Network Connection + 1076 82541GI Gigabit Ethernet Controller + 1028 0165 PowerEdge 750 + 1028 019a PowerEdge SC1425 + 8086 0076 PRO/1000 MT Network Connection + 8086 1076 PRO/1000 MT Network Connection + 8086 1176 PRO/1000 MT Desktop Adapter + 8086 1276 PRO/1000 MT Network Adapter + 1077 82541GI Gigabit Ethernet Controller + 1179 0001 PRO/1000 MT Mobile Connection + 8086 0077 PRO/1000 MT Mobile Connection + 8086 1077 PRO/1000 MT Mobile Connection + 1078 82541ER Gigabit Ethernet Controller + 8086 1078 82541ER-based Network Connection + 1079 82546GB Gigabit Ethernet Controller + 103c 12a6 Dual Port 1000Base-T [A9900A] + 103c 12cf Core Dual Port 1000Base-T [AB352A] + 1775 10d0 V5D Single Board Computer Gigabit Ethernet + 1775 ce90 CE9 + 1fc1 0027 Niagara 2261 Failover NIC + 4c53 1090 Cx9 / Vx9 mainboard + 4c53 10b0 CL9 mainboard + 8086 0079 PRO/1000 MT Dual Port Network Connection + 8086 1079 PRO/1000 MT Dual Port Network Connection + 8086 1179 PRO/1000 MT Dual Port Server Adapter + 8086 117a PRO/1000 MT Dual Port Server Adapter + 107a 82546GB Gigabit Ethernet Controller + 103c 12a8 Dual Port 1000base-SX [A9899A] + 8086 107a PRO/1000 MF Dual Port Server Adapter + 8086 127a PRO/1000 MF Dual Port Server Adapter + 107b 82546GB Gigabit Ethernet Controller + 8086 007b PRO/1000 MB Dual Port Server Connection + 8086 107b PRO/1000 MB Dual Port Server Connection + 107c 82541PI Gigabit Ethernet Controller + 8086 1376 PRO/1000 GT Desktop Adapter + 8086 1476 PRO/1000 GT Desktop Adapter + 107d 82572EI Gigabit Ethernet Controller (Copper) + 8086 1082 PRO/1000 PT Server Adapter + 8086 1092 PRO/1000 PT Server Adapter + 107e 82572EI Gigabit Ethernet Controller (Fiber) + 8086 1084 PRO/1000 PF Server Adapter + 8086 1094 PRO/1000 PF Server Adapter + 107f 82572EI Gigabit Ethernet Controller + 1080 FA82537EP 56K V.92 Data/Fax Modem PCI + 1081 631xESB/632xESB LAN Controller Copper + 1082 631xESB/632xESB LAN Controller fiber + 1083 631xESB/632xESB LAN Controller SERDES + 1084 631xESB/632xESB IDE Redirection + 1085 631xESB/632xESB Serial Port Redirection + 1086 631xESB/632xESB IPMI/KCS0 + 1087 631xESB/632xESB UHCI Redirection + 1089 631xESB/632xESB BT + 108a 82546GB Gigabit Ethernet Controller + 8086 108a PRO/1000 P Dual Port Server Adapter + 8086 118a PRO/1000 P Dual Port Server Adapter + 108b 82573V Gigabit Ethernet Controller (Copper) + 108c 82573E Gigabit Ethernet Controller (Copper) + 108e 82573E KCS (Active Management) + 108f Active Management Technology - SOL + 1092 PRO/100 VE Network Connection + 1096 80003ES2LAN Gigabit Ethernet Controller (Copper) + 1097 631xESB/632xESB DPT LAN Controller (Fiber) + 1098 80003ES2LAN Gigabit Ethernet Controller (Serdes) + 1099 82546GB Gigabit Ethernet Controller (Copper) + 8086 1099 PRO/1000 GT Quad Port Server Adapter + 109a 82573L Gigabit Ethernet Controller + 17aa 2001 ThinkPad T60 + 17aa 207e Thinkpad X60s + 8086 109a PRO/1000 PL Network Connection + 109b 82546GB PRO/1000 GF Quad Port Server Adapter + 10a0 82571EB PRO/1000 AT Quad Port Bypass Adapter + 10a1 82571EB PRO/1000 AF Quad Port Bypass Adapter + 10b0 82573L PRO/1000 PL Network Connection + 10b2 82573V PRO/1000 PM Network Connection + 10b3 82573E PRO/1000 PM Network Connection + 10b4 82573L PRO/1000 PL Network Connection + 10b5 82546GB Gigabit Ethernet Controller (Copper) + 103c 3109 NC340T PCI-X Quad-port Gigabit Server Adapter + 8086 1099 PRO/1000 GT Quad Port Server Adapter + 8086 1199 PRO/1000 GT Quad Port Server Adapter + 10b9 82572EI Gigabit Ethernet Controller (Copper) + 8086 1083 PRO/1000 PT Desktop Adapter + 8086 1093 PRO/1000 PT Desktop Adapter + 10ba 80003ES2LAN Gigabit Ethernet Controller (Copper) + 10bb 80003ES2LAN Gigabit Ethernet Controller (Serdes) + 1107 PRO/1000 MF Server Adapter (LX) + 1130 82815 815 Chipset Host Bridge and Memory Controller Hub + 1025 1016 Travelmate 612 TX + 1043 8027 TUSL2-C Mainboard + 104d 80df Vaio PCG-FX403 + 8086 4532 D815EEA2 mainboard + 8086 4557 D815EGEW Mainboard + 1131 82815 815 Chipset AGP Bridge + 1132 82815 CGC [Chipset Graphics Controller] + 1025 1016 Travelmate 612 TX + 104d 80df Vaio PCG-FX403 + 8086 4532 D815EEA2 Mainboard + 8086 4541 D815EEA Motherboard + 8086 4557 D815EGEW Mainboard + 1161 82806AA PCI64 Hub Advanced Programmable Interrupt Controller + 8086 1161 82806AA PCI64 Hub APIC + 1162 Xscale 80200 Big Endian Companion Chip + 1200 IXP1200 Network Processor + 172a 0000 AEP SSL Accelerator + 1209 8255xER/82551IT Fast Ethernet Controller + 4c53 1050 CT7 mainboard + 4c53 1051 CE7 mainboard + 4c53 1070 PC6 mainboard + 1221 82092AA PCI to PCMCIA Bridge + 1222 82092AA IDE Controller + 1223 SAA7116 + 1225 82452KX/GX [Orion] + 1226 82596 PRO/10 PCI + 1227 82865 EtherExpress PRO/100A + 1228 82556 EtherExpress PRO/100 Smart +# the revision field differentiates between them (1-3 is 82557, 4-5 is 82558, 6-8 is 82559, 9 is 82559ER) + 1229 82557/8/9 [Ethernet Pro 100] + 0e11 3001 82559 Fast Ethernet LOM with Alert on LAN* + 0e11 3002 82559 Fast Ethernet LOM with Alert on LAN* + 0e11 3003 82559 Fast Ethernet LOM with Alert on LAN* + 0e11 3004 82559 Fast Ethernet LOM with Alert on LAN* + 0e11 3005 82559 Fast Ethernet LOM with Alert on LAN* + 0e11 3006 82559 Fast Ethernet LOM with Alert on LAN* + 0e11 3007 82559 Fast Ethernet LOM with Alert on LAN* + 0e11 b01e NC3120 Fast Ethernet NIC + 0e11 b01f NC3122 Fast Ethernet NIC (dual port) + 0e11 b02f NC1120 Ethernet NIC + 0e11 b04a Netelligent 10/100TX NIC with Wake on LAN + 0e11 b0c6 NC3161 Fast Ethernet NIC (embedded, WOL) + 0e11 b0c7 NC3160 Fast Ethernet NIC (embedded) + 0e11 b0d7 NC3121 Fast Ethernet NIC (WOL) + 0e11 b0dd NC3131 Fast Ethernet NIC (dual port) + 0e11 b0de NC3132 Fast Ethernet Module (dual port) + 0e11 b0e1 NC3133 Fast Ethernet Module (100-FX) + 0e11 b134 NC3163 Fast Ethernet NIC (embedded, WOL) + 0e11 b13c NC3162 Fast Ethernet NIC (embedded) + 0e11 b144 NC3123 Fast Ethernet NIC (WOL) + 0e11 b163 NC3134 Fast Ethernet NIC (dual port) + 0e11 b164 NC3135 Fast Ethernet Upgrade Module (dual port) + 0e11 b1a4 NC7131 Gigabit Server Adapter + 1014 005c 82558B Ethernet Pro 10/100 + 1014 01bc 82559 Fast Ethernet LAN On Motherboard + 1014 01f1 10/100 Ethernet Server Adapter + 1014 01f2 10/100 Ethernet Server Adapter + 1014 0207 Ethernet Pro/100 S + 1014 0232 10/100 Dual Port Server Adapter + 1014 023a ThinkPad R30 + 1014 105c Netfinity 10/100 + 1014 2205 ThinkPad A22p + 1014 305c 10/100 EtherJet Management Adapter + 1014 405c 10/100 EtherJet Adapter with Alert on LAN + 1014 505c 10/100 EtherJet Secure Management Adapter + 1014 605c 10/100 EtherJet Secure Management Adapter + 1014 705c 10/100 Netfinity 10/100 Ethernet Security Adapter + 1014 805c 10/100 Netfinity 10/100 Ethernet Security Adapter + 1028 009b PowerEdge 2500/2550 + 1028 00ce PowerEdge 1400 + 1033 8000 PC-9821X-B06 + 1033 8016 PK-UG-X006 + 1033 801f PK-UG-X006 + 1033 8026 PK-UG-X006 + 1033 8063 82559-based Fast Ethernet Adapter + 1033 8064 82559-based Fast Ethernet Adapter + 103c 10c0 NetServer 10/100TX + 103c 10c3 NetServer 10/100TX + 103c 10ca NetServer 10/100TX + 103c 10cb NetServer 10/100TX + 103c 10e3 NetServer 10/100TX + 103c 10e4 NetServer 10/100TX + 103c 1200 NetServer 10/100TX + 108e 10cf EtherExpress PRO/100(B) + 10c3 1100 SmartEther100 SC1100 + 10cf 1115 8255x-based Ethernet Adapter (10/100) + 10cf 1143 8255x-based Ethernet Adapter (10/100) + 110a 008b 82551QM Fast Ethernet Multifuction PCI/CardBus Controller + 1179 0001 8255x-based Ethernet Adapter (10/100) + 1179 0002 PCI FastEther LAN on Docker + 1179 0003 8255x-based Fast Ethernet + 1259 2560 AT-2560 100 + 1259 2561 AT-2560 100 FX Ethernet Adapter + 1266 0001 NE10/100 Adapter + 13e9 1000 6221L-4U + 144d 2501 SEM-2000 MiniPCI LAN Adapter + 144d 2502 SEM-2100IL MiniPCI LAN Adapter + 1668 1100 EtherExpress PRO/100B (TX) (MiniPCI Ethernet+Modem) + 1775 ce90 CE9 + 4c53 1080 CT8 mainboard + 4c53 10e0 PSL09 PrPMC + 8086 0001 EtherExpress PRO/100B (TX) + 8086 0002 EtherExpress PRO/100B (T4) + 8086 0003 EtherExpress PRO/10+ + 8086 0004 EtherExpress PRO/100 WfM + 8086 0005 82557 10/100 + 8086 0006 82557 10/100 with Wake on LAN + 8086 0007 82558 10/100 Adapter + 8086 0008 82558 10/100 with Wake on LAN + 8086 000a EtherExpress PRO/100+ Management Adapter + 8086 000b EtherExpress PRO/100+ + 8086 000c EtherExpress PRO/100+ Management Adapter + 8086 000d EtherExpress PRO/100+ Alert On LAN II* Adapter + 8086 000e EtherExpress PRO/100+ Management Adapter with Alert On LAN* + 8086 000f EtherExpress PRO/100 Desktop Adapter + 8086 0010 EtherExpress PRO/100 S Management Adapter + 8086 0011 EtherExpress PRO/100 S Management Adapter + 8086 0012 EtherExpress PRO/100 S Advanced Management Adapter (D) + 8086 0013 EtherExpress PRO/100 S Advanced Management Adapter (E) + 8086 0030 EtherExpress PRO/100 Management Adapter with Alert On LAN* GC + 8086 0031 EtherExpress PRO/100 Desktop Adapter + 8086 0040 EtherExpress PRO/100 S Desktop Adapter + 8086 0041 EtherExpress PRO/100 S Desktop Adapter + 8086 0042 EtherExpress PRO/100 Desktop Adapter + 8086 0050 EtherExpress PRO/100 S Desktop Adapter + 8086 1009 EtherExpress PRO/100+ Server Adapter + 8086 100c EtherExpress PRO/100+ Server Adapter (PILA8470B) + 8086 1012 EtherExpress PRO/100 S Server Adapter (D) + 8086 1013 EtherExpress PRO/100 S Server Adapter (E) + 8086 1015 EtherExpress PRO/100 S Dual Port Server Adapter + 8086 1017 EtherExpress PRO/100+ Dual Port Server Adapter + 8086 1030 EtherExpress PRO/100+ Management Adapter with Alert On LAN* G Server + 8086 1040 EtherExpress PRO/100 S Server Adapter + 8086 1041 EtherExpress PRO/100 S Server Adapter + 8086 1042 EtherExpress PRO/100 Server Adapter + 8086 1050 EtherExpress PRO/100 S Server Adapter + 8086 1051 EtherExpress PRO/100 Server Adapter + 8086 1052 EtherExpress PRO/100 Server Adapter + 8086 10f0 EtherExpress PRO/100+ Dual Port Adapter + 8086 2009 EtherExpress PRO/100 S Mobile Adapter + 8086 200d EtherExpress PRO/100 Cardbus + 8086 200e EtherExpress PRO/100 LAN+V90 Cardbus Modem + 8086 200f EtherExpress PRO/100 SR Mobile Adapter + 8086 2010 EtherExpress PRO/100 S Mobile Combo Adapter + 8086 2013 EtherExpress PRO/100 SR Mobile Combo Adapter + 8086 2016 EtherExpress PRO/100 S Mobile Adapter + 8086 2017 EtherExpress PRO/100 S Combo Mobile Adapter + 8086 2018 EtherExpress PRO/100 SR Mobile Adapter + 8086 2019 EtherExpress PRO/100 SR Combo Mobile Adapter + 8086 2101 EtherExpress PRO/100 P Mobile Adapter + 8086 2102 EtherExpress PRO/100 SP Mobile Adapter + 8086 2103 EtherExpress PRO/100 SP Mobile Adapter + 8086 2104 EtherExpress PRO/100 SP Mobile Adapter + 8086 2105 EtherExpress PRO/100 SP Mobile Adapter + 8086 2106 EtherExpress PRO/100 P Mobile Adapter + 8086 2107 EtherExpress PRO/100 Network Connection + 8086 2108 EtherExpress PRO/100 Network Connection + 8086 2200 EtherExpress PRO/100 P Mobile Combo Adapter + 8086 2201 EtherExpress PRO/100 P Mobile Combo Adapter + 8086 2202 EtherExpress PRO/100 SP Mobile Combo Adapter + 8086 2203 EtherExpress PRO/100+ MiniPCI + 8086 2204 EtherExpress PRO/100+ MiniPCI + 8086 2205 EtherExpress PRO/100 SP Mobile Combo Adapter + 8086 2206 EtherExpress PRO/100 SP Mobile Combo Adapter + 8086 2207 EtherExpress PRO/100 SP Mobile Combo Adapter + 8086 2208 EtherExpress PRO/100 P Mobile Combo Adapter + 8086 2402 EtherExpress PRO/100+ MiniPCI + 8086 2407 EtherExpress PRO/100+ MiniPCI + 8086 2408 EtherExpress PRO/100+ MiniPCI + 8086 2409 EtherExpress PRO/100+ MiniPCI + 8086 240f EtherExpress PRO/100+ MiniPCI + 8086 2410 EtherExpress PRO/100+ MiniPCI + 8086 2411 EtherExpress PRO/100+ MiniPCI + 8086 2412 EtherExpress PRO/100+ MiniPCI + 8086 2413 EtherExpress PRO/100+ MiniPCI + 8086 3000 82559 Fast Ethernet LAN on Motherboard + 8086 3001 82559 Fast Ethernet LOM with Basic Alert on LAN* + 8086 3002 82559 Fast Ethernet LOM with Alert on LAN II* + 8086 3006 EtherExpress PRO/100 S Network Connection + 8086 3007 EtherExpress PRO/100 S Network Connection + 8086 3008 EtherExpress PRO/100 Network Connection + 8086 3010 EtherExpress PRO/100 S Network Connection + 8086 3011 EtherExpress PRO/100 S Network Connection + 8086 3012 EtherExpress PRO/100 Network Connection + 8086 3411 SDS2 Mainboard + 122d 430FX - 82437FX TSC [Triton I] + 122e 82371FB PIIX ISA [Triton I] + 1230 82371FB PIIX IDE [Triton I] + 1231 DSVD Modem + 1234 430MX - 82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) + 1235 430MX - 82437MX Mob. System Ctrlr (MTSC) & 82438MX Data Path (MTDP) + 1237 440FX - 82441FX PMC [Natoma] + 1239 82371FB PIIX IDE Interface + 123b 82380PB PCI to PCI Docking Bridge + 123c 82380AB (MISA) Mobile PCI-to-ISA Bridge + 123d 683053 Programmable Interrupt Device + 123e 82466GX (IHPC) Integrated Hot-Plug Controller (hidden mode) + 123f 82466GX Integrated Hot-Plug Controller (IHPC) + 1240 82752 (752) AGP Graphics Accelerator + 124b 82380FB (MPCI2) Mobile Docking Controller + 1250 430HX - 82439HX TXC [Triton II] + 1360 82806AA PCI64 Hub PCI Bridge + 1361 82806AA PCI64 Hub Controller (HRes) + 8086 1361 82806AA PCI64 Hub Controller (HRes) + 8086 8000 82806AA PCI64 Hub Controller (HRes) + 1460 82870P2 P64H2 Hub PCI Bridge + 1461 82870P2 P64H2 I/OxAPIC + 15d9 3480 P4DP6 + 4c53 1090 Cx9/Vx9 mainboard + 1462 82870P2 P64H2 Hot Plug Controller + 1960 80960RP [i960RP Microprocessor] + 101e 0431 MegaRAID 431 RAID Controller + 101e 0438 MegaRAID 438 Ultra2 LVD RAID Controller + 101e 0466 MegaRAID 466 Express Plus RAID Controller + 101e 0467 MegaRAID 467 Enterprise 1500 RAID Controller + 101e 0490 MegaRAID 490 Express 300 RAID Controller + 101e 0762 MegaRAID 762 Express RAID Controller + 101e 09a0 PowerEdge Expandable RAID Controller 2/SC + 1028 0467 PowerEdge Expandable RAID Controller 2/DC + 1028 1111 PowerEdge Expandable RAID Controller 2/SC + 103c 03a2 MegaRAID + 103c 10c6 MegaRAID 438, NetRAID-3Si + 103c 10c7 MegaRAID T5, Integrated NetRAID + 103c 10cc MegaRAID, Integrated NetRAID + 103c 10cd NetRAID-1Si + 105a 0000 SuperTrak + 105a 2168 SuperTrak Pro + 105a 5168 SuperTrak66/100 + 1111 1111 MegaRAID 466, PowerEdge Expandable RAID Controller 2/SC + 1111 1112 PowerEdge Expandable RAID Controller 2/SC + 113c 03a2 MegaRAID + e4bf 1010 CG1-RADIO + e4bf 1020 CU2-QUARTET + e4bf 1040 CU1-CHORUS + e4bf 3100 CX1-BAND + 1962 80960RM [i960RM Microprocessor] + 105a 0000 SuperTrak SX6000 I2O CPU + 1a21 82840 840 (Carmel) Chipset Host Bridge (Hub A) + 1a23 82840 840 (Carmel) Chipset AGP Bridge + 1a24 82840 840 (Carmel) Chipset PCI Bridge (Hub B) + 1a30 82845 845 (Brookdale) Chipset Host Bridge + 1028 010e Optiplex GX240 + 1a31 82845 845 (Brookdale) Chipset AGP Bridge + 1a38 5000 Series Chipset DMA Engine + 1a48 PRO/10GbE SR Server Adapter + 2410 82801AA ISA Bridge (LPC) + 2411 82801AA IDE + 2412 82801AA USB + 2413 82801AA SMBus + 2415 82801AA AC'97 Audio + 1028 0095 Precision Workstation 220 Integrated Digital Audio + 110a 0051 Activy 2xx + 11d4 0040 SoundMAX Integrated Digital Audio + 11d4 0048 SoundMAX Integrated Digital Audio + 11d4 5340 SoundMAX Integrated Digital Audio + 1734 1025 Activy 3xx + 2416 82801AA AC'97 Modem + 2418 82801AA PCI Bridge + 2420 82801AB ISA Bridge (LPC) + 2421 82801AB IDE + 2422 82801AB USB + 2423 82801AB SMBus + 2425 82801AB AC'97 Audio + 11d4 0040 SoundMAX Integrated Digital Audio + 11d4 0048 SoundMAX Integrated Digital Audio + 2426 82801AB AC'97 Modem + 2428 82801AB PCI Bridge + 2440 82801BA ISA Bridge (LPC) + 2442 82801BA/BAM USB (Hub #1) + 1014 01c6 Netvista A40/A40p + 1025 1016 Travelmate 612 TX + 1028 00c7 Dimension 8100 + 1028 010e Optiplex GX240 + 1043 8027 TUSL2-C Mainboard + 104d 80df Vaio PCG-FX403 + 147b 0507 TH7II-RAID + 8086 4532 D815EEA2 mainboard + 8086 4557 D815EGEW Mainboard + 2443 82801BA/BAM SMBus + 1014 01c6 Netvista A40/A40p + 1025 1016 Travelmate 612 TX + 1028 00c7 Dimension 8100 + 1028 010e Optiplex GX240 + 1043 8027 TUSL2-C Mainboard + 104d 80df Vaio PCG-FX403 + 147b 0507 TH7II-RAID + 8086 4532 D815EEA2 mainboard + 8086 4557 D815EGEW Mainboard + 2444 82801BA/BAM USB (Hub #2) + 1025 1016 Travelmate 612 TX + 1028 00c7 Dimension 8100 + 1028 010e Optiplex GX240 + 1043 8027 TUSL2-C Mainboard + 104d 80df Vaio PCG-FX403 + 147b 0507 TH7II-RAID + 8086 4532 D815EEA2 mainboard + 2445 82801BA/BAM AC'97 Audio + 0e11 0088 Evo D500 + 1014 01c6 Netvista A40/A40p + 1025 1016 Travelmate 612 TX + 104d 80df Vaio PCG-FX403 + 1462 3370 STAC9721 AC + 147b 0507 TH7II-RAID + 8086 4557 D815EGEW Mainboard + 2446 82801BA/BAM AC'97 Modem + 1025 1016 Travelmate 612 TX + 104d 80df Vaio PCG-FX403 + 2448 82801 Mobile PCI Bridge + 103c 099c NX6110/NC6120 + 1734 1055 Amilo M1420 + 2449 82801BA/BAM/CA/CAM Ethernet Controller + 0e11 0012 EtherExpress PRO/100 VM + 0e11 0091 EtherExpress PRO/100 VE + 1014 01ce EtherExpress PRO/100 VE + 1014 01dc EtherExpress PRO/100 VE + 1014 01eb EtherExpress PRO/100 VE + 1014 01ec EtherExpress PRO/100 VE + 1014 0202 EtherExpress PRO/100 VE + 1014 0205 EtherExpress PRO/100 VE + 1014 0217 EtherExpress PRO/100 VE + 1014 0234 EtherExpress PRO/100 VE + 1014 023d EtherExpress PRO/100 VE + 1014 0244 EtherExpress PRO/100 VE + 1014 0245 EtherExpress PRO/100 VE + 1014 0265 PRO/100 VE Desktop Connection + 1014 0267 PRO/100 VE Desktop Connection + 1014 026a PRO/100 VE Desktop Connection + 109f 315d EtherExpress PRO/100 VE + 109f 3181 EtherExpress PRO/100 VE + 1179 ff01 PRO/100 VE Network Connection + 1186 7801 EtherExpress PRO/100 VE + 144d 2602 HomePNA 1M CNR + 8086 3010 EtherExpress PRO/100 VE + 8086 3011 EtherExpress PRO/100 VM + 8086 3012 82562EH based Phoneline + 8086 3013 EtherExpress PRO/100 VE + 8086 3014 EtherExpress PRO/100 VM + 8086 3015 82562EH based Phoneline + 8086 3016 EtherExpress PRO/100 P Mobile Combo + 8086 3017 EtherExpress PRO/100 P Mobile + 8086 3018 EtherExpress PRO/100 + 244a 82801BAM IDE U100 + 1025 1016 Travelmate 612TX + 104d 80df Vaio PCG-FX403 + 244b 82801BA IDE U100 + 1014 01c6 Netvista A40/A40p + 1028 00c7 Dimension 8100 + 1028 010e Optiplex GX240 + 1043 8027 TUSL2-C Mainboard + 147b 0507 TH7II-RAID + 8086 4532 D815EEA2 mainboard + 8086 4557 D815EGEW Mainboard + 244c 82801BAM ISA Bridge (LPC) + 244e 82801 PCI Bridge + 1014 0267 NetVista A30p + 2450 82801E ISA Bridge (LPC) + 2452 82801E USB + 2453 82801E SMBus + 2459 82801E Ethernet Controller 0 + 245b 82801E IDE U100 + 245d 82801E Ethernet Controller 1 + 245e 82801E PCI Bridge + 2480 82801CA LPC Interface Controller + 2482 82801CA/CAM USB (Hub #1) + 0e11 0030 Evo N600c + 1014 0220 ThinkPad A/T/X Series + 104d 80e7 VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP + 15d9 3480 P4DP6 + 8086 1958 vpr Matrix 170B4 + 8086 3424 SE7501HG2 Mainboard + 8086 4541 Latitude C640 + 2483 82801CA/CAM SMBus Controller + 1014 0220 ThinkPad A/T/X Series + 104d 80e7 VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP + 15d9 3480 P4DP6 + 8086 1958 vpr Matrix 170B4 + 2484 82801CA/CAM USB (Hub #2) + 0e11 0030 Evo N600c + 1014 0220 ThinkPad A/T/X Series + 104d 80e7 VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP + 15d9 3480 P4DP6 + 8086 1958 vpr Matrix 170B4 + 2485 82801CA/CAM AC'97 Audio Controller + 1013 5959 Crystal WMD Audio Codec + 1014 0222 ThinkPad T23 (2647-4MG) or A30/A30p (2652/2653) + 1014 0508 ThinkPad T30 + 1014 051c ThinkPad A/T/X Series + 104d 80e7 VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP + 144d c006 vpr Matrix 170B4 + 2486 82801CA/CAM AC'97 Modem Controller + 1014 0223 ThinkPad A/T/X Series + 1014 0503 ThinkPad R31 2656BBG + 1014 051a ThinkPad A/T/X Series + 101f 1025 620 Series + 104d 80e7 VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP + 134d 4c21 Dell Inspiron 2100 internal modem + 144d 2115 vpr Matrix 170B4 internal modem + 14f1 5421 MD56ORD V.92 MDC Modem + 2487 82801CA/CAM USB (Hub #3) + 0e11 0030 Evo N600c + 1014 0220 ThinkPad A/T/X Series + 104d 80e7 VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP + 15d9 3480 P4DP6 + 8086 1958 vpr Matrix 170B4 + 248a 82801CAM IDE U100 + 0e11 0030 Evo N600c + 1014 0220 ThinkPad A/T/X Series + 104d 80e7 VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP + 8086 1958 vpr Matrix 170B4 + 8086 4541 Latitude C640 + 248b 82801CA Ultra ATA Storage Controller + 15d9 3480 P4DP6 + 248c 82801CAM ISA Bridge (LPC) + 24c0 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge + 1014 0267 NetVista A30p + 1462 5800 845PE Max (MS-6580) + 24c1 82801DBL (ICH4-L) IDE Controller + 24c2 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #1 + 1014 0267 NetVista A30p + 1014 052d Thinkpad R50e model 1634 + 1025 005a TravelMate 290 + 1028 0126 Optiplex GX260 + 1028 0163 Latitude D505 + 1028 0196 Inspiron 5160 + 103c 088c NC8000 laptop + 103c 0890 NC6000 laptop + 103c 08b0 tc1100 tablet + 1071 8160 MIM2000 + 1462 5800 845PE Max (MS-6580) + 1509 2990 Averatec 5110H laptop + 1734 1004 D1451 Mainboard (SCENIC N300, i845GV) + 1734 1055 Amilo M1420 + 4c53 1090 Cx9 / Vx9 mainboard + 8086 4541 Latitude D400 + 24c3 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) SMBus Controller + 1014 0267 NetVista A30p + 1014 052d Thinkpad R50e model 1634 + 1025 005a TravelMate 290 + 1028 0126 Optiplex GX260 + 103c 088c NC8000 laptop + 103c 0890 NC6000 laptop + 103c 08b0 tc1100 tablet + 1071 8160 MIM2000 + 1458 24c2 GA-8PE667 Ultra + 1462 5800 845PE Max (MS-6580) + 1734 1004 D1451 Mainboard (SCENIC N300, i845GV) + 1734 1055 Amilo M1420 + 4c53 1090 Cx9 / Vx9 mainboard + 24c4 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #2 + 1014 0267 NetVista A30p + 1014 052d Thinkpad R50e model 1634 + 1025 005a TravelMate 290 + 1028 0126 Optiplex GX260 + 1028 0163 Latitude D505 + 1028 0196 Inspiron 5160 + 103c 088c NC8000 laptop + 103c 0890 NC6000 laptop + 103c 08b0 tc1100 tablet + 1071 8160 MIM2000 + 1462 5800 845PE Max (MS-6580) + 1509 2990 Averatec 5110H + 1734 1004 D1451 Mainboard (SCENIC N300, i845GV) + 4c53 1090 Cx9 / Vx9 mainboard + 8086 4541 Latitude D400 + 24c5 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 Audio Controller + 0e11 00b8 Analog Devices Inc. codec [SoundMAX] + 1014 0267 NetVista A30p + 1014 055f Thinkpad R50e model 1634 + 1025 005a TravelMate 290 + 1028 0139 Latitude D400 + 1028 0163 Latitude D505 + 1028 0196 Inspiron 5160 + 103c 088c NC8000 laptop + 103c 0890 NC6000 laptop + 103c 08b0 tc1100 tablet + 1071 8160 MIM2000 + 1458 a002 GA-8PE667 Ultra + 1462 5800 845PE Max (MS-6580) + 1734 1005 D1451 (SCENIC N300, i845GV) Sigmatel STAC9750T + 1734 1055 Amilo M1420 + 24c6 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 Modem Controller + 1014 0559 Thinkpad R50e model 1634 + 1025 003c Aspire 2001WLCi (Compal CL50 motherboard) implementation + 1025 005a TravelMate 290 + 1028 0196 Inspiron 5160 + 103c 088c NC8000 laptop + 103c 0890 NC6000 laptop + 103c 08b0 tc1100 tablet + 1071 8160 MIM2000 + 24c7 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #3 + 1014 0267 NetVista A30p + 1014 052d Thinkpad R50e model 1634 + 1025 005a TravelMate 290 + 1028 0126 Optiplex GX260 + 1028 0163 Latitude D505 + 1028 0196 Inspiron 5160 + 103c 088c NC8000 laptop + 103c 0890 NC6000 laptop + 103c 08b0 tc1100 tablet + 1071 8160 MIM2000 + 1462 5800 845PE Max (MS-6580) + 1509 2990 Averatec 5110H + 1734 1004 D1451 Mainboard (SCENIC N300, i845GV) + 4c53 1090 Cx9 / Vx9 mainboard + 8086 4541 Latitude D400 + 24ca 82801DBM (ICH4-M) IDE Controller + 1014 052d Thinkpad R50e model 1634 + 1025 005a TravelMate 290 + 1028 0163 Latitude D505 + 1028 0196 Inspiron 5160 + 103c 088c NC8000 laptop + 103c 0890 NC6000 laptop + 103c 08b0 tc1100 tablet + 1071 8160 MIM2000 + 1734 1055 Amilo M1420 + 8086 4541 Latitude D400 + 24cb 82801DB (ICH4) IDE Controller + 1014 0267 NetVista A30p + 1028 0126 Optiplex GX260 + 1458 24c2 GA-8PE667 Ultra + 1462 5800 845PE Max (MS-6580) + 1734 1004 D1451 Mainboard (SCENIC N300, i845GV) + 4c53 1090 Cx9 / Vx9 mainboard + 24cc 82801DBM (ICH4-M) LPC Interface Bridge + 1734 1055 Amilo M1420 + 24cd 82801DB/DBM (ICH4/ICH4-M) USB2 EHCI Controller + 1014 0267 NetVista A30p + 1014 052e Thinkpad R50e model 1634 + 1025 005a TravelMate 290 + 1028 011d Latitude D600 + 1028 0126 Optiplex GX260 + 1028 0139 Latitude D400 + 1028 0163 Latitude D505 + 1028 0196 Inspiron 5160 + 103c 088c NC8000 laptop + 103c 0890 NC6000 laptop + 103c 08b0 tc1100 tablet + 1071 8160 MIM2000 + 1179 ff00 Satellite 2430 + 1462 3981 845PE Max (MS-6580) + 1509 1968 Averatec 5110H + 1734 1004 D1451 Mainboard (SCENIC N300, i845GV) + 1734 1055 Amilo M1420 + 4c53 1090 Cx9 / Vx9 mainboard + 24d0 82801EB/ER (ICH5/ICH5R) LPC Interface Bridge + 24d1 82801EB (ICH5) SATA Controller + 1028 0169 Precision 470 + 1028 019a PowerEdge SC1425 + 103c 12bc d530 CMT (DG746A) + 1043 80a6 P4P800 SE Mainboard + 1458 24d1 GA-8IPE1000 Pro2 motherboard (865PE) + 1462 7280 865PE Neo2 (MS-6728) + 15d9 4580 P4SCE Mainboard + 8086 3427 S875WP1-E mainboard + 8086 4246 Desktop Board D865GBF + 8086 4c43 Desktop Board D865GLC + 8086 524c D865PERL mainboard + 24d2 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #1 + 1014 02ed xSeries server mainboard + 1028 0169 Precision 470 + 1028 0183 PowerEdge 1800 + 1028 019a PowerEdge SC1425 + 103c 006a NX9500 + 103c 12bc d530 CMT (DG746A) + 1043 80a6 P5P800-MX Mainboard + 1458 24d2 GA-8IPE1000/8KNXP motherboard + 1462 7280 865PE Neo2 (MS-6728) + 15d9 4580 P4SCE Mainboard + 1734 101c Primergy RX300 S2 + 8086 3427 S875WP1-E mainboard + 8086 4246 Desktop Board D865GBF + 8086 4c43 Desktop Board D865GLC + 8086 524c D865PERL mainboard + 24d3 82801EB/ER (ICH5/ICH5R) SMBus Controller + 1014 02ed xSeries server mainboard + 1028 0156 Precision 360 + 1028 0169 Precision 470 + 1043 80a6 P4P800 Mainboard + 1458 24d2 GA-8IPE1000 Pro2 motherboard (865PE) + 1462 7280 865PE Neo2 (MS-6728) + 15d9 4580 P4SCE Mainboard + 1734 101c Primergy RX300 S2 + 8086 3427 S875WP1-E mainboard + 8086 4246 Desktop Board D865GBF + 8086 4c43 Desktop Board D865GLC + 8086 524c D865PERL mainboard + 24d4 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #2 + 1014 02ed xSeries server mainboard + 1028 0169 Precision 470 + 1028 0183 PowerEdge 1800 + 1028 019a PowerEdge SC1425 + 103c 006a NX9500 + 103c 12bc d530 CMT (DG746A) + 1043 80a6 P5P800-MX Mainboard + 1458 24d2 GA-8IPE1000 Pro2 motherboard (865PE) + 1462 7280 865PE Neo2 (MS-6728) + 15d9 4580 P4SCE Mainboard + 1734 101c Primergy RX300 S2 + 8086 3427 S875WP1-E mainboard + 8086 4246 Desktop Board D865GBF + 8086 4c43 Desktop Board D865GLC + 8086 524c D865PERL mainboard + 24d5 82801EB/ER (ICH5/ICH5R) AC'97 Audio Controller + 1028 0169 Precision 470 + 103c 006a NX9500 + 103c 12bc d330 uT + 1043 80f3 P4P800 Mainboard + 1043 810f P5P800-MX Mainboard + 1458 a002 GA-8IPE1000/8KNXP motherboard + 1462 0080 65PE Neo2-V (MS-6788) mainboard + 1462 7280 865PE Neo2 (MS-6728) + 8086 a000 D865PERL mainboard + 8086 e000 D865PERL mainboard + 8086 e001 Desktop Board D865GBF + 8086 e002 SoundMax Intergrated Digital Audio + 24d6 82801EB/ER (ICH5/ICH5R) AC'97 Modem Controller + 103c 006a NX9500 + 24d7 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #3 + 1014 02ed xSeries server mainboard + 1028 0169 Precision 470 + 1028 0183 PowerEdge 1800 + 103c 006a NX9500 + 103c 12bc d530 CMT (DG746A) + 1043 80a6 P5P800-MX Mainboard + 1458 24d2 GA-8IPE1000 Pro2 motherboard (865PE) + 1462 7280 865PE Neo2 (MS-6728) + 15d9 4580 P4SCE Mainboard + 1734 101c Primergy RX300 S2 + 8086 3427 S875WP1-E mainboard + 8086 4246 Desktop Board D865GBF + 8086 4c43 Desktop Board D865GLC + 8086 524c D865PERL mainboard + 24db 82801EB/ER (ICH5/ICH5R) IDE Controller + 1014 02ed xSeries server mainboard + 1028 0169 Precision 470 + 1028 019a PowerEdge SC1425 + 103c 006a NX9500 + 103c 12bc d530 CMT (DG746A) + 1043 80a6 P5P800-MX Mainboard + 1458 24d2 GA-8IPE1000 Pro2 motherboard (865PE) + 1462 7280 865PE Neo2 (MS-6728) + 1462 7580 MSI 875P + 15d9 4580 P4SCE Mainboard + 1734 101c Primergy RX300 S2 + 8086 24db P4C800 Mainboard + 8086 3427 S875WP1-E mainboard + 8086 4246 Desktop Board D865GBF + 8086 4c43 Desktop Board D865GLC + 8086 524c D865PERL mainboard + 24dc 82801EB (ICH5) LPC Interface Bridge + 24dd 82801EB/ER (ICH5/ICH5R) USB2 EHCI Controller + 1014 02ed xSeries server mainboard + 1028 0169 Precision 470 + 1028 0183 PowerEdge 1800 + 1028 019a PowerEdge SC1425 + 103c 006a NX9500 + 103c 12bc d530 CMT (DG746A) + 1043 80a6 P5P800-MX Mainboard + 1458 5006 GA-8IPE1000 Pro2 motherboard (865PE) + 1462 7280 865PE Neo2 (MS-6728) + 8086 3427 S875WP1-E mainboard + 8086 4246 Desktop Board D865GBF + 8086 4c43 Desktop Board D865GLC + 8086 524c D865PERL mainboard + 24de 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #4 + 1014 02ed xSeries server mainboard + 1028 0169 Precision 470 + 1043 80a6 P5P800-MX Mainboard + 1458 24d2 GA-8IPE1000 Pro2 motherboard (865PE) + 1462 7280 865PE Neo2 (MS-6728) + 15d9 4580 P4SCE Mainboard + 1734 101c Primergy RX300 S2 + 8086 3427 S875WP1-E mainboard + 8086 4246 Desktop Board D865GBF + 8086 4c43 Desktop Board D865GLC + 8086 524c D865PERL mainboard + 24df 82801ER (ICH5R) SATA Controller + 2500 82820 820 (Camino) Chipset Host Bridge (MCH) + 1028 0095 Precision Workstation 220 Chipset + 1043 801c P3C-2000 system chipset + 2501 82820 820 (Camino) Chipset Host Bridge (MCH) + 1043 801c P3C-2000 system chipset + 250b 82820 820 (Camino) Chipset Host Bridge + 250f 82820 820 (Camino) Chipset AGP Bridge + 2520 82805AA MTH Memory Translator Hub + 2521 82804AA MRH-S Memory Repeater Hub for SDRAM + 2530 82850 850 (Tehama) Chipset Host Bridge (MCH) + 1028 00c7 Dimension 8100 + 147b 0507 TH7II-RAID + 2531 82860 860 (Wombat) Chipset Host Bridge (MCH) + 2532 82850 850 (Tehama) Chipset AGP Bridge + 2533 82860 860 (Wombat) Chipset AGP Bridge + 2534 82860 860 (Wombat) Chipset PCI Bridge + 2540 E7500 Memory Controller Hub + 15d9 3480 P4DP6 + 2541 E7500/E7501 Host RASUM Controller + 15d9 3480 P4DP6 + 4c53 1090 Cx9 / Vx9 mainboard + 8086 3424 SE7501HG2 Mainboard + 2543 E7500/E7501 Hub Interface B PCI-to-PCI Bridge + 2544 E7500/E7501 Hub Interface B RASUM Controller + 4c53 1090 Cx9 / Vx9 mainboard + 2545 E7500/E7501 Hub Interface C PCI-to-PCI Bridge + 2546 E7500/E7501 Hub Interface C RASUM Controller + 2547 E7500/E7501 Hub Interface D PCI-to-PCI Bridge + 2548 E7500/E7501 Hub Interface D RASUM Controller + 254c E7501 Memory Controller Hub + 4c53 1090 Cx9 / Vx9 mainboard + 8086 3424 SE7501HG2 Mainboard + 2550 E7505 Memory Controller Hub + 2551 E7505/E7205 Series RAS Controller + 2552 E7505/E7205 PCI-to-AGP Bridge + 2553 E7505 Hub Interface B PCI-to-PCI Bridge + 2554 E7505 Hub Interface B PCI-to-PCI Bridge RAS Controller + 255d E7205 Memory Controller Hub + 2560 82845G/GL[Brookdale-G]/GE/PE DRAM Controller/Host-Hub Interface + 1028 0126 Optiplex GX260 + 1458 2560 GA-8PE667 Ultra + 1462 5800 845PE Max (MS-6580) + 2561 82845G/GL[Brookdale-G]/GE/PE Host-to-AGP Bridge + 2562 82845G/GL[Brookdale-G]/GE Chipset Integrated Graphics Device + 0e11 00b9 Evo D510 SFF + 1014 0267 NetVista A30p + 1734 1004 D1451 Mainboard (SCENIC N300, i845GV) + 2570 82865G/PE/P DRAM Controller/Host-Hub Interface + 103c 006a NX9500 + 1043 80f2 P5P800-MX Mainboard + 1458 2570 GA-8IPE1000 Pro2 motherboard (865PE) + 2571 82865G/PE/P PCI to AGP Controller + 2572 82865G Integrated Graphics Controller + 1028 019d Dimension 3000 + 103c 12bc D530 sff(dc578av) + 1043 80a5 P5P800-MX Mainboard + 8086 4246 Desktop Board D865GBF + 8086 4c43 Desktop Board D865GLC + 2573 82865G/PE/P PCI to CSA Bridge + 2576 82865G/PE/P Processor to I/O Memory Interface + 2578 82875P/E7210 Memory Controller Hub + 1458 2578 GA-8KNXP motherboard (875P) + 1462 7580 MS-6758 (875P Neo) + 15d9 4580 P4SCE Motherboard + 2579 82875P Processor to AGP Controller + 257b 82875P/E7210 Processor to PCI to CSA Bridge + 257e 82875P/E7210 Processor to I/O Memory Interface + 2580 82915G/P/GV/GL/PL/910GL Memory Controller Hub + 1458 2580 GA-8I915ME-G Mainboard + 1462 7028 915P/G Neo2 + 1734 105b Scenic W620 + 2581 82915G/P/GV/GL/PL/910GL PCI Express Root Port + 2582 82915G/GV/910GL Integrated Graphics Controller + 1028 1079 Optiplex GX280 + 103c 3006 DC7100 SFF(DX878AV) + 1043 2582 P5GD1-VW Mainboard + 1458 2582 GA-8I915ME-G Mainboard + 1734 105b Scenic W620 + 2584 82925X/XE Memory Controller Hub + 2585 82925X/XE PCI Express Root Port + 2588 E7220/E7221 Memory Controller Hub + 2589 E7220/E7221 PCI Express Root Port + 258a E7221 Integrated Graphics Controller + 2590 Mobile 915GM/PM/GMS/910GML Express Processor to DRAM Controller + 1028 0182 Dell Latidude C610 + 103c 099c NX6110/NC6120 + a304 81b7 Vaio VGN-S3XP + 2591 Mobile 915GM/PM Express PCI Express Root Port + 2592 Mobile 915GM/GMS/910GML Express Graphics Controller + 103c 099c NX6110/NC6120 + 103c 308a NC6220 + 1043 1881 GMA 900 915GM Integrated Graphics + 25a1 6300ESB LPC Interface Controller + 25a2 6300ESB PATA Storage Controller + 1775 10d0 V5D Single Board Computer IDE + 1775 ce90 CE9 + 4c53 10b0 CL9 mainboard + 4c53 10e0 PSL09 PrPMC + 25a3 6300ESB SATA Storage Controller + 1775 ce90 CE9 + 4c53 10b0 CL9 mainboard + 4c53 10d0 Telum ASLP10 Processor AMC + 4c53 10e0 PSL09 PrPMC + 25a4 6300ESB SMBus Controller + 1775 10d0 V5D Single Board Computer + 1775 ce90 CE9 + 4c53 10b0 CL9 mainboard + 4c53 10d0 Telum ASLP10 Processor AMC + 4c53 10e0 PSL09 PrPMC + 25a6 6300ESB AC'97 Audio Controller + 1775 ce90 CE9 + 4c53 10b0 CL9 mainboard + 25a7 6300ESB AC'97 Modem Controller + 25a9 6300ESB USB Universal Host Controller + 1775 10d0 V5D Single Board Computer USB + 1775 ce90 CE9 + 4c53 10b0 CL9 mainboard + 4c53 10d0 Telum ASLP10 Processor AMC + 4c53 10e0 PSL09 PrPMC + 25aa 6300ESB USB Universal Host Controller + 1775 ce90 CE9 + 4c53 10b0 CL9 mainboard + 4c53 10e0 PSL09 PrPMC + 25ab 6300ESB Watchdog Timer + 1775 10d0 V5D Single Board Computer + 1775 ce90 CE9 + 4c53 10b0 CL9 mainboard + 4c53 10d0 Telum ASLP10 Processor AMC + 4c53 10e0 PSL09 PrPMC + 25ac 6300ESB I/O Advanced Programmable Interrupt Controller + 1775 10d0 V5D Single Board Computer + 1775 ce90 CE9 + 4c53 10b0 CL9 mainboard + 4c53 10d0 Telum ASLP10 Processor AMC + 4c53 10e0 PSL09 PrPMC + 25ad 6300ESB USB2 Enhanced Host Controller + 1775 10d0 V5D Single Board Computer USB 2.0 + 1775 ce90 CE9 + 4c53 10b0 CL9 mainboard + 4c53 10d0 Telum ASLP10 Processor AMC + 4c53 10e0 PSL09 PrPMC + 25ae 6300ESB 64-bit PCI-X Bridge + 25b0 6300ESB SATA RAID Controller + 4c53 10d0 Telum ASLP10 Processor AMC + 4c53 10e0 PSL09 PrPMC + 25c0 5000X Chipset Memory Controller Hub + 25d0 5000Z Chipset Memory Controller Hub + 25d4 5000V Chipset Memory Controller Hub + 25d8 5000P Chipset Memory Controller Hub + 25e2 5000 Series Chipset PCI Express x4 Port 2 + 25e3 5000 Series Chipset PCI Express x4 Port 3 + 25e4 5000 Series Chipset PCI Express x4 Port 4 + 25e5 5000 Series Chipset PCI Express x4 Port 5 + 25e6 5000 Series Chipset PCI Express x4 Port 6 + 25e7 5000 Series Chipset PCI Express x4 Port 7 + 25f0 5000 Series Chipset Error Reporting Registers + 25f1 5000 Series Chipset Reserved Registers + 25f3 5000 Series Chipset Reserved Registers + 25f5 5000 Series Chipset FBD Registers + 25f6 5000 Series Chipset FBD Registers + 25f7 5000 Series Chipset PCI Express x8 Port 2-3 + 25f8 5000 Series Chipset PCI Express x8 Port 4-5 + 25f9 5000 Series Chipset PCI Express x8 Port 6-7 + 25fa 5000X Chipset PCI Express x16 Port 4-7 + 2600 E8500/E8501 Hub Interface 1.5 + 2601 E8500/E8501 PCI Express x4 Port D + 2602 E8500/E8501 PCI Express x4 Port C0 + 2603 E8500/E8501 PCI Express x4 Port C1 + 2604 E8500/E8501 PCI Express x4 Port B0 + 2605 E8500/E8501 PCI Express x4 Port B1 + 2606 E8500/E8501 PCI Express x4 Port A0 + 2607 E8500/E8501 PCI Express x4 Port A1 + 2608 E8500/E8501 PCI Express x8 Port C + 2609 E8500/E8501 PCI Express x8 Port B + 260a E8500/E8501 PCI Express x8 Port A + 260c E8500/E8501 IMI Registers + 2610 E8500/E8501 Front Side Bus, Boot, and Interrupt Registers + 2611 E8500/E8501 Address Mapping Registers + 2612 E8500/E8501 RAS Registers + 2613 E8500/E8501 Reserved Registers + 2614 E8500/E8501 Reserved Registers + 2615 E8500/E8501 Miscellaneous Registers + 2617 E8500/E8501 Reserved Registers + 2618 E8500/E8501 Reserved Registers + 2619 E8500/E8501 Reserved Registers + 261a E8500/E8501 Reserved Registers + 261b E8500/E8501 Reserved Registers + 261c E8500/E8501 Reserved Registers + 261d E8500/E8501 Reserved Registers + 261e E8500/E8501 Reserved Registers + 2620 E8500/E8501 eXternal Memory Bridge + 2621 E8500/E8501 XMB Miscellaneous Registers + 2622 E8500/E8501 XMB Memory Interleaving Registers + 2623 E8500/E8501 XMB DDR Initialization and Calibration + 2624 E8500/E8501 XMB Reserved Registers + 2625 E8500/E8501 XMB Reserved Registers + 2626 E8500/E8501 XMB Reserved Registers + 2627 E8500/E8501 XMB Reserved Registers + 2640 82801FB/FR (ICH6/ICH6R) LPC Interface Bridge + 1462 7028 915P/G Neo2 + 1734 105c Scenic W620 + 2641 82801FBM (ICH6M) LPC Interface Bridge + 103c 099c NX6110/NC6120 + 2642 82801FW/FRW (ICH6W/ICH6RW) LPC Interface Bridge + 2651 82801FB/FW (ICH6/ICH6W) SATA Controller + 1028 0179 Optiplex GX280 + 1043 2601 P5GD1-VW Mainboard + 1734 105c Scenic W620 + 8086 4147 D915GAG Motherboard + 2652 82801FR/FRW (ICH6R/ICH6RW) SATA Controller + 1462 7028 915P/G Neo2 + 2653 82801FBM (ICH6M) SATA Controller + 2658 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #1 + 1028 0179 Optiplex GX280 + 103c 099c NX6110/NC6120 + 1043 80a6 P5GD1-VW Mainboard + 1458 2558 GA-8I915ME-G Mainboard + 1462 7028 915P/G Neo2 + 1734 105c Scenic W620 + 2659 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #2 + 1028 0179 Optiplex GX280 + 103c 099c NX6110/NC6120 + 1043 80a6 P5GD1-VW Mainboard + 1458 2659 GA-8I915ME-G Mainboard + 1462 7028 915P/G Neo2 + 1734 105c Scenic W620 + 265a 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #3 + 1028 0179 Optiplex GX280 + 103c 099c NX6110/NC6120 + 1043 80a6 P5GD1-VW Mainboard + 1458 265a GA-8I915ME-G Mainboard + 1462 7028 915P/G Neo2 + 1734 105c Scenic W620 + 265b 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #4 + 1028 0179 Optiplex GX280 + 103c 099c NX6110/NC6120 + 1043 80a6 P5GD1-VW Mainboard + 1458 265a GA-8I915ME-G Mainboard + 1462 7028 915P/G Neo2 + 1734 105c Scenic W620 + 265c 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller + 1028 0179 Optiplex GX280 + 103c 099c NX6110/NC6120 + 1043 80a6 P5GD1-VW Mainboard + 1458 5006 GA-8I915ME-G Mainboard + 1462 7028 915P/G Neo2 + 1734 105c Scenic W620 + 8086 265c Dimension 3100 + 2660 82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 1 + 103c 099c NX6110/NC6120 + 2662 82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 2 + 2664 82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 3 + 2666 82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 4 + 2668 82801FB/FBM/FR/FW/FRW (ICH6 Family) High Definition Audio Controller +# based on the PTGD1-LA motherboard + 103c 2a09 PufferM-UL8E + 1043 814e P5GD1-VW Mainboard + 266a 82801FB/FBM/FR/FW/FRW (ICH6 Family) SMBus Controller + 1028 0179 Optiplex GX280 + 1043 80a6 P5GD1-VW Mainboard + 1458 266a GA-8I915ME-G Mainboard + 1462 7028 915P/G Neo2 + 1734 105c Scenic W620 + 266c 82801FB/FBM/FR/FW/FRW (ICH6 Family) LAN Controller + 266d 82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Modem Controller + 1025 006a Conexant AC'97 CoDec (in Acer TravelMate 2410 serie laptop) + 103c 099c NX6110/NC6120 + 266e 82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Audio Controller + 1025 006a Realtek ALC 655 codec (in Acer TravelMate 2410 serie laptop) + 1028 0179 Optiplex GX280 + 1028 0182 Latitude D610 Laptop + 1028 0188 Inspiron 6000 laptop + 103c 0944 Compaq NC6220 + 103c 099c NX6110/NC6120 + 103c 3006 DC7100 SFF(DX878AV) + 1458 a002 GA-8I915ME-G Mainboard + 152d 0745 Packard Bell A8550 Laptop + 1734 105a Scenic W620 + 266f 82801FB/FBM/FR/FW/FRW (ICH6 Family) IDE Controller + 103c 099c NX6110/NC6120 + 1043 80a6 P5GD1-VW Mainboard + 1458 266f GA-8I915ME-G Mainboard + 1462 7028 915P/G Neo2 + 1734 105c Scenic W620 + 2670 631xESB/632xESB/3100 Chipset LPC Interface Controller + 2680 631xESB/632xESB/3100 Chipset SATA Storage Controller IDE + 2681 631xESB/632xESB SATA Storage Controller AHCI + 2682 631xESB/632xESB SATA Storage Controller RAID + 2683 631xESB/632xESB SATA Storage Controller RAID + 2688 631xESB/632xESB/3100 Chipset UHCI USB Controller #1 + 2689 631xESB/632xESB/3100 Chipset UHCI USB Controller #2 + 268a 631xESB/632xESB/3100 Chipset UHCI USB Controller #3 + 268b 631xESB/632xESB/3100 Chipset UHCI USB Controller #4 + 268c 631xESB/632xESB/3100 Chipset EHCI USB2 Controller + 2690 631xESB/632xESB/3100 Chipset PCI Express Root Port 1 + 2692 631xESB/632xESB/3100 Chipset PCI Express Root Port 2 + 2694 631xESB/632xESB/3100 Chipset PCI Express Root Port 3 + 2696 631xESB/632xESB/3100 Chipset PCI Express Root Port 4 + 2698 631xESB/632xESB AC '97 Audio Controller + 2699 631xESB/632xESB AC '97 Modem Controller + 269a 631xESB/632xESB High Definition Audio Controller + 269b 631xESB/632xESB/3100 Chipset SMBus Controller + 269e 631xESB/632xESB IDE Controller + 2770 82945G/GZ/P/PL Memory Controller Hub + 107b 5048 E4500 + 8086 544e DeskTop Board D945GTP + 2771 82945G/GZ/P/PL PCI Express Root Port + 2772 82945G/GZ Integrated Graphics Controller + 8086 544e DeskTop Board D945GTP + 2774 82955X Memory Controller Hub + 2775 82955X PCI Express Root Port + 2776 82945G/GZ Integrated Graphics Controller + 2778 E7230/3000/3010 Memory Controller Hub + 2779 E7230/3000/3010 PCI Express Root Port + 277a 82975X/3010 PCI Express Root Port + 277c 82975X Memory Controller Hub + 277d 82975X PCI Express Root Port + 2782 82915G Integrated Graphics Controller + 1043 2582 P5GD1-VW Mainboard + 1734 105b Scenic W620 + 2792 Mobile 915GM/GMS/910GML Express Graphics Controller + 103c 099c NX6110/NC6120 + 1043 1881 GMA 900 915GM Integrated Graphics + 27a0 Mobile 945GM/PM/GMS/940GML and 945GT Express Memory Controller Hub + 17aa 2017 Thinkpad R60e model 0657 + 27a1 Mobile 945GM/PM/GMS/940GML and 945GT Express PCI Express Root Port + 27a2 Mobile 945GM/GMS/940GML Express Integrated Graphics Controller + 17aa 201a Thinkpad R60e model 0657 + 27a6 Mobile 945GM/GMS/940GML Express Integrated Graphics Controller + 17aa 201a Thinkpad R60e model 0657 + 27b0 82801GH (ICH7DH) LPC Interface Bridge + 27b8 82801GB/GR (ICH7 Family) LPC Interface Bridge + 107b 5048 E4500 + 8086 544e DeskTop Board D945GTP + 27b9 82801GBM (ICH7-M) LPC Interface Bridge + 17aa 2009 ThinkPad T60/R60 series + 27bd 82801GHM (ICH7-M DH) LPC Interface Bridge + 27c0 82801GB/GR/GH (ICH7 Family) Serial ATA Storage Controller IDE + 107b 5048 E4500 + 8086 544e DeskTop Board D945GTP + 27c1 82801GR/GH (ICH7 Family) Serial ATA Storage Controller AHCI + 27c3 82801GR/GH (ICH7 Family) Serial ATA Storage Controller RAID + 27c4 82801GBM/GHM (ICH7 Family) Serial ATA Storage Controller IDE + 27c5 82801GBM/GHM (ICH7 Family) Serial ATA Storage Controller AHCI + 17aa 200d Thinkpad R60e model 0657 + 27c6 82801GHM (ICH7-M DH) Serial ATA Storage Controller RAID + 27c8 82801G (ICH7 Family) USB UHCI #1 + 107b 5048 E4500 + 17aa 200a ThinkPad T60/R60 series + 8086 544e DeskTop Board D945GTP + 27c9 82801G (ICH7 Family) USB UHCI #2 + 107b 5048 E4500 + 17aa 200a ThinkPad T60/R60 series + 8086 544e DeskTop Board D945GTP + 27ca 82801G (ICH7 Family) USB UHCI #3 + 107b 5048 E4500 + 17aa 200a ThinkPad T60/R60 series + 8086 544e DeskTop Board D945GTP + 27cb 82801G (ICH7 Family) USB UHCI #4 + 107b 5048 E4500 + 17aa 200a ThinkPad T60/R60 series + 8086 544e DeskTop Board D945GTP + 27cc 82801G (ICH7 Family) USB2 EHCI Controller + 17aa 200b ThinkPad T60/R60 series + 8086 544e DeskTop Board D945GTP + 27d0 82801G (ICH7 Family) PCI Express Port 1 + 27d2 82801G (ICH7 Family) PCI Express Port 2 + 27d4 82801G (ICH7 Family) PCI Express Port 3 + 27d6 82801G (ICH7 Family) PCI Express Port 4 + 27d8 82801G (ICH7 Family) High Definition Audio Controller + 107b 5048 E4500 + 152d 0753 Softmodem + 17aa 2010 ThinkPad T60/R60 series + 27da 82801G (ICH7 Family) SMBus Controller + 17aa 200f ThinkPad T60/R60 series + 8086 544e DeskTop Board D945GTP + 27dc 82801G (ICH7 Family) LAN Controller + 8086 308d DeskTop Board D945GTP + 27dd 82801G (ICH7 Family) AC'97 Modem Controller + 27de 82801G (ICH7 Family) AC'97 Audio Controller + 27df 82801G (ICH7 Family) IDE Controller + 107b 5048 E4500 + 17aa 200c Thinkpad R60e model 0657 + 8086 544e DeskTop Board D945GTP + 27e0 82801GR/GH/GHM (ICH7 Family) PCI Express Port 5 + 27e2 82801GR/GH/GHM (ICH7 Family) PCI Express Port 6 + 2810 82801HB/HR (ICH8/R) LPC Interface Controller + 2811 Mobile LPC Interface Controller + 2812 82801HH (ICH8DH) LPC Interface Controller + 2814 82801HO (ICH8DO) LPC Interface Controller + 2815 Mobile LPC Interface Controller + 2820 82801H (ICH8 Family) 4 port SATA IDE Controller + 2821 82801HB (ICH8) SATA AHCI Controller + 2822 82801HR/HO/HH (ICH8R/DO/DH) SATA RAID Controller + 2824 82801HR/HO/HH (ICH8R/DO/DH) SATA AHCI Controller + 2825 82801H (ICH8 Family) 2 port SATA IDE Controller + 2828 Mobile SATA IDE Controller + 2829 Mobile SATA AHCI Controller + 282a Mobile SATA RAID Controller + 2830 82801H (ICH8 Family) USB UHCI #1 + 2831 82801H (ICH8 Family) USB UHCI #2 + 2832 82801H (ICH8 Family) USB UHCI #3 + 2834 82801H (ICH8 Family) USB UHCI #4 + 2835 82801H (ICH8 Family) USB UHCI #5 + 2836 82801H (ICH8 Family) USB2 EHCI #1 + 283a 82801H (ICH8 Family) USB2 EHCI #2 + 283e 82801H (ICH8 Family) SMBus Controller + 283f 82801H (ICH8 Family) PCI Express Port 1 + 2841 82801H (ICH8 Family) PCI Express Port 2 + 2843 82801H (ICH8 Family) PCI Express Port 3 + 2845 82801H (ICH8 Family) PCI Express Port 4 + 2847 82801H (ICH8 Family) PCI Express Port 5 + 2849 82801H (ICH8 Family) PCI Express Port 6 + 284b 82801H (ICH8 Family) HD Audio Controller + 284f 82801H (ICH8 Family) Thermal Reporting Device + 2850 Mobile IDE Controller + 2970 82946GZ/PL/GL Memory Controller Hub + 2971 82946GZ/PL/GL PCI Express Root Port + 2972 82946GZ/GL Integrated Graphics Controller + 2973 82946GZ/GL Integrated Graphics Controller + 2974 82946GZ/GL HECI Controller + 2975 82946GZ/GL HECI Controller + 2976 82946GZ/GL PT IDER Controller + 2977 82946GZ/GL KT Controller + 2980 965 G1 Memory Controller Hub + 2981 965 G1 PCI Express Root Port + 2982 965 G1 Integrated Graphics Controller + 2990 82Q963/Q965 Memory Controller Hub + 2991 82Q963/Q965 PCI Express Root Port + 2992 82Q963/Q965 Integrated Graphics Controller + 2993 82Q963/Q965 Integrated Graphics Controller + 2994 82Q963/Q965 HECI Controller + 2995 82Q963/Q965 HECI Controller + 2996 82Q963/Q965 PT IDER Controller + 2997 82Q963/Q965 KT Controller + 29a0 82P965/G965 Memory Controller Hub + 29a1 82P965/G965 PCI Express Root Port + 29a2 82G965 Integrated Graphics Controller + 29a3 82G965 Integrated Graphics Controller + 29a4 82P965/G965 HECI Controller + 29a5 82P965/G965 HECI Controller + 29a6 82P965/G965 PT IDER Controller + 29a7 82P965/G965 KT Controller + 2a00 Mobile Memory Controller Hub + 2a01 Mobile PCI Express Root Port + 2a02 Mobile Integrated Graphics Controller + 2a03 Mobile Integrated Graphics Controller + 2a04 Mobile HECI Controller + 2a05 Mobile HECI Controller + 2a06 Mobile PT IDER Controller + 2a07 Mobile KT Controller + 3092 Integrated RAID + 3200 GD31244 PCI-X SATA HBA + 3340 82855PM Processor to I/O Controller + 1025 005a TravelMate 290 + 103c 088c NC8000 laptop + 103c 0890 NC6000 laptop + 103c 08b0 tc1100 tablet + 3341 82855PM Processor to AGP Controller + 3500 6311ESB/6321ESB PCI Express Upstream Port + 3501 6310ESB PCI Express Upstream Port + 3504 6311ESB/6321ESB I/OxAPIC Interrupt Controller + 3505 6310ESB I/OxAPIC Interrupt Controller + 350c 6311ESB/6321ESB PCI Express to PCI-X Bridge + 350d 6310ESB PCI Express to PCI-X Bridge + 3510 6311ESB/6321ESB PCI Express Downstream Port E1 + 3511 6310ESB PCI Express Downstream Port E1 + 3514 6311ESB/6321ESB PCI Express Downstream Port E2 + 3515 6310ESB PCI Express Downstream Port E2 + 3518 6311ESB/6321ESB PCI Express Downstream Port E3 + 3519 6310ESB PCI Express Downstream Port E3 + 3575 82830 830 Chipset Host Bridge + 0e11 0030 Evo N600c + 1014 021d ThinkPad A/T/X Series + 104d 80e7 VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP + 3576 82830 830 Chipset AGP Bridge + 3577 82830 CGC [Chipset Graphics Controller] + 1014 0513 ThinkPad A/T/X Series + 3578 82830 830 Chipset Host Bridge + 3580 82852/82855 GM/GME/PM/GMV Processor to I/O Controller + 1014 055c Thinkpad R50e model 1634 + 1028 0139 Latitude D400 + 1028 0163 Latitude D505 + 1028 0196 Inspiron 5160 + 1734 1055 Amilo M1420 + 1775 10d0 V5D Single Board Computer + 1775 ce90 CE9 + 4c53 10b0 CL9 mainboard + 4c53 10e0 PSL09 PrPMC + 3581 82852/82855 GM/GME/PM/GMV Processor to AGP Controller + 1734 1055 Amilo M1420 + 3582 82852/855GM Integrated Graphics Device + 1014 0562 Thinkpad R50e model 1634 + 1028 0139 Latitude D400 + 1028 0163 Latitude D505 + 1775 10d0 V5D Single Board Computer VGA + 1775 ce90 CE9 + 4c53 10b0 CL9 mainboard + 4c53 10e0 PSL09 PrPMC + 3584 82852/82855 GM/GME/PM/GMV Processor to I/O Controller + 1014 055d Thinkpad R50e model 1634 + 1028 0139 Latitude D400 + 1028 0163 Latitude D505 + 1028 0196 Inspiron 5160 + 1734 1055 Amilo M1420 + 1775 10d0 V5D Single Board Computer + 1775 ce90 CE9 + 4c53 10b0 CL9 mainboard + 4c53 10e0 PSL09 PrPMC + 3585 82852/82855 GM/GME/PM/GMV Processor to I/O Controller + 1014 055e Thinkpad R50e model 1634 + 1028 0139 Latitude D400 + 1028 0163 Latitude D505 + 1028 0196 Inspiron 5160 + 1734 1055 Amilo M1420 + 1775 10d0 V5D Single Board Computer + 1775 ce90 CE9 + 4c53 10b0 CL9 mainboard + 4c53 10e0 PSL09 PrPMC + 3590 E7520 Memory Controller Hub + 1028 019a PowerEdge SC1425 + 1734 103e Primergy RX300 S2 + 4c53 10d0 Telum ASLP10 Processor AMC + 3591 E7525/E7520 Error Reporting Registers + 1028 0169 Precision 470 + 4c53 10d0 Telum ASLP10 Processor AMC + 3592 E7320 Memory Controller Hub + 3593 E7320 Error Reporting Registers + 3594 E7520 DMA Controller + 4c53 10d0 Telum ASLP10 Processor AMC + 3595 E7525/E7520/E7320 PCI Express Port A + 3596 E7525/E7520/E7320 PCI Express Port A1 + 3597 E7525/E7520 PCI Express Port B + 3598 E7520 PCI Express Port B1 + 3599 E7520 PCI Express Port C + 359a E7520 PCI Express Port C1 + 359b E7525/E7520/E7320 Extended Configuration Registers + 359e E7525 Memory Controller Hub + 1028 0169 Precision 470 + 35b0 3100 Chipset Memory I/O Controller Hub + 35b1 3100 DRAM Controller Error Reporting Registers + 35b5 3100 Chipset Enhanced DMA Controller + 35b6 3100 Chipset PCI Express Port A + 35b7 3100 Chipset PCI Express Port A1 + 35c8 3100 Extended Configuration Test Overflow Registers + 4220 PRO/Wireless 2200BG Network Connection + 4222 PRO/Wireless 3945ABG Network Connection + 8086 1005 PRO/Wireless 3945BG Network Connection + 8086 1034 PRO/Wireless 3945BG Network Connection + 8086 1044 PRO/Wireless 3945BG Network Connection + 4223 PRO/Wireless 2915ABG Network Connection + 1351 103c Compaq NC6220 + 4224 PRO/Wireless 2915ABG Network Connection + 4227 PRO/Wireless 3945ABG Network Connection + 8086 1011 Thinkpad X60s, R60e model 0657 + 8086 1014 PRO/Wireless 3945BG Network Connection + 5001 Pro/DSL 2100 Modem + 5200 EtherExpress PRO/100 Intelligent Server + 5201 EtherExpress PRO/100 Intelligent Server + 8086 0001 EtherExpress PRO/100 Server Ethernet Adapter + 530d 80310 IOP [IO Processor] + 7000 82371SB PIIX3 ISA [Natoma/Triton II] + 7010 82371SB PIIX3 IDE [Natoma/Triton II] + 7020 82371SB PIIX3 USB [Natoma/Triton II] + 7030 430VX - 82437VX TVX [Triton VX] + 7050 Intercast Video Capture Card + 7051 PB 642365-003 (Business Video Conferencing Card) + 7100 430TX - 82439TX MTXC + 7110 82371AB/EB/MB PIIX4 ISA + 15ad 1976 virtualHW v3 + 7111 82371AB/EB/MB PIIX4 IDE + 15ad 1976 virtualHW v3 + 7112 82371AB/EB/MB PIIX4 USB + 15ad 1976 virtualHW v3 + 7113 82371AB/EB/MB PIIX4 ACPI + 15ad 1976 virtualHW v3 + 7120 82810 GMCH [Graphics Memory Controller Hub] + 4c53 1040 CL7 mainboard + 4c53 1060 PC7 mainboard + 7121 82810 CGC [Chipset Graphics Controller] + 4c53 1040 CL7 mainboard + 4c53 1060 PC7 mainboard + 8086 4341 Cayman (CA810) Mainboard + 7122 82810 DC-100 GMCH [Graphics Memory Controller Hub] + 7123 82810 DC-100 CGC [Chipset Graphics Controller] + 7124 82810E DC-133 GMCH [Graphics Memory Controller Hub] + 7125 82810E DC-133 CGC [Chipset Graphics Controller] + 7126 82810 DC-133 System and Graphics Controller + 7128 82810-M DC-100 System and Graphics Controller + 712a 82810-M DC-133 System and Graphics Controller + 7180 440LX/EX - 82443LX/EX Host bridge + 7181 440LX/EX - 82443LX/EX AGP bridge + 7190 440BX/ZX/DX - 82443BX/ZX/DX Host bridge + 0e11 0500 Armada 1750 Laptop System Chipset + 0e11 b110 Armada M700/E500 + 1028 008e PowerEdge 1300 mainboard + 1179 0001 Toshiba Tecra 8100 Laptop System Chipset + 15ad 1976 virtualHW v3 + 4c53 1050 CT7 mainboard + 4c53 1051 CE7 mainboard + 7191 440BX/ZX/DX - 82443BX/ZX/DX AGP bridge + 1028 008e PowerEdge 1300 mainboard + 7192 440BX/ZX/DX - 82443BX/ZX/DX Host bridge (AGP disabled) + 0e11 0460 Armada 1700 Laptop System Chipset + 4c53 1000 CC7/CR7/CP7/VC7/VP7/VR7 mainboard + 7194 82440MX Host Bridge + 1033 0000 Versa Note Vxi + 4c53 10a0 CA3/CR3 mainboard + 7195 82440MX AC'97 Audio Controller + 1033 80cc Versa Note VXi + 10cf 1099 QSound_SigmaTel Stac97 PCI Audio + 11d4 0040 SoundMAX Integrated Digital Audio + 11d4 0048 SoundMAX Integrated Digital Audio + 7196 82440MX AC'97 Modem Controller + 7198 82440MX ISA Bridge + 7199 82440MX EIDE Controller + 719a 82440MX USB Universal Host Controller + 719b 82440MX Power Management Controller + 71a0 440GX - 82443GX Host bridge + 4c53 1050 CT7 mainboard + 4c53 1051 CE7 mainboard + 71a1 440GX - 82443GX AGP bridge + 71a2 440GX - 82443GX Host bridge (AGP disabled) + 4c53 1000 CC7/CR7/CP7/VC7/VP7/VR7 mainboard + 7600 82372FB PIIX5 ISA + 7601 82372FB PIIX5 IDE + 7602 82372FB PIIX5 USB + 7603 82372FB PIIX5 SMBus + 7800 82740 (i740) AGP Graphics Accelerator + 003d 0008 Starfighter AGP + 003d 000b Starfighter AGP + 1092 0100 Stealth II G460 + 10b4 201a Lightspeed 740 + 10b4 202f Lightspeed 740 + 8086 0000 Terminator 2x/i + 8086 0100 Intel740 Graphics Accelerator + 84c4 450KX/GX [Orion] - 82454KX/GX PCI bridge + 84c5 450KX/GX [Orion] - 82453KX/GX Memory controller + 84ca 450NX - 82451NX Memory & I/O Controller + 84cb 450NX - 82454NX/84460GX PCI Expander Bridge + 84e0 460GX - 84460GX System Address Controller (SAC) + 84e1 460GX - 84460GX System Data Controller (SDC) + 84e2 460GX - 84460GX AGP Bridge (GXB function 2) + 84e3 460GX - 84460GX Memory Address Controller (MAC) + 84e4 460GX - 84460GX Memory Data Controller (MDC) + 84e6 460GX - 82466GX Wide and fast PCI eXpander Bridge (WXB) + 84ea 460GX - 84460GX AGP Bridge (GXB function 1) + 8500 IXP4XX Network Processor (IXP420/421/422/425/IXC1100) + 1993 0ded mGuard-PCI AV#2 + 1993 0dee mGuard-PCI AV#1 + 1993 0def mGuard-PCI AV#0 + 9000 IXP2000 Family Network Processor + 9001 IXP2400 Network Processor + 9002 IXP2300 Network Processor + 9004 IXP2800 Network Processor + 9621 Integrated RAID + 9622 Integrated RAID + 9641 Integrated RAID + 96a1 Integrated RAID + b152 21152 PCI-to-PCI Bridge +# observed, and documented in Intel revision note; new mask of 1011:0026 + b154 21154 PCI-to-PCI Bridge + b555 21555 Non transparent PCI-to-PCI Bridge + 12c7 5005 SS7HD PCI Adaptor Card + 12c7 5006 SS7HDC cPCI Adaptor Card + 12d9 000a PCI VoIP Gateway + 4c53 1050 CT7 mainboard + 4c53 1051 CE7 mainboard + e4bf 1000 CC8-1-BLUES +8401 TRENDware International Inc. +8686 ScaleMP + 1010 vSMPowered system controller [vSMP CTL] +8800 Trigem Computer Inc. + 2008 Video assistent component +8866 T-Square Design Inc. +8888 Silicon Magic +8912 TRX +# 8c4a is not Winbond but there is a board misprogrammed +8c4a Winbond + 1980 W89C940 misprogrammed [ne2k] +8e0e Computone Corporation +8e2e KTI + 3000 ET32P2 +9004 Adaptec + 0078 AHA-2940U_CN + 1078 AIC-7810 + 1160 AIC-1160 [Family Fibre Channel Adapter] + 2178 AIC-7821 + 3860 AHA-2930CU + 3b78 AHA-4844W/4844UW + 5075 AIC-755x + 5078 AHA-7850 + 9004 7850 AHA-2904/Integrated AIC-7850 + 5175 AIC-755x + 5178 AIC-7851 + 5275 AIC-755x + 5278 AIC-7852 + 5375 AIC-755x + 5378 AIC-7850 + 5475 AIC-755x + 5478 AIC-7850 + 5575 AVA-2930 + 5578 AIC-7855 + 5647 ANA-7711 TCP Offload Engine + 9004 7710 ANA-7711F TCP Offload Engine - Optical + 9004 7711 ANA-7711LP TCP Offload Engine - Copper + 5675 AIC-755x + 5678 AIC-7856 + 5775 AIC-755x + 5778 AIC-7850 + 5800 AIC-5800 + 5900 ANA-5910/5930/5940 ATM155 & 25 LAN Adapter + 5905 ANA-5910A/5930A/5940A ATM Adapter + 6038 AIC-3860 + 6075 AIC-1480 / APA-1480 + 9004 7560 AIC-1480 / APA-1480 Cardbus + 6078 AIC-7860 + 6178 AIC-7861 + 9004 7861 AHA-2940AU Single + 6278 AIC-7860 + 6378 AIC-7860 + 6478 AIC-786x + 6578 AIC-786x + 6678 AIC-786x + 6778 AIC-786x + 6915 ANA620xx/ANA69011A + 9004 0008 ANA69011A/TX 10/100 + 9004 0009 ANA69011A/TX 10/100 + 9004 0010 ANA62022 2-port 10/100 + 9004 0018 ANA62044 4-port 10/100 + 9004 0019 ANA62044 4-port 10/100 + 9004 0020 ANA62022 2-port 10/100 + 9004 0028 ANA69011A/TX 10/100 + 9004 8008 ANA69011A/TX 64 bit 10/100 + 9004 8009 ANA69011A/TX 64 bit 10/100 + 9004 8010 ANA62022 2-port 64 bit 10/100 + 9004 8018 ANA62044 4-port 64 bit 10/100 + 9004 8019 ANA62044 4-port 64 bit 10/100 + 9004 8020 ANA62022 2-port 64 bit 10/100 + 9004 8028 ANA69011A/TX 64 bit 10/100 + 7078 AHA-294x / AIC-7870 + 7178 AHA-2940/2940W / AIC-7871 + 7278 AHA-3940/3940W / AIC-7872 + 7378 AHA-3985 / AIC-7873 + 7478 AHA-2944/2944W / AIC-7874 + 7578 AHA-3944/3944W / AIC-7875 + 7678 AHA-4944W/UW / AIC-7876 + 7710 ANA-7711F Network Accelerator Card (NAC) - Optical + 7711 ANA-7711C Network Accelerator Card (NAC) - Copper + 7778 AIC-787x + 7810 AIC-7810 + 7815 AIC-7815 RAID+Memory Controller IC + 9004 7815 ARO-1130U2 RAID Controller + 9004 7840 AIC-7815 RAID+Memory Controller IC + 7850 AIC-7850 + 7855 AHA-2930 + 7860 AIC-7860 + 7870 AIC-7870 + 7871 AHA-2940 + 7872 AHA-3940 + 7873 AHA-3980 + 7874 AHA-2944 + 7880 AIC-7880P + 7890 AIC-7890 + 7891 AIC-789x + 7892 AIC-789x + 7893 AIC-789x + 7894 AIC-789x + 7895 AHA-2940U/UW / AHA-39xx / AIC-7895 + 9004 7890 AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B + 9004 7891 AHA-2940U/2940UW Dual + 9004 7892 AHA-3940AU/AUW/AUWD/UWD + 9004 7894 AHA-3944AUWD + 9004 7895 AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B + 9004 7896 AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B + 9004 7897 AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B + 7896 AIC-789x + 7897 AIC-789x + 8078 AIC-7880U + 9004 7880 AIC-7880P Ultra/Ultra Wide SCSI Chipset + 8178 AHA-2940U/UW/D / AIC-7881U + 9004 7881 AHA-2940UW SCSI Host Adapter + 8278 AHA-3940U/UW/UWD / AIC-7882U + 8378 AHA-3940U/UW / AIC-7883U + 8478 AHA-2944UW / AIC-7884U + 8578 AHA-3944U/UWD / AIC-7885 + 8678 AHA-4944UW / AIC-7886 + 8778 AHA-2940UW Pro / AIC-788x + 9004 7887 2940UW Pro Ultra-Wide SCSI Controller + 8878 AHA-2930UW / AIC-7888 + 9004 7888 AHA-2930UW SCSI Controller + 8b78 ABA-1030 + ec78 AHA-4944W/UW +9005 Adaptec + 0010 AHA-2940U2/U2W + 9005 2180 AHA-2940U2 SCSI Controller + 9005 8100 AHA-2940U2B SCSI Controller + 9005 a100 AHA-2940U2B SCSI Controller + 9005 a180 AHA-2940U2W SCSI Controller + 9005 e100 AHA-2950U2B SCSI Controller + 0011 AHA-2930U2 + 0013 78902 + 9005 0003 AAA-131U2 Array1000 1 Channel RAID Controller + 9005 000f AIC7890_ARO + 001f AHA-2940U2/U2W / 7890/7891 + 9005 000f 2940U2W SCSI Controller + 9005 a180 2940U2W SCSI Controller + 0020 AIC-7890 + 002f AIC-7890 + 0030 AIC-7890 + 003f AIC-7890 + 0050 AHA-3940U2x/395U2x + 9005 f500 AHA-3950U2B + 9005 ffff AHA-3950U2B + 0051 AHA-3950U2D + 9005 b500 AHA-3950U2D + 0053 AIC-7896 SCSI Controller + 9005 ffff AIC-7896 SCSI Controller mainboard implementation + 005f AIC-7896U2/7897U2 + 0080 AIC-7892A U160/m + 0e11 e2a0 Compaq 64-Bit/66MHz Wide Ultra3 SCSI Adapter + 9005 6220 AHA-29160C + 9005 62a0 29160N Ultra160 SCSI Controller + 9005 e220 29160LP Low Profile Ultra160 SCSI Controller + 9005 e2a0 29160 Ultra160 SCSI Controller + 0081 AIC-7892B U160/m + 9005 62a1 19160 Ultra160 SCSI Controller + 0083 AIC-7892D U160/m + 008f AIC-7892P U160/m + 1179 0001 Magnia Z310 + 15d9 9005 Onboard SCSI Host Adapter + 00c0 AHA-3960D / AIC-7899A U160/m + 0e11 f620 Compaq 64-Bit/66MHz Dual Channel Wide Ultra3 SCSI Adapter + 9005 f620 AHA-3960D U160/m + 00c1 AIC-7899B U160/m + 00c3 AIC-7899D U160/m + 00c5 RAID subsystem HBA + 1028 00c5 PowerEdge 2400,2500,2550,4400 + 00cf AIC-7899P U160/m + 1028 00ce PowerEdge 1400 + 1028 00d1 PowerEdge 2550 + 1028 00d9 PowerEdge 2500 + 10f1 2462 Thunder K7 S2462 + 15d9 9005 Onboard SCSI Host Adapter + 8086 3411 SDS2 Mainboard + 0241 Serial ATA II RAID 1420SA + 0250 ServeRAID Controller + 1014 0279 ServeRAID-xx + 1014 028c ServeRAID-xx + 0279 ServeRAID 6M + 0283 AAC-RAID + 9005 0283 Catapult + 0284 AAC-RAID + 9005 0284 Tomcat + 0285 AAC-RAID + 0e11 0295 SATA 6Ch (Bearcat) + 1014 02f2 ServeRAID 8i + 1028 0287 PowerEdge Expandable RAID Controller 320/DC + 1028 0291 CERC SATA RAID 2 PCI SATA 6ch (DellCorsair) + 103c 3227 AAR-2610SA + 17aa 0286 Legend S220 (Legend Crusader) + 17aa 0287 Legend S230 (Legend Vulcan) + 9005 0285 2200S (Vulcan) + 9005 0286 2120S (Crusader) + 9005 0287 2200S (Vulcan-2m) + 9005 0288 3230S (Harrier) + 9005 0289 3240S (Tornado) +# Some early versions reported 2020S + 9005 028a ASR-2020ZCR +# Some early versions reported 2025S + 9005 028b ASR-2025ZCR (Terminator) + 9005 028e ASR-2020SA (Skyhawk) + 9005 028f ASR-2025SA + 9005 0290 AAR-2410SA PCI SATA 4ch (Jaguar II) + 9005 0292 AAR-2810SA PCI SATA 8ch (Corsair-8) + 9005 0293 AAR-21610SA PCI SATA 16ch (Corsair-16) + 9005 0294 ESD SO-DIMM PCI-X SATA ZCR (Prowler) + 9005 0296 ASR-2240S + 9005 0297 ASR-4005SAS + 9005 0298 ASR-4000SAS + 9005 0299 ASR-4800SAS + 9005 029a 4805SAS + 9005 02b5 ASR5800 + 9005 02b6 ASR5805 + 9005 02b7 ASR5808 + 0286 AAC-RAID (Rocket) + 1014 034d 8s + 1014 9540 ServeRAID 8k/8k-l4 + 1014 9580 ServeRAID 8k/8k-l8 + 9005 028c ASR-2230S + ASR-2230SLP PCI-X (Lancer) + 9005 028d ASR-2130S + 9005 029b ASR-2820SA + 9005 029c ASR-2620SA + 9005 029d ASR-2420SA + 9005 029e ICP ICP9024R0 + 9005 029f ICP ICP9014R0 + 9005 02a0 ICP ICP9047MA + 9005 02a1 ICP ICP9087MA + 9005 02a2 3800SAS + 9005 02a3 ICP ICP5445AU + 9005 02a4 ICP ICP9085LI + 9005 02a5 ICP ICP5085BR + 9005 02a6 ICP9067MA + 9005 02a7 3805SAS + 9005 02a8 3400SAS + 9005 02a9 ICP ICP5085AU + 9005 02aa ICP ICP5045AU + 9005 02ac 1800SAS + 9005 02b3 ASR-2400SAS + 9005 02b4 ICP ICP5045AL + 9005 0800 Callisto + 0410 AIC-9410W SAS (Razor HBA RAID) + 9005 0410 ASC-48300(Spirit RAID) + 9005 0411 ASC-58300 (Oakmont RAID) + 0412 AIC-9410W SAS (Razor HBA non-RAID) + 9005 0412 ASC-48300 (Spirit non-RAID) + 9005 0413 ASC-58300 (Oakmont non-RAID) + 041e AIC-9410W SAS (Razor ASIC non-RAID) + 041f AIC-9410W SAS (Razor ASIC RAID) + 9005 041f AIC-9410W SAS (Razor ASIC RAID) + 0430 AIC-9405W SAS (Razor-Lite HBA RAID) + 9005 0430 ASC-44300 (Spirit-Lite RAID) + 0432 AIC-9405W SAS (Razor-Lite HBA non-RAID) + 9005 0432 ASC-44300 (Spirit-Lite non-RAID) + 043e AIC-9405W SAS (Razor-Lite ASIC non-RAID) + 043f AIC-9405W SAS (Razor-Lite ASIC RAID) + 0500 Obsidian chipset SCSI controller + 1014 02c1 PCI-X DDR 3Gb SAS Adapter (572A/572C) + 1014 02c2 PCI-X DDR 3Gb SAS RAID Adapter (572B/572D) + 0503 Scamp chipset SCSI controller + 1014 02bf Quad Channel PCI-X DDR U320 SCSI RAID Adapter (571E) + 1014 02d5 Quad Channel PCI-X DDR U320 SCSI RAID Adapter (571F) + 0910 AUA-3100B + 091e AUA-3100B + 8000 ASC-29320A U320 + 800f AIC-7901 U320 + 8010 ASC-39320 U320 + 8011 ASC-39320D + 0e11 00ac ASC-39320D U320 + 9005 0041 ASC-39320D U320 + 8012 ASC-29320 U320 + 8013 ASC-29320B U320 + 8014 ASC-29320LP U320 + 8015 ASC-39320B U320 + 8016 ASC-39320A U320 + 8017 ASC-29320ALP U320 + 801c ASC-39320D U320 + 801d AIC-7902B U320 + 801e AIC-7901A U320 + 801f AIC-7902 U320 + 1734 1011 Primergy RX300 + 8080 ASC-29320A U320 w/HostRAID + 808f AIC-7901 U320 w/HostRAID + 8090 ASC-39320 U320 w/HostRAID + 8091 ASC-39320D U320 w/HostRAID + 8092 ASC-29320 U320 w/HostRAID + 8093 ASC-29320B U320 w/HostRAID + 8094 ASC-29320LP U320 w/HostRAID + 8095 ASC-39320(B) U320 w/HostRAID + 8096 ASC-39320A U320 w/HostRAID + 8097 ASC-29320ALP U320 w/HostRAID + 809c ASC-39320D(B) U320 w/HostRAID + 809d AIC-7902(B) U320 w/HostRAID + 809e AIC-7901A U320 w/HostRAID + 809f AIC-7902 U320 w/HostRAID +907f Atronics + 2015 IDE-2015PL +919a Gigapixel Corp +9412 Holtek + 6565 6565 +9699 Omni Media Technology Inc + 6565 6565 +9710 NetMos Technology + 7780 USB IRDA-port + 9805 PCI 1 port parallel adapter + 9815 PCI 9815 Multi-I/O Controller + 1000 0020 2P0S (2 port parallel adaptor) + 9835 PCI 9835 Multi-I/O Controller + 1000 0002 2S (16C550 UART) + 1000 0012 1P2S + 9845 PCI 9845 Multi-I/O Controller + 1000 0004 0P4S (4 port 16550A serial card) + 1000 0006 0P6S (6 port 16550a serial card) + 9855 PCI 9855 Multi-I/O Controller + 1000 0014 1P4S +9902 Stargen Inc. + 0001 SG2010 PCI over Starfabric Bridge + 0002 SG2010 PCI to Starfabric Gateway + 0003 SG1010 Starfabric Switch and PCI Bridge +a0a0 AOPEN Inc. +a0f1 UNISYS Corporation +a200 NEC Corporation +a259 Hewlett Packard +a25b Hewlett Packard GmbH PL24-MKT +a304 Sony +a727 3Com Corporation + 0013 3CRPAG175 Wireless PC Card +aa42 Scitex Digital Video +ac1e Digital Receiver Technology Inc +ac3d Actuality Systems +aecb Adrienne Electronics Corporation + 6250 VITC/LTC Timecode Reader card [PCI-VLTC/RDR] +affe Sirrix AG security technologies + 02e1 PCI2E1 2-port ISDN E1 interface + dead Sirrix.PCI4S0 4-port ISDN S0 interface +# Not registered officially +b10b Uakron PCI Project +b1b3 Shiva Europe Limited +# Pinnacle should be 11bd, but they got it wrong several times --mj +bd11 Pinnacle Systems, Inc. (Wrong ID) +c001 TSI Telsys +c0a9 Micron/Crucial Technology +c0de Motorola +c0fe Motion Engineering, Inc. +ca50 Varian Australia Pty Ltd +cafe Chrysalis-ITS + 0003 Luna K3 Hardware Security Module +cccc Catapult Communications +ccec Curtiss-Wright Controls Embedded Computing +cddd Tyzx, Inc. + 0101 DeepSea 1 High Speed Stereo Vision Frame Grabber + 0200 DeepSea 2 High Speed Stereo Vision Frame Grabber +d161 Digium, Inc. + 0205 Wildcard TE205P + 0210 Wildcard TE210P + 0405 Wildcard TE405P Quad-Span togglable E1/T1/J1 card 5.0v + 0406 Wildcard TE406P Quad-Span togglable E1/T1/J1 echo cancellation card 5.0v + 0410 Wildcard TE410P Quad-Span togglable E1/T1/J1 card 3.3v + 0411 Wildcard TE411P Quad-Span togglable E1/T1/J1 echo cancellation card 3.3v + 2400 Wildcard TDM2400P +d4d4 Dy4 Systems Inc + 0601 PCI Mezzanine Card +d531 I+ME ACTIA GmbH +d84d Exsys +dead Indigita Corporation +deaf Middle Digital Inc. + 9050 PC Weasel Virtual VGA + 9051 PC Weasel Serial Port + 9052 PC Weasel Watchdog Timer +e000 Winbond + e000 W89C940 +e159 Tiger Jet Network Inc. + 0001 Tiger3XX Modem/ISDN interface + 0059 0001 128k ISDN-S/T Adapter + 0059 0003 128k ISDN-U Adapter + 00a7 0001 TELES.S0/PCI 2.x ISDN Adapter + 8086 0003 Digium X100P/X101P analogue PSTN FXO interface + 0002 Tiger100APC ISDN chipset +e4bf EKF Elektronik GmbH +e55e Essence Technology, Inc. +ea01 Eagle Technology + 000a PCI-773 Temperature Card + 0032 PCI-730 & PC104P-30 Card + 003e PCI-762 Opto-Isolator Card + 0041 PCI-763 Reed Relay Card + 0043 PCI-769 Opto-Isolator Reed Relay Combo Card + 0046 PCI-766 Analog Output Card + 0052 PCI-703 Analog I/O Card + 0800 PCI-800 Digital I/O Card +# The main chip of all these devices is by Xilinx -> It could also be a Xilinx ID. +ea60 RME + 9896 Digi32 + 9897 Digi32 Pro + 9898 Digi32/8 +eabb Aashima Technology B.V. +eace Endace Measurement Systems, Ltd + 3100 DAG 3.10 OC-3/OC-12 + 3200 DAG 3.2x OC-3/OC-12 + 320e DAG 3.2E Fast Ethernet + 340e DAG 3.4E Fast Ethernet + 341e DAG 3.41E Fast Ethernet + 3500 DAG 3.5 OC-3/OC-12 + 351c DAG 3.5ECM Fast Ethernet + 4100 DAG 4.10 OC-48 + 4110 DAG 4.11 OC-48 + 4220 DAG 4.2 OC-48 + 422e DAG 4.2E Dual Gigabit Ethernet +ec80 Belkin Corporation + ec00 F5D6000 +ecc0 Echo Digital Audio Corporation +edd8 ARK Logic Inc + a091 1000PV [Stingray] + a099 2000PV [Stingray] + a0a1 2000MT + a0a9 2000MI +f1d0 AJA Video + c0fe Xena HS/HD-R + c0ff Kona/Xena 2 + cafe Kona SD + cfee Xena LS/SD-22-DA/SD-DA + dcaf Kona HD + dfee Xena HD-DA + efac Xena SD-MM/SD-22-MM + facd Xena HD-MM +fa57 Interagon AS + 0001 PMC [Pattern Matching Chip] +fab7 Fabric7 Systems, Inc. +febd Ultraview Corp. +# Nee Epigram +feda Broadcom Inc + a0fa BCM4210 iLine10 HomePNA 2.0 + a10e BCM4230 iLine10 HomePNA 2.0 +fede Fedetec Inc. + 0003 TABIC PCI v3 +fffd XenSource, Inc. + 0101 PCI Event Channel Controller +fffe VMWare Inc + 0405 Virtual SVGA 4.0 + 0710 Virtual SVGA +ffff Illegal Vendor ID + + +# List of known device classes, subclasses and programming interfaces + +# Syntax: +# C class class_name +# subclass subclass_name <-- single tab +# prog-if prog-if_name <-- two tabs + +C 00 Unclassified device + 00 Non-VGA unclassified device + 01 VGA compatible unclassified device +C 01 Mass storage controller + 00 SCSI storage controller + 01 IDE interface + 02 Floppy disk controller + 03 IPI bus controller + 04 RAID bus controller + 05 ATA controller + 20 ADMA single stepping + 40 ADMA continuous operation + 06 SATA controller + 00 Vendor specific + 01 AHCI 1.0 + 07 Serial Attached SCSI controller + 80 Mass storage controller +C 02 Network controller + 00 Ethernet controller + 01 Token ring network controller + 02 FDDI network controller + 03 ATM network controller + 04 ISDN controller + 80 Network controller +C 03 Display controller + 00 VGA compatible controller + 00 VGA + 01 8514 + 01 XGA compatible controller + 02 3D controller + 80 Display controller +C 04 Multimedia controller + 00 Multimedia video controller + 01 Multimedia audio controller + 02 Computer telephony device + 03 Audio device + 80 Multimedia controller +C 05 Memory controller + 00 RAM memory + 01 FLASH memory + 80 Memory controller +C 06 Bridge + 00 Host bridge + 01 ISA bridge + 02 EISA bridge + 03 MicroChannel bridge + 04 PCI bridge + 00 Normal decode + 01 Subtractive decode + 05 PCMCIA bridge + 06 NuBus bridge + 07 CardBus bridge + 08 RACEway bridge + 00 Transparent mode + 01 Endpoint mode + 09 Semi-transparent PCI-to-PCI bridge + 40 Primary bus towards host CPU + 80 Secondary bus towards host CPU + 0a InfiniBand to PCI host bridge + 80 Bridge +C 07 Communication controller + 00 Serial controller + 00 8250 + 01 16450 + 02 16550 + 03 16650 + 04 16750 + 05 16850 + 06 16950 + 01 Parallel controller + 00 SPP + 01 BiDir + 02 ECP + 03 IEEE1284 + fe IEEE1284 Target + 02 Multiport serial controller + 03 Modem + 00 Generic + 01 Hayes/16450 + 02 Hayes/16550 + 03 Hayes/16650 + 04 Hayes/16750 + 80 Communication controller +C 08 Generic system peripheral + 00 PIC + 00 8259 + 01 ISA PIC + 02 EISA PIC + 10 IO-APIC + 20 IO(X)-APIC + 01 DMA controller + 00 8237 + 01 ISA DMA + 02 EISA DMA + 02 Timer + 00 8254 + 01 ISA Timer + 02 EISA Timers + 03 RTC + 00 Generic + 01 ISA RTC + 04 PCI Hot-plug controller + 80 System peripheral +C 09 Input device controller + 00 Keyboard controller + 01 Digitizer Pen + 02 Mouse controller + 03 Scanner controller + 04 Gameport controller + 00 Generic + 10 Extended + 80 Input device controller +C 0a Docking station + 00 Generic Docking Station + 80 Docking Station +C 0b Processor + 00 386 + 01 486 + 02 Pentium + 10 Alpha + 20 Power PC + 30 MIPS + 40 Co-processor +C 0c Serial bus controller + 00 FireWire (IEEE 1394) + 00 Generic + 10 OHCI + 01 ACCESS Bus + 02 SSA + 03 USB Controller + 00 UHCI + 10 OHCI + 20 EHCI + 80 Unspecified + fe USB Device + 04 Fibre Channel + 05 SMBus + 06 InfiniBand +C 0d Wireless controller + 00 IRDA controller + 01 Consumer IR controller + 10 RF controller + 80 Wireless controller +C 0e Intelligent controller + 00 I2O +C 0f Satellite communications controller + 00 Satellite TV controller + 01 Satellite audio communication controller + 03 Satellite voice communication controller + 04 Satellite data communication controller +C 10 Encryption controller + 00 Network and computing encryption device + 10 Entertainment encryption device + 80 Encryption controller +C 11 Signal processing controller + 00 DPIO module + 01 Performance counters + 10 Communication synchronizer + 80 Signal processing controller diff --git a/hw/xfree86/scanpci/pciid2c.pl b/hw/xfree86/scanpci/pciid2c.pl new file mode 100644 index 000000000..b8947ed05 --- /dev/null +++ b/hw/xfree86/scanpci/pciid2c.pl @@ -0,0 +1,388 @@ +#!/usr/bin/perl + +# $XdotOrg$ + +# Automatically generate the data structures for PCI vendor/device lists +# from the pci.ids file. +# +# It should be run as: +# +# perl pciid2c.pl ../common/xf86PciInfo.h < pci.ids > xf86PciStdIds.h +# +# +# Copyright © 2002 by The XFree86 Project, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# Except as contained in this notice, the name of the copyright holder(s) +# and author(s) shall not be used in advertising or otherwise to promote +# the sale, use or other dealings in this Software without prior written +# authorization from the copyright holder(s) and author(s). +# + +# +# Author: David Dawes +# +# $XFree86: xc/programs/Xserver/hw/xfree86/scanpci/pciid2c.pl,v 1.3 2003/08/24 17:37:10 dawes Exp $ +# + +if (@ARGV[0]) { + $infofile = @ARGV[0]; +} + +# +# The basic pci.ids format is: +# - Vendor lines start with four (lower case) hex digits +# - Device lines start with one tab followed by four hex digits +# - Subsystem lines start with two tabs followed by two sets of four +# hex digits. +# - Class overrides for devices start with two tabs followed by a "C", +# followed by four hex digits with the class/subclass value. +# - Class lines start with a "C". +# - Comment lines start with a '#'. +# - Blank lines are ignored. +# +# We allow for extra lines to be appended to modify existing entries or +# add new ones. To add/modify Device entries without modifying the +# Vendor name, a special vendor name of '"' is used (mnemonic: "ditto"). +# Similarly for adding subsystem names without modifying (or adding) +# a corresponding device entry. To rename an existing entry, simply +# provide the new name. To remove an existing entry, use the special +# name '-'. +# + +while () { + # Process data lines + if (/^([0-9a-f]{4})\s+(.*)/) { + $vendor = $1; + if ($2 eq '-') { + delete($vendors{$vendor}); + } elsif ($2 ne '"') { + $vendors{$vendor} = $2; + # Remove " characters + $vendors{$vendor} =~ s/"//g; + # Remove multiple "?" sequences to avoid trigraphs + $vendors{$vendor} =~ s/\?+/\?/g; + } + } elsif (/^\t([0-9a-f]{4})\s+(.*)/) { + $device = $1; + if ($2 eq '-') { + delete($devices{$vendor}{$device}); + } elsif ($2 ne '"') { + $devices{$vendor}{$device} = $2; + # Remove " characters + $devices{$vendor}{$device} =~ s/"//g; + # Remove multiple "?" sequences to avoid trigraphs + $devices{$vendor}{$device} =~ s/\?+/\?/g; + } + } elsif (/^\t\t([0-9a-f]{4})\s+([0-9a-f]{4})\s+(.*)/) { + $v = $1; + $s = $2; + if ($3 eq '-') { + delete($subsystems{$v}{$s}); + delete($devsubsystems{$vendor}{$device}{"$v-$s"}); + } elsif ($3 ne '"') { + if ($subsystems{$v}{$s}) { + #print STDERR "Duplicate subsytem: $v, $s, \"$subsystems{$v}{$s}\", \"$3\"\n"; + } + $subsystems{$v}{$s} = $3; + # Remove " characters + $subsystems{$v}{$s} =~ s/"//g; + # Remove multiple "?" sequences to avoid trigraphs + $subsystems{$v}{$s} =~ s/\?+/\?/g; + $devsubsystems{$vendor}{$device}{"$v-$s"} = $subsystems{$v}{$s}; + } + } elsif (/^\t\tC\s+([0-9a-f]{4})/) { + $classes{$vendor}{$device} = $1; + } + # Ignore all other lines. +} + +# Find which vendors are "video" vendors. +if ($infofile) { + open(INFO, "<$infofile") || die "Can't open $infofile"; + while () { + if (/^#define\s+PCI_VENDOR_.*0x([0-9a-fA-F]{4})/) { + $vendor = $1; + $vendor =~ tr/A-F/a-f/; + $video{$vendor} = 1; + } + } +} + +# +# This layout is quite different from that used in the old xf86PciInfo.h +# file. One main difference is that the list is initialised at runtime. +# It's currently a flat list. This could be improved. +# + +# Print out header information. + +$proj = "XdotOrg"; +print " +/* + * THIS FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + * + * It is generated by pciid2c.pl using data from the following files: + * + * ../etc/pci.ids + * ../etc/extrapci.ids + * ../common/xf86PciInfo.h + */ + +/* + * Copyright © 2002 by the XFree86 Project, Inc. + * + * The pci.ids file and the data it contains are from the Linux PCI ID's + * Project (http://pciids.sf.net/). It is maintained by Martin Mares + * and other volunteers. The pci.ids file is licensed under + * the BSD 3-clause or GPL version 2 or later licenses. + */ + +#include \"xf86PciInfo.h\" +#ifndef NULL +#define NULL (void *)0 +#endif + +"; + +# The following #ifdefs are used: +# - INIT_SUBSYS_INFO -- initialise subsystem data +# - INIT_VENDOR_SUBSYS_INFO -- initialise a vendor<->subsystem table. +# - VENDOR_INCLUDE_NONVIDEO -- include data for non-video vendors. + +# Define static variables with all of the strings. + +foreach $vendor (sort keys %vendors) { + if ($infofile && !$video{$vendor}) { + print "#ifdef VENDOR_INCLUDE_NONVIDEO\n"; + } + print "static const char pci_vendor_${vendor}[] = \"$vendors{$vendor}\";\n"; + foreach $device (sort keys %{$devices{$vendor}}) { + print "static const char pci_device_${vendor}_${device}[] = " . + "\"$devices{$vendor}{$device}\";\n"; + foreach $subsys (sort keys %{$devsubsystems{$vendor}{$device}}) { + $s = $subsys; + ($v) = split /-/, $s; + if ($infofile && !$video{$vendor} && $video{$v}) { + print "#endif\n"; + } + $s =~ s/-/_/; + print "#ifdef INIT_SUBSYS_INFO\n"; + print "static const char pci_subsys_${vendor}_${device}_${s}[] = " . + "\"$devsubsystems{$vendor}{$device}{$subsys}\";\n"; + print "#endif\n"; + if ($infofile && !$video{$vendor} && $video{$v}) { + print "#ifdef VENDOR_INCLUDE_NONVIDEO\n"; + } + } + } + if ($infofile && !$video{$vendor}) { + print "#endif\n"; + } +} + + +# Pre-initialise the table structures (from the inner to the outer). + +# First, the subsys structures. + +print "#ifdef INIT_SUBSYS_INFO\n"; +foreach $vendor (sort keys %vendors) { + if ($infofile && !$video{$vendor}) { + $pre = "#ifdef VENDOR_INCLUDE_NONVIDEO\n"; + } else { + undef($pre); + undef($post); + } + foreach $device (sort keys %{$devices{$vendor}}) { + foreach $subsys (sort keys %{$devsubsystems{$vendor}{$device}}) { + $s = $subsys; + $s =~ tr/-/_/; + ($vid, $sid) = split /_/, $s; + if ($pre) { + print $pre; + undef($pre); + $post = "#endif\n"; + } + if ($infofile && !$video{$vendor} && $video{$vid}) { + print "#endif\n"; + } + print "static const pciSubsystemInfo " . + "pci_ss_info_${vendor}_${device}_$s =\n"; + print "\t{0x$vid, 0x$sid, pci_subsys_${vendor}_${device}_$s, 0};\n"; + print "#undef pci_ss_info_$s\n"; + print "#define pci_ss_info_$s pci_ss_info_${vendor}_${device}_$s\n"; + if ($infofile && !$video{$vendor} && $video{$vid}) { + print "#ifdef VENDOR_INCLUDE_NONVIDEO\n"; + } + } + } + if ($post) { + print $post; + undef($post); + } +} + +# Next, the list of per vendor+device subsystem arrays + +foreach $vendor (sort keys %vendors) { + if ($infofile && !$video{$vendor}) { + $pre = "#ifdef VENDOR_INCLUDE_NONVIDEO\n"; + } else { + undef($pre); + undef($post); + } + foreach $device (sort keys %{$devices{$vendor}}) { + if (scalar(keys %{$devsubsystems{$vendor}{$device}}) > 0) { + if ($pre) { + print $pre; + undef($pre); + $post = "#endif\n"; + } + print "static const pciSubsystemInfo *pci_ss_list_${vendor}_${device}[] = {\n"; + foreach $sub (sort keys %{$devsubsystems{$vendor}{$device}}) { + $sub =~ s/-/_/; + print "\t&pci_ss_info_${vendor}_${device}_${sub},\n"; + } + print "\tNULL\n};\n"; + } else { + print "#define pci_ss_list_${vendor}_${device} NULL\n"; + } + } + if ($post) { + print $post; + undef($post); + } +} + +# Next, the list of per vendor subsystem arrays + +print "#ifdef INIT_VENDOR_SUBSYS_INFO\n"; +foreach $vendor (sort keys %vendors) { + if (scalar(keys %{$subsystems{$vendor}}) > 0) { + if ($infofile && !$video{$vendor}) { + print "#ifdef VENDOR_INCLUDE_NONVIDEO\n"; + } + print "static const pciSubsystemInfo *pci_ss_list_${vendor}[] = {\n"; + foreach $sub (sort keys %{$subsystems{$vendor}}) { + print "\t&pci_ss_info_${vendor}_${sub},\n"; + } + print "\tNULL\n};\n"; + if ($infofile && !$video{$vendor}) { + print "#endif\n"; + } + } else { + print "#define pci_ss_list_${vendor} NULL\n"; + } +} +print "#endif /* INIT_VENDOR_SUBSYS_INFO */\n"; +print "#endif /* INIT_SUBSYS_INFO */\n"; + +# Next the device structures + +foreach $vendor (sort keys %vendors) { + if ($infofile && !$video{$vendor}) { + $pre = "#ifdef VENDOR_INCLUDE_NONVIDEO\n"; + } else { + undef($pre); + undef($post); + } + foreach $device (sort keys %{$devices{$vendor}}) { + if ($pre) { + print $pre; + undef($pre); + $post = "#endif\n"; + } + if ($classes{$vendor}{$device}) { + $class = "0x$classes{$vendor}{$device}"; + } else { + $class = "0"; + } + print "static const pciDeviceInfo " . + "pci_dev_info_${vendor}_${device} = {\n"; + print "\t0x$device, pci_device_${vendor}_${device},\n"; + print "#ifdef INIT_SUBSYS_INFO\n"; + print "\tpci_ss_list_${vendor}_${device},\n"; + print "#else\n"; + print "\tNULL,\n"; + print "#endif\n"; + print "\t$class\n};\n"; + } + if ($post) { + print $post; + undef($post); + } +} + +# Next, the list of per vendor device arrays + +foreach $vendor (sort keys %vendors) { + if (scalar(keys %{$devices{$vendor}}) > 0) { + if ($infofile && !$video{$vendor}) { + print "#ifdef VENDOR_INCLUDE_NONVIDEO\n"; + } + print "static const pciDeviceInfo *pci_dev_list_${vendor}[] = {\n"; + foreach $device (sort keys %{$devices{$vendor}}) { + print "\t&pci_dev_info_${vendor}_${device},\n"; + } + print "\tNULL\n};\n"; + if ($infofile && !$video{$vendor}) { + print "#endif\n"; + } + } else { + print "#define pci_dev_list_${vendor} NULL\n"; + } +} + +# Next, the main vendor list + +print " +static const pciVendorInfo pciVendorInfoList[] = { +"; + +foreach $vendor (sort keys %vendors) { + if ($infofile && !$video{$vendor}) { + print "#ifdef VENDOR_INCLUDE_NONVIDEO\n"; + } + print "\t{0x$vendor, pci_vendor_$vendor, pci_dev_list_$vendor},\n"; + if ($infofile && !$video{$vendor}) { + print "#endif\n"; + } +} +print "\t{0x0000, NULL, NULL}\n};\n"; + +# Finally, the main vendor/subsystem list + +print " +#if defined(INIT_VENDOR_SUBSYS_INFO) && defined(INIT_SUBSYS_INFO) +static const pciVendorSubsysInfo pciVendorSubsysInfoList[] = { +"; + +foreach $vendor (sort keys %vendors) { + if ($infofile && !$video{$vendor}) { + print "#ifdef VENDOR_INCLUDE_NONVIDEO\n"; + } + print "\t{0x$vendor, pci_vendor_$vendor, pci_ss_list_$vendor},\n"; + if ($infofile && !$video{$vendor}) { + print "#endif\n"; + } +} +print "\t{0x0000, NULL, NULL}\n};\n"; +print "#endif\n"; diff --git a/hw/xfree86/scanpci/xf86PciStdIds.h b/hw/xfree86/scanpci/xf86PciStdIds.h new file mode 100644 index 000000000..d86d686c8 --- /dev/null +++ b/hw/xfree86/scanpci/xf86PciStdIds.h @@ -0,0 +1,139619 @@ + +/* + * THIS FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + * + * It is generated by pciid2c.pl using data from the following files: + * + * ../etc/pci.ids + * ../etc/extrapci.ids + * ../common/xf86PciInfo.h + */ + +/* + * Copyright © 2002 by the XFree86 Project, Inc. + * + * The pci.ids file and the data it contains are from the Linux PCI ID's + * Project (http://pciids.sf.net/). It is maintained by Martin Mares + * and other volunteers. The pci.ids file is licensed under + * the BSD 3-clause or GPL version 2 or later licenses. + */ + +#include "xf86PciInfo.h" +#ifndef NULL +#define NULL (void *)0 +#endif + +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0000[] = "Gammagraphx, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_001a[] = "Ascend Communications, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0033[] = "Paradyne corp."; +#endif +static const char pci_vendor_003d[] = "Lockheed Martin-Marietta Corp"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0059[] = "Tiger Jet Network Inc. (Wrong ID)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0070[] = "Hauppauge computer works Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0071[] = "Nebula Electronics Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0095[] = "Silicon Image, Inc. (Wrong ID)"; +static const char pci_device_0095_0680[] = "Ultra ATA/133 IDE RAID CONTROLLER CARD"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_00a7[] = "Teles AG (Wrong ID)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_00f5[] = "BFG Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0100[] = "Ncipher Corp Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0123[] = "General Dynamics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_018a[] = "LevelOne"; +static const char pci_device_018a_0106[] = "FPC-0106TX misprogrammed [RTL81xx]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_021b[] = "Compaq Computer Corporation"; +static const char pci_device_021b_8139[] = "HNE-300 (RealTek RTL8139c) [iPaq Networking]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0270[] = "Hauppauge computer works Inc. (Wrong ID)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0291[] = "Davicom Semiconductor, Inc."; +static const char pci_device_0291_8212[] = "DM9102A(DM9102AE, SM9102AF) Ethernet 100/10 MBit(Rev 40)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_02ac[] = "SpeedStream"; +static const char pci_device_02ac_1012[] = "1012 PCMCIA 10/100 Ethernet Card [RTL81xx]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0315[] = "SK-Electronics Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0357[] = "TTTech AG"; +static const char pci_device_0357_000a[] = "TTP-Monitoring Card V2.0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0432[] = "SCM Microsystems, Inc."; +static const char pci_device_0432_0001[] = "Pluto2 DVB-T Receiver for PCMCIA [EasyWatch MobilSet]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_045e[] = "Microsoft"; +static const char pci_device_045e_006e[] = "MN-510 802.11b wireless USB paddle"; +static const char pci_device_045e_00c2[] = "MN-710 wireless USB paddle"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0482[] = "Kyocera"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_04cf[] = "Myson Century, Inc"; +static const char pci_device_04cf_8818[] = "CS8818 USB2.0-to-ATAPI Bridge Controller with Embedded PHY"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_050d[] = "Belkin"; +static const char pci_device_050d_001a[] = "FSD7000 802.11g PCI Wireless card"; +static const char pci_device_050d_0109[] = "F5U409-CU USB/Serial Portable Adapter"; +static const char pci_device_050d_7050[] = "F5D7050 802.11g Wireless USB Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_05a9[] = "OmniVision"; +static const char pci_device_05a9_8519[] = "OV519 series"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_05e3[] = "CyberDoor"; +static const char pci_device_05e3_0701[] = "CBD516"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_066f[] = "Sigmatel Inc."; +static const char pci_device_066f_3410[] = "SMTP3410"; +static const char pci_device_066f_3500[] = "SMTP3500"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0675[] = "Dynalink"; +static const char pci_device_0675_1700[] = "IS64PH ISDN Adapter"; +static const char pci_device_0675_1702[] = "IS64PH ISDN Adapter"; +static const char pci_device_0675_1703[] = "ISDN Adapter (PCI Bus, DV, W)"; +static const char pci_device_0675_1704[] = "ISDN Adapter (PCI Bus, D, C)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_067b[] = "Prolific Technology, Inc."; +static const char pci_device_067b_2303[] = "PL-2303 USB-to-Serial Converter"; +static const char pci_device_067b_3507[] = "PL-3507 Hi-Speed USB & IEEE 1394 Combo to IDE Bridge Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0721[] = "Sapphire, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_07e2[] = "ELMEG Communication Systems GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0925[] = "VIA Technologies, Inc. (Wrong ID)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_093a[] = "PixArt Imaging Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_09c1[] = "Arris"; +static const char pci_device_09c1_0704[] = "CM 200E Cable Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0a89[] = "BREA Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0b0b[] = "Rhino Equiment Corp."; +static const char pci_device_0b0b_0105[] = "Rhino R1T1"; +static const char pci_device_0b0b_0205[] = "Rhino R4FXO"; +static const char pci_device_0b0b_0305[] = "Rhino R4T1"; +static const char pci_device_0b0b_0405[] = "Rhino R8FXX"; +static const char pci_device_0b0b_0505[] = "Rhino R24FXX"; +static const char pci_device_0b0b_0506[] = "Rhino R2T1"; +static const char pci_device_0b0b_0605[] = "Rhino R2T1"; +static const char pci_device_0b0b_0705[] = "Rhino R24FXS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0b49[] = "ASCII Corporation"; +static const char pci_device_0b49_064f[] = "Trance Vibrator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0ccd[] = "TerraTec Electronic GmbH"; +static const char pci_device_0ccd_0038[] = "Cinergy T^2 DVB-T Receiver"; +#endif +static const char pci_vendor_0e11[] = "Compaq Computer Corporation"; +static const char pci_device_0e11_0001[] = "PCI to EISA Bridge"; +static const char pci_device_0e11_0002[] = "PCI to ISA Bridge"; +static const char pci_device_0e11_0046[] = "Smart Array 64xx"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_0046_0e11_409a[] = "Smart Array 641"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_0046_0e11_409b[] = "Smart Array 642"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_0046_0e11_409c[] = "Smart Array 6400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_0046_0e11_409d[] = "Smart Array 6400 EM"; +#endif +static const char pci_device_0e11_0049[] = "NC7132 Gigabit Upgrade Module"; +static const char pci_device_0e11_004a[] = "NC6136 Gigabit Server Adapter"; +static const char pci_device_0e11_005a[] = "Remote Insight II board - Lights-Out"; +static const char pci_device_0e11_007c[] = "NC7770 1000BaseTX"; +static const char pci_device_0e11_007d[] = "NC6770 1000BaseTX"; +static const char pci_device_0e11_0085[] = "NC7780 1000BaseTX"; +static const char pci_device_0e11_00b1[] = "Remote Insight II board - PCI device"; +static const char pci_device_0e11_00bb[] = "NC7760"; +static const char pci_device_0e11_00ca[] = "NC7771"; +static const char pci_device_0e11_00cb[] = "NC7781"; +static const char pci_device_0e11_00cf[] = "NC7772"; +static const char pci_device_0e11_00d0[] = "NC7782"; +static const char pci_device_0e11_00d1[] = "NC7783"; +static const char pci_device_0e11_00e3[] = "NC7761"; +static const char pci_device_0e11_0508[] = "Netelligent 4/16 Token Ring"; +static const char pci_device_0e11_1000[] = "Triflex/Pentium Bridge, Model 1000"; +static const char pci_device_0e11_2000[] = "Triflex/Pentium Bridge, Model 2000"; +static const char pci_device_0e11_3032[] = "QVision 1280/p"; +static const char pci_device_0e11_3033[] = "QVision 1280/p"; +static const char pci_device_0e11_3034[] = "QVision 1280/p"; +static const char pci_device_0e11_4000[] = "4000 [Triflex]"; +static const char pci_device_0e11_4030[] = "SMART-2/P"; +static const char pci_device_0e11_4031[] = "SMART-2SL"; +static const char pci_device_0e11_4032[] = "Smart Array 3200"; +static const char pci_device_0e11_4033[] = "Smart Array 3100ES"; +static const char pci_device_0e11_4034[] = "Smart Array 221"; +static const char pci_device_0e11_4040[] = "Integrated Array"; +static const char pci_device_0e11_4048[] = "Compaq Raid LC2"; +static const char pci_device_0e11_4050[] = "Smart Array 4200"; +static const char pci_device_0e11_4051[] = "Smart Array 4250ES"; +static const char pci_device_0e11_4058[] = "Smart Array 431"; +static const char pci_device_0e11_4070[] = "Smart Array 5300"; +static const char pci_device_0e11_4080[] = "Smart Array 5i"; +static const char pci_device_0e11_4082[] = "Smart Array 532"; +static const char pci_device_0e11_4083[] = "Smart Array 5312"; +static const char pci_device_0e11_4091[] = "Smart Array 6i"; +static const char pci_device_0e11_409a[] = "Smart Array 641"; +static const char pci_device_0e11_409b[] = "Smart Array 642"; +static const char pci_device_0e11_409c[] = "Smart Array 6400"; +static const char pci_device_0e11_409d[] = "Smart Array 6400 EM"; +static const char pci_device_0e11_6010[] = "HotPlug PCI Bridge 6010"; +static const char pci_device_0e11_7020[] = "USB Controller"; +static const char pci_device_0e11_a0ec[] = "Fibre Channel Host Controller"; +static const char pci_device_0e11_a0f0[] = "Advanced System Management Controller"; +static const char pci_device_0e11_a0f3[] = "Triflex PCI to ISA Bridge"; +static const char pci_device_0e11_a0f7[] = "PCI Hotplug Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_a0f7_8086_002a[] = "PCI Hotplug Controller A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_a0f7_8086_002b[] = "PCI Hotplug Controller B"; +#endif +static const char pci_device_0e11_a0f8[] = "ZFMicro Chipset USB"; +static const char pci_device_0e11_a0fc[] = "FibreChannel HBA Tachyon"; +static const char pci_device_0e11_ae10[] = "Smart-2/P RAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_ae10_0e11_4030[] = "Smart-2/P Array Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_ae10_0e11_4031[] = "Smart-2SL Array Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_ae10_0e11_4032[] = "Smart Array Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_ae10_0e11_4033[] = "Smart 3100ES Array Controller"; +#endif +static const char pci_device_0e11_ae29[] = "MIS-L"; +static const char pci_device_0e11_ae2a[] = "MPC"; +static const char pci_device_0e11_ae2b[] = "MIS-E"; +static const char pci_device_0e11_ae31[] = "System Management Controller"; +static const char pci_device_0e11_ae32[] = "Netelligent 10/100 TX PCI UTP"; +static const char pci_device_0e11_ae33[] = "Triflex Dual EIDE Controller"; +static const char pci_device_0e11_ae34[] = "Netelligent 10 T PCI UTP"; +static const char pci_device_0e11_ae35[] = "Integrated NetFlex-3/P"; +static const char pci_device_0e11_ae40[] = "Netelligent Dual 10/100 TX PCI UTP"; +static const char pci_device_0e11_ae43[] = "Netelligent Integrated 10/100 TX UTP"; +static const char pci_device_0e11_ae69[] = "CETUS-L"; +static const char pci_device_0e11_ae6c[] = "Northstar"; +static const char pci_device_0e11_ae6d[] = "NorthStar CPU to PCI Bridge"; +static const char pci_device_0e11_b011[] = "Netelligent 10/100 TX Embedded UTP"; +static const char pci_device_0e11_b012[] = "Netelligent 10 T/2 PCI UTP/Coax"; +static const char pci_device_0e11_b01e[] = "NC3120 Fast Ethernet NIC"; +static const char pci_device_0e11_b01f[] = "NC3122 Fast Ethernet NIC"; +static const char pci_device_0e11_b02f[] = "NC1120 Ethernet NIC"; +static const char pci_device_0e11_b030[] = "Netelligent 10/100 TX UTP"; +static const char pci_device_0e11_b04a[] = "10/100 TX PCI Intel WOL UTP Controller"; +static const char pci_device_0e11_b060[] = "Smart Array 5300 Controller"; +static const char pci_device_0e11_b0c6[] = "NC3161 Fast Ethernet NIC"; +static const char pci_device_0e11_b0c7[] = "NC3160 Fast Ethernet NIC"; +static const char pci_device_0e11_b0d7[] = "NC3121 Fast Ethernet NIC"; +static const char pci_device_0e11_b0dd[] = "NC3131 Fast Ethernet NIC"; +static const char pci_device_0e11_b0de[] = "NC3132 Fast Ethernet Module"; +static const char pci_device_0e11_b0df[] = "NC6132 Gigabit Module"; +static const char pci_device_0e11_b0e0[] = "NC6133 Gigabit Module"; +static const char pci_device_0e11_b0e1[] = "NC3133 Fast Ethernet Module"; +static const char pci_device_0e11_b123[] = "NC6134 Gigabit NIC"; +static const char pci_device_0e11_b134[] = "NC3163 Fast Ethernet NIC"; +static const char pci_device_0e11_b13c[] = "NC3162 Fast Ethernet NIC"; +static const char pci_device_0e11_b144[] = "NC3123 Fast Ethernet NIC"; +static const char pci_device_0e11_b163[] = "NC3134 Fast Ethernet NIC"; +static const char pci_device_0e11_b164[] = "NC3165 Fast Ethernet Upgrade Module"; +static const char pci_device_0e11_b178[] = "Smart Array 5i/532"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_b178_0e11_4080[] = "Smart Array 5i"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_b178_0e11_4082[] = "Smart Array 532"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_0e11_b178_0e11_4083[] = "Smart Array 5312"; +#endif +static const char pci_device_0e11_b1a4[] = "NC7131 Gigabit Server Adapter"; +static const char pci_device_0e11_b200[] = "Memory Hot-Plug Controller"; +static const char pci_device_0e11_b203[] = "Integrated Lights Out Controller"; +static const char pci_device_0e11_b204[] = "Integrated Lights Out Processor"; +static const char pci_device_0e11_f130[] = "NetFlex-3/P ThunderLAN 1.0"; +static const char pci_device_0e11_f150[] = "NetFlex-3/P ThunderLAN 2.3"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0e21[] = "Cowon Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0e55[] = "HaSoTec GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_0eac[] = "SHF Communication Technologies AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1000[] = "LSI Logic / Symbios Logic"; +static const char pci_device_1000_0001[] = "53c810"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0001_1000_1000[] = "LSI53C810AE PCI to SCSI I/O Processor"; +#endif +static const char pci_device_1000_0002[] = "53c820"; +static const char pci_device_1000_0003[] = "53c825"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0003_1000_1000[] = "LSI53C825AE PCI to SCSI I/O Processor (Ultra Wide)"; +#endif +static const char pci_device_1000_0004[] = "53c815"; +static const char pci_device_1000_0005[] = "53c810AP"; +static const char pci_device_1000_0006[] = "53c860"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0006_1000_1000[] = "LSI53C860E PCI to Ultra SCSI I/O Processor"; +#endif +static const char pci_device_1000_000a[] = "53c1510"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000a_0e11_b143[] = "Integrated Dual Channel Wide Ultra2 SCSI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000a_1000_1000[] = "LSI53C1510 PCI to Dual Channel Wide Ultra2 SCSI Controller (Nonintelligent mode)"; +#endif +static const char pci_device_1000_000b[] = "53C896/897"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000b_0e11_6004[] = "EOB003 Series SCSI host adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000b_1000_1000[] = "LSI53C896/7 PCI to Dual Channel Ultra2 SCSI Multifunction Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000b_1000_1010[] = "LSI22910 PCI to Dual Channel Ultra2 SCSI host adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000b_1000_1020[] = "LSI21002 PCI to Dual Channel Ultra2 SCSI host adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000b_13e9_1000[] = "6221L-4U (Dual U2W SCSI, dual 10/100TX, graphics)"; +#endif +static const char pci_device_1000_000c[] = "53c895"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000c_1000_1010[] = "LSI8951U PCI to Ultra2 SCSI host adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000c_1000_1020[] = "LSI8952U PCI to Ultra2 SCSI host adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000c_1de1_3906[] = "DC-390U2B SCSI adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000c_1de1_3907[] = "DC-390U2W"; +#endif +static const char pci_device_1000_000d[] = "53c885"; +static const char pci_device_1000_000f[] = "53c875"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_0e11_7004[] = "Embedded Ultra Wide SCSI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_1000_1000[] = "LSI53C876/E PCI to Dual Channel SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_1000_1010[] = "LSI22801 PCI to Dual Channel Ultra SCSI host adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_1000_1020[] = "LSI22802 PCI to Dual Channel Ultra SCSI host adapter"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_1092_8760[] = "FirePort 40 Dual SCSI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_1775_10d0[] = "V5D Single Board Computer Wide Ultra SCSI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_1775_10d1[] = "V5D Single Board Computer Ultra SCSI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_1de1_3904[] = "DC390F/U Ultra Wide SCSI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_000f_4c53_1050[] = "CT7 mainboard"; +#endif +static const char pci_device_1000_0010[] = "53C1510"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0010_0e11_4040[] = "Integrated Array Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0010_0e11_4048[] = "RAID LC2 Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0010_1000_1000[] = "53C1510 PCI to Dual Channel Wide Ultra2 SCSI Controller (Intelligent mode)"; +#endif +static const char pci_device_1000_0012[] = "53c895a"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0012_1000_1000[] = "LSI53C895A PCI to Ultra2 SCSI Controller"; +#endif +static const char pci_device_1000_0013[] = "53c875a"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0013_1000_1000[] = "LSI53C875A PCI to Ultra SCSI Controller"; +#endif +static const char pci_device_1000_0020[] = "53c1010 Ultra3 SCSI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0020_1000_1000[] = "LSI53C1010-33 PCI to Dual Channel Ultra160 SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0020_107b_1040[] = "Server Onboard 53C1010-33"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0020_1de1_1020[] = "DC-390U3W"; +#endif +static const char pci_device_1000_0021[] = "53c1010 66MHz Ultra3 SCSI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_1000_1000[] = "LSI53C1000/1000R/1010R/1010-66 PCI to Ultra160 SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_1000_1010[] = "Asus TR-DLS onboard 53C1010-66"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_103c_1330[] = "Ultra160 SCSI [A7059A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_103c_1340[] = "Ultra160 SCSI [A7060A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_124b_1070[] = "PMC-USCSI3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_4c53_1300[] = "P017 mezzanine (32-bit PMC)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0021_4c53_1310[] = "P017 mezzanine (64-bit PMC)"; +#endif +static const char pci_device_1000_0030[] = "53c1030 PCI-X Fusion-MPT Dual Ultra320 SCSI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_0e11_00da[] = "ProLiant ML 350"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1028_0123[] = "PowerEdge 2600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1028_014a[] = "PowerEdge 1750"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1028_016c[] = "PowerEdge 1850 MPT Fusion SCSI/RAID (Perc 4)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1028_0183[] = "PowerEdge 1800"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1028_1010[] = "LSI U320 SCSI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_103c_12c5[] = "Ultra320 SCSI [A7173A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_124b_1170[] = "PMC-USCSI320"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0030_1734_1052[] = "Primergy RX300 S2"; +#endif +static const char pci_device_1000_0031[] = "53c1030ZC PCI-X Fusion-MPT Dual Ultra320 SCSI"; +static const char pci_device_1000_0032[] = "53c1035 PCI-X Fusion-MPT Dual Ultra320 SCSI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0032_1000_1000[] = "LSI53C1020/1030 PCI-X to Ultra320 SCSI Controller"; +#endif +static const char pci_device_1000_0033[] = "1030ZC_53c1035 PCI-X Fusion-MPT Dual Ultra320 SCSI"; +static const char pci_device_1000_0040[] = "53c1035 PCI-X Fusion-MPT Dual Ultra320 SCSI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0040_1000_0033[] = "MegaRAID SCSI 320-2XR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0040_1000_0066[] = "MegaRAID SCSI 320-2XRWS"; +#endif +static const char pci_device_1000_0041[] = "53C1035ZC PCI-X Fusion-MPT Dual Ultra320 SCSI"; +static const char pci_device_1000_0050[] = "SAS1064 PCI-X Fusion-MPT SAS"; +static const char pci_device_1000_0054[] = "SAS1068 PCI-X Fusion-MPT SAS"; +static const char pci_device_1000_0056[] = "SAS1064E PCI-Express Fusion-MPT SAS"; +static const char pci_device_1000_0058[] = "SAS1068E PCI-Express Fusion-MPT SAS"; +static const char pci_device_1000_005a[] = "SAS1066E PCI-Express Fusion-MPT SAS"; +static const char pci_device_1000_005c[] = "SAS1064A PCI-X Fusion-MPT SAS"; +static const char pci_device_1000_005e[] = "SAS1066 PCI-X Fusion-MPT SAS"; +static const char pci_device_1000_0060[] = "MegaRAID SAS 1078"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0060_1028_1f0a[] = "PERC 6/E Adapter RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0060_1028_1f0b[] = "PERC 6/i Adapter RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0060_1028_1f0c[] = "PERC 6/i Integrated RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0060_1028_1f0d[] = "PERC 6/i Enhanced RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1000_0062[] = "SAS1078 PCI-Express Fusion-MPT SAS"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0062_1000_0062[] = "SAS1078 PCI-Express Fusion-MPT SAS"; +#endif +static const char pci_device_1000_008f[] = "53c875J"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_008f_1092_8000[] = "FirePort 40 SCSI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_008f_1092_8760[] = "FirePort 40 Dual SCSI Host Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1000_0407[] = "MegaRAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_1000_0530[] = "MegaRAID 530 SCSI 320-0X RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_1000_0531[] = "MegaRAID 531 SCSI 320-4X RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_1000_0532[] = "MegaRAID 532 SCSI 320-2X RAID Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_1028_0531[] = "PowerEdge Expandable RAID Controller 4/QC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_1028_0533[] = "PowerEdge Expandable RAID Controller 4/QC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_8086_0530[] = "MegaRAID Intel RAID Controller SRCZCRX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0407_8086_0532[] = "MegaRAID Intel RAID Controller SRCU42X"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1000_0408[] = "MegaRAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1000_0001[] = "MegaRAID SCSI 320-1E RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1000_0002[] = "MegaRAID SCSI 320-2E RAID Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1025_004d[] = "MegaRAID ACER ROMB-2E RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1028_0001[] = "PowerEdge RAID Controller PERC4e/SC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1028_0002[] = "PowerEdge RAID Controller PERC4e/DC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_1734_1065[] = "FSC MegaRAID PCI Express ROMB"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0408_8086_0002[] = "MegaRAID Intel RAID Controller SRCU42E"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1000_0409[] = "MegaRAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0409_1000_3004[] = "MegaRAID SATA 300-4X RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0409_1000_3008[] = "MegaRAID SATA 300-8X RAID Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0409_8086_3008[] = "MegaRAID RAID Controller SRCS28X"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0409_8086_3431[] = "MegaRAID RAID Controller Alief SROMBU42E"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0409_8086_3499[] = "MegaRAID RAID Controller Harwich SROMBU42E"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1000_0411[] = "MegaRAID SAS"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0411_1000_1001[] = "MegaRAID SAS 8408E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0411_1000_1002[] = "MegaRAID SAS 8480E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0411_1000_1003[] = "MegaRAID SAS 8344ELP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0411_1000_1004[] = "MegaRAID SAS 8308ELP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0411_1000_100c[] = "MegaRAID SATA 300-12E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0411_1000_100d[] = "MegaRAID SATA 300-16E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0411_1000_2004[] = "MegaRAID SATA 300-8ELP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0411_1000_2005[] = "MegaRAID SATA 300-4ELP"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0411_1033_8287[] = "MegaRAID SAS PCI Express ROMB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0411_1054_3016[] = "MegaRAID SAS RoMB Server"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0411_1734_1081[] = "MegaRAID SAS PCI Express ROMB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0411_1734_10a3[] = "MegaRAID SAS PCI Express ROMB"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0411_8086_1001[] = "SRCSAS18E RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0411_8086_1003[] = "SRCSAS144E RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0411_8086_3500[] = "SROMBSAS18E RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0411_8086_3501[] = "SROMBSAS18E RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0411_8086_3504[] = "SROMBSAS18E RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1000_0413[] = "MegaRAID SAS Verde ZCR"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0413_1000_1005[] = "MegaRAID SAS 8300XLP"; +#endif +static const char pci_device_1000_0621[] = "FC909 Fibre Channel Adapter"; +static const char pci_device_1000_0622[] = "FC929 Fibre Channel Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0622_1000_1020[] = "44929 O Dual Fibre Channel card"; +#endif +static const char pci_device_1000_0623[] = "FC929 LAN"; +static const char pci_device_1000_0624[] = "FC919 Fibre Channel Adapter"; +static const char pci_device_1000_0625[] = "FC919 LAN"; +static const char pci_device_1000_0626[] = "FC929X Fibre Channel Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0626_1000_1010[] = "7202-XP-LC Dual Fibre Channel card"; +#endif +static const char pci_device_1000_0627[] = "FC929X LAN"; +static const char pci_device_1000_0628[] = "FC919X Fibre Channel Adapter"; +static const char pci_device_1000_0629[] = "FC919X LAN"; +static const char pci_device_1000_0640[] = "FC949X Fibre Channel Adapter"; +static const char pci_device_1000_0642[] = "FC939X Fibre Channel Adapter"; +static const char pci_device_1000_0646[] = "FC949ES Fibre Channel Adapter"; +static const char pci_device_1000_0701[] = "83C885 NT50 DigitalScape Fast Ethernet"; +static const char pci_device_1000_0702[] = "Yellowfin G-NIC gigabit ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_0702_1318_0000[] = "PEI100X"; +#endif +static const char pci_device_1000_0804[] = "SA2010"; +static const char pci_device_1000_0805[] = "SA2010ZC"; +static const char pci_device_1000_0806[] = "SA2020"; +static const char pci_device_1000_0807[] = "SA2020ZC"; +static const char pci_device_1000_0901[] = "61C102"; +static const char pci_device_1000_1000[] = "63C815"; +static const char pci_device_1000_1960[] = "MegaRAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_0518[] = "MegaRAID 518 SCSI 320-2 Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_0520[] = "MegaRAID 520 SCSI 320-1 Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_0522[] = "MegaRAID 522 i4 133 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_0523[] = "MegaRAID SATA 150-6 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_4523[] = "MegaRAID SATA 150-4 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1000_a520[] = "MegaRAID ZCR SCSI 320-0 Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1028_0518[] = "MegaRAID 518 DELL PERC 4/DC RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1028_0520[] = "MegaRAID 520 DELL PERC 4/SC RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1028_0531[] = "PowerEdge Expandable RAID Controller 4/QC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_1028_0533[] = "PowerEdge Expandable RAID Controller 4/QC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_8086_0520[] = "MegaRAIDRAID Controller SRCU41L"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1000_1960_8086_0523[] = "MegaRAID RAID Controller SRCS16"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1001[] = "Kolter Electronic"; +static const char pci_device_1001_0010[] = "PCI 1616 Measurement card with 32 digital I/O lines"; +static const char pci_device_1001_0011[] = "OPTO-PCI Opto-Isolated digital I/O board"; +static const char pci_device_1001_0012[] = "PCI-AD/DA Analogue I/O board"; +static const char pci_device_1001_0013[] = "PCI-OPTO-RELAIS Digital I/O board with relay outputs"; +static const char pci_device_1001_0014[] = "PCI-Counter/Timer Counter Timer board"; +static const char pci_device_1001_0015[] = "PCI-DAC416 Analogue output board"; +static const char pci_device_1001_0016[] = "PCI-MFB Analogue I/O board"; +static const char pci_device_1001_0017[] = "PROTO-3 PCI Prototyping board"; +static const char pci_device_1001_9100[] = "INI-9100/9100W SCSI Host"; +#endif +static const char pci_vendor_1002[] = "ATI Technologies Inc"; +static const char pci_device_1002_3150[] = "M24 1P [Radeon Mobility X600]"; +static const char pci_device_1002_3152[] = "M22 [Radeon Mobility X300]"; +static const char pci_device_1002_3154[] = "M24 1T [FireGL M24 GL]"; +static const char pci_device_1002_3e50[] = "RV380 0x3e50 [Radeon X600]"; +static const char pci_device_1002_3e54[] = "RV380 0x3e54 [FireGL V3200]"; +static const char pci_device_1002_3e70[] = "RV380 [Radeon X600] Secondary"; +static const char pci_device_1002_4136[] = "Radeon IGP 320 M"; +static const char pci_device_1002_4137[] = "Radeon IGP330/340/350"; +static const char pci_device_1002_4144[] = "R300 AD [Radeon 9500 Pro]"; +static const char pci_device_1002_4145[] = "R300 AE [Radeon 9700 Pro]"; +static const char pci_device_1002_4146[] = "R300 AF [Radeon 9700 Pro]"; +static const char pci_device_1002_4147[] = "R300 AG [FireGL Z1/X1]"; +static const char pci_device_1002_4148[] = "R350 AH [Radeon 9800]"; +static const char pci_device_1002_4149[] = "R350 AI [Radeon 9800]"; +static const char pci_device_1002_414a[] = "R350 AJ [Radeon 9800]"; +static const char pci_device_1002_414b[] = "R350 AK [Fire GL X2]"; +static const char pci_device_1002_4150[] = "RV350 AP [Radeon 9600]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_1002_0002[] = "R9600 Pro primary (Asus OEM for HP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_1002_0003[] = "R9600 Pro secondary (Asus OEM for HP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_1002_4722[] = "All-in-Wonder 2006 AGP Edition"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_1458_4024[] = "Giga-Byte GV-R96128D Primary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_148c_2064[] = "PowerColor R96A-C3N"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_148c_2066[] = "PowerColor R96A-C3N"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_174b_7c19[] = "Sapphire Atlantis Radeon 9600 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_174b_7c29[] = "GC-R9600PRO Primary [Sapphire]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_17ee_2002[] = "Radeon 9600 256Mb Primary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4150_18bc_0101[] = "GC-R9600PRO Primary"; +#endif +static const char pci_device_1002_4151[] = "RV350 AQ [Radeon 9600]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4151_1043_c004[] = "A9600SE"; +#endif +static const char pci_device_1002_4152[] = "RV350 AR [Radeon 9600]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_1002_0002[] = "Radeon 9600XT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_1002_4772[] = "All-in-Wonder 9600 XT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_1043_c002[] = "Radeon 9600 XT TVD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_1043_c01a[] = "A9600XT/TD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_174b_7c29[] = "Sapphire Radeon 9600XT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4152_1787_4002[] = "Radeon 9600 XT"; +#endif +static const char pci_device_1002_4153[] = "RV350 AS [Radeon 9550]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4153_1043_010c[] = "A9550GE/TD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4153_1462_932c[] = "865PE Neo2-V (MS-6788) mainboard"; +#endif +static const char pci_device_1002_4154[] = "RV350 AT [Fire GL T2]"; +static const char pci_device_1002_4155[] = "RV350 AU [Fire GL T2]"; +static const char pci_device_1002_4156[] = "RV350 AV [Fire GL T2]"; +static const char pci_device_1002_4157[] = "RV350 AW [Fire GL T2]"; +static const char pci_device_1002_4158[] = "68800AX [Mach32]"; +static const char pci_device_1002_4164[] = "R300 AD [Radeon 9500 Pro] (Secondary)"; +static const char pci_device_1002_4165[] = "R300 AE [Radeon 9700 Pro] (Secondary)"; +static const char pci_device_1002_4166[] = "R300 AF [Radeon 9700 Pro] (Secondary)"; +static const char pci_device_1002_4168[] = "Radeon R350 [Radeon 9800] (Secondary)"; +static const char pci_device_1002_4170[] = "RV350 AP [Radeon 9600] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_1002_0003[] = "R9600 Pro secondary (Asus OEM for HP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_1002_4723[] = "All-in-Wonder 2006 AGP Edition (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_1458_4025[] = "Giga-Byte GV-R96128D Secondary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_148c_2067[] = "PowerColor R96A-C3N (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_174b_7c28[] = "GC-R9600PRO Secondary [Sapphire]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_17ee_2003[] = "Radeon 9600 256Mb Secondary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4170_18bc_0100[] = "GC-R9600PRO Secondary"; +#endif +static const char pci_device_1002_4171[] = "RV350 AQ [Radeon 9600] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4171_1043_c005[] = "A9600SE (Secondary)"; +#endif +static const char pci_device_1002_4172[] = "RV350 AR [Radeon 9600] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_1002_0003[] = "Radeon 9600XT (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_1002_4773[] = "All-in-Wonder 9600 XT (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_1043_c003[] = "A9600XT (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_1043_c01b[] = "A9600XT/TD (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_174b_7c28[] = "Sapphire Radeon 9600XT (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4172_1787_4003[] = "Radeon 9600 XT (Secondary)"; +#endif +static const char pci_device_1002_4173[] = "RV350 AS [Radeon 9550] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4173_1043_010d[] = "A9550GE/TD (Secondary)"; +#endif +static const char pci_device_1002_4237[] = "Radeon 7000 IGP"; +static const char pci_device_1002_4242[] = "R200 BB [Radeon All in Wonder 8500DV]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4242_1002_02aa[] = "Radeon 8500 AIW DV Edition"; +#endif +static const char pci_device_1002_4243[] = "R200 BC [Radeon All in Wonder 8500]"; +static const char pci_device_1002_4336[] = "Radeon Mobility U1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4336_1002_4336[] = "Pavilion ze4300 ATI Radeon Mobility U1 (IGP 320 M)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4336_103c_0024[] = "Pavilion ze4400 builtin Video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4336_161f_2029[] = "eMachines M5312 builtin Video"; +#endif +static const char pci_device_1002_4337[] = "Radeon IGP 330M/340M/350M"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4337_1014_053a[] = "ThinkPad R40e (2684-HVG) builtin VGA controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4337_103c_0850[] = "Radeon IGP 345M"; +#endif +static const char pci_device_1002_4341[] = "IXP150 AC'97 Audio Controller"; +static const char pci_device_1002_4345[] = "EHCI USB Controller"; +static const char pci_device_1002_4347[] = "OHCI USB Controller #1"; +static const char pci_device_1002_4348[] = "OHCI USB Controller #2"; +static const char pci_device_1002_4349[] = "ATI Dual Channel Bus Master PCI IDE Controller"; +static const char pci_device_1002_434d[] = "IXP AC'97 Modem"; +static const char pci_device_1002_4353[] = "ATI SMBus"; +static const char pci_device_1002_4354[] = "215CT [Mach64 CT]"; +static const char pci_device_1002_4358[] = "210888CX [Mach64 CX]"; +static const char pci_device_1002_4363[] = "ATI SMBus"; +static const char pci_device_1002_436e[] = "ATI 436E Serial ATA Controller"; +static const char pci_device_1002_4370[] = "IXP SB400 AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4370_1025_0079[] = "Aspire 5024WLMMi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4370_103c_308b[] = "MX6125"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4370_107b_0300[] = "MX6421"; +#endif +static const char pci_device_1002_4371[] = "IXP SB400 PCI-PCI Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4371_103c_308b[] = "MX6125"; +#endif +static const char pci_device_1002_4372[] = "IXP SB400 SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4372_1025_0080[] = "Aspire 5024WLMMi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4372_103c_308b[] = "MX6125"; +#endif +static const char pci_device_1002_4373[] = "IXP SB400 USB2 Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4373_1025_0080[] = "Aspire 5024WLMMi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4373_103c_308b[] = "MX6125"; +#endif +static const char pci_device_1002_4374[] = "IXP SB400 USB Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4374_103c_308b[] = "MX6125"; +#endif +static const char pci_device_1002_4375[] = "IXP SB400 USB Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4375_1025_0080[] = "Aspire 5024WLMMi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4375_103c_308b[] = "MX6125"; +#endif +static const char pci_device_1002_4376[] = "Standard Dual Channel PCI IDE Controller ATI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4376_1025_0080[] = "Aspire 5024WLMMi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4376_103c_308b[] = "MX6125"; +#endif +static const char pci_device_1002_4377[] = "IXP SB400 PCI-ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4377_1025_0080[] = "Aspire 5024WLMi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4377_103c_308b[] = "MX6125"; +#endif +static const char pci_device_1002_4378[] = "ATI SB400 - AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4378_1025_0080[] = "Aspire 5024WLMMi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4378_103c_308b[] = "MX6125"; +#endif +static const char pci_device_1002_4379[] = "ATI 4379 Serial ATA Controller"; +static const char pci_device_1002_437a[] = "ATI 437A Serial ATA Controller"; +static const char pci_device_1002_437b[] = "SB450 HDA Audio"; +static const char pci_device_1002_4380[] = "SB600 Non-Raid-5 SATA"; +static const char pci_device_1002_4381[] = "SB600 Raid-5 SATA"; +static const char pci_device_1002_4382[] = "SB600 AC97 Audio"; +static const char pci_device_1002_4383[] = "SB600 Azalia"; +static const char pci_device_1002_4384[] = "SB600 PCI to PCI Bridge"; +static const char pci_device_1002_4385[] = "SB600 SMBus"; +static const char pci_device_1002_4386[] = "SB600 USB Controller (EHCI)"; +static const char pci_device_1002_4387[] = "SB600 USB (OHCI0)"; +static const char pci_device_1002_4388[] = "SB600 USB (OHCI1)"; +static const char pci_device_1002_4389[] = "SB600 USB (OHCI2)"; +static const char pci_device_1002_438a[] = "SB600 USB (OHCI3)"; +static const char pci_device_1002_438b[] = "SB600 USB (OHCI4)"; +static const char pci_device_1002_438c[] = "SB600 IDE"; +static const char pci_device_1002_438d[] = "SB600 PCI to LPC Bridge"; +static const char pci_device_1002_438e[] = "SB600 AC97 Modem"; +static const char pci_device_1002_4437[] = "Radeon Mobility 7000 IGP"; +static const char pci_device_1002_4554[] = "210888ET [Mach64 ET]"; +static const char pci_device_1002_4654[] = "Mach64 VT"; +static const char pci_device_1002_4742[] = "3D Rage Pro AGP 1X/2X"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0040[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0044[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0061[] = "Rage Pro AIW AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0062[] = "Rage Pro AIW AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0063[] = "Rage Pro AIW AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0080[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_0084[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_4742[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1002_8001[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1028_0082[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1028_4082[] = "Optiplex GX1 Onboard Display Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1028_8082[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_1028_c082[] = "Rage Pro Turbo AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_8086_4152[] = "Xpert 98D AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4742_8086_464a[] = "Rage Pro Turbo AGP 2X"; +#endif +static const char pci_device_1002_4744[] = "3D Rage Pro AGP 1X"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4744_1002_4744[] = "Rage Pro Turbo AGP"; +#endif +static const char pci_device_1002_4747[] = "3D Rage Pro"; +static const char pci_device_1002_4749[] = "3D Rage Pro"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4749_1002_0061[] = "Rage Pro AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4749_1002_0062[] = "Rage Pro AIW"; +#endif +static const char pci_device_1002_474c[] = "Rage XC"; +static const char pci_device_1002_474d[] = "Rage XL AGP 2X"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_0004[] = "Xpert 98 RXL AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_0008[] = "Xpert 98 RXL AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_0080[] = "Rage XL AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_0084[] = "Xpert 98 AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1002_474d[] = "Rage XL AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474d_1033_806a[] = "Rage XL AGP"; +#endif +static const char pci_device_1002_474e[] = "Rage XC AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474e_1002_474e[] = "Rage XC AGP"; +#endif +static const char pci_device_1002_474f[] = "Rage XL"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474f_1002_0008[] = "Rage XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_474f_1002_474f[] = "Rage XL"; +#endif +static const char pci_device_1002_4750[] = "3D Rage Pro 215GP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_0040[] = "Rage Pro Turbo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_0044[] = "Rage Pro Turbo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_0080[] = "Rage Pro Turbo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_0084[] = "Rage Pro Turbo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4750_1002_4750[] = "Rage Pro Turbo"; +#endif +static const char pci_device_1002_4751[] = "3D Rage Pro 215GQ"; +static const char pci_device_1002_4752[] = "Rage XL"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_0e11_001e[] = "Proliant Rage XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1002_0008[] = "Rage XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1002_4752[] = "Proliant Rage XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1002_8008[] = "Rage XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1028_00ce[] = "PowerEdge 1400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1028_00d1[] = "PowerEdge 2550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1028_00d9[] = "PowerEdge 2500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1028_0134[] = "PowerEdge 600SC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_103c_10e1[] = "NetServer Rage XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_107b_6400[] = "6400 Server"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_1734_007a[] = "Primergy RX300"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_8086_3411[] = "SDS2 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4752_8086_3427[] = "S875WP1-E mainboard"; +#endif +static const char pci_device_1002_4753[] = "Rage XC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4753_1002_4753[] = "Rage XC"; +#endif +static const char pci_device_1002_4754[] = "3D Rage I/II 215GT [Mach64 GT]"; +static const char pci_device_1002_4755[] = "3D Rage II+ 215GTB [Mach64 GTB]"; +static const char pci_device_1002_4756[] = "3D Rage IIC 215IIC [Mach64 GT IIC]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4756_1002_4756[] = "Rage IIC"; +#endif +static const char pci_device_1002_4757[] = "3D Rage IIC AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1002_4757[] = "Rage IIC AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1028_0089[] = "Rage 3D IIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1028_008e[] = "PowerEdge 1300 onboard video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1028_4082[] = "Rage 3D IIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1028_8082[] = "Rage 3D IIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4757_1028_c082[] = "Rage 3D IIC"; +#endif +static const char pci_device_1002_4758[] = "210888GX [Mach64 GX]"; +static const char pci_device_1002_4759[] = "3D Rage IIC"; +static const char pci_device_1002_475a[] = "3D Rage IIC AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_475a_1002_0084[] = "Rage 3D Pro AGP 2x XPERT 98"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_475a_1002_0087[] = "Rage 3D IIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_475a_1002_475a[] = "Rage IIC AGP"; +#endif +static const char pci_device_1002_4964[] = "Radeon RV250 Id [Radeon 9000]"; +static const char pci_device_1002_4965[] = "Radeon RV250 Ie [Radeon 9000]"; +static const char pci_device_1002_4966[] = "Radeon RV250 If [Radeon 9000]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_10f1_0002[] = "RV250 If [Tachyon G9000 PRO]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_148c_2039[] = "RV250 If [Radeon 9000 Pro Evil Commando]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_1509_9a00[] = "RV250 If [Radeon 9000 AT009]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_1681_0040[] = "RV250 If [3D prophet 9000]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_174b_7176[] = "RV250 If [Sapphire Radeon 9000 Pro]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_174b_7192[] = "RV250 If [Radeon 9000 Atlantis]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_17af_2005[] = "RV250 If [Excalibur Radeon 9000 Pro]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4966_17af_2006[] = "RV250 If [Excalibur Radeon 9000]"; +#endif +static const char pci_device_1002_4967[] = "Radeon RV250 Ig [Radeon 9000]"; +static const char pci_device_1002_496e[] = "Radeon RV250 [Radeon 9000] (Secondary)"; +static const char pci_device_1002_4a48[] = "R420 JH [Radeon X800]"; +static const char pci_device_1002_4a49[] = "R420 JI [Radeon X800PRO]"; +static const char pci_device_1002_4a4a[] = "R420 JJ [Radeon X800SE]"; +static const char pci_device_1002_4a4b[] = "R420 JK [Radeon X800]"; +static const char pci_device_1002_4a4c[] = "R420 JL [Radeon X800]"; +static const char pci_device_1002_4a4d[] = "R420 JM [FireGL X3]"; +static const char pci_device_1002_4a4e[] = "M18 JN [Radeon Mobility 9800]"; +static const char pci_device_1002_4a50[] = "R420 JP [Radeon X800XT]"; +static const char pci_device_1002_4a54[] = "R420 [Radeon X800 VE]"; +static const char pci_device_1002_4a69[] = "R420 [Radeon X800 PRO/GTO] (Secondary)"; +static const char pci_device_1002_4a6a[] = "R420 [Radeon X800] (Secondary)"; +static const char pci_device_1002_4a6b[] = "R420 [Radeon X800] (Secondary)"; +static const char pci_device_1002_4a70[] = "R420 [X800XT-PE] (Secondary)"; +static const char pci_device_1002_4a74[] = "R420 [Radeon X800 VE] (Secondary)"; +static const char pci_device_1002_4b49[] = "R480 [Radeon X850XT]"; +static const char pci_device_1002_4b4b[] = "R480 [Radeon X850Pro]"; +static const char pci_device_1002_4b4c[] = "R481 [Radeon X850XT-PE]"; +static const char pci_device_1002_4b69[] = "R480 [Radeon X850XT] (Secondary)"; +static const char pci_device_1002_4b6b[] = "R480 [Radeon X850Pro] (Secondary)"; +static const char pci_device_1002_4b6c[] = "R481 [Radeon X850XT-PE] (Secondary)"; +static const char pci_device_1002_4c42[] = "3D Rage LT Pro AGP-133"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_0e11_b0e7[] = "Rage LT Pro (Compaq Presario 5240)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_0e11_b0e8[] = "Rage 3D LT Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_0e11_b10e[] = "3D Rage LT Pro (Compaq Armada 1750)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1002_0040[] = "Rage LT Pro AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1002_0044[] = "Rage LT Pro AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1002_4c42[] = "Rage LT Pro AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1002_8001[] = "Rage LT Pro AGP 2X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c42_1028_0085[] = "Rage 3D LT Pro"; +#endif +static const char pci_device_1002_4c44[] = "3D Rage LT Pro AGP-66"; +static const char pci_device_1002_4c45[] = "Rage Mobility M3 AGP"; +static const char pci_device_1002_4c46[] = "Rage Mobility M3 AGP 2x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c46_1028_00b1[] = "Latitude C600"; +#endif +static const char pci_device_1002_4c47[] = "3D Rage LT-G 215LG"; +static const char pci_device_1002_4c49[] = "3D Rage LT Pro"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c49_1002_0004[] = "Rage LT Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c49_1002_0040[] = "Rage LT Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c49_1002_0044[] = "Rage LT Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c49_1002_4c49[] = "Rage LT Pro"; +#endif +static const char pci_device_1002_4c4d[] = "Rage Mobility P/M AGP 2x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_0e11_b111[] = "Armada M700"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_0e11_b160[] = "Armada E500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_1002_0084[] = "Xpert 98 AGP 2X (Mobility)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_1014_0154[] = "ThinkPad A20m/A21m"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_1028_00aa[] = "Latitude CPt"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_1028_00bb[] = "Latitude CPx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_10e1_10cf[] = "Fujitsu Siemens LifeBook C Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_1179_ff00[] = "Satellite 1715XCDS laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c4d_13bd_1019[] = "PC-AR10"; +#endif +static const char pci_device_1002_4c4e[] = "Rage Mobility L AGP 2x"; +static const char pci_device_1002_4c50[] = "3D Rage LT Pro"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c50_1002_4c50[] = "Rage LT Pro"; +#endif +static const char pci_device_1002_4c51[] = "3D Rage LT Pro"; +static const char pci_device_1002_4c52[] = "Rage Mobility P/M"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c52_1033_8112[] = "Versa Note VXi"; +#endif +static const char pci_device_1002_4c53[] = "Rage Mobility L"; +static const char pci_device_1002_4c54[] = "264LT [Mach64 LT]"; +static const char pci_device_1002_4c57[] = "Radeon Mobility M7 LW [Radeon Mobility 7500]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c57_1014_0517[] = "ThinkPad T30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c57_1028_00e6[] = "Radeon Mobility M7 LW (Dell Inspiron 8100)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c57_1028_012a[] = "Latitude C640"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c57_144d_c006[] = "Radeon Mobility M7 LW in vpr Matrix 170B4"; +#endif +static const char pci_device_1002_4c58[] = "Radeon RV200 LX [Mobility FireGL 7800 M7]"; +static const char pci_device_1002_4c59[] = "Radeon Mobility M6 LY"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c59_0e11_b111[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c59_1014_0235[] = "ThinkPad A30/A30p (2652/2653)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c59_1014_0239[] = "ThinkPad X22/X23/X24"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c59_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c59_104d_8140[] = "PCG-Z1SP laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4c59_1509_1930[] = "Medion MD9703"; +#endif +static const char pci_device_1002_4c5a[] = "Radeon Mobility M6 LZ"; +static const char pci_device_1002_4c64[] = "Radeon R250 Ld [Radeon Mobility 9000 M9]"; +static const char pci_device_1002_4c65[] = "Radeon R250 Le [Radeon Mobility 9000 M9]"; +static const char pci_device_1002_4c66[] = "Radeon R250 [Mobility FireGL 9000]"; +static const char pci_device_1002_4c67[] = "Radeon R250 Lg [Radeon Mobility 9000 M9]"; +static const char pci_device_1002_4c6e[] = "Radeon R250 Ln [Radeon Mobility 9000 M9] [Secondary]"; +static const char pci_device_1002_4d46[] = "Rage Mobility M4 AGP"; +static const char pci_device_1002_4d4c[] = "Rage Mobility M4 AGP"; +static const char pci_device_1002_4e44[] = "Radeon R300 ND [Radeon 9700 Pro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e44_1002_515e[] = "Radeon ES1000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e44_1002_5965[] = "Radeon ES1000"; +#endif +static const char pci_device_1002_4e45[] = "Radeon R300 NE [Radeon 9500 Pro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e45_1002_0002[] = "Radeon R300 NE [Radeon 9500 Pro]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e45_1681_0002[] = "Hercules 3D Prophet 9500 PRO [Radeon 9500 Pro]"; +#endif +static const char pci_device_1002_4e46[] = "RV350 NF [Radeon 9600]"; +static const char pci_device_1002_4e47[] = "Radeon R300 NG [FireGL X1]"; +static const char pci_device_1002_4e48[] = "Radeon R350 [Radeon 9800 Pro]"; +static const char pci_device_1002_4e49[] = "Radeon R350 [Radeon 9800]"; +static const char pci_device_1002_4e4a[] = "RV350 NJ [Radeon 9800 XT]"; +static const char pci_device_1002_4e4b[] = "R350 NK [Fire GL X2]"; +static const char pci_device_1002_4e50[] = "RV350 [Mobility Radeon 9600 M10]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e50_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e50_103c_088c[] = "NC8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e50_103c_0890[] = "NC6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e50_1462_0311[] = "MSI M510A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e50_1734_1055[] = "Amilo M1420W"; +#endif +static const char pci_device_1002_4e51[] = "M10 NQ [Radeon Mobility 9600]"; +static const char pci_device_1002_4e52[] = "RV350 [Mobility Radeon 9600 M10]"; +static const char pci_device_1002_4e53[] = "M10 NS [Radeon Mobility 9600]"; +static const char pci_device_1002_4e54[] = "M10 NT [FireGL Mobility T2]"; +static const char pci_device_1002_4e56[] = "M11 NV [FireGL Mobility T2e]"; +static const char pci_device_1002_4e64[] = "Radeon R300 [Radeon 9700 Pro] (Secondary)"; +static const char pci_device_1002_4e65[] = "Radeon R300 [Radeon 9500 Pro] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e65_1002_0003[] = "Radeon R300 NE [Radeon 9500 Pro]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e65_1681_0003[] = "Hercules 3D Prophet 9500 PRO [Radeon 9500 Pro] (Secondary)"; +#endif +static const char pci_device_1002_4e66[] = "RV350 NF [Radeon 9600] (Secondary)"; +static const char pci_device_1002_4e67[] = "Radeon R300 [FireGL X1] (Secondary)"; +static const char pci_device_1002_4e68[] = "Radeon R350 [Radeon 9800 Pro] (Secondary)"; +static const char pci_device_1002_4e69[] = "Radeon R350 [Radeon 9800] (Secondary)"; +static const char pci_device_1002_4e6a[] = "RV350 NJ [Radeon 9800 XT] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_4e6a_1002_4e71[] = "ATI Technologies Inc M10 NQ [Radeon Mobility 9600]"; +#endif +static const char pci_device_1002_4e71[] = "M10 NQ [Radeon Mobility 9600] (Secondary)"; +static const char pci_device_1002_4f72[] = "RV250 [Radeon 9000 Series]"; +static const char pci_device_1002_4f73[] = "Radeon RV250 [Radeon 9000 Series] (Secondary)"; +static const char pci_device_1002_5041[] = "Rage 128 PA/PRO"; +static const char pci_device_1002_5042[] = "Rage 128 PB/PRO AGP 2x"; +static const char pci_device_1002_5043[] = "Rage 128 PC/PRO AGP 4x"; +static const char pci_device_1002_5044[] = "Rage 128 PD/PRO TMDS"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5044_1002_0028[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5044_1002_0029[] = "Rage 128 AIW"; +#endif +static const char pci_device_1002_5045[] = "Rage 128 PE/PRO AGP 2x TMDS"; +static const char pci_device_1002_5046[] = "Rage 128 PF/PRO AGP 4x TMDS"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0004[] = "Rage Fury Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0008[] = "Rage Fury Pro/Xpert 2000 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0014[] = "Rage Fury Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0018[] = "Rage Fury Pro/Xpert 2000 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0028[] = "Rage 128 Pro AIW AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_002a[] = "Rage 128 Pro AIW AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_0048[] = "Rage Fury Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_2000[] = "Rage Fury MAXX AGP 4x (TMDS) (VGA device)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5046_1002_2001[] = "Rage Fury MAXX AGP 4x (TMDS) (Extra device?!)"; +#endif +static const char pci_device_1002_5047[] = "Rage 128 PG/PRO"; +static const char pci_device_1002_5048[] = "Rage 128 PH/PRO AGP 2x"; +static const char pci_device_1002_5049[] = "Rage 128 PI/PRO AGP 4x"; +static const char pci_device_1002_504a[] = "Rage 128 PJ/PRO TMDS"; +static const char pci_device_1002_504b[] = "Rage 128 PK/PRO AGP 2x TMDS"; +static const char pci_device_1002_504c[] = "Rage 128 PL/PRO AGP 4x TMDS"; +static const char pci_device_1002_504d[] = "Rage 128 PM/PRO"; +static const char pci_device_1002_504e[] = "Rage 128 PN/PRO AGP 2x"; +static const char pci_device_1002_504f[] = "Rage 128 PO/PRO AGP 4x"; +static const char pci_device_1002_5050[] = "Rage 128 PP/PRO TMDS [Xpert 128]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5050_1002_0008[] = "Xpert 128"; +#endif +static const char pci_device_1002_5051[] = "Rage 128 PQ/PRO AGP 2x TMDS"; +static const char pci_device_1002_5052[] = "Rage 128 PR/PRO AGP 4x TMDS"; +static const char pci_device_1002_5053[] = "Rage 128 PS/PRO"; +static const char pci_device_1002_5054[] = "Rage 128 PT/PRO AGP 2x"; +static const char pci_device_1002_5055[] = "Rage 128 PU/PRO AGP 4x"; +static const char pci_device_1002_5056[] = "Rage 128 PV/PRO TMDS"; +static const char pci_device_1002_5057[] = "Rage 128 PW/PRO AGP 2x TMDS"; +static const char pci_device_1002_5058[] = "Rage 128 PX/PRO AGP 4x TMDS"; +static const char pci_device_1002_5144[] = "Radeon R100 QD [Radeon 7200]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0008[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0009[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_000a[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_001a[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0029[] = "Radeon AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0038[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0039[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_008a[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_00ba[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_0139[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_028a[] = "Radeon 7000/Radeon"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_02aa[] = "Radeon AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5144_1002_053a[] = "Radeon 7000/Radeon"; +#endif +static const char pci_device_1002_5145[] = "Radeon R100 QE"; +static const char pci_device_1002_5146[] = "Radeon R100 QF"; +static const char pci_device_1002_5147[] = "Radeon R100 QG"; +static const char pci_device_1002_5148[] = "Radeon R200 QH [Radeon 8500]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5148_1002_010a[] = "FireGL 8800 64Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5148_1002_0152[] = "FireGL 8800 128Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5148_1002_0162[] = "FireGL 8700 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5148_1002_0172[] = "FireGL 8700 64Mb"; +#endif +static const char pci_device_1002_5149[] = "Radeon R200 QI"; +static const char pci_device_1002_514a[] = "Radeon R200 QJ"; +static const char pci_device_1002_514b[] = "Radeon R200 QK"; +static const char pci_device_1002_514c[] = "Radeon R200 QL [Radeon 8500 LE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_514c_1002_003a[] = "Radeon R200 QL [Radeon 8500 LE]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_514c_1002_013a[] = "Radeon 8500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_514c_148c_2026[] = "R200 QL [Radeon 8500 Evil Master II Multi Display Edition]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_514c_1681_0010[] = "Radeon 8500 [3D Prophet 8500 128Mb]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_514c_174b_7149[] = "Radeon R200 QL [Sapphire Radeon 8500 LE]"; +#endif +static const char pci_device_1002_514d[] = "Radeon R200 QM [Radeon 9100]"; +static const char pci_device_1002_514e[] = "Radeon R200 QN [Radeon 8500LE]"; +static const char pci_device_1002_514f[] = "Radeon R200 QO [Radeon 8500LE]"; +static const char pci_device_1002_5154[] = "R200 QT [Radeon 8500]"; +static const char pci_device_1002_5155[] = "R200 QU [Radeon 9100]"; +static const char pci_device_1002_5157[] = "Radeon RV200 QW [Radeon 7500]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_1002_013a[] = "Radeon 7500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_1002_103a[] = "Dell Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_1458_4000[] = "RV200 QW [RADEON 7500 PRO MAYA AR]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_148c_2024[] = "RV200 QW [Radeon 7500LE Dual Display]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_148c_2025[] = "RV200 QW [Radeon 7500 Evil Master Multi Display Edition]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_148c_2036[] = "RV200 QW [Radeon 7500 PCI Dual Display]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_174b_7146[] = "RV200 QW [Radeon 7500 LE]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_174b_7147[] = "RV200 QW [Sapphire Radeon 7500LE]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_174b_7161[] = "Radeon RV200 QW [Radeon 7500 LE]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5157_17af_0202[] = "RV200 QW [Excalibur Radeon 7500LE]"; +#endif +static const char pci_device_1002_5158[] = "Radeon RV200 QX [Radeon 7500]"; +static const char pci_device_1002_5159[] = "Radeon RV100 QY [Radeon 7000/VE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_000a[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_000b[] = "Radeon 7000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_0038[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_003a[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_00ba[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_013a[] = "Radeon 7000/Radeon VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1002_0908[] = "XVR-100 (supplied by Sun)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1014_029a[] = "Remote Supervisor Adapter II (RSA2)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1014_02c8[] = "IBM eServer xSeries server mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_103c_1292[] = "Radeon 7000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1458_4002[] = "RV100 QY [RADEON 7000 PRO MAYA AV Series]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_148c_2003[] = "RV100 QY [Radeon 7000 Multi-Display Edition]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_148c_2023[] = "RV100 QY [Radeon 7000 Evil Master Multi-Display]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_174b_7112[] = "RV100 QY [Sapphire Radeon VE 7000]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_174b_7c28[] = "Sapphire Radeon VE 7000 DDR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_1787_0202[] = "RV100 QY [Excalibur Radeon 7000]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5159_17ee_1001[] = "Radeon 7000 64MB DDR + DVI"; +#endif +static const char pci_device_1002_515a[] = "Radeon RV100 QZ [Radeon 7000/VE]"; +static const char pci_device_1002_515e[] = "ES1000"; +static const char pci_device_1002_515f[] = "ES1000"; +static const char pci_device_1002_5168[] = "Radeon R200 Qh"; +static const char pci_device_1002_5169[] = "Radeon R200 Qi"; +static const char pci_device_1002_516a[] = "Radeon R200 Qj"; +static const char pci_device_1002_516b[] = "Radeon R200 Qk"; +static const char pci_device_1002_516c[] = "Radeon R200 Ql"; +static const char pci_device_1002_5245[] = "Rage 128 RE/SG"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5245_1002_0008[] = "Xpert 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5245_1002_0028[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5245_1002_0029[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5245_1002_0068[] = "Rage 128 AIW"; +#endif +static const char pci_device_1002_5246[] = "Rage 128 RF/SG AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0004[] = "Magnum/Xpert 128/Xpert 99"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0008[] = "Magnum/Xpert128/X99/Xpert2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0028[] = "Rage 128 AIW AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0044[] = "Rage Fury/Xpert 128/Xpert 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0068[] = "Rage 128 AIW AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5246_1002_0448[] = "Rage Fury"; +#endif +static const char pci_device_1002_5247[] = "Rage 128 RG"; +static const char pci_device_1002_524b[] = "Rage 128 RK/VR"; +static const char pci_device_1002_524c[] = "Rage 128 RL/VR AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_524c_1002_0008[] = "Xpert 99/Xpert 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_524c_1002_0088[] = "Xpert 99"; +#endif +static const char pci_device_1002_5345[] = "Rage 128 SE/4x"; +static const char pci_device_1002_5346[] = "Rage 128 SF/4x AGP 2x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5346_1002_0048[] = "RAGE 128 16MB VGA TVOUT AMC PAL"; +#endif +static const char pci_device_1002_5347[] = "Rage 128 SG/4x AGP 4x"; +static const char pci_device_1002_5348[] = "Rage 128 SH"; +static const char pci_device_1002_534b[] = "Rage 128 SK/4x"; +static const char pci_device_1002_534c[] = "Rage 128 SL/4x AGP 2x"; +static const char pci_device_1002_534d[] = "Rage 128 SM/4x AGP 4x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_534d_1002_0008[] = "Xpert 99/Xpert 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_534d_1002_0018[] = "Xpert 2000"; +#endif +static const char pci_device_1002_534e[] = "Rage 128 4x"; +static const char pci_device_1002_5354[] = "Mach 64 VT"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5354_1002_5654[] = "Mach 64 reference"; +#endif +static const char pci_device_1002_5446[] = "Rage 128 Pro Ultra TF"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0004[] = "Rage Fury Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0008[] = "Rage Fury Pro/Xpert 2000 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0018[] = "Rage Fury Pro/Xpert 2000 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0028[] = "Rage 128 AIW Pro AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0029[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_002a[] = "Rage 128 AIW Pro AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_002b[] = "Rage 128 AIW"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5446_1002_0048[] = "Xpert 2000 Pro"; +#endif +static const char pci_device_1002_544c[] = "Rage 128 Pro Ultra TL"; +static const char pci_device_1002_5452[] = "Rage 128 Pro Ultra TR"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5452_1002_001c[] = "Rage 128 Pro 4XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5452_103c_1279[] = "Rage 128 Pro 4XL"; +#endif +static const char pci_device_1002_5453[] = "Rage 128 Pro Ultra TS"; +static const char pci_device_1002_5454[] = "Rage 128 Pro Ultra TT"; +static const char pci_device_1002_5455[] = "Rage 128 Pro Ultra TU"; +static const char pci_device_1002_5460[] = "M22 [Radeon Mobility M300]"; +static const char pci_device_1002_5462[] = "M24 [Radeon Mobility X600]"; +static const char pci_device_1002_5464[] = "M22 [FireGL GL]"; +static const char pci_device_1002_5548[] = "R423 UH [Radeon X800 (PCIE)]"; +static const char pci_device_1002_5549[] = "R423 UI [Radeon X800PRO (PCIE)]"; +static const char pci_device_1002_554a[] = "R423 UJ [Radeon X800LE (PCIE)]"; +static const char pci_device_1002_554b[] = "R423 UK [Radeon X800SE (PCIE)]"; +static const char pci_device_1002_554d[] = "R430 [Radeon X800 XL] (PCIe)"; +static const char pci_device_1002_554f[] = "R430 [Radeon X800 (PCIE)]"; +static const char pci_device_1002_5550[] = "R423 [Fire GL V7100]"; +static const char pci_device_1002_5551[] = "R423 UQ [FireGL V7200 (PCIE)]"; +static const char pci_device_1002_5552[] = "R423 UR [FireGL V5100 (PCIE)]"; +static const char pci_device_1002_5554[] = "R423 UT [FireGL V7100 (PCIE)]"; +static const char pci_device_1002_5569[] = "R423 UI [Radeon X800PRO (PCIE)] Secondary"; +static const char pci_device_1002_556b[] = "Radeon R423 UK (PCIE) [X800 SE] (Secondary)"; +static const char pci_device_1002_556d[] = "R430 [Radeon X800 XL] (PCIe) Secondary"; +static const char pci_device_1002_556f[] = "R430 [Radeon X800 (PCIE) Secondary]"; +static const char pci_device_1002_5571[] = "R423GL-SE ATI FIREGL V5100 PCI-EX Secondary"; +static const char pci_device_1002_564a[] = "M26 [Mobility FireGL V5000]"; +static const char pci_device_1002_564b[] = "M26 [Mobility FireGL V5000]"; +static const char pci_device_1002_564f[] = "M26 [Radeon Mobility X700 XL] (PCIE)"; +static const char pci_device_1002_5652[] = "M26 [Radeon Mobility X700]"; +static const char pci_device_1002_5653[] = "Radeon Mobility X700 (PCIE)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5653_1025_0080[] = "Aspire 5024WLMi"; +#endif +static const char pci_device_1002_5654[] = "264VT [Mach64 VT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5654_1002_5654[] = "Mach64VT Reference"; +#endif +static const char pci_device_1002_5655[] = "264VT3 [Mach64 VT3]"; +static const char pci_device_1002_5656[] = "264VT4 [Mach64 VT4]"; +static const char pci_device_1002_5830[] = "RS300 Host Bridge"; +static const char pci_device_1002_5831[] = "RS300 Host Bridge"; +static const char pci_device_1002_5832[] = "RS300 Host Bridge"; +static const char pci_device_1002_5833[] = "Radeon 9100 IGP Host Bridge"; +static const char pci_device_1002_5834[] = "Radeon 9100 IGP"; +static const char pci_device_1002_5835[] = "RS300M AGP [Radeon Mobility 9100IGP]"; +static const char pci_device_1002_5838[] = "Radeon 9100 IGP AGP Bridge"; +static const char pci_device_1002_5940[] = "RV280 [Radeon 9200 PRO] (Secondary)"; +static const char pci_device_1002_5941[] = "RV280 [Radeon 9200] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5941_1458_4019[] = "Gigabyte Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5941_174b_7c12[] = "Sapphire Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5941_17af_200d[] = "Excalibur Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5941_18bc_0050[] = "GeXcube GC-R9200-C3 (Secondary)"; +#endif +static const char pci_device_1002_5944[] = "RV280 [Radeon 9200 SE (PCI)]"; +static const char pci_device_1002_5950[] = "RS480 Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5950_1025_0080[] = "Aspire 5024WLMMi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5950_103c_308b[] = "MX6125"; +#endif +static const char pci_device_1002_5951[] = "ATI Radeon Xpress 200 (RS480/RS482/RX480/RX482) Chipset - Host bridge"; +static const char pci_device_1002_5954[] = "RS480 [Radeon Xpress 200G Series]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5954_1002_5954[] = "RV370 [Radeon Xpress 200G Series]"; +#endif +static const char pci_device_1002_5955[] = "ATI Radeon XPRESS 200M 5955 (PCIE)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5955_1002_5955[] = "RS480 0x5955 [ATI Radeon XPRESS 200M 5955 (PCIE)]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5955_103c_308b[] = "MX6125"; +#endif +static const char pci_device_1002_5960[] = "RV280 [Radeon 9200 PRO]"; +static const char pci_device_1002_5961[] = "RV280 [Radeon 9200]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_1002_2f72[] = "All-in-Wonder 9200 Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_1019_4c30[] = "Radeon 9200 VIVO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_12ab_5961[] = "YUAN SMARTVGA Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_1458_4018[] = "Gigabyte Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_174b_7c13[] = "Sapphire Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_17af_200c[] = "Excalibur Radeon 9200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_18bc_0050[] = "Radeon 9200 Game Buster"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_18bc_0051[] = "GeXcube GC-R9200-C3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5961_18bc_0053[] = "Radeon 9200 Game Buster VIVO"; +#endif +static const char pci_device_1002_5962[] = "RV280 [Radeon 9200]"; +static const char pci_device_1002_5964[] = "RV280 [Radeon 9200 SE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_1043_c006[] = "ASUS Radeon 9200 SE / TD / 128M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_1458_4018[] = "Radeon 9200 SE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_1458_4032[] = "Radeon 9200 SE 128MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_147b_6191[] = "R9200SE-DT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_148c_2073[] = "CN-AG92E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_174b_7c13[] = "Sapphire Radeon 9200 SE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_1787_5964[] = "Excalibur 9200SE VIVO 128M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_17af_2012[] = "Radeon 9200 SE Excalibur"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_18bc_0170[] = "Sapphire Radeon 9200 SE 128MB Game Buster"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5964_18bc_0173[] = "GC-R9200L(SE)-C3H [Radeon 9200 Game Buster]"; +#endif +static const char pci_device_1002_5969[] = "ES1000"; +static const char pci_device_1002_5974[] = "RS482 [Radeon Xpress 200]"; +static const char pci_device_1002_5975[] = "RS482 [Radeon Xpress 200M]"; +static const char pci_device_1002_5a33[] = "Radeon Xpress 200 Host Bridge"; +static const char pci_device_1002_5a34[] = "RS480 PCI-X Root Port"; +static const char pci_device_1002_5a36[] = "RS480 PCI Bridge"; +static const char pci_device_1002_5a38[] = "RS480 PCI Bridge"; +static const char pci_device_1002_5a39[] = "RS480 PCI Bridge"; +static const char pci_device_1002_5a3f[] = "RS480 PCI Bridge"; +static const char pci_device_1002_5a41[] = "RS400 [Radeon Xpress 200]"; +static const char pci_device_1002_5a42[] = "RS400 [Radeon Xpress 200M]"; +static const char pci_device_1002_5a61[] = "RC410 [Radeon Xpress 200]"; +static const char pci_device_1002_5a62[] = "RC410 [Radeon Xpress 200M]"; +static const char pci_device_1002_5b60[] = "RV370 5B60 [Radeon X300 (PCIE)]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5b60_1043_002a[] = "Extreme AX300SE-X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5b60_1043_032e[] = "Extreme AX300/TD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5b60_1462_0400[] = "RX300SE-TD128E (MS-8940 REV:200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5b60_1462_0402[] = "RX300SE-TD128E (MS-8940)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5b60_196d_1086[] = "X300SE HM"; +#endif +static const char pci_device_1002_5b62[] = "RV380 [Radeon X600 (PCIE)]"; +static const char pci_device_1002_5b63[] = "RV370 [Sapphire X550 Silent]"; +static const char pci_device_1002_5b64[] = "RV370 5B64 [FireGL V3100 (PCIE)]"; +static const char pci_device_1002_5b65[] = "RV370 5B65 [FireGL D1100 (PCIE)]"; +static const char pci_device_1002_5b70[] = "RV370 [Radeon X300SE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5b70_1462_0403[] = "RX300SE-TD128E (MS-8940) (secondary display)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5b70_196d_1087[] = "X300SE HM"; +#endif +static const char pci_device_1002_5b72[] = "RV380 [Radeon X600]"; +static const char pci_device_1002_5b73[] = "RV370 secondary [Sapphire X550 Silent]"; +static const char pci_device_1002_5b74[] = "RV370 5B64 [FireGL V3100 (PCIE)] (Secondary)"; +static const char pci_device_1002_5c61[] = "M9+ 5C61 [Radeon Mobility 9200 (AGP)]"; +static const char pci_device_1002_5c63[] = "M9+ 5C63 [Radeon Mobility 9200 (AGP)]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5c63_1002_5c63[] = "Apple iBook G4 2004"; +#endif +static const char pci_device_1002_5d44[] = "RV280 [Radeon 9200 SE] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_1458_4019[] = "Radeon 9200 SE (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_1458_4032[] = "Radeon 9200 SE 128MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_174b_7c12[] = "Sapphire Radeon 9200 SE (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_1787_5965[] = "Excalibur 9200SE VIVO 128M (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_17af_2013[] = "Radeon 9200 SE Excalibur (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_18bc_0171[] = "Radeon 9200 SE 128MB Game Buster (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d44_18bc_0172[] = "GC-R9200L(SE)-C3H [Radeon 9200 Game Buster]"; +#endif +static const char pci_device_1002_5d48[] = "M28 [Radeon Mobility X800XT]"; +static const char pci_device_1002_5d49[] = "M28 [Mobility FireGL V5100]"; +static const char pci_device_1002_5d4a[] = "Mobility Radeon X800"; +static const char pci_device_1002_5d4d[] = "R480 [Radeon X850XT Platinum (PCIE)]"; +static const char pci_device_1002_5d4f[] = "R480 [Radeon X800 GTO (PCIE)]"; +static const char pci_device_1002_5d52[] = "R480 [Radeon X850XT (PCIE)] (Primary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d52_1002_0b12[] = "PowerColor X850XT PCIe Primary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5d52_1002_0b13[] = "PowerColor X850XT PCIe Secondary"; +#endif +static const char pci_device_1002_5d57[] = "R423 5F57 [Radeon X800XT (PCIE)]"; +static const char pci_device_1002_5d6d[] = "R480 [Radeon X850XT Platinum (PCIE)] (Secondary)"; +static const char pci_device_1002_5d6f[] = "R480 [Radeon X800 GTO (PCIE)] (Secondary)"; +static const char pci_device_1002_5d72[] = "R480 [Radeon X850XT (PCIE)] (Secondary)"; +static const char pci_device_1002_5d77[] = "R423 5F57 [Radeon X800XT (PCIE)] (Secondary)"; +static const char pci_device_1002_5e48[] = "RV410 [FireGL V5000]"; +static const char pci_device_1002_5e49[] = "RV410 [FireGL V3300]"; +static const char pci_device_1002_5e4a[] = "RV410 [Radeon X700XT]"; +static const char pci_device_1002_5e4b[] = "RV410 [Radeon X700 Pro (PCIE)]"; +static const char pci_device_1002_5e4c[] = "RV410 [Radeon X700SE]"; +static const char pci_device_1002_5e4d[] = "RV410 [Radeon X700 (PCIE)]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5e4d_148c_2116[] = "PowerColor Bravo X700"; +#endif +static const char pci_device_1002_5e4f[] = "RV410 [Radeon X700]"; +static const char pci_device_1002_5e6b[] = "RV410 [Radeon X700 Pro (PCIE)] Secondary"; +static const char pci_device_1002_5e6d[] = "RV410 [Radeon X700 (PCIE)] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_5e6d_148c_2117[] = "PowerColor Bravo X700"; +#endif +static const char pci_device_1002_5f57[] = "R423 [Radeon X800XT (PCIE)]"; +static const char pci_device_1002_700f[] = "PCI Bridge [IGP 320M]"; +static const char pci_device_1002_7010[] = "PCI Bridge [IGP 340M]"; +static const char pci_device_1002_7100[] = "R520 [Radeon X1800]"; +static const char pci_device_1002_7102[] = "M58 [Radeon Mobility X1800]"; +static const char pci_device_1002_7103[] = "M58 [Mobility FireGL V7200]"; +static const char pci_device_1002_7104[] = "R520 GL ATI FireGL V7200 Primary"; +static const char pci_device_1002_7105[] = "R520 [FireGL]"; +static const char pci_device_1002_7106[] = "M58 [Mobility FireGL V7100]"; +static const char pci_device_1002_7108[] = "M58 [Radeon Mobility X1800]"; +static const char pci_device_1002_7109[] = "R520 [Radeon X1800]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_7109_1002_0322[] = "All-in-Wonder X1800XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_7109_1002_0d02[] = "Radeon X1800 CrossFire Edition"; +#endif +static const char pci_device_1002_710a[] = "R520 [Radeon X1800]"; +static const char pci_device_1002_710b[] = "R520 [Radeon X1800]"; +static const char pci_device_1002_710c[] = "R520 [Radeon X1800]"; +static const char pci_device_1002_7120[] = "R520 [Radeon X1800] (Secondary)"; +static const char pci_device_1002_7124[] = "R520 GL ATI FireGL V7200 Secondary"; +static const char pci_device_1002_7129[] = "R520 [Radeon X1800] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_7129_1002_0323[] = "All-in-Wonder X1800XL (Secondary)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_7129_1002_0d03[] = "Radeon X1800 CrossFire Edition (Secondary)"; +#endif +static const char pci_device_1002_7140[] = "RV515 [Radeon X1600]"; +static const char pci_device_1002_7142[] = "RV515 [Radeon X1300]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_7142_1002_0322[] = "All-in-Wonder 2006 PCI-E Edition"; +#endif +static const char pci_device_1002_7145[] = "Radeon Mobility X1400"; +static const char pci_device_1002_7146[] = "RV515 [Radeon X1300]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_7146_1002_0322[] = "All-in-Wonder 2006 PCI-E Edition"; +#endif +static const char pci_device_1002_7149[] = "M52 [ATI Mobility Radeon X1300]"; +static const char pci_device_1002_714a[] = "M52 [ATI Mobility Radeon X1300]"; +static const char pci_device_1002_714b[] = "M52 [ATI Mobility Radeon X1300]"; +static const char pci_device_1002_714c[] = "M52 [ATI Mobility Radeon X1300]"; +static const char pci_device_1002_714d[] = "RV515 [Radeon X1300]"; +static const char pci_device_1002_714e[] = "RV515 [Radeon X1300]"; +static const char pci_device_1002_7152[] = "RV515 GL ATI FireGL V3300 Primary"; +static const char pci_device_1002_715e[] = "RV515 [Radeon X1300]"; +static const char pci_device_1002_7162[] = "RV515 [Radeon X1300] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_7162_1002_0323[] = "All-in-Wonder 2006 PCI-E Edition (Secondary)"; +#endif +static const char pci_device_1002_7166[] = "RV515 [Radeon X1300] (Secondary)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_7166_1002_0323[] = "All-in-Wonder 2006 PCI-E Edition (Secondary)"; +#endif +static const char pci_device_1002_7172[] = "RV515 GL ATI FireGL V3300 Secondary"; +static const char pci_device_1002_7180[] = "RV516 Radeon X1300 Series Primary"; +static const char pci_device_1002_7181[] = "RV516 XT Radeon X1600 Series Primary"; +static const char pci_device_1002_71a0[] = "RV516 Radeon X1300 Series Secondary"; +static const char pci_device_1002_71a1[] = "RV516 XT Radeon X1600 Series Secondary"; +static const char pci_device_1002_71c0[] = "RV530 [Radeon X1600]"; +static const char pci_device_1002_71c2[] = "RV530 [Radeon X1600]"; +static const char pci_device_1002_71c4[] = "M56GL [ATI Mobility FireGL V5200]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1002_71c4_17aa_2007[] = "ThinkPad T60p"; +#endif +static const char pci_device_1002_71c5[] = "M56P [Radeon Mobility X1600]"; +static const char pci_device_1002_71c6[] = "RV530LE [Radeon X1600]"; +static const char pci_device_1002_71ce[] = "RV530LE [Radeon X1600]"; +static const char pci_device_1002_71d5[] = "M66-P ATI Mobility Radeon X1700"; +static const char pci_device_1002_71d6[] = "M66-XT ATI Mobility Radeon X1700"; +static const char pci_device_1002_71de[] = "RV530LE [Radeon X1600]"; +static const char pci_device_1002_71e0[] = "RV530 [Radeon X1600] (Secondary)"; +static const char pci_device_1002_71e2[] = "RV530 [Radeon X1600] (Secondary)"; +static const char pci_device_1002_7240[] = "R580 [Radeon X1900]"; +static const char pci_device_1002_7241[] = "R580 [Radeon X1900]"; +static const char pci_device_1002_7242[] = "R580 [Radeon X1900]"; +static const char pci_device_1002_7243[] = "R580 [Radeon X1900]"; +static const char pci_device_1002_7244[] = "R580 [Radeon X1900]"; +static const char pci_device_1002_7245[] = "R580 [Radeon X1900]"; +static const char pci_device_1002_7246[] = "R580 [Radeon X1900]"; +static const char pci_device_1002_7247[] = "R580 [Radeon X1900]"; +static const char pci_device_1002_7248[] = "R580 [Radeon X1900]"; +static const char pci_device_1002_7249[] = "R580 [Radeon X1900 XT] Primary"; +static const char pci_device_1002_724a[] = "R580 [Radeon X1900]"; +static const char pci_device_1002_724b[] = "R580 [Radeon X1900]"; +static const char pci_device_1002_724c[] = "R580 [Radeon X1900]"; +static const char pci_device_1002_724d[] = "R580 [Radeon X1900]"; +static const char pci_device_1002_724e[] = "R580 [FireGL V7300/V7350] Primary (PCIE)"; +static const char pci_device_1002_7269[] = "R580 [Radeon X1900 XT] Secondary"; +static const char pci_device_1002_726e[] = "R580 [FireGL V7300/V7350] Secondary (PCIE)"; +static const char pci_device_1002_7833[] = "Radeon 9100 IGP Host Bridge"; +static const char pci_device_1002_7834[] = "Radeon 9100 PRO IGP"; +static const char pci_device_1002_7835[] = "Radeon Mobility 9200 IGP"; +static const char pci_device_1002_7838[] = "Radeon 9100 IGP PCI/AGP Bridge"; +static const char pci_device_1002_7c37[] = "RV350 AQ [Radeon 9600 SE]"; +static const char pci_device_1002_cab0[] = "AGP Bridge [IGP 320M]"; +static const char pci_device_1002_cab2[] = "RS200/RS200M AGP Bridge [IGP 340M]"; +static const char pci_device_1002_cab3[] = "R200 AGP Bridge [Mobility Radeon 7000 IGP]"; +static const char pci_device_1002_cbb2[] = "RS200/RS200M AGP Bridge [IGP 340M]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1003[] = "ULSI Systems"; +static const char pci_device_1003_0201[] = "US201"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1004[] = "VLSI Technology Inc"; +static const char pci_device_1004_0005[] = "82C592-FC1"; +static const char pci_device_1004_0006[] = "82C593-FC1"; +static const char pci_device_1004_0007[] = "82C594-AFC2"; +static const char pci_device_1004_0008[] = "82C596/7 [Wildcat]"; +static const char pci_device_1004_0009[] = "82C597-AFC2"; +static const char pci_device_1004_000c[] = "82C541 [Lynx]"; +static const char pci_device_1004_000d[] = "82C543 [Lynx]"; +static const char pci_device_1004_0101[] = "82C532"; +static const char pci_device_1004_0102[] = "82C534 [Eagle]"; +static const char pci_device_1004_0103[] = "82C538"; +static const char pci_device_1004_0104[] = "82C535"; +static const char pci_device_1004_0105[] = "82C147"; +static const char pci_device_1004_0200[] = "82C975"; +static const char pci_device_1004_0280[] = "82C925"; +static const char pci_device_1004_0304[] = "QSound ThunderBird PCI Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0304_1004_0304[] = "QSound ThunderBird PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0304_122d_1206[] = "DSP368 Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0304_1483_5020[] = "XWave Thunder 3D Audio"; +#endif +static const char pci_device_1004_0305[] = "QSound ThunderBird PCI Audio Gameport"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0305_1004_0305[] = "QSound ThunderBird PCI Audio Gameport"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0305_122d_1207[] = "DSP368 Audio Gameport"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0305_1483_5021[] = "XWave Thunder 3D Audio Gameport"; +#endif +static const char pci_device_1004_0306[] = "QSound ThunderBird PCI Audio Support Registers"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0306_1004_0306[] = "QSound ThunderBird PCI Audio Support Registers"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0306_122d_1208[] = "DSP368 Audio Support Registers"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1004_0306_1483_5022[] = "XWave Thunder 3D Audio Support Registers"; +#endif +static const char pci_device_1004_0307[] = "Thunderbird"; +static const char pci_device_1004_0308[] = "Thunderbird"; +static const char pci_device_1004_0702[] = "VAS96011 [Golden Gate II]"; +static const char pci_device_1004_0703[] = "Tollgate"; +#endif +static const char pci_vendor_1005[] = "Avance Logic Inc. [ALI]"; +static const char pci_device_1005_2064[] = "ALG2032/2064"; +static const char pci_device_1005_2128[] = "ALG2364A"; +static const char pci_device_1005_2301[] = "ALG2301"; +static const char pci_device_1005_2302[] = "ALG2302"; +static const char pci_device_1005_2364[] = "ALG2364"; +static const char pci_device_1005_2464[] = "ALG2364A"; +static const char pci_device_1005_2501[] = "ALG2564A/25128A"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1006[] = "Reply Group"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1007[] = "NetFrame Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1008[] = "Epson"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_100a[] = "Phoenix Technologies"; +#endif +static const char pci_vendor_100b[] = "National Semiconductor Corporation"; +static const char pci_device_100b_0001[] = "DP83810"; +static const char pci_device_100b_0002[] = "87415/87560 IDE"; +static const char pci_device_100b_000e[] = "87560 Legacy I/O"; +static const char pci_device_100b_000f[] = "FireWire Controller"; +static const char pci_device_100b_0011[] = "NS87560 National PCI System I/O"; +static const char pci_device_100b_0012[] = "USB Controller"; +static const char pci_device_100b_0020[] = "DP83815 (MacPhyter) Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_100b_0020_103c_0024[] = "Pavilion ze4400 builtin Network"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_100b_0020_12d9_000c[] = "Aculab E1/T1 PMXc cPCI carrier card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_100b_0020_1385_f311[] = "FA311 / FA312 (FA311 with WoL HW)"; +#endif +static const char pci_device_100b_0021[] = "PC87200 PCI to ISA Bridge"; +static const char pci_device_100b_0022[] = "DP83820 10/100/1000 Ethernet Controller"; +static const char pci_device_100b_0028[] = "Geode GX2 Host Bridge"; +static const char pci_device_100b_002a[] = "CS5535 South Bridge"; +static const char pci_device_100b_002b[] = "CS5535 ISA bridge"; +static const char pci_device_100b_002d[] = "CS5535 IDE"; +static const char pci_device_100b_002e[] = "CS5535 Audio"; +static const char pci_device_100b_002f[] = "CS5535 USB"; +static const char pci_device_100b_0030[] = "Geode GX2 Graphics Processor"; +static const char pci_device_100b_0035[] = "DP83065 [Saturn] 10/100/1000 Ethernet Controller"; +static const char pci_device_100b_0500[] = "SCx200 Bridge"; +static const char pci_device_100b_0501[] = "SCx200 SMI"; +static const char pci_device_100b_0502[] = "SCx200 IDE"; +static const char pci_device_100b_0503[] = "SCx200 Audio"; +static const char pci_device_100b_0504[] = "SCx200 Video"; +static const char pci_device_100b_0505[] = "SCx200 XBus"; +static const char pci_device_100b_0510[] = "SC1100 Bridge"; +static const char pci_device_100b_0511[] = "SC1100 SMI"; +static const char pci_device_100b_0515[] = "SC1100 XBus"; +static const char pci_device_100b_d001[] = "87410 IDE"; +static const char pci_vendor_100c[] = "Tseng Labs Inc"; +static const char pci_device_100c_3202[] = "ET4000/W32p rev A"; +static const char pci_device_100c_3205[] = "ET4000/W32p rev B"; +static const char pci_device_100c_3206[] = "ET4000/W32p rev C"; +static const char pci_device_100c_3207[] = "ET4000/W32p rev D"; +static const char pci_device_100c_3208[] = "ET6000"; +static const char pci_device_100c_4702[] = "ET6300"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_100d[] = "AST Research Inc"; +#endif +static const char pci_vendor_100e[] = "Weitek"; +static const char pci_device_100e_9000[] = "P9000 Viper"; +static const char pci_device_100e_9001[] = "P9000 Viper"; +static const char pci_device_100e_9002[] = "P9000 Viper"; +static const char pci_device_100e_9100[] = "P9100 Viper Pro/SE"; +static const char pci_vendor_1010[] = "Video Logic, Ltd."; +static const char pci_vendor_1011[] = "Digital Equipment Corporation"; +static const char pci_device_1011_0001[] = "DECchip 21050"; +static const char pci_device_1011_0002[] = "DECchip 21040 [Tulip]"; +static const char pci_device_1011_0004[] = "DECchip 21030 [TGA]"; +static const char pci_device_1011_0007[] = "NVRAM [Zephyr NVRAM]"; +static const char pci_device_1011_0008[] = "KZPSA [KZPSA]"; +static const char pci_device_1011_0009[] = "DECchip 21140 [FasterNet]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1025_0310[] = "21140 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_10b8_2001[] = "SMC9332BDT EtherPower 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_10b8_2002[] = "SMC9332BVT EtherPower T4 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_10b8_2003[] = "SMC9334BDT EtherPower 10/100 (1-port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1109_2400[] = "ANA-6944A/TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1112_2300[] = "RNS2300 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1112_2320[] = "RNS2320 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1112_2340[] = "RNS2340 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1113_1207[] = "EN-1207-TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1186_1100[] = "DFE-500TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1186_1112[] = "DFE-570TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1186_1140[] = "DFE-660 Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1186_1142[] = "DFE-660 Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_11f6_0503[] = "Freedomline Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1282_9100[] = "AEF-380TXD Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_1385_1100[] = "FA310TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0009_2646_0001[] = "KNE100TX Fast Ethernet"; +#endif +static const char pci_device_1011_000a[] = "21230 Video Codec"; +static const char pci_device_1011_000d[] = "PBXGB [TGA2]"; +static const char pci_device_1011_000f[] = "PCI-to-PDQ Interface Chip [PFI]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_000f_1011_def1[] = "FDDI controller (DEFPA)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_000f_103c_def1[] = "FDDI controller (3X-DEFPA)"; +#endif +static const char pci_device_1011_0014[] = "DECchip 21041 [Tulip Pass 3]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0014_1186_0100[] = "DE-530+"; +#endif +static const char pci_device_1011_0016[] = "DGLPB [OPPO]"; +static const char pci_device_1011_0017[] = "PV-PCI Graphics Controller (ZLXp-L)"; +static const char pci_device_1011_0019[] = "DECchip 21142/43"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1011_500a[] = "DE500A Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1011_500b[] = "DE500B Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1014_0001[] = "10/100 EtherJet Cardbus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1025_0315[] = "ALN315 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1033_800c[] = "PC-9821-CS01 100BASE-TX Interface Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1033_800d[] = "PC-9821NR-B06 100BASE-TX Interface Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_103c_125a[] = "10/100Base-TX (PCI) [A5506B]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_108d_0016[] = "Rapidfire 2327 10/100 Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_108d_0017[] = "GoCard 2250 Ethernet 10/100 Cardbus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_10b8_2005[] = "SMC8032DT Extreme Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_10b8_8034[] = "SMC8034 Extreme Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_10ef_8169[] = "Cardbus Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1109_2a00[] = "ANA-6911A/TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1109_2b00[] = "ANA-6911A/TXC Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1109_3000[] = "ANA-6922/TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1113_1207[] = "Cheetah Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1113_2220[] = "Cardbus Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_115d_0002[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1179_0203[] = "Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1179_0204[] = "Cardbus Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1186_1100[] = "DFE-500TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1186_1101[] = "DFE-500TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1186_1102[] = "DFE-500TX Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1186_1112[] = "DFE-570TX Quad Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1259_2800[] = "AT-2800Tx Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1266_0004[] = "Eagle Fast EtherMAX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_12af_0019[] = "NetFlyer Cardbus Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1374_0001[] = "Cardbus Ethernet Card 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1374_0002[] = "Cardbus Ethernet Card 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1374_0007[] = "Cardbus Ethernet Card 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1374_0008[] = "Cardbus Ethernet Card 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1385_2100[] = "FA510"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1395_0001[] = "10/100 Ethernet CardBus PC Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_13d1_ab01[] = "EtherFast 10/100 Cardbus (PCMPC200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1498_000a[] = "TPMC880-10 10/100Base-T and 10Base2 PMC Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1498_000b[] = "TPMC880-11 Single 10/100Base-T PMC Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_1498_000c[] = "TPMC880-12 Single 10Base2 PMC Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_14cb_0100[] = "LNDL-100N 100Base-TX Ethernet PC Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0019_8086_0001[] = "EtherExpress PRO/100 Mobile CardBus 32"; +#endif +static const char pci_device_1011_001a[] = "Farallon PN9000SX Gigabit Ethernet"; +static const char pci_device_1011_0021[] = "DECchip 21052"; +static const char pci_device_1011_0022[] = "DECchip 21150"; +static const char pci_device_1011_0023[] = "DECchip 21150"; +static const char pci_device_1011_0024[] = "DECchip 21152"; +static const char pci_device_1011_0025[] = "DECchip 21153"; +static const char pci_device_1011_0026[] = "DECchip 21154"; +static const char pci_device_1011_0034[] = "56k Modem Cardbus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0034_1374_0003[] = "56k Modem Cardbus"; +#endif +static const char pci_device_1011_0045[] = "DECchip 21553"; +static const char pci_device_1011_0046[] = "DECchip 21554"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_0e11_4050[] = "Integrated Smart Array"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_0e11_4051[] = "Integrated Smart Array"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_0e11_4058[] = "Integrated Smart Array"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_103c_10c2[] = "NetRAID-4M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_12d9_000a[] = "IP Telephony card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_4c53_1051[] = "CE7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_9005_0364[] = "5400S (Mustang)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_9005_0365[] = "5400S (Mustang)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_9005_1364[] = "Dell PowerEdge RAID Controller 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_9005_1365[] = "Dell PowerEdge RAID Controller 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_0046_e4bf_1000[] = "CC8-1-BLUES"; +#endif +static const char pci_device_1011_1065[] = "StrongARM DC21285"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1011_1065_1069_0020[] = "DAC960P / DAC1164P"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1012[] = "Micronics Computers Inc"; +#endif +static const char pci_vendor_1013[] = "Cirrus Logic"; +static const char pci_device_1013_0038[] = "GD 7548"; +static const char pci_device_1013_0040[] = "GD 7555 Flat Panel GUI Accelerator"; +static const char pci_device_1013_004c[] = "GD 7556 Video/Graphics LCD/CRT Ctrlr"; +static const char pci_device_1013_00a0[] = "GD 5430/40 [Alpine]"; +static const char pci_device_1013_00a2[] = "GD 5432 [Alpine]"; +static const char pci_device_1013_00a4[] = "GD 5434-4 [Alpine]"; +static const char pci_device_1013_00a8[] = "GD 5434-8 [Alpine]"; +static const char pci_device_1013_00ac[] = "GD 5436 [Alpine]"; +static const char pci_device_1013_00b0[] = "GD 5440"; +static const char pci_device_1013_00b8[] = "GD 5446"; +static const char pci_device_1013_00bc[] = "GD 5480"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_00bc_1013_00bc[] = "CL-GD5480"; +#endif +static const char pci_device_1013_00d0[] = "GD 5462"; +static const char pci_device_1013_00d2[] = "GD 5462 [Laguna I]"; +static const char pci_device_1013_00d4[] = "GD 5464 [Laguna]"; +static const char pci_device_1013_00d5[] = "GD 5464 BD [Laguna]"; +static const char pci_device_1013_00d6[] = "GD 5465 [Laguna]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_00d6_13ce_8031[] = "Barco Metheus 2 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_00d6_13cf_8031[] = "Barco Metheus 2 Megapixel, Dual Head"; +#endif +static const char pci_device_1013_00e8[] = "GD 5436U"; +static const char pci_device_1013_1100[] = "CL 6729"; +static const char pci_device_1013_1110[] = "PD 6832 PCMCIA/CardBus Ctrlr"; +static const char pci_device_1013_1112[] = "PD 6834 PCMCIA/CardBus Ctrlr"; +static const char pci_device_1013_1113[] = "PD 6833 PCMCIA/CardBus Ctrlr"; +static const char pci_device_1013_1200[] = "GD 7542 [Nordic]"; +static const char pci_device_1013_1202[] = "GD 7543 [Viking]"; +static const char pci_device_1013_1204[] = "GD 7541 [Nordic Light]"; +static const char pci_device_1013_4000[] = "MD 5620 [CLM Data Fax Voice]"; +static const char pci_device_1013_4400[] = "CD 4400"; +static const char pci_device_1013_6001[] = "CS 4610/11 [CrystalClear SoundFusion Audio Accelerator]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6001_1014_1010[] = "CS4610 SoundFusion Audio Accelerator"; +#endif +static const char pci_device_1013_6003[] = "CS 4614/22/24/30 [CrystalClear SoundFusion Audio Accelerator]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6003_1013_4280[] = "Crystal SoundFusion PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6003_1014_0153[] = "ThinkPad A20m"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6003_153b_112e[] = "DMX XFire 1024"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6003_153b_1136[] = "SiXPack 5.1+"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6003_1681_0050[] = "Game Theater XP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6003_1681_a011[] = "Fortissimo III 7.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6003_5053_3357[] = "Santa Cruz"; +#endif +static const char pci_device_1013_6004[] = "CS 4614/22/24 [CrystalClear SoundFusion Audio Accelerator]"; +static const char pci_device_1013_6005[] = "Crystal CS4281 PCI Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_1013_4281[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10a8[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10a9[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10aa[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10ab[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10ac[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10ad[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_10cf_10b4[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_1179_0001[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1013_6005_14c0_000c[] = "Crystal CS4281 PCI Audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1014[] = "IBM"; +static const char pci_device_1014_0002[] = "PCI to MCA Bridge"; +static const char pci_device_1014_0005[] = "Alta Lite"; +static const char pci_device_1014_0007[] = "Alta MP"; +static const char pci_device_1014_000a[] = "Fire Coral"; +static const char pci_device_1014_0017[] = "CPU to PCI Bridge"; +static const char pci_device_1014_0018[] = "TR Auto LANstreamer"; +static const char pci_device_1014_001b[] = "GXT-150P"; +static const char pci_device_1014_001c[] = "Carrera"; +static const char pci_device_1014_001d[] = "82G2675"; +static const char pci_device_1014_0020[] = "GXT1000 Graphics Adapter"; +static const char pci_device_1014_0022[] = "IBM27-82351"; +static const char pci_device_1014_002d[] = "Python"; +static const char pci_device_1014_002e[] = "SCSI RAID Adapter [ServeRAID]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_002e_1014_002e[] = "ServeRAID-3x"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_002e_1014_022e[] = "ServeRAID-4H"; +#endif +static const char pci_device_1014_0031[] = "2 Port Serial Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0031_1014_0031[] = "2721 WAN IOA - 2 Port Sync Serial Adapter"; +#endif +static const char pci_device_1014_0036[] = "Miami"; +static const char pci_device_1014_0037[] = "82660 CPU to PCI Bridge"; +static const char pci_device_1014_003a[] = "CPU to PCI Bridge"; +static const char pci_device_1014_003c[] = "GXT250P/GXT255P Graphics Adapter"; +static const char pci_device_1014_003e[] = "16/4 Token ring UTP/STP controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_003e[] = "Token-Ring Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00cd[] = "Token-Ring Adapter + Wake-On-LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00ce[] = "16/4 Token-Ring Adapter 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00cf[] = "16/4 Token-Ring Adapter Special"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00e4[] = "High-Speed 100/16/4 Token-Ring Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_00e5[] = "16/4 Token-Ring Adapter 2 + Wake-On-LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_003e_1014_016d[] = "iSeries 2744 Card"; +#endif +static const char pci_device_1014_0045[] = "SSA Adapter"; +static const char pci_device_1014_0046[] = "MPIC interrupt controller"; +static const char pci_device_1014_0047[] = "PCI to PCI Bridge"; +static const char pci_device_1014_0048[] = "PCI to PCI Bridge"; +static const char pci_device_1014_0049[] = "Warhead SCSI Controller"; +static const char pci_device_1014_004e[] = "ATM Controller (14104e00)"; +static const char pci_device_1014_004f[] = "ATM Controller (14104f00)"; +static const char pci_device_1014_0050[] = "ATM Controller (14105000)"; +static const char pci_device_1014_0053[] = "25 MBit ATM Controller"; +static const char pci_device_1014_0054[] = "GXT500P/GXT550P Graphics Adapter"; +static const char pci_device_1014_0057[] = "MPEG PCI Bridge"; +static const char pci_device_1014_0058[] = "SSA Adapter [Advanced SerialRAID/X]"; +static const char pci_device_1014_005c[] = "i82557B 10/100"; +static const char pci_device_1014_005e[] = "GXT800P Graphics Adapter"; +static const char pci_device_1014_007c[] = "ATM Controller (14107c00)"; +static const char pci_device_1014_007d[] = "3780IDSP [MWave]"; +static const char pci_device_1014_008b[] = "EADS PCI to PCI Bridge"; +static const char pci_device_1014_008e[] = "GXT3000P Graphics Adapter"; +static const char pci_device_1014_0090[] = "GXT 3000P"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0090_1014_008e[] = "GXT-3000P"; +#endif +static const char pci_device_1014_0091[] = "SSA Adapter"; +static const char pci_device_1014_0095[] = "20H2999 PCI Docking Bridge"; +static const char pci_device_1014_0096[] = "Chukar chipset SCSI controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0096_1014_0097[] = "iSeries 2778 DASD IOA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0096_1014_0098[] = "iSeries 2763 DASD IOA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0096_1014_0099[] = "iSeries 2748 DASD IOA"; +#endif +static const char pci_device_1014_009f[] = "PCI 4758 Cryptographic Accelerator"; +static const char pci_device_1014_00a5[] = "ATM Controller (1410a500)"; +static const char pci_device_1014_00a6[] = "ATM 155MBPS MM Controller (1410a600)"; +static const char pci_device_1014_00b7[] = "256-bit Graphics Rasterizer [Fire GL1]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_00b7_1092_00b8[] = "FireGL1 AGP 32Mb"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1014_00b8[] = "GXT2000P Graphics Adapter"; +static const char pci_device_1014_00be[] = "ATM 622MBPS Controller (1410be00)"; +static const char pci_device_1014_00dc[] = "Advanced Systems Management Adapter (ASMA)"; +static const char pci_device_1014_00fc[] = "CPC710 Dual Bridge and Memory Controller (PCI-64)"; +static const char pci_device_1014_0104[] = "Gigabit Ethernet-SX Adapter"; +static const char pci_device_1014_0105[] = "CPC710 Dual Bridge and Memory Controller (PCI-32)"; +static const char pci_device_1014_010f[] = "Remote Supervisor Adapter (RSA)"; +static const char pci_device_1014_0142[] = "Yotta Video Compositor Input"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0142_1014_0143[] = "Yotta Input Controller (ytin)"; +#endif +static const char pci_device_1014_0144[] = "Yotta Video Compositor Output"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0144_1014_0145[] = "Yotta Output Controller (ytout)"; +#endif +static const char pci_device_1014_0156[] = "405GP PLB to PCI Bridge"; +static const char pci_device_1014_015e[] = "622Mbps ATM PCI Adapter"; +static const char pci_device_1014_0160[] = "64bit/66MHz PCI ATM 155 MMF"; +static const char pci_device_1014_016e[] = "GXT4000P Graphics Adapter"; +static const char pci_device_1014_0170[] = "GXT6000P Graphics Adapter"; +static const char pci_device_1014_017d[] = "GXT300P Graphics Adapter"; +static const char pci_device_1014_0180[] = "Snipe chipset SCSI controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0180_1014_0241[] = "iSeries 2757 DASD IOA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0180_1014_0264[] = "Quad Channel PCI-X U320 SCSI RAID Adapter (2780)"; +#endif +static const char pci_device_1014_0188[] = "EADS-X PCI-X to PCI-X Bridge"; +static const char pci_device_1014_01a7[] = "PCI-X to PCI-X Bridge"; +static const char pci_device_1014_01bd[] = "ServeRAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_01be[] = "ServeRAID-4M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_01bf[] = "ServeRAID-4L"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_0208[] = "ServeRAID-4Mx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_020e[] = "ServeRAID-4Lx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_022e[] = "ServeRAID-4H"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_0258[] = "ServeRAID-5i"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_01bd_1014_0259[] = "ServeRAID-5i"; +#endif +static const char pci_device_1014_01c1[] = "64bit/66MHz PCI ATM 155 UTP"; +static const char pci_device_1014_01e6[] = "Cryptographic Accelerator"; +static const char pci_device_1014_01ff[] = "10/100 Mbps Ethernet"; +static const char pci_device_1014_0219[] = "Multiport Serial Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0219_1014_021a[] = "Dual RVX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0219_1014_0251[] = "Internal Modem/RVX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_0219_1014_0252[] = "Quad Internal Modem"; +#endif +static const char pci_device_1014_021b[] = "GXT6500P Graphics Adapter"; +static const char pci_device_1014_021c[] = "GXT4500P Graphics Adapter"; +static const char pci_device_1014_0233[] = "GXT135P Graphics Adapter"; +static const char pci_device_1014_0266[] = "PCI-X Dual Channel SCSI"; +static const char pci_device_1014_0268[] = "Gigabit Ethernet-SX Adapter (PCI-X)"; +static const char pci_device_1014_0269[] = "10/100/1000 Base-TX Ethernet Adapter (PCI-X)"; +static const char pci_device_1014_028c[] = "Citrine chipset SCSI controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_028c_1014_028d[] = "Dual Channel PCI-X DDR SAS RAID Adapter (572E)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_028c_1014_02be[] = "Dual Channel PCI-X DDR U320 SCSI RAID Adapter (571B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_028c_1014_02c0[] = "Dual Channel PCI-X DDR U320 SCSI Adapter (571A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_028c_1014_030d[] = "PCI-X DDR Auxiliary Cache Adapter (575B)"; +#endif +static const char pci_device_1014_02a1[] = "Calgary PCI-X Host Bridge"; +static const char pci_device_1014_02bd[] = "Obsidian chipset SCSI controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_02bd_1014_02c1[] = "PCI-X DDR 3Gb SAS Adapter (572A/572C)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1014_02bd_1014_02c2[] = "PCI-X DDR 3Gb SAS RAID Adapter (572B/571D)"; +#endif +static const char pci_device_1014_0302[] = "Winnipeg PCI-X Host Bridge"; +static const char pci_device_1014_0308[] = "CalIOC2 PCI-E Root Port"; +static const char pci_device_1014_0314[] = "ZISC 036 Neural accelerator card"; +static const char pci_device_1014_3022[] = "QLA3022 Network Adapter"; +static const char pci_device_1014_4022[] = "QLA3022 Network Adapter"; +static const char pci_device_1014_ffff[] = "MPIC-2 interrupt controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1015[] = "LSI Logic Corp of Canada"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1016[] = "ICL Personal Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1017[] = "SPEA Software AG"; +static const char pci_device_1017_5343[] = "SPEA 3D Accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1018[] = "Unisys Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1019[] = "Elitegroup Computer Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101a[] = "AT&T GIS (NCR)"; +static const char pci_device_101a_0005[] = "100VG ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101b[] = "Vitesse Semiconductor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101c[] = "Western Digital"; +static const char pci_device_101c_0193[] = "33C193A"; +static const char pci_device_101c_0196[] = "33C196A"; +static const char pci_device_101c_0197[] = "33C197A"; +static const char pci_device_101c_0296[] = "33C296A"; +static const char pci_device_101c_3193[] = "7193"; +static const char pci_device_101c_3197[] = "7197"; +static const char pci_device_101c_3296[] = "33C296A"; +static const char pci_device_101c_4296[] = "34C296"; +static const char pci_device_101c_9710[] = "Pipeline 9710"; +static const char pci_device_101c_9712[] = "Pipeline 9712"; +static const char pci_device_101c_c24a[] = "90C"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101e[] = "American Megatrends Inc."; +static const char pci_device_101e_0009[] = "MegaRAID 428 Ultra RAID Controller (rev 03)"; +static const char pci_device_101e_1960[] = "MegaRAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0471[] = "MegaRAID 471 Enterprise 1600 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0475[] = "MegaRAID 475 Express 500/500LC RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0477[] = "MegaRAID 477 Elite 3100 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0493[] = "MegaRAID 493 Elite 1600 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0494[] = "MegaRAID 494 Elite 1650 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0503[] = "MegaRAID 503 Enterprise 1650 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0511[] = "MegaRAID 511 i4 IDE RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_101e_0522[] = "MegaRAID 522 i4133 RAID Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_1028_0471[] = "PowerEdge RAID Controller 3/QC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_1028_0475[] = "PowerEdge RAID Controller 3/SC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_1028_0493[] = "PowerEdge RAID Controller 3/DC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_1028_0511[] = "PowerEdge Cost Effective RAID Controller ATA100/4Ch"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_1960_103c_60e7[] = "NetRAID-1M"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_101e_9010[] = "MegaRAID 428 Ultra RAID Controller"; +static const char pci_device_101e_9030[] = "EIDE Controller"; +static const char pci_device_101e_9031[] = "EIDE Controller"; +static const char pci_device_101e_9032[] = "EIDE & SCSI Controller"; +static const char pci_device_101e_9033[] = "SCSI Controller"; +static const char pci_device_101e_9040[] = "Multimedia card"; +static const char pci_device_101e_9060[] = "MegaRAID 434 Ultra GT RAID Controller"; +static const char pci_device_101e_9063[] = "MegaRAC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_101e_9063_101e_0767[] = "Dell Remote Assistant Card 2"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_101f[] = "PictureTel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1020[] = "Hitachi Computer Products"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1021[] = "OKI Electric Industry Co. Ltd."; +#endif +static const char pci_vendor_1022[] = "Advanced Micro Devices [AMD]"; +static const char pci_device_1022_1100[] = "K8 [Athlon64/Opteron] HyperTransport Technology Configuration"; +static const char pci_device_1022_1101[] = "K8 [Athlon64/Opteron] Address Map"; +static const char pci_device_1022_1102[] = "K8 [Athlon64/Opteron] DRAM Controller"; +static const char pci_device_1022_1103[] = "K8 [Athlon64/Opteron] Miscellaneous Control"; +static const char pci_device_1022_2000[] = "79c970 [PCnet32 LANCE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1014_2000[] = "NetFinity 10/100 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1022_2000[] = "PCnet - Fast 79C971"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_104c[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_1064[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_1065[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_106c[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_106e[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_103c_10ea[] = "Ethernet with LAN remote power Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1113_1220[] = "EN1220 10/100 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2450[] = "AT-2450 10/100 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2454[] = "AT-2450v4 10Mb Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2700[] = "AT-2700TX 10/100 Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2701[] = "AT-2700FX 100Mb Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2702[] = "AT-2700FTX 10/100 Mb Fiber/Copper Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2703[] = "AT-2701FX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_1259_2704[] = "AT-2701FTX 10/100 Mb Fiber/Copper Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1010[] = "CP5/CR6 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1020[] = "VR6 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1030[] = "PC5 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1040[] = "CL7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2000_4c53_1060[] = "PC7 mainboard"; +#endif +static const char pci_device_1022_2001[] = "79c978 [HomePNA]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2001_1092_0a78[] = "Multimedia Home Network Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_2001_1668_0299[] = "ActionLink Home Network Adapter"; +#endif +static const char pci_device_1022_2003[] = "Am 1771 MBW [Alchemy]"; +static const char pci_device_1022_2020[] = "53c974 [PCscsi]"; +static const char pci_device_1022_2040[] = "79c974"; +static const char pci_device_1022_2081[] = "Geode LX Video"; +static const char pci_device_1022_2082[] = "Geode LX AES Security Block"; +static const char pci_device_1022_208f[] = "CS5536 GeodeLink PCI South Bridge"; +static const char pci_device_1022_2090[] = "CS5536 [Geode companion] ISA"; +static const char pci_device_1022_2091[] = "CS5536 [Geode companion] FLASH"; +static const char pci_device_1022_2093[] = "CS5536 [Geode companion] Audio"; +static const char pci_device_1022_2094[] = "CS5536 [Geode companion] OHC"; +static const char pci_device_1022_2095[] = "CS5536 [Geode companion] EHC"; +static const char pci_device_1022_2096[] = "CS5536 [Geode companion] UDC"; +static const char pci_device_1022_2097[] = "CS5536 [Geode companion] UOC"; +static const char pci_device_1022_209a[] = "CS5536 [Geode companion] IDE"; +static const char pci_device_1022_3000[] = "ELanSC520 Microcontroller"; +static const char pci_device_1022_7006[] = "AMD-751 [Irongate] System Controller"; +static const char pci_device_1022_7007[] = "AMD-751 [Irongate] AGP Bridge"; +static const char pci_device_1022_700a[] = "AMD-IGR4 AGP Host to PCI Bridge"; +static const char pci_device_1022_700b[] = "AMD-IGR4 PCI to PCI Bridge"; +static const char pci_device_1022_700c[] = "AMD-760 MP [IGD4-2P] System Controller"; +static const char pci_device_1022_700d[] = "AMD-760 MP [IGD4-2P] AGP Bridge"; +static const char pci_device_1022_700e[] = "AMD-760 [IGD4-1P] System Controller"; +static const char pci_device_1022_700f[] = "AMD-760 [IGD4-1P] AGP Bridge"; +static const char pci_device_1022_7400[] = "AMD-755 [Cobra] ISA"; +static const char pci_device_1022_7401[] = "AMD-755 [Cobra] IDE"; +static const char pci_device_1022_7403[] = "AMD-755 [Cobra] ACPI"; +static const char pci_device_1022_7404[] = "AMD-755 [Cobra] USB"; +static const char pci_device_1022_7408[] = "AMD-756 [Viper] ISA"; +static const char pci_device_1022_7409[] = "AMD-756 [Viper] IDE"; +static const char pci_device_1022_740b[] = "AMD-756 [Viper] ACPI"; +static const char pci_device_1022_740c[] = "AMD-756 [Viper] USB"; +static const char pci_device_1022_7410[] = "AMD-766 [ViperPlus] ISA"; +static const char pci_device_1022_7411[] = "AMD-766 [ViperPlus] IDE"; +static const char pci_device_1022_7413[] = "AMD-766 [ViperPlus] ACPI"; +static const char pci_device_1022_7414[] = "AMD-766 [ViperPlus] USB"; +static const char pci_device_1022_7440[] = "AMD-768 [Opus] ISA"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7440_1043_8044[] = "A7M-D Mainboard"; +#endif +static const char pci_device_1022_7441[] = "AMD-768 [Opus] IDE"; +static const char pci_device_1022_7443[] = "AMD-768 [Opus] ACPI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7443_1043_8044[] = "A7M-D Mainboard"; +#endif +static const char pci_device_1022_7445[] = "AMD-768 [Opus] Audio"; +static const char pci_device_1022_7446[] = "AMD-768 [Opus] MC97 Modem (Smart Link HAMR5600 compatible)"; +static const char pci_device_1022_7448[] = "AMD-768 [Opus] PCI"; +static const char pci_device_1022_7449[] = "AMD-768 [Opus] USB"; +static const char pci_device_1022_7450[] = "AMD-8131 PCI-X Bridge"; +static const char pci_device_1022_7451[] = "AMD-8131 PCI-X IOAPIC"; +static const char pci_device_1022_7454[] = "AMD-8151 System Controller"; +static const char pci_device_1022_7455[] = "AMD-8151 AGP Bridge"; +static const char pci_device_1022_7458[] = "AMD-8132 PCI-X Bridge"; +static const char pci_device_1022_7459[] = "AMD-8132 PCI-X IOAPIC"; +static const char pci_device_1022_7460[] = "AMD-8111 PCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7460_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_7461[] = "AMD-8111 USB"; +static const char pci_device_1022_7462[] = "AMD-8111 Ethernet"; +static const char pci_device_1022_7464[] = "AMD-8111 USB"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7464_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_7468[] = "AMD-8111 LPC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7468_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_7469[] = "AMD-8111 IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7469_1022_2b80[] = "AMD-8111 IDE [Quartet]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_7469_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_746a[] = "AMD-8111 SMBus 2.0"; +static const char pci_device_1022_746b[] = "AMD-8111 ACPI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_746b_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_746d[] = "AMD-8111 AC97 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1022_746d_161f_3017[] = "HDAMB"; +#endif +static const char pci_device_1022_746e[] = "AMD-8111 MC97 Modem"; +static const char pci_device_1022_756b[] = "AMD-8111 ACPI"; +static const char pci_vendor_1023[] = "Trident Microsystems"; +static const char pci_device_1023_0194[] = "82C194"; +static const char pci_device_1023_2000[] = "4DWave DX"; +static const char pci_device_1023_2001[] = "4DWave NX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_2001_122d_1400[] = "Trident PCI288-Q3DII (NX)"; +#endif +static const char pci_device_1023_2100[] = "CyberBlade XP4m32"; +static const char pci_device_1023_2200[] = "XGI Volari XP5"; +static const char pci_device_1023_8400[] = "CyberBlade/i7"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8400_1023_8400[] = "CyberBlade i7 AGP"; +#endif +static const char pci_device_1023_8420[] = "CyberBlade/i7d"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8420_0e11_b15a[] = "CyberBlade i7 AGP"; +#endif +static const char pci_device_1023_8500[] = "CyberBlade/i1"; +static const char pci_device_1023_8520[] = "CyberBlade i1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8520_0e11_b16e[] = "CyberBlade i1 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8520_1023_8520[] = "CyberBlade i1 AGP"; +#endif +static const char pci_device_1023_8620[] = "CyberBlade/i1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8620_1014_0502[] = "ThinkPad R30/T30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_8620_1014_1025[] = "Travelmate 352TE"; +#endif +static const char pci_device_1023_8820[] = "CyberBlade XPAi1"; +static const char pci_device_1023_9320[] = "TGUI 9320"; +static const char pci_device_1023_9350[] = "GUI Accelerator"; +static const char pci_device_1023_9360[] = "Flat panel GUI Accelerator"; +static const char pci_device_1023_9382[] = "Cyber 9382 [Reference design]"; +static const char pci_device_1023_9383[] = "Cyber 9383 [Reference design]"; +static const char pci_device_1023_9385[] = "Cyber 9385 [Reference design]"; +static const char pci_device_1023_9386[] = "Cyber 9386"; +static const char pci_device_1023_9388[] = "Cyber 9388"; +static const char pci_device_1023_9397[] = "Cyber 9397"; +static const char pci_device_1023_939a[] = "Cyber 9397DVD"; +static const char pci_device_1023_9420[] = "TGUI 9420"; +static const char pci_device_1023_9430[] = "TGUI 9430"; +static const char pci_device_1023_9440[] = "TGUI 9440"; +static const char pci_device_1023_9460[] = "TGUI 9460"; +static const char pci_device_1023_9470[] = "TGUI 9470"; +static const char pci_device_1023_9520[] = "Cyber 9520"; +static const char pci_device_1023_9525[] = "Cyber 9525"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_9525_10cf_1094[] = "Lifebook C6155"; +#endif +static const char pci_device_1023_9540[] = "Cyber 9540"; +static const char pci_device_1023_9660[] = "TGUI 9660/938x/968x"; +static const char pci_device_1023_9680[] = "TGUI 9680"; +static const char pci_device_1023_9682[] = "TGUI 9682"; +static const char pci_device_1023_9683[] = "TGUI 9683"; +static const char pci_device_1023_9685[] = "ProVIDIA 9685"; +static const char pci_device_1023_9750[] = "3DImage 9750"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_9750_1014_9750[] = "3DImage 9750"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_9750_1023_9750[] = "3DImage 9750"; +#endif +static const char pci_device_1023_9753[] = "TGUI 9753"; +static const char pci_device_1023_9754[] = "TGUI 9754"; +static const char pci_device_1023_9759[] = "TGUI 975"; +static const char pci_device_1023_9783[] = "TGUI 9783"; +static const char pci_device_1023_9785[] = "TGUI 9785"; +static const char pci_device_1023_9850[] = "3DImage 9850"; +static const char pci_device_1023_9880[] = "Blade 3D PCI/AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1023_9880_1023_9880[] = "Blade 3D"; +#endif +static const char pci_device_1023_9910[] = "CyberBlade/XP"; +static const char pci_device_1023_9930[] = "CyberBlade/XPm"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1024[] = "Zenith Data Systems"; +#endif +static const char pci_vendor_1025[] = "Acer Incorporated [ALI]"; +static const char pci_device_1025_0090[] = "BCM440x 100Base-TX Fast Ethernet"; +static const char pci_device_1025_1435[] = "M1435"; +static const char pci_device_1025_1445[] = "M1445"; +static const char pci_device_1025_1449[] = "M1449"; +static const char pci_device_1025_1451[] = "M1451"; +static const char pci_device_1025_1461[] = "M1461"; +static const char pci_device_1025_1489[] = "M1489"; +static const char pci_device_1025_1511[] = "M1511"; +static const char pci_device_1025_1512[] = "ALI M1512 Aladdin"; +static const char pci_device_1025_1513[] = "M1513"; +static const char pci_device_1025_1521[] = "ALI M1521 Aladdin III CPU Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_1521_10b9_1521[] = "ALI M1521 Aladdin III CPU Bridge"; +#endif +static const char pci_device_1025_1523[] = "ALI M1523 ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_1523_10b9_1523[] = "ALI M1523 ISA Bridge"; +#endif +static const char pci_device_1025_1531[] = "M1531 Northbridge [Aladdin IV/IV+]"; +static const char pci_device_1025_1533[] = "M1533 PCI-to-ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_1533_10b9_1533[] = "ALI M1533 Aladdin IV/V ISA South Bridge"; +#endif +static const char pci_device_1025_1535[] = "M1535 PCI Bridge + Super I/O + FIR"; +static const char pci_device_1025_1541[] = "M1541 Northbridge [Aladdin V]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_1541_10b9_1541[] = "ALI M1541 Aladdin V/V+ AGP+PCI North Bridge"; +#endif +static const char pci_device_1025_1542[] = "M1542 Northbridge [Aladdin V]"; +static const char pci_device_1025_1543[] = "M1543 PCI-to-ISA Bridge + Super I/O + FIR"; +static const char pci_device_1025_1561[] = "M1561 Northbridge [Aladdin 7]"; +static const char pci_device_1025_1621[] = "M1621 Northbridge [Aladdin-Pro II]"; +static const char pci_device_1025_1631[] = "M1631 Northbridge+3D Graphics [Aladdin TNT2]"; +static const char pci_device_1025_1641[] = "M1641 Northbridge [Aladdin-Pro IV]"; +static const char pci_device_1025_1647[] = "M1647 [MaGiK1] PCI North Bridge"; +static const char pci_device_1025_1671[] = "M1671 Northbridge [ALADDiN-P4]"; +static const char pci_device_1025_1672[] = "Northbridge [CyberALADDiN-P4]"; +static const char pci_device_1025_3141[] = "M3141"; +static const char pci_device_1025_3143[] = "M3143"; +static const char pci_device_1025_3145[] = "M3145"; +static const char pci_device_1025_3147[] = "M3147"; +static const char pci_device_1025_3149[] = "M3149"; +static const char pci_device_1025_3151[] = "M3151"; +static const char pci_device_1025_3307[] = "M3307 MPEG-I Video Controller"; +static const char pci_device_1025_3309[] = "M3309 MPEG-II Video w/ Software Audio Decoder"; +static const char pci_device_1025_3321[] = "M3321 MPEG-II Audio/Video Decoder"; +static const char pci_device_1025_5212[] = "M4803"; +static const char pci_device_1025_5215[] = "ALI PCI EIDE Controller"; +static const char pci_device_1025_5217[] = "M5217H"; +static const char pci_device_1025_5219[] = "M5219"; +static const char pci_device_1025_5225[] = "M5225"; +static const char pci_device_1025_5229[] = "M5229"; +static const char pci_device_1025_5235[] = "M5235"; +static const char pci_device_1025_5237[] = "M5237 PCI USB Host Controller"; +static const char pci_device_1025_5240[] = "EIDE Controller"; +static const char pci_device_1025_5241[] = "PCMCIA Bridge"; +static const char pci_device_1025_5242[] = "General Purpose Controller"; +static const char pci_device_1025_5243[] = "PCI to PCI Bridge Controller"; +static const char pci_device_1025_5244[] = "Floppy Disk Controller"; +static const char pci_device_1025_5247[] = "M1541 PCI to PCI Bridge"; +static const char pci_device_1025_5251[] = "M5251 P1394 Controller"; +static const char pci_device_1025_5427[] = "PCI to AGP Bridge"; +static const char pci_device_1025_5451[] = "M5451 PCI AC-Link Controller Audio Device"; +static const char pci_device_1025_5453[] = "M5453 PCI AC-Link Controller Modem Device"; +static const char pci_device_1025_7101[] = "M7101 PCI PMU Power Management Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1025_7101_10b9_7101[] = "M7101 PCI PMU Power Management Controller"; +#endif +static const char pci_vendor_1028[] = "Dell"; +static const char pci_device_1028_0001[] = "PowerEdge Expandable RAID Controller 2/Si"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0001_1028_0001[] = "PowerEdge 2400"; +#endif +static const char pci_device_1028_0002[] = "PowerEdge Expandable RAID Controller 3/Di"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0002_1028_0002[] = "PowerEdge 4400"; +#endif +static const char pci_device_1028_0003[] = "PowerEdge Expandable RAID Controller 3/Si"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0003_1028_0003[] = "PowerEdge 2450"; +#endif +static const char pci_device_1028_0006[] = "PowerEdge Expandable RAID Controller 3/Di"; +static const char pci_device_1028_0007[] = "Remote Access Card III"; +static const char pci_device_1028_0008[] = "Remote Access Card III"; +static const char pci_device_1028_0009[] = "Remote Access Card III: BMC/SMIC device not present"; +static const char pci_device_1028_000a[] = "PowerEdge Expandable RAID Controller 3/Di"; +static const char pci_device_1028_000c[] = "Embedded Remote Access or ERA/O"; +static const char pci_device_1028_000d[] = "Embedded Remote Access: BMC/SMIC device"; +static const char pci_device_1028_000e[] = "PowerEdge Expandable RAID controller 4/Di"; +static const char pci_device_1028_000f[] = "PowerEdge Expandable RAID controller 4/Di"; +static const char pci_device_1028_0010[] = "Remote Access Card 4"; +static const char pci_device_1028_0011[] = "Remote Access Card 4 Daughter Card"; +static const char pci_device_1028_0012[] = "Remote Access Card 4 Daughter Card Virtual UART"; +static const char pci_device_1028_0013[] = "PowerEdge Expandable RAID controller 4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0013_1028_016c[] = "PowerEdge Expandable RAID Controller 4e/Si"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0013_1028_016d[] = "PowerEdge Expandable RAID Controller 4e/Di"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0013_1028_016e[] = "PowerEdge Expandable RAID Controller 4e/Di"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0013_1028_016f[] = "PowerEdge Expandable RAID Controller 4e/Di"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1028_0013_1028_0170[] = "PowerEdge Expandable RAID Controller 4e/Di"; +#endif +static const char pci_device_1028_0014[] = "Remote Access Card 4 Daughter Card SMIC interface"; +static const char pci_device_1028_0015[] = "PowerEdge Expandable RAID controller 5i"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1029[] = "Siemens Nixdorf IS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_102a[] = "LSI Logic"; +static const char pci_device_102a_0000[] = "HYDRA"; +static const char pci_device_102a_0010[] = "ASPEN"; +static const char pci_device_102a_001f[] = "AHA-2940U2/U2W /7890/7891 SCSI Controllers"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_001f_9005_000f[] = "2940U2W SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_001f_9005_0106[] = "2940U2W SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_001f_9005_a180[] = "2940U2W SCSI Controller"; +#endif +static const char pci_device_102a_00c5[] = "AIC-7899 U160/m SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_00c5_1028_00c5[] = "PowerEdge 2550/2650/4600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_102a_00cf[] = "AIC-7899P U160/m"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_00cf_1028_0106[] = "PowerEdge 4600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102a_00cf_1028_0121[] = "PowerEdge 2650"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const char pci_vendor_102b[] = "Matrox Graphics, Inc."; +static const char pci_device_102b_0010[] = "MGA-I [Impression?]"; +static const char pci_device_102b_0100[] = "MGA 1064SG [Mystique]"; +static const char pci_device_102b_0518[] = "MGA-II [Athena]"; +static const char pci_device_102b_0519[] = "MGA 2064W [Millennium]"; +static const char pci_device_102b_051a[] = "MGA 1064SG [Mystique]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_102b_0100[] = "MGA-1064SG Mystique"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_102b_1100[] = "MGA-1084SG Mystique"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_102b_1200[] = "MGA-1084SG Mystique"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_1100_102b[] = "MGA-1084SG Mystique"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051a_110a_0018[] = "Scenic Pro C5 (D1025)"; +#endif +static const char pci_device_102b_051b[] = "MGA 2164W [Millennium II]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051b_102b_051b[] = "MGA-2164W Millennium II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051b_102b_1100[] = "MGA-2164W Millennium II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_051b_102b_1200[] = "MGA-2164W Millennium II"; +#endif +static const char pci_device_102b_051e[] = "MGA 1064SG [Mystique] AGP"; +static const char pci_device_102b_051f[] = "MGA 2164W [Millennium II] AGP"; +static const char pci_device_102b_0520[] = "MGA G200"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_dbc2[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_dbc8[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_dbe2[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_dbe8[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_ff03[] = "Millennium G200 SD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0520_102b_ff04[] = "Marvel G200"; +#endif +static const char pci_device_102b_0521[] = "MGA G200 AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_1014_ff03[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_48e9[] = "Mystique G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_48f8[] = "Millennium G200 SD AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_4a60[] = "Millennium G200 LE AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_4a64[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_c93c[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_c9b0[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_c9bc[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ca60[] = "Millennium G250 LE AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ca6c[] = "Millennium G250 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbbc[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbc2[] = "Millennium G200 MMS (Dual G200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbc3[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbc8[] = "Millennium G200 MMS (Dual G200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd2[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd3[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd4[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd5[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd8[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbd9[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbe2[] = "Millennium G200 MMS (Quad G200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbe3[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbe8[] = "Millennium G200 MMS (Quad G200)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf2[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf3[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf4[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf5[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf8[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_dbf9[] = "G200 Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_f806[] = "Mystique G200 Video AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ff00[] = "MGA-G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ff02[] = "Mystique G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ff03[] = "Millennium G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_102b_ff04[] = "Marvel G200 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0521_110a_0032[] = "MGA-G200 AGP"; +#endif +static const char pci_device_102b_0522[] = "MGA G200e [Pilot] ServerEngines (SEP1)"; +static const char pci_device_102b_0525[] = "MGA G400/G450"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_0e11_b16f[] = "MGA-G400 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0328[] = "Millennium G400 16Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0338[] = "Millennium G400 16Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0378[] = "Millennium G400 32Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0541[] = "Millennium G450 Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0542[] = "Millennium G450 Dual Head LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0543[] = "Millennium G450 Single Head LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0641[] = "Millennium G450 32Mb SDRAM Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0642[] = "Millennium G450 32Mb SDRAM Dual Head LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0643[] = "Millennium G450 32Mb SDRAM Single Head LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_07c0[] = "Millennium G450 Dual Head LE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_07c1[] = "Millennium G450 SDR Dual Head LE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0d41[] = "Millennium G450 Dual Head PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0d42[] = "Millennium G450 Dual Head LX PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0d43[] = "Millennium G450 32Mb Dual Head PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0e00[] = "Marvel G450 eTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0e01[] = "Marvel G450 eTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0e02[] = "Marvel G450 eTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0e03[] = "Marvel G450 eTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0f80[] = "Millennium G450 Low Profile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0f81[] = "Millennium G450 Low Profile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0f82[] = "Millennium G450 Low Profile DVI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_0f83[] = "Millennium G450 Low Profile DVI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_19d8[] = "Millennium G400 16Mb SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_19f8[] = "Millennium G400 32Mb SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_2159[] = "Millennium G400 Dual Head 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_2179[] = "Millennium G400 MAX/Dual Head 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_217d[] = "Millennium G400 Dual Head Max"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_23c0[] = "Millennium G450"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_23c1[] = "Millennium G450"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_23c2[] = "Millennium G450 DVI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_23c3[] = "Millennium G450 DVI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_2f58[] = "Millennium G400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_2f78[] = "Millennium G400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_3693[] = "Marvel G400 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_5dd0[] = "4Sight II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_5f50[] = "4Sight II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_5f51[] = "4Sight II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_5f52[] = "4Sight II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_102b_9010[] = "Millennium G400 Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1458_0400[] = "GA-G400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1705_0001[] = "Millennium G450 32MB SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1705_0002[] = "Millennium G450 16MB SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1705_0003[] = "Millennium G450 32MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0525_1705_0004[] = "Millennium G450 16MB"; +#endif +static const char pci_device_102b_0527[] = "MGA Parhelia AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0527_102b_0840[] = "Parhelia 128Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0527_102b_0850[] = "Parhelia 256MB AGP 4X"; +#endif +static const char pci_device_102b_0528[] = "Parhelia 8X"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0528_102b_1020[] = "Parhelia 128MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0528_102b_1030[] = "Parhelia 256 MB Dual DVI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0528_102b_14e1[] = "Parhelia PCI 256MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_0528_102b_2021[] = "QID Pro"; +#endif +static const char pci_device_102b_0d10[] = "MGA Ultima/Impression"; +static const char pci_device_102b_1000[] = "MGA G100 [Productiva]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1000_102b_ff01[] = "Productiva G100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1000_102b_ff05[] = "Productiva G100 Multi-Monitor"; +#endif +static const char pci_device_102b_1001[] = "MGA G100 [Productiva] AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_1001[] = "MGA-G100 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff00[] = "MGA-G100 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff01[] = "MGA-G100 Productiva AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff03[] = "Millennium G100 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff04[] = "MGA-G100 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_102b_ff05[] = "MGA-G100 Productiva AGP Multi-Monitor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_1001_110a_001e[] = "MGA-G100 AGP"; +#endif +static const char pci_device_102b_2007[] = "MGA Mistral"; +static const char pci_device_102b_2527[] = "MGA G550 AGP"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2527_102b_0f83[] = "Millennium G550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2527_102b_0f84[] = "Millennium G550 Dual Head DDR 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2527_102b_1e41[] = "Millennium G550"; +#endif +static const char pci_device_102b_2537[] = "Millenium P650/P750"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2537_102b_1820[] = "Millennium P750 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2537_102b_1830[] = "Millennium P650 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2537_102b_1c10[] = "QID 128MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2537_102b_2811[] = "Millennium P650 Low-profile PCI 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2537_102b_2c11[] = "QID Low-profile PCI"; +#endif +static const char pci_device_102b_2538[] = "Millenium P650 PCIe"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_08c7[] = "Millennium P650 PCIe 128MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_0907[] = "Millennium P650 PCIe 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_1047[] = "Millennium P650 LP PCIe 128MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_1087[] = "Millennium P650 LP PCIe 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_2538[] = "Parhelia APVe"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102b_2538_102b_3007[] = "QID Low-profile PCIe"; +#endif +static const char pci_device_102b_4536[] = "VIA Framegrabber"; +static const char pci_device_102b_4cdc[] = "Morphis Vision System Jpeg2000"; +static const char pci_device_102b_4fc5[] = "Morphis Vision System"; +static const char pci_device_102b_5e10[] = "Morphis Vision System Aux/IO"; +static const char pci_device_102b_6573[] = "Shark 10/100 Multiport SwitchNIC"; +static const char pci_vendor_102c[] = "Chips and Technologies"; +static const char pci_device_102c_00b8[] = "F64310"; +static const char pci_device_102c_00c0[] = "F69000 HiQVideo"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_102c_00c0[] = "F69000 HiQVideo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1010[] = "CP5/CR6 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1020[] = "VR6 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1030[] = "PC5 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00c0_4c53_1051[] = "CE7 mainboard"; +#endif +static const char pci_device_102c_00d0[] = "F65545"; +static const char pci_device_102c_00d8[] = "F65545"; +static const char pci_device_102c_00dc[] = "F65548"; +static const char pci_device_102c_00e0[] = "F65550"; +static const char pci_device_102c_00e4[] = "F65554"; +static const char pci_device_102c_00e5[] = "F65555 HiQVPro"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00e5_0e11_b049[] = "Armada 1700 Laptop Display Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_00e5_1179_0001[] = "Satellite Pro"; +#endif +static const char pci_device_102c_00f0[] = "F68554"; +static const char pci_device_102c_00f4[] = "F68554 HiQVision"; +static const char pci_device_102c_00f5[] = "F68555"; +static const char pci_device_102c_0c30[] = "F69030"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_0c30_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_0c30_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_0c30_4c53_1051[] = "CE7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102c_0c30_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_102d[] = "Wyse Technology Inc."; +static const char pci_device_102d_50dc[] = "3328 Audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_102e[] = "Olivetti Advanced Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_102f[] = "Toshiba America"; +static const char pci_device_102f_0009[] = "r4x00"; +static const char pci_device_102f_000a[] = "TX3927 MIPS RISC PCI Controller"; +static const char pci_device_102f_0020[] = "ATM Meteor 155"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_102f_0020_102f_00f8[] = "ATM Meteor 155"; +#endif +static const char pci_device_102f_0030[] = "TC35815CF PCI 10/100 Mbit Ethernet Controller"; +static const char pci_device_102f_0031[] = "TC35815CF PCI 10/100 Mbit Ethernet Controller with WOL"; +static const char pci_device_102f_0105[] = "TC86C001 [goku-s] IDE"; +static const char pci_device_102f_0106[] = "TC86C001 [goku-s] USB 1.1 Host"; +static const char pci_device_102f_0107[] = "TC86C001 [goku-s] USB Device Controller"; +static const char pci_device_102f_0108[] = "TC86C001 [goku-s] I2C/SIO/GPIO Controller"; +static const char pci_device_102f_0180[] = "TX4927/38 MIPS RISC PCI Controller"; +static const char pci_device_102f_0181[] = "TX4925 MIPS RISC PCI Controller"; +static const char pci_device_102f_0182[] = "TX4937 MIPS RISC PCI Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1030[] = "TMC Research"; +#endif +static const char pci_vendor_1031[] = "Miro Computer Products AG"; +static const char pci_device_1031_5601[] = "DC20 ASIC"; +static const char pci_device_1031_5607[] = "Video I/O & motion JPEG compressor"; +static const char pci_device_1031_5631[] = "Media 3D"; +static const char pci_device_1031_6057[] = "MiroVideo DC10/DC30+"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1032[] = "Compaq"; +#endif +static const char pci_vendor_1033[] = "NEC Corporation"; +static const char pci_device_1033_0000[] = "Vr4181A USB Host or Function Control Unit"; +static const char pci_device_1033_0001[] = "PCI to 486-like bus Bridge"; +static const char pci_device_1033_0002[] = "PCI to VL98 Bridge"; +static const char pci_device_1033_0003[] = "ATM Controller"; +static const char pci_device_1033_0004[] = "R4000 PCI Bridge"; +static const char pci_device_1033_0005[] = "PCI to 486-like bus Bridge"; +static const char pci_device_1033_0006[] = "PC-9800 Graphic Accelerator"; +static const char pci_device_1033_0007[] = "PCI to UX-Bus Bridge"; +static const char pci_device_1033_0008[] = "PC-9800 Graphic Accelerator"; +static const char pci_device_1033_0009[] = "PCI to PC9800 Core-Graph Bridge"; +static const char pci_device_1033_0016[] = "PCI to VL Bridge"; +static const char pci_device_1033_001a[] = "[Nile II]"; +static const char pci_device_1033_0021[] = "Vrc4373 [Nile I]"; +static const char pci_device_1033_0029[] = "PowerVR PCX1"; +static const char pci_device_1033_002a[] = "PowerVR 3D"; +static const char pci_device_1033_002c[] = "Star Alpha 2"; +static const char pci_device_1033_002d[] = "PCI to C-bus Bridge"; +static const char pci_device_1033_0035[] = "USB"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_1033_0035[] = "Hama USB 2.0 CardBus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_1179_0001[] = "USB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_12ee_7000[] = "Root Hub"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_14c2_0105[] = "PTI-205N USB 2.0 Host Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_1799_0001[] = "Root Hub"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_1931_000a[] = "GlobeTrotter Fusion Quad Lite (PPP data)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_1931_000b[] = "GlobeTrotter Fusion Quad Lite (GSM data)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0035_807d_0035[] = "PCI-USB2 (OHCI subsystem)"; +#endif +static const char pci_device_1033_003b[] = "PCI to C-bus Bridge"; +static const char pci_device_1033_003e[] = "NAPCCARD Cardbus Controller"; +static const char pci_device_1033_0046[] = "PowerVR PCX2 [midas]"; +static const char pci_device_1033_005a[] = "Vrc5074 [Nile 4]"; +static const char pci_device_1033_0063[] = "Firewarden"; +static const char pci_device_1033_0067[] = "PowerVR Neon 250 Chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0020[] = "PowerVR Neon 250 AGP 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0080[] = "PowerVR Neon 250 AGP 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0088[] = "PowerVR Neon 250 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0090[] = "PowerVR Neon 250 AGP 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0098[] = "PowerVR Neon 250 16Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_00a0[] = "PowerVR Neon 250 AGP 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_00a8[] = "PowerVR Neon 250 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0067_1010_0120[] = "PowerVR Neon 250 AGP 32Mb"; +#endif +static const char pci_device_1033_0072[] = "uPD72874 IEEE1394 OHCI 1.1 3-port PHY-Link Ctrlr"; +static const char pci_device_1033_0074[] = "56k Voice Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_0074_1033_8014[] = "RCV56ACF 56k Voice Modem"; +#endif +static const char pci_device_1033_009b[] = "Vrc5476"; +static const char pci_device_1033_00a5[] = "VRC4173"; +static const char pci_device_1033_00a6[] = "VRC5477 AC97"; +static const char pci_device_1033_00cd[] = "IEEE 1394 [OrangeLink] Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_00cd_12ee_8011[] = "Root hub"; +#endif +static const char pci_device_1033_00ce[] = "IEEE 1394 Host Controller"; +static const char pci_device_1033_00df[] = "Vr4131"; +static const char pci_device_1033_00e0[] = "USB 2.0"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_00e0_12ee_7001[] = "Root hub"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_00e0_14c2_0205[] = "PTI-205N USB 2.0 Host Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_00e0_1799_0002[] = "Root Hub"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1033_00e0_807d_1043[] = "PCI-USB2 (EHCI subsystem)"; +#endif +static const char pci_device_1033_00e7[] = "IEEE 1394 Host Controller"; +static const char pci_device_1033_00f2[] = "uPD72874 IEEE1394 OHCI 1.1 3-port PHY-Link Ctrlr"; +static const char pci_device_1033_00f3[] = "uPD6113x Multimedia Decoder/Processor [EMMA2]"; +static const char pci_device_1033_010c[] = "VR7701"; +static const char pci_device_1033_0125[] = "uPD720400 PCI Express - PCI/PCI-X Bridge"; +static const char pci_device_1033_013a[] = "Dual Tuner/MPEG Encoder"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1034[] = "Framatome Connectors USA Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1035[] = "Comp. & Comm. Research Lab"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1036[] = "Future Domain Corp."; +static const char pci_device_1036_0000[] = "TMC-18C30 [36C70]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1037[] = "Hitachi Micro Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1038[] = "AMP, Inc"; +#endif +static const char pci_vendor_1039[] = "Silicon Integrated Systems [SiS]"; +static const char pci_device_1039_0001[] = "Virtual PCI-to-PCI bridge (AGP)"; +static const char pci_device_1039_0002[] = "SG86C202"; +static const char pci_device_1039_0003[] = "SiS AGP Port (virtual PCI-to-PCI bridge)"; +static const char pci_device_1039_0004[] = "PCI-to-PCI bridge"; +static const char pci_device_1039_0006[] = "85C501/2/3"; +static const char pci_device_1039_0008[] = "SiS85C503/5513 (LPC Bridge)"; +static const char pci_device_1039_0009[] = "ACPI"; +static const char pci_device_1039_000a[] = "PCI-to-PCI bridge"; +static const char pci_device_1039_0016[] = "SiS961/2 SMBus Controller"; +static const char pci_device_1039_0018[] = "SiS85C503/5513 (LPC Bridge)"; +static const char pci_device_1039_0180[] = "RAID bus controller 180 SATA/PATA [SiS]"; +static const char pci_device_1039_0181[] = "SATA"; +static const char pci_device_1039_0182[] = "182 SATA/RAID Controller"; +static const char pci_device_1039_0186[] = "AHCI Controller (0106)"; +static const char pci_device_1039_0190[] = "190 Gigabit Ethernet Adapter"; +static const char pci_device_1039_0191[] = "191 Gigabit Ethernet Adapter"; +static const char pci_device_1039_0200[] = "5597/5598/6326 VGA"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_0200_1039_0000[] = "SiS5597 SVGA (Shared RAM)"; +#endif +static const char pci_device_1039_0204[] = "82C204"; +static const char pci_device_1039_0205[] = "SG86C205"; +static const char pci_device_1039_0300[] = "300/305 PCI/AGP VGA Display Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_0300_107d_2720[] = "Leadtek WinFast VR300"; +#endif +static const char pci_device_1039_0310[] = "315H PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_0315[] = "315 PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_0325[] = "315PRO PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_0330[] = "330 [Xabre] PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_0406[] = "85C501/2"; +static const char pci_device_1039_0496[] = "85C496"; +static const char pci_device_1039_0530[] = "530 Host"; +static const char pci_device_1039_0540[] = "540 Host"; +static const char pci_device_1039_0550[] = "550 Host"; +static const char pci_device_1039_0597[] = "5513C"; +static const char pci_device_1039_0601[] = "85C601"; +static const char pci_device_1039_0620[] = "620 Host"; +static const char pci_device_1039_0630[] = "630 Host"; +static const char pci_device_1039_0633[] = "633 Host"; +static const char pci_device_1039_0635[] = "635 Host"; +static const char pci_device_1039_0645[] = "SiS645 Host & Memory & AGP Controller"; +static const char pci_device_1039_0646[] = "SiS645DX Host & Memory & AGP Controller"; +static const char pci_device_1039_0648[] = "645xx"; +static const char pci_device_1039_0650[] = "650/M650 Host"; +static const char pci_device_1039_0651[] = "651 Host"; +static const char pci_device_1039_0655[] = "655 Host"; +static const char pci_device_1039_0660[] = "660 Host"; +static const char pci_device_1039_0661[] = "661FX/M661FX/M661MX Host"; +static const char pci_device_1039_0662[] = "662 Host"; +static const char pci_device_1039_0730[] = "730 Host"; +static const char pci_device_1039_0733[] = "733 Host"; +static const char pci_device_1039_0735[] = "735 Host"; +static const char pci_device_1039_0740[] = "740 Host"; +static const char pci_device_1039_0741[] = "741/741GX/M741 Host"; +static const char pci_device_1039_0745[] = "745 Host"; +static const char pci_device_1039_0746[] = "746 Host"; +static const char pci_device_1039_0755[] = "755 Host"; +static const char pci_device_1039_0760[] = "760/M760 Host"; +static const char pci_device_1039_0761[] = "761/M761 Host"; +static const char pci_device_1039_0900[] = "SiS900 PCI Fast Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_0900_1019_0a14[] = "K7S5A motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_0900_1039_0900[] = "SiS900 10/100 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_0900_1043_8035[] = "CUSI-FX motherboard"; +#endif +static const char pci_device_1039_0961[] = "SiS961 [MuTIOL Media IO]"; +static const char pci_device_1039_0962[] = "SiS962 [MuTIOL Media IO]"; +static const char pci_device_1039_0963[] = "SiS963 [MuTIOL Media IO]"; +static const char pci_device_1039_0964[] = "SiS964 [MuTIOL Media IO]"; +static const char pci_device_1039_0965[] = "SiS965 [MuTIOL Media IO]"; +static const char pci_device_1039_0966[] = "SiS966 [MuTIOL Media IO]"; +static const char pci_device_1039_0968[] = "SiS968 [MuTIOL Media IO]"; +static const char pci_device_1039_1180[] = "SATA Controller / IDE mode"; +static const char pci_device_1039_1182[] = "SATA Controller / RAID mode"; +static const char pci_device_1039_1183[] = "SATA Controller / IDE mode"; +static const char pci_device_1039_1184[] = "AHCI Controller / RAID mode"; +static const char pci_device_1039_1185[] = "AHCI IDE Controller (0106)"; +static const char pci_device_1039_3602[] = "83C602"; +static const char pci_device_1039_5107[] = "5107"; +static const char pci_device_1039_5300[] = "SiS540 PCI Display Adapter"; +static const char pci_device_1039_5315[] = "550 PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_5401[] = "486 PCI Chipset"; +static const char pci_device_1039_5511[] = "5511/5512"; +static const char pci_device_1039_5513[] = "5513 [IDE]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_5513_1019_0970[] = "P6STP-FL motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_5513_1039_5513[] = "SiS5513 EIDE Controller (A,B step)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_5513_1043_8035[] = "CUSI-FX motherboard"; +#endif +static const char pci_device_1039_5517[] = "5517"; +static const char pci_device_1039_5571[] = "5571"; +static const char pci_device_1039_5581[] = "5581 Pentium Chipset"; +static const char pci_device_1039_5582[] = "5582"; +static const char pci_device_1039_5591[] = "5591/5592 Host"; +static const char pci_device_1039_5596[] = "5596 Pentium Chipset"; +static const char pci_device_1039_5597[] = "5597 [SiS5582]"; +static const char pci_device_1039_5600[] = "5600 Host"; +static const char pci_device_1039_6204[] = "Video decoder & MPEG interface"; +static const char pci_device_1039_6205[] = "VGA Controller"; +static const char pci_device_1039_6236[] = "6236 3D-AGP"; +static const char pci_device_1039_6300[] = "630/730 PCI/AGP VGA Display Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6300_1019_0970[] = "P6STP-FL motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6300_1043_8035[] = "CUSI-FX motherboard"; +#endif +static const char pci_device_1039_6306[] = "530/620 PCI/AGP VGA Display Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6306_1039_6306[] = "SiS530,620 GUI Accelerator+3D"; +#endif +static const char pci_device_1039_6325[] = "65x/M650/740 PCI/AGP VGA Display Adapter"; +static const char pci_device_1039_6326[] = "86C326 5598/6326"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1039_6326[] = "SiS6326 GUI Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1092_0a50[] = "SpeedStar A50"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1092_0a70[] = "SpeedStar A70"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1092_4910[] = "SpeedStar A70"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1092_4920[] = "SpeedStar A70"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6326_1569_6326[] = "SiS6326 GUI Accelerator"; +#endif +static const char pci_device_1039_6330[] = "661/741/760 PCI/AGP or 662/761Gx PCIE VGA Display Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_6330_1039_6330[] = "[M]661xX/[M]741[GX]/[M]760 PCI/AGP VGA Adapter"; +#endif +static const char pci_device_1039_6350[] = "770/670 PCIE VGA Display Adapter"; +static const char pci_device_1039_6351[] = "771/671 PCIE VGA Display Adapter"; +static const char pci_device_1039_7001[] = "USB 1.0 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7001_1019_0a14[] = "K7S5A motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7001_1039_7000[] = "Onboard USB Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7001_1462_5470[] = "K7SOM+ 5.2C Motherboard"; +#endif +static const char pci_device_1039_7002[] = "USB 2.0 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7002_1509_7002[] = "Onboard USB Controller"; +#endif +static const char pci_device_1039_7007[] = "FireWire Controller"; +static const char pci_device_1039_7012[] = "AC'97 Sound Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7012_15bd_1001[] = "DFI 661FX motherboard"; +#endif +static const char pci_device_1039_7013[] = "AC'97 Modem Controller"; +static const char pci_device_1039_7016[] = "SiS7016 PCI Fast Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7016_1039_7016[] = "SiS7016 10/100 Ethernet Adapter"; +#endif +static const char pci_device_1039_7018[] = "SiS PCI Audio Accelerator"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1014_01b6[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1014_01b7[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1019_7018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1025_000e[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1025_0018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1039_7018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1043_800b[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1054_7018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_107d_5330[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_107d_5350[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1170_3209[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1462_400a[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_14a4_2089[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_14cd_2194[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_14ff_1100[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_152d_8808[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1558_1103[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1558_2200[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_1563_7018[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_15c5_0111[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_270f_a171[] = "SiS PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1039_7018_a0a0_0022[] = "SiS PCI Audio Accelerator"; +#endif +static const char pci_device_1039_7019[] = "SiS7019 Audio Accelerator"; +static const char pci_device_1039_7502[] = "Azalia Audio Controller"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_103a[] = "Seiko Epson Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_103b[] = "Tatung Co. of America"; +#endif +static const char pci_vendor_103c[] = "Hewlett-Packard Company"; +static const char pci_device_103c_002a[] = "NX9000 Notebook"; +static const char pci_device_103c_1005[] = "A4977A Visualize EG"; +static const char pci_device_103c_1008[] = "Visualize FX"; +static const char pci_device_103c_1028[] = "Tach TL Fibre Channel Host Adapter"; +static const char pci_device_103c_1029[] = "Tach XL2 Fibre Channel Host Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1029_107e_000f[] = "Interphase 5560 Fibre Channel Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1029_9004_9210[] = "1Gb/2Gb Family Fibre Channel Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1029_9004_9211[] = "1Gb/2Gb Family Fibre Channel Controller"; +#endif +static const char pci_device_103c_102a[] = "Tach TS Fibre Channel Host Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_102a_107e_000e[] = "Interphase 5540/5541 Fibre Channel Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_102a_9004_9110[] = "1Gb/2Gb Family Fibre Channel Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_102a_9004_9111[] = "1Gb/2Gb Family Fibre Channel Controller"; +#endif +static const char pci_device_103c_1030[] = "J2585A DeskDirect 10/100VG NIC"; +static const char pci_device_103c_1031[] = "J2585B HP 10/100VG PCI LAN Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1031_103c_1040[] = "J2973A DeskDirect 10BaseT NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1031_103c_1041[] = "J2585B DeskDirect 10/100VG NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1031_103c_1042[] = "J2970A DeskDirect 10BaseT/2 NIC"; +#endif +static const char pci_device_103c_1040[] = "J2973A DeskDirect 10BaseT NIC"; +static const char pci_device_103c_1041[] = "J2585B DeskDirect 10/100 NIC"; +static const char pci_device_103c_1042[] = "J2970A DeskDirect 10BaseT/2 NIC"; +static const char pci_device_103c_1048[] = "Diva Serial [GSP] Multiport UART"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1049[] = "Tosca Console"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_104a[] = "Tosca Secondary"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_104b[] = "Maestro SP2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1223[] = "Superdome Console"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1226[] = "Keystone SP2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1227[] = "Powerbar SP2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1282[] = "Everest SP2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_1048_103c_1301[] = "Diva RMP3"; +#endif +static const char pci_device_103c_1054[] = "PCI Local Bus Adapter"; +static const char pci_device_103c_1064[] = "79C970 PCnet Ethernet Controller"; +static const char pci_device_103c_108b[] = "Visualize FXe"; +static const char pci_device_103c_10c1[] = "NetServer Smart IRQ Router"; +static const char pci_device_103c_10ed[] = "TopTools Remote Control"; +static const char pci_device_103c_10f0[] = "rio System Bus Adapter"; +static const char pci_device_103c_10f1[] = "rio I/O Controller"; +static const char pci_device_103c_1200[] = "82557B 10/100 NIC"; +static const char pci_device_103c_1219[] = "NetServer PCI Hot-Plug Controller"; +static const char pci_device_103c_121a[] = "NetServer SMIC Controller"; +static const char pci_device_103c_121b[] = "NetServer Legacy COM Port Decoder"; +static const char pci_device_103c_121c[] = "NetServer PCI COM Port Decoder"; +static const char pci_device_103c_1229[] = "zx1 System Bus Adapter"; +static const char pci_device_103c_122a[] = "zx1 I/O Controller"; +static const char pci_device_103c_122e[] = "PCI-X Local Bus Adapter"; +static const char pci_device_103c_127b[] = "sx1000 System Bus Adapter"; +static const char pci_device_103c_127c[] = "sx1000 I/O Controller"; +static const char pci_device_103c_1290[] = "Auxiliary Diva Serial Port"; +static const char pci_device_103c_1291[] = "Auxiliary Diva Serial Port"; +static const char pci_device_103c_12b4[] = "zx1 QuickSilver AGP8x Local Bus Adapter"; +static const char pci_device_103c_12eb[] = "sx2000 System Bus Adapter"; +static const char pci_device_103c_12ec[] = "sx2000 I/O Controller"; +static const char pci_device_103c_12ee[] = "PCI-X 2.0 Local Bus Adapter"; +static const char pci_device_103c_12f8[] = "Broadcom BCM4306 802.11b/g Wireless LAN"; +static const char pci_device_103c_12fa[] = "BCM4306 802.11b/g Wireless LAN Controller"; +static const char pci_device_103c_2910[] = "E2910A PCIBus Exerciser"; +static const char pci_device_103c_2925[] = "E2925A 32 Bit, 33 MHzPCI Exerciser & Analyzer"; +static const char pci_device_103c_3080[] = "Pavilion ze2028ea"; +static const char pci_device_103c_3085[] = "Realtek RTL8139/8139C/8139C+"; +static const char pci_device_103c_3220[] = "Smart Array P600"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_103c_3220_103c_3225[] = "3 Gb/s SAS RAID"; +#endif +static const char pci_device_103c_3230[] = "Smart Array Controller"; +static const char pci_device_103c_4030[] = "zx2 System Bus Adapter"; +static const char pci_device_103c_4031[] = "zx2 I/O Controller"; +static const char pci_device_103c_4037[] = "PCIe Local Bus Adapter"; +static const char pci_device_103c_403b[] = "PCIe Root Port"; +static const char pci_device_103c_60e8[] = "NetRAID-2M : ZX1/M (OEM AMI MegaRAID 493)"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_103e[] = "Solliday Engineering"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_103f[] = "Synopsys/Logic Modeling Group"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1040[] = "Accelgraphics Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1041[] = "Computrend"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1042[] = "Micron"; +static const char pci_device_1042_1000[] = "PC Tech RZ1000"; +static const char pci_device_1042_1001[] = "PC Tech RZ1001"; +static const char pci_device_1042_3000[] = "Samurai_0"; +static const char pci_device_1042_3010[] = "Samurai_1"; +static const char pci_device_1042_3020[] = "Samurai_IDE"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1043[] = "ASUSTeK Computer Inc."; +static const char pci_device_1043_0675[] = "ISDNLink P-IN100-ST-D"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1043_0675_0675_1704[] = "ISDN Adapter (PCI Bus, D, C)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1043_0675_0675_1707[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1043_0675_10cf_105e[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +static const char pci_device_1043_0c11[] = "A7N8X Motherboard nForce2 IDE/USB/SMBus"; +static const char pci_device_1043_4015[] = "v7100 SDRAM [GeForce2 MX]"; +static const char pci_device_1043_4021[] = "v7100 Combo Deluxe [GeForce2 MX + TV tuner]"; +static const char pci_device_1043_4057[] = "v8200 GeForce 3"; +static const char pci_device_1043_8043[] = "v8240 PAL 128M [P4T] Motherboard"; +static const char pci_device_1043_8047[] = "v8420 Deluxe [GeForce4 Ti4200]"; +static const char pci_device_1043_807b[] = "v9280/TD [Geforce4 TI4200 8X With TV-Out and DVI]"; +static const char pci_device_1043_8095[] = "A7N8X Motherboard nForce2 AC97 Audio"; +static const char pci_device_1043_80ac[] = "A7N8X Motherboard nForce2 AGP/Memory"; +static const char pci_device_1043_80bb[] = "v9180 Magic/T [GeForce4 MX440 AGP 8x 64MB TV-out]"; +static const char pci_device_1043_80c5[] = "nForce3 chipset motherboard [SK8N]"; +static const char pci_device_1043_80df[] = "v9520 Magic/T"; +static const char pci_device_1043_815a[] = "A8N-SLI Motherboard nForce4 SATA"; +static const char pci_device_1043_8187[] = "802.11a/b/g Wireless LAN Card"; +static const char pci_device_1043_8188[] = "Tiger Hybrid TV Capture Device"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1044[] = "Adaptec (formerly DPT)"; +static const char pci_device_1044_1012[] = "Domino RAID Engine"; +static const char pci_device_1044_a400[] = "SmartCache/Raid I-IV Controller"; +static const char pci_device_1044_a500[] = "PCI Bridge"; +static const char pci_device_1044_a501[] = "SmartRAID V Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c001[] = "PM1554U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c002[] = "PM1654U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c003[] = "PM1564U3 Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c004[] = "PM1564U3 Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c005[] = "PM1554U2 Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00a[] = "PM2554U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00b[] = "PM2654U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00c[] = "PM2664U3 Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00d[] = "PM2664U3 Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00e[] = "PM2554U2 Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c00f[] = "PM2654U2 Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c014[] = "PM3754U2 Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c015[] = "PM3755U2B Ultra2 Single Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c016[] = "PM3755F Fibre Channel (NON ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c01e[] = "PM3757U2 Ultra2 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c01f[] = "PM3757U2 Ultra2 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c020[] = "PM3767U3 Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c021[] = "PM3767U3 Ultra3 Quad Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c028[] = "PM2865U3 Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c029[] = "PM2865U3 Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c02a[] = "PM2865F Fibre Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c03c[] = "2000S Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c03d[] = "2000S Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c03e[] = "2000F Fibre Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c046[] = "3000S Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c047[] = "3000S Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c048[] = "3000F Fibre Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c050[] = "5000S Ultra3 Single Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c051[] = "5000S Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c052[] = "5000F Fibre Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c05a[] = "2400A UDMA Four Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c05b[] = "2400A UDMA Four Channel DAC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c064[] = "3010S Ultra3 Dual Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c065[] = "3410S Ultra160 Four Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a501_1044_c066[] = "3010S Fibre Channel"; +#endif +static const char pci_device_1044_a511[] = "SmartRAID V Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a511_1044_c032[] = "ASR-2005S I2O Zero Channel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1044_a511_1044_c035[] = "ASR-2010S I2O Zero Channel"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1045[] = "OPTi Inc."; +static const char pci_device_1045_a0f8[] = "82C750 [Vendetta] USB Controller"; +static const char pci_device_1045_c101[] = "92C264"; +static const char pci_device_1045_c178[] = "92C178"; +static const char pci_device_1045_c556[] = "82X556 [Viper]"; +static const char pci_device_1045_c557[] = "82C557 [Viper-M]"; +static const char pci_device_1045_c558[] = "82C558 [Viper-M ISA+IDE]"; +static const char pci_device_1045_c567[] = "82C750 [Vendetta], device 0"; +static const char pci_device_1045_c568[] = "82C750 [Vendetta], device 1"; +static const char pci_device_1045_c569[] = "82C579 [Viper XPress+ Chipset]"; +static const char pci_device_1045_c621[] = "82C621 [Viper-M/N+]"; +static const char pci_device_1045_c700[] = "82C700 [FireStar]"; +static const char pci_device_1045_c701[] = "82C701 [FireStar Plus]"; +static const char pci_device_1045_c814[] = "82C814 [Firebridge 1]"; +static const char pci_device_1045_c822[] = "82C822"; +static const char pci_device_1045_c824[] = "82C824"; +static const char pci_device_1045_c825[] = "82C825 [Firebridge 2]"; +static const char pci_device_1045_c832[] = "82C832"; +static const char pci_device_1045_c861[] = "82C861"; +static const char pci_device_1045_c895[] = "82C895"; +static const char pci_device_1045_c935[] = "EV1935 ECTIVA MachOne PCIAudio"; +static const char pci_device_1045_d568[] = "82C825 [Firebridge 2]"; +static const char pci_device_1045_d721[] = "IDE [FireStar]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1046[] = "IPC Corporation, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1047[] = "Genoa Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1048[] = "Elsa AG"; +static const char pci_device_1048_0c60[] = "Gladiac MX"; +static const char pci_device_1048_0d22[] = "Quadro4 900XGL [ELSA GLoria4 900XGL]"; +static const char pci_device_1048_1000[] = "QuickStep 1000"; +static const char pci_device_1048_3000[] = "QuickStep 3000"; +static const char pci_device_1048_8901[] = "Gloria XL"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1048_8901_1048_0935[] = "GLoria XL (Virge)"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1049[] = "Fountain Technologies, Inc."; +#endif +static const char pci_vendor_104a[] = "STMicroelectronics"; +static const char pci_device_104a_0008[] = "STG 2000X"; +static const char pci_device_104a_0009[] = "STG 1764X"; +static const char pci_device_104a_0010[] = "STG4000 [3D Prophet Kyro Series]"; +static const char pci_device_104a_0209[] = "STPC Consumer/Industrial North- and Southbridge"; +static const char pci_device_104a_020a[] = "STPC Atlas/ConsumerS/Consumer IIA Northbridge"; +static const char pci_device_104a_0210[] = "STPC Atlas ISA Bridge"; +static const char pci_device_104a_021a[] = "STPC Consumer S Southbridge"; +static const char pci_device_104a_021b[] = "STPC Consumer IIA Southbridge"; +static const char pci_device_104a_0500[] = "ST70137 [Unicorn] ADSL DMT Transceiver"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104a_0500_104a_0500[] = "BeWAN ADSL PCI st"; +#endif +static const char pci_device_104a_0564[] = "STPC Client Northbridge"; +static const char pci_device_104a_0981[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_104a_1746[] = "STG 1764X"; +static const char pci_device_104a_2774[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_104a_3520[] = "MPEG-II decoder card"; +static const char pci_device_104a_55cc[] = "STPC Client Southbridge"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_104b[] = "BusLogic"; +static const char pci_device_104b_0140[] = "BT-946C (old) [multimaster 01]"; +static const char pci_device_104b_1040[] = "BT-946C (BA80C30) [MultiMaster 10]"; +static const char pci_device_104b_8130[] = "Flashpoint LT"; +#endif +static const char pci_vendor_104c[] = "Texas Instruments"; +static const char pci_device_104c_0500[] = "100 MBit LAN Controller"; +static const char pci_device_104c_0508[] = "TMS380C2X Compressor Interface"; +static const char pci_device_104c_1000[] = "Eagle i/f AS"; +static const char pci_device_104c_104c[] = "PCI1510 PC card Cardbus Controller"; +static const char pci_device_104c_3d04[] = "TVP4010 [Permedia]"; +static const char pci_device_104c_3d07[] = "TVP4020 [Permedia 2]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1011_4d10[] = "Comet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1040_000f[] = "AccelStar II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1040_0011[] = "AccelStar II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a31[] = "WINNER 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a32[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a34[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a35[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a36[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a43[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1048_0a44[] = "GLoria Synergy"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_107d_2633[] = "WinFast 3D L2300"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0127[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0136[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0141[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0146[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0148[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0149[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0152[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0154[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0155[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0156[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1092_0157[] = "FIRE GL 1000 PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1097_3d01[] = "Jeronimo Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_1102_100f[] = "Graphics Blaster Extreme"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_3d07_3d3d_0100[] = "Reference Permedia 2 3D"; +#endif +static const char pci_device_104c_8000[] = "PCILynx/PCILynx2 IEEE 1394 Link Layer Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8000_e4bf_1010[] = "CF1-1-SNARE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8000_e4bf_1020[] = "CF1-2-SNARE"; +#endif +static const char pci_device_104c_8009[] = "FireWire Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8009_104d_8032[] = "8032 OHCI i.LINK (IEEE 1394) Controller"; +#endif +static const char pci_device_104c_8017[] = "PCI4410 FireWire Controller"; +static const char pci_device_104c_8019[] = "TSB12LV23 IEEE-1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8019_11bd_000a[] = "Studio DV500-1394"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8019_11bd_000e[] = "Studio DV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8019_e4bf_1010[] = "CF2-1-CYMBAL"; +#endif +static const char pci_device_104c_8020[] = "TSB12LV26 IEEE-1394 Controller (Link)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8020_11bd_000f[] = "Studio DV500-1394"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8020_11bd_001c[] = "Excalibur 4.1"; +#endif +static const char pci_device_104c_8021[] = "TSB43AA22 IEEE-1394 Controller (PHY/Link Integrated)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8021_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8021_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +static const char pci_device_104c_8022[] = "TSB43AB22 IEEE-1394a-2000 Controller (PHY/Link)"; +static const char pci_device_104c_8023[] = "TSB43AB22/A IEEE-1394a-2000 Controller (PHY/Link)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8023_103c_088c[] = "NC8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8023_1043_808b[] = "K8N4-E Mainboard"; +#endif +static const char pci_device_104c_8024[] = "TSB43AB23 IEEE-1394a-2000 Controller (PHY/Link)"; +static const char pci_device_104c_8025[] = "TSB82AA2 IEEE-1394b Link Layer Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8025_1458_1000[] = "GA-K8N Ultra-9 Mainboard"; +#endif +static const char pci_device_104c_8026[] = "TSB43AB21 IEEE-1394a-2000 Controller (PHY/Link)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8026_1025_003c[] = "Aspire 2001WLCi (Compaq CL50 motherboard)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8026_103c_006a[] = "NX9500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8026_1043_808d[] = "A7V333 mainboard."; +#endif +static const char pci_device_104c_8027[] = "PCI4451 IEEE-1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8027_1028_00e6[] = "PCI4451 IEEE-1394 Controller (Dell Inspiron 8100)"; +#endif +static const char pci_device_104c_8029[] = "PCI4510 IEEE-1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8029_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8029_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8029_1071_8160[] = "MIM2900"; +#endif +static const char pci_device_104c_802b[] = "PCI7410,7510,7610 OHCI-Lynx Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_802b_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_802b_1028_014e[] = "PCI7410,7510,7610 OHCI-Lynx Controller (Latitude D800)"; +#endif +static const char pci_device_104c_802e[] = "PCI7x20 1394a-2000 OHCI Two-Port PHY/Link-Layer Controller"; +static const char pci_device_104c_8031[] = "PCIxx21/x515 Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8031_1025_0080[] = "Aspire 5024WLMi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8031_103c_099c[] = "NX6110/NC6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8031_103c_308b[] = "MX6125"; +#endif +static const char pci_device_104c_8032[] = "OHCI Compliant IEEE 1394 Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8032_1025_0080[] = "Aspire 5024WLMi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8032_103c_099c[] = "NX6110/NC6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8032_103c_308b[] = "MX6125"; +#endif +static const char pci_device_104c_8033[] = "PCIxx21 Integrated FlashMedia Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8033_1025_0080[] = "Aspire 5024WLMi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8033_103c_099c[] = "NX6110/NC6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8033_103c_308b[] = "MX6125"; +#endif +static const char pci_device_104c_8034[] = "PCI6411/6421/6611/6621/7411/7421/7611/7621 Secure Digital Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8034_1025_0080[] = "Aspire 5024WLMi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8034_103c_099c[] = "NX6110/NC6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8034_103c_308b[] = "MX6125"; +#endif +static const char pci_device_104c_8035[] = "PCI6411/6421/6611/6621/7411/7421/7611/7621 Smart Card Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8035_103c_099c[] = "NX6110/NC6120"; +#endif +static const char pci_device_104c_8036[] = "PCI6515 Cardbus Controller"; +static const char pci_device_104c_8038[] = "PCI6515 SmartCard Controller"; +static const char pci_device_104c_8039[] = "PCIxx12 Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8039_103c_309f[] = "nx9420"; +#endif +static const char pci_device_104c_803a[] = "PCIxx12 OHCI Compliant IEEE 1394 Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_803a_103c_309f[] = "nx9420"; +#endif +static const char pci_device_104c_803b[] = "5-in-1 Multimedia Card Reader (SD/MMC/MS/MS PRO/xD)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_803b_103c_309f[] = "nx9420"; +#endif +static const char pci_device_104c_803c[] = "PCIxx12 SDA Standard Compliant SD Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_803c_103c_309f[] = "nx9420"; +#endif +static const char pci_device_104c_803d[] = "PCIxx12 GemCore based SmartCard controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_803d_103c_309f[] = "nx9420"; +#endif +static const char pci_device_104c_8201[] = "PCI1620 Firmware Loading Function"; +static const char pci_device_104c_8204[] = "PCI7410,7510,7610 PCI Firmware Loading Function"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8204_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8204_1028_014e[] = "Latitude D800"; +#endif +static const char pci_device_104c_8231[] = "XIO2000(A)/XIO2200(A) PCI Express-to-PCI Bridge"; +static const char pci_device_104c_8235[] = "XIO2200(A) IEEE-1394a-2000 Controller (PHY/Link)"; +static const char pci_device_104c_8400[] = "ACX 100 22Mbps Wireless Interface"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8400_1186_3b00[] = "DWL-650+ PC Card cardbus 22Mbs Wireless Adapter [AirPlus]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8400_1186_3b01[] = "DWL-520+ 22Mbps PCI Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_8400_16ab_8501[] = "WL-8305 IEEE802.11b+ Wireless LAN PCI Adapter"; +#endif +static const char pci_device_104c_8401[] = "ACX 100 22Mbps Wireless Interface"; +static const char pci_device_104c_9000[] = "Wireless Interface (of unknown type)"; +static const char pci_device_104c_9065[] = "TMS320DM642"; +static const char pci_device_104c_9066[] = "ACX 111 54Mbps Wireless Interface"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_9066_104c_9066[] = "Trendnet TEW-421PC Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_9066_1186_3b04[] = "DWL-G520+ Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_9066_1186_3b05[] = "DWL-G650+ AirPlusG+ CardBus Wireless LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_9066_13d1_aba0[] = "SWLMP-54108 108Mbps Wireless mini PCI card 802.11g+"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_9066_1737_0033[] = "WPC54G Ver.2 802.11G PC Card"; +#endif +static const char pci_device_104c_a001[] = "TDC1570"; +static const char pci_device_104c_a100[] = "TDC1561"; +static const char pci_device_104c_a102[] = "TNETA1575 HyperSAR Plus w/PCI Host i/f & UTOPIA i/f"; +static const char pci_device_104c_a106[] = "TMS320C6414 TMS320C6415 TMS320C6416"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_a106_175c_5000[] = "ASI50xx Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_a106_175c_6400[] = "ASI6400 Cobranet series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_a106_175c_8700[] = "ASI87xx Radio Tuner card"; +#endif +static const char pci_device_104c_ac10[] = "PCI1050"; +static const char pci_device_104c_ac11[] = "PCI1053"; +static const char pci_device_104c_ac12[] = "PCI1130"; +static const char pci_device_104c_ac13[] = "PCI1031"; +static const char pci_device_104c_ac15[] = "PCI1131"; +static const char pci_device_104c_ac16[] = "PCI1250"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac16_1014_0092[] = "ThinkPad 600"; +#endif +static const char pci_device_104c_ac17[] = "PCI1220"; +static const char pci_device_104c_ac18[] = "PCI1260"; +static const char pci_device_104c_ac19[] = "PCI1221"; +static const char pci_device_104c_ac1a[] = "PCI1210"; +static const char pci_device_104c_ac1b[] = "PCI1450"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac1b_0e11_b113[] = "Armada M700"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac1b_1014_0130[] = "Thinkpad T20/T22/A21m"; +#endif +static const char pci_device_104c_ac1c[] = "PCI1225"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac1c_0e11_b121[] = "Armada E500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac1c_1028_0088[] = "Latitude CPi A400XT"; +#endif +static const char pci_device_104c_ac1d[] = "PCI1251A"; +static const char pci_device_104c_ac1e[] = "PCI1211"; +static const char pci_device_104c_ac1f[] = "PCI1251B"; +static const char pci_device_104c_ac20[] = "TI 2030"; +static const char pci_device_104c_ac21[] = "PCI2031"; +static const char pci_device_104c_ac22[] = "PCI2032 PCI Docking Bridge"; +static const char pci_device_104c_ac23[] = "PCI2250 PCI-to-PCI Bridge"; +static const char pci_device_104c_ac28[] = "PCI2050 PCI-to-PCI Bridge"; +static const char pci_device_104c_ac30[] = "PCI1260 PC card Cardbus Controller"; +static const char pci_device_104c_ac40[] = "PCI4450 PC card Cardbus Controller"; +static const char pci_device_104c_ac41[] = "PCI4410 PC card Cardbus Controller"; +static const char pci_device_104c_ac42[] = "PCI4451 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac42_1028_00e6[] = "PCI4451 PC card CardBus Controller (Inspiron 8100)"; +#endif +static const char pci_device_104c_ac44[] = "PCI4510 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac44_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac44_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac44_1071_8160[] = "MIM2000"; +#endif +static const char pci_device_104c_ac46[] = "PCI4520 PC card Cardbus Controller"; +static const char pci_device_104c_ac47[] = "PCI7510 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac47_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac47_1028_013f[] = "Precision M60"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac47_1028_014e[] = "Latitude D800"; +#endif +static const char pci_device_104c_ac4a[] = "PCI7510,7610 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac4a_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac4a_1028_014e[] = "Latitude D800"; +#endif +static const char pci_device_104c_ac50[] = "PCI1410 PC card Cardbus Controller"; +static const char pci_device_104c_ac51[] = "PCI1420"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_0e11_004e[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_1014_0148[] = "ThinkPad A20m"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_1014_023b[] = "ThinkPad T23 (2647-4MG)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_1028_00b1[] = "Latitude C600"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_1028_012a[] = "Latitude C640"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_1033_80cd[] = "Versa Note VXi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_1095_10cf[] = "Fujitsu-Siemens LifeBook C Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_10cf_1095[] = "Lifebook S-4510/C6155"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac51_e4bf_1000[] = "CP2-2-HIPHOP"; +#endif +static const char pci_device_104c_ac52[] = "PCI1451 PC card Cardbus Controller"; +static const char pci_device_104c_ac53[] = "PCI1421 PC card Cardbus Controller"; +static const char pci_device_104c_ac54[] = "PCI1620 PC Card Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac54_103c_08b0[] = "tc1100 tablet"; +#endif +static const char pci_device_104c_ac55[] = "PCI1520 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac55_1014_0512[] = "ThinkPad T30/T40"; +#endif +static const char pci_device_104c_ac56[] = "PCI1510 PC card Cardbus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac56_1014_0512[] = "Thinkpad R50e model 1634"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac56_1014_0528[] = "ThinkPad R40e (2684-HVG) Cardbus Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac56_17aa_2012[] = "Thinkpad R60e model 0657"; +#endif +static const char pci_device_104c_ac60[] = "PCI2040 PCI to DSP Bridge Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac60_175c_5100[] = "ASI51xx Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac60_175c_6100[] = "ASI61xx Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac60_175c_6200[] = "ASI62xx Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_104c_ac60_175c_8800[] = "ASI88xx Audio Adapter"; +#endif +static const char pci_device_104c_ac8d[] = "PCI 7620"; +static const char pci_device_104c_ac8e[] = "PCI7420 CardBus Controller"; +static const char pci_device_104c_ac8f[] = "PCI7420/7620 Combo CardBus, 1394a-2000 OHCI and SD/MS-Pro Controller"; +static const char pci_device_104c_fe00[] = "FireWire Host Controller"; +static const char pci_device_104c_fe03[] = "12C01A FireWire Host Controller"; +static const char pci_vendor_104d[] = "Sony Corporation"; +static const char pci_device_104d_8004[] = "DTL-H2500 [Playstation development board]"; +static const char pci_device_104d_8009[] = "CXD1947Q i.LINK Controller"; +static const char pci_device_104d_8039[] = "CXD3222 i.LINK Controller"; +static const char pci_device_104d_8056[] = "Rockwell HCF 56K modem"; +static const char pci_device_104d_808a[] = "Memory Stick Controller"; +static const char pci_vendor_104e[] = "Oak Technology, Inc"; +static const char pci_device_104e_0017[] = "OTI-64017"; +static const char pci_device_104e_0107[] = "OTI-107 [Spitfire]"; +static const char pci_device_104e_0109[] = "Video Adapter"; +static const char pci_device_104e_0111[] = "OTI-64111 [Spitfire]"; +static const char pci_device_104e_0217[] = "OTI-64217"; +static const char pci_device_104e_0317[] = "OTI-64317"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_104f[] = "Co-time Computer Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1050[] = "Winbond Electronics Corp"; +static const char pci_device_1050_0000[] = "NE2000"; +static const char pci_device_1050_0001[] = "W83769F"; +static const char pci_device_1050_0033[] = "W89C33D 802.11 a/b/g BB/MAC"; +static const char pci_device_1050_0105[] = "W82C105"; +static const char pci_device_1050_0840[] = "W89C840"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_0840_1050_0001[] = "W89C840 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_0840_1050_0840[] = "W89C840 Ethernet Adapter"; +#endif +static const char pci_device_1050_0940[] = "W89C940"; +static const char pci_device_1050_5a5a[] = "W89C940F"; +static const char pci_device_1050_6692[] = "W6692"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_1043_1702[] = "ISDN Adapter (PCI Bus, D, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_1043_1703[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_1043_1707[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_144f_1702[] = "ISDN Adapter (PCI Bus, D, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_144f_1703[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1050_6692_144f_1707[] = "ISDN Adapter (PCI Bus, DV, W)"; +#endif +static const char pci_device_1050_9921[] = "W99200F MPEG-1 Video Encoder"; +static const char pci_device_1050_9922[] = "W99200F/W9922PF MPEG-1/2 Video Encoder"; +static const char pci_device_1050_9970[] = "W9970CF"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1051[] = "Anigma, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1052[] = "?Young Micro Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1053[] = "Young Micro Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1054[] = "Hitachi, Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1055[] = "Efar Microsystems"; +static const char pci_device_1055_9130[] = "SLC90E66 [Victory66] IDE"; +static const char pci_device_1055_9460[] = "SLC90E66 [Victory66] ISA"; +static const char pci_device_1055_9462[] = "SLC90E66 [Victory66] USB"; +static const char pci_device_1055_9463[] = "SLC90E66 [Victory66] ACPI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1056[] = "ICL"; +#endif +static const char pci_vendor_1057[] = "Motorola"; +static const char pci_device_1057_0001[] = "MPC105 [Eagle]"; +static const char pci_device_1057_0002[] = "MPC106 [Grackle]"; +static const char pci_device_1057_0003[] = "MPC8240 [Kahlua]"; +static const char pci_device_1057_0004[] = "MPC107"; +static const char pci_device_1057_0006[] = "MPC8245 [Unity]"; +static const char pci_device_1057_0008[] = "MPC8540"; +static const char pci_device_1057_0009[] = "MPC8560"; +static const char pci_device_1057_0012[] = "MPC8548 [PowerQUICC III]"; +static const char pci_device_1057_0100[] = "MC145575 [HFC-PCI]"; +static const char pci_device_1057_0431[] = "KTI829c 100VG"; +static const char pci_device_1057_1801[] = "DSP56301 Digital Signal Processor"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0101[] = "Transas Radar Imitator Board [RIM]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0102[] = "Transas Radar Imitator Board [RIM-2]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0202[] = "Transas Radar Integrator Board [RIB-2]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0611[] = "1 channel CAN bus Controller [CanPci-1]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0612[] = "2 channels CAN bus Controller [CanPci-2]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0613[] = "3 channels CAN bus Controller [CanPci-3]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0614[] = "4 channels CAN bus Controller [CanPci-4]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0621[] = "1 channel CAN bus Controller [CanPci2-1]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0622[] = "2 channels CAN bus Controller [CanPci2-2]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_14fb_0810[] = "Transas VTS Radar Integrator Board [RIB-4]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_175c_4200[] = "ASI4215 Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_175c_4300[] = "ASI43xx Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_175c_4400[] = "ASI4401 Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0010[] = "Darla"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0020[] = "Gina"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0030[] = "Layla rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0031[] = "Layla rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0040[] = "Darla24 rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0041[] = "Darla24 rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0050[] = "Gina24 rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0051[] = "Gina24 rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0070[] = "Mona rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0071[] = "Mona rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_1801_ecc0_0072[] = "Mona rev.2"; +#endif +static const char pci_device_1057_18c0[] = "MPC8265A/8266/8272"; +static const char pci_device_1057_18c1[] = "MPC8271/MPC8272"; +static const char pci_device_1057_3055[] = "SM56 Data Fax Modem"; +static const char pci_device_1057_3410[] = "DSP56361 Digital Signal Processor"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0050[] = "Gina24 rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0051[] = "Gina24 rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0060[] = "Layla24"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0070[] = "Mona rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0071[] = "Mona rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0072[] = "Mona rev.2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0080[] = "Mia rev.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0081[] = "Mia rev.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0090[] = "Indigo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_00a0[] = "Indigo IO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_00b0[] = "Indigo DJ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_3410_ecc0_0100[] = "3G"; +#endif +static const char pci_device_1057_4801[] = "Raven"; +static const char pci_device_1057_4802[] = "Falcon"; +static const char pci_device_1057_4803[] = "Hawk"; +static const char pci_device_1057_4806[] = "CPX8216"; +static const char pci_device_1057_4d68[] = "20268"; +static const char pci_device_1057_5600[] = "SM56 PCI Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1057_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1057_0301[] = "SM56 PCI Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1057_0302[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1057_5600[] = "SM56 PCI Voice modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_13d2_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_13d2_0301[] = "SM56 PCI Voice modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_13d2_0302[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1436_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1436_0301[] = "SM56 PCI Voice modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1436_0302[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_144f_100c[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1494_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1494_0301[] = "SM56 PCI Voice modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_14c8_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_14c8_0302[] = "SM56 PCI Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1668_0300[] = "SM56 PCI Speakerphone Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1057_5600_1668_0302[] = "SM56 PCI Fax Modem"; +#endif +static const char pci_device_1057_5608[] = "Wildcard X100P"; +static const char pci_device_1057_5803[] = "MPC5200"; +static const char pci_device_1057_5806[] = "MCF54 Coldfire"; +static const char pci_device_1057_5808[] = "MPC8220"; +static const char pci_device_1057_5809[] = "MPC5200B"; +static const char pci_device_1057_6400[] = "MPC190 Security Processor (S1 family, encryption)"; +static const char pci_device_1057_6405[] = "MPC184 Security Processor (S1 family)"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1058[] = "Electronics & Telecommunications RSH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1059[] = "Teknor Industrial Computers Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105a[] = "Promise Technology, Inc."; +static const char pci_device_105a_0d30[] = "PDC20265 (FastTrak100 Lite/Ultra100)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_0d30_105a_4d33[] = "Ultra100"; +#endif +static const char pci_device_105a_0d38[] = "20263"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_0d38_105a_4d39[] = "Fasttrak66"; +#endif +static const char pci_device_105a_1275[] = "20275"; +static const char pci_device_105a_3318[] = "PDC20318 (SATA150 TX4)"; +static const char pci_device_105a_3319[] = "PDC20319 (FastTrak S150 TX4)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_3319_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_105a_3371[] = "PDC20371 (FastTrak S150 TX2plus)"; +static const char pci_device_105a_3373[] = "PDC20378 (FastTrak 378/SATA 378)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_3373_1043_80f5[] = "K8V Deluxe/PC-DL Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_3373_1462_702e[] = "K8T NEO FIS2R motherboard"; +#endif +static const char pci_device_105a_3375[] = "PDC20375 (SATA150 TX2plus)"; +static const char pci_device_105a_3376[] = "PDC20376 (FastTrak 376)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_3376_1043_809e[] = "A7V8X motherboard"; +#endif +static const char pci_device_105a_3515[] = "PDC40719 [FastTrak TX4300/TX4310]"; +static const char pci_device_105a_3519[] = "PDC40519 (FastTrak TX4200)"; +static const char pci_device_105a_3570[] = "20771 (FastTrak TX2300)"; +static const char pci_device_105a_3571[] = "PDC20571 (FastTrak TX2200)"; +static const char pci_device_105a_3574[] = "PDC20579 SATAII 150 IDE Controller"; +static const char pci_device_105a_3577[] = "PDC40779 (SATA 300 779)"; +static const char pci_device_105a_3d17[] = "PDC40718 (SATA 300 TX4)"; +static const char pci_device_105a_3d18[] = "PDC20518/PDC40518 (SATAII 150 TX4)"; +static const char pci_device_105a_3d73[] = "PDC40775 (SATA 300 TX2plus)"; +static const char pci_device_105a_3d75[] = "PDC20575 (SATAII150 TX2plus)"; +static const char pci_device_105a_4302[] = "80333 [SuperTrak EX4350]"; +static const char pci_device_105a_4d30[] = "PDC20267 (FastTrak100/Ultra100)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d30_105a_4d33[] = "Ultra100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d30_105a_4d39[] = "FastTrak100"; +#endif +static const char pci_device_105a_4d33[] = "20246"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d33_105a_4d33[] = "20246 IDE Controller"; +#endif +static const char pci_device_105a_4d38[] = "PDC20262 (FastTrak66/Ultra66)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d38_105a_4d30[] = "Ultra Device on SuperTrak"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d38_105a_4d33[] = "Ultra66"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d38_105a_4d39[] = "FastTrak66"; +#endif +static const char pci_device_105a_4d68[] = "PDC20268 (Ultra100 TX2)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d68_105a_4d68[] = "Ultra100TX2"; +#endif +static const char pci_device_105a_4d69[] = "20269"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_4d69_105a_4d68[] = "Ultra133TX2"; +#endif +static const char pci_device_105a_5275[] = "PDC20276 (MBFastTrak133 Lite)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_5275_1043_807e[] = "A7V333 motherboard."; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_5275_105a_0275[] = "SuperTrak SX6000 IDE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_5275_105a_1275[] = "MBFastTrak133 Lite (tm) Controller (RAID mode)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_5275_1458_b001[] = "MBUltra 133"; +#endif +static const char pci_device_105a_5300[] = "DC5300"; +static const char pci_device_105a_6268[] = "PDC20270 (FastTrak100 LP/TX2/TX4)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_6268_105a_4d68[] = "FastTrak100 TX2"; +#endif +static const char pci_device_105a_6269[] = "PDC20271 (FastTrak TX2000)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105a_6269_105a_6269[] = "FastTrak TX2/TX2000"; +#endif +static const char pci_device_105a_6621[] = "PDC20621 (FastTrak S150 SX4/FastTrak SX4000 lite)"; +static const char pci_device_105a_6622[] = "PDC20621 [SATA150 SX4] 4 Channel IDE RAID Controller"; +static const char pci_device_105a_6624[] = "PDC20621 [FastTrak SX4100]"; +static const char pci_device_105a_6626[] = "PDC20618 (Ultra 618)"; +static const char pci_device_105a_6629[] = "PDC20619 (FastTrak TX4000)"; +static const char pci_device_105a_7275[] = "PDC20277 (SBFastTrak133 Lite)"; +static const char pci_device_105a_8002[] = "SATAII150 SX8"; +static const char pci_device_105a_8350[] = "80333 [SuperTrak EX8350/EX16350], 80331 [SuperTrak EX8300/EX16300]"; +static const char pci_device_105a_c350[] = "80333 [SuperTrak EX12350]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105b[] = "Foxconn International, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105c[] = "Wipro Infotech Limited"; +#endif +static const char pci_vendor_105d[] = "Number 9 Computer Company"; +static const char pci_device_105d_2309[] = "Imagine 128"; +static const char pci_device_105d_2339[] = "Imagine 128-II"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0000[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0001[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0002[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0003[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0004[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0005[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0006[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0007[] = "Imagine 128 series 2 4Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0008[] = "Imagine 128 series 2e 4Mb DRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_0009[] = "Imagine 128 series 2e 4Mb DRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_000a[] = "Imagine 128 series 2 8Mb VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_105d_000b[] = "Imagine 128 series 2 8Mb H-VRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_11a4_000a[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0000[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0004[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0005[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0006[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0008[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_0009[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_000a[] = "Barco Metheus 5 Megapixel"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_2339_13cc_000c[] = "Barco Metheus 5 Megapixel"; +#endif +static const char pci_device_105d_493d[] = "Imagine 128 T2R [Ticket to Ride]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_11a4_000a[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_11a4_000b[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0002[] = "Barco Metheus 4 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0003[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0007[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0008[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_0009[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_493d_13cc_000a[] = "Barco Metheus 5 Megapixel, Dual Head"; +#endif +static const char pci_device_105d_5348[] = "Revolution 4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_5348_105d_0037[] = "Revolution IV-FP AGP (For SGI 1600SW)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_5348_11a4_0028[] = "PVS5600M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_105d_5348_11a4_0038[] = "PVS5600D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105e[] = "Vtech Computers Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_105f[] = "Infotronic America Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1060[] = "United Microelectronics [UMC]"; +static const char pci_device_1060_0001[] = "UM82C881"; +static const char pci_device_1060_0002[] = "UM82C886"; +static const char pci_device_1060_0101[] = "UM8673F"; +static const char pci_device_1060_0881[] = "UM8881"; +static const char pci_device_1060_0886[] = "UM8886F"; +static const char pci_device_1060_0891[] = "UM8891A"; +static const char pci_device_1060_1001[] = "UM886A"; +static const char pci_device_1060_673a[] = "UM8886BF"; +static const char pci_device_1060_673b[] = "EIDE Master/DMA"; +static const char pci_device_1060_8710[] = "UM8710"; +static const char pci_device_1060_886a[] = "UM8886A"; +static const char pci_device_1060_8881[] = "UM8881F"; +static const char pci_device_1060_8886[] = "UM8886F"; +static const char pci_device_1060_888a[] = "UM8886A"; +static const char pci_device_1060_8891[] = "UM8891A"; +static const char pci_device_1060_9017[] = "UM9017F"; +static const char pci_device_1060_9018[] = "UM9018"; +static const char pci_device_1060_9026[] = "UM9026"; +static const char pci_device_1060_e881[] = "UM8881N"; +static const char pci_device_1060_e886[] = "UM8886N"; +static const char pci_device_1060_e88a[] = "UM8886N"; +static const char pci_device_1060_e891[] = "UM8891N"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1061[] = "I.I.T."; +static const char pci_device_1061_0001[] = "AGX016"; +static const char pci_device_1061_0002[] = "IIT3204/3501"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1062[] = "Maspar Computer Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1063[] = "Ocean Office Automation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1064[] = "Alcatel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1065[] = "Texas Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1066[] = "PicoPower Technology"; +static const char pci_device_1066_0000[] = "PT80C826"; +static const char pci_device_1066_0001[] = "PT86C521 [Vesuvius v1] Host Bridge"; +static const char pci_device_1066_0002[] = "PT86C523 [Vesuvius v3] PCI-ISA Bridge Master"; +static const char pci_device_1066_0003[] = "PT86C524 [Nile] PCI-to-PCI Bridge"; +static const char pci_device_1066_0004[] = "PT86C525 [Nile-II] PCI-to-PCI Bridge"; +static const char pci_device_1066_0005[] = "National PC87550 System Controller"; +static const char pci_device_1066_8002[] = "PT86C523 [Vesuvius v3] PCI-ISA Bridge Slave"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1067[] = "Mitsubishi Electric"; +static const char pci_device_1067_0301[] = "AccelGraphics AccelECLIPSE"; +static const char pci_device_1067_0304[] = "AccelGALAXY A2100 [OEM Evans & Sutherland]"; +static const char pci_device_1067_0308[] = "Tornado 3000 [OEM Evans & Sutherland]"; +static const char pci_device_1067_1002[] = "VG500 [VolumePro Volume Rendering Accelerator]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1068[] = "Diversified Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1069[] = "Mylex Corporation"; +static const char pci_device_1069_0001[] = "DAC960P"; +static const char pci_device_1069_0002[] = "DAC960PD"; +static const char pci_device_1069_0010[] = "DAC960PG"; +static const char pci_device_1069_0020[] = "DAC960LA"; +static const char pci_device_1069_0050[] = "AcceleRAID 352/170/160 support Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_0050_1069_0050[] = "AcceleRAID 352 support Device"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_0050_1069_0052[] = "AcceleRAID 170 support Device"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_0050_1069_0054[] = "AcceleRAID 160 support Device"; +#endif +static const char pci_device_1069_b166[] = "AcceleRAID 600/500/400/Sapphire support Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1014_0242[] = "iSeries 2872 DASD IOA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1014_0266[] = "Dual Channel PCI-X U320 SCSI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1014_0278[] = "Dual Channel PCI-X U320 SCSI RAID Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1014_02d3[] = "Dual Channel PCI-X U320 SCSI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1014_02d4[] = "Dual Channel PCI-X U320 SCSI RAID Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1069_0200[] = "AcceleRAID 400, Single Channel, PCI-X, U320, SCSI RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1069_0202[] = "AcceleRAID Sapphire, Dual Channel, PCI-X, U320, SCSI RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1069_0204[] = "AcceleRAID 500, Dual Channel, Low-Profile, PCI-X, U320, SCSI RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_b166_1069_0206[] = "AcceleRAID 600, Dual Channel, PCI-X, U320, SCSI RAID"; +#endif +static const char pci_device_1069_ba55[] = "eXtremeRAID 1100 support Device"; +static const char pci_device_1069_ba56[] = "eXtremeRAID 2000/3000 support Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_ba56_1069_0030[] = "eXtremeRAID 3000 support Device"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_ba56_1069_0040[] = "eXtremeRAID 2000 support Device"; +#endif +static const char pci_device_1069_ba57[] = "eXtremeRAID 4000/5000 support Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1069_ba57_1069_0072[] = "eXtremeRAID 5000 support Device"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106a[] = "Aten Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106b[] = "Apple Computer Inc."; +static const char pci_device_106b_0001[] = "Bandit PowerPC host bridge"; +static const char pci_device_106b_0002[] = "Grand Central I/O"; +static const char pci_device_106b_0003[] = "Control Video"; +static const char pci_device_106b_0004[] = "PlanB Video-In"; +static const char pci_device_106b_0007[] = "O'Hare I/O"; +static const char pci_device_106b_000c[] = "DOS on Mac"; +static const char pci_device_106b_000e[] = "Hydra Mac I/O"; +static const char pci_device_106b_0010[] = "Heathrow Mac I/O"; +static const char pci_device_106b_0017[] = "Paddington Mac I/O"; +static const char pci_device_106b_0018[] = "UniNorth FireWire"; +static const char pci_device_106b_0019[] = "KeyLargo USB"; +static const char pci_device_106b_001e[] = "UniNorth Internal PCI"; +static const char pci_device_106b_001f[] = "UniNorth PCI"; +static const char pci_device_106b_0020[] = "UniNorth AGP"; +static const char pci_device_106b_0021[] = "UniNorth GMAC (Sun GEM)"; +static const char pci_device_106b_0022[] = "KeyLargo Mac I/O"; +static const char pci_device_106b_0024[] = "UniNorth/Pangea GMAC (Sun GEM)"; +static const char pci_device_106b_0025[] = "KeyLargo/Pangea Mac I/O"; +static const char pci_device_106b_0026[] = "KeyLargo/Pangea USB"; +static const char pci_device_106b_0027[] = "UniNorth/Pangea AGP"; +static const char pci_device_106b_0028[] = "UniNorth/Pangea PCI"; +static const char pci_device_106b_0029[] = "UniNorth/Pangea Internal PCI"; +static const char pci_device_106b_002d[] = "UniNorth 1.5 AGP"; +static const char pci_device_106b_002e[] = "UniNorth 1.5 PCI"; +static const char pci_device_106b_002f[] = "UniNorth 1.5 Internal PCI"; +static const char pci_device_106b_0030[] = "UniNorth/Pangea FireWire"; +static const char pci_device_106b_0031[] = "UniNorth 2 FireWire"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_106b_0031_106b_5811[] = "iBook G4 2004"; +#endif +static const char pci_device_106b_0032[] = "UniNorth 2 GMAC (Sun GEM)"; +static const char pci_device_106b_0033[] = "UniNorth 2 ATA/100"; +static const char pci_device_106b_0034[] = "UniNorth 2 AGP"; +static const char pci_device_106b_0035[] = "UniNorth 2 PCI"; +static const char pci_device_106b_0036[] = "UniNorth 2 Internal PCI"; +static const char pci_device_106b_003b[] = "UniNorth/Intrepid ATA/100"; +static const char pci_device_106b_003e[] = "KeyLargo/Intrepid Mac I/O"; +static const char pci_device_106b_003f[] = "KeyLargo/Intrepid USB"; +static const char pci_device_106b_0040[] = "K2 KeyLargo USB"; +static const char pci_device_106b_0041[] = "K2 KeyLargo Mac/IO"; +static const char pci_device_106b_0042[] = "K2 FireWire"; +static const char pci_device_106b_0043[] = "K2 ATA/100"; +static const char pci_device_106b_0045[] = "K2 HT-PCI Bridge"; +static const char pci_device_106b_0046[] = "K2 HT-PCI Bridge"; +static const char pci_device_106b_0047[] = "K2 HT-PCI Bridge"; +static const char pci_device_106b_0048[] = "K2 HT-PCI Bridge"; +static const char pci_device_106b_0049[] = "K2 HT-PCI Bridge"; +static const char pci_device_106b_004b[] = "U3 AGP"; +static const char pci_device_106b_004c[] = "K2 GMAC (Sun GEM)"; +static const char pci_device_106b_004f[] = "Shasta Mac I/O"; +static const char pci_device_106b_0050[] = "Shasta IDE"; +static const char pci_device_106b_0051[] = "Shasta (Sun GEM)"; +static const char pci_device_106b_0052[] = "Shasta Firewire"; +static const char pci_device_106b_0053[] = "Shasta PCI Bridge"; +static const char pci_device_106b_0054[] = "Shasta PCI Bridge"; +static const char pci_device_106b_0055[] = "Shasta PCI Bridge"; +static const char pci_device_106b_0058[] = "U3L AGP Bridge"; +static const char pci_device_106b_0059[] = "U3H AGP Bridge"; +static const char pci_device_106b_0066[] = "Intrepid2 AGP Bridge"; +static const char pci_device_106b_0067[] = "Intrepid2 PCI Bridge"; +static const char pci_device_106b_0068[] = "Intrepid2 PCI Bridge"; +static const char pci_device_106b_0069[] = "Intrepid2 ATA/100"; +static const char pci_device_106b_006a[] = "Intrepid2 Firewire"; +static const char pci_device_106b_006b[] = "Intrepid2 GMAC (Sun GEM)"; +static const char pci_device_106b_1645[] = "Tigon3 Gigabit Ethernet NIC (BCM5701)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106c[] = "Hynix Semiconductor"; +static const char pci_device_106c_8801[] = "Dual Pentium ISA/PCI Motherboard"; +static const char pci_device_106c_8802[] = "PowerPC ISA/PCI Motherboard"; +static const char pci_device_106c_8803[] = "Dual Window Graphics Accelerator"; +static const char pci_device_106c_8804[] = "LAN Controller"; +static const char pci_device_106c_8805[] = "100-BaseT LAN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106d[] = "Sequent Computer Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106e[] = "DFI, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_106f[] = "City Gate Development Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1070[] = "Daewoo Telecom Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1071[] = "Mitac"; +static const char pci_device_1071_8160[] = "Mitac 8060B Mobile Platform"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1072[] = "GIT Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1073[] = "Yamaha Corporation"; +static const char pci_device_1073_0001[] = "3D GUI Accelerator"; +static const char pci_device_1073_0002[] = "YGV615 [RPA3 3D-Graphics Controller]"; +static const char pci_device_1073_0003[] = "YMF-740"; +static const char pci_device_1073_0004[] = "YMF-724"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0004_1073_0004[] = "YMF724-Based PCI Audio Adapter"; +#endif +static const char pci_device_1073_0005[] = "DS1 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0005_1073_0005[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_0006[] = "DS1 Audio"; +static const char pci_device_1073_0008[] = "DS1 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0008_1073_0008[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_000a[] = "DS1L Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_000a_1073_0004[] = "DS-XG PCI Audio CODEC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_000a_1073_000a[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_000c[] = "YMF-740C [DS-1L Audio Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_000c_107a_000c[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_000d[] = "YMF-724F [DS-1 Audio Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_000d_1073_000d[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_0010[] = "YMF-744B [DS-1S Audio Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0010_1073_0006[] = "DS-XG PCI Audio CODEC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0010_1073_0010[] = "DS-XG PCI Audio CODEC"; +#endif +static const char pci_device_1073_0012[] = "YMF-754 [DS-1E Audio Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_0012_1073_0012[] = "DS-XG PCI Audio Codec"; +#endif +static const char pci_device_1073_0020[] = "DS-1 Audio"; +static const char pci_device_1073_2000[] = "DS2416 Digital Mixing Card"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1073_2000_1073_2000[] = "DS2416 Digital Mixing Card"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1074[] = "NexGen Microsystems"; +static const char pci_device_1074_4e78[] = "82c500/1"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1075[] = "Advanced Integrations Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1076[] = "Chaintech Computer Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1077[] = "QLogic Corp."; +static const char pci_device_1077_1016[] = "ISP10160 Single Channel Ultra3 SCSI Processor"; +static const char pci_device_1077_1020[] = "ISP1020 Fast-wide SCSI"; +static const char pci_device_1077_1022[] = "ISP1022 Fast-wide SCSI"; +static const char pci_device_1077_1080[] = "ISP1080 SCSI Host Adapter"; +static const char pci_device_1077_1216[] = "ISP12160 Dual Channel Ultra3 SCSI Processor"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1077_1216_101e_8471[] = "QLA12160 on AMI MegaRAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1077_1216_101e_8493[] = "QLA12160 on AMI MegaRAID"; +#endif +static const char pci_device_1077_1240[] = "ISP1240 SCSI Host Adapter"; +static const char pci_device_1077_1280[] = "ISP1280 SCSI Host Adapter"; +static const char pci_device_1077_2020[] = "ISP2020A Fast!SCSI Basic Adapter"; +static const char pci_device_1077_2100[] = "QLA2100 64-bit Fibre Channel Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1077_2100_1077_0001[] = "QLA2100 64-bit Fibre Channel Adapter"; +#endif +static const char pci_device_1077_2200[] = "QLA2200 64-bit Fibre Channel Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1077_2200_1077_0002[] = "QLA2200"; +#endif +static const char pci_device_1077_2300[] = "QLA2300 64-bit Fibre Channel Adapter"; +static const char pci_device_1077_2312[] = "QLA2312 Fibre Channel Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1077_2312_103c_0131[] = "2Gb Fibre Channel - Single port [A7538A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1077_2312_103c_12ba[] = "2Gb Fibre Channel - Dual port [A6826A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1077_2322[] = "QLA2322 Fibre Channel Adapter"; +static const char pci_device_1077_2422[] = "QLA2422 Fibre Channel Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1077_2422_103c_12d7[] = "4Gb Fibre Channel [AB379A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1077_2422_103c_12dd[] = "4Gb Fibre Channel [AB429A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1077_2432[] = "QLA2432 Fibre Channel Adapter"; +static const char pci_device_1077_3010[] = "QLA3010 Network Adapter"; +static const char pci_device_1077_3022[] = "QLA3022 Network Adapter"; +static const char pci_device_1077_4010[] = "QLA4010 iSCSI TOE Adapter"; +static const char pci_device_1077_4022[] = "QLA4022 iSCSI TOE Adapter"; +static const char pci_device_1077_6312[] = "QLA6312 Fibre Channel Adapter"; +static const char pci_device_1077_6322[] = "QLA6322 Fibre Channel Adapter"; +#endif +static const char pci_vendor_1078[] = "Cyrix Corporation"; +static const char pci_device_1078_0000[] = "5510 [Grappa]"; +static const char pci_device_1078_0001[] = "PCI Master"; +static const char pci_device_1078_0002[] = "5520 [Cognac]"; +static const char pci_device_1078_0100[] = "5530 Legacy [Kahlua]"; +static const char pci_device_1078_0101[] = "5530 SMI [Kahlua]"; +static const char pci_device_1078_0102[] = "5530 IDE [Kahlua]"; +static const char pci_device_1078_0103[] = "5530 Audio [Kahlua]"; +static const char pci_device_1078_0104[] = "5530 Video [Kahlua]"; +static const char pci_device_1078_0400[] = "ZFMicro PCI Bridge"; +static const char pci_device_1078_0401[] = "ZFMicro Chipset SMI"; +static const char pci_device_1078_0402[] = "ZFMicro Chipset IDE"; +static const char pci_device_1078_0403[] = "ZFMicro Expansion Bus"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1079[] = "I-Bus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107a[] = "NetWorth"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107b[] = "Gateway 2000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107c[] = "LG Electronics [Lucky Goldstar Co. Ltd]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107d[] = "LeadTek Research Inc."; +static const char pci_device_107d_0000[] = "P86C850"; +static const char pci_device_107d_204d[] = "[GeForce 7800 GTX] Winfast PX7800 GTX TDH"; +static const char pci_device_107d_2134[] = "WinFast 3D S320 II"; +static const char pci_device_107d_2971[] = "[GeForce FX 5900] WinFast A350 TDH MyViVo"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107e[] = "Interphase Corporation"; +static const char pci_device_107e_0001[] = "5515 ATM Adapter [Flipper]"; +static const char pci_device_107e_0002[] = "100 VG AnyLan Controller"; +static const char pci_device_107e_0004[] = "5526 Fibre Channel Host Adapter"; +static const char pci_device_107e_0005[] = "x526 Fibre Channel Host Adapter"; +static const char pci_device_107e_0008[] = "5525/5575 ATM Adapter (155 Mbit) [Atlantic]"; +static const char pci_device_107e_9003[] = "5535-4P-BRI-ST"; +static const char pci_device_107e_9007[] = "5535-4P-BRI-U"; +static const char pci_device_107e_9008[] = "5535-1P-SR"; +static const char pci_device_107e_900c[] = "5535-1P-SR-ST"; +static const char pci_device_107e_900e[] = "5535-1P-SR-U"; +static const char pci_device_107e_9011[] = "5535-1P-PRI"; +static const char pci_device_107e_9013[] = "5535-2P-PRI"; +static const char pci_device_107e_9023[] = "5536-4P-BRI-ST"; +static const char pci_device_107e_9027[] = "5536-4P-BRI-U"; +static const char pci_device_107e_9031[] = "5536-1P-PRI"; +static const char pci_device_107e_9033[] = "5536-2P-PRI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_107f[] = "Data Technology Corporation"; +static const char pci_device_107f_0802[] = "SL82C105"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1080[] = "Contaq Microsystems"; +static const char pci_device_1080_0600[] = "82C599"; +static const char pci_device_1080_c691[] = "Cypress CY82C691"; +static const char pci_device_1080_c693[] = "82c693"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1081[] = "Supermac Technology"; +static const char pci_device_1081_0d47[] = "Radius PCI to NuBUS Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1082[] = "EFA Corporation of America"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1083[] = "Forex Computer Corporation"; +static const char pci_device_1083_0001[] = "FR710"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1084[] = "Parador"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1085[] = "Tulip Computers Int.B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1086[] = "J. Bond Computer Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1087[] = "Cache Computer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1088[] = "Microcomputer Systems (M) Son"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1089[] = "Data General Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_108a[] = "SBS Technologies"; +static const char pci_device_108a_0001[] = "VME Bridge Model 617"; +static const char pci_device_108a_0010[] = "VME Bridge Model 618"; +static const char pci_device_108a_0040[] = "dataBLIZZARD"; +static const char pci_device_108a_3000[] = "VME Bridge Model 2706"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_108c[] = "Oakleigh Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_108d[] = "Olicom"; +static const char pci_device_108d_0001[] = "Token-Ring 16/4 PCI Adapter (3136/3137)"; +static const char pci_device_108d_0002[] = "16/4 Token Ring"; +static const char pci_device_108d_0004[] = "RapidFire 3139 Token-Ring 16/4 PCI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0004_108d_0004[] = "OC-3139/3140 RapidFire Token-Ring 16/4 Adapter"; +#endif +static const char pci_device_108d_0005[] = "GoCard 3250 Token-Ring 16/4 CardBus PC Card"; +static const char pci_device_108d_0006[] = "OC-3530 RapidFire Token-Ring 100"; +static const char pci_device_108d_0007[] = "RapidFire 3141 Token-Ring 16/4 PCI Fiber Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0007_108d_0007[] = "OC-3141 RapidFire Token-Ring 16/4 Adapter"; +#endif +static const char pci_device_108d_0008[] = "RapidFire 3540 HSTR 100/16/4 PCI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0008_108d_0008[] = "OC-3540 RapidFire HSTR 100/16/4 Adapter"; +#endif +static const char pci_device_108d_0011[] = "OC-2315"; +static const char pci_device_108d_0012[] = "OC-2325"; +static const char pci_device_108d_0013[] = "OC-2183/2185"; +static const char pci_device_108d_0014[] = "OC-2326"; +static const char pci_device_108d_0019[] = "OC-2327/2250 10/100 Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0019_108d_0016[] = "OC-2327 Rapidfire 10/100 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_108d_0019_108d_0017[] = "OC-2250 GoCard 10/100 Ethernet Adapter"; +#endif +static const char pci_device_108d_0021[] = "OC-6151/6152 [RapidFire ATM 155]"; +static const char pci_device_108d_0022[] = "ATM Adapter"; +#endif +static const char pci_vendor_108e[] = "Sun Microsystems Computer Corp."; +static const char pci_device_108e_0001[] = "EBUS"; +static const char pci_device_108e_1000[] = "EBUS"; +static const char pci_device_108e_1001[] = "Happy Meal"; +static const char pci_device_108e_1100[] = "RIO EBUS"; +static const char pci_device_108e_1101[] = "RIO GEM"; +static const char pci_device_108e_1102[] = "RIO 1394"; +static const char pci_device_108e_1103[] = "RIO USB"; +static const char pci_device_108e_1648[] = "[bge] Gigabit Ethernet"; +static const char pci_device_108e_2bad[] = "GEM"; +static const char pci_device_108e_5000[] = "Simba Advanced PCI Bridge"; +static const char pci_device_108e_5043[] = "SunPCI Co-processor"; +static const char pci_device_108e_8000[] = "Psycho PCI Bus Module"; +static const char pci_device_108e_8001[] = "Schizo PCI Bus Module"; +static const char pci_device_108e_8002[] = "Schizo+ PCI Bus Module"; +static const char pci_device_108e_a000[] = "Ultra IIi"; +static const char pci_device_108e_a001[] = "Ultra IIe"; +static const char pci_device_108e_a801[] = "Tomatillo PCI Bus Module"; +static const char pci_device_108e_abba[] = "Cassini 10/100/1000"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_108f[] = "Systemsoft"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1090[] = "Compro Computer Services, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1091[] = "Intergraph Corporation"; +static const char pci_device_1091_0020[] = "3D graphics processor"; +static const char pci_device_1091_0021[] = "3D graphics processor w/Texturing"; +static const char pci_device_1091_0040[] = "3D graphics frame buffer"; +static const char pci_device_1091_0041[] = "3D graphics frame buffer"; +static const char pci_device_1091_0060[] = "Proprietary bus bridge"; +static const char pci_device_1091_00e4[] = "Powerstorm 4D50T"; +static const char pci_device_1091_0720[] = "Motion JPEG codec"; +static const char pci_device_1091_07a0[] = "Sun Expert3D-Lite Graphics Accelerator"; +static const char pci_device_1091_1091[] = "Sun Expert3D Graphics Accelerator"; +#endif +static const char pci_vendor_1092[] = "Diamond Multimedia Systems"; +static const char pci_device_1092_00a0[] = "Speedstar Pro SE"; +static const char pci_device_1092_00a8[] = "Speedstar 64"; +static const char pci_device_1092_0550[] = "Viper V550"; +static const char pci_device_1092_08d4[] = "Supra 2260 Modem"; +static const char pci_device_1092_094c[] = "SupraExpress 56i Pro"; +static const char pci_device_1092_1092[] = "Viper V330"; +static const char pci_device_1092_6120[] = "Maximum DVD"; +static const char pci_device_1092_8810[] = "Stealth SE"; +static const char pci_device_1092_8811[] = "Stealth 64/SE"; +static const char pci_device_1092_8880[] = "Stealth"; +static const char pci_device_1092_8881[] = "Stealth"; +static const char pci_device_1092_88b0[] = "Stealth 64"; +static const char pci_device_1092_88b1[] = "Stealth 64"; +static const char pci_device_1092_88c0[] = "Stealth 64"; +static const char pci_device_1092_88c1[] = "Stealth 64"; +static const char pci_device_1092_88d0[] = "Stealth 64"; +static const char pci_device_1092_88d1[] = "Stealth 64"; +static const char pci_device_1092_88f0[] = "Stealth 64"; +static const char pci_device_1092_88f1[] = "Stealth 64"; +static const char pci_device_1092_9999[] = "DMD-I0928-1 Monster sound sound chip"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1093[] = "National Instruments"; +static const char pci_device_1093_0160[] = "PCI-DIO-96"; +static const char pci_device_1093_0162[] = "PCI-MIO-16XE-50"; +static const char pci_device_1093_1150[] = "PCI-DIO-32HS High Speed Digital I/O Board"; +static const char pci_device_1093_1170[] = "PCI-MIO-16XE-10"; +static const char pci_device_1093_1180[] = "PCI-MIO-16E-1"; +static const char pci_device_1093_1190[] = "PCI-MIO-16E-4"; +static const char pci_device_1093_1310[] = "PCI-6602"; +static const char pci_device_1093_1330[] = "PCI-6031E"; +static const char pci_device_1093_1350[] = "PCI-6071E"; +static const char pci_device_1093_14e0[] = "PCI-6110"; +static const char pci_device_1093_14f0[] = "PCI-6111"; +static const char pci_device_1093_17d0[] = "PCI-6503"; +static const char pci_device_1093_1870[] = "PCI-6713"; +static const char pci_device_1093_1880[] = "PCI-6711"; +static const char pci_device_1093_18b0[] = "PCI-6052E"; +static const char pci_device_1093_2410[] = "PCI-6733"; +static const char pci_device_1093_2890[] = "PCI-6036E"; +static const char pci_device_1093_2a60[] = "PCI-6023E"; +static const char pci_device_1093_2a70[] = "PCI-6024E"; +static const char pci_device_1093_2a80[] = "PCI-6025E"; +static const char pci_device_1093_2c80[] = "PCI-6035E"; +static const char pci_device_1093_2ca0[] = "PCI-6034E"; +static const char pci_device_1093_70a9[] = "PCI-6528 (Digital I/O at 60V)"; +static const char pci_device_1093_70b8[] = "PCI-6251 [M Series - High Speed Multifunction DAQ]"; +static const char pci_device_1093_b001[] = "IMAQ-PCI-1408"; +static const char pci_device_1093_b011[] = "IMAQ-PXI-1408"; +static const char pci_device_1093_b021[] = "IMAQ-PCI-1424"; +static const char pci_device_1093_b031[] = "IMAQ-PCI-1413"; +static const char pci_device_1093_b041[] = "IMAQ-PCI-1407"; +static const char pci_device_1093_b051[] = "IMAQ-PXI-1407"; +static const char pci_device_1093_b061[] = "IMAQ-PCI-1411"; +static const char pci_device_1093_b071[] = "IMAQ-PCI-1422"; +static const char pci_device_1093_b081[] = "IMAQ-PXI-1422"; +static const char pci_device_1093_b091[] = "IMAQ-PXI-1411"; +static const char pci_device_1093_c801[] = "PCI-GPIB"; +static const char pci_device_1093_c831[] = "PCI-GPIB bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1094[] = "First International Computers [FIC]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1095[] = "Silicon Image, Inc."; +static const char pci_device_1095_0240[] = "Adaptec AAR-1210SA SATA HostRAID Controller"; +static const char pci_device_1095_0640[] = "PCI0640"; +static const char pci_device_1095_0643[] = "PCI0643"; +static const char pci_device_1095_0646[] = "PCI0646"; +static const char pci_device_1095_0647[] = "PCI0647"; +static const char pci_device_1095_0648[] = "PCI0648"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0648_1043_8025[] = "CUBX motherboard"; +#endif +static const char pci_device_1095_0649[] = "SiI 0649 Ultra ATA/100 PCI to ATA Host Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0649_0e11_005d[] = "Integrated Ultra ATA-100 Dual Channel Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0649_0e11_007e[] = "Integrated Ultra ATA-100 IDE RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0649_101e_0649[] = "AMI MegaRAID IDE 100 Controller"; +#endif +static const char pci_device_1095_0650[] = "PBC0650A"; +static const char pci_device_1095_0670[] = "USB0670"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0670_1095_0670[] = "USB0670"; +#endif +static const char pci_device_1095_0673[] = "USB0673"; +static const char pci_device_1095_0680[] = "PCI0680 Ultra ATA-133 Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_0680_1095_3680[] = "Winic W-680 (Silicon Image 680 based)"; +#endif +static const char pci_device_1095_3112[] = "SiI 3112 [SATALink/SATARaid] Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3112_1095_3112[] = "SiI 3112 SATALink Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3112_1095_6112[] = "SiI 3112 SATARaid Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3112_9005_0250[] = "SATAConnect 1205SA Host Controller"; +#endif +static const char pci_device_1095_3114[] = "SiI 3114 [SATALink/SATARaid] Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3114_1095_3114[] = "SiI 3114 SATALink Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3114_1095_6114[] = "SiI 3114 SATARaid Controller"; +#endif +static const char pci_device_1095_3124[] = "SiI 3124 PCI-X Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3124_1095_3124[] = "SiI 3124 PCI-X Serial ATA Controller"; +#endif +static const char pci_device_1095_3132[] = "SiI 3132 Serial ATA Raid II Controller"; +static const char pci_device_1095_3512[] = "SiI 3512 [SATALink/SATARaid] Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3512_1095_3512[] = "SiI 3512 SATALink Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1095_3512_1095_6512[] = "SiI 3512 SATARaid Controller"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1096[] = "Alacron"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1097[] = "Appian Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1098[] = "Quantum Designs (H.K.) Ltd"; +static const char pci_device_1098_0001[] = "QD-8500"; +static const char pci_device_1098_0002[] = "QD-8580"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1099[] = "Samsung Electronics Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109a[] = "Packard Bell"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109b[] = "Gemlight Computer Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109c[] = "Megachips Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109d[] = "Zida Technologies Ltd."; +#endif +static const char pci_vendor_109e[] = "Brooktree Corporation"; +static const char pci_device_109e_032e[] = "Bt878 Video Capture"; +static const char pci_device_109e_0350[] = "Bt848 Video Capture"; +static const char pci_device_109e_0351[] = "Bt849A Video capture"; +static const char pci_device_109e_0369[] = "Bt878 Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0369_1002_0001[] = "TV-Wonder"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0369_1002_0003[] = "TV-Wonder/VE"; +#endif +static const char pci_device_109e_036c[] = "Bt879(?) Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036c_13e9_0070[] = "Win/TV (Video Section)"; +#endif +static const char pci_device_109e_036e[] = "Bt878 Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_0070_13eb[] = "WinTV Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_0070_ff01[] = "Viewcast Osprey 200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_0071_0101[] = "DigiTV PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_107d_6606[] = "WinFast TV 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_11bd_0012[] = "PCTV pro (TV + FM stereo receiver)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_11bd_001c[] = "PCTV Sat (DBC receiver)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_127a_0001[] = "Bt878 Mediastream Controller NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_127a_0002[] = "Bt878 Mediastream Controller PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_127a_0003[] = "Bt878a Mediastream Controller PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_127a_0048[] = "Bt878/832 Mediastream Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_144f_3000[] = "MagicTView CPH060 - Video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1461_0002[] = "TV98 Series (TV/No FM/Remote)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1461_0003[] = "AverMedia UltraTV PCI 350"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1461_0004[] = "AVerTV WDM Video Capture"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1461_0761[] = "AverTV DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1461_0771[] = "AverMedia AVerTV DVB-T 771"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_14f1_0001[] = "Bt878 Mediastream Controller NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_14f1_0002[] = "Bt878 Mediastream Controller PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_14f1_0003[] = "Bt878a Mediastream Controller PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_14f1_0048[] = "Bt878/832 Mediastream Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1822_0001[] = "VisionPlus DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1851_1850[] = "FlyVideo'98 - Video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1851_1851[] = "FlyVideo II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_1852_1852[] = "FlyVideo'98 - Video (with FM Tuner)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_18ac_d500[] = "DViCO FusionHDTV5 Lite"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_270f_fc00[] = "Digitop DTT-1000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036e_bd11_1200[] = "PCTV pro (TV + FM stereo receiver)"; +#endif +static const char pci_device_109e_036f[] = "Bt879 Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0044[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0122[] = "Bt879 Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0144[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0222[] = "Bt879 Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0244[] = "Bt879a Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0322[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_0422[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1122[] = "Bt879 Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1222[] = "Bt879 Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1322[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1522[] = "Bt879a Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1622[] = "Bt879a Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_127a_1722[] = "Bt879a Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0044[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0122[] = "Bt879 Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0144[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0222[] = "Bt879 Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0244[] = "Bt879a Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0322[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_0422[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1122[] = "Bt879 Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1222[] = "Bt879 Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1322[] = "Bt879 Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1522[] = "Bt879a Video Capture PAL I"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1622[] = "Bt879a Video Capture PAL BG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_14f1_1722[] = "Bt879a Video Capture NTSC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_1851_1850[] = "FlyVideo'98 - Video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_1851_1851[] = "FlyVideo II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_036f_1852_1852[] = "FlyVideo'98 - Video (with FM Tuner)"; +#endif +static const char pci_device_109e_0370[] = "Bt880 Video Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0370_1851_1850[] = "FlyVideo'98"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0370_1851_1851[] = "FlyVideo'98 EZ - video"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0370_1852_1852[] = "FlyVideo'98 (with FM Tuner)"; +#endif +static const char pci_device_109e_0878[] = "Bt878 Audio Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_0070_13eb[] = "WinTV Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_0070_ff01[] = "Viewcast Osprey 200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_0071_0101[] = "DigiTV PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1002_0001[] = "TV-Wonder"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1002_0003[] = "TV-Wonder/VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_11bd_0012[] = "PCTV pro (TV + FM stereo receiver, audio section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_11bd_001c[] = "PCTV Sat (DBC receiver)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_127a_0001[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_127a_0002[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_127a_0003[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_127a_0048[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_13e9_0070[] = "Win/TV (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_144f_3000[] = "MagicTView CPH060 - Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1461_0002[] = "Avermedia PCTV98 Audio Capture"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1461_0004[] = "AVerTV WDM Audio Capture"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1461_0761[] = "AVerTV DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1461_0771[] = "AverMedia AVerTV DVB-T 771"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_14f1_0001[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_14f1_0002[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_14f1_0003[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_14f1_0048[] = "Bt878 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_1822_0001[] = "VisionPlus DVB Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_18ac_d500[] = "DViCO FusionHDTV5 Lite"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_270f_fc00[] = "Digitop DTT-1000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0878_bd11_1200[] = "PCTV pro (TV + FM stereo receiver, audio section)"; +#endif +static const char pci_device_109e_0879[] = "Bt879 Audio Capture"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0044[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0122[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0144[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0222[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0244[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0322[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_0422[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1122[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1222[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1322[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1522[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1622[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_127a_1722[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0044[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0122[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0144[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0222[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0244[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0322[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_0422[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1122[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1222[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1322[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1522[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1622[] = "Bt879 Video Capture (Audio Section)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_109e_0879_14f1_1722[] = "Bt879 Video Capture (Audio Section)"; +#endif +static const char pci_device_109e_0880[] = "Bt880 Audio Capture"; +static const char pci_device_109e_2115[] = "BtV 2115 Mediastream controller"; +static const char pci_device_109e_2125[] = "BtV 2125 Mediastream controller"; +static const char pci_device_109e_2164[] = "BtV 2164"; +static const char pci_device_109e_2165[] = "BtV 2165"; +static const char pci_device_109e_8230[] = "Bt8230 ATM Segment/Reassembly Ctrlr (SRC)"; +static const char pci_device_109e_8472[] = "Bt8472"; +static const char pci_device_109e_8474[] = "Bt8474"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_109f[] = "Trigem Computer Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a0[] = "Meidensha Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a1[] = "Juko Electronics Ind. Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a2[] = "Quantum Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a3[] = "Everex Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a4[] = "Globe Manufacturing Sales"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a5[] = "Smart Link Ltd."; +static const char pci_device_10a5_3052[] = "SmartPCI562 56K Modem"; +static const char pci_device_10a5_5449[] = "SmartPCI561 modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a6[] = "Informtech Industrial Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a7[] = "Benchmarq Microelectronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a8[] = "Sierra Semiconductor"; +static const char pci_device_10a8_0000[] = "STB Horizon 64"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10a9[] = "Silicon Graphics, Inc."; +static const char pci_device_10a9_0001[] = "Crosstalk to PCI Bridge"; +static const char pci_device_10a9_0002[] = "Linc I/O controller"; +static const char pci_device_10a9_0003[] = "IOC3 I/O controller"; +static const char pci_device_10a9_0004[] = "O2 MACE"; +static const char pci_device_10a9_0005[] = "RAD Audio"; +static const char pci_device_10a9_0006[] = "HPCEX"; +static const char pci_device_10a9_0007[] = "RPCEX"; +static const char pci_device_10a9_0008[] = "DiVO VIP"; +static const char pci_device_10a9_0009[] = "AceNIC Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10a9_0009_10a9_8002[] = "AceNIC Gigabit Ethernet"; +#endif +static const char pci_device_10a9_0010[] = "AMP Video I/O"; +static const char pci_device_10a9_0011[] = "GRIP"; +static const char pci_device_10a9_0012[] = "SGH PSHAC GSN"; +static const char pci_device_10a9_1001[] = "Magic Carpet"; +static const char pci_device_10a9_1002[] = "Lithium"; +static const char pci_device_10a9_1003[] = "Dual JPEG 1"; +static const char pci_device_10a9_1004[] = "Dual JPEG 2"; +static const char pci_device_10a9_1005[] = "Dual JPEG 3"; +static const char pci_device_10a9_1006[] = "Dual JPEG 4"; +static const char pci_device_10a9_1007[] = "Dual JPEG 5"; +static const char pci_device_10a9_1008[] = "Cesium"; +static const char pci_device_10a9_100a[] = "IOC4 I/O controller"; +static const char pci_device_10a9_2001[] = "Fibre Channel"; +static const char pci_device_10a9_2002[] = "ASDE"; +static const char pci_device_10a9_4001[] = "TIO-CE PCI Express Bridge"; +static const char pci_device_10a9_4002[] = "TIO-CE PCI Express Port"; +static const char pci_device_10a9_8001[] = "O2 1394"; +static const char pci_device_10a9_8002[] = "G-net NT"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10aa[] = "ACC Microelectronics"; +static const char pci_device_10aa_0000[] = "ACCM 2188"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ab[] = "Digicom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ac[] = "Honeywell IAC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ad[] = "Symphony Labs"; +static const char pci_device_10ad_0001[] = "W83769F"; +static const char pci_device_10ad_0003[] = "SL82C103"; +static const char pci_device_10ad_0005[] = "SL82C105"; +static const char pci_device_10ad_0103[] = "SL82c103"; +static const char pci_device_10ad_0105[] = "SL82c105"; +static const char pci_device_10ad_0565[] = "W83C553"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ae[] = "Cornerstone Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10af[] = "Micro Computer Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b0[] = "CardExpert Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b1[] = "Cabletron Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b2[] = "Raytheon Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b3[] = "Databook Inc"; +static const char pci_device_10b3_3106[] = "DB87144"; +static const char pci_device_10b3_b106[] = "DB87144"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b4[] = "STB Systems Inc"; +static const char pci_device_10b4_1b1d[] = "Velocity 128 3D"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b4_1b1d_10b4_237e[] = "Velocity 4400"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b5[] = "PLX Technology, Inc."; +static const char pci_device_10b5_0001[] = "i960 PCI bus interface"; +static const char pci_device_10b5_1042[] = "Brandywine / jxi2, Inc. - PMC-SyncClock32, IRIG A & B, Nasa 36"; +static const char pci_device_10b5_1076[] = "VScom 800 8 port serial adaptor"; +static const char pci_device_10b5_1077[] = "VScom 400 4 port serial adaptor"; +static const char pci_device_10b5_1078[] = "VScom 210 2 port serial and 1 port parallel adaptor"; +static const char pci_device_10b5_1103[] = "VScom 200 2 port serial adaptor"; +static const char pci_device_10b5_1146[] = "VScom 010 1 port parallel adaptor"; +static const char pci_device_10b5_1147[] = "VScom 020 2 port parallel adaptor"; +static const char pci_device_10b5_2540[] = "IXXAT CAN-Interface PC-I 04/PCI"; +static const char pci_device_10b5_2724[] = "Thales PCSM Security Card"; +static const char pci_device_10b5_6540[] = "PCI6540/6466 PCI-PCI bridge (transparent mode)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_6540_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_10b5_6541[] = "PCI6540/6466 PCI-PCI bridge (non-transparent mode, primary side)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_6541_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_10b5_6542[] = "PCI6540/6466 PCI-PCI bridge (non-transparent mode, secondary side)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_6542_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_10b5_8111[] = "PEX 8111 PCI Express-to-PCI Bridge"; +static const char pci_device_10b5_8114[] = "PEX 8114 PCI Express-to-PCI/PCI-X Bridge"; +static const char pci_device_10b5_8516[] = "PEX 8516 Versatile PCI Express Switch"; +static const char pci_device_10b5_8532[] = "PEX 8532 Versatile PCI Express Switch"; +static const char pci_device_10b5_9030[] = "PCI <-> IOBus Bridge Hot Swap"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_2862[] = "Alpermann+Velte PCL PCI LV (3V/5V): Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_2906[] = "Alpermann+Velte PCI TS (3V/5V): Time Synchronisation Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_2940[] = "Alpermann+Velte PCL PCI D (3V/5V): Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_2977[] = "IXXAT iPC-I XC16/PCI CAN Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_2978[] = "SH ARC-PCIu SOHARD ARCNET card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_3025[] = "Alpermann+Velte PCL PCI L (3V/5V): Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_10b5_3068[] = "Alpermann+Velte PCL PCI HD (3V/5V): Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_1397_3136[] = "4xS0-ISDN PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_1397_3137[] = "S2M-E1-ISDN PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_1518_0200[] = "Kontron ThinkIO-C"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_15ed_1002[] = "MCCS 8-port Serial Hot Swap"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9030_15ed_1003[] = "MCCS 16-port Serial Hot Swap"; +#endif +static const char pci_device_10b5_9036[] = "9036"; +static const char pci_device_10b5_9050[] = "PCI <-> IOBus Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_1067[] = "IXXAT CAN i165"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_1172[] = "IK220 (Heidenhain)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_2036[] = "SatPak GPS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_2221[] = "Alpermann+Velte PCL PCI LV: Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_2273[] = "SH ARC-PCI SOHARD ARCNET card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_2431[] = "Alpermann+Velte PCL PCI D: Timecode Reader Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_2905[] = "Alpermann+Velte PCI TS: Time Synchronisation Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_10b5_9050[] = "PCI-I04 PCI Passive PC/CAN Interface"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1498_0362[] = "TPMC866 8 Channel Serial Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0001[] = "RockForce 4 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0002[] = "RockForce 2 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0003[] = "RockForce 6 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0004[] = "RockForce 8 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0010[] = "RockForce2000 4 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_1522_0020[] = "RockForce2000 2 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_15ed_1000[] = "Macrolink MCCS 8-port Serial"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_15ed_1001[] = "Macrolink MCCS 16-port Serial"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_15ed_1002[] = "Macrolink MCCS 8-port Serial Hot Swap"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_15ed_1003[] = "Macrolink MCCS 16-port Serial Hot Swap"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_5654_2036[] = "OpenSwitch 6 Telephony card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_5654_3132[] = "OpenSwitch 12 Telephony card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_5654_5634[] = "OpenLine4 Telephony Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d531_c002[] = "PCIntelliCAN 2xSJA1000 CAN bus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4006[] = "EX-4006 1P"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4008[] = "EX-4008 1P EPP/ECP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4014[] = "EX-4014 2P"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4018[] = "EX-4018 3P EPP/ECP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4025[] = "EX-4025 1S(16C550) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4027[] = "EX-4027 1S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4028[] = "EX-4028 1S(16C850) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4036[] = "EX-4036 2S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4037[] = "EX-4037 2S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4038[] = "EX-4038 2S(16C850) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4052[] = "EX-4052 1S(16C550) RS-422/485"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4053[] = "EX-4053 2S(16C550) RS-422/485"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4055[] = "EX-4055 4S(16C550) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4058[] = "EX-4055 4S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4065[] = "EX-4065 8S(16C550) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4068[] = "EX-4068 8S(16C650) RS-232"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9050_d84d_4078[] = "EX-4078 2S(16C552) RS-232+1P"; +#endif +static const char pci_device_10b5_9054[] = "PCI <-> IOBus Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_10b5_2455[] = "Wessex Techology PHIL-PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_10b5_2696[] = "Innes Corp AM Radcap card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_10b5_2717[] = "Innes Corp Auricon card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_10b5_2844[] = "Innes Corp TVS Encoder card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_12c7_4001[] = "Intel Dialogic DM/V960-4T1 PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_12d9_0002[] = "PCI Prosody Card rev 1.5"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0011[] = "PIKA PrimeNet MM PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0012[] = "PIKA PrimeNet MM cPCI 8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0013[] = "PIKA PrimeNet MM cPCI 8 (without CAS Signaling)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0014[] = "PIKA PrimeNet MM cPCI 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0015[] = "PIKA Daytona MM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9054_16df_0016[] = "PIKA InLine MM"; +#endif +static const char pci_device_10b5_9056[] = "Francois"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9056_10b5_2979[] = "CellinkBlade 11 - CPCI board VoATM AAL1"; +#endif +static const char pci_device_10b5_9060[] = "9060"; +static const char pci_device_10b5_906d[] = "9060SD"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_906d_125c_0640[] = "Aries 16000P"; +#endif +static const char pci_device_10b5_906e[] = "9060ES"; +static const char pci_device_10b5_9080[] = "9080"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_103c_10eb[] = "(Agilent) E2777B 83K Series Optical Communication Interface"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_103c_10ec[] = "(Agilent) E6978-66442 PCI CIC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_10b5_1123[] = "Sectra KK631 encryption board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_10b5_9080[] = "9080 [real subsystem ID not set]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_129d_0002[] = "Aculab PCI Prosidy card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_12d9_0002[] = "PCI Prosody Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_12df_4422[] = "4422PCI [Do-All Telemetry Data Aquisition System]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9080_1517_000b[] = "ECSG-1R3ADC-PMC Clock synthesizer"; +#endif +static const char pci_device_10b5_9656[] = "PCI <-> IOBus Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9656_1517_000f[] = "ECDR-GC314-PMC Receiver"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9656_1885_0700[] = "Tsunami FPGA PMC with Altera Stratix S40"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b5_9656_1885_0701[] = "Tsunami FPGA PMC with Altera Stratix S30"; +#endif +static const char pci_device_10b5_bb04[] = "B&B 3PCIOSD1A Isolated PCI Serial"; +static const char pci_device_10b5_c001[] = "CronyxOmega-PCI (8-port RS232)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b6[] = "Madge Networks"; +static const char pci_device_10b6_0001[] = "Smart 16/4 PCI Ringnode"; +static const char pci_device_10b6_0002[] = "Smart 16/4 PCI Ringnode Mk2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0002_10b6_0002[] = "Smart 16/4 PCI Ringnode Mk2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0002_10b6_0006[] = "16/4 CardBus Adapter"; +#endif +static const char pci_device_10b6_0003[] = "Smart 16/4 PCI Ringnode Mk3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0003_0e11_b0fd[] = "Compaq NC4621 PCI, 4/16, WOL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0003_10b6_0003[] = "Smart 16/4 PCI Ringnode Mk3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0003_10b6_0007[] = "Presto PCI Plus Adapter"; +#endif +static const char pci_device_10b6_0004[] = "Smart 16/4 PCI Ringnode Mk1"; +static const char pci_device_10b6_0006[] = "16/4 Cardbus Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0006_10b6_0006[] = "16/4 CardBus Adapter"; +#endif +static const char pci_device_10b6_0007[] = "Presto PCI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0007_10b6_0007[] = "Presto PCI"; +#endif +static const char pci_device_10b6_0009[] = "Smart 100/16/4 PCI-HS Ringnode"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_0009_10b6_0009[] = "Smart 100/16/4 PCI-HS Ringnode"; +#endif +static const char pci_device_10b6_000a[] = "Smart 100/16/4 PCI Ringnode"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_000a_10b6_000a[] = "Smart 100/16/4 PCI Ringnode"; +#endif +static const char pci_device_10b6_000b[] = "16/4 CardBus Adapter Mk2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_000b_10b6_0008[] = "16/4 CardBus Adapter Mk2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_000b_10b6_000b[] = "16/4 Cardbus Adapter Mk2"; +#endif +static const char pci_device_10b6_000c[] = "RapidFire 3140V2 16/4 TR Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b6_000c_10b6_000c[] = "RapidFire 3140V2 16/4 TR Adapter"; +#endif +static const char pci_device_10b6_1000[] = "Collage 25/155 ATM Client Adapter"; +static const char pci_device_10b6_1001[] = "Collage 155 ATM Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b7[] = "3Com Corporation"; +static const char pci_device_10b7_0001[] = "3c985 1000BaseSX (SX/TX)"; +static const char pci_device_10b7_0013[] = "AR5212 802.11abg NIC (3CRDAG675)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_0013_10b7_2031[] = "3CRDAG675 11a/b/g Wireless PCI Adapter"; +#endif +static const char pci_device_10b7_0910[] = "3C910-A01"; +static const char pci_device_10b7_1006[] = "MINI PCI type 3B Data Fax Modem"; +static const char pci_device_10b7_1007[] = "Mini PCI 56k Winmodem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_1007_10b7_615c[] = "Mini PCI 56K Modem"; +#endif +static const char pci_device_10b7_1201[] = "3c982-TXM 10/100baseTX Dual Port A [Hydra]"; +static const char pci_device_10b7_1202[] = "3c982-TXM 10/100baseTX Dual Port B [Hydra]"; +static const char pci_device_10b7_1700[] = "3c940 10/100/1000Base-T [Marvell]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_1700_1043_80eb[] = "A7V600/P4P800/K8V motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_1700_10b7_0010[] = "3C940 Gigabit LOM Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_1700_10b7_0020[] = "3C941 Gigabit LOM Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_1700_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +static const char pci_device_10b7_3390[] = "3c339 TokenLink Velocity"; +static const char pci_device_10b7_3590[] = "3c359 TokenLink Velocity XL"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_3590_10b7_3590[] = "TokenLink Velocity XL Adapter (3C359/359B)"; +#endif +static const char pci_device_10b7_4500[] = "3c450 HomePNA [Tornado]"; +static const char pci_device_10b7_5055[] = "3c555 Laptop Hurricane"; +static const char pci_device_10b7_5057[] = "3c575 Megahertz 10/100 LAN CardBus [Boomerang]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_5057_10b7_5a57[] = "3C575 Megahertz 10/100 LAN Cardbus PC Card"; +#endif +static const char pci_device_10b7_5157[] = "3cCFE575BT Megahertz 10/100 LAN CardBus [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_5157_10b7_5b57[] = "3C575 Megahertz 10/100 LAN Cardbus PC Card"; +#endif +static const char pci_device_10b7_5257[] = "3cCFE575CT CardBus [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_5257_10b7_5c57[] = "FE575C-3Com 10/100 LAN CardBus-Fast Ethernet"; +#endif +static const char pci_device_10b7_5900[] = "3c590 10BaseT [Vortex]"; +static const char pci_device_10b7_5920[] = "3c592 EISA 10mbps Demon/Vortex"; +static const char pci_device_10b7_5950[] = "3c595 100BaseTX [Vortex]"; +static const char pci_device_10b7_5951[] = "3c595 100BaseT4 [Vortex]"; +static const char pci_device_10b7_5952[] = "3c595 100Base-MII [Vortex]"; +static const char pci_device_10b7_5970[] = "3c597 EISA Fast Demon/Vortex"; +static const char pci_device_10b7_5b57[] = "3c595 Megahertz 10/100 LAN CardBus [Boomerang]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_5b57_10b7_5b57[] = "3C575 Megahertz 10/100 LAN Cardbus PC Card"; +#endif +static const char pci_device_10b7_6000[] = "3CRSHPW796 [OfficeConnect Wireless CardBus]"; +static const char pci_device_10b7_6001[] = "3com 3CRWE154G72 [Office Connect Wireless LAN Adapter]"; +static const char pci_device_10b7_6055[] = "3c556 Hurricane CardBus [Cyclone]"; +static const char pci_device_10b7_6056[] = "3c556B CardBus [Tornado]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6056_10b7_6556[] = "10/100 Mini PCI Ethernet Adapter"; +#endif +static const char pci_device_10b7_6560[] = "3cCFE656 CardBus [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6560_10b7_656a[] = "3CCFEM656 10/100 LAN+56K Modem CardBus"; +#endif +static const char pci_device_10b7_6561[] = "3cCFEM656 10/100 LAN+56K Modem CardBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6561_10b7_656b[] = "3CCFEM656 10/100 LAN+56K Modem CardBus"; +#endif +static const char pci_device_10b7_6562[] = "3cCFEM656B 10/100 LAN+Winmodem CardBus [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6562_10b7_656b[] = "3CCFEM656B 10/100 LAN+56K Modem CardBus"; +#endif +static const char pci_device_10b7_6563[] = "3cCFEM656B 10/100 LAN+56K Modem CardBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_6563_10b7_656b[] = "3CCFEM656 10/100 LAN+56K Modem CardBus"; +#endif +static const char pci_device_10b7_6564[] = "3cXFEM656C 10/100 LAN+Winmodem CardBus [Tornado]"; +static const char pci_device_10b7_7646[] = "3cSOHO100-TX Hurricane"; +static const char pci_device_10b7_7770[] = "3CRWE777 PCI(PLX) Wireless Adaptor [Airconnect]"; +static const char pci_device_10b7_7940[] = "3c803 FDDILink UTP Controller"; +static const char pci_device_10b7_7980[] = "3c804 FDDILink SAS Controller"; +static const char pci_device_10b7_7990[] = "3c805 FDDILink DAS Controller"; +static const char pci_device_10b7_80eb[] = "3c940B 10/100/1000Base-T"; +static const char pci_device_10b7_8811[] = "Token ring"; +static const char pci_device_10b7_9000[] = "3c900 10BaseT [Boomerang]"; +static const char pci_device_10b7_9001[] = "3c900 10Mbps Combo [Boomerang]"; +static const char pci_device_10b7_9004[] = "3c900B-TPO Etherlink XL [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9004_10b7_9004[] = "3C900B-TPO Etherlink XL TPO 10Mb"; +#endif +static const char pci_device_10b7_9005[] = "3c900B-Combo Etherlink XL [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9005_10b7_9005[] = "3C900B-Combo Etherlink XL Combo"; +#endif +static const char pci_device_10b7_9006[] = "3c900B-TPC Etherlink XL [Cyclone]"; +static const char pci_device_10b7_900a[] = "3c900B-FL 10base-FL [Cyclone]"; +static const char pci_device_10b7_9050[] = "3c905 100BaseTX [Boomerang]"; +static const char pci_device_10b7_9051[] = "3c905 100BaseT4 [Boomerang]"; +static const char pci_device_10b7_9054[] = "3C905B-TX Fast Etherlink XL PCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9054_10b7_9054[] = "3C905B-TX Fast Etherlink XL PCI"; +#endif +static const char pci_device_10b7_9055[] = "3c905B 100BaseTX [Cyclone]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0080[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0081[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0082[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0083[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0084[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0085[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0086[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0087[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0088[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0089[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0090[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0091[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0092[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0093[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0094[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0095[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0096[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0097[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0098[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_1028_0099[] = "3C905B Fast Etherlink XL 10/100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9055_10b7_9055[] = "3C905B Fast Etherlink XL 10/100"; +#endif +static const char pci_device_10b7_9056[] = "3c905B-T4 Fast EtherLink XL [Cyclone]"; +static const char pci_device_10b7_9058[] = "3c905B Deluxe Etherlink 10/100/BNC [Cyclone]"; +static const char pci_device_10b7_905a[] = "3c905B-FX Fast Etherlink XL FX 100baseFx [Cyclone]"; +static const char pci_device_10b7_9200[] = "3c905C-TX/TX-M [Tornado]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_1028_0095[] = "3C920 Integrated Fast Ethernet Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_1028_0097[] = "3C920 Integrated Fast Ethernet Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_1028_00fe[] = "Optiplex GX240"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_1028_012a[] = "3C920 Integrated Fast Ethernet Controller [Latitude C640]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_10b7_1000[] = "3C905C-TX Fast Etherlink for PC Management NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_10b7_7000[] = "10/100 Mini PCI Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9200_10f1_2466[] = "Tiger MPX S2466 (3C920 Integrated Fast Ethernet Controller)"; +#endif +static const char pci_device_10b7_9201[] = "3C920B-EMB Integrated Fast Ethernet Controller [Tornado]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9201_1043_80ab[] = "A7N8X Deluxe onboard 3C920B-EMB Integrated Fast Ethernet Controller"; +#endif +static const char pci_device_10b7_9202[] = "3Com 3C920B-EMB-WNM Integrated Fast Ethernet Controller"; +static const char pci_device_10b7_9210[] = "3C920B-EMB-WNM Integrated Fast Ethernet Controller"; +static const char pci_device_10b7_9300[] = "3CSOHO100B-TX 910-A01 [tulip]"; +static const char pci_device_10b7_9800[] = "3c980-TX Fast Etherlink XL Server Adapter [Cyclone]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9800_10b7_9800[] = "3c980-TX Fast Etherlink XL Server Adapter"; +#endif +static const char pci_device_10b7_9805[] = "3c980-C 10/100baseTX NIC [Python-T]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9805_10b7_1201[] = "EtherLink Server 10/100 Dual Port A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9805_10b7_1202[] = "EtherLink Server 10/100 Dual Port B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9805_10b7_9805[] = "3c980 10/100baseTX NIC [Python-T]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9805_10f1_2462[] = "Thunder K7 S2462"; +#endif +static const char pci_device_10b7_9900[] = "3C990-TX [Typhoon]"; +static const char pci_device_10b7_9902[] = "3CR990-TX-95 [Typhoon 56-bit]"; +static const char pci_device_10b7_9903[] = "3CR990-TX-97 [Typhoon 168-bit]"; +static const char pci_device_10b7_9904[] = "3C990B-TX-M/3C990BSVR [Typhoon2]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9904_10b7_1000[] = "3CR990B-TX-M [Typhoon2]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9904_10b7_2000[] = "3CR990BSVR [Typhoon2 Server]"; +#endif +static const char pci_device_10b7_9905[] = "3CR990-FX-95/97/95 [Typhon Fiber]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9905_10b7_1101[] = "3CR990-FX-95 [Typhoon Fiber 56-bit]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9905_10b7_1102[] = "3CR990-FX-97 [Typhoon Fiber 168-bit]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9905_10b7_2101[] = "3CR990-FX-95 Server [Typhoon Fiber 56-bit]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b7_9905_10b7_2102[] = "3CR990-FX-97 Server [Typhoon Fiber 168-bit]"; +#endif +static const char pci_device_10b7_9908[] = "3CR990SVR95 [Typhoon Server 56-bit]"; +static const char pci_device_10b7_9909[] = "3CR990SVR97 [Typhoon Server 168-bit]"; +static const char pci_device_10b7_990a[] = "3C990SVR [Typhoon Server]"; +static const char pci_device_10b7_990b[] = "3C990SVR [Typhoon Server]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b8[] = "Standard Microsystems Corp [SMC]"; +static const char pci_device_10b8_0005[] = "83c170 EPIC/100 Fast Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_1055_e000[] = "LANEPIC 10/100 [EVB171Q-PCI]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_1055_e002[] = "LANEPIC 10/100 [EVB171G-PCI]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a011[] = "EtherPower II 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a014[] = "EtherPower II 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a015[] = "EtherPower II 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a016[] = "EtherPower II 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0005_10b8_a017[] = "EtherPower II 10/100"; +#endif +static const char pci_device_10b8_0006[] = "83c175 EPIC/100 Fast Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_1055_e100[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_1055_e102[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_1055_e300[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_1055_e302[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_10b8_a012[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_13a2_8002[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b8_0006_13a2_8006[] = "LANEPIC Cardbus Fast Ethernet Adapter"; +#endif +static const char pci_device_10b8_1000[] = "FDC 37c665"; +static const char pci_device_10b8_1001[] = "FDC 37C922"; +static const char pci_device_10b8_2802[] = "SMC2802W [EZ Connect g]"; +static const char pci_device_10b8_a011[] = "83C170QF"; +static const char pci_device_10b8_b106[] = "SMC34C90"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10b9[] = "ALi Corporation"; +static const char pci_device_10b9_0101[] = "CMI8338/C3DX PCI Audio Device"; +static const char pci_device_10b9_0111[] = "C-Media CMI8738/C3DX Audio Device (OEM)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_0111_10b9_0111[] = "C-Media CMI8738/C3DX Audio Device (OEM)"; +#endif +static const char pci_device_10b9_0780[] = "Multi-IO Card"; +static const char pci_device_10b9_0782[] = "Multi-IO Card"; +static const char pci_device_10b9_1435[] = "M1435"; +static const char pci_device_10b9_1445[] = "M1445"; +static const char pci_device_10b9_1449[] = "M1449"; +static const char pci_device_10b9_1451[] = "M1451"; +static const char pci_device_10b9_1461[] = "M1461"; +static const char pci_device_10b9_1489[] = "M1489"; +static const char pci_device_10b9_1511[] = "M1511 [Aladdin]"; +static const char pci_device_10b9_1512[] = "M1512 [Aladdin]"; +static const char pci_device_10b9_1513[] = "M1513 [Aladdin]"; +static const char pci_device_10b9_1521[] = "M1521 [Aladdin III]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_1521_10b9_1521[] = "ALI M1521 Aladdin III CPU Bridge"; +#endif +static const char pci_device_10b9_1523[] = "M1523"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_1523_10b9_1523[] = "ALI M1523 ISA Bridge"; +#endif +static const char pci_device_10b9_1531[] = "M1531 [Aladdin IV]"; +static const char pci_device_10b9_1533[] = "M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_1533_1014_053b[] = "ThinkPad R40e (2684-HVG) PCI to ISA Bridge"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_1533_10b9_1533[] = "ALi M1533 Aladdin IV/V ISA Bridge"; +#endif +static const char pci_device_10b9_1541[] = "M1541"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_1541_10b9_1541[] = "ALI M1541 Aladdin V/V+ AGP System Controller"; +#endif +static const char pci_device_10b9_1543[] = "M1543"; +static const char pci_device_10b9_1563[] = "M1563 HyperTransport South Bridge"; +static const char pci_device_10b9_1573[] = "PCI to LPC Controller"; +static const char pci_device_10b9_1621[] = "M1621"; +static const char pci_device_10b9_1631[] = "ALI M1631 PCI North Bridge Aladdin Pro III"; +static const char pci_device_10b9_1632[] = "M1632M Northbridge+Trident"; +static const char pci_device_10b9_1641[] = "ALI M1641 PCI North Bridge Aladdin Pro IV"; +static const char pci_device_10b9_1644[] = "M1644/M1644T Northbridge+Trident"; +static const char pci_device_10b9_1646[] = "M1646 Northbridge+Trident"; +static const char pci_device_10b9_1647[] = "M1647 Northbridge [MAGiK 1 / MobileMAGiK 1]"; +static const char pci_device_10b9_1651[] = "M1651/M1651T Northbridge [Aladdin-Pro 5/5M,Aladdin-Pro 5T/5TM]"; +static const char pci_device_10b9_1671[] = "M1671 Super P4 Northbridge [AGP4X,PCI and SDR/DDR]"; +static const char pci_device_10b9_1672[] = "M1672 Northbridge [CyberALADDiN-P4]"; +static const char pci_device_10b9_1681[] = "M1681 P4 Northbridge [AGP8X,HyperTransport and SDR/DDR]"; +static const char pci_device_10b9_1687[] = "M1687 K8 Northbridge [AGP8X and HyperTransport]"; +static const char pci_device_10b9_1689[] = "M1689 K8 Northbridge [Super K8 Single Chip]"; +static const char pci_device_10b9_1695[] = "M1695 K8 Northbridge [PCI Express and HyperTransport]"; +static const char pci_device_10b9_1697[] = "M1697 HTT Host Bridge"; +static const char pci_device_10b9_3141[] = "M3141"; +static const char pci_device_10b9_3143[] = "M3143"; +static const char pci_device_10b9_3145[] = "M3145"; +static const char pci_device_10b9_3147[] = "M3147"; +static const char pci_device_10b9_3149[] = "M3149"; +static const char pci_device_10b9_3151[] = "M3151"; +static const char pci_device_10b9_3307[] = "M3307"; +static const char pci_device_10b9_3309[] = "M3309"; +static const char pci_device_10b9_3323[] = "M3325 Video/Audio Decoder"; +static const char pci_device_10b9_5212[] = "M4803"; +static const char pci_device_10b9_5215[] = "MS4803"; +static const char pci_device_10b9_5217[] = "M5217H"; +static const char pci_device_10b9_5219[] = "M5219"; +static const char pci_device_10b9_5225[] = "M5225"; +static const char pci_device_10b9_5228[] = "M5228 ALi ATA/RAID Controller"; +static const char pci_device_10b9_5229[] = "M5229 IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5229_1014_050f[] = "ThinkPad R30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5229_1014_053d[] = "ThinkPad R40e (2684-HVG) builtin IDE"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5229_103c_0024[] = "Pavilion ze4400 builtin IDE"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5229_1043_8053[] = "A7A266 Motherboard IDE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5229_1849_5229[] = "ASRock 939Dual-SATA2 Motherboard IDE (PATA)"; +#endif +static const char pci_device_10b9_5235[] = "M5225"; +static const char pci_device_10b9_5237[] = "USB 1.1 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5237_1014_0540[] = "ThinkPad R40e (2684-HVG) builtin USB"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5237_103c_0024[] = "Pavilion ze4400 builtin USB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5237_104d_810f[] = "VAIO PCG-U1 USB/OHCI Revision 1.0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_10b9_5239[] = "USB 2.0 Controller"; +static const char pci_device_10b9_5243[] = "M1541 PCI to AGP Controller"; +static const char pci_device_10b9_5246[] = "AGP8X Controller"; +static const char pci_device_10b9_5247[] = "PCI to AGP Controller"; +static const char pci_device_10b9_5249[] = "M5249 HTT to PCI Bridge"; +static const char pci_device_10b9_524b[] = "PCI Express Root Port"; +static const char pci_device_10b9_524c[] = "PCI Express Root Port"; +static const char pci_device_10b9_524d[] = "PCI Express Root Port"; +static const char pci_device_10b9_524e[] = "PCI Express Root Port"; +static const char pci_device_10b9_5251[] = "M5251 P1394 OHCI 1.0 Controller"; +static const char pci_device_10b9_5253[] = "M5253 P1394 OHCI 1.1 Controller"; +static const char pci_device_10b9_5261[] = "M5261 Ethernet Controller"; +static const char pci_device_10b9_5263[] = "ULi 1689,1573 integrated ethernet."; +static const char pci_device_10b9_5281[] = "ALi M5281 Serial ATA / RAID Host Controller"; +static const char pci_device_10b9_5287[] = "ULi 5287 SATA"; +static const char pci_device_10b9_5288[] = "ULi M5288 SATA"; +static const char pci_device_10b9_5289[] = "ULi 5289 SATA"; +static const char pci_device_10b9_5450[] = "Lucent Technologies Soft Modem AMR"; +static const char pci_device_10b9_5451[] = "M5451 PCI AC-Link Controller Audio Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5451_1014_0506[] = "ThinkPad R30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5451_1014_053e[] = "ThinkPad R40e (2684-HVG) builtin Audio"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5451_103c_0024[] = "Pavilion ze4400 builtin Audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5451_10b9_5451[] = "HP Compaq nc4010 (DY885AA#ABN)"; +#endif +static const char pci_device_10b9_5453[] = "M5453 PCI AC-Link Controller Modem Device"; +static const char pci_device_10b9_5455[] = "M5455 PCI AC-Link Controller Audio Device"; +static const char pci_device_10b9_5457[] = "M5457 AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5457_1014_0535[] = "ThinkPad R40e (2684-HVG) builtin modem"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_5457_103c_0024[] = "Pavilion ze4400 builtin Modem Device"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_10b9_5459[] = "SmartLink SmartPCI561 56K Modem"; +static const char pci_device_10b9_545a[] = "SmartLink SmartPCI563 56K Modem"; +static const char pci_device_10b9_5461[] = "High Definition Audio/AC'97 Host Controller"; +static const char pci_device_10b9_5471[] = "M5471 Memory Stick Controller"; +static const char pci_device_10b9_5473[] = "M5473 SD-MMC Controller"; +static const char pci_device_10b9_7101[] = "M7101 Power Management Controller [PMU]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_7101_1014_0510[] = "ThinkPad R30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_7101_1014_053c[] = "ThinkPad R40e (2684-HVG) Power Management Controller"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10b9_7101_103c_0024[] = "Pavilion ze4400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ba[] = "Mitsubishi Electric Corp."; +static const char pci_device_10ba_0301[] = "AccelGraphics AccelECLIPSE"; +static const char pci_device_10ba_0304[] = "AccelGALAXY A2100 [OEM Evans & Sutherland]"; +static const char pci_device_10ba_0308[] = "Tornado 3000 [OEM Evans & Sutherland]"; +static const char pci_device_10ba_1002[] = "VG500 [VolumePro Volume Rendering Accelerator]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10bb[] = "Dapha Electronics Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10bc[] = "Advanced Logic Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10bd[] = "Surecom Technology"; +static const char pci_device_10bd_0e34[] = "NE-34"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10be[] = "Tseng Labs International Co."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10bf[] = "Most Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c0[] = "Boca Research Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c1[] = "ICM Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c2[] = "Auspex Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c3[] = "Samsung Semiconductors, Inc."; +static const char pci_device_10c3_1100[] = "Smartether100 SC1100 LAN Adapter (i82557B)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c4[] = "Award Software International Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c5[] = "Xerox Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c6[] = "Rambus Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c7[] = "Media Vision"; +#endif +static const char pci_vendor_10c8[] = "Neomagic Corporation"; +static const char pci_device_10c8_0001[] = "NM2070 [MagicGraph 128]"; +static const char pci_device_10c8_0002[] = "NM2090 [MagicGraph 128V]"; +static const char pci_device_10c8_0003[] = "NM2093 [MagicGraph 128ZV]"; +static const char pci_device_10c8_0004[] = "NM2160 [MagicGraph 128XD]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1014_00ba[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1025_1007[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1028_0074[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1028_0075[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1028_007d[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1028_007e[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_1033_802f[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_104d_801b[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_104d_802f[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_104d_830b[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10ba_0e00[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10c8_0004[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10cf_1029[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_8308[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_8309[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_830b[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_830d[] = "MagicGraph 128XD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0004_10f7_8312[] = "MagicGraph 128XD"; +#endif +static const char pci_device_10c8_0005[] = "NM2200 [MagicGraph 256AV]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0005_1014_00dd[] = "ThinkPad 570"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0005_1028_0088[] = "Latitude CPi A"; +#endif +static const char pci_device_10c8_0006[] = "NM2360 [MagicMedia 256ZX]"; +static const char pci_device_10c8_0016[] = "NM2380 [MagicMedia 256XL+]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_0016_10c8_0016[] = "MagicMedia 256XL+"; +#endif +static const char pci_device_10c8_0025[] = "NM2230 [MagicGraph 256AV+]"; +static const char pci_device_10c8_0083[] = "NM2093 [MagicGraph 128ZV+]"; +static const char pci_device_10c8_8005[] = "NM2200 [MagicMedia 256AV Audio]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_0e11_b0d1[] = "MagicMedia 256AV Audio Device on Discovery"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_0e11_b126[] = "MagicMedia 256AV Audio Device on Durango"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_1014_00dd[] = "MagicMedia 256AV Audio Device on BlackTip Thinkpad"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_1025_1003[] = "MagicMedia 256AV Audio Device on TravelMate 720"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_1028_0088[] = "Latitude CPi A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_1028_008f[] = "MagicMedia 256AV Audio Device on Colorado Inspiron"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_103c_0007[] = "MagicMedia 256AV Audio Device on Voyager II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_103c_0008[] = "MagicMedia 256AV Audio Device on Voyager III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_103c_000d[] = "MagicMedia 256AV Audio Device on Omnibook 900"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_10c8_8005[] = "MagicMedia 256AV Audio Device on FireAnt"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_110a_8005[] = "MagicMedia 256AV Audio Device"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10c8_8005_14c0_0004[] = "MagicMedia 256AV Audio Device"; +#endif +static const char pci_device_10c8_8006[] = "NM2360 [MagicMedia 256ZX Audio]"; +static const char pci_device_10c8_8016[] = "NM2380 [MagicMedia 256XL+ Audio]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10c9[] = "Dataexpert Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ca[] = "Fujitsu Microelectr., Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10cb[] = "Omron Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10cc[] = "Mai Logic Incorporated"; +static const char pci_device_10cc_0660[] = "Articia S Host Bridge"; +static const char pci_device_10cc_0661[] = "Articia S PCI Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10cd[] = "Advanced System Products, Inc"; +static const char pci_device_10cd_1100[] = "ASC1100"; +static const char pci_device_10cd_1200[] = "ASC1200 [(abp940) Fast SCSI-II]"; +static const char pci_device_10cd_1300[] = "ABP940-U / ABP960-U"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10cd_1300_10cd_1310[] = "ASC1300 SCSI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10cd_1300_1195_1320[] = "Ultra-SCSI CardBus PC Card REX CB31"; +#endif +static const char pci_device_10cd_2300[] = "ABP940-UW"; +static const char pci_device_10cd_2500[] = "ABP940-U2W"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ce[] = "Radius"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10cf[] = "Fujitsu Limited."; +static const char pci_device_10cf_2001[] = "mb86605"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d1[] = "FuturePlus Systems Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d2[] = "Molex Incorporated"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d3[] = "Jabil Circuit Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d4[] = "Hualon Microelectronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d5[] = "Autologic Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d6[] = "Cetia"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d7[] = "BCM Advanced Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d8[] = "Advanced Peripherals Labs"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10d9[] = "Macronix, Inc. [MXIC]"; +static const char pci_device_10d9_0431[] = "MX98715"; +static const char pci_device_10d9_0512[] = "MX98713"; +static const char pci_device_10d9_0531[] = "MX987x5"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10d9_0531_1186_1200[] = "DFE-540TX ProFAST 10/100 Adapter"; +#endif +static const char pci_device_10d9_8625[] = "MX86250"; +static const char pci_device_10d9_8626[] = "Macronix MX86251 + 3Dfx Voodoo Rush"; +static const char pci_device_10d9_8888[] = "MX86200"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10da[] = "Compaq IPG-Austin"; +static const char pci_device_10da_0508[] = "TC4048 Token Ring 4/16"; +static const char pci_device_10da_3390[] = "Tl3c3x9"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10db[] = "Rohm LSI Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10dc[] = "CERN/ECP/EDU"; +static const char pci_device_10dc_0001[] = "STAR/RD24 SCI-PCI (PMC)"; +static const char pci_device_10dc_0002[] = "TAR/RD24 SCI-PCI (PMC)"; +static const char pci_device_10dc_0021[] = "HIPPI destination"; +static const char pci_device_10dc_0022[] = "HIPPI source"; +static const char pci_device_10dc_10dc[] = "ATT2C15-3 FPGA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10dd[] = "Evans & Sutherland"; +static const char pci_device_10dd_0100[] = "Lightning 1200"; +#endif +static const char pci_vendor_10de[] = "nVidia Corporation"; +static const char pci_device_10de_0008[] = "NV1 [EDGE 3D]"; +static const char pci_device_10de_0009[] = "NV1 [EDGE 3D]"; +static const char pci_device_10de_0010[] = "NV2 [Mutara V08]"; +static const char pci_device_10de_0020[] = "NV4 [RIVA TNT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1043_0200[] = "V3400 TNT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1048_0c18[] = "Erazor II SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1048_0c19[] = "Erazor II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1048_0c1b[] = "Erazor II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1048_0c1c[] = "Erazor II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_0550[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_0552[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4804[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4808[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4810[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4812[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4815[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4820[] = "Viper V550 with TV out"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4822[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4904[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_4914[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1092_8225[] = "Viper V550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_10b4_273d[] = "Velocity 4400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_10b4_273e[] = "Velocity 4400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_10b4_2740[] = "Velocity 4400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_10de_0020[] = "Riva TNT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1102_1015[] = "Graphics Blaster CT6710"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0020_1102_1016[] = "Graphics Blaster RIVA TNT"; +#endif +static const char pci_device_10de_0028[] = "NV5 [RIVA TNT2/TNT2 Pro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1043_0200[] = "AGP-V3800 SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1043_0201[] = "AGP-V3800 SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1043_0205[] = "PCI-V3800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1043_4000[] = "AGP-V3800PRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c21[] = "Synergy II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c28[] = "Erazor III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c29[] = "Erazor III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c2a[] = "Erazor III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c2b[] = "Erazor III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c31[] = "Erazor III Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c32[] = "Erazor III Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c33[] = "Erazor III Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1048_0c34[] = "Erazor III Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_107d_2134[] = "WinFast 3D S320 II + TV-Out"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_4804[] = "Viper V770"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_4a00[] = "Viper V770"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_4a02[] = "Viper V770 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_5a00[] = "RIVA TNT2/TNT2 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_6a02[] = "Viper V770 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1092_7a02[] = "Viper V770 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_10de_0005[] = "RIVA TNT2 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_10de_000f[] = "Compaq NVIDIA TNT2 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1102_1020[] = "3D Blaster RIVA TNT2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_1102_1026[] = "3D Blaster RIVA TNT2 Digital"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0028_14af_5810[] = "Maxi Gamer Xentor"; +#endif +static const char pci_device_10de_0029[] = "NV5 [RIVA TNT2 Ultra]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1043_0200[] = "AGP-V3800 Deluxe"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1043_0201[] = "AGP-V3800 Ultra SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1043_0205[] = "PCI-V3800 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1048_0c2e[] = "Erazor III Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1048_0c2f[] = "Erazor III Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1048_0c30[] = "Erazor III Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1102_1021[] = "3D Blaster RIVA TNT2 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1102_1029[] = "3D Blaster RIVA TNT2 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_1102_102f[] = "3D Blaster RIVA TNT2 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0029_14af_5820[] = "Maxi Gamer Xentor 32"; +#endif +static const char pci_device_10de_002a[] = "NV5 [Riva TnT2]"; +static const char pci_device_10de_002b[] = "NV5 [Riva TnT2]"; +static const char pci_device_10de_002c[] = "NV6 [Vanta/Vanta LT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1043_0200[] = "AGP-V3800 Combat SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1043_0201[] = "AGP-V3800 Combat"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1048_0c20[] = "TNT2 Vanta"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1048_0c21[] = "TNT2 Vanta"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1092_6820[] = "Viper V730"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1102_1031[] = "CT6938 VANTA 8MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_1102_1034[] = "CT6894 VANTA 16MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002c_14af_5008[] = "Maxi Gamer Phoenix 2"; +#endif +static const char pci_device_10de_002d[] = "NV5M64 [RIVA TNT2 Model 64/Model 64 Pro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1043_0200[] = "AGP-V3800M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1043_0201[] = "AGP-V3800M"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1048_0c3a[] = "Erazor III LT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1048_0c3b[] = "Erazor III LT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_10de_001e[] = "M64 AGP4x"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1102_1023[] = "CT6892 RIVA TNT2 Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1102_1024[] = "CT6932 RIVA TNT2 Value 32Mb"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1102_102c[] = "CT6931 RIVA TNT2 Value [Jumper]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1462_8808[] = "MSI-8808"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1554_1041[] = "Pixelview RIVA TNT2 M64"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_002d_1569_002d[] = "Palit Microsystems Daytona TNT2 M64"; +#endif +static const char pci_device_10de_002e[] = "NV6 [Vanta]"; +static const char pci_device_10de_002f[] = "NV6 [Vanta]"; +static const char pci_device_10de_0034[] = "MCP04 SMBus"; +static const char pci_device_10de_0035[] = "MCP04 IDE"; +static const char pci_device_10de_0036[] = "MCP04 Serial ATA Controller"; +static const char pci_device_10de_0037[] = "MCP04 Ethernet Controller"; +static const char pci_device_10de_0038[] = "MCP04 Ethernet Controller"; +static const char pci_device_10de_003a[] = "MCP04 AC'97 Audio Controller"; +static const char pci_device_10de_003b[] = "MCP04 USB Controller"; +static const char pci_device_10de_003c[] = "MCP04 USB Controller"; +static const char pci_device_10de_003d[] = "MCP04 PCI Bridge"; +static const char pci_device_10de_003e[] = "MCP04 Serial ATA Controller"; +static const char pci_device_10de_0040[] = "NV40 [GeForce 6800 Ultra]"; +static const char pci_device_10de_0041[] = "NV40 [GeForce 6800]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0041_1043_817b[] = "V9999 Gamer Edition"; +#endif +static const char pci_device_10de_0042[] = "NV40.2 [GeForce 6800 LE]"; +static const char pci_device_10de_0043[] = "NV40.3"; +static const char pci_device_10de_0044[] = "NV40 [GeForce 6800 XT]"; +static const char pci_device_10de_0045[] = "NV40 [GeForce 6800 GT]"; +static const char pci_device_10de_0046[] = "NV40 [GeForce 6800 GT]"; +static const char pci_device_10de_0047[] = "NV40 [GeForce 6800 GS]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0047_1682_2109[] = "GeForce 6800 GS"; +#endif +static const char pci_device_10de_0048[] = "NV40 [GeForce 6800 XT]"; +static const char pci_device_10de_0049[] = "NV40GL"; +static const char pci_device_10de_004d[] = "NV40GL [Quadro FX 4000]"; +static const char pci_device_10de_004e[] = "NV40GL [Quadro FX 4000]"; +static const char pci_device_10de_0050[] = "CK804 ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0050_1043_815a[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0050_1458_0c11[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0050_1462_7100[] = "MSI K8N Diamond"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0050_147b_1c1a[] = "KN8-Ultra Mainboard"; +#endif +static const char pci_device_10de_0051[] = "CK804 ISA Bridge"; +static const char pci_device_10de_0052[] = "CK804 SMBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0052_1043_815a[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0052_1458_0c11[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0052_1462_7100[] = "MSI K8N Diamond"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0052_147b_1c1a[] = "KN8-Ultra Mainboard"; +#endif +static const char pci_device_10de_0053[] = "CK804 IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0053_1043_815a[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0053_1458_5002[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0053_1462_7100[] = "MSI K8N Diamond"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0053_147b_1c1a[] = "KN8-Ultra Mainboard"; +#endif +static const char pci_device_10de_0054[] = "CK804 Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0054_1458_b003[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0054_1462_7100[] = "MSI K8N Diamond"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0054_147b_1c1a[] = "KN8-Ultra Mainboard"; +#endif +static const char pci_device_10de_0055[] = "CK804 Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0055_1043_815a[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0055_1458_b003[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0055_147b_1c1a[] = "KN8-Ultra Mainboard"; +#endif +static const char pci_device_10de_0056[] = "CK804 Ethernet Controller"; +static const char pci_device_10de_0057[] = "CK804 Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0057_1043_8141[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0057_1458_e000[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0057_1462_7100[] = "MSI K8N Diamond"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0057_147b_1c1a[] = "KN8-Ultra Mainboard"; +#endif +static const char pci_device_10de_0058[] = "CK804 AC'97 Modem"; +static const char pci_device_10de_0059[] = "CK804 AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0059_1043_812a[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0059_147b_1c1a[] = "KN8-Ultra Mainboard"; +#endif +static const char pci_device_10de_005a[] = "CK804 USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005a_1043_815a[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005a_1458_5004[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005a_1462_7100[] = "MSI K8N Diamond"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005a_147b_1c1a[] = "KN8-Ultra Mainboard"; +#endif +static const char pci_device_10de_005b[] = "CK804 USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005b_1043_815a[] = "K8N4-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005b_1458_5004[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005b_1462_7100[] = "MSI K8N Diamond"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005b_147b_1c1a[] = "KN8-Ultra Mainboard"; +#endif +static const char pci_device_10de_005c[] = "CK804 PCI Bridge"; +static const char pci_device_10de_005d[] = "CK804 PCIE Bridge"; +static const char pci_device_10de_005e[] = "CK804 Memory Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005e_10f1_2891[] = "Thunder K8SRE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005e_1458_5000[] = "GA-K8N Ultra-9 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005e_1462_7100[] = "MSI K8N Diamond"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_005e_147b_1c1a[] = "KN8-Ultra Mainboard"; +#endif +static const char pci_device_10de_005f[] = "CK804 Memory Controller"; +static const char pci_device_10de_0060[] = "nForce2 ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0060_1043_80ad[] = "A7N8X Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0060_a0a0_03ba[] = "UK79G-1394 motherboard"; +#endif +static const char pci_device_10de_0064[] = "nForce2 SMBus (MCP)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0064_a0a0_03bb[] = "UK79G-1394 motherboard"; +#endif +static const char pci_device_10de_0065[] = "nForce2 IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0065_a0a0_03b2[] = "UK79G-1394 motherboard"; +#endif +static const char pci_device_10de_0066[] = "nForce2 Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0066_1043_80a7[] = "A7N8X Mainboard onboard nForce2 Ethernet"; +#endif +static const char pci_device_10de_0067[] = "nForce2 USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0067_1043_0c11[] = "A7N8X Mainboard"; +#endif +static const char pci_device_10de_0068[] = "nForce2 USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0068_1043_0c11[] = "A7N8X Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0068_a0a0_03b4[] = "UK79G-1394 motherboard"; +#endif +static const char pci_device_10de_006a[] = "nForce2 AC97 Audio Controler (MCP)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_006a_1043_8095[] = "nForce2 AC97 Audio Controler (MCP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_006a_a0a0_0304[] = "UK79G-1394 motherboard"; +#endif +static const char pci_device_10de_006b[] = "nForce Audio Processing Unit"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_006b_10de_006b[] = "nForce2 MCP Audio Processing Unit"; +#endif +static const char pci_device_10de_006c[] = "nForce2 External PCI Bridge"; +static const char pci_device_10de_006d[] = "nForce2 PCI Bridge"; +static const char pci_device_10de_006e[] = "nForce2 FireWire (IEEE 1394) Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_006e_a0a0_0306[] = "UK79G-1394 motherboard"; +#endif +static const char pci_device_10de_0080[] = "MCP2A ISA bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0080_147b_1c09[] = "NV7 Motherboard"; +#endif +static const char pci_device_10de_0084[] = "MCP2A SMBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0084_147b_1c09[] = "NV7 Motherboard"; +#endif +static const char pci_device_10de_0085[] = "MCP2A IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0085_147b_1c09[] = "NV7 Motherboard"; +#endif +static const char pci_device_10de_0086[] = "MCP2A Ethernet Controller"; +static const char pci_device_10de_0087[] = "MCP2A USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0087_147b_1c09[] = "NV7 Motherboard"; +#endif +static const char pci_device_10de_0088[] = "MCP2A USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0088_147b_1c09[] = "NV7 Motherboard"; +#endif +static const char pci_device_10de_008a[] = "MCP2S AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_008a_147b_1c09[] = "NV7 Motherboard"; +#endif +static const char pci_device_10de_008b[] = "MCP2A PCI Bridge"; +static const char pci_device_10de_008c[] = "MCP2A Ethernet Controller"; +static const char pci_device_10de_008e[] = "nForce2 Serial ATA Controller"; +static const char pci_device_10de_0090[] = "G70 [GeForce 7800 GTX]"; +static const char pci_device_10de_0091[] = "G70 [GeForce 7800 GTX]"; +static const char pci_device_10de_0092[] = "G70 [GeForce 7800 GT]"; +static const char pci_device_10de_0093[] = "G70 [GeForce 7800 GS]"; +static const char pci_device_10de_0098[] = "GeForce Go 7800"; +static const char pci_device_10de_0099[] = "GE Force Go 7800 GTX"; +static const char pci_device_10de_009d[] = "G70GL [Quadro FX4500]"; +static const char pci_device_10de_00a0[] = "NV5 [Aladdin TNT2]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00a0_14af_5810[] = "Maxi Gamer Xentor"; +#endif +static const char pci_device_10de_00c0[] = "NV41 [GeForce 6800 GS]"; +static const char pci_device_10de_00c1[] = "NV41.1 [GeForce 6800]"; +static const char pci_device_10de_00c2[] = "NV41.2 [GeForce 6800 LE]"; +static const char pci_device_10de_00c3[] = "NV42 [Geforce 6800 XT]"; +static const char pci_device_10de_00c8[] = "NV41.8 [GeForce Go 6800]"; +static const char pci_device_10de_00c9[] = "NV41.9 [GeForce Go 6800 Ultra]"; +static const char pci_device_10de_00cc[] = "NV41 [Quadro FX Go1400]"; +static const char pci_device_10de_00cd[] = "NV41 [Quadro FX 3450/4000 SDI]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00cd_10de_029b[] = "wx4300 Workstation"; +#endif +static const char pci_device_10de_00ce[] = "NV41GL [Quadro FX 1400]"; +static const char pci_device_10de_00d0[] = "nForce3 LPC Bridge"; +static const char pci_device_10de_00d1[] = "nForce3 Host Bridge"; +static const char pci_device_10de_00d2[] = "nForce3 AGP Bridge"; +static const char pci_device_10de_00d3[] = "CK804 Memory Controller"; +static const char pci_device_10de_00d4[] = "nForce3 SMBus"; +static const char pci_device_10de_00d5[] = "nForce3 IDE"; +static const char pci_device_10de_00d6[] = "nForce3 Ethernet"; +static const char pci_device_10de_00d7[] = "nForce3 USB 1.1"; +static const char pci_device_10de_00d8[] = "nForce3 USB 2.0"; +static const char pci_device_10de_00d9[] = "nForce3 Audio"; +static const char pci_device_10de_00da[] = "nForce3 Audio"; +static const char pci_device_10de_00dd[] = "nForce3 PCI Bridge"; +static const char pci_device_10de_00df[] = "CK8S Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00df_105b_0c43[] = "Winfast NF3250K8AA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00df_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e0[] = "nForce3 250Gb LPC Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e0_10de_0c11[] = "Winfast NF3250K8AA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e0_1462_7030[] = "K8N Neo-FSR v2.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e0_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e1[] = "nForce3 250Gb Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e1_1462_7030[] = "K8N Neo-FSR v2.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e1_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e2[] = "nForce3 250Gb AGP Host to PCI Bridge"; +static const char pci_device_10de_00e3[] = "CK8S Serial ATA Controller (v2.5)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e3_105b_0c43[] = "Winfast NF3250K8AA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e3_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e4[] = "nForce 250Gb PCI System Management"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e4_105b_0c43[] = "Winfast NF3250K8AA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e4_1462_7030[] = "K8N Neo-FSR v2.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e4_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e5[] = "CK8S Parallel ATA Controller (v2.5)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e5_105b_0c43[] = "Winfast NF3250K8AA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e5_1462_7030[] = "K8N Neo-FSR v2.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e5_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e6[] = "CK8S Ethernet Controller"; +static const char pci_device_10de_00e7[] = "CK8S USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e7_105b_0c43[] = "Winfast NF3250K8AA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e7_1462_7030[] = "K8N Neo-FSR v2.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e7_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00e8[] = "nForce3 EHCI USB 2.0 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e8_105b_0c43[] = "Winfast NF3250K8AA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e8_1462_7030[] = "K8N Neo-FSR v2.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00e8_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00ea[] = "nForce3 250Gb AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00ea_105b_0c43[] = "Winfast NF3250K8AA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00ea_147b_1c0b[] = "NF8 Mainboard"; +#endif +static const char pci_device_10de_00ed[] = "nForce3 250Gb PCI-to-PCI Bridge"; +static const char pci_device_10de_00ee[] = "CK8S Serial ATA Controller (v2.5)"; +static const char pci_device_10de_00f0[] = "NV40 [GeForce 6800/GeForce 6800 Ultra]"; +static const char pci_device_10de_00f1[] = "NV43 [GeForce 6600/GeForce 6600 GT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00f1_1043_81a6[] = "N6600GT TD 128M AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00f1_1682_2119[] = "GeForce 6600 GT AGP 128MB DDR3 DUAL DVI TV"; +#endif +static const char pci_device_10de_00f2[] = "NV43 [GeForce 6600/GeForce 6600 GT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00f2_1682_211c[] = "GeForce 6600 256MB DDR DUAL DVI TV"; +#endif +static const char pci_device_10de_00f3[] = "NV43 [GeForce 6200]"; +static const char pci_device_10de_00f4[] = "NV43 [GeForce 6600 LE]"; +static const char pci_device_10de_00f5[] = "G70 [GeForce 7800 GS]"; +static const char pci_device_10de_00f6[] = "NV43 [GeForce 6600 GS]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00f6_1682_217e[] = "XFX GeForce 6800 XTreme 256MB DDR3 AGP"; +#endif +static const char pci_device_10de_00f8[] = "NV45GL [Quadro FX 3400/4400]"; +static const char pci_device_10de_00f9[] = "NV40 [GeForce 6800 Ultra/GeForce 6800 GT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_00f9_1682_2120[] = "GEFORCE 6800 GT PCI-E"; +#endif +static const char pci_device_10de_00fa[] = "NV36 [GeForce PCX 5750]"; +static const char pci_device_10de_00fb[] = "NV35 [GeForce PCX 5900]"; +static const char pci_device_10de_00fc[] = "NV37GL [Quadro FX 330/GeForce PCX 5300]"; +static const char pci_device_10de_00fd[] = "NV37GL [Quadro FX 330/Quadro NVS280]"; +static const char pci_device_10de_00fe[] = "NV38GL [Quadro FX 1300]"; +static const char pci_device_10de_00ff[] = "NV18 [GeForce PCX 4300]"; +static const char pci_device_10de_0100[] = "NV10 [GeForce 256 SDR]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1043_0200[] = "AGP-V6600 SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1043_0201[] = "AGP-V6600 SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1043_4008[] = "AGP-V6600 SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1043_4009[] = "AGP-V6600 SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1048_0c41[] = "Erazor X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1048_0c43[] = "ERAZOR X PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1048_0c48[] = "Synergy Force"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_1102_102d[] = "CT6941 GeForce 256"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0100_14af_5022[] = "3D Prophet SE"; +#endif +static const char pci_device_10de_0101[] = "NV10DDR [GeForce 256 DDR]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_1043_0202[] = "AGP-V6800 DDR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_1043_400a[] = "AGP-V6800 DDR SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_1043_400b[] = "AGP-V6800 DDR SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_1048_0c42[] = "Erazor X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_107d_2822[] = "WinFast GeForce 256"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_1102_102e[] = "CT6971 GeForce 256 DDR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0101_14af_5021[] = "3D Prophet DDR-DVI"; +#endif +static const char pci_device_10de_0103[] = "NV10GL [Quadro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0103_1048_0c40[] = "GLoria II-64"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0103_1048_0c44[] = "GLoria II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0103_1048_0c45[] = "GLoria II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0103_1048_0c4a[] = "GLoria II-64 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0103_1048_0c4b[] = "GLoria II-64 Pro DVII"; +#endif +static const char pci_device_10de_0110[] = "NV11 [GeForce2 MX/MX 400]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1043_4015[] = "AGP-V7100 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1043_4031[] = "V7100 Pro with TV output"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c60[] = "Gladiac MX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c61[] = "Gladiac 511PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c63[] = "Gladiac 511TV-OUT 32MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c64[] = "Gladiac 511TV-OUT 64MB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c65[] = "Gladiac 511TWIN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1048_0c66[] = "Gladiac 311"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_10de_0091[] = "Dell OEM GeForce 2 MX 400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_10de_00a1[] = "Apple OEM GeForce2 MX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_1462_8817[] = "MSI GeForce2 MX400 Pro32S [MS-8817]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_14af_7102[] = "3D Prophet II MX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0110_14af_7103[] = "3D Prophet II MX Dual-Display"; +#endif +static const char pci_device_10de_0111[] = "NV11DDR [GeForce2 MX 100 DDR/200 DDR]"; +static const char pci_device_10de_0112[] = "NV11 [GeForce2 Go]"; +static const char pci_device_10de_0113[] = "NV11GL [Quadro2 MXR/EX/Go]"; +static const char pci_device_10de_0140[] = "NV43 [GeForce 6600 GT]"; +static const char pci_device_10de_0141[] = "NV43 [GeForce 6600]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0141_1458_3124[] = "GV-NX66128DP Turbo Force Edition"; +#endif +static const char pci_device_10de_0142[] = "NV43 [GeForce 6600 PCIe]"; +static const char pci_device_10de_0144[] = "NV43 [GeForce Go 6600]"; +static const char pci_device_10de_0145[] = "NV43 [GeForce 6610 XL]"; +static const char pci_device_10de_0146[] = "NV43 [Geforce Go 6600TE/6200TE]"; +static const char pci_device_10de_0147[] = "GeForce 6700 XL"; +static const char pci_device_10de_0148[] = "NV43 [GeForce Go 6600]"; +static const char pci_device_10de_0149[] = "NV43 [GeForce Go 6600 GT]"; +static const char pci_device_10de_014a[] = "Quadro NVS 440"; +static const char pci_device_10de_014c[] = "Quadro FX 550"; +static const char pci_device_10de_014d[] = "NV18GL [Quadro FX 550]"; +static const char pci_device_10de_014e[] = "NV43GL [Quadro FX 540]"; +static const char pci_device_10de_014f[] = "NV43 [GeForce 6200]"; +static const char pci_device_10de_0150[] = "NV15 [GeForce2 GTS/Pro]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_1043_4016[] = "V7700 AGP Video Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_1048_0c50[] = "Gladiac"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_1048_0c52[] = "Gladiac-64"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_107d_2840[] = "WinFast GeForce2 GTS with TV output"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_107d_2842[] = "WinFast GeForce 2 Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_10de_002e[] = "GeForce2 GTS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0150_1462_8831[] = "Creative GeForce2 Pro"; +#endif +static const char pci_device_10de_0151[] = "NV15DDR [GeForce2 Ti]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0151_1043_405f[] = "V7700Ti"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0151_1462_5506[] = "Creative 3D Blaster Geforce2 Titanium"; +#endif +static const char pci_device_10de_0152[] = "NV15BR [GeForce2 Ultra, Bladerunner]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0152_1048_0c56[] = "GLADIAC Ultra"; +#endif +static const char pci_device_10de_0153[] = "NV15GL [Quadro2 Pro]"; +static const char pci_device_10de_0160[] = "GeForce 6500"; +static const char pci_device_10de_0161[] = "NV44 [GeForce 6200 TurboCache(TM)]"; +static const char pci_device_10de_0162[] = "NV44 [GeForce 6200 SE TurboCache (TM)]"; +static const char pci_device_10de_0163[] = "NV44 [GeForce 6200 LE]"; +static const char pci_device_10de_0164[] = "NV44 [GeForce Go 6200]"; +static const char pci_device_10de_0165[] = "NV44 [Quadro NVS 285]"; +static const char pci_device_10de_0166[] = "NV43 [GeForce Go 6400]"; +static const char pci_device_10de_0167[] = "GeForce Go 6200 TurboCache"; +static const char pci_device_10de_0168[] = "NV43 [GeForce Go 6200 TurboCache]"; +static const char pci_device_10de_0169[] = "GeForce 6250"; +static const char pci_device_10de_0170[] = "NV17 [GeForce4 MX 460]"; +static const char pci_device_10de_0171[] = "NV17 [GeForce4 MX 440]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_10b0_0002[] = "Gainward Pro/600 TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_10de_0008[] = "Apple OEM GeForce4 MX 440"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_1462_8661[] = "G4MX440-VTP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_1462_8730[] = "MX440SES-T (MS-8873)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_1462_8852[] = "GeForce4 MX440 PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0171_147b_8f00[] = "Abit Siluro GeForce4MX440"; +#endif +static const char pci_device_10de_0172[] = "NV17 [GeForce4 MX 420]"; +static const char pci_device_10de_0173[] = "NV17 [GeForce4 MX 440-SE]"; +static const char pci_device_10de_0174[] = "NV17 [GeForce4 440 Go]"; +static const char pci_device_10de_0175[] = "NV17 [GeForce4 420 Go]"; +static const char pci_device_10de_0176[] = "NV17 [GeForce4 420 Go 32M]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0176_103c_08b0[] = "tc1100 tablet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0176_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +static const char pci_device_10de_0177[] = "NV17 [GeForce4 460 Go]"; +static const char pci_device_10de_0178[] = "NV17GL [Quadro4 550 XGL]"; +static const char pci_device_10de_0179[] = "NV17 [GeForce4 420 Go 32M]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0179_10de_0179[] = "GeForce4 MX (Mac)"; +#endif +static const char pci_device_10de_017a[] = "NV17GL [Quadro4 200/400 NVS]"; +static const char pci_device_10de_017b[] = "NV17GL [Quadro4 550 XGL]"; +static const char pci_device_10de_017c[] = "NV17GL [Quadro4 500 GoGL]"; +static const char pci_device_10de_017d[] = "NV17 [GeForce4 410 Go 16M]"; +static const char pci_device_10de_0181[] = "NV18 [GeForce4 MX 440 AGP 8x]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0181_1043_8063[] = "GeForce4 MX 440 AGP 8X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0181_1043_806f[] = "V9180 Magic"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0181_1462_8880[] = "MS-StarForce GeForce4 MX 440 with AGP8X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0181_1462_8900[] = "MS-8890 GeForce 4 MX440 AGP8X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0181_1462_9350[] = "MSI Geforce4 MX T8X with AGP8X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0181_147b_8f0d[] = "Siluro GF4 MX-8X"; +#endif +static const char pci_device_10de_0182[] = "NV18 [GeForce4 MX 440SE AGP 8x]"; +static const char pci_device_10de_0183[] = "NV18 [GeForce4 MX 420 AGP 8x]"; +static const char pci_device_10de_0185[] = "NV18 [GeForce4 MX 4000 AGP 8x]"; +static const char pci_device_10de_0186[] = "NV18M [GeForce4 448 Go]"; +static const char pci_device_10de_0187[] = "NV18M [GeForce4 488 Go]"; +static const char pci_device_10de_0188[] = "NV18GL [Quadro4 580 XGL]"; +static const char pci_device_10de_018a[] = "NV18GL [Quadro4 NVS AGP 8x]"; +static const char pci_device_10de_018b[] = "NV18GL [Quadro4 380 XGL]"; +static const char pci_device_10de_018c[] = "Quadro NVS 50 PCI"; +static const char pci_device_10de_018d[] = "NV18M [GeForce4 448 Go]"; +static const char pci_device_10de_01a0[] = "NVCrush11 [GeForce2 MX Integrated Graphics]"; +static const char pci_device_10de_01a4[] = "nForce CPU bridge"; +static const char pci_device_10de_01ab[] = "nForce 420 Memory Controller (DDR)"; +static const char pci_device_10de_01ac[] = "nForce 220/420 Memory Controller"; +static const char pci_device_10de_01ad[] = "nForce 220/420 Memory Controller"; +static const char pci_device_10de_01b0[] = "nForce Audio"; +static const char pci_device_10de_01b1[] = "nForce Audio"; +static const char pci_device_10de_01b2[] = "nForce ISA Bridge"; +static const char pci_device_10de_01b4[] = "nForce PCI System Management"; +static const char pci_device_10de_01b7[] = "nForce AGP to PCI Bridge"; +static const char pci_device_10de_01b8[] = "nForce PCI-to-PCI bridge"; +static const char pci_device_10de_01bc[] = "nForce IDE"; +static const char pci_device_10de_01c1[] = "nForce AC'97 Modem Controller"; +static const char pci_device_10de_01c2[] = "nForce USB Controller"; +static const char pci_device_10de_01c3[] = "nForce Ethernet Controller"; +static const char pci_device_10de_01d1[] = "GeForce 7300 LE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_01d1_1462_0345[] = "7300LE PCI Express Graphics Adapter"; +#endif +static const char pci_device_10de_01d6[] = "GeForce Go 7200"; +static const char pci_device_10de_01d7[] = "Quadro NVS 110M / GeForce Go 7300"; +static const char pci_device_10de_01d8[] = "GeForce Go 7400"; +static const char pci_device_10de_01da[] = "Quadro NVS 110M"; +static const char pci_device_10de_01de[] = "Quadro FX 350"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_01de_10de_01dc[] = "Quadro FX Go350M"; +#endif +static const char pci_device_10de_01df[] = "GeForce 7300 GS"; +static const char pci_device_10de_01e0[] = "nForce2 AGP (different version?)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_01e0_147b_1c09[] = "NV7 Motherboard"; +#endif +static const char pci_device_10de_01e8[] = "nForce2 AGP"; +static const char pci_device_10de_01ea[] = "nForce2 Memory Controller 0"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_01ea_a0a0_03b9[] = "UK79G-1394 motherboard"; +#endif +static const char pci_device_10de_01eb[] = "nForce2 Memory Controller 1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_01eb_a0a0_03b9[] = "UK79G-1394 motherboard"; +#endif +static const char pci_device_10de_01ec[] = "nForce2 Memory Controller 2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_01ec_a0a0_03b9[] = "UK79G-1394 motherboard"; +#endif +static const char pci_device_10de_01ed[] = "nForce2 Memory Controller 3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_01ed_a0a0_03b9[] = "UK79G-1394 motherboard"; +#endif +static const char pci_device_10de_01ee[] = "nForce2 Memory Controller 4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_01ee_a0a0_03b9[] = "UK79G-1394 motherboard"; +#endif +static const char pci_device_10de_01ef[] = "nForce2 Memory Controller 5"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_01ef_a0a0_03b9[] = "UK79G-1394 motherboard"; +#endif +static const char pci_device_10de_01f0[] = "NV18 [GeForce4 MX - nForce GPU]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_01f0_a0a0_03b5[] = "UK79G-1394 motherboard"; +#endif +static const char pci_device_10de_0200[] = "NV20 [GeForce3]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0200_1043_402f[] = "AGP-V8200 DDR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0200_1048_0c70[] = "GLADIAC 920"; +#endif +static const char pci_device_10de_0201[] = "NV20 [GeForce3 Ti 200]"; +static const char pci_device_10de_0202[] = "NV20 [GeForce3 Ti 500]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0202_1043_405b[] = "V8200 T5"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0202_1545_002f[] = "Xtasy 6964"; +#endif +static const char pci_device_10de_0203[] = "NV20DCC [Quadro DCC]"; +static const char pci_device_10de_0211[] = "NV40 [GeForce 6800]"; +static const char pci_device_10de_0212[] = "NV40 [GeForce 6800 LE]"; +static const char pci_device_10de_0215[] = "NV40 [GeForce 6800 GT]"; +static const char pci_device_10de_0218[] = "NV40 [GeForce 6800 XT]"; +static const char pci_device_10de_0221[] = "NV44A [GeForce 6200]"; +static const char pci_device_10de_0240[] = "C51PV [GeForce 6150]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0240_1462_7207[] = "K8NGM2 series"; +#endif +static const char pci_device_10de_0241[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0242[] = "C51G [GeForce 6100]"; +static const char pci_device_10de_0243[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0244[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0245[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0246[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0247[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0248[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0249[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024a[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024b[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024c[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024d[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024e[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_024f[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_0250[] = "NV25 [GeForce4 Ti 4600]"; +static const char pci_device_10de_0251[] = "NV25 [GeForce4 Ti 4400]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0251_1043_8023[] = "v8440 GeForce 4 Ti4400"; +#endif +static const char pci_device_10de_0252[] = "NV25 [GeForce4 Ti]"; +static const char pci_device_10de_0253[] = "NV25 [GeForce4 Ti 4200]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0253_107d_2896[] = "WinFast A250 LE TD (Dual VGA/TV-out/DVI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0253_147b_8f09[] = "Siluro (Dual VGA/TV-out/DVI)"; +#endif +static const char pci_device_10de_0258[] = "NV25GL [Quadro4 900 XGL]"; +static const char pci_device_10de_0259[] = "NV25GL [Quadro4 750 XGL]"; +static const char pci_device_10de_025b[] = "NV25GL [Quadro4 700 XGL]"; +static const char pci_device_10de_0260[] = "MCP51 LPC Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0260_1462_7207[] = "K8NGM2 series"; +#endif +static const char pci_device_10de_0261[] = "MCP51 LPC Bridge"; +static const char pci_device_10de_0262[] = "MCP51 LPC Bridge"; +static const char pci_device_10de_0263[] = "MCP51 LPC Bridge"; +static const char pci_device_10de_0264[] = "MCP51 SMBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0264_1462_7207[] = "K8NGM2 series"; +#endif +static const char pci_device_10de_0265[] = "MCP51 IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0265_1462_7207[] = "K8NGM2 series"; +#endif +static const char pci_device_10de_0266[] = "MCP51 Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0266_1462_7207[] = "K8NGM2 series"; +#endif +static const char pci_device_10de_0267[] = "MCP51 Serial ATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0267_1462_7207[] = "K8NGM2 series"; +#endif +static const char pci_device_10de_0268[] = "MCP51 Ethernet Controller"; +static const char pci_device_10de_0269[] = "MCP51 Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0269_1462_7207[] = "K8NGM2 series"; +#endif +static const char pci_device_10de_026a[] = "MCP51 MCI"; +static const char pci_device_10de_026b[] = "MCP51 AC97 Audio Controller"; +static const char pci_device_10de_026c[] = "MCP51 High Definition Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_026c_1462_7207[] = "K8NGM2 series"; +#endif +static const char pci_device_10de_026d[] = "MCP51 USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_026d_1462_7207[] = "K8NGM2 series"; +#endif +static const char pci_device_10de_026e[] = "MCP51 USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_026e_1462_7207[] = "K8NGM2 series"; +#endif +static const char pci_device_10de_026f[] = "MCP51 PCI Bridge"; +static const char pci_device_10de_0270[] = "MCP51 Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0270_1462_7207[] = "K8NGM2 series"; +#endif +static const char pci_device_10de_0271[] = "MCP51 PMU"; +static const char pci_device_10de_0272[] = "MCP51 Memory Controller 0"; +static const char pci_device_10de_027e[] = "C51 Memory Controller 2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_027e_1462_7207[] = "K8NGM2 series"; +#endif +static const char pci_device_10de_027f[] = "C51 Memory Controller 3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_027f_1462_7207[] = "K8NGM2 series"; +#endif +static const char pci_device_10de_0280[] = "NV28 [GeForce4 Ti 4800]"; +static const char pci_device_10de_0281[] = "NV28 [GeForce4 Ti 4200 AGP 8x]"; +static const char pci_device_10de_0282[] = "NV28 [GeForce4 Ti 4800 SE]"; +static const char pci_device_10de_0286[] = "NV28 [GeForce4 Ti 4200 Go AGP 8x]"; +static const char pci_device_10de_0288[] = "NV28GL [Quadro4 980 XGL]"; +static const char pci_device_10de_0289[] = "NV28GL [Quadro4 780 XGL]"; +static const char pci_device_10de_028c[] = "NV28GLM [Quadro4 700 GoGL]"; +static const char pci_device_10de_0290[] = "GeForce 7900 GTX"; +static const char pci_device_10de_0291[] = "GeForce 7900 GT"; +static const char pci_device_10de_0292[] = "GeForce 7900 GS"; +static const char pci_device_10de_0298[] = "GeForce Go 7900 GS"; +static const char pci_device_10de_0299[] = "GeForce Go 7900 GTX"; +static const char pci_device_10de_029a[] = "G71 [Quadro FX 2500M]"; +static const char pci_device_10de_029b[] = "G71 [Quadro FX 1500M]"; +static const char pci_device_10de_029c[] = "Quadro FX 5500"; +static const char pci_device_10de_029d[] = "Quadro FX 3500"; +static const char pci_device_10de_029e[] = "Quadro FX 1500"; +static const char pci_device_10de_029f[] = "Quadro FX 4500 X2"; +static const char pci_device_10de_02a0[] = "NV2A [XGPU]"; +static const char pci_device_10de_02e1[] = "GeForce 7600 GS"; +static const char pci_device_10de_02f0[] = "C51 Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_02f0_1462_7207[] = "K8NGM2 series"; +#endif +static const char pci_device_10de_02f1[] = "C51 Host Bridge"; +static const char pci_device_10de_02f2[] = "C51 Host Bridge"; +static const char pci_device_10de_02f3[] = "C51 Host Bridge"; +static const char pci_device_10de_02f4[] = "C51 Host Bridge"; +static const char pci_device_10de_02f5[] = "C51 Host Bridge"; +static const char pci_device_10de_02f6[] = "C51 Host Bridge"; +static const char pci_device_10de_02f7[] = "C51 Host Bridge"; +static const char pci_device_10de_02f8[] = "C51 Memory Controller 5"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_02f8_1462_7207[] = "K8NGM2 series"; +#endif +static const char pci_device_10de_02f9[] = "C51 Memory Controller 4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_02f9_1462_7207[] = "K8NGM2 series"; +#endif +static const char pci_device_10de_02fa[] = "C51 Memory Controller 0"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_02fa_1462_7207[] = "K8NGM2 series"; +#endif +static const char pci_device_10de_02fb[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_02fc[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_02fd[] = "C51 PCI Express Bridge"; +static const char pci_device_10de_02fe[] = "C51 Memory Controller 1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_02fe_1462_7207[] = "K8NGM2 series"; +#endif +static const char pci_device_10de_02ff[] = "C51 Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_02ff_1462_7207[] = "K8NGM2 series"; +#endif +static const char pci_device_10de_0300[] = "NV30 [GeForce FX]"; +static const char pci_device_10de_0301[] = "NV30 [GeForce FX 5800 Ultra]"; +static const char pci_device_10de_0302[] = "NV30 [GeForce FX 5800]"; +static const char pci_device_10de_0308[] = "NV30GL [Quadro FX 2000]"; +static const char pci_device_10de_0309[] = "NV30GL [Quadro FX 1000]"; +static const char pci_device_10de_0311[] = "NV31 [GeForce FX 5600 Ultra]"; +static const char pci_device_10de_0312[] = "NV31 [GeForce FX 5600]"; +static const char pci_device_10de_0313[] = "NV31"; +static const char pci_device_10de_0314[] = "NV31 [GeForce FX 5600XT]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0314_1043_814a[] = "V9560XT/TD"; +#endif +static const char pci_device_10de_0316[] = "NV31M"; +static const char pci_device_10de_0317[] = "NV31M Pro"; +static const char pci_device_10de_031a[] = "NV31M [GeForce FX Go5600]"; +static const char pci_device_10de_031b[] = "NV31M [GeForce FX Go5650]"; +static const char pci_device_10de_031c[] = "NVIDIA Quadro FX Go700"; +static const char pci_device_10de_031d[] = "NV31GLM"; +static const char pci_device_10de_031e[] = "NV31GLM Pro"; +static const char pci_device_10de_031f[] = "NV31GLM Pro"; +static const char pci_device_10de_0320[] = "NV34 [GeForce FX 5200]"; +static const char pci_device_10de_0321[] = "NV34 [GeForce FX 5200 Ultra]"; +static const char pci_device_10de_0322[] = "NV34 [GeForce FX 5200]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0322_1462_9171[] = "MS-8917 (FX5200-T128)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0322_1462_9360[] = "MS-8936 (FX5200-T128)"; +#endif +static const char pci_device_10de_0323[] = "NV34 [GeForce FX 5200LE]"; +static const char pci_device_10de_0324[] = "NV34M [GeForce FX Go5200]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0324_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0324_1071_8160[] = "MIM2000"; +#endif +static const char pci_device_10de_0325[] = "NV34M [GeForce FX Go5250]"; +static const char pci_device_10de_0326[] = "NV34 [GeForce FX 5500]"; +static const char pci_device_10de_0327[] = "NV34 [GeForce FX 5100]"; +static const char pci_device_10de_0328[] = "NV34M [GeForce FX Go5200 32M/64M]"; +static const char pci_device_10de_0329[] = "NV34M [GeForce FX Go5200]"; +static const char pci_device_10de_032a[] = "NV34GL [Quadro NVS 280 PCI]"; +static const char pci_device_10de_032b[] = "NV34GL [Quadro FX 500/600 PCI]"; +static const char pci_device_10de_032c[] = "NV34GLM [GeForce FX Go 5300]"; +static const char pci_device_10de_032d[] = "NV34 [GeForce FX Go5100]"; +static const char pci_device_10de_032f[] = "NV34GL"; +static const char pci_device_10de_0330[] = "NV35 [GeForce FX 5900 Ultra]"; +static const char pci_device_10de_0331[] = "NV35 [GeForce FX 5900]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0331_1043_8145[] = "V9950GE"; +#endif +static const char pci_device_10de_0332[] = "NV35 [GeForce FX 5900XT]"; +static const char pci_device_10de_0333[] = "NV38 [GeForce FX 5950 Ultra]"; +static const char pci_device_10de_0334[] = "NV35 [GeForce FX 5900ZT]"; +static const char pci_device_10de_0338[] = "NV35GL [Quadro FX 3000]"; +static const char pci_device_10de_033f[] = "NV35GL [Quadro FX 700]"; +static const char pci_device_10de_0341[] = "NV36.1 [GeForce FX 5700 Ultra]"; +static const char pci_device_10de_0342[] = "NV36.2 [GeForce FX 5700]"; +static const char pci_device_10de_0343[] = "NV36 [GeForce FX 5700LE]"; +static const char pci_device_10de_0344[] = "NV36.4 [GeForce FX 5700VE]"; +static const char pci_device_10de_0345[] = "NV36.5"; +static const char pci_device_10de_0347[] = "NV36 [GeForce FX Go5700]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0347_103c_006a[] = "NX9500"; +#endif +static const char pci_device_10de_0348[] = "NV36 [GeForce FX Go5700]"; +static const char pci_device_10de_0349[] = "NV36M Pro"; +static const char pci_device_10de_034b[] = "NV36MAP"; +static const char pci_device_10de_034c[] = "NV36 [Quadro FX Go1000]"; +static const char pci_device_10de_034e[] = "NV36GL [Quadro FX 1100]"; +static const char pci_device_10de_034f[] = "NV36GL"; +static const char pci_device_10de_0360[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0361[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0362[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0363[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0364[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0365[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0366[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0367[] = "MCP55 LPC Bridge"; +static const char pci_device_10de_0368[] = "MCP55 SMBus"; +static const char pci_device_10de_0369[] = "MCP55 Memory Controller"; +static const char pci_device_10de_036a[] = "MCP55 Memory Controller"; +static const char pci_device_10de_036b[] = "MCP55 SMU"; +static const char pci_device_10de_036c[] = "MCP55 USB Controller"; +static const char pci_device_10de_036d[] = "MCP55 USB Controller"; +static const char pci_device_10de_036e[] = "MCP55 IDE"; +static const char pci_device_10de_0370[] = "MCP55 PCI bridge"; +static const char pci_device_10de_0371[] = "MCP55 High Definition Audio"; +static const char pci_device_10de_0372[] = "MCP55 Ethernet"; +static const char pci_device_10de_0373[] = "MCP55 Ethernet"; +static const char pci_device_10de_0374[] = "MCP55 PCI Express bridge"; +static const char pci_device_10de_0375[] = "MCP55 PCI Express bridge"; +static const char pci_device_10de_0376[] = "MCP55 PCI Express bridge"; +static const char pci_device_10de_0377[] = "MCP55 PCI Express bridge"; +static const char pci_device_10de_0378[] = "MCP55 PCI Express bridge"; +static const char pci_device_10de_037a[] = "MCP55 Memory Controller"; +static const char pci_device_10de_037e[] = "MCP55 SATA Controller"; +static const char pci_device_10de_037f[] = "MCP55 SATA Controller"; +static const char pci_device_10de_0391[] = "G70 [GeForce 7600 GT]"; +static const char pci_device_10de_0392[] = "G70 [GeForce 7600 GS]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10de_0392_1462_0622[] = "NX7600GS-T2D256EH"; +#endif +static const char pci_device_10de_0393[] = "G70 [GeForce 7300 GT]"; +static const char pci_device_10de_0398[] = "G70 [GeForce Go 7600]"; +static const char pci_device_10de_039e[] = "Quadro FX 560"; +static const char pci_device_10de_03a0[] = "C55 Host Bridge"; +static const char pci_device_10de_03a1[] = "C55 Host Bridge"; +static const char pci_device_10de_03a2[] = "C55 Host Bridge"; +static const char pci_device_10de_03a3[] = "C55 Host Bridge"; +static const char pci_device_10de_03a4[] = "C55 Host Bridge"; +static const char pci_device_10de_03a5[] = "C55 Host Bridge"; +static const char pci_device_10de_03a6[] = "C55 Host Bridge"; +static const char pci_device_10de_03a7[] = "C55 Host Bridge"; +static const char pci_device_10de_03a8[] = "C55 Memory Controller"; +static const char pci_device_10de_03a9[] = "C55 Memory Controller"; +static const char pci_device_10de_03aa[] = "C55 Memory Controller"; +static const char pci_device_10de_03ab[] = "C55 Memory Controller"; +static const char pci_device_10de_03ac[] = "C55 Memory Controller"; +static const char pci_device_10de_03ad[] = "C55 Memory Controller"; +static const char pci_device_10de_03ae[] = "C55 Memory Controller"; +static const char pci_device_10de_03af[] = "C55 Memory Controller"; +static const char pci_device_10de_03b0[] = "C55 Memory Controller"; +static const char pci_device_10de_03b1[] = "C55 Memory Controller"; +static const char pci_device_10de_03b2[] = "C55 Memory Controller"; +static const char pci_device_10de_03b3[] = "C55 Memory Controller"; +static const char pci_device_10de_03b4[] = "C55 Memory Controller"; +static const char pci_device_10de_03b5[] = "C55 Memory Controller"; +static const char pci_device_10de_03b6[] = "C55 Memory Controller"; +static const char pci_device_10de_03b7[] = "C55 PCI Express bridge"; +static const char pci_device_10de_03b8[] = "C55 PCI Express bridge"; +static const char pci_device_10de_03b9[] = "C55 PCI Express bridge"; +static const char pci_device_10de_03ba[] = "C55 Memory Controller"; +static const char pci_device_10de_03bb[] = "C55 PCI Express bridge"; +static const char pci_device_10de_03d0[] = "GeForce 6100 nForce 430"; +static const char pci_device_10de_03d1[] = "GeForce 6100 nForce 405"; +static const char pci_device_10de_03d2[] = "GeForce 6100 nForce 400"; +static const char pci_device_10de_03d5[] = "GeForce 6100 nForce 420"; +static const char pci_device_10de_03e0[] = "MCP61 LPC Bridge"; +static const char pci_device_10de_03e1[] = "MCP61 LPC Bridge"; +static const char pci_device_10de_03e2[] = "MCP61 LPC Bridge"; +static const char pci_device_10de_03e3[] = "MCP61 LPC Bridge"; +static const char pci_device_10de_03e4[] = "MCP61 High Definition Audio"; +static const char pci_device_10de_03e5[] = "MCP61 Ethernet"; +static const char pci_device_10de_03e6[] = "MCP61 Ethernet"; +static const char pci_device_10de_03e7[] = "MCP61 SATA Controller"; +static const char pci_device_10de_03e8[] = "MCP61 PCI Express bridge"; +static const char pci_device_10de_03e9[] = "MCP61 PCI Express bridge"; +static const char pci_device_10de_03ea[] = "MCP61 Memory Controller"; +static const char pci_device_10de_03eb[] = "MCP61 SMBus"; +static const char pci_device_10de_03ec[] = "MCP61 IDE"; +static const char pci_device_10de_03ee[] = "MCP61 Ethernet"; +static const char pci_device_10de_03ef[] = "MCP61 Ethernet"; +static const char pci_device_10de_03f0[] = "MCP61 High Definition Audio"; +static const char pci_device_10de_03f1[] = "MCP61 USB Controller"; +static const char pci_device_10de_03f2[] = "MCP61 USB Controller"; +static const char pci_device_10de_03f3[] = "MCP61 PCI bridge"; +static const char pci_device_10de_03f4[] = "MCP61 SMU"; +static const char pci_device_10de_03f5[] = "MCP61 Memory Controller"; +static const char pci_device_10de_03f6[] = "MCP61 SATA Controller"; +static const char pci_device_10de_03f7[] = "MCP61 SATA Controller"; +static const char pci_device_10de_0440[] = "MCP65 LPC Bridge"; +static const char pci_device_10de_0441[] = "MCP65 LPC Bridge"; +static const char pci_device_10de_0442[] = "MCP65 LPC Bridge"; +static const char pci_device_10de_0443[] = "MCP65 LPC Bridge"; +static const char pci_device_10de_0444[] = "MCP65 Memory Controller"; +static const char pci_device_10de_0445[] = "MCP65 Memory Controller"; +static const char pci_device_10de_0446[] = "MCP65 SMBus"; +static const char pci_device_10de_0447[] = "MCP65 SMU"; +static const char pci_device_10de_0448[] = "MCP65 IDE"; +static const char pci_device_10de_0449[] = "MCP65 PCI bridge"; +static const char pci_device_10de_044a[] = "MCP65 High Definition Audio"; +static const char pci_device_10de_044b[] = "MCP65 High Definition Audio"; +static const char pci_device_10de_044c[] = "MCP65 AHCI Controller"; +static const char pci_device_10de_044d[] = "MCP65 AHCI Controller"; +static const char pci_device_10de_044e[] = "MCP65 AHCI Controller"; +static const char pci_device_10de_044f[] = "MCP65 AHCI Controller"; +static const char pci_device_10de_0450[] = "MCP65 Ethernet"; +static const char pci_device_10de_0451[] = "MCP65 Ethernet"; +static const char pci_device_10de_0452[] = "MCP65 Ethernet"; +static const char pci_device_10de_0453[] = "MCP65 Ethernet"; +static const char pci_device_10de_0454[] = "MCP65 USB Controller"; +static const char pci_device_10de_0455[] = "MCP65 USB Controller"; +static const char pci_device_10de_0456[] = "MCP65 USB Controller"; +static const char pci_device_10de_0457[] = "MCP65 USB Controller"; +static const char pci_device_10de_0458[] = "MCP65 PCI Express bridge"; +static const char pci_device_10de_0459[] = "MCP65 PCI Express bridge"; +static const char pci_device_10de_045a[] = "MCP65 PCI Express bridge"; +static const char pci_device_10de_045c[] = "MCP65 SATA Controller"; +static const char pci_device_10de_045d[] = "MCP65 SATA Controller"; +static const char pci_device_10de_045e[] = "MCP65 SATA Controller"; +static const char pci_device_10de_045f[] = "MCP65 SATA Controller"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10df[] = "Emulex Corporation"; +static const char pci_device_10df_1ae5[] = "LP6000 Fibre Channel Host Adapter"; +static const char pci_device_10df_f085[] = "LP850 Fibre Channel Host Adapter"; +static const char pci_device_10df_f095[] = "LP952 Fibre Channel Host Adapter"; +static const char pci_device_10df_f098[] = "LP982 Fibre Channel Host Adapter"; +static const char pci_device_10df_f0a1[] = "Thor LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0a5[] = "Thor LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0b5[] = "Viper LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0d1[] = "Helios LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0d5[] = "Helios LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0e1[] = "Zephyr LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0e5[] = "Zephyr LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f0f5[] = "Neptune LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_f700[] = "LP7000 Fibre Channel Host Adapter"; +static const char pci_device_10df_f701[] = "LP7000 Fibre Channel Host Adapter Alternate ID (JX1:2-3, JX2:1-2)"; +static const char pci_device_10df_f800[] = "LP8000 Fibre Channel Host Adapter"; +static const char pci_device_10df_f801[] = "LP8000 Fibre Channel Host Adapter Alternate ID (JX1:2-3, JX2:1-2)"; +static const char pci_device_10df_f900[] = "LP9000 Fibre Channel Host Adapter"; +static const char pci_device_10df_f901[] = "LP9000 Fibre Channel Host Adapter Alternate ID (JX1:2-3, JX2:1-2)"; +static const char pci_device_10df_f980[] = "LP9802 Fibre Channel Host Adapter"; +static const char pci_device_10df_f981[] = "LP9802 Fibre Channel Host Adapter Alternate ID"; +static const char pci_device_10df_f982[] = "LP9802 Fibre Channel Host Adapter Alternate ID"; +static const char pci_device_10df_fa00[] = "Thor-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fb00[] = "Viper LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fc00[] = "Thor-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fc10[] = "Helios-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fc20[] = "Zephyr-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fd00[] = "Helios-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_fe00[] = "Zephyr-X LightPulse Fibre Channel Host Adapter"; +static const char pci_device_10df_ff00[] = "Neptune LightPulse Fibre Channel Host Adapter"; +#endif +static const char pci_vendor_10e0[] = "Integrated Micro Solutions Inc."; +static const char pci_device_10e0_5026[] = "IMS5026/27/28"; +static const char pci_device_10e0_5027[] = "IMS5027"; +static const char pci_device_10e0_5028[] = "IMS5028"; +static const char pci_device_10e0_8849[] = "IMS8849"; +static const char pci_device_10e0_8853[] = "IMS8853"; +static const char pci_device_10e0_9128[] = "IMS9128 [Twin turbo 128]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e1[] = "Tekram Technology Co.,Ltd."; +static const char pci_device_10e1_0391[] = "TRM-S1040"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10e1_0391_10e1_0391[] = "DC-315U SCSI-3 Host Adapter"; +#endif +static const char pci_device_10e1_690c[] = "DC-690c"; +static const char pci_device_10e1_dc29[] = "DC-290"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e2[] = "Aptix Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e3[] = "Tundra Semiconductor Corp."; +static const char pci_device_10e3_0000[] = "CA91C042 [Universe]"; +static const char pci_device_10e3_0108[] = "Tsi108 Host Bridge for Single PowerPC"; +static const char pci_device_10e3_0148[] = "Tsi148 [Tempe]"; +static const char pci_device_10e3_0860[] = "CA91C860 [QSpan]"; +static const char pci_device_10e3_0862[] = "CA91C862A [QSpan-II]"; +static const char pci_device_10e3_8260[] = "CA91L8200B [Dual PCI PowerSpan II]"; +static const char pci_device_10e3_8261[] = "CA91L8260B [Single PCI PowerSpan II]"; +static const char pci_device_10e3_a108[] = "Tsi109 Host Bridge for Dual PowerPC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e4[] = "Tandem Computers"; +static const char pci_device_10e4_8029[] = "Realtek 8029 Network Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e5[] = "Micro Industries Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e6[] = "Gainbery Computer Products Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e7[] = "Vadem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e8[] = "Applied Micro Circuits Corp."; +static const char pci_device_10e8_1072[] = "INES GPIB-PCI (AMCC5920 based)"; +static const char pci_device_10e8_2011[] = "Q-Motion Video Capture/Edit board"; +static const char pci_device_10e8_4750[] = "S5930 [Matchmaker]"; +static const char pci_device_10e8_5920[] = "S5920"; +static const char pci_device_10e8_8043[] = "LANai4.x [Myrinet LANai interface chip]"; +static const char pci_device_10e8_8062[] = "S5933_PARASTATION"; +static const char pci_device_10e8_807d[] = "S5933 [Matchmaker]"; +static const char pci_device_10e8_8088[] = "Kongsberg Spacetec Format Synchronizer"; +static const char pci_device_10e8_8089[] = "Kongsberg Spacetec Serial Output Board"; +static const char pci_device_10e8_809c[] = "S5933_HEPC3"; +static const char pci_device_10e8_80d7[] = "PCI-9112"; +static const char pci_device_10e8_80d9[] = "PCI-9118"; +static const char pci_device_10e8_80da[] = "PCI-9812"; +static const char pci_device_10e8_811a[] = "PCI-IEEE1355-DS-DE Interface"; +static const char pci_device_10e8_814c[] = "Fastcom ESCC-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_8170[] = "S5933 [Matchmaker] (Chipset Development Tool)"; +static const char pci_device_10e8_81e6[] = "Multimedia video controller"; +static const char pci_device_10e8_8291[] = "Fastcom 232/8-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82c4[] = "Fastcom 422/4-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82c5[] = "Fastcom 422/2-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82c6[] = "Fastcom IG422/1-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82c7[] = "Fastcom IG232/2-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82ca[] = "Fastcom 232/4-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_82db[] = "AJA HDNTV HD SDI Framestore"; +static const char pci_device_10e8_82e2[] = "Fastcom DIO24H-PCI (Commtech, Inc.)"; +static const char pci_device_10e8_8851[] = "S5933 on Innes Corp FM Radio Capture card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10e9[] = "Alps Electric Co., Ltd."; +#endif +static const char pci_vendor_10ea[] = "Intergraphics Systems"; +static const char pci_device_10ea_1680[] = "IGA-1680"; +static const char pci_device_10ea_1682[] = "IGA-1682"; +static const char pci_device_10ea_1683[] = "IGA-1683"; +static const char pci_device_10ea_2000[] = "CyberPro 2000"; +static const char pci_device_10ea_2010[] = "CyberPro 2000A"; +static const char pci_device_10ea_5000[] = "CyberPro 5000"; +static const char pci_device_10ea_5050[] = "CyberPro 5050"; +static const char pci_device_10ea_5202[] = "CyberPro 5202"; +static const char pci_device_10ea_5252[] = "CyberPro5252"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10eb[] = "Artists Graphics"; +static const char pci_device_10eb_0101[] = "3GA"; +static const char pci_device_10eb_8111[] = "Twist3 Frame Grabber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ec[] = "Realtek Semiconductor Co., Ltd."; +static const char pci_device_10ec_0139[] = "Zonet Zen3200"; +static const char pci_device_10ec_0883[] = "High Definition Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_0883_1025_1605[] = "TravelMate 5600 series"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_10ec_8029[] = "RTL-8029(AS)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_10b8_2011[] = "EZ-Card (SMC1208)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_10ec_8029[] = "RTL-8029(AS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_1113_1208[] = "EN1208"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_1186_0300[] = "DE-528"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8029_1259_2400[] = "AT-2400"; +#endif +static const char pci_device_10ec_8129[] = "RTL-8129"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8129_10ec_8129[] = "RT8129 Fast Ethernet Adapter"; +#endif +static const char pci_device_10ec_8136[] = "RTL8101E PCI Express Fast Ethernet controller"; +static const char pci_device_10ec_8138[] = "RT8139 (B/C) Cardbus Fast Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8138_10ec_8138[] = "RT8139 (B/C) Fast Ethernet Adapter"; +#endif +static const char pci_device_10ec_8139[] = "RTL-8139/8139C/8139C+"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_0357_000a[] = "TTP-Monitoring Card V2.0"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1025_005a[] = "TravelMate 290"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1025_8920[] = "ALN-325"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1025_8921[] = "ALN-325"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_103c_006a[] = "NX9500"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1043_8109[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_10bd_0320[] = "EP-320X-R"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_10ec_8139[] = "RT8139"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1113_ec01[] = "FNC-0107TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1186_1300[] = "DFE-538TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1186_1320[] = "SN5200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1186_8139[] = "DRN-32TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_11f6_8139[] = "FN22-3(A) LinxPRO Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1259_2500[] = "AT-2500TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1259_2503[] = "AT-2500TX/ACPI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1429_d010[] = "ND010"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1432_9130[] = "EN-9130TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1436_8139[] = "RT8139"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1458_e000[] = "GA-7VM400M/7VT600 Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1462_788c[] = "865PE Neo2-V Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_146c_1439[] = "FE-1439TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1489_6001[] = "GF100TXRII"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1489_6002[] = "GF100TXRA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_149c_139a[] = "LFE-8139ATX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_149c_8139[] = "LFE-8139TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_14cb_0200[] = "LNR-100 Family 10/100 Base-TX Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1695_9001[] = "Onboard RTL8101L 10/100 MBit"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1799_5000[] = "F5D5000 PCI Card/Desktop Network PCI Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_1904_8139[] = "RTL8139D Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_2646_0001[] = "EtheRx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_8e2e_7000[] = "KF-230TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_8e2e_7100[] = "KF-230TX/2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8139_a0a0_0007[] = "ALN-325C"; +#endif +static const char pci_device_10ec_8167[] = "RTL-8169SC Gigabit Ethernet"; +static const char pci_device_10ec_8168[] = "RTL8111/8168B PCI Express Gigabit Ethernet controller"; +static const char pci_device_10ec_8169[] = "RTL-8169 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8169_1025_0079[] = "Aspire 5024WLMi"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8169_1259_c107[] = "CG-LAPCIGT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8169_1371_434e[] = "ProG-2000L"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8169_1458_e000[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_10ec_8169_1462_702c[] = "K8T NEO 2 motherboard"; +#endif +static const char pci_device_10ec_8180[] = "RTL8180L 802.11b MAC"; +static const char pci_device_10ec_8185[] = "RTL-8185 IEEE 802.11a/b/g Wireless LAN Controller"; +static const char pci_device_10ec_8197[] = "SmartLAN56 56K Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ed[] = "Ascii Corporation"; +static const char pci_device_10ed_7310[] = "V7310"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ee[] = "Xilinx Corporation"; +static const char pci_device_10ee_0205[] = "Wildcard TE205P"; +static const char pci_device_10ee_0210[] = "Wildcard TE210P"; +static const char pci_device_10ee_0314[] = "Wildcard TE405P/TE410P (1st Gen)"; +static const char pci_device_10ee_0405[] = "Wildcard TE405P (2nd Gen)"; +static const char pci_device_10ee_0410[] = "Wildcard TE410P (2nd Gen)"; +static const char pci_device_10ee_3fc0[] = "RME Digi96"; +static const char pci_device_10ee_3fc1[] = "RME Digi96/8"; +static const char pci_device_10ee_3fc2[] = "RME Digi96/8 Pro"; +static const char pci_device_10ee_3fc3[] = "RME Digi96/8 Pad"; +static const char pci_device_10ee_3fc4[] = "RME Digi9652 (Hammerfall)"; +static const char pci_device_10ee_3fc5[] = "RME Hammerfall DSP"; +static const char pci_device_10ee_3fc6[] = "RME Hammerfall DSP MADI"; +static const char pci_device_10ee_8381[] = "Ellips Santos Frame Grabber"; +static const char pci_device_10ee_d154[] = "Copley Controls CAN card (PCI-CAN-02)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ef[] = "Racore Computer Products, Inc."; +static const char pci_device_10ef_8154[] = "M815x Token Ring Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f0[] = "Peritek Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f1[] = "Tyan Computer"; +static const char pci_device_10f1_2865[] = "Tyan Thunder K8E S2865"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f2[] = "Achme Computer, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f3[] = "Alaris, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f4[] = "S-MOS Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f5[] = "NKK Corporation"; +static const char pci_device_10f5_a001[] = "NDR4000 [NR4600 Bridge]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f6[] = "Creative Electronic Systems SA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f7[] = "Matsushita Electric Industrial Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f8[] = "Altos India Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10f9[] = "PC Direct"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fa[] = "Truevision"; +static const char pci_device_10fa_000c[] = "TARGA 1000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fb[] = "Thesys Gesellschaft fuer Mikroelektronik mbH"; +static const char pci_device_10fb_186f[] = "TH 6255"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fc[] = "I-O Data Device, Inc."; +static const char pci_device_10fc_0003[] = "Cardbus IDE Controller"; +static const char pci_device_10fc_0005[] = "Cardbus SCSI CBSC II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fd[] = "Soyo Computer, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10fe[] = "Fast Multimedia AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_10ff[] = "NCube"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1100[] = "Jazz Multimedia"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1101[] = "Initio Corporation"; +static const char pci_device_1101_1060[] = "INI-A100U2W"; +static const char pci_device_1101_1622[] = "INI-1623 PCI SATA-II Controller"; +static const char pci_device_1101_9100[] = "INI-9100/9100W"; +static const char pci_device_1101_9400[] = "INI-940"; +static const char pci_device_1101_9401[] = "INI-950"; +static const char pci_device_1101_9500[] = "360P"; +static const char pci_device_1101_9502[] = "Initio INI-9100UW Ultra Wide SCSI Controller INIC-950P chip"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1102[] = "Creative Labs"; +static const char pci_device_1102_0002[] = "SB Live! EMU10k1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_0020[] = "CT4850 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_0021[] = "CT4620 SBLive!"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_002f[] = "SBLive! mainboard implementation"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_100a[] = "SB Live! 5.1 Digital OEM [SB0220]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_4001[] = "E-mu APS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8022[] = "CT4780 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8023[] = "CT4790 SoundBlaster PCI512"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8024[] = "CT4760 SBLive!"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8025[] = "SBLive! Mainboard Implementation"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8026[] = "CT4830 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8027[] = "CT4832 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8028[] = "CT4760 SBLive! OEM version"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8031[] = "CT4831 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8040[] = "CT4760 SBLive!"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8051[] = "CT4850 SBLive! Value"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8061[] = "SBLive! Player 5.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8064[] = "SBLive! 5.1 Model SB0100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8065[] = "SBLive! 5.1 Digital Model SB0220"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0002_1102_8067[] = "SBLive! 5.1 eMicro 28028"; +#endif +static const char pci_device_1102_0004[] = "SB Audigy"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0004_1102_0051[] = "SB0090 Audigy Player"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0004_1102_0053[] = "SB0090 Audigy Player/OEM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0004_1102_0058[] = "SB0090 Audigy Player/OEM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0004_1102_1007[] = "SB0240 Audigy 2 Platinum 6.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0004_1102_2002[] = "SB Audigy 2 ZS (SB0350)"; +#endif +static const char pci_device_1102_0005[] = "SB X-Fi"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0005_1102_0021[] = "X-Fi Platinum"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0005_1102_1003[] = "X-Fi XtremeMusic"; +#endif +static const char pci_device_1102_0006[] = "[SB Live! Value] EMU10k1X"; +static const char pci_device_1102_0007[] = "SB Audigy LS"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0007_1102_0007[] = "SBLive! 24bit"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0007_1102_1001[] = "SB0310 Audigy LS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0007_1102_1002[] = "SB0312 Audigy LS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0007_1102_1006[] = "SB0410 SBLive! 24-bit"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0007_1462_1009[] = "K8N Diamond"; +#endif +static const char pci_device_1102_0008[] = "SB0400 Audigy2 Value"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_0008_1102_0008[] = "EMU0404 Digital Audio System"; +#endif +static const char pci_device_1102_4001[] = "SB Audigy FireWire Port"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_4001_1102_0010[] = "SB Audigy FireWire Port"; +#endif +static const char pci_device_1102_7002[] = "SB Live! Game Port"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_7002_1102_0020[] = "Gameport Joystick"; +#endif +static const char pci_device_1102_7003[] = "SB Audigy Game Port"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_7003_1102_0040[] = "SB Audigy MIDI/Game Port"; +#endif +static const char pci_device_1102_7004[] = "[SB Live! Value] Input device controller"; +static const char pci_device_1102_7005[] = "SB Audigy LS Game Port"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_7005_1102_1001[] = "SB0310 Audigy LS MIDI/Game port"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_7005_1102_1002[] = "SB0312 Audigy LS MIDI/Game port"; +#endif +static const char pci_device_1102_8064[] = "SB0100 [SBLive! 5.1 OEM]"; +static const char pci_device_1102_8938[] = "Ectiva EV1938"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_1033_80e5[] = "SlimTower-Jim (NEC)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_1071_7150[] = "Mitac 7150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_110a_5938[] = "Siemens Scenic Mobile 510PIII"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_13bd_100c[] = "Ceres-C (Sharp, Intel BX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_13bd_100d[] = "Sharp, Intel Banister"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_13bd_100e[] = "TwinHead P09S/P09S3 (Sharp)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_13bd_f6f1[] = "Marlin (Sharp)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_14ff_0e70[] = "P88TE (TWINHEAD INTERNATIONAL Corp)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_14ff_c401[] = "Notebook 9100/9200/2000 (TWINHEAD INTERNATIONAL Corp)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b400[] = "G400 - Geo (AlphaTop (Taiwan))"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b550[] = "G560 (AlphaTop (Taiwan))"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b560[] = "G560 (AlphaTop (Taiwan))"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b700[] = "G700/U700 (AlphaTop (Taiwan))"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b795[] = "G795 (AlphaTop (Taiwan))"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1102_8938_156d_b797[] = "G797 (AlphaTop (Taiwan))"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1103[] = "Triones Technologies, Inc."; +static const char pci_device_1103_0003[] = "HPT343/345/346/363"; +static const char pci_device_1103_0004[] = "HPT366/368/370/370A/372/372N"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0001[] = "HPT370A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0004[] = "HPT366 UDMA66 (r1) / HPT368 UDMA66 (r2) / HPT370 UDMA100 (r3) / HPT370 UDMA100 RAID (r4)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1103_0004_1103_0005[] = "HPT370 UDMA100"; +#endif +static const char pci_device_1103_0005[] = "HPT372A/372N"; +static const char pci_device_1103_0006[] = "HPT302/302N"; +static const char pci_device_1103_0007[] = "HPT371/371N"; +static const char pci_device_1103_0008[] = "HPT374"; +static const char pci_device_1103_0009[] = "HPT372N"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1104[] = "RasterOps Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1105[] = "Sigma Designs, Inc."; +static const char pci_device_1105_1105[] = "REALmagic Xcard MPEG 1/2/3/4 DVD Decoder"; +static const char pci_device_1105_8300[] = "REALmagic Hollywood Plus DVD Decoder"; +static const char pci_device_1105_8400[] = "EM840x REALmagic DVD/MPEG-2 Audio/Video Decoder"; +static const char pci_device_1105_8401[] = "EM8401 REALmagic DVD/MPEG-2 A/V Decoder"; +static const char pci_device_1105_8470[] = "EM8470 REALmagic DVD/MPEG-4 A/V Decoder"; +static const char pci_device_1105_8471[] = "EM8471 REALmagic DVD/MPEG-4 A/V Decoder"; +static const char pci_device_1105_8475[] = "EM8475 REALmagic DVD/MPEG-4 A/V Decoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1105_8475_1105_0001[] = "REALmagic X-Card"; +#endif +static const char pci_device_1105_8476[] = "EM8476 REALmagic DVD/MPEG-4 A/V Decoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1105_8476_127d_0000[] = "CineView II"; +#endif +static const char pci_device_1105_8485[] = "EM8485 REALmagic DVD/MPEG-4 A/V Decoder"; +static const char pci_device_1105_8486[] = "EM8486 REALmagic DVD/MPEG-4 A/V Decoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1106[] = "VIA Technologies, Inc."; +static const char pci_device_1106_0102[] = "Embedded VIA Ethernet Controller"; +static const char pci_device_1106_0130[] = "VT6305 1394.A Controller"; +static const char pci_device_1106_0204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_0208[] = "PT890 Host Bridge"; +static const char pci_device_1106_0238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_0258[] = "PT880 Host Bridge"; +static const char pci_device_1106_0259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_0269[] = "KT880 Host Bridge"; +static const char pci_device_1106_0282[] = "K8T800Pro Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0282_1043_80a3[] = "A8V Deluxe"; +#endif +static const char pci_device_1106_0290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_0293[] = "PM896 Host Bridge"; +static const char pci_device_1106_0296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_0305[] = "VT8363/8365 [KT133/KM133]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0305_1019_0987[] = "K7VZA Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0305_1043_8033[] = "A7V Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0305_1043_803e[] = "A7V-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0305_1043_8042[] = "A7V133/A7V133-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0305_147b_a401[] = "KT7/KT7-RAID/KT7A/KT7A-RAID Mainboard"; +#endif +static const char pci_device_1106_0308[] = "PT894 Host Bridge"; +static const char pci_device_1106_0314[] = "CN700/VN800/P4M800CE/Pro Host Bridge"; +static const char pci_device_1106_0324[] = "CX700 Host Bridge"; +static const char pci_device_1106_0327[] = "P4M890 Host Bridge"; +static const char pci_device_1106_0336[] = "K8M890CE Host Bridge"; +static const char pci_device_1106_0340[] = "PT900 Host Bridge"; +static const char pci_device_1106_0351[] = "VT3351 Host Bridge"; +static const char pci_device_1106_0364[] = "P4M900 Host Bridge"; +static const char pci_device_1106_0391[] = "VT8371 [KX133]"; +static const char pci_device_1106_0501[] = "VT8501 [Apollo MVP4]"; +static const char pci_device_1106_0505[] = "VT82C505"; +static const char pci_device_1106_0561[] = "VT82C576MV"; +static const char pci_device_1106_0571[] = "VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1019_0a81[] = "L7VTA v1.0 Motherboard (KT400-8235)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1043_8052[] = "VT8233A Bus Master ATA100/66/33 IDE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1043_808c[] = "A7V8X / A7V333 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1043_80a1[] = "A7V8X-X motherboard rev. 1.01"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1043_80ed[] = "A7V600/K8V-X/A8V Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1106_0571[] = "VT82C586/B/VT82C686/A/B/VT8233/A/C/VT8235 PIPC Bus Master IDE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1179_0001[] = "Magnia Z310"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1297_f641[] = "FX41 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1458_5002[] = "GA-7VAX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1462_7020[] = "K8T NEO 2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0571_1849_0571[] = "K7VT2/K7VT6 motherboard"; +#endif +static const char pci_device_1106_0576[] = "VT82C576 3V [Apollo Master]"; +static const char pci_device_1106_0585[] = "VT82C585VP [Apollo VP1/VPX]"; +static const char pci_device_1106_0586[] = "VT82C586/A/B PCI-to-ISA [Apollo VP]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0586_1106_0000[] = "MVP3 ISA Bridge"; +#endif +static const char pci_device_1106_0591[] = "VT8237A SATA 2-Port Controller"; +static const char pci_device_1106_0595[] = "VT82C595 [Apollo VP2]"; +static const char pci_device_1106_0596[] = "VT82C596 ISA [Mobile South]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0596_1106_0000[] = "VT82C596/A/B PCI to ISA Bridge"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0596_1458_0596[] = "VT82C596/A/B PCI to ISA Bridge"; +#endif +static const char pci_device_1106_0597[] = "VT82C597 [Apollo VP3]"; +static const char pci_device_1106_0598[] = "VT82C598 [Apollo MVP3]"; +static const char pci_device_1106_0601[] = "VT8601 [Apollo ProMedia]"; +static const char pci_device_1106_0605[] = "VT8605 [ProSavage PM133]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0605_1043_802c[] = "CUV4X mainboard"; +#endif +static const char pci_device_1106_0680[] = "VT82C680 [Apollo P6]"; +static const char pci_device_1106_0686[] = "VT82C686 [Apollo Super South]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1043_802c[] = "CUV4X mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1043_8033[] = "A7V Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1043_803e[] = "A7V-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1043_8040[] = "A7M266 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1043_8042[] = "A7V133/A7V133-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1106_0000[] = "VT82C686/A PCI to ISA Bridge"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1106_0686[] = "VT82C686/A PCI to ISA Bridge"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_1179_0001[] = "Magnia Z310"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0686_147b_a702[] = "KG7-Lite Mainboard"; +#endif +static const char pci_device_1106_0691[] = "VT82C693A/694x [Apollo PRO133x]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0691_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0691_1179_0001[] = "Magnia Z310"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_0691_1458_0691[] = "VT82C691 Apollo Pro System Controller"; +#endif +static const char pci_device_1106_0693[] = "VT82C693 [Apollo Pro Plus]"; +static const char pci_device_1106_0698[] = "VT82C693A [Apollo Pro133 AGP]"; +static const char pci_device_1106_0926[] = "VT82C926 [Amazon]"; +static const char pci_device_1106_1000[] = "VT82C570MV"; +static const char pci_device_1106_1106[] = "VT82C570MV"; +static const char pci_device_1106_1204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_1208[] = "PT890 Host Bridge"; +static const char pci_device_1106_1238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_1258[] = "PT880 Host Bridge"; +static const char pci_device_1106_1259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_1269[] = "KT880 Host Bridge"; +static const char pci_device_1106_1282[] = "K8T800Pro Host Bridge"; +static const char pci_device_1106_1290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_1293[] = "PM896 Host Bridge"; +static const char pci_device_1106_1296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_1308[] = "PT894 Host Bridge"; +static const char pci_device_1106_1314[] = "CN700/VN800/P4M800CE/Pro Host Bridge"; +static const char pci_device_1106_1324[] = "CX700 Host Bridge"; +static const char pci_device_1106_1327[] = "P4M890 Host Bridge"; +static const char pci_device_1106_1336[] = "K8M890CE Host Bridge"; +static const char pci_device_1106_1340[] = "PT900 Host Bridge"; +static const char pci_device_1106_1351[] = "VT3351 Host Bridge"; +static const char pci_device_1106_1364[] = "P4M900 Host Bridge"; +static const char pci_device_1106_1571[] = "VT82C576M/VT82C586"; +static const char pci_device_1106_1595[] = "VT82C595/97 [Apollo VP2/97]"; +static const char pci_device_1106_2204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_2208[] = "PT890 Host Bridge"; +static const char pci_device_1106_2238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_2258[] = "PT880 Host Bridge"; +static const char pci_device_1106_2259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_2269[] = "KT880 Host Bridge"; +static const char pci_device_1106_2282[] = "K8T800Pro Host Bridge"; +static const char pci_device_1106_2290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_2293[] = "PM896 Host Bridge"; +static const char pci_device_1106_2296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_2308[] = "PT894 Host Bridge"; +static const char pci_device_1106_2314[] = "CN700/VN800/P4M800CE/Pro Host Bridge"; +static const char pci_device_1106_2324[] = "CX700 Host Bridge"; +static const char pci_device_1106_2327[] = "P4M890 Host Bridge"; +static const char pci_device_1106_2336[] = "K8M890CE Host Bridge"; +static const char pci_device_1106_2340[] = "PT900 Host Bridge"; +static const char pci_device_1106_2351[] = "VT3351 Host Bridge"; +static const char pci_device_1106_2364[] = "P4M900 Host Bridge"; +static const char pci_device_1106_287a[] = "VT8251 PCI to PCI Bridge"; +static const char pci_device_1106_287b[] = "VT8251 Host Bridge"; +static const char pci_device_1106_287c[] = "VT8251 PCIE Root Port"; +static const char pci_device_1106_287d[] = "VT8251 PCIE Root Port"; +static const char pci_device_1106_287e[] = "VT8251 Ultra VLINK Controller"; +static const char pci_device_1106_3022[] = "CLE266"; +static const char pci_device_1106_3038[] = "VT82xxxxx UHCI USB 1.1 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_0925_1234[] = "USB Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1019_0a81[] = "L7VTA v1.0 Motherboard (KT400-8235)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1043_8080[] = "A7V333 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1043_808c[] = "VT6202 USB2.0 4 port controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1043_80a1[] = "A7V8X-X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1043_80ed[] = "A7V600/K8V-X/A8V Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1179_0001[] = "Magnia Z310"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1458_5004[] = "GA-7VAX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1462_7020[] = "K8T NEO 2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_182d_201d[] = "CN-029 USB2.0 4 port PCI Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3038_1849_3038[] = "K7VT6"; +#endif +static const char pci_device_1106_3040[] = "VT82C586B ACPI"; +static const char pci_device_1106_3043[] = "VT86C100A [Rhine]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3043_10bd_0000[] = "VT86C100A Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3043_1106_0100[] = "VT86C100A Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3043_1186_1400[] = "DFE-530TX rev A"; +#endif +static const char pci_device_1106_3044[] = "IEEE 1394 Host Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_1025_005a[] = "TravelMate 290"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_1043_808a[] = "A8V Deluxe"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_1458_1000[] = "GA-7VT600-1394 Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_1462_207d[] = "K8NGM2 series motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_1462_702d[] = "K8T NEO 2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3044_1462_971d[] = "MS-6917"; +#endif +static const char pci_device_1106_3050[] = "VT82C596 Power Management"; +static const char pci_device_1106_3051[] = "VT82C596 Power Management"; +static const char pci_device_1106_3053[] = "VT6105M [Rhine-III]"; +static const char pci_device_1106_3057[] = "VT82C686 [Apollo Super ACPI]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1019_0987[] = "K7VZA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1043_8033[] = "A7V Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1043_803e[] = "A7V-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1043_8040[] = "A7M266 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1043_8042[] = "A7V133/A7V133-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3057_1179_0001[] = "Magnia Z310"; +#endif +static const char pci_device_1106_3058[] = "VT82C686 AC97 Audio Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_0e11_0097[] = "SoundMax Digital Integrated Audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_0e11_b194[] = "Soundmax integrated digital audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1019_0985[] = "P6VXA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1019_0987[] = "K7VZA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1043_1106[] = "A7V133/A7V133-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1106_4511[] = "Onboard Audio on EP7KXA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1458_7600[] = "Onboard Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1462_3091[] = "MS-6309 Onboard Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_1462_3300[] = "MS-6330 Onboard Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3058_15dd_7609[] = "Onboard Audio"; +#endif +static const char pci_device_1106_3059[] = "VT8233/A/8235/8237 AC97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1019_0a81[] = "L7VTA v1.0 Motherboard (KT400-8235)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1043_8095[] = "A7V8X Motherboard (Realtek ALC650 codec)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1043_80a1[] = "A7V8X-X Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1043_80b0[] = "A7V600/K8V-X/K8V Deluxe motherboard (ADI AD1980 codec [SoundMAX])"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1043_812a[] = "A8V Deluxe motherboard (Realtek ALC850 codec)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1106_3059[] = "L7VMM2 Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1106_4161[] = "K7VT2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1106_4170[] = "PCPartner P4M800-8237R Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1106_4552[] = "Soyo KT-600 Dragon Plus (Realtek ALC 650)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1297_c160[] = "FX41 motherboard (Realtek ALC650 codec)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1458_a002[] = "GA-7VAX Onboard Audio (Realtek ALC650)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1462_0080[] = "K8T NEO 2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1462_3800[] = "KT266 onboard audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_1849_9761[] = "K7VT6 motherboard"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_4005_4710[] = "MSI K7T266 Pro2-RU (MSI-6380 v2) onboard audio (Realtek/ALC 200/200P)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3059_a0a0_01b6[] = "AK77-8XN onboard audio"; +#endif +static const char pci_device_1106_3065[] = "VT6102 [Rhine-II]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1043_80a1[] = "A7V8X-X Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1106_0102[] = "VT6102 [Rhine II] Embeded Ethernet Controller on VT8235"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1186_1400[] = "DFE-530TX rev A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1186_1401[] = "DFE-530TX rev B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_13b9_1421[] = "LD-10/100AL PCI Fast Ethernet Adapter (rev.B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_147b_1c09[] = "NV7 Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1695_3005[] = "VT6103"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1695_300c[] = "Realtek ALC655 sound chip"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3065_1849_3065[] = "K7VT6 motherboard"; +#endif +static const char pci_device_1106_3068[] = "AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3068_1462_309e[] = "MS-6309 Saturn Motherboard"; +#endif +static const char pci_device_1106_3074[] = "VT8233 PCI to ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3074_1043_8052[] = "VT8233A"; +#endif +static const char pci_device_1106_3091[] = "VT8633 [Apollo Pro266]"; +static const char pci_device_1106_3099[] = "VT8366/A/7 [Apollo KT266/A/333]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3099_1043_8064[] = "A7V266-E Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3099_1043_807f[] = "A7V333 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3099_1849_3099[] = "K7VT2 motherboard"; +#endif +static const char pci_device_1106_3101[] = "VT8653 Host Bridge"; +static const char pci_device_1106_3102[] = "VT8662 Host Bridge"; +static const char pci_device_1106_3103[] = "VT8615 Host Bridge"; +static const char pci_device_1106_3104[] = "USB 2.0"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1019_0a81[] = "L7VTA v1.0 Motherboard (KT400-8235)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1043_808c[] = "A7V8X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1043_80a1[] = "A7V8X-X motherboard rev 1.01"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1043_80ed[] = "A7V600/K8V-X/A8V Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1297_f641[] = "FX41 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1458_5004[] = "GA-7VAX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1462_7020[] = "K8T NEO 2 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_182d_201d[] = "CN-029 USB 2.0 4 port PCI Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3104_1849_3104[] = "K7VT6 motherboard"; +#endif +static const char pci_device_1106_3106[] = "VT6105 [Rhine-III]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3106_1186_1403[] = "DFE-530TX rev C"; +#endif +static const char pci_device_1106_3108[] = "S3 Unichrome Pro VGA Adapter"; +static const char pci_device_1106_3109[] = "VT8233C PCI to ISA Bridge"; +static const char pci_device_1106_3112[] = "VT8361 [KLE133] Host Bridge"; +static const char pci_device_1106_3113[] = "VPX/VPX2 PCI to PCI Bridge Controller"; +static const char pci_device_1106_3116[] = "VT8375 [KM266/KL266] Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3116_1297_f641[] = "FX41 motherboard"; +#endif +static const char pci_device_1106_3118[] = "S3 Unichrome Pro VGA Adapter"; +static const char pci_device_1106_3119[] = "VT6120/VT6121/VT6122 Gigabit Ethernet Adapter"; +static const char pci_device_1106_3122[] = "VT8623 [Apollo CLE266] integrated CastleRock graphics"; +static const char pci_device_1106_3123[] = "VT8623 [Apollo CLE266]"; +static const char pci_device_1106_3128[] = "VT8753 [P4X266 AGP]"; +static const char pci_device_1106_3133[] = "VT3133 Host Bridge"; +static const char pci_device_1106_3147[] = "VT8233A ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3147_1043_808c[] = "A7V333 motherboard"; +#endif +static const char pci_device_1106_3148[] = "P4M266 Host Bridge"; +static const char pci_device_1106_3149[] = "VIA VT6420 SATA RAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_1043_80ed[] = "A7V600/K8V Deluxe/K8V-X/A8V Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_1458_b003[] = "GA-7VM400AM(F) Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_1462_7020[] = "K8T Neo 2 Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_147b_1408[] = "KV7"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3149_1849_3149[] = "K7VT6 motherboard"; +#endif +static const char pci_device_1106_3156[] = "P/KN266 Host Bridge"; +static const char pci_device_1106_3164[] = "VT6410 ATA133 RAID controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3164_1043_80f4[] = "P4P800 Mainboard Deluxe ATX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3164_1462_7028[] = "915P/G Neo2"; +#endif +static const char pci_device_1106_3168[] = "VT8374 P4X400 Host Controller/AGP Bridge"; +static const char pci_device_1106_3177[] = "VT8235 ISA Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1019_0a81[] = "L7VTA v1.0 Motherboard (KT400-8235)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1043_808c[] = "A7V8X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1043_80a1[] = "A7V8X-X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1297_f641[] = "FX41 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1458_5001[] = "GA-7VAX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3177_1849_3177[] = "K7VT2 motherboard"; +#endif +static const char pci_device_1106_3178[] = "ProSavageDDR P4N333 Host Bridge"; +static const char pci_device_1106_3188[] = "VT8385 [K8T800 AGP] Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3188_1043_80a3[] = "K8V Deluxe/K8V-X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3188_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +static const char pci_device_1106_3189[] = "VT8377 [KT400/KT600 AGP] Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3189_1043_807f[] = "A7V8X motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3189_1458_5000[] = "GA-7VAX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3189_1849_3189[] = "K7VT6 motherboard"; +#endif +static const char pci_device_1106_3204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_3205[] = "VT8378 [KM400/A] Chipset Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3205_1458_5000[] = "GA-7VM400M Motherboard"; +#endif +static const char pci_device_1106_3208[] = "PT890 Host Bridge"; +static const char pci_device_1106_3213[] = "VPX/VPX2 PCI to PCI Bridge Controller"; +static const char pci_device_1106_3218[] = "K8T800M Host Bridge"; +static const char pci_device_1106_3227[] = "VT8237 ISA bridge [KT600/K8T800/K8T890 South]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3227_1043_80ed[] = "A7V600/K8V-X/A8V Deluxe motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3227_1106_3227[] = "DFI KT600-AL Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3227_1458_5001[] = "GA-7VT600 Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3227_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_3227_1849_3227[] = "K7VT4 motherboard"; +#endif +static const char pci_device_1106_3238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_3249[] = "VT6421 IDE RAID Controller"; +static const char pci_device_1106_324a[] = "CX700 PCI to PCI Bridge"; +static const char pci_device_1106_324b[] = "CX700 Host Bridge"; +static const char pci_device_1106_324e[] = "CX700 Internal Module Bus"; +static const char pci_device_1106_3258[] = "PT880 Host Bridge"; +static const char pci_device_1106_3259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_3269[] = "KT880 Host Bridge"; +static const char pci_device_1106_3282[] = "K8T800Pro Host Bridge"; +static const char pci_device_1106_3287[] = "VT8251 PCI to ISA Bridge"; +static const char pci_device_1106_3288[] = "VIA High Definition Audio Controller"; +static const char pci_device_1106_3290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_3296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_3324[] = "CX700 Host Bridge"; +static const char pci_device_1106_3327[] = "P4M890 Host Bridge"; +static const char pci_device_1106_3336[] = "K8M890CE Host Bridge"; +static const char pci_device_1106_3337[] = "VT8237A PCI to ISA Bridge"; +static const char pci_device_1106_3340[] = "PT900 Host Bridge"; +static const char pci_device_1106_3344[] = "UniChrome Pro IGP"; +static const char pci_device_1106_3349[] = "VT8251 AHCI/SATA 4-Port Controller"; +static const char pci_device_1106_3351[] = "VT3351 Host Bridge"; +static const char pci_device_1106_3364[] = "P4M900 Host Bridge"; +static const char pci_device_1106_337a[] = "VT8237A PCI to PCI Bridge"; +static const char pci_device_1106_337b[] = "VT8237A Host Bridge"; +static const char pci_device_1106_4149[] = "VIA VT6420 (ATA133) Controller"; +static const char pci_device_1106_4204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_4208[] = "PT890 Host Bridge"; +static const char pci_device_1106_4238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_4258[] = "PT880 Host Bridge"; +static const char pci_device_1106_4259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_4269[] = "KT880 Host Bridge"; +static const char pci_device_1106_4282[] = "K8T800Pro Host Bridge"; +static const char pci_device_1106_4290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_4293[] = "PM896 Host Bridge"; +static const char pci_device_1106_4296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_4308[] = "PT894 Host Bridge"; +static const char pci_device_1106_4314[] = "CN700/VN800/P4M800CE/Pro Host Bridge"; +static const char pci_device_1106_4324[] = "CX700 Host Bridge"; +static const char pci_device_1106_4327[] = "P4M890 Host Bridge"; +static const char pci_device_1106_4336[] = "K8M890CE Host Bridge"; +static const char pci_device_1106_4340[] = "PT900 Host Bridge"; +static const char pci_device_1106_4351[] = "VT3351 Host Bridge"; +static const char pci_device_1106_4364[] = "P4M900 Host Bridge"; +static const char pci_device_1106_5030[] = "VT82C596 ACPI [Apollo PRO]"; +static const char pci_device_1106_5208[] = "PT890 I/O APIC Interrupt Controller"; +static const char pci_device_1106_5238[] = "K8T890 I/O APIC Interrupt Controller"; +static const char pci_device_1106_5290[] = "K8M890 I/O APIC Interrupt Controller"; +static const char pci_device_1106_5308[] = "PT894 I/O APIC Interrupt Controller"; +static const char pci_device_1106_5327[] = "P4M890 I/O APIC Interrupt Controller"; +static const char pci_device_1106_5336[] = "K8M890CE I/O APIC Interrupt Controller"; +static const char pci_device_1106_5340[] = "PT900 I/O APIC Interrupt Controller"; +static const char pci_device_1106_5351[] = "VT3351 I/O APIC Interrupt Controller"; +static const char pci_device_1106_5364[] = "P4M900 I/O APIC Interrupt Controller"; +static const char pci_device_1106_6100[] = "VT85C100A [Rhine II]"; +static const char pci_device_1106_6327[] = "P4M890 Security Device"; +static const char pci_device_1106_7204[] = "K8M800 Host Bridge"; +static const char pci_device_1106_7205[] = "VT8378 [S3 UniChrome] Integrated Video"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_7205_1458_d000[] = "Gigabyte GA-7VM400(A)M(F) Motherboard"; +#endif +static const char pci_device_1106_7208[] = "PT890 Host Bridge"; +static const char pci_device_1106_7238[] = "K8T890 Host Bridge"; +static const char pci_device_1106_7258[] = "PT880 Host Bridge"; +static const char pci_device_1106_7259[] = "CN400/PM880 Host Bridge"; +static const char pci_device_1106_7269[] = "KT880 Host Bridge"; +static const char pci_device_1106_7282[] = "K8T800Pro Host Bridge"; +static const char pci_device_1106_7290[] = "K8M890 Host Bridge"; +static const char pci_device_1106_7293[] = "PM896 Host Bridge"; +static const char pci_device_1106_7296[] = "P4M800 Host Bridge"; +static const char pci_device_1106_7308[] = "PT894 Host Bridge"; +static const char pci_device_1106_7314[] = "CN700/VN800/P4M800CE/Pro Host Bridge"; +static const char pci_device_1106_7324[] = "CX700 Host Bridge"; +static const char pci_device_1106_7327[] = "P4M890 Host Bridge"; +static const char pci_device_1106_7336[] = "K8M890CE Host Bridge"; +static const char pci_device_1106_7340[] = "PT900 Host Bridge"; +static const char pci_device_1106_7351[] = "VT3351 Host Bridge"; +static const char pci_device_1106_7364[] = "P4M900 Host Bridge"; +static const char pci_device_1106_8231[] = "VT8231 [PCI-to-ISA Bridge]"; +static const char pci_device_1106_8235[] = "VT8235 ACPI"; +static const char pci_device_1106_8305[] = "VT8363/8365 [KT133/KM133 AGP]"; +static const char pci_device_1106_8324[] = "CX700 PCI to ISA Bridge"; +static const char pci_device_1106_8391[] = "VT8371 [KX133 AGP]"; +static const char pci_device_1106_8501[] = "VT8501 [Apollo MVP4 AGP]"; +static const char pci_device_1106_8596[] = "VT82C596 [Apollo PRO AGP]"; +static const char pci_device_1106_8597[] = "VT82C597 [Apollo VP3 AGP]"; +static const char pci_device_1106_8598[] = "VT82C598/694x [Apollo MVP3/Pro133x AGP]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_8598_1019_0985[] = "P6VXA Motherboard"; +#endif +static const char pci_device_1106_8601[] = "VT8601 [Apollo ProMedia AGP]"; +static const char pci_device_1106_8605[] = "VT8605 [PM133 AGP]"; +static const char pci_device_1106_8691[] = "VT82C691 [Apollo Pro]"; +static const char pci_device_1106_8693[] = "VT82C693 [Apollo Pro Plus] PCI Bridge"; +static const char pci_device_1106_a208[] = "PT890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_a238[] = "K8T890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_a327[] = "P4M890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_a364[] = "P4M900 PCI to PCI Bridge Controller"; +static const char pci_device_1106_b091[] = "VT8633 [Apollo Pro266 AGP]"; +static const char pci_device_1106_b099[] = "VT8366/A/7 [Apollo KT266/A/333 AGP]"; +static const char pci_device_1106_b101[] = "VT8653 AGP Bridge"; +static const char pci_device_1106_b102[] = "VT8362 AGP Bridge"; +static const char pci_device_1106_b103[] = "VT8615 AGP Bridge"; +static const char pci_device_1106_b112[] = "VT8361 [KLE133] AGP Bridge"; +static const char pci_device_1106_b113[] = "VPX/VPX2 I/O APIC Interrupt Controller"; +static const char pci_device_1106_b115[] = "VT8363/8365 [KT133/KM133] PCI Bridge"; +static const char pci_device_1106_b168[] = "VT8235 PCI Bridge"; +static const char pci_device_1106_b188[] = "VT8237 PCI bridge [K8T800/K8T890 South]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1106_b188_147b_1407[] = "KV8-MAX3 motherboard"; +#endif +static const char pci_device_1106_b198[] = "VT8237 PCI Bridge"; +static const char pci_device_1106_b213[] = "VPX/VPX2 I/O APIC Interrupt Controller"; +static const char pci_device_1106_b999[] = "[K8T890 North / VT8237 South] PCI Bridge"; +static const char pci_device_1106_c208[] = "PT890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_c238[] = "K8T890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_c327[] = "P4M890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_c340[] = "PT900 PCI to PCI Bridge Controller"; +static const char pci_device_1106_c364[] = "P4M900 PCI to PCI Bridge Controller"; +static const char pci_device_1106_d104[] = "VT8237 Integrated Fast Ethernet Controller"; +static const char pci_device_1106_d208[] = "PT890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_d213[] = "VPX/VPX2 PCI to PCI Bridge Controller"; +static const char pci_device_1106_d238[] = "K8T890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_d340[] = "PT900 PCI to PCI Bridge Controller"; +static const char pci_device_1106_e208[] = "PT890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_e238[] = "K8T890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_e340[] = "PT900 PCI to PCI Bridge Controller"; +static const char pci_device_1106_f208[] = "PT890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_f238[] = "K8T890 PCI to PCI Bridge Controller"; +static const char pci_device_1106_f340[] = "PT900 PCI to PCI Bridge Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1107[] = "Stratus Computers"; +static const char pci_device_1107_0576[] = "VIA VT82C570MV [Apollo] (Wrong vendor ID!)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1108[] = "Proteon, Inc."; +static const char pci_device_1108_0100[] = "p1690plus_AA"; +static const char pci_device_1108_0101[] = "p1690plus_AB"; +static const char pci_device_1108_0105[] = "P1690Plus"; +static const char pci_device_1108_0108[] = "P1690Plus"; +static const char pci_device_1108_0138[] = "P1690Plus"; +static const char pci_device_1108_0139[] = "P1690Plus"; +static const char pci_device_1108_013c[] = "P1690Plus"; +static const char pci_device_1108_013d[] = "P1690Plus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1109[] = "Cogent Data Technologies, Inc."; +static const char pci_device_1109_1400[] = "EM110TX [EX110TX]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110a[] = "Siemens Nixdorf AG"; +static const char pci_device_110a_0002[] = "Pirahna 2-port"; +static const char pci_device_110a_0005[] = "Tulip controller, power management, switch extender"; +static const char pci_device_110a_0006[] = "FSC PINC (I/O-APIC)"; +static const char pci_device_110a_0015[] = "FSC Multiprocessor Interrupt Controller"; +static const char pci_device_110a_001d[] = "FSC Copernicus Management Controller"; +static const char pci_device_110a_007b[] = "FSC Remote Service Controller, mailbox device"; +static const char pci_device_110a_007c[] = "FSC Remote Service Controller, shared memory device"; +static const char pci_device_110a_007d[] = "FSC Remote Service Controller, SMIC device"; +static const char pci_device_110a_2101[] = "HST SAPHIR V Primary PCI (ISDN/PMx)"; +static const char pci_device_110a_2102[] = "DSCC4 PEB/PEF 20534 DMA Supported Serial Communication Controller with 4 Channels"; +static const char pci_device_110a_2104[] = "Eicon Diva 2.02 compatible passive ISDN card"; +static const char pci_device_110a_3142[] = "SIMATIC NET CP 5613A1 (Profibus Adapter)"; +static const char pci_device_110a_4021[] = "SIMATIC NET CP 5512 (Profibus and MPI Cardbus Adapter)"; +static const char pci_device_110a_4029[] = "SIMATIC NET CP 5613A2 (Profibus Adapter)"; +static const char pci_device_110a_4942[] = "FPGA I-Bus Tracer for MBD"; +static const char pci_device_110a_6120[] = "SZB6120"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110b[] = "Chromatic Research Inc."; +static const char pci_device_110b_0001[] = "Mpact Media Processor"; +static const char pci_device_110b_0004[] = "Mpact 2"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110c[] = "Mini-Max Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110d[] = "Znyx Advanced Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110e[] = "CPU Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_110f[] = "Ross Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1110[] = "Powerhouse Systems"; +static const char pci_device_1110_6037[] = "Firepower Powerized SMP I/O ASIC"; +static const char pci_device_1110_6073[] = "Firepower Powerized SMP I/O ASIC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1111[] = "Santa Cruz Operation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1112[] = "Osicom Technologies Inc"; +static const char pci_device_1112_2200[] = "FDDI Adapter"; +static const char pci_device_1112_2300[] = "Fast Ethernet Adapter"; +static const char pci_device_1112_2340[] = "4 Port Fast Ethernet Adapter"; +static const char pci_device_1112_2400[] = "ATM Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1113[] = "Accton Technology Corporation"; +static const char pci_device_1113_1211[] = "SMC2-1211TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1113_1211_103c_1207[] = "EN-1207D Fast Ethernet Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1113_1211_1113_1211[] = "EN-1207D Fast Ethernet Adapter"; +#endif +static const char pci_device_1113_1216[] = "EN-1216 Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1113_1216_1113_2242[] = "EN2242 10/100 Ethernet Mini-PCI Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1113_1216_111a_1020[] = "SpeedStream 1020 PCI 10/100 Ethernet Adaptor [EN-1207F-TX ?]"; +#endif +static const char pci_device_1113_1217[] = "EN-1217 Ethernet Adapter"; +static const char pci_device_1113_5105[] = "10Mbps Network card"; +static const char pci_device_1113_9211[] = "EN-1207D Fast Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1113_9211_1113_9211[] = "EN-1207D Fast Ethernet Adapter"; +#endif +static const char pci_device_1113_9511[] = "21x4x DEC-Tulip compatible Fast Ethernet"; +static const char pci_device_1113_d301[] = "CPWNA100 (Philips wireless PCMCIA)"; +static const char pci_device_1113_ec02[] = "SMC 1244TX v3"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1114[] = "Atmel Corporation"; +static const char pci_device_1114_0506[] = "at76c506 802.11b Wireless Network Adaptor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1115[] = "3D Labs"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1116[] = "Data Translation"; +static const char pci_device_1116_0022[] = "DT3001"; +static const char pci_device_1116_0023[] = "DT3002"; +static const char pci_device_1116_0024[] = "DT3003"; +static const char pci_device_1116_0025[] = "DT3004"; +static const char pci_device_1116_0026[] = "DT3005"; +static const char pci_device_1116_0027[] = "DT3001-PGL"; +static const char pci_device_1116_0028[] = "DT3003-PGL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1117[] = "Datacube, Inc"; +static const char pci_device_1117_9500[] = "Max-1C SVGA card"; +static const char pci_device_1117_9501[] = "Max-1C image processing"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1118[] = "Berg Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1119[] = "ICP Vortex Computersysteme GmbH"; +static const char pci_device_1119_0000[] = "GDT 6000/6020/6050"; +static const char pci_device_1119_0001[] = "GDT 6000B/6010"; +static const char pci_device_1119_0002[] = "GDT 6110/6510"; +static const char pci_device_1119_0003[] = "GDT 6120/6520"; +static const char pci_device_1119_0004[] = "GDT 6530"; +static const char pci_device_1119_0005[] = "GDT 6550"; +static const char pci_device_1119_0006[] = "GDT 6117/6517"; +static const char pci_device_1119_0007[] = "GDT 6127/6527"; +static const char pci_device_1119_0008[] = "GDT 6537"; +static const char pci_device_1119_0009[] = "GDT 6557/6557-ECC"; +static const char pci_device_1119_000a[] = "GDT 6115/6515"; +static const char pci_device_1119_000b[] = "GDT 6125/6525"; +static const char pci_device_1119_000c[] = "GDT 6535"; +static const char pci_device_1119_000d[] = "GDT 6555"; +static const char pci_device_1119_0010[] = "GDT 6115/6515"; +static const char pci_device_1119_0011[] = "GDT 6125/6525"; +static const char pci_device_1119_0012[] = "GDT 6535"; +static const char pci_device_1119_0013[] = "GDT 6555/6555-ECC"; +static const char pci_device_1119_0100[] = "GDT 6117RP/6517RP"; +static const char pci_device_1119_0101[] = "GDT 6127RP/6527RP"; +static const char pci_device_1119_0102[] = "GDT 6537RP"; +static const char pci_device_1119_0103[] = "GDT 6557RP"; +static const char pci_device_1119_0104[] = "GDT 6111RP/6511RP"; +static const char pci_device_1119_0105[] = "GDT 6121RP/6521RP"; +static const char pci_device_1119_0110[] = "GDT 6117RD/6517RD"; +static const char pci_device_1119_0111[] = "GDT 6127RD/6527RD"; +static const char pci_device_1119_0112[] = "GDT 6537RD"; +static const char pci_device_1119_0113[] = "GDT 6557RD"; +static const char pci_device_1119_0114[] = "GDT 6111RD/6511RD"; +static const char pci_device_1119_0115[] = "GDT 6121RD/6521RD"; +static const char pci_device_1119_0118[] = "GDT 6118RD/6518RD/6618RD"; +static const char pci_device_1119_0119[] = "GDT 6128RD/6528RD/6628RD"; +static const char pci_device_1119_011a[] = "GDT 6538RD/6638RD"; +static const char pci_device_1119_011b[] = "GDT 6558RD/6658RD"; +static const char pci_device_1119_0120[] = "GDT 6117RP2/6517RP2"; +static const char pci_device_1119_0121[] = "GDT 6127RP2/6527RP2"; +static const char pci_device_1119_0122[] = "GDT 6537RP2"; +static const char pci_device_1119_0123[] = "GDT 6557RP2"; +static const char pci_device_1119_0124[] = "GDT 6111RP2/6511RP2"; +static const char pci_device_1119_0125[] = "GDT 6121RP2/6521RP2"; +static const char pci_device_1119_0136[] = "GDT 6113RS/6513RS"; +static const char pci_device_1119_0137[] = "GDT 6123RS/6523RS"; +static const char pci_device_1119_0138[] = "GDT 6118RS/6518RS/6618RS"; +static const char pci_device_1119_0139[] = "GDT 6128RS/6528RS/6628RS"; +static const char pci_device_1119_013a[] = "GDT 6538RS/6638RS"; +static const char pci_device_1119_013b[] = "GDT 6558RS/6658RS"; +static const char pci_device_1119_013c[] = "GDT 6533RS/6633RS"; +static const char pci_device_1119_013d[] = "GDT 6543RS/6643RS"; +static const char pci_device_1119_013e[] = "GDT 6553RS/6653RS"; +static const char pci_device_1119_013f[] = "GDT 6563RS/6663RS"; +static const char pci_device_1119_0166[] = "GDT 7113RN/7513RN/7613RN"; +static const char pci_device_1119_0167[] = "GDT 7123RN/7523RN/7623RN"; +static const char pci_device_1119_0168[] = "GDT 7118RN/7518RN/7518RN"; +static const char pci_device_1119_0169[] = "GDT 7128RN/7528RN/7628RN"; +static const char pci_device_1119_016a[] = "GDT 7538RN/7638RN"; +static const char pci_device_1119_016b[] = "GDT 7558RN/7658RN"; +static const char pci_device_1119_016c[] = "GDT 7533RN/7633RN"; +static const char pci_device_1119_016d[] = "GDT 7543RN/7643RN"; +static const char pci_device_1119_016e[] = "GDT 7553RN/7653RN"; +static const char pci_device_1119_016f[] = "GDT 7563RN/7663RN"; +static const char pci_device_1119_01d6[] = "GDT 4x13RZ"; +static const char pci_device_1119_01d7[] = "GDT 4x23RZ"; +static const char pci_device_1119_01f6[] = "GDT 8x13RZ"; +static const char pci_device_1119_01f7[] = "GDT 8x23RZ"; +static const char pci_device_1119_01fc[] = "GDT 8x33RZ"; +static const char pci_device_1119_01fd[] = "GDT 8x43RZ"; +static const char pci_device_1119_01fe[] = "GDT 8x53RZ"; +static const char pci_device_1119_01ff[] = "GDT 8x63RZ"; +static const char pci_device_1119_0210[] = "GDT 6519RD/6619RD"; +static const char pci_device_1119_0211[] = "GDT 6529RD/6629RD"; +static const char pci_device_1119_0260[] = "GDT 7519RN/7619RN"; +static const char pci_device_1119_0261[] = "GDT 7529RN/7629RN"; +static const char pci_device_1119_02ff[] = "GDT MAXRP"; +static const char pci_device_1119_0300[] = "GDT NEWRX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111a[] = "Efficient Networks, Inc"; +static const char pci_device_111a_0000[] = "155P-MF1 (FPGA)"; +static const char pci_device_111a_0002[] = "155P-MF1 (ASIC)"; +static const char pci_device_111a_0003[] = "ENI-25P ATM"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0003_111a_0000[] = "ENI-25p Miniport ATM Adapter"; +#endif +static const char pci_device_111a_0005[] = "SpeedStream (LANAI)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0001[] = "ENI-3010 ATM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0009[] = "ENI-3060 ADSL (VPI=0)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0101[] = "ENI-3010 ATM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0109[] = "ENI-3060CO ADSL (VPI=0)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0809[] = "ENI-3060 ADSL (VPI=0 or 8)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0909[] = "ENI-3060CO ADSL (VPI=0 or 8)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0005_111a_0a09[] = "ENI-3060 ADSL (VPI=<0..15>)"; +#endif +static const char pci_device_111a_0007[] = "SpeedStream ADSL"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_111a_0007_111a_1001[] = "ENI-3061 ADSL [ASIC]"; +#endif +static const char pci_device_111a_1203[] = "SpeedStream 1023 Wireless PCI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111b[] = "Teledyne Electronic Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111c[] = "Tricord Systems Inc."; +static const char pci_device_111c_0001[] = "Powerbis Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111d[] = "Integrated Device Technology, Inc."; +static const char pci_device_111d_0001[] = "IDT77201/77211 155Mbps ATM SAR Controller [NICStAR]"; +static const char pci_device_111d_0003[] = "IDT77222/77252 155Mbps ATM MICRO ABR SAR Controller"; +static const char pci_device_111d_0004[] = "IDT77V252 155Mbps ATM MICRO ABR SAR Controller"; +static const char pci_device_111d_0005[] = "IDT77V222 155Mbps ATM MICRO ABR SAR Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111e[] = "Eldec"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_111f[] = "Precision Digital Images"; +static const char pci_device_111f_4a47[] = "Precision MX Video engine interface"; +static const char pci_device_111f_5243[] = "Frame capture bus interface"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1120[] = "EMC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1121[] = "Zilog"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1122[] = "Multi-tech Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1123[] = "Excellent Design, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1124[] = "Leutron Vision AG"; +static const char pci_device_1124_2581[] = "Picport Monochrome"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1125[] = "Eurocore"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1126[] = "Vigra"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1127[] = "FORE Systems Inc"; +static const char pci_device_1127_0200[] = "ForeRunner PCA-200 ATM"; +static const char pci_device_1127_0210[] = "PCA-200PC"; +static const char pci_device_1127_0250[] = "ATM"; +static const char pci_device_1127_0300[] = "ForeRunner PCA-200EPC ATM"; +static const char pci_device_1127_0310[] = "ATM"; +static const char pci_device_1127_0400[] = "ForeRunnerHE ATM Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1127_0400_1127_0400[] = "ForeRunnerHE ATM"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1129[] = "Firmworks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112a[] = "Hermes Electronics Company, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112b[] = "Linotype - Hell AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112c[] = "Zenith Data Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112d[] = "Ravicad"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112e[] = "Infomedia Microelectronics Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_112f[] = "Imaging Technology Inc"; +static const char pci_device_112f_0000[] = "MVC IC-PCI"; +static const char pci_device_112f_0001[] = "MVC IM-PCI Video frame grabber/processor"; +static const char pci_device_112f_0008[] = "PC-CamLink PCI framegrabber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1130[] = "Computervision"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1131[] = "Philips Semiconductors"; +static const char pci_device_1131_1561[] = "USB 1.1 Host Controller"; +static const char pci_device_1131_1562[] = "USB 2.0 Host Controller"; +static const char pci_device_1131_3400[] = "SmartPCI56(UCB1500) 56K Modem"; +static const char pci_device_1131_5400[] = "TriMedia TM1000/1100"; +static const char pci_device_1131_5402[] = "TriMedia TM-1300"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_5402_1244_0f00[] = "Fritz!Card DSL"; +#endif +static const char pci_device_1131_5405[] = "TriMedia TM1500"; +static const char pci_device_1131_5406[] = "TriMedia TM1700"; +static const char pci_device_1131_7130[] = "SAA7130 Video Broadcast Decoder"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_102b_48d0[] = "Matrox CronosPlus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1048_226b[] = "ELSA EX-VISION 300TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1131_2001[] = "10MOONS PCI TV CAPTURE CARD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1131_2005[] = "Techcom (India) TV Tuner Card (SSD-TV-670)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1461_050c[] = "Nagase Sangyo TransGear 3000TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1461_10ff[] = "AVerMedia DVD EZMaker"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1461_2108[] = "AverMedia AverTV/305"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_1461_2115[] = "AverMedia AverTV Studio 305"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_153b_1152[] = "Terratec Cinergy 200 TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_185b_c100[] = "Compro VideoMate TV PVR/FM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_185b_c901[] = "Videomate DVB-T200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7130_5168_0138[] = "LifeView FlyVIDEO2000"; +#endif +static const char pci_device_1131_7133[] = "SAA7133/SAA7135 Video Broadcast Decoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_0000_4091[] = "Beholder BeholdTV 409 FM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1019_4cb5[] = "Elitegroup ECS TVP3XP FM1236 Tuner Card (NTSC,FM)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1043_0210[] = "FlyTV mini Asus Digimatrix"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1043_4843[] = "ASUS TV-FM 7133"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1043_4845[] = "TV-FM 7135"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1043_4862[] = "P7131 Dual"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1131_2001[] = "Proteus Pro [philips reference design]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1131_2018[] = "Tiger reference design"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1131_4ee9[] = "MonsterTV Mobile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_11bd_002b[] = "PCTV Stereo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_11bd_002e[] = "PCTV 110i (saa7133)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_12ab_0800[] = "PURPLE TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1421_0335[] = "Instant TV DVB-T Cardbus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1421_1370[] = "Instant TV (saa7135)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1435_7330[] = "VFG7330"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1435_7350[] = "VFG7350"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1461_1044[] = "AVerTVHD MCE A180"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1461_f31f[] = "Avermedia AVerTV GO 007 FM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1462_6231[] = "TV@Anywhere plus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_1489_0214[] = "LifeView FlyTV Platinum FM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_14c0_1212[] = "LifeView FlyTV Platinum Mini2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_153b_1160[] = "Cinergy 250 PCI TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_153b_1162[] = "Terratec Cinergy 400 mobile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_185b_c100[] = "VideoMate TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_5168_0306[] = "LifeView FlyDVB-T DUO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_5168_0319[] = "LifeView FlyDVB Trio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_5168_0502[] = "LifeView FlyDVB-T Duo CardBus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_5168_0520[] = "LifeView FlyDVB Trio CardBus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_5168_1502[] = "LifeView FlyTV CardBus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_5168_2502[] = "LifeView FlyDVB-T CardBus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_5168_2520[] = "LifeView FlyDVB-S Duo CardBus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_5168_3502[] = "LifeView FlyDVB-T Hybrid CardBus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7133_5168_3520[] = "LifeView FlyDVB Trio N CardBus"; +#endif +static const char pci_device_1131_7134[] = "SAA7134/SAA7135HL Video Broadcast Decoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1019_4cb4[] = "Elitegroup ECS TVP3XP FM1216 Tuner Card(PAL-BG,FM)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1043_0210[] = "Digimatrix TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1043_4840[] = "ASUS TV-FM 7134"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1043_4842[] = "TV-FM 7134"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1131_2004[] = "EUROPA V3 reference design"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1131_4e85[] = "SKNet Monster TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1131_6752[] = "EMPRESS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_11bd_002b[] = "PCTV Stereo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_11bd_002d[] = "PCTV 300i DVB-T + PAL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1461_2c00[] = "AverTV Hybrid+FM PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1461_9715[] = "AVerTV Studio 307"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1461_a70a[] = "Avermedia AVerTV 307"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1461_a70b[] = "AverMedia M156 / Medion 2819"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1461_d6ee[] = "Cardbus TV/Radio (E500)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1471_b7e9[] = "AVerTV Cardbus plus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_153b_1142[] = "Terratec Cinergy 400 TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_153b_1143[] = "Terratec Cinergy 600 TV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_153b_1158[] = "Terratec Cinergy 600 TV MK3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1540_9524[] = "ProVideo PV952"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_16be_0003[] = "Medion 7134"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_185b_c200[] = "Compro VideoMate Gold+ Pal"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_185b_c900[] = "Videomate DVB-T300"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1894_a006[] = "KNC One TV-Station DVR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7134_1894_fe01[] = "KNC One TV-Station RDS / Typhoon TV Tuner RDS"; +#endif +static const char pci_device_1131_7145[] = "SAA7145"; +static const char pci_device_1131_7146[] = "SAA7146"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_110a_0000[] = "Fujitsu/Siemens DVB-C card rev1.5"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_110a_ffff[] = "Fujitsu/Siemens DVB-C card rev1.5"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_1131_4f56[] = "KNC1 DVB-S Budget"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_1131_4f60[] = "Fujitsu-Siemens Activy DVB-S Budget Rev AL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_1131_4f61[] = "Activy DVB-S Budget Rev GR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_1131_5f61[] = "Activy DVB-T Budget"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_114b_2003[] = "DVRaptor Video Edit/Capture Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_11bd_0006[] = "DV500 Overlay"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_11bd_000a[] = "DV500 Overlay"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_11bd_000f[] = "DV500 Overlay"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0000[] = "Siemens/Technotrend/Hauppauge DVB card rev1.3 or rev1.5"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0001[] = "Technotrend/Hauppauge DVB card rev1.3 or rev1.6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0002[] = "Technotrend/Hauppauge DVB card rev2.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0003[] = "Technotrend/Hauppauge DVB card rev2.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0004[] = "Technotrend/Hauppauge DVB card rev2.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0006[] = "Technotrend/Hauppauge DVB card rev1.3 or rev1.6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_0008[] = "Technotrend/Hauppauge DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_000a[] = "Octal/Technotrend DVB-C for iTV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1003[] = "Technotrend-Budget/Hauppauge WinTV-NOVA-S DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1004[] = "Technotrend-Budget/Hauppauge WinTV-NOVA-C DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1005[] = "Technotrend-Budget/Hauppauge WinTV-NOVA-T DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_100c[] = "Technotrend-Budget/Hauppauge WinTV-NOVA-CI DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_100f[] = "Technotrend-Budget/Hauppauge WinTV-NOVA-CI DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1011[] = "Technotrend-Budget/Hauppauge WinTV-NOVA-T DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1013[] = "SATELCO Multimedia DVB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1016[] = "WinTV-NOVA-SE DVB card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_13c2_1102[] = "Technotrend/Hauppauge DVB card rev2.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_7146_153b_1156[] = "Terratec Cynergy 1200C"; +#endif +static const char pci_device_1131_9730[] = "SAA9730 Integrated Multimedia and Peripheral Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1131_9730_1131_0000[] = "Integrated Multimedia and Peripheral Controller"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1132[] = "Mitel Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1133[] = "Eicon Networks Corporation"; +static const char pci_device_1133_7901[] = "EiconCard S90"; +static const char pci_device_1133_7902[] = "EiconCard S90"; +static const char pci_device_1133_7911[] = "EiconCard S91"; +static const char pci_device_1133_7912[] = "EiconCard S91"; +static const char pci_device_1133_7941[] = "EiconCard S94"; +static const char pci_device_1133_7942[] = "EiconCard S94"; +static const char pci_device_1133_7943[] = "EiconCard S94"; +static const char pci_device_1133_7944[] = "EiconCard S94"; +static const char pci_device_1133_b921[] = "EiconCard P92"; +static const char pci_device_1133_b922[] = "EiconCard P92"; +static const char pci_device_1133_b923[] = "EiconCard P92"; +static const char pci_device_1133_e001[] = "Diva Pro 2.0 S/T"; +static const char pci_device_1133_e002[] = "Diva 2.0 S/T PCI"; +static const char pci_device_1133_e003[] = "Diva Pro 2.0 U"; +static const char pci_device_1133_e004[] = "Diva 2.0 U PCI"; +static const char pci_device_1133_e005[] = "Diva 2.01 S/T PCI"; +static const char pci_device_1133_e006[] = "Diva CT S/T PCI"; +static const char pci_device_1133_e007[] = "Diva CT U PCI"; +static const char pci_device_1133_e008[] = "Diva CT Lite S/T PCI"; +static const char pci_device_1133_e009[] = "Diva CT Lite U PCI"; +static const char pci_device_1133_e00a[] = "Diva ISDN+V.90 PCI"; +static const char pci_device_1133_e00b[] = "Diva 2.02 PCI S/T"; +static const char pci_device_1133_e00c[] = "Diva 2.02 PCI U"; +static const char pci_device_1133_e00d[] = "Diva ISDN Pro 3.0 PCI"; +static const char pci_device_1133_e00e[] = "Diva ISDN+CT S/T PCI Rev 2"; +static const char pci_device_1133_e010[] = "Diva Server BRI-2M PCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e010_110a_0021[] = "Fujitsu Siemens ISDN S0"; +#endif +static const char pci_device_1133_e011[] = "Diva Server BRI S/T Rev 2"; +static const char pci_device_1133_e012[] = "Diva Server 4BRI-8M PCI"; +static const char pci_device_1133_e013[] = "Diva Server 4BRI Rev 2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e013_1133_1300[] = "Diva Server V-4BRI-8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e013_1133_e013[] = "Diva Server 4BRI-8M 2.0 PCI"; +#endif +static const char pci_device_1133_e014[] = "Diva Server PRI-30M PCI"; +static const char pci_device_1133_e015[] = "DIVA Server PRI Rev 2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e015_1133_e015[] = "Diva Server PRI 2.0 PCI"; +#endif +static const char pci_device_1133_e016[] = "Diva Server Voice 4BRI PCI"; +static const char pci_device_1133_e017[] = "Diva Server Voice 4BRI Rev 2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e017_1133_e017[] = "Diva Server Voice 4BRI-8M 2.0 PCI"; +#endif +static const char pci_device_1133_e018[] = "Diva Server BRI-2M 2.0 PCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e018_1133_1800[] = "Diva Server V-BRI-2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e018_1133_e018[] = "Diva Server BRI-2M 2.0 PCI"; +#endif +static const char pci_device_1133_e019[] = "Diva Server Voice PRI Rev 2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e019_1133_e019[] = "Diva Server Voice PRI 2.0 PCI"; +#endif +static const char pci_device_1133_e01a[] = "Diva Server 2FX"; +static const char pci_device_1133_e01b[] = "Diva Server Voice BRI-2M 2.0 PCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01b_1133_e01b[] = "Diva Server Voice BRI-2M 2.0 PCI"; +#endif +static const char pci_device_1133_e01c[] = "Diva Server PRI Rev 3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c01[] = "Diva Server PRI/E1/T1-8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c02[] = "Diva Server PRI/T1-24"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c03[] = "Diva Server PRI/E1-30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c04[] = "Diva Server PRI/E1/T1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c05[] = "Diva Server V-PRI/T1-24"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c06[] = "Diva Server V-PRI/E1-30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c07[] = "Diva Server PRI/E1/T1-8 Cornet NQ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c08[] = "Diva Server PRI/T1-24 Cornet NQ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c09[] = "Diva Server PRI/E1-30 Cornet NQ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c0a[] = "Diva Server PRI/E1/T1 Cornet NQ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c0b[] = "Diva Server V-PRI/T1-24 Cornet NQ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e01c_1133_1c0c[] = "Diva Server V-PRI/E1-30 Cornet NQ"; +#endif +static const char pci_device_1133_e01e[] = "Diva Server 2PRI"; +static const char pci_device_1133_e020[] = "Diva Server 4PRI"; +static const char pci_device_1133_e022[] = "Diva Server Analog-2P"; +static const char pci_device_1133_e024[] = "Diva Server Analog-4P"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e024_1133_2400[] = "Diva Server V-Analog-4P"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e024_1133_e024[] = "Diva Server Analog-4P"; +#endif +static const char pci_device_1133_e028[] = "Diva Server Analog-8P"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e028_1133_2800[] = "Diva Server V-Analog-8P"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1133_e028_1133_e028[] = "Diva Server Analog-8P"; +#endif +static const char pci_device_1133_e02a[] = "Diva Server IPM-300"; +static const char pci_device_1133_e02c[] = "Diva Server IPM-600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1134[] = "Mercury Computer Systems"; +static const char pci_device_1134_0001[] = "Raceway Bridge"; +static const char pci_device_1134_0002[] = "Dual PCI to RapidIO Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1135[] = "Fuji Xerox Co Ltd"; +static const char pci_device_1135_0001[] = "Printer controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1136[] = "Momentum Data Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1137[] = "Cisco Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1138[] = "Ziatech Corporation"; +static const char pci_device_1138_8905[] = "8905 [STD 32 Bridge]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1139[] = "Dynamic Pictures, Inc"; +static const char pci_device_1139_0001[] = "VGA Compatable 3D Graphics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113a[] = "FWB Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113b[] = "Network Computing Devices"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113c[] = "Cyclone Microsystems, Inc."; +static const char pci_device_113c_0000[] = "PCI-9060 i960 Bridge"; +static const char pci_device_113c_0001[] = "PCI-SDK [PCI i960 Evaluation Platform]"; +static const char pci_device_113c_0911[] = "PCI-911 [i960Jx-based Intelligent I/O Controller]"; +static const char pci_device_113c_0912[] = "PCI-912 [i960CF-based Intelligent I/O Controller]"; +static const char pci_device_113c_0913[] = "PCI-913"; +static const char pci_device_113c_0914[] = "PCI-914 [I/O Controller w/ secondary PCI bus]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113d[] = "Leading Edge Products Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113e[] = "Sanyo Electric Co - Computer Engineering Dept"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_113f[] = "Equinox Systems, Inc."; +static const char pci_device_113f_0808[] = "SST-64P Adapter"; +static const char pci_device_113f_1010[] = "SST-128P Adapter"; +static const char pci_device_113f_80c0[] = "SST-16P DB Adapter"; +static const char pci_device_113f_80c4[] = "SST-16P RJ Adapter"; +static const char pci_device_113f_80c8[] = "SST-16P Adapter"; +static const char pci_device_113f_8888[] = "SST-4P Adapter"; +static const char pci_device_113f_9090[] = "SST-8P Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1140[] = "Intervoice Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1141[] = "Crest Microsystem Inc"; +#endif +static const char pci_vendor_1142[] = "Alliance Semiconductor Corporation"; +static const char pci_device_1142_3210[] = "AP6410"; +static const char pci_device_1142_6422[] = "ProVideo 6422"; +static const char pci_device_1142_6424[] = "ProVideo 6424"; +static const char pci_device_1142_6425[] = "ProMotion AT25"; +static const char pci_device_1142_643d[] = "ProMotion AT3D"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1143[] = "NetPower, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1144[] = "Cincinnati Milacron"; +static const char pci_device_1144_0001[] = "Noservo controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1145[] = "Workbit Corporation"; +static const char pci_device_1145_8007[] = "NinjaSCSI-32 Workbit"; +static const char pci_device_1145_f007[] = "NinjaSCSI-32 KME"; +static const char pci_device_1145_f010[] = "NinjaSCSI-32 Workbit"; +static const char pci_device_1145_f012[] = "NinjaSCSI-32 Logitec"; +static const char pci_device_1145_f013[] = "NinjaSCSI-32 Logitec"; +static const char pci_device_1145_f015[] = "NinjaSCSI-32 Melco"; +static const char pci_device_1145_f020[] = "NinjaSCSI-32 Sony PCGA-DVD51"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1146[] = "Force Computers"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1147[] = "Interface Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1148[] = "SysKonnect"; +static const char pci_device_1148_4000[] = "FDDI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03b[] = "Netelligent 100 FDDI DAS Fibre SC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03c[] = "Netelligent 100 FDDI SAS Fibre SC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03d[] = "Netelligent 100 FDDI DAS UTP"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03e[] = "Netelligent 100 FDDI SAS UTP"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_0e11_b03f[] = "Netelligent 100 FDDI SAS Fibre MIC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5521[] = "FDDI SK-5521 (SK-NET FDDI-UP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5522[] = "FDDI SK-5522 (SK-NET FDDI-UP DAS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5541[] = "FDDI SK-5541 (SK-NET FDDI-FP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5543[] = "FDDI SK-5543 (SK-NET FDDI-LP)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5544[] = "FDDI SK-5544 (SK-NET FDDI-LP DAS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5821[] = "FDDI SK-5821 (SK-NET FDDI-UP64)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5822[] = "FDDI SK-5822 (SK-NET FDDI-UP64 DAS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5841[] = "FDDI SK-5841 (SK-NET FDDI-FP64)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5843[] = "FDDI SK-5843 (SK-NET FDDI-LP64)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4000_1148_5844[] = "FDDI SK-5844 (SK-NET FDDI-LP64 DAS)"; +#endif +static const char pci_device_1148_4200[] = "Token Ring adapter"; +static const char pci_device_1148_4300[] = "SK-9872 Gigabit Ethernet Server Adapter (SK-NET GE-ZX dual link)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9821[] = "SK-9821 Gigabit Ethernet Server Adapter (SK-NET GE-T)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9822[] = "SK-9822 Gigabit Ethernet Server Adapter (SK-NET GE-T dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9841[] = "SK-9841 Gigabit Ethernet Server Adapter (SK-NET GE-LX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9842[] = "SK-9842 Gigabit Ethernet Server Adapter (SK-NET GE-LX dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9843[] = "SK-9843 Gigabit Ethernet Server Adapter (SK-NET GE-SX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9844[] = "SK-9844 Gigabit Ethernet Server Adapter (SK-NET GE-SX dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9861[] = "SK-9861 Gigabit Ethernet Server Adapter (SK-NET GE-SX Volition)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9862[] = "SK-9862 Gigabit Ethernet Server Adapter (SK-NET GE-SX Volition dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9871[] = "SK-9871 Gigabit Ethernet Server Adapter (SK-NET GE-ZX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1148_9872[] = "SK-9872 Gigabit Ethernet Server Adapter (SK-NET GE-ZX dual link)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2970[] = "AT-2970SX Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2971[] = "AT-2970LX Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2972[] = "AT-2970TX Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2973[] = "AT-2971SX Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2974[] = "AT-2971T Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2975[] = "AT-2970SX/2SC Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2976[] = "AT-2970LX/2SC Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4300_1259_2977[] = "AT-2970TX/2TX Gigabit Ethernet Adapter"; +#endif +static const char pci_device_1148_4320[] = "SK-9871 V2.0 Gigabit Ethernet 1000Base-ZX Adapter, PCI64, Fiber ZX/SC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0121[] = "Marvell RDK-8001 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0221[] = "Marvell RDK-8002 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0321[] = "Marvell RDK-8003 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0421[] = "Marvell RDK-8004 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0621[] = "Marvell RDK-8006 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0721[] = "Marvell RDK-8007 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0821[] = "Marvell RDK-8008 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_0921[] = "Marvell RDK-8009 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_1121[] = "Marvell RDK-8011 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_1221[] = "Marvell RDK-8012 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_3221[] = "SK-9521 V2.0 10/100/1000Base-T Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5021[] = "SK-9821 V2.0 Gigabit Ethernet 10/100/1000Base-T Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5041[] = "SK-9841 V2.0 Gigabit Ethernet 1000Base-LX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5043[] = "SK-9843 V2.0 Gigabit Ethernet 1000Base-SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5051[] = "SK-9851 V2.0 Gigabit Ethernet 1000Base-SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5061[] = "SK-9861 V2.0 Gigabit Ethernet 1000Base-SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_5071[] = "SK-9871 V2.0 Gigabit Ethernet 1000Base-ZX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_4320_1148_9521[] = "SK-9521 10/100/1000Base-T Adapter"; +#endif +static const char pci_device_1148_4400[] = "SK-9Dxx Gigabit Ethernet Adapter"; +static const char pci_device_1148_4500[] = "SK-9Mxx Gigabit Ethernet Adapter"; +static const char pci_device_1148_9000[] = "SK-9S21 10/100/1000Base-T Server Adapter, PCI-X, Copper RJ-45"; +static const char pci_device_1148_9843[] = "[Fujitsu] Gigabit Ethernet"; +static const char pci_device_1148_9e00[] = "SK-9E21D 10/100/1000Base-T Adapter, Copper RJ-45"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_2100[] = "SK-9E21 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_21d0[] = "SK-9E21D 10/100/1000Base-T Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_2200[] = "SK-9E22 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_8100[] = "SK-9E81 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_8200[] = "SK-9E82 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_9100[] = "SK-9E91 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1148_9e00_1148_9200[] = "SK-9E92 Server Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1149[] = "Win System Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114a[] = "VMIC"; +static const char pci_device_114a_5579[] = "VMIPCI-5579 (Reflective Memory Card)"; +static const char pci_device_114a_5587[] = "VMIPCI-5587 (Reflective Memory Card)"; +static const char pci_device_114a_6504[] = "VMIC PCI 7755 FPGA"; +static const char pci_device_114a_7587[] = "VMIVME-7587"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114b[] = "Canopus Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114c[] = "Annabooks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114d[] = "IC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114e[] = "Nikon Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_114f[] = "Digi International"; +static const char pci_device_114f_0002[] = "AccelePort EPC"; +static const char pci_device_114f_0003[] = "RightSwitch SE-6"; +static const char pci_device_114f_0004[] = "AccelePort Xem"; +static const char pci_device_114f_0005[] = "AccelePort Xr"; +static const char pci_device_114f_0006[] = "AccelePort Xr,C/X"; +static const char pci_device_114f_0009[] = "AccelePort Xr/J"; +static const char pci_device_114f_000a[] = "AccelePort EPC/J"; +static const char pci_device_114f_000c[] = "DataFirePRIme T1 (1-port)"; +static const char pci_device_114f_000d[] = "SyncPort 2-Port (x.25/FR)"; +static const char pci_device_114f_0011[] = "AccelePort 8r EIA-232 (IBM)"; +static const char pci_device_114f_0012[] = "AccelePort 8r EIA-422"; +static const char pci_device_114f_0014[] = "AccelePort 8r EIA-422"; +static const char pci_device_114f_0015[] = "AccelePort Xem"; +static const char pci_device_114f_0016[] = "AccelePort EPC/X"; +static const char pci_device_114f_0017[] = "AccelePort C/X"; +static const char pci_device_114f_001a[] = "DataFirePRIme E1 (1-port)"; +static const char pci_device_114f_001b[] = "AccelePort C/X (IBM)"; +static const char pci_device_114f_001d[] = "DataFire RAS T1/E1/PRI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_001d_114f_0050[] = "DataFire RAS E1 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_001d_114f_0051[] = "DataFire RAS Dual E1 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_001d_114f_0052[] = "DataFire RAS T1 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_001d_114f_0053[] = "DataFire RAS Dual T1 Adapter"; +#endif +static const char pci_device_114f_0023[] = "AccelePort RAS"; +static const char pci_device_114f_0024[] = "DataFire RAS B4 ST/U"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_0024_114f_0030[] = "DataFire RAS BRI U Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_114f_0024_114f_0031[] = "DataFire RAS BRI S/T Adapter"; +#endif +static const char pci_device_114f_0026[] = "AccelePort 4r 920"; +static const char pci_device_114f_0027[] = "AccelePort Xr 920"; +static const char pci_device_114f_0028[] = "ClassicBoard 4"; +static const char pci_device_114f_0029[] = "ClassicBoard 8"; +static const char pci_device_114f_0034[] = "AccelePort 2r 920"; +static const char pci_device_114f_0035[] = "DataFire DSP T1/E1/PRI cPCI"; +static const char pci_device_114f_0040[] = "AccelePort Xp"; +static const char pci_device_114f_0042[] = "AccelePort 2p"; +static const char pci_device_114f_0043[] = "AccelePort 4p"; +static const char pci_device_114f_0044[] = "AccelePort 8p"; +static const char pci_device_114f_0045[] = "AccelePort 16p"; +static const char pci_device_114f_004e[] = "AccelePort 32p"; +static const char pci_device_114f_0070[] = "Datafire Micro V IOM2 (Europe)"; +static const char pci_device_114f_0071[] = "Datafire Micro V (Europe)"; +static const char pci_device_114f_0072[] = "Datafire Micro V IOM2 (North America)"; +static const char pci_device_114f_0073[] = "Datafire Micro V (North America)"; +static const char pci_device_114f_00b0[] = "Digi Neo 4"; +static const char pci_device_114f_00b1[] = "Digi Neo 8"; +static const char pci_device_114f_00c8[] = "Digi Neo 2 DB9"; +static const char pci_device_114f_00c9[] = "Digi Neo 2 DB9 PRI"; +static const char pci_device_114f_00ca[] = "Digi Neo 2 RJ45"; +static const char pci_device_114f_00cb[] = "Digi Neo 2 RJ45 PRI"; +static const char pci_device_114f_00d0[] = "ClassicBoard 4 422"; +static const char pci_device_114f_00d1[] = "ClassicBoard 8 422"; +static const char pci_device_114f_6001[] = "Avanstar"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1150[] = "Thinking Machines Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1151[] = "JAE Electronics Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1152[] = "Megatek"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1153[] = "Land Win Electronic Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1154[] = "Melco Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1155[] = "Pine Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1156[] = "Periscope Engineering"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1157[] = "Avsys Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1158[] = "Voarx R & D Inc"; +static const char pci_device_1158_3011[] = "Tokenet/vg 1001/10m anylan"; +static const char pci_device_1158_9050[] = "Lanfleet/Truevalue"; +static const char pci_device_1158_9051[] = "Lanfleet/Truevalue"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1159[] = "Mutech Corp"; +static const char pci_device_1159_0001[] = "MV-1000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115a[] = "Harlequin Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115b[] = "Parallax Graphics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115c[] = "Photron Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115d[] = "Xircom"; +static const char pci_device_115d_0003[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1014_0181[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1014_1181[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1014_8181[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1014_9181[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_115d_0181[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_115d_0182[] = "RealPort2 CardBus Ethernet 10/100 (R2BE-100)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_115d_1181[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_1179_0181[] = "Cardbus Ethernet 10/100"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_8086_8181[] = "EtherExpress PRO/100 Mobile CardBus 32 Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0003_8086_9181[] = "EtherExpress PRO/100 Mobile CardBus 32 Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_115d_0005[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0005_1014_0182[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0005_1014_1182[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0005_115d_0182[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0005_115d_1182[] = "Cardbus Ethernet 10/100"; +#endif +static const char pci_device_115d_0007[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0007_1014_0182[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0007_1014_1182[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0007_115d_0182[] = "Cardbus Ethernet 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0007_115d_1182[] = "Cardbus Ethernet 10/100"; +#endif +static const char pci_device_115d_000b[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_000b_1014_0183[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_000b_115d_0183[] = "Cardbus Ethernet 10/100"; +#endif +static const char pci_device_115d_000c[] = "Mini-PCI V.90 56k Modem"; +static const char pci_device_115d_000f[] = "Cardbus Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_000f_1014_0183[] = "10/100 EtherJet Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_000f_115d_0183[] = "Cardbus Ethernet 10/100"; +#endif +static const char pci_device_115d_00d4[] = "Mini-PCI K56Flex Modem"; +static const char pci_device_115d_0101[] = "Cardbus 56k modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0101_115d_1081[] = "Cardbus 56k Modem"; +#endif +static const char pci_device_115d_0103[] = "Cardbus Ethernet + 56k Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0103_1014_9181[] = "Cardbus 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0103_1115_1181[] = "Cardbus Ethernet 100 + 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0103_115d_1181[] = "CBEM56G-100 Ethernet + 56k Modem"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_115d_0103_8086_9181[] = "PRO/100 LAN + Modem56 CardBus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115e[] = "Peer Protocols Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_115f[] = "Maxtor Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1160[] = "Megasoft Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1161[] = "PFU Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1162[] = "OA Laboratory Co Ltd"; +#endif +static const char pci_vendor_1163[] = "Rendition"; +static const char pci_device_1163_0001[] = "Verite 1000"; +static const char pci_device_1163_2000[] = "Verite V2000/V2100/V2200"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1163_2000_1092_2000[] = "Stealth II S220"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1164[] = "Advanced Peripherals Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1165[] = "Imagraph Corporation"; +static const char pci_device_1165_0001[] = "Motion TPEG Recorder/Player with audio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1166[] = "Broadcom"; +static const char pci_device_1166_0000[] = "CMIC-LE"; +static const char pci_device_1166_0005[] = "CNB20-LE Host Bridge"; +static const char pci_device_1166_0006[] = "CNB20HE Host Bridge"; +static const char pci_device_1166_0007[] = "CNB20-LE Host Bridge"; +static const char pci_device_1166_0008[] = "CNB20HE Host Bridge"; +static const char pci_device_1166_0009[] = "CNB20LE Host Bridge"; +static const char pci_device_1166_0010[] = "CIOB30"; +static const char pci_device_1166_0011[] = "CMIC-HE"; +static const char pci_device_1166_0012[] = "CMIC-WS Host Bridge (GC-LE chipset)"; +static const char pci_device_1166_0013[] = "CNB20-HE Host Bridge"; +static const char pci_device_1166_0014[] = "CMIC-LE Host Bridge (GC-LE chipset)"; +static const char pci_device_1166_0015[] = "CMIC-GC Host Bridge"; +static const char pci_device_1166_0016[] = "CMIC-GC Host Bridge"; +static const char pci_device_1166_0017[] = "GCNB-LE Host Bridge"; +static const char pci_device_1166_0036[] = "HT1000 PCI/PCI-X bridge"; +static const char pci_device_1166_0101[] = "CIOB-X2 PCI-X I/O Bridge"; +static const char pci_device_1166_0103[] = "EPB PCI-Express to PCI-X Bridge"; +static const char pci_device_1166_0104[] = "HT1000 PCI/PCI-X bridge"; +static const char pci_device_1166_0110[] = "CIOB-E I/O Bridge with Gigabit Ethernet"; +static const char pci_device_1166_0130[] = "HT2000 PCI-X bridge"; +static const char pci_device_1166_0132[] = "HT2000 PCI-Express bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0132_1166_0132[] = "HT2000 PCI-Express bridge"; +#endif +static const char pci_device_1166_0140[] = "HT2100 PCI-Express Bridge"; +static const char pci_device_1166_0141[] = "HT2100 PCI-Express Bridge"; +static const char pci_device_1166_0142[] = "HT2100 PCI-Express Bridge"; +static const char pci_device_1166_0200[] = "OSB4 South Bridge"; +static const char pci_device_1166_0201[] = "CSB5 South Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0201_4c53_1080[] = "CT8 mainboard"; +#endif +static const char pci_device_1166_0203[] = "CSB6 South Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0203_1734_1012[] = "Primergy RX300"; +#endif +static const char pci_device_1166_0205[] = "HT1000 Legacy South Bridge"; +static const char pci_device_1166_0211[] = "OSB4 IDE Controller"; +static const char pci_device_1166_0212[] = "CSB5 IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0212_4c53_1080[] = "CT8 mainboard"; +#endif +static const char pci_device_1166_0213[] = "CSB6 RAID/IDE Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0213_1028_4134[] = "PowerEdge 600SC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0213_1028_c134[] = "Poweredge SC600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0213_1734_1012[] = "Primergy RX300"; +#endif +static const char pci_device_1166_0214[] = "HT1000 Legacy IDE controller"; +static const char pci_device_1166_0217[] = "CSB6 IDE Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0217_1028_4134[] = "Poweredge SC600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1166_0220[] = "OSB4/CSB5 OHCI USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0220_4c53_1080[] = "CT8 mainboard"; +#endif +static const char pci_device_1166_0221[] = "CSB6 OHCI USB Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0221_1734_1012[] = "Primergy RX300"; +#endif +static const char pci_device_1166_0223[] = "HT1000 USB Controller"; +static const char pci_device_1166_0225[] = "CSB5 LPC bridge"; +static const char pci_device_1166_0227[] = "GCLE-2 Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0227_1734_1012[] = "Primergy RX300"; +#endif +static const char pci_device_1166_0230[] = "CSB5 LPC bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1166_0230_4c53_1080[] = "CT8 mainboard"; +#endif +static const char pci_device_1166_0234[] = "HT1000 LPC Bridge"; +static const char pci_device_1166_0240[] = "K2 SATA"; +static const char pci_device_1166_0241[] = "RAIDCore RC4000"; +static const char pci_device_1166_0242[] = "RAIDCore BC4000"; +static const char pci_device_1166_024a[] = "BCM5785 (HT1000) SATA Native SATA Mode"; +static const char pci_device_1166_024b[] = "BCM5785 (HT1000) PATA/IDE Mode"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1167[] = "Mutoh Industries Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1168[] = "Thine Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1169[] = "Centre for Development of Advanced Computing"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116a[] = "Polaris Communications"; +static const char pci_device_116a_6100[] = "Bus/Tag Channel"; +static const char pci_device_116a_6800[] = "Escon Channel"; +static const char pci_device_116a_7100[] = "Bus/Tag Channel"; +static const char pci_device_116a_7800[] = "Escon Channel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116b[] = "Connectware Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116c[] = "Intelligent Resources Integrated Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116d[] = "Martin-Marietta"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116e[] = "Electronics for Imaging"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_116f[] = "Workstation Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1170[] = "Inventec Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1171[] = "Loughborough Sound Images Plc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1172[] = "Altera Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1173[] = "Adobe Systems, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1174[] = "Bridgeport Machines"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1175[] = "Mitron Computer Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1176[] = "SBE Incorporated"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1177[] = "Silicon Engineering"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1178[] = "Alfa, Inc."; +static const char pci_device_1178_afa1[] = "Fast Ethernet Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1179[] = "Toshiba America Info Systems"; +static const char pci_device_1179_0102[] = "Extended IDE Controller"; +static const char pci_device_1179_0103[] = "EX-IDE Type-B"; +static const char pci_device_1179_0404[] = "DVD Decoder card"; +static const char pci_device_1179_0406[] = "Tecra Video Capture device"; +static const char pci_device_1179_0407[] = "DVD Decoder card (Version 2)"; +static const char pci_device_1179_0601[] = "CPU to PCI bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1179_0601_1179_0001[] = "Satellite Pro"; +#endif +static const char pci_device_1179_0603[] = "ToPIC95 PCI to CardBus Bridge for Notebooks"; +static const char pci_device_1179_060a[] = "ToPIC95"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1179_060a_1179_0001[] = "Satellite Pro"; +#endif +static const char pci_device_1179_060f[] = "ToPIC97"; +static const char pci_device_1179_0617[] = "ToPIC100 PCI to Cardbus Bridge with ZV Support"; +static const char pci_device_1179_0618[] = "CPU to PCI and PCI to ISA bridge"; +static const char pci_device_1179_0701[] = "FIR Port"; +static const char pci_device_1179_0804[] = "TC6371AF SmartMedia Controller"; +static const char pci_device_1179_0805[] = "SD TypA Controller"; +static const char pci_device_1179_0d01[] = "FIR Port Type-DO"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1179_0d01_1179_0001[] = "FIR Port Type-DO"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117a[] = "A-Trend Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117b[] = "L G Electronics, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117c[] = "Atto Technology"; +static const char pci_device_117c_0030[] = "Ultra320 SCSI Host Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_117c_0030_117c_8013[] = "ExpressPCI UL4D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_117c_0030_117c_8014[] = "ExpressPCI UL4S"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117d[] = "Becton & Dickinson"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117e[] = "T/R Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_117f[] = "Integrated Circuit Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1180[] = "Ricoh Co Ltd"; +static const char pci_device_1180_0465[] = "RL5c465"; +static const char pci_device_1180_0466[] = "RL5c466"; +static const char pci_device_1180_0475[] = "RL5c475"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0475_144d_c006[] = "vpr Matrix 170B4 CardBus bridge"; +#endif +static const char pci_device_1180_0476[] = "RL5c476 II"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_1014_0185[] = "ThinkPad A/T/X Series"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_1028_0188[] = "Inspiron 6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_1043_1967[] = "V6800V"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_1043_1987[] = "Asus A4K and Z81K notebooks, possibly others ( mid-2005 machines )"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_144d_c00c[] = "P35 notebook"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_14ef_0220[] = "PCD-RP-220S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0476_17aa_201c[] = "Thinkpad X60s"; +#endif +static const char pci_device_1180_0477[] = "RL5c477"; +static const char pci_device_1180_0478[] = "RL5c478"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0478_1014_0184[] = "ThinkPad A30p (2653-64G)"; +#endif +static const char pci_device_1180_0511[] = "R5C511"; +static const char pci_device_1180_0522[] = "R5C522 IEEE 1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0522_1014_01cf[] = "ThinkPad A30p (2653-64G)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0522_1043_1967[] = "V6800V"; +#endif +static const char pci_device_1180_0551[] = "R5C551 IEEE 1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0551_144d_c006[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_1180_0552[] = "R5C552 IEEE 1394 Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0552_1014_0511[] = "ThinkPad A/T/X Series"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0552_1028_0188[] = "Inspiron 6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0552_144d_c00c[] = "P35 notebook"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0552_17aa_201e[] = "Thinkpad X60s"; +#endif +static const char pci_device_1180_0554[] = "R5C554"; +static const char pci_device_1180_0575[] = "R5C575 SD Bus Host Adapter"; +static const char pci_device_1180_0576[] = "R5C576 SD Bus Host Adapter"; +static const char pci_device_1180_0592[] = "R5C592 Memory Stick Bus Host Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0592_1043_1967[] = "V6800V"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0592_144d_c018[] = "X20 IV"; +#endif +static const char pci_device_1180_0811[] = "R5C811"; +static const char pci_device_1180_0822[] = "R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0822_1014_0556[] = "Thinkpad X40"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0822_1014_0598[] = "Thinkpad Z60m"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0822_1028_0188[] = "Inspiron 6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0822_1028_01a2[] = "Inspiron 9200"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0822_1043_1967[] = "ASUS V6800V"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0822_144d_c018[] = "X20 IV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0822_17aa_201d[] = "Thinkpad X60s"; +#endif +static const char pci_device_1180_0841[] = "R5C841 CardBus/SD/SDIO/MMC/MS/MSPro/xD/IEEE1394"; +static const char pci_device_1180_0852[] = "xD-Picture Card Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1180_0852_1043_1967[] = "V6800V"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1181[] = "Telmatics International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1183[] = "Fujikura Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1184[] = "Forks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1185[] = "Dataworld International Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1186[] = "D-Link System Inc"; +static const char pci_device_1186_0100[] = "DC21041"; +static const char pci_device_1186_1002[] = "DL10050 Sundance Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_1002_1186_1002[] = "DFE-550TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_1002_1186_1012[] = "DFE-580TX"; +#endif +static const char pci_device_1186_1025[] = "AirPlus Xtreme G DWL-G650 Adapter"; +static const char pci_device_1186_1026[] = "AirXpert DWL-AG650 Wireless Cardbus Adapter"; +static const char pci_device_1186_1043[] = "AirXpert DWL-AG650 Wireless Cardbus Adapter"; +static const char pci_device_1186_1300[] = "RTL8139 Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_1300_1186_1300[] = "DFE-538TX 10/100 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_1300_1186_1301[] = "DFE-530TX+ 10/100 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_1300_1186_1303[] = "DFE-528TX 10/100 Fast Ethernet PCI Adapter"; +#endif +static const char pci_device_1186_1340[] = "DFE-690TXD CardBus PC Card"; +static const char pci_device_1186_1405[] = "DFE-520TX Fast Ethernet PCI Adapter"; +static const char pci_device_1186_1541[] = "DFE-680TXD CardBus PC Card"; +static const char pci_device_1186_1561[] = "DRP-32TXD Cardbus PC Card"; +static const char pci_device_1186_2027[] = "AirPlus Xtreme G DWL-G520 Adapter"; +static const char pci_device_1186_3203[] = "AirPlus Xtreme G DWL-G520 Adapter"; +static const char pci_device_1186_3300[] = "DWL-510 2.4GHz Wireless PCI Adapter"; +static const char pci_device_1186_3a03[] = "AirPro DWL-A650 Wireless Cardbus Adapter(rev.B)"; +static const char pci_device_1186_3a04[] = "AirPro DWL-AB650 Multimode Wireless Cardbus Adapter"; +static const char pci_device_1186_3a05[] = "AirPro DWL-AB520 Multimode Wireless PCI Adapter"; +static const char pci_device_1186_3a07[] = "AirXpert DWL-AG650 Wireless Cardbus Adapter"; +static const char pci_device_1186_3a08[] = "AirXpert DWL-AG520 Wireless PCI Adapter"; +static const char pci_device_1186_3a10[] = "AirXpert DWL-AG650 Wireless Cardbus Adapter(rev.B)"; +static const char pci_device_1186_3a11[] = "AirXpert DWL-AG520 Wireless PCI Adapter(rev.B)"; +static const char pci_device_1186_3a12[] = "AirPlus DWL-G650 Wireless Cardbus Adapter(rev.C)"; +static const char pci_device_1186_3a13[] = "AirPlus DWL-G520 Wireless PCI Adapter(rev.B)"; +static const char pci_device_1186_3a14[] = "AirPremier DWL-AG530 Wireless PCI Adapter"; +static const char pci_device_1186_3a63[] = "AirXpert DWL-AG660 Wireless Cardbus Adapter"; +static const char pci_device_1186_4000[] = "DL2000-based Gigabit Ethernet"; +static const char pci_device_1186_4300[] = "DGE-528T Gigabit Ethernet Adapter"; +static const char pci_device_1186_4800[] = "DGE-530T Gigabit Ethernet Adapter (rev 11)"; +static const char pci_device_1186_4b01[] = "DGE-530T Gigabit Ethernet Adapter (rev 11)"; +static const char pci_device_1186_4c00[] = "Gigabit Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1186_4c00_1186_4c00[] = "DGE-530T Gigabit Ethernet Adapter"; +#endif +static const char pci_device_1186_8400[] = "D-Link DWL-650+ CardBus PC Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1187[] = "Advanced Technology Laboratories, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1188[] = "Shima Seiki Manufacturing Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1189[] = "Matsushita Electronics Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118a[] = "Hilevel Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118b[] = "Hypertec Pty Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118c[] = "Corollary, Inc"; +static const char pci_device_118c_0014[] = "PCIB [C-bus II to PCI bus host bridge chip]"; +static const char pci_device_118c_1117[] = "Intel 8-way XEON Profusion Chipset [Cache Coherency Filter]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118d[] = "BitFlow Inc"; +static const char pci_device_118d_0001[] = "Raptor-PCI framegrabber"; +static const char pci_device_118d_0012[] = "Model 12 Road Runner Frame Grabber"; +static const char pci_device_118d_0014[] = "Model 14 Road Runner Frame Grabber"; +static const char pci_device_118d_0024[] = "Model 24 Road Runner Frame Grabber"; +static const char pci_device_118d_0044[] = "Model 44 Road Runner Frame Grabber"; +static const char pci_device_118d_0112[] = "Model 12 Road Runner Frame Grabber"; +static const char pci_device_118d_0114[] = "Model 14 Road Runner Frame Grabber"; +static const char pci_device_118d_0124[] = "Model 24 Road Runner Frame Grabber"; +static const char pci_device_118d_0144[] = "Model 44 Road Runner Frame Grabber"; +static const char pci_device_118d_0212[] = "Model 12 Road Runner Frame Grabber"; +static const char pci_device_118d_0214[] = "Model 14 Road Runner Frame Grabber"; +static const char pci_device_118d_0224[] = "Model 24 Road Runner Frame Grabber"; +static const char pci_device_118d_0244[] = "Model 44 Road Runner Frame Grabber"; +static const char pci_device_118d_0312[] = "Model 12 Road Runner Frame Grabber"; +static const char pci_device_118d_0314[] = "Model 14 Road Runner Frame Grabber"; +static const char pci_device_118d_0324[] = "Model 24 Road Runner Frame Grabber"; +static const char pci_device_118d_0344[] = "Model 44 Road Runner Frame Grabber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118e[] = "Hermstedt GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_118f[] = "Green Logic"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1190[] = "Tripace"; +static const char pci_device_1190_c731[] = "TP-910/920/940 PCI Ultra(Wide) SCSI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1191[] = "Artop Electronic Corp"; +static const char pci_device_1191_0003[] = "SCSI Cache Host Adapter"; +static const char pci_device_1191_0004[] = "ATP8400"; +static const char pci_device_1191_0005[] = "ATP850UF"; +static const char pci_device_1191_0006[] = "ATP860 NO-BIOS"; +static const char pci_device_1191_0007[] = "ATP860"; +static const char pci_device_1191_0008[] = "ATP865 NO-ROM"; +static const char pci_device_1191_0009[] = "ATP865"; +static const char pci_device_1191_8002[] = "AEC6710 SCSI-2 Host Adapter"; +static const char pci_device_1191_8010[] = "AEC6712UW SCSI"; +static const char pci_device_1191_8020[] = "AEC6712U SCSI"; +static const char pci_device_1191_8030[] = "AEC6712S SCSI"; +static const char pci_device_1191_8040[] = "AEC6712D SCSI"; +static const char pci_device_1191_8050[] = "AEC6712SUW SCSI"; +static const char pci_device_1191_8060[] = "AEC6712 SCSI"; +static const char pci_device_1191_8080[] = "AEC67160 SCSI"; +static const char pci_device_1191_8081[] = "AEC67160S SCSI"; +static const char pci_device_1191_808a[] = "AEC67162 2-ch. LVD SCSI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1192[] = "Densan Company Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1193[] = "Zeitnet Inc."; +static const char pci_device_1193_0001[] = "1221"; +static const char pci_device_1193_0002[] = "1225"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1194[] = "Toucan Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1195[] = "Ratoc System Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1196[] = "Hytec Electronics Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1197[] = "Gage Applied Sciences, Inc."; +static const char pci_device_1197_010c[] = "CompuScope 82G 8bit 2GS/s Analog Input Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1198[] = "Lambda Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1199[] = "Attachmate Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119a[] = "Mind Share, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119b[] = "Omega Micro Inc."; +static const char pci_device_119b_1221[] = "82C092G"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119c[] = "Information Technology Inst."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119d[] = "Bug, Inc. Sapporo Japan"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119e[] = "Fujitsu Microelectronics Ltd."; +static const char pci_device_119e_0001[] = "FireStream 155"; +static const char pci_device_119e_0003[] = "FireStream 50"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_119f[] = "Bull HN Information Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a0[] = "Convex Computer Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a1[] = "Hamamatsu Photonics K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a2[] = "Sierra Research and Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a3[] = "Deuretzbacher GmbH & Co. Eng. KG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a4[] = "Barco Graphics NV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a5[] = "Microunity Systems Eng. Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a6[] = "Pure Data Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a7[] = "Power Computing Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a8[] = "Systech Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11a9[] = "InnoSys Inc."; +static const char pci_device_11a9_4240[] = "AMCC S933Q Intelligent Serial Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11aa[] = "Actel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ab[] = "Marvell Technology Group Ltd."; +static const char pci_device_11ab_0146[] = "GT-64010/64010A System Controller"; +static const char pci_device_11ab_138f[] = "W8300 802.11 Adapter (rev 07)"; +static const char pci_device_11ab_1fa6[] = "Marvell W8300 802.11 Adapter"; +static const char pci_device_11ab_1fa7[] = "88W8310 and 88W8000G [Libertas] 802.11g client chipset"; +static const char pci_device_11ab_1faa[] = "88w8335 [Libertas] 802.11b/g Wireless"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_1faa_1385_4e00[] = "WG511 v2 54MBit/ Wireless PC-Card"; +#endif +static const char pci_device_11ab_4320[] = "88E8001 Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1019_0f38[] = "Marvell 88E8001 Gigabit Ethernet Controller (ECS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1019_8001[] = "Marvell 88E8001 Gigabit Ethernet Controller (ECS)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1043_173c[] = "Marvell 88E8001 Gigabit Ethernet Controller (Asus)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1043_811a[] = "Marvell 88E8001 Gigabit Ethernet Controller (Asus)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_105b_0c19[] = "Marvell 88E8001 Gigabit Ethernet Controller (Foxconn)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_10b8_b452[] = "EZ Card 1000 (SMC9452TXV.2)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_11ab_0121[] = "Marvell RDK-8001"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_11ab_0321[] = "Marvell RDK-8003"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_11ab_1021[] = "Marvell RDK-8010"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_11ab_4320[] = "Marvell Yukon Gigabit Ethernet 10/100/1000Baset-T Constroller (Asus)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_11ab_5021[] = "Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Controller (64 bit)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_11ab_9521[] = "Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Controller (32 bit)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1458_e000[] = "Marvell 88E8001 Gigabit Ethernet Controller (Gigabyte)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_147b_1406[] = "Marvell 88E8001 Gigabit Ethernet Controller (Abit)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_15d4_0047[] = "Marvell 88E8001 Gigabit Ethernet Controller (Iwill)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_1695_9025[] = "Marvell 88E8001 Gigabit Ethernet Controller (Epox)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_17f2_1c03[] = "Marvell 88E8001 Gigabit Ethernet Controller (Albatron)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4320_270f_2803[] = "Marvell 88E8001 Gigabit Ethernet Controller (Chaintech)"; +#endif +static const char pci_device_11ab_4340[] = "88E8021 PCI-X IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4341[] = "88E8022 PCI-X IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4342[] = "88E8061 PCI-E IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4343[] = "88E8062 PCI-E IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4344[] = "88E8021 PCI-X IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4345[] = "88E8022 PCI-X IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4346[] = "88E8061 PCI-E IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4347[] = "88E8062 PCI-E IPMI Gigabit Ethernet Controller"; +static const char pci_device_11ab_4350[] = "88E8035 PCI-E Fast Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1179_0001[] = "Marvell 88E8035 Fast Ethernet Controller (Toshiba)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_11ab_3521[] = "Marvell RDK-8035"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_000d[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_000e[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_000f[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0011[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0012[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0016[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0017[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0018[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0019[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_001c[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_001e[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4350_1854_0020[] = "Marvell 88E8035 Fast Ethernet Controller (LGE)"; +#endif +static const char pci_device_11ab_4351[] = "88E8036 PCI-E Fast Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_107b_4009[] = "Marvell 88E8036 Fast Ethernet Controller (Wistron)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_10f7_8338[] = "Marvell 88E8036 Fast Ethernet Controller (Panasonic)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1179_0001[] = "Marvell 88E8036 Fast Ethernet Controller (Toshiba)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1179_ff00[] = "Marvell 88E8036 Fast Ethernet Controller (Compal)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1179_ff10[] = "Marvell 88E8036 Fast Ethernet Controller (Inventec)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_11ab_3621[] = "Marvell RDK-8036"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_13d1_ac12[] = "Abocom EFE3K - 10/100 Ethernet Expresscard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_161f_203d[] = "Marvell 88E8036 Fast Ethernet Controller (Arima)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_000d[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_000e[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_000f[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0011[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0012[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0016[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0017[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0018[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0019[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_001c[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_001e[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4351_1854_0020[] = "Marvell 88E8036 Fast Ethernet Controller (LGE)"; +#endif +static const char pci_device_11ab_4352[] = "88E8038 PCI-E Fast Ethernet Controller"; +static const char pci_device_11ab_4360[] = "88E8052 PCI-E ASF Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_1043_8134[] = "Marvell 88E8052 Gigabit Ethernet Controller (Asus)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_107b_4009[] = "Marvell 88E8052 Gigabit Ethernet Controller (Wistron)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_11ab_5221[] = "Marvell RDK-8052"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_1458_e000[] = "Marvell 88E8052 Gigabit Ethernet Controller (Gigabyte)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_1462_052c[] = "Marvell 88E8052 Gigabit Ethernet Controller (MSI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_1849_8052[] = "Marvell 88E8052 Gigabit Ethernet Controller (ASRock)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4360_a0a0_0509[] = "Marvell 88E8052 Gigabit Ethernet Controller (Aopen)"; +#endif +static const char pci_device_11ab_4361[] = "88E8050 PCI-E ASF Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4361_107b_3015[] = "Marvell 88E8050 Gigabit Ethernet Controller (Gateway)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4361_11ab_5021[] = "Marvell 88E8050 Gigabit Ethernet Controller (Intel)"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4361_8086_3063[] = "D925XCVLK mainboard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4361_8086_3439[] = "Marvell 88E8050 Gigabit Ethernet Controller (Intel)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_11ab_4362[] = "88E8053 PCI-E Gigabit Ethernet Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_103c_2a0d[] = "Marvell 88E8053 Gigabit Ethernet Controller (Asus)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1043_8142[] = "Marvell 88E8053 Gigabit Ethernet controller PCIe (Asus)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_109f_3197[] = "Marvell 88E8053 Gigabit Ethernet Controller (Trigem)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_10f7_8338[] = "Marvell 88E8053 Gigabit Ethernet Controller (Panasonic)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_10fd_a430[] = "Marvell 88E8053 Gigabit Ethernet Controller (SOYO)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1179_0001[] = "Marvell 88E8053 Gigabit Ethernet Controller (Toshiba)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1179_ff00[] = "Marvell 88E8053 Gigabit Ethernet Controller (Compal)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1179_ff10[] = "Marvell 88E8053 Gigabit Ethernet Controller (Inventec)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_11ab_5321[] = "Marvell RDK-8053"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1297_c240[] = "Marvell 88E8053 Gigabit Ethernet Controller (Shuttle)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1297_c241[] = "Marvell 88E8053 Gigabit Ethernet Controller (Shuttle)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1297_c242[] = "Marvell 88E8053 Gigabit Ethernet Controller (Shuttle)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1297_c243[] = "Marvell 88E8053 Gigabit Ethernet Controller (Shuttle)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1297_c244[] = "Marvell 88E8053 Gigabit Ethernet Controller (Shuttle)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_13d1_ac11[] = "EGE5K - Giga Ethernet Expresscard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1458_e000[] = "Marvell 88E8053 Gigabit Ethernet Controller (Gigabyte)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1462_058c[] = "Marvell 88E8053 Gigabit Ethernet Controller (MSI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_14c0_0012[] = "Marvell 88E8053 Gigabit Ethernet Controller (Compal)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1558_04a0[] = "Marvell 88E8053 Gigabit Ethernet Controller (Clevo)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_15bd_1003[] = "Marvell 88E8053 Gigabit Ethernet Controller (DFI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_161f_203c[] = "Marvell 88E8053 Gigabit Ethernet Controller (Arima)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_161f_203d[] = "Marvell 88E8053 Gigabit Ethernet Controller (Arima)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1695_9029[] = "Marvell 88E8053 Gigabit Ethernet Controller (Epox)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_17f2_2c08[] = "Marvell 88E8053 Gigabit Ethernet Controller (Albatron)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_17ff_0585[] = "Marvell 88E8053 Gigabit Ethernet Controller (Quanta)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1849_8053[] = "Marvell 88E8053 Gigabit Ethernet Controller (ASRock)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_000b[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_000c[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0010[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0013[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0014[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0015[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_001a[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_001b[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_001d[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_001f[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0021[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_1854_0022[] = "Marvell 88E8053 Gigabit Ethernet Controller (LGE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_270f_2801[] = "Marvell 88E8053 Gigabit Ethernet Controller (Chaintech)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ab_4362_a0a0_0506[] = "Marvell 88E8053 Gigabit Ethernet Controller (Aopen)"; +#endif +static const char pci_device_11ab_4363[] = "88E8055 PCI-E Gigabit Ethernet Controller"; +static const char pci_device_11ab_4611[] = "GT-64115 System Controller"; +static const char pci_device_11ab_4620[] = "GT-64120/64120A/64121A System Controller"; +static const char pci_device_11ab_4801[] = "GT-48001"; +static const char pci_device_11ab_5005[] = "Belkin F5D5005 Gigabit Desktop Network PCI Card"; +static const char pci_device_11ab_5040[] = "MV88SX5040 4-port SATA I PCI-X Controller"; +static const char pci_device_11ab_5041[] = "MV88SX5041 4-port SATA I PCI-X Controller"; +static const char pci_device_11ab_5080[] = "MV88SX5080 8-port SATA I PCI-X Controller"; +static const char pci_device_11ab_5081[] = "MV88SX5081 8-port SATA I PCI-X Controller"; +static const char pci_device_11ab_6041[] = "MV88SX6041 4-port SATA II PCI-X Controller"; +static const char pci_device_11ab_6081[] = "MV88SX6081 8-port SATA II PCI-X Controller"; +static const char pci_device_11ab_6460[] = "MV64360/64361/64362 System Controller"; +static const char pci_device_11ab_6480[] = "MV64460/64461/64462 System Controller"; +static const char pci_device_11ab_6485[] = "MV64460/64461/64462 System Controller, Revision B"; +static const char pci_device_11ab_f003[] = "GT-64010 Primary Image Piranha Image Generator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ac[] = "Canon Information Systems Research Aust."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ad[] = "Lite-On Communications Inc"; +static const char pci_device_11ad_0002[] = "LNE100TX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_11ad_0002[] = "LNE100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_11ad_0003[] = "LNE100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_11ad_f003[] = "LNE100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_11ad_ffff[] = "LNE100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_0002_1385_f004[] = "FA310TX"; +#endif +static const char pci_device_11ad_c115[] = "LNE100TX [Linksys EtherFast 10/100]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11ad_c115_11ad_c001[] = "LNE100TX [ver 2.0]"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ae[] = "Aztech System Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11af[] = "Avid Technology Inc."; +static const char pci_device_11af_0001[] = "Cinema"; +static const char pci_device_11af_ee40[] = "Digidesign Audiomedia III"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b0[] = "V3 Semiconductor Inc."; +static const char pci_device_11b0_0002[] = "V300PSC"; +static const char pci_device_11b0_0292[] = "V292PBC [Am29030/40 Bridge]"; +static const char pci_device_11b0_0960[] = "V96xPBC"; +static const char pci_device_11b0_c960[] = "V96DPC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b1[] = "Apricot Computers"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b2[] = "Eastman Kodak"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b3[] = "Barr Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b4[] = "Leitch Technology International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b5[] = "Radstone Technology Plc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b6[] = "United Video Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b7[] = "Motorola"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b8[] = "XPoint Technologies, Inc"; +static const char pci_device_11b8_0001[] = "Quad PeerMaster"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11b9[] = "Pathlight Technology Inc."; +static const char pci_device_11b9_c0ed[] = "SSA Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ba[] = "Videotron Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11bb[] = "Pyramid Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11bc[] = "Network Peripherals Inc"; +static const char pci_device_11bc_0001[] = "NP-PCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11bd[] = "Pinnacle Systems Inc."; +static const char pci_device_11bd_002e[] = "PCTV 40i"; +static const char pci_device_11bd_bede[] = "AV/DV Studio Capture Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11be[] = "International Microcircuits Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11bf[] = "Astrodesign, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c0[] = "Hewlett Packard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c1[] = "Agere Systems"; +static const char pci_device_11c1_0440[] = "56k WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_1033_8015[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_1033_8047[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_1033_804f[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_10cf_102c[] = "LB LT Modem V.90 56k"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_10cf_104a[] = "BIBLO LT Modem 56k"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_10cf_105f[] = "LB2 LT Modem V.90 56k"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_1179_0001[] = "Internal V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_11c1_0440[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_122d_4101[] = "MDP7800-U Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_122d_4102[] = "MDP7800SP-U Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_0040[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_0440[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_0441[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_0450[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_f100[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_13e0_f101[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_144d_2101[] = "LT56PV Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0440_149f_0440[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +static const char pci_device_11c1_0441[] = "56k WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1033_804d[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1033_8065[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1092_0440[] = "Supra 56i"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1179_0001[] = "Internal V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_11c1_0440[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_11c1_0441[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_122d_4100[] = "MDP7800-U Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0040[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0100[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0410[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0420[] = "TelePath Internet 56k WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0440[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_0443[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_13e0_f102[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1416_9804[] = "CommWave 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_141d_0440[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_144f_0441[] = "Lucent 56k V.90 DF Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_144f_0449[] = "Lucent 56k V.90 DF Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_144f_110d[] = "Lucent Win Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1468_0441[] = "Presario 56k V.90 DF Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0441_1668_0440[] = "Lucent Win Modem"; +#endif +static const char pci_device_11c1_0442[] = "56k WinModem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_11c1_0440[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_11c1_0442[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_13e0_0412[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_13e0_0442[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_13fc_2471[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_144d_2104[] = "LT56PT Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_144f_1104[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_149f_0440[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0442_1668_0440[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +static const char pci_device_11c1_0443[] = "LT WinModem"; +static const char pci_device_11c1_0444[] = "LT WinModem"; +static const char pci_device_11c1_0445[] = "LT WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0445_8086_2203[] = "PRO/100+ MiniPCI (probably an Ambit U98.003.C.00 combo card)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0445_8086_2204[] = "PRO/100+ MiniPCI on Armada E500"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_11c1_0446[] = "LT WinModem"; +static const char pci_device_11c1_0447[] = "LT WinModem"; +static const char pci_device_11c1_0448[] = "WinModem 56k"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_1014_0131[] = "Lucent Win Modem"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_1033_8066[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_13e0_0030[] = "56k Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_13e0_0040[] = "LT WinModem 56k Data+Fax+Voice+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0448_1668_2400[] = "LT WinModem 56k (MiniPCI Ethernet+Modem)"; +#endif +static const char pci_device_11c1_0449[] = "WinModem 56k"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_0e11_b14d[] = "56k V.90 Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_13e0_0020[] = "LT WinModem 56k Data+Fax"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_13e0_0041[] = "TelePath Internet 56k WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_1436_0440[] = "Lucent Win Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_144f_0449[] = "Lucent 56k V.90 DFi Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_1468_0410[] = "IBM ThinkPad T23 (2647-4MG)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_1468_0440[] = "Lucent Win Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0449_1468_0449[] = "Presario 56k V.90 DFi Modem"; +#endif +static const char pci_device_11c1_044a[] = "F-1156IV WinModem (V90, 56KFlex)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_044a_10cf_1072[] = "LB Global LT Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_044a_13e0_0012[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_044a_13e0_0042[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_044a_144f_1005[] = "LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd"; +#endif +static const char pci_device_11c1_044b[] = "LT WinModem"; +static const char pci_device_11c1_044c[] = "LT WinModem"; +static const char pci_device_11c1_044d[] = "LT WinModem"; +static const char pci_device_11c1_044e[] = "LT WinModem"; +static const char pci_device_11c1_044f[] = "V90 WildWire Modem"; +static const char pci_device_11c1_0450[] = "LT WinModem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0450_1033_80a8[] = "Versa Note Vxi"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0450_144f_4005[] = "Magnia SG20"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0450_1468_0450[] = "Evo N600c"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_0450_4005_144f[] = "LifeBook C Series"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_11c1_0451[] = "LT WinModem"; +static const char pci_device_11c1_0452[] = "LT WinModem"; +static const char pci_device_11c1_0453[] = "LT WinModem"; +static const char pci_device_11c1_0454[] = "LT WinModem"; +static const char pci_device_11c1_0455[] = "LT WinModem"; +static const char pci_device_11c1_0456[] = "LT WinModem"; +static const char pci_device_11c1_0457[] = "LT WinModem"; +static const char pci_device_11c1_0458[] = "LT WinModem"; +static const char pci_device_11c1_0459[] = "LT WinModem"; +static const char pci_device_11c1_045a[] = "LT WinModem"; +static const char pci_device_11c1_045c[] = "LT WinModem"; +static const char pci_device_11c1_0461[] = "V90 WildWire Modem"; +static const char pci_device_11c1_0462[] = "V90 WildWire Modem"; +static const char pci_device_11c1_0480[] = "Venus Modem (V90, 56KFlex)"; +static const char pci_device_11c1_048c[] = "V.92 56K WinModem"; +static const char pci_device_11c1_048f[] = "V.92 56k WinModem"; +static const char pci_device_11c1_5801[] = "USB"; +static const char pci_device_11c1_5802[] = "USS-312 USB Controller"; +static const char pci_device_11c1_5803[] = "USS-344S USB Controller"; +static const char pci_device_11c1_5811[] = "FW323"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_5811_8086_524c[] = "D865PERL mainboard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_5811_dead_0800[] = "FireWire Host Bus Adapter"; +#endif +static const char pci_device_11c1_8110[] = "T8110 H.100/H.110 TDM switch"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_8110_12d9_000c[] = "E1/T1 PMXc cPCI carrier card"; +#endif +static const char pci_device_11c1_ab10[] = "WL60010 Wireless LAN MAC"; +static const char pci_device_11c1_ab11[] = "WL60040 Multimode Wireles LAN MAC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_ab11_11c1_ab12[] = "WaveLAN 11abg Cardbus card (Model 1102)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_ab11_11c1_ab13[] = "WaveLAN 11abg MiniPCI card (Model 0512)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_ab11_11c1_ab15[] = "WaveLAN 11abg Cardbus card (Model 1106)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_ab11_11c1_ab16[] = "WaveLAN 11abg MiniPCI card (Model 0516)"; +#endif +static const char pci_device_11c1_ab20[] = "ORiNOCO PCI Adapter"; +static const char pci_device_11c1_ab21[] = "Agere Wireless PCI Adapter"; +static const char pci_device_11c1_ab30[] = "Hermes2 Mini-PCI WaveLAN a/b/g"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11c1_ab30_14cd_2012[] = "Hermes2 Mini-PCI WaveLAN a/b/g"; +#endif +static const char pci_device_11c1_ed00[] = "ET-131x PCI-E Ethernet Controller"; +static const char pci_device_11c1_ed01[] = "ET-131x PCI-E Ethernet Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c2[] = "Sand Microelectronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c3[] = "NEC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c4[] = "Document Technologies, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c5[] = "Shiva Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c6[] = "Dainippon Screen Mfg. Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c7[] = "D.C.M. Data Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c8[] = "Dolphin Interconnect Solutions AS"; +static const char pci_device_11c8_0658[] = "PSB32 SCI-Adapter D31x"; +static const char pci_device_11c8_d665[] = "PSB64 SCI-Adapter D32x"; +static const char pci_device_11c8_d667[] = "PSB66 SCI-Adapter D33x"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11c9[] = "Magma"; +static const char pci_device_11c9_0010[] = "16-line serial port w/- DMA"; +static const char pci_device_11c9_0011[] = "4-line serial port w/- DMA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ca[] = "LSI Systems, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11cb[] = "Specialix Research Ltd."; +static const char pci_device_11cb_2000[] = "PCI_9050"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11cb_2000_11cb_0200[] = "SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11cb_2000_11cb_b008[] = "I/O8+"; +#endif +static const char pci_device_11cb_4000[] = "SUPI_1"; +static const char pci_device_11cb_8000[] = "T225"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11cc[] = "Michels & Kleberhoff Computer GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11cd[] = "HAL Computer Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ce[] = "Netaccess"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11cf[] = "Pioneer Electronic Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d0[] = "Lockheed Martin Federal Systems-Manassas"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d1[] = "Auravision"; +static const char pci_device_11d1_01f7[] = "VxP524"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d2[] = "Intercom Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d3[] = "Trancell Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d4[] = "Analog Devices"; +static const char pci_device_11d4_1535[] = "Blackfin BF535 processor"; +static const char pci_device_11d4_1805[] = "SM56 PCI modem"; +static const char pci_device_11d4_1889[] = "AD1889 sound chip"; +static const char pci_device_11d4_1986[] = "AD1986A sound chip"; +static const char pci_device_11d4_5340[] = "AD1881 sound chip"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d5[] = "Ikon Corporation"; +static const char pci_device_11d5_0115[] = "10115"; +static const char pci_device_11d5_0117[] = "10117"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d6[] = "Tekelec Telecom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d7[] = "Trenton Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d8[] = "Image Technologies Development"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11d9[] = "TEC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11da[] = "Novell"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11db[] = "Sega Enterprises Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11dc[] = "Questra Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11dd[] = "Crosfield Electronics Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11de[] = "Zoran Corporation"; +static const char pci_device_11de_6057[] = "ZR36057PQC Video cutting chipset"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6057_1031_7efe[] = "DC10 Plus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6057_1031_fc00[] = "MiroVIDEO DC50, Motion JPEG Capture/CODEC Board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6057_12f8_8a02[] = "Tekram Video Kit"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6057_13ca_4231[] = "JPEG/TV Card"; +#endif +static const char pci_device_11de_6120[] = "ZR36120"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6120_1328_f001[] = "Cinemaster C DVD Decoder"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6120_13c2_0000[] = "MediaFocus Satellite TV Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11de_6120_1de1_9fff[] = "Video Kit C210"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11df[] = "New Wave PDG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e0[] = "Cray Communications A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e1[] = "GEC Plessey Semi Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e2[] = "Samsung Information Systems America"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e3[] = "Quicklogic Corporation"; +static const char pci_device_11e3_0001[] = "COM-ON-AIR Dosch&Amand DECT"; +static const char pci_device_11e3_5030[] = "PC Watchdog"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e4[] = "Second Wave Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e5[] = "IIX Consulting"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e6[] = "Mitsui-Zosen System Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e7[] = "Toshiba America, Elec. Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e8[] = "Digital Processing Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11e9[] = "Highwater Designs Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ea[] = "Elsag Bailey"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11eb[] = "Formation Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ec[] = "Coreco Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ed[] = "Mediamatics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ee[] = "Dome Imaging Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ef[] = "Nicolet Technologies B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f0[] = "Compu-Shack"; +static const char pci_device_11f0_4231[] = "FDDI"; +static const char pci_device_11f0_4232[] = "FASTline UTP Quattro"; +static const char pci_device_11f0_4233[] = "FASTline FO"; +static const char pci_device_11f0_4234[] = "FASTline UTP"; +static const char pci_device_11f0_4235[] = "FASTline-II UTP"; +static const char pci_device_11f0_4236[] = "FASTline-II FO"; +static const char pci_device_11f0_4731[] = "GIGAline"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f1[] = "Symbios Logic Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f2[] = "Picture Tel Japan K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f3[] = "Keithley Metrabyte"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f4[] = "Kinetic Systems Corporation"; +static const char pci_device_11f4_2915[] = "CAMAC controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f5[] = "Computing Devices International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f6[] = "Compex"; +static const char pci_device_11f6_0112[] = "ENet100VG4"; +static const char pci_device_11f6_0113[] = "FreedomLine 100"; +static const char pci_device_11f6_1401[] = "ReadyLink 2000"; +static const char pci_device_11f6_2011[] = "RL100-ATX 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11f6_2011_11f6_2011[] = "RL100-ATX"; +#endif +static const char pci_device_11f6_2201[] = "ReadyLink 100TX (Winbond W89C840)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_11f6_2201_11f6_2011[] = "ReadyLink 100TX"; +#endif +static const char pci_device_11f6_9881[] = "RL100TX Fast Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f7[] = "Scientific Atlanta"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f8[] = "PMC-Sierra Inc."; +static const char pci_device_11f8_7375[] = "PM7375 [LASAR-155 ATM SAR]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11f9[] = "I-Cube Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fa[] = "Kasan Electronics Company, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fb[] = "Datel Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fc[] = "Silicon Magic"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fd[] = "High Street Consultants"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11fe[] = "Comtrol Corporation"; +static const char pci_device_11fe_0001[] = "RocketPort 32 port w/external I/F"; +static const char pci_device_11fe_0002[] = "RocketPort 8 port w/external I/F"; +static const char pci_device_11fe_0003[] = "RocketPort 16 port w/external I/F"; +static const char pci_device_11fe_0004[] = "RocketPort 4 port w/quad cable"; +static const char pci_device_11fe_0005[] = "RocketPort 8 port w/octa cable"; +static const char pci_device_11fe_0006[] = "RocketPort 8 port w/RJ11 connectors"; +static const char pci_device_11fe_0007[] = "RocketPort 4 port w/RJ11 connectors"; +static const char pci_device_11fe_0008[] = "RocketPort 8 port w/ DB78 SNI (Siemens) connector"; +static const char pci_device_11fe_0009[] = "RocketPort 16 port w/ DB78 SNI (Siemens) connector"; +static const char pci_device_11fe_000a[] = "RocketPort Plus 4 port"; +static const char pci_device_11fe_000b[] = "RocketPort Plus 8 port"; +static const char pci_device_11fe_000c[] = "RocketModem 6 port"; +static const char pci_device_11fe_000d[] = "RocketModem 4-port"; +static const char pci_device_11fe_000e[] = "RocketPort Plus 2 port RS232"; +static const char pci_device_11fe_000f[] = "RocketPort Plus 2 port RS422"; +static const char pci_device_11fe_0801[] = "RocketPort UPCI 32 port w/external I/F"; +static const char pci_device_11fe_0802[] = "RocketPort UPCI 8 port w/external I/F"; +static const char pci_device_11fe_0803[] = "RocketPort UPCI 16 port w/external I/F"; +static const char pci_device_11fe_0805[] = "RocketPort UPCI 8 port w/octa cable"; +static const char pci_device_11fe_080c[] = "RocketModem III 8 port"; +static const char pci_device_11fe_080d[] = "RocketModem III 4 port"; +static const char pci_device_11fe_0812[] = "RocketPort UPCI Plus 8 port RS422"; +static const char pci_device_11fe_0903[] = "RocketPort Compact PCI 16 port w/external I/F"; +static const char pci_device_11fe_8015[] = "RocketPort 4-port UART 16954"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_11ff[] = "Scion Corporation"; +static const char pci_device_11ff_0003[] = "AG-5"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1200[] = "CSS Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1201[] = "Vista Controls Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1202[] = "Network General Corp."; +static const char pci_device_1202_4300[] = "Gigabit Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1202_4300_1202_9841[] = "SK-9841 LX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1202_4300_1202_9842[] = "SK-9841 LX dual link"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1202_4300_1202_9843[] = "SK-9843 SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1202_4300_1202_9844[] = "SK-9843 SX dual link"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1203[] = "Bayer Corporation, Agfa Division"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1204[] = "Lattice Semiconductor Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1205[] = "Array Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1206[] = "Amdahl Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1208[] = "Parsytec GmbH"; +static const char pci_device_1208_4853[] = "HS-Link Device"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1209[] = "SCI Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120a[] = "Synaptel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120b[] = "Adaptive Solutions"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120c[] = "Technical Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120d[] = "Compression Labs, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120e[] = "Cyclades Corporation"; +static const char pci_device_120e_0100[] = "Cyclom-Y below first megabyte"; +static const char pci_device_120e_0101[] = "Cyclom-Y above first megabyte"; +static const char pci_device_120e_0102[] = "Cyclom-4Y below first megabyte"; +static const char pci_device_120e_0103[] = "Cyclom-4Y above first megabyte"; +static const char pci_device_120e_0104[] = "Cyclom-8Y below first megabyte"; +static const char pci_device_120e_0105[] = "Cyclom-8Y above first megabyte"; +static const char pci_device_120e_0200[] = "Cyclades-Z below first megabyte"; +static const char pci_device_120e_0201[] = "Cyclades-Z above first megabyte"; +static const char pci_device_120e_0300[] = "PC300/RSV or /X21 (2 ports)"; +static const char pci_device_120e_0301[] = "PC300/RSV or /X21 (1 port)"; +static const char pci_device_120e_0310[] = "PC300/TE (2 ports)"; +static const char pci_device_120e_0311[] = "PC300/TE (1 port)"; +static const char pci_device_120e_0320[] = "PC300/TE-M (2 ports)"; +static const char pci_device_120e_0321[] = "PC300/TE-M (1 port)"; +static const char pci_device_120e_0400[] = "PC400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_120f[] = "Essential Communications"; +static const char pci_device_120f_0001[] = "Roadrunner serial HIPPI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1210[] = "Hyperparallel Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1211[] = "Braintech Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1212[] = "Kingston Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1213[] = "Applied Intelligent Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1214[] = "Performance Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1215[] = "Interware Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1216[] = "Purup Prepress A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1217[] = "O2 Micro, Inc."; +static const char pci_device_1217_00f7[] = "Firewire (IEEE 1394)"; +static const char pci_device_1217_6729[] = "OZ6729"; +static const char pci_device_1217_673a[] = "OZ6730"; +static const char pci_device_1217_6832[] = "OZ6832/6833 CardBus Controller"; +static const char pci_device_1217_6836[] = "OZ6836/6860 CardBus Controller"; +static const char pci_device_1217_6872[] = "OZ6812 CardBus Controller"; +static const char pci_device_1217_6925[] = "OZ6922 CardBus Controller"; +static const char pci_device_1217_6933[] = "OZ6933/711E1 CardBus/SmartCardBus Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_6933_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1217_6972[] = "OZ601/6912/711E0 CardBus/SmartCardBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_6972_1014_020c[] = "ThinkPad R30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_6972_1179_0001[] = "Magnia Z310"; +#endif +static const char pci_device_1217_7110[] = "OZ711Mx 4-in-1 MemoryCardBus Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_7110_103c_088c[] = "NC8000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_7110_103c_0890[] = "NC6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_7110_1734_106c[] = "Amilo A1645"; +#endif +static const char pci_device_1217_7112[] = "OZ711EC1/M1 SmartCardBus/MemoryCardBus Controller"; +static const char pci_device_1217_7113[] = "OZ711EC1 SmartCardBus Controller"; +static const char pci_device_1217_7114[] = "OZ711M1/MC1 4-in-1 MemoryCardBus Controller"; +static const char pci_device_1217_7120[] = "Integrated MMC/SD Controller"; +static const char pci_device_1217_7130[] = "Integrated MS/xD Controller"; +static const char pci_device_1217_7134[] = "OZ711MP1/MS1 MemoryCardBus Controller"; +static const char pci_device_1217_7135[] = "Cardbus bridge"; +static const char pci_device_1217_71e2[] = "OZ711E2 SmartCardBus Controller"; +static const char pci_device_1217_7212[] = "OZ711M2 4-in-1 MemoryCardBus Controller"; +static const char pci_device_1217_7213[] = "OZ6933E CardBus Controller"; +static const char pci_device_1217_7223[] = "OZ711M3/MC3 4-in-1 MemoryCardBus Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_7223_103c_088c[] = "NC8000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1217_7223_103c_0890[] = "NC6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1217_7233[] = "OZ711MP3/MS3 4-in-1 MemoryCardBus Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1218[] = "Hybricon Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1219[] = "First Virtual Corporation"; +#endif +static const char pci_vendor_121a[] = "3Dfx Interactive, Inc."; +static const char pci_device_121a_0001[] = "Voodoo"; +static const char pci_device_121a_0002[] = "Voodoo 2"; +static const char pci_device_121a_0003[] = "Voodoo Banshee"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_0003[] = "Monster Fusion"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_4000[] = "Monster Fusion"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_4002[] = "Monster Fusion"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_4801[] = "Monster Fusion AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_4803[] = "Monster Fusion AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_8030[] = "Monster Fusion"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1092_8035[] = "Monster Fusion AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_10b0_0001[] = "Dragon 4000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_1102_1018[] = "3D Blaster Banshee VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_121a_0001[] = "Voodoo Banshee AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_121a_0003[] = "Voodoo Banshee AGP SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_121a_0004[] = "Voodoo Banshee"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_139c_0016[] = "Raven"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_139c_0017[] = "Raven"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0003_14af_0002[] = "Maxi Gamer Phoenix"; +#endif +static const char pci_device_121a_0004[] = "Voodoo Banshee [Velocity 100]"; +static const char pci_device_121a_0005[] = "Voodoo 3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0004[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0030[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0031[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0034[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0036[] = "Voodoo3 2000 PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0037[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0038[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_003a[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0044[] = "Voodoo3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_004b[] = "Velocity 100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_004c[] = "Velocity 200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_004d[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_004e[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0051[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0052[] = "Voodoo3 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0057[] = "Voodoo3 3000 PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0060[] = "Voodoo3 3500 TV (NTSC)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0061[] = "Voodoo3 3500 TV (PAL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0005_121a_0062[] = "Voodoo3 3500 TV (SECAM)"; +#endif +static const char pci_device_121a_0009[] = "Voodoo 4 / Voodoo 5"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0009_121a_0003[] = "Voodoo5 PCI 5500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_121a_0009_121a_0009[] = "Voodoo5 AGP 5500/6000"; +#endif +static const char pci_device_121a_0057[] = "Voodoo 3/3000 [Avenger]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121b[] = "Advanced Telecommunications Modules"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121c[] = "Nippon Texaco., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121d[] = "Lippert Automationstechnik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121e[] = "CSPI"; +static const char pci_device_121e_0201[] = "Myrinet 2000 Scalable Cluster Interconnect"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_121f[] = "Arcus Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1220[] = "Ariel Corporation"; +static const char pci_device_1220_1220[] = "AMCC 5933 TMS320C80 DSP/Imaging board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1221[] = "Contec Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1222[] = "Ancor Communications, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1223[] = "Artesyn Communication Products"; +static const char pci_device_1223_0003[] = "PM/Link"; +static const char pci_device_1223_0004[] = "PM/T1"; +static const char pci_device_1223_0005[] = "PM/E1"; +static const char pci_device_1223_0008[] = "PM/SLS"; +static const char pci_device_1223_0009[] = "BajaSpan Resource Target"; +static const char pci_device_1223_000a[] = "BajaSpan Section 0"; +static const char pci_device_1223_000b[] = "BajaSpan Section 1"; +static const char pci_device_1223_000c[] = "BajaSpan Section 2"; +static const char pci_device_1223_000d[] = "BajaSpan Section 3"; +static const char pci_device_1223_000e[] = "PM/PPC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1224[] = "Interactive Images"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1225[] = "Power I/O, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1227[] = "Tech-Source"; +static const char pci_device_1227_0006[] = "Raptor GFX 8P"; +static const char pci_device_1227_0023[] = "Raptor GFX [1100T]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1228[] = "Norsk Elektro Optikk A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1229[] = "Data Kinesis Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122a[] = "Integrated Telecom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122b[] = "LG Industrial Systems Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122c[] = "Sican GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122d[] = "Aztech System Ltd"; +static const char pci_device_122d_1206[] = "368DSP"; +static const char pci_device_122d_1400[] = "Trident PCI288-Q3DII (NX)"; +static const char pci_device_122d_50dc[] = "3328 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_122d_50dc_122d_0001[] = "3328 Audio"; +#endif +static const char pci_device_122d_80da[] = "3328 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_122d_80da_122d_0001[] = "3328 Audio"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122e[] = "Xyratex"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_122f[] = "Andrew Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1230[] = "Fishcamp Engineering"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1231[] = "Woodward McCoach, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1232[] = "GPT Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1233[] = "Bus-Tech, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1234[] = "Technical Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1235[] = "Risq Modular Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1236[] = "Sigma Designs Corporation"; +static const char pci_device_1236_0000[] = "RealMagic64/GX"; +static const char pci_device_1236_6401[] = "REALmagic 64/GX (SD 6425)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1237[] = "Alta Technology Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1238[] = "Adtran"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1239[] = "3DO Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123a[] = "Visicom Laboratories, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123b[] = "Seeq Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123c[] = "Century Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123d[] = "Engineering Design Team, Inc."; +static const char pci_device_123d_0000[] = "EasyConnect 8/32"; +static const char pci_device_123d_0002[] = "EasyConnect 8/64"; +static const char pci_device_123d_0003[] = "EasyIO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123e[] = "Simutech, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_123f[] = "C-Cube Microsystems"; +static const char pci_device_123f_00e4[] = "MPEG"; +static const char pci_device_123f_8120[] = "E4?"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8120_11bd_0006[] = "DV500 E4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8120_11bd_000a[] = "DV500 E4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8120_11bd_000f[] = "DV500 E4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8120_1809_0016[] = "Emuzed MAUI-III PCI PVR FM TV"; +#endif +static const char pci_device_123f_8888[] = "Cinemaster C 3.0 DVD Decoder"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8888_1002_0001[] = "Cinemaster C 3.0 DVD Decoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8888_1002_0002[] = "Cinemaster C 3.0 DVD Decoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_123f_8888_1328_0001[] = "Cinemaster C 3.0 DVD Decoder"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1240[] = "Marathon Technologies Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1241[] = "DSC Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1242[] = "JNI Corporation"; +static const char pci_device_1242_1560[] = "JNIC-1560 PCI-X Fibre Channel Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1242_1560_1242_6562[] = "FCX2-6562 Dual Channel PCI-X Fibre Channel Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1242_1560_1242_656a[] = "FCX-6562 PCI-X Fibre Channel Adapter"; +#endif +static const char pci_device_1242_4643[] = "FCI-1063 Fibre Channel Adapter"; +static const char pci_device_1242_6562[] = "FCX2-6562 Dual Channel PCI-X Fibre Channel Adapter"; +static const char pci_device_1242_656a[] = "FCX-6562 PCI-X Fibre Channel Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1243[] = "Delphax"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1244[] = "AVM Audiovisuelles MKTG & Computer System GmbH"; +static const char pci_device_1244_0700[] = "B1 ISDN"; +static const char pci_device_1244_0800[] = "C4 ISDN"; +static const char pci_device_1244_0a00[] = "A1 ISDN [Fritz]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1244_0a00_1244_0a00[] = "FRITZ!Card ISDN Controller"; +#endif +static const char pci_device_1244_0e00[] = "Fritz!PCI v2.0 ISDN"; +static const char pci_device_1244_1100[] = "C2 ISDN"; +static const char pci_device_1244_1200[] = "T1 ISDN"; +static const char pci_device_1244_2700[] = "Fritz!Card DSL SL"; +static const char pci_device_1244_2900[] = "Fritz!Card DSL v2.0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1245[] = "A.P.D., S.A."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1246[] = "Dipix Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1247[] = "Xylon Research, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1248[] = "Central Data Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1249[] = "Samsung Electronics Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124a[] = "AEG Electrocom GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124b[] = "SBS/Greenspring Modular I/O"; +static const char pci_device_124b_0040[] = "PCI-40A or cPCI-200 Quad IndustryPack carrier"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_124b_0040_124b_9080[] = "PCI9080 Bridge"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124c[] = "Solitron Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124d[] = "Stallion Technologies, Inc."; +static const char pci_device_124d_0000[] = "EasyConnection 8/32"; +static const char pci_device_124d_0002[] = "EasyConnection 8/64"; +static const char pci_device_124d_0003[] = "EasyIO"; +static const char pci_device_124d_0004[] = "EasyConnection/RA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124e[] = "Cylink"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_124f[] = "Infortrend Technology, Inc."; +static const char pci_device_124f_0041[] = "IFT-2000 Series RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1250[] = "Hitachi Microcomputer System Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1251[] = "VLSI Solutions Oy"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1253[] = "Guzik Technical Enterprises"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1254[] = "Linear Systems Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1255[] = "Optibase Ltd"; +static const char pci_device_1255_1110[] = "MPEG Forge"; +static const char pci_device_1255_1210[] = "MPEG Fusion"; +static const char pci_device_1255_2110[] = "VideoPlex"; +static const char pci_device_1255_2120[] = "VideoPlex CC"; +static const char pci_device_1255_2130[] = "VideoQuest"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1256[] = "Perceptive Solutions, Inc."; +static const char pci_device_1256_4201[] = "PCI-2220I"; +static const char pci_device_1256_4401[] = "PCI-2240I"; +static const char pci_device_1256_5201[] = "PCI-2000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1257[] = "Vertex Networks, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1258[] = "Gilbarco, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1259[] = "Allied Telesyn International"; +static const char pci_device_1259_2560[] = "AT-2560 Fast Ethernet Adapter (i82557B)"; +static const char pci_device_1259_a117[] = "RTL81xx Fast Ethernet"; +static const char pci_device_1259_a11e[] = "RTL81xx Fast Ethernet"; +static const char pci_device_1259_a120[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125a[] = "ABB Power Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125b[] = "Asix Electronics Corporation"; +static const char pci_device_125b_1400[] = "ALFA GFC2204 Fast Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125b_1400_1186_1100[] = "AX8814X Based PCI Fast Ethernet Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125c[] = "Aurora Technologies, Inc."; +static const char pci_device_125c_0101[] = "Saturn 4520P"; +static const char pci_device_125c_0640[] = "Aries 16000P"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125d[] = "ESS Technology"; +static const char pci_device_125d_0000[] = "ES336H Fax Modem (Early Model)"; +static const char pci_device_125d_1948[] = "Solo?"; +static const char pci_device_125d_1968[] = "ES1968 Maestro 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1968_1028_0085[] = "ES1968 Maestro-2 PCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1968_1033_8051[] = "ES1968 Maestro-2 Audiodrive"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_125d_1969[] = "ES1969 Solo-1 Audiodrive"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1969_1014_0166[] = "ES1969 SOLO-1 AudioDrive on IBM Aptiva Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1969_125d_8888[] = "Solo-1 Audio Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1969_153b_111b[] = "Terratec 128i PCI"; +#endif +static const char pci_device_125d_1978[] = "ES1978 Maestro 2E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_0e11_b112[] = "Armada M700/E500"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_1033_803c[] = "ES1978 Maestro-2E Audiodrive"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_1033_8058[] = "ES1978 Maestro-2E Audiodrive"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_1092_4000[] = "Monster Sound MX400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1978_1179_0001[] = "ES1978 Maestro-2E Audiodrive"; +#endif +static const char pci_device_125d_1988[] = "ES1988 Allegro-1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1988_0e11_0098[] = "Evo N600c"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1988_1092_4100[] = "Sonic Impact S100"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1988_125d_1988[] = "ESS Allegro-1 Audiodrive"; +#endif +static const char pci_device_125d_1989[] = "ESS Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1989_125d_1989[] = "ESS Modem"; +#endif +static const char pci_device_125d_1998[] = "ES1983S Maestro-3i PCI Audio Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1998_1028_00b1[] = "Latitude C600"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_1998_1028_00e6[] = "ES1983S Maestro-3i (Dell Inspiron 8100)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_125d_1999[] = "ES1983S Maestro-3i PCI Modem Accelerator"; +static const char pci_device_125d_199a[] = "ES1983S Maestro-3i PCI Audio Accelerator"; +static const char pci_device_125d_199b[] = "ES1983S Maestro-3i PCI Modem Accelerator"; +static const char pci_device_125d_2808[] = "ES336H Fax Modem (Later Model)"; +static const char pci_device_125d_2838[] = "ES2838/2839 SuperLink Modem"; +static const char pci_device_125d_2898[] = "ES2898 Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0424[] = "ES56-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0425[] = "ES56T-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0426[] = "ES56V-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0427[] = "VW-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0428[] = "ES56ST-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_125d_0429[] = "ES56SV-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_147a_c001[] = "ES56-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_14fe_0428[] = "ES56-PI Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_125d_2898_14fe_0429[] = "ES56-PI Data Fax Modem"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125e[] = "Specialvideo Engineering SRL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_125f[] = "Concurrent Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1260[] = "Intersil Corporation"; +static const char pci_device_1260_3872[] = "Prism 2.5 Wavelan chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3872_1468_0202[] = "LAN-Express IEEE 802.11b Wireless LAN"; +#endif +static const char pci_device_1260_3873[] = "Prism 2.5 Wavelan chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_1186_3501[] = "DWL-520 Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_1186_3700[] = "DWL-520 Wireless PCI Adapter, Rev E1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_1385_4105[] = "MA311 802.11b wireless adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_1668_0414[] = "HWP01170-01 802.11b PCI Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_16a5_1601[] = "AIR.mate PC-400 PCI Wireless LAN Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_1737_3874[] = "WMP11 Wireless 802.11b PCI Adapter"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3873_8086_2513[] = "Wireless 802.11b MiniPCI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1260_3886[] = "ISL3886 [Prism Javelin/Prism Xbow]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3886_17cf_0037[] = "XG-901 and clones Wireless Adapter"; +#endif +static const char pci_device_1260_3890[] = "ISL3890 [Prism GT/Prism Duette]/ISL3886 [Prism Javelin/Prism Xbow]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_10b8_2802[] = "SMC2802W Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_10b8_2835[] = "SMC2835W Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_10b8_a835[] = "SMC2835W V2 Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1113_4203[] = "WN4201B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1113_ee03[] = "SMC2802W V2 Wireless PCI Adapter [ISL3886]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1113_ee08[] = "SMC2835W V3 EU Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1186_3202[] = "DWL-G650 A1 Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1259_c104[] = "CG-WLCB54GT Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1260_0000[] = "WG511 Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_1385_4800[] = "WG511 Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_16a5_1605[] = "ALLNET ALL0271 Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_17cf_0014[] = "XG-600 and clones Wireless Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_3890_17cf_0020[] = "XG-900 and clones Wireless Adapter"; +#endif +static const char pci_device_1260_8130[] = "HMP8130 NTSC/PAL Video Decoder"; +static const char pci_device_1260_8131[] = "HMP8131 NTSC/PAL Video Decoder"; +static const char pci_device_1260_ffff[] = "ISL3886IK"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1260_ffff_1260_0000[] = "Senao 3054MP+ (J) mini-PCI WLAN 802.11g adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1261[] = "Matsushita-Kotobuki Electronics Industries, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1262[] = "ES Computer Company, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1263[] = "Sonic Solutions"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1264[] = "Aval Nagasaki Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1265[] = "Casio Computer Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1266[] = "Microdyne Corporation"; +static const char pci_device_1266_0001[] = "NE10/100 Adapter (i82557B)"; +static const char pci_device_1266_1910[] = "NE2000Plus (RT8029) Ethernet Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1266_1910_1266_1910[] = "NE2000Plus Ethernet Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1267[] = "S. A. Telecommunications"; +static const char pci_device_1267_5352[] = "PCR2101"; +static const char pci_device_1267_5a4b[] = "Telsat Turbo"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1268[] = "Tektronix"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1269[] = "Thomson-CSF/TTM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126a[] = "Lexmark International, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126b[] = "Adax, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126c[] = "Northern Telecom"; +static const char pci_device_126c_1211[] = "10/100BaseTX [RTL81xx]"; +static const char pci_device_126c_126c[] = "802.11b Wireless Ethernet Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126d[] = "Splash Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_126e[] = "Sumitomo Metal Industries, Ltd."; +#endif +static const char pci_vendor_126f[] = "Silicon Motion, Inc."; +static const char pci_device_126f_0501[] = "SM501 VoyagerGX Rev. AA"; +static const char pci_device_126f_0510[] = "SM501 VoyagerGX Rev. B"; +static const char pci_device_126f_0710[] = "SM710 LynxEM"; +static const char pci_device_126f_0712[] = "SM712 LynxEM+"; +static const char pci_device_126f_0720[] = "SM720 Lynx3DM"; +static const char pci_device_126f_0730[] = "SM731 Cougar3DR"; +static const char pci_device_126f_0810[] = "SM810 LynxE"; +static const char pci_device_126f_0811[] = "SM811 LynxE"; +static const char pci_device_126f_0820[] = "SM820 Lynx3D"; +static const char pci_device_126f_0910[] = "SM910"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1270[] = "Olympus Optical Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1271[] = "GW Instruments"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1272[] = "Telematics International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1273[] = "Hughes Network Systems"; +static const char pci_device_1273_0002[] = "DirecPC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1274[] = "Ensoniq"; +static const char pci_device_1274_1171[] = "ES1373 [AudioPCI] (also Creative Labs CT5803)"; +static const char pci_device_1274_1371[] = "ES1371 [AudioPCI-97]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_0e11_0024[] = "AudioPCI on Motherboard Compaq Deskpro"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_0e11_b1a7[] = "ES1371, ES1373 AudioPCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1033_80ac[] = "ES1371, ES1373 AudioPCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1042_1854[] = "Tazer"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_107b_8054[] = "Tabor2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1274_1371[] = "Creative Sound Blaster AudioPCI64V, AudioPCI128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1274_8001[] = "CT4751 board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6470[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6147 1.1A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6560[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6156 1.10"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6630[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6163BX 1.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6631[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6163VIA 1.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6632[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6163BX 2.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6633[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6163VIA 2.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6820[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6182 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6822[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6182 1.00A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6830[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6183 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6880[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6188 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6900[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6190 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6910[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6191"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6930[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6193"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6990[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6199BX 2.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1462_6991[] = "ES1371, ES1373 AudioPCI On Motherboard MS-6199VIA 2.0A"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_14a4_2077[] = "ES1371, ES1373 AudioPCI On Motherboard KR639"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_14a4_2105[] = "ES1371, ES1373 AudioPCI On Motherboard MR800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_14a4_2107[] = "ES1371, ES1373 AudioPCI On Motherboard MR801"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_14a4_2172[] = "ES1371, ES1373 AudioPCI On Motherboard DR739"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1509_9902[] = "ES1371, ES1373 AudioPCI On Motherboard KW11"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1509_9903[] = "ES1371, ES1373 AudioPCI On Motherboard KW31"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1509_9904[] = "ES1371, ES1373 AudioPCI On Motherboard KA11"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_1509_9905[] = "ES1371, ES1373 AudioPCI On Motherboard KC13"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8801[] = "ES1371, ES1373 AudioPCI On Motherboard CP810E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8802[] = "ES1371, ES1373 AudioPCI On Motherboard CP810"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8803[] = "ES1371, ES1373 AudioPCI On Motherboard P3810E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8804[] = "ES1371, ES1373 AudioPCI On Motherboard P3810-S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_152d_8805[] = "ES1371, ES1373 AudioPCI On Motherboard P3820-S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_2001[] = "ES1371, ES1373 AudioPCI On Motherboard 6CTR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_2200[] = "ES1371, ES1373 AudioPCI On Motherboard 6WTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_3000[] = "ES1371, ES1373 AudioPCI On Motherboard 6WSV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_3100[] = "ES1371, ES1373 AudioPCI On Motherboard 6WIV2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_3102[] = "ES1371, ES1373 AudioPCI On Motherboard 6WIV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_270f_7060[] = "ES1371, ES1373 AudioPCI On Motherboard 6ASA2"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4249[] = "ES1371, ES1373 AudioPCI On Motherboard BI440ZX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_424c[] = "ES1371, ES1373 AudioPCI On Motherboard BL440ZX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_425a[] = "ES1371, ES1373 AudioPCI On Motherboard BZ440ZX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4341[] = "ES1371, ES1373 AudioPCI On Motherboard Cayman"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4343[] = "ES1371, ES1373 AudioPCI On Motherboard Cape Cod"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4541[] = "D815EEA Motherboard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4649[] = "ES1371, ES1373 AudioPCI On Motherboard Fire Island"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_464a[] = "ES1371, ES1373 AudioPCI On Motherboard FJ440ZX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4d4f[] = "ES1371, ES1373 AudioPCI On Motherboard Montreal"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_4f43[] = "ES1371, ES1373 AudioPCI On Motherboard OC440LX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_5243[] = "ES1371, ES1373 AudioPCI On Motherboard RC440BX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_5352[] = "ES1371, ES1373 AudioPCI On Motherboard SunRiver"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_5643[] = "ES1371, ES1373 AudioPCI On Motherboard Vancouver"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_1371_8086_5753[] = "ES1371, ES1373 AudioPCI On Motherboard WS440BX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1274_5000[] = "ES1370 [AudioPCI]"; +static const char pci_device_1274_5880[] = "5880 AudioPCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1274_2000[] = "Creative Sound Blaster AudioPCI128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1274_2003[] = "Creative SoundBlaster AudioPCI 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1274_5880[] = "Creative Sound Blaster AudioPCI128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1274_8001[] = "Sound Blaster 16PCI 4.1ch"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1458_a000[] = "5880 AudioPCI On Motherboard 6OXET"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_1462_6880[] = "5880 AudioPCI On Motherboard MS-6188 1.00"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_270f_2001[] = "5880 AudioPCI On Motherboard 6CTR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_270f_2200[] = "5880 AudioPCI On Motherboard 6WTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1274_5880_270f_7040[] = "5880 AudioPCI On Motherboard 6ATA4"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1275[] = "Network Appliance Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1276[] = "Switched Network Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1277[] = "Comstream"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1278[] = "Transtech Parallel Systems Ltd."; +static const char pci_device_1278_0701[] = "TPE3/TM3 PowerPC Node"; +static const char pci_device_1278_0710[] = "TPE5 PowerPC PCI board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1279[] = "Transmeta Corporation"; +static const char pci_device_1279_0060[] = "TM8000 Northbridge"; +static const char pci_device_1279_0061[] = "TM8000 AGP bridge"; +static const char pci_device_1279_0295[] = "Northbridge"; +static const char pci_device_1279_0395[] = "LongRun Northbridge"; +static const char pci_device_1279_0396[] = "SDRAM controller"; +static const char pci_device_1279_0397[] = "BIOS scratchpad"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127a[] = "Rockwell International"; +static const char pci_device_127a_1002[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_1092_094c[] = "SupraExpress 56i PRO [Diamond SUP2380]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4002[] = "HPG / MDP3858-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4005[] = "MDP3858-E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4007[] = "MDP3858-A/-NZ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4012[] = "MDP3858-SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4017[] = "MDP3858-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_122d_4018[] = "MDP3858-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1002_127a_1002[] = "Rockwell 56K D/F HCF Modem"; +#endif +static const char pci_device_127a_1003[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_0e11_b0bc[] = "229-DF Zephyr"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_0e11_b114[] = "229-DF Cheetah"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_1033_802b[] = "229-DF"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13df_1003[] = "PCI56RX Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_0117[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_0147[] = "IBM F-1156IV+/R3 Spain V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_0197[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_01c7[] = "IBM F-1156IV+/R3 WW V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_13e0_01f7[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_1436_1003[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_1436_1103[] = "IBM 5614PM3G V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1003_1436_1602[] = "Compaq 229-DF Ducati"; +#endif +static const char pci_device_127a_1004[] = "HCF 56k Data/Fax/Voice Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1004_1048_1500[] = "MicroLink 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1004_10cf_1059[] = "Fujitsu 229-DFRT"; +#endif +static const char pci_device_127a_1005[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1005_127a[] = "AOpen FM56-P"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1033_8029[] = "229-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1033_8054[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_10cf_103c[] = "Fujitsu"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_10cf_1055[] = "Fujitsu 229-DFSV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_10cf_1056[] = "Fujitsu 229-DFSV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4003[] = "MDP3858SP-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4006[] = "Packard Bell MDP3858V-E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4008[] = "MDP3858SP-A/SP-NZ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4009[] = "MDP3858SP-E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4010[] = "MDP3858V-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4011[] = "MDP3858SP-SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4013[] = "MDP3858V-A/V-NZ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4015[] = "MDP3858SP-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4016[] = "MDP3858V-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_122d_4019[] = "MDP3858V-SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13df_1005[] = "PCI56RVP Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13e0_0187[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13e0_01a7[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13e0_01b7[] = "IBM DF-1156IV+/R3 Spain V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_13e0_01d7[] = "IBM DF-1156IV+/R3 WW V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1436_1005[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1436_1105[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1005_1437_1105[] = "IBM 5614PS3G V.90 Modem"; +#endif +static const char pci_device_127a_1022[] = "HCF 56k Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1022_1436_1303[] = "M3-5614PM3G V.90 Modem"; +#endif +static const char pci_device_127a_1023[] = "HCF 56k Data/Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_122d_4020[] = "Packard Bell MDP3858-WE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_122d_4023[] = "MDP3858-UE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_13e0_0247[] = "IBM F-1156IV+/R6 Spain V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_13e0_0297[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_13e0_02c7[] = "IBM F-1156IV+/R6 WW V.90 Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_1436_1203[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1023_1436_1303[] = "IBM"; +#endif +static const char pci_device_127a_1024[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_127a_1025[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_10cf_106a[] = "Fujitsu 235-DFSV"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_122d_4021[] = "Packard Bell MDP3858V-WE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_122d_4022[] = "MDP3858SP-WE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_122d_4024[] = "MDP3858V-UE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_1025_122d_4025[] = "MDP3858SP-UE"; +#endif +static const char pci_device_127a_1026[] = "HCF 56k PCI Speakerphone Modem"; +static const char pci_device_127a_1032[] = "HCF 56k Modem"; +static const char pci_device_127a_1033[] = "HCF 56k Modem"; +static const char pci_device_127a_1034[] = "HCF 56k Modem"; +static const char pci_device_127a_1035[] = "HCF 56k PCI Speakerphone Modem"; +static const char pci_device_127a_1036[] = "HCF 56k Modem"; +static const char pci_device_127a_1085[] = "HCF 56k Volcano PCI Modem"; +static const char pci_device_127a_2005[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8044[] = "229-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8045[] = "229-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8055[] = "PBE/Aztech 235W-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8056[] = "235-DFSV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_805a[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_805f[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2005_104d_8074[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_127a_2013[] = "HSF 56k Data/Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2013_1179_0001[] = "Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2013_1179_ff00[] = "Modem"; +#endif +static const char pci_device_127a_2014[] = "HSF 56k Data/Fax/Voice Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2014_10cf_1057[] = "Fujitsu Citicorp III"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2014_122d_4050[] = "MSP3880-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2014_122d_4055[] = "MSP3880-W"; +#endif +static const char pci_device_127a_2015[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2015_10cf_1063[] = "Fujitsu"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2015_10cf_1064[] = "Fujitsu"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2015_1468_2015[] = "Fujitsu"; +#endif +static const char pci_device_127a_2016[] = "HSF 56k Data/Fax/Voice/Spkp Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4051[] = "MSP3880V-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4052[] = "MSP3880SP-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4054[] = "MSP3880V-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4056[] = "MSP3880SP-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_2016_122d_4057[] = "MSP3880SP-A"; +#endif +static const char pci_device_127a_4311[] = "Riptide HSF 56k PCI Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4311_127a_4311[] = "Ring Modular? Riptide HSF RT HP Dom"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4311_13e0_0210[] = "HP-GVC"; +#endif +static const char pci_device_127a_4320[] = "Riptide PCI Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4320_1235_4320[] = "Riptide PCI Audio Controller"; +#endif +static const char pci_device_127a_4321[] = "Riptide HCF 56k PCI Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4321_1235_4321[] = "Hewlett Packard DF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4321_1235_4324[] = "Hewlett Packard DF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4321_13e0_0210[] = "Hewlett Packard DF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4321_144d_2321[] = "Riptide"; +#endif +static const char pci_device_127a_4322[] = "Riptide PCI Game Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_4322_1235_4322[] = "Riptide PCI Game Controller"; +#endif +static const char pci_device_127a_8234[] = "RapidFire 616X ATM155 Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_8234_108d_0022[] = "RapidFire 616X ATM155 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_127a_8234_108d_0027[] = "RapidFire 616X ATM155 Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127b[] = "Pixera Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127c[] = "Crosspoint Solutions, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127d[] = "Vela Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127e[] = "Winnov, L.P."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_127f[] = "Fujifilm"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1280[] = "Photoscript Group Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1281[] = "Yokogawa Electric Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1282[] = "Davicom Semiconductor, Inc."; +static const char pci_device_1282_9009[] = "Ethernet 100/10 MBit"; +static const char pci_device_1282_9100[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_1282_9102[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_1282_9132[] = "Ethernet 100/10 MBit"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1283[] = "Integrated Technology Express, Inc."; +static const char pci_device_1283_673a[] = "IT8330G"; +static const char pci_device_1283_8211[] = "ITE 8211F Single Channel UDMA 133 (ASUS 8211 (ITE IT8212 ATA RAID Controller))"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1283_8211_1043_8138[] = "P5GD1-VW Mainboard"; +#endif +static const char pci_device_1283_8212[] = "IT/ITE8212 Dual channel ATA RAID controller (PCI version seems to be IT8212, embedded seems to be ITE8212)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1283_8212_1283_0001[] = "IT/ITE8212 Dual channel ATA RAID controller"; +#endif +static const char pci_device_1283_8330[] = "IT8330G"; +static const char pci_device_1283_8872[] = "IT8874F PCI Dual Serial Port Controller"; +static const char pci_device_1283_8888[] = "IT8888F PCI to ISA Bridge with SMB"; +static const char pci_device_1283_8889[] = "IT8889F PCI to ISA Bridge"; +static const char pci_device_1283_e886[] = "IT8330G"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1284[] = "Sahara Networks, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1285[] = "Platform Technologies, Inc."; +static const char pci_device_1285_0100[] = "AGOGO sound chip (aka ESS Maestro 1)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1286[] = "Mazet GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1287[] = "M-Pact, Inc."; +static const char pci_device_1287_001e[] = "LS220D DVD Decoder"; +static const char pci_device_1287_001f[] = "LS220C DVD Decoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1288[] = "Timestep Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1289[] = "AVC Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128a[] = "Asante Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128b[] = "Transwitch Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128c[] = "Retix Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128d[] = "G2 Networks, Inc."; +static const char pci_device_128d_0021[] = "ATM155 Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128e[] = "Hoontech Corporation/Samho Multi Tech Ltd."; +static const char pci_device_128e_0008[] = "ST128 WSS/SB"; +static const char pci_device_128e_0009[] = "ST128 SAM9407"; +static const char pci_device_128e_000a[] = "ST128 Game Port"; +static const char pci_device_128e_000b[] = "ST128 MPU Port"; +static const char pci_device_128e_000c[] = "ST128 Ctrl Port"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_128f[] = "Tateno Dennou, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1290[] = "Sord Computer Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1291[] = "NCS Computer Italia"; +#endif +static const char pci_vendor_1292[] = "Tritech Microelectronics Inc"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1293[] = "Media Reality Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1294[] = "Rhetorex, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1295[] = "Imagenation Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1296[] = "Kofax Image Products"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1297[] = "Holco Enterprise Co, Ltd/Shuttle Computer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1298[] = "Spellcaster Telecommunications Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1299[] = "Knowledge Technology Lab."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129a[] = "VMetro, inc."; +static const char pci_device_129a_0615[] = "PBT-615 PCI-X Bus Analyzer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129b[] = "Image Access"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129c[] = "Jaycor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129d[] = "Compcore Multimedia, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129e[] = "Victor Company of Japan, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_129f[] = "OEC Medical Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a0[] = "Allen-Bradley Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a1[] = "Simpact Associates, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a2[] = "Newgen Systems Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a3[] = "Lucent Technologies"; +static const char pci_device_12a3_8105[] = "T8105 H100 Digital Switch"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a4[] = "NTT Electronics Technology Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a5[] = "Vision Dynamics Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a6[] = "Scalable Networks, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a7[] = "AMO GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a8[] = "News Datacom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12a9[] = "Xiotech Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12aa[] = "SDL Communications, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ab[] = "Yuan Yuan Enterprise Co., Ltd."; +static const char pci_device_12ab_0002[] = "AU8830 [Vortex2] Based Sound Card With A3D Support"; +static const char pci_device_12ab_3000[] = "MPG-200C PCI DVD Decoder Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ac[] = "Measurex Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ad[] = "Multidata GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ae[] = "Alteon Networks Inc."; +static const char pci_device_12ae_0001[] = "AceNIC Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12ae_0001_1014_0104[] = "Gigabit Ethernet-SX PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12ae_0001_12ae_0001[] = "Gigabit Ethernet-SX (Universal)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12ae_0001_1410_0104[] = "Gigabit Ethernet-SX PCI Adapter"; +#endif +static const char pci_device_12ae_0002[] = "AceNIC Gigabit Ethernet (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12ae_0002_10a9_8002[] = "Acenic Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12ae_0002_12ae_0002[] = "Gigabit Ethernet-T (3C986-T)"; +#endif +static const char pci_device_12ae_00fa[] = "Farallon PN9100-T Gigabit Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12af[] = "TDK USA Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b0[] = "Jorge Scientific Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b1[] = "GammaLink"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b2[] = "General Signal Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b3[] = "Inter-Face Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b4[] = "FutureTel Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b5[] = "Granite Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b6[] = "Natural Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b7[] = "Cognex Modular Vision Systems Div. - Acumen Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b8[] = "Korg"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12b9[] = "3Com Corp, Modem Division"; +static const char pci_device_12b9_1006[] = "WinModem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_005c[] = "USR 56k Internal Voice WinModem (Model 3472)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_005e[] = "USR 56k Internal WinModem (Models 662975)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0062[] = "USR 56k Internal Voice WinModem (Model 662978)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0068[] = "USR 56k Internal Voice WinModem (Model 5690)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_007a[] = "USR 56k Internal Voice WinModem (Model 662974)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_007f[] = "USR 56k Internal WinModem (Models 5698, 5699)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0080[] = "USR 56k Internal WinModem (Models 2975, 3528)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0081[] = "USR 56k Internal Voice WinModem (Models 2974, 3529)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1006_12b9_0091[] = "USR 56k Internal Voice WinModem (Model 2978)"; +#endif +static const char pci_device_12b9_1007[] = "USR 56k Internal WinModem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1007_12b9_00a3[] = "USR 56k Internal WinModem (Model 3595)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1007_12b9_00c4[] = "U.S. Robotics 56K Voice Win Int (2884a)"; +#endif +static const char pci_device_12b9_1008[] = "56K FaxModem Model 5610"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00a2[] = "USR 56k Internal FAX Modem (Model 2977)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00aa[] = "USR 56k Internal Voice Modem (Model 2976)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00ab[] = "USR 56k Internal Voice Modem (Model 5609)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00ac[] = "USR 56k Internal Voice Modem (Model 3298)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12b9_1008_12b9_00ad[] = "USR 56k Internal FAX Modem (Model 5610)"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ba[] = "BittWare, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12bb[] = "Nippon Unisoft Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12bc[] = "Array Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12bd[] = "Computerm Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12be[] = "Anchor Chips Inc."; +static const char pci_device_12be_3041[] = "AN3041Q CO-MEM"; +static const char pci_device_12be_3042[] = "AN3042Q CO-MEM Lite"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12be_3042_12be_3042[] = "Anchor Chips Lite Evaluation Board"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12bf[] = "Fujifilm Microdevices"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c0[] = "Infimed"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c1[] = "GMM Research Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c2[] = "Mentec Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c3[] = "Holtek Microelectronics Inc"; +static const char pci_device_12c3_0058[] = "PCI NE2K Ethernet"; +static const char pci_device_12c3_5598[] = "PCI NE2K Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c4[] = "Connect Tech Inc"; +static const char pci_device_12c4_0001[] = "Blue HEAT/PCI 8 (RS232/CL/RJ11)"; +static const char pci_device_12c4_0002[] = "Blue HEAT/PCI 4 (RS232)"; +static const char pci_device_12c4_0003[] = "Blue HEAT/PCI 2 (RS232)"; +static const char pci_device_12c4_0004[] = "Blue HEAT/PCI 8 (UNIV, RS485)"; +static const char pci_device_12c4_0005[] = "Blue HEAT/PCI 4+4/6+2 (UNIV, RS232/485)"; +static const char pci_device_12c4_0006[] = "Blue HEAT/PCI 4 (OPTO, RS485)"; +static const char pci_device_12c4_0007[] = "Blue HEAT/PCI 2+2 (RS232/485)"; +static const char pci_device_12c4_0008[] = "Blue HEAT/PCI 2 (OPTO, Tx, RS485)"; +static const char pci_device_12c4_0009[] = "Blue HEAT/PCI 2+6 (RS232/485)"; +static const char pci_device_12c4_000a[] = "Blue HEAT/PCI 8 (Tx, RS485)"; +static const char pci_device_12c4_000b[] = "Blue HEAT/PCI 4 (Tx, RS485)"; +static const char pci_device_12c4_000c[] = "Blue HEAT/PCI 2 (20 MHz, RS485)"; +static const char pci_device_12c4_000d[] = "Blue HEAT/PCI 2 PTM"; +static const char pci_device_12c4_0100[] = "NT960/PCI"; +static const char pci_device_12c4_0201[] = "cPCI Titan - 2 Port"; +static const char pci_device_12c4_0202[] = "cPCI Titan - 4 Port"; +static const char pci_device_12c4_0300[] = "CTI PCI UART 2 (RS232)"; +static const char pci_device_12c4_0301[] = "CTI PCI UART 4 (RS232)"; +static const char pci_device_12c4_0302[] = "CTI PCI UART 8 (RS232)"; +static const char pci_device_12c4_0310[] = "CTI PCI UART 1+1 (RS232/485)"; +static const char pci_device_12c4_0311[] = "CTI PCI UART 2+2 (RS232/485)"; +static const char pci_device_12c4_0312[] = "CTI PCI UART 4+4 (RS232/485)"; +static const char pci_device_12c4_0320[] = "CTI PCI UART 2"; +static const char pci_device_12c4_0321[] = "CTI PCI UART 4"; +static const char pci_device_12c4_0322[] = "CTI PCI UART 8"; +static const char pci_device_12c4_0330[] = "CTI PCI UART 2 (RS485)"; +static const char pci_device_12c4_0331[] = "CTI PCI UART 4 (RS485)"; +static const char pci_device_12c4_0332[] = "CTI PCI UART 8 (RS485)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c5[] = "Picture Elements Incorporated"; +static const char pci_device_12c5_007e[] = "Imaging/Scanning Subsystem Engine"; +static const char pci_device_12c5_007f[] = "Imaging/Scanning Subsystem Engine"; +static const char pci_device_12c5_0081[] = "PCIVST [Grayscale Thresholding Engine]"; +static const char pci_device_12c5_0085[] = "Video Simulator/Sender"; +static const char pci_device_12c5_0086[] = "THR2 Multi-scale Thresholder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c6[] = "Mitani Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c7[] = "Dialogic Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c8[] = "G Force Co, Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12c9[] = "Gigi Operations"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ca[] = "Integrated Computing Engines"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12cb[] = "Antex Electronics Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12cc[] = "Pluto Technologies International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12cd[] = "Aims Lab"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ce[] = "Netspeed Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12cf[] = "Prophet Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d0[] = "GDE Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d1[] = "PSITech"; +#endif +static const char pci_vendor_12d2[] = "NVidia / SGS Thomson (Joint Venture)"; +static const char pci_device_12d2_0008[] = "NV1"; +static const char pci_device_12d2_0009[] = "DAC64"; +static const char pci_device_12d2_0018[] = "Riva128"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_1048_0c10[] = "VICTORY Erazor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_107b_8030[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_1092_0350[] = "Viper V330"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_1092_1092[] = "Viper V330"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b1b[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b1d[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b1e[] = "STB Velocity 128, PAL TV-Out"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b20[] = "STB Velocity 128 Sapphire"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b21[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b22[] = "STB Velocity 128 AGP, NTSC TV-Out"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b23[] = "STB Velocity 128 AGP, PAL TV-Out"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b27[] = "STB Velocity 128 DVD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_1b88[] = "MVP Pro 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_222a[] = "STB Velocity 128 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_2230[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_2232[] = "STB Velocity 128"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_10b4_2235[] = "STB Velocity 128 AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d2_0018_2a15_54a3[] = "3DVision-SAGP / 3DexPlorer 3000"; +#endif +static const char pci_device_12d2_0019[] = "Riva128ZX"; +static const char pci_device_12d2_0020[] = "TNT"; +static const char pci_device_12d2_0028[] = "TNT2"; +static const char pci_device_12d2_0029[] = "UTNT2"; +static const char pci_device_12d2_002c[] = "VTNT2"; +static const char pci_device_12d2_00a0[] = "ITNT2"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d3[] = "Vingmed Sound A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d4[] = "Ulticom (Formerly DGM&S)"; +static const char pci_device_12d4_0200[] = "T1 Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d5[] = "Equator Technologies Inc"; +static const char pci_device_12d5_0003[] = "BSP16"; +static const char pci_device_12d5_1000[] = "BSP15"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d6[] = "Analogic Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d7[] = "Biotronic SRL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d8[] = "Pericom Semiconductor"; +static const char pci_device_12d8_8150[] = "PCI to PCI Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12d9[] = "Aculab PLC"; +static const char pci_device_12d9_0002[] = "PCI Prosody"; +static const char pci_device_12d9_0004[] = "cPCI Prosody"; +static const char pci_device_12d9_0005[] = "Aculab E1/T1 PCI card"; +static const char pci_device_12d9_1078[] = "Prosody X class e1000 device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12d9_1078_12d9_000d[] = "Prosody X PCI"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12da[] = "True Time Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12db[] = "Annapolis Micro Systems, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12dc[] = "Symicron Computer Communication Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12dd[] = "Management Graphics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12de[] = "Rainbow Technologies"; +static const char pci_device_12de_0200[] = "CryptoSwift CS200"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12df[] = "SBS Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e0[] = "Chase Research"; +static const char pci_device_12e0_0010[] = "ST16C654 Quad UART"; +static const char pci_device_12e0_0020[] = "ST16C654 Quad UART"; +static const char pci_device_12e0_0030[] = "ST16C654 Quad UART"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e1[] = "Nintendo Co, Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e2[] = "Datum Inc. Bancomm-Timing Division"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e3[] = "Imation Corp - Medical Imaging Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e4[] = "Brooktrout Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e5[] = "Apex Semiconductor Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e6[] = "Cirel Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e7[] = "Sunsgroup Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e8[] = "Crisc Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12e9[] = "GE Spacenet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ea[] = "Zuken"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12eb[] = "Aureal Semiconductor"; +static const char pci_device_12eb_0001[] = "Vortex 1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_104d_8036[] = "AU8820 Vortex Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_1092_2000[] = "Sonic Impact A3D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_1092_2100[] = "Sonic Impact A3D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_1092_2110[] = "Sonic Impact A3D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_1092_2200[] = "Sonic Impact A3D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_122d_1002[] = "AU8820 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_12eb_0001[] = "AU8820 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0001_5053_3355[] = "Montego"; +#endif +static const char pci_device_12eb_0002[] = "Vortex 2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_104d_8049[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_104d_807b[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3000[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3001[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3002[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3003[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_1092_3004[] = "Monster Sound II"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_12eb_0002[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_12eb_0088[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_144d_3510[] = "AU8830 Vortex 3D Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0002_5053_3356[] = "Montego II"; +#endif +static const char pci_device_12eb_0003[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_104d_8049[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_104d_8077[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_109f_1000[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_12eb_0003[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_1462_6780[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_14a4_2073[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_14a4_2091[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_14a4_2104[] = "AU8810 Vortex Digital Audio Processor"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_0003_14a4_2106[] = "AU8810 Vortex Digital Audio Processor"; +#endif +static const char pci_device_12eb_8803[] = "Vortex 56k Software Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_12eb_8803_12eb_8803[] = "Vortex 56k Software Modem"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ec[] = "3A International, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ed[] = "Optivision Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ee[] = "Orange Micro"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ef[] = "Vienna Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f0[] = "Pentek"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f1[] = "Sorenson Vision Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f2[] = "Gammagraphx, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f3[] = "Radstone Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f4[] = "Megatel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f5[] = "Forks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f6[] = "Dawson France"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f7[] = "Cognex"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f8[] = "Electronic Design GmbH"; +static const char pci_device_12f8_0002[] = "VideoMaker"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12f9[] = "Four Fold Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12fb[] = "Spectrum Signal Processing"; +static const char pci_device_12fb_0001[] = "PMC-MAI"; +static const char pci_device_12fb_00f5[] = "F5 Dakar"; +static const char pci_device_12fb_02ad[] = "PMC-2MAI"; +static const char pci_device_12fb_2adc[] = "ePMC-2ADC"; +static const char pci_device_12fb_3100[] = "PRO-3100"; +static const char pci_device_12fb_3500[] = "PRO-3500"; +static const char pci_device_12fb_4d4f[] = "Modena"; +static const char pci_device_12fb_8120[] = "ePMC-8120"; +static const char pci_device_12fb_da62[] = "Daytona C6201 PCI (Hurricane)"; +static const char pci_device_12fb_db62[] = "Ingliston XBIF"; +static const char pci_device_12fb_dc62[] = "Ingliston PLX9054"; +static const char pci_device_12fb_dd62[] = "Ingliston JTAG/ISP"; +static const char pci_device_12fb_eddc[] = "ePMC-MSDDC"; +static const char pci_device_12fb_fa01[] = "ePMC-FPGA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12fc[] = "Capital Equipment Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12fd[] = "I2S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12fe[] = "ESD Electronic System Design GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_12ff[] = "Lexicon"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1300[] = "Harman International Industries Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1302[] = "Computer Sciences Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1303[] = "Innovative Integration"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1304[] = "Juniper Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1305[] = "Netphone, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1306[] = "Duet Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1307[] = "Measurement Computing"; +static const char pci_device_1307_0001[] = "PCI-DAS1602/16"; +static const char pci_device_1307_000b[] = "PCI-DIO48H"; +static const char pci_device_1307_000c[] = "PCI-PDISO8"; +static const char pci_device_1307_000d[] = "PCI-PDISO16"; +static const char pci_device_1307_000f[] = "PCI-DAS1200"; +static const char pci_device_1307_0010[] = "PCI-DAS1602/12"; +static const char pci_device_1307_0014[] = "PCI-DIO24H"; +static const char pci_device_1307_0015[] = "PCI-DIO24H/CTR3"; +static const char pci_device_1307_0016[] = "PCI-DIO48H/CTR15"; +static const char pci_device_1307_0017[] = "PCI-DIO96H"; +static const char pci_device_1307_0018[] = "PCI-CTR05"; +static const char pci_device_1307_0019[] = "PCI-DAS1200/JR"; +static const char pci_device_1307_001a[] = "PCI-DAS1001"; +static const char pci_device_1307_001b[] = "PCI-DAS1002"; +static const char pci_device_1307_001c[] = "PCI-DAS1602JR/16"; +static const char pci_device_1307_001d[] = "PCI-DAS6402/16"; +static const char pci_device_1307_001e[] = "PCI-DAS6402/12"; +static const char pci_device_1307_001f[] = "PCI-DAS16/M1"; +static const char pci_device_1307_0020[] = "PCI-DDA02/12"; +static const char pci_device_1307_0021[] = "PCI-DDA04/12"; +static const char pci_device_1307_0022[] = "PCI-DDA08/12"; +static const char pci_device_1307_0023[] = "PCI-DDA02/16"; +static const char pci_device_1307_0024[] = "PCI-DDA04/16"; +static const char pci_device_1307_0025[] = "PCI-DDA08/16"; +static const char pci_device_1307_0026[] = "PCI-DAC04/12-HS"; +static const char pci_device_1307_0027[] = "PCI-DAC04/16-HS"; +static const char pci_device_1307_0028[] = "PCI-DIO24"; +static const char pci_device_1307_0029[] = "PCI-DAS08"; +static const char pci_device_1307_002c[] = "PCI-INT32"; +static const char pci_device_1307_0033[] = "PCI-DUAL-AC5"; +static const char pci_device_1307_0034[] = "PCI-DAS-TC"; +static const char pci_device_1307_0035[] = "PCI-DAS64/M1/16"; +static const char pci_device_1307_0036[] = "PCI-DAS64/M2/16"; +static const char pci_device_1307_0037[] = "PCI-DAS64/M3/16"; +static const char pci_device_1307_004c[] = "PCI-DAS1000"; +static const char pci_device_1307_004d[] = "PCI-QUAD04"; +static const char pci_device_1307_0052[] = "PCI-DAS4020/12"; +static const char pci_device_1307_0054[] = "PCI-DIO96"; +static const char pci_device_1307_005e[] = "PCI-DAS6025"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1308[] = "Jato Technologies Inc."; +static const char pci_device_1308_0001[] = "NetCelerator Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1308_0001_1308_0001[] = "NetCelerator Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1309[] = "AB Semiconductor Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130a[] = "Mitsubishi Electric Microcomputer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130b[] = "Colorgraphic Communications Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130c[] = "Ambex Technologies, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130d[] = "Accelerix Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130e[] = "Yamatake-Honeywell Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_130f[] = "Advanet Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1310[] = "Gespac"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1311[] = "Videoserver, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1312[] = "Acuity Imaging, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1313[] = "Yaskawa Electric Co."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1316[] = "Teradyne Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1317[] = "ADMtek"; +static const char pci_device_1317_0981[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_1317_0985[] = "NC100 Network Everywhere Fast Ethernet 10/100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1317_0985_1734_100c[] = "Scenic N300 ADMtek AN983 10/100 Mbps PCI Adapter"; +#endif +static const char pci_device_1317_1985[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_1317_2850[] = "HSP MicroModem 56"; +static const char pci_device_1317_5120[] = "ADM5120 OpenGate System-on-Chip"; +static const char pci_device_1317_8201[] = "ADM8211 802.11b Wireless Interface"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1317_8201_10b8_2635[] = "SMC2635W 802.11b (11Mbps) wireless lan pcmcia (cardbus) card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1317_8201_1317_8201[] = "SMC2635W 802.11b (11mbps) wireless lan pcmcia (cardbus) card"; +#endif +static const char pci_device_1317_8211[] = "ADM8211 802.11b Wireless Interface"; +static const char pci_device_1317_9511[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1318[] = "Packet Engines Inc."; +static const char pci_device_1318_0911[] = "GNIC-II PCI Gigabit Ethernet [Hamachi]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1319[] = "Fortemedia, Inc"; +static const char pci_device_1319_0801[] = "Xwave QS3000A [FM801]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1319_0801_1319_1319[] = "FM801 PCI Audio"; +#endif +static const char pci_device_1319_0802[] = "Xwave QS3000A [FM801 game port]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1319_0802_1319_1319[] = "FM801 PCI Joystick"; +#endif +static const char pci_device_1319_1000[] = "FM801 PCI Audio"; +static const char pci_device_1319_1001[] = "FM801 PCI Joystick"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131a[] = "Finisar Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131c[] = "Nippon Electro-Sensory Devices Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131d[] = "Sysmic, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131e[] = "Xinex Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_131f[] = "Siig Inc"; +static const char pci_device_131f_1000[] = "CyberSerial (1-port) 16550"; +static const char pci_device_131f_1001[] = "CyberSerial (1-port) 16650"; +static const char pci_device_131f_1002[] = "CyberSerial (1-port) 16850"; +static const char pci_device_131f_1010[] = "Duet 1S(16550)+1P"; +static const char pci_device_131f_1011[] = "Duet 1S(16650)+1P"; +static const char pci_device_131f_1012[] = "Duet 1S(16850)+1P"; +static const char pci_device_131f_1020[] = "CyberParallel (1-port)"; +static const char pci_device_131f_1021[] = "CyberParallel (2-port)"; +static const char pci_device_131f_1030[] = "CyberSerial (2-port) 16550"; +static const char pci_device_131f_1031[] = "CyberSerial (2-port) 16650"; +static const char pci_device_131f_1032[] = "CyberSerial (2-port) 16850"; +static const char pci_device_131f_1034[] = "Trio 2S(16550)+1P"; +static const char pci_device_131f_1035[] = "Trio 2S(16650)+1P"; +static const char pci_device_131f_1036[] = "Trio 2S(16850)+1P"; +static const char pci_device_131f_1050[] = "CyberSerial (4-port) 16550"; +static const char pci_device_131f_1051[] = "CyberSerial (4-port) 16650"; +static const char pci_device_131f_1052[] = "CyberSerial (4-port) 16850"; +static const char pci_device_131f_2000[] = "CyberSerial (1-port) 16550"; +static const char pci_device_131f_2001[] = "CyberSerial (1-port) 16650"; +static const char pci_device_131f_2002[] = "CyberSerial (1-port) 16850"; +static const char pci_device_131f_2010[] = "Duet 1S(16550)+1P"; +static const char pci_device_131f_2011[] = "Duet 1S(16650)+1P"; +static const char pci_device_131f_2012[] = "Duet 1S(16850)+1P"; +static const char pci_device_131f_2020[] = "CyberParallel (1-port)"; +static const char pci_device_131f_2021[] = "CyberParallel (2-port)"; +static const char pci_device_131f_2030[] = "CyberSerial (2-port) 16550"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_131f_2030_131f_2030[] = "PCI Serial Card"; +#endif +static const char pci_device_131f_2031[] = "CyberSerial (2-port) 16650"; +static const char pci_device_131f_2032[] = "CyberSerial (2-port) 16850"; +static const char pci_device_131f_2040[] = "Trio 1S(16550)+2P"; +static const char pci_device_131f_2041[] = "Trio 1S(16650)+2P"; +static const char pci_device_131f_2042[] = "Trio 1S(16850)+2P"; +static const char pci_device_131f_2050[] = "CyberSerial (4-port) 16550"; +static const char pci_device_131f_2051[] = "CyberSerial (4-port) 16650"; +static const char pci_device_131f_2052[] = "CyberSerial (4-port) 16850"; +static const char pci_device_131f_2060[] = "Trio 2S(16550)+1P"; +static const char pci_device_131f_2061[] = "Trio 2S(16650)+1P"; +static const char pci_device_131f_2062[] = "Trio 2S(16850)+1P"; +static const char pci_device_131f_2081[] = "CyberSerial (8-port) ST16654"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1320[] = "Crypto AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1321[] = "Arcobel Graphics BV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1322[] = "MTT Co., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1323[] = "Dome Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1324[] = "Sphere Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1325[] = "Salix Technologies, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1326[] = "Seachange international"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1327[] = "Voss scientific"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1328[] = "quadrant international"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1329[] = "Productivity Enhancement"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_132a[] = "Microcom Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_132b[] = "Broadband Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_132c[] = "Micrel Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_132d[] = "Integrated Silicon Solution, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1330[] = "MMC Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1331[] = "Radisys Corp."; +static const char pci_device_1331_0030[] = "ENP-2611"; +static const char pci_device_1331_8200[] = "82600 Host Bridge"; +static const char pci_device_1331_8201[] = "82600 IDE"; +static const char pci_device_1331_8202[] = "82600 USB"; +static const char pci_device_1331_8210[] = "82600 PCI Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1332[] = "Micro Memory"; +static const char pci_device_1332_5415[] = "MM-5415CN PCI Memory Module with Battery Backup"; +static const char pci_device_1332_5425[] = "MM-5425CN PCI 64/66 Memory Module with Battery Backup"; +static const char pci_device_1332_6140[] = "MM-6140D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1334[] = "Redcreek Communications, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1335[] = "Videomail, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1337[] = "Third Planet Publishing"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1338[] = "BT Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133a[] = "Vtel Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133b[] = "Softcom Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133c[] = "Holontech Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133d[] = "SS Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133e[] = "Virtual Computer Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_133f[] = "SCM Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1340[] = "Atalla Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1341[] = "Kyoto Microcomputer Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1342[] = "Promax Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1343[] = "Phylon Communications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1344[] = "Crucial Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1345[] = "Arescom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1347[] = "Odetics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1349[] = "Sumitomo Electric Industries, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134a[] = "DTC Technology Corp."; +static const char pci_device_134a_0001[] = "Domex 536"; +static const char pci_device_134a_0002[] = "Domex DMX3194UP SCSI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134b[] = "ARK Research Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134c[] = "Chori Joho System Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134d[] = "PCTel Inc"; +static const char pci_device_134d_2189[] = "HSP56 MicroModem"; +static const char pci_device_134d_2486[] = "2304WT V.92 MDC Modem"; +static const char pci_device_134d_7890[] = "HSP MicroModem 56"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_134d_7890_134d_0001[] = "PCT789 adapter"; +#endif +static const char pci_device_134d_7891[] = "HSP MicroModem 56"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_134d_7891_134d_0001[] = "HSP MicroModem 56"; +#endif +static const char pci_device_134d_7892[] = "HSP MicroModem 56"; +static const char pci_device_134d_7893[] = "HSP MicroModem 56"; +static const char pci_device_134d_7894[] = "HSP MicroModem 56"; +static const char pci_device_134d_7895[] = "HSP MicroModem 56"; +static const char pci_device_134d_7896[] = "HSP MicroModem 56"; +static const char pci_device_134d_7897[] = "HSP MicroModem 56"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134e[] = "CSTI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_134f[] = "Algo System Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1350[] = "Systec Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1351[] = "Sonix Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1353[] = "Thales Idatys"; +static const char pci_device_1353_0002[] = "Proserver"; +static const char pci_device_1353_0003[] = "PCI-FUT"; +static const char pci_device_1353_0004[] = "PCI-S0"; +static const char pci_device_1353_0005[] = "PCI-FUT-S0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1354[] = "Dwave System Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1355[] = "Kratos Analytical Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1356[] = "The Logical Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1359[] = "Prisa Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135a[] = "Brain Boxes"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135b[] = "Giganet Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135c[] = "Quatech Inc"; +static const char pci_device_135c_0010[] = "QSC-100"; +static const char pci_device_135c_0020[] = "DSC-100"; +static const char pci_device_135c_0030[] = "DSC-200/300"; +static const char pci_device_135c_0040[] = "QSC-200/300"; +static const char pci_device_135c_0050[] = "ESC-100D"; +static const char pci_device_135c_0060[] = "ESC-100M"; +static const char pci_device_135c_00f0[] = "MPAC-100 Syncronous Serial Card (Zilog 85230)"; +static const char pci_device_135c_0170[] = "QSCLP-100"; +static const char pci_device_135c_0180[] = "DSCLP-100"; +static const char pci_device_135c_0190[] = "SSCLP-100"; +static const char pci_device_135c_01a0[] = "QSCLP-200/300"; +static const char pci_device_135c_01b0[] = "DSCLP-200/300"; +static const char pci_device_135c_01c0[] = "SSCLP-200/300"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135d[] = "ABB Network Partner AB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135e[] = "Sealevel Systems Inc"; +static const char pci_device_135e_5101[] = "Route 56.PCI - Multi-Protocol Serial Interface (Zilog Z16C32)"; +static const char pci_device_135e_7101[] = "Single Port RS-232/422/485/530"; +static const char pci_device_135e_7201[] = "Dual Port RS-232/422/485 Interface"; +static const char pci_device_135e_7202[] = "Dual Port RS-232 Interface"; +static const char pci_device_135e_7401[] = "Four Port RS-232 Interface"; +static const char pci_device_135e_7402[] = "Four Port RS-422/485 Interface"; +static const char pci_device_135e_7801[] = "Eight Port RS-232 Interface"; +static const char pci_device_135e_7804[] = "Eight Port RS-232/422/485 Interface"; +static const char pci_device_135e_8001[] = "8001 Digital I/O Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_135f[] = "I-Data International A-S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1360[] = "Meinberg Funkuhren"; +static const char pci_device_1360_0101[] = "PCI32 DCF77 Radio Clock"; +static const char pci_device_1360_0102[] = "PCI509 DCF77 Radio Clock"; +static const char pci_device_1360_0103[] = "PCI510 DCF77 Radio Clock"; +static const char pci_device_1360_0104[] = "PCI511 DCF77 Radio Clock"; +static const char pci_device_1360_0201[] = "GPS167PCI GPS Receiver"; +static const char pci_device_1360_0202[] = "GPS168PCI GPS Receiver"; +static const char pci_device_1360_0203[] = "GPS169PCI GPS Receiver"; +static const char pci_device_1360_0204[] = "GPS170PCI GPS Receiver"; +static const char pci_device_1360_0301[] = "TCR510PCI IRIG Timecode Reader"; +static const char pci_device_1360_0302[] = "TCR167PCI IRIG Timecode Reader"; +static const char pci_device_1360_0303[] = "TCR511PCI IRIG Timecode Reader"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1361[] = "Soliton Systems K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1362[] = "Fujifacom Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1363[] = "Phoenix Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1364[] = "ATM Communications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1365[] = "Hypercope GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1366[] = "Teijin Seiki Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1367[] = "Hitachi Zosen Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1368[] = "Skyware Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1369[] = "Digigram"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136a[] = "High Soft Tech"; +static const char pci_device_136a_0004[] = "HST Saphir VII mini PCI"; +static const char pci_device_136a_0007[] = "HST Saphir III E MultiLink 4"; +static const char pci_device_136a_0008[] = "HST Saphir III E MultiLink 8"; +static const char pci_device_136a_000a[] = "HST Saphir III E MultiLink 2"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136b[] = "Kawasaki Steel Corporation"; +static const char pci_device_136b_ff01[] = "KL5A72002 Motion JPEG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136c[] = "Adtek System Science Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136d[] = "Gigalabs Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_136f[] = "Applied Magic Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1370[] = "ATL Products"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1371[] = "CNet Technology Inc"; +static const char pci_device_1371_434e[] = "GigaCard Network Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1371_434e_1371_434e[] = "N-Way PCI-Bus Giga-Card 1000/100/10Mbps(L)"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1373[] = "Silicon Vision Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1374[] = "Silicom Ltd."; +static const char pci_device_1374_0024[] = "Silicom Dual port Giga Ethernet BGE Bypass Server Adapter"; +static const char pci_device_1374_0025[] = "Silicom Quad port Giga Ethernet BGE Bypass Server Adapter"; +static const char pci_device_1374_0026[] = "Silicom Dual port Fiber Giga Ethernet 546 Bypass Server Adapter"; +static const char pci_device_1374_0027[] = "Silicom Dual port Fiber LX Giga Ethernet 546 Bypass Server Adapter"; +static const char pci_device_1374_0029[] = "Silicom Dual port Copper Giga Ethernet 546GB Bypass Server Adapter"; +static const char pci_device_1374_002a[] = "Silicom Dual port Fiber Giga Ethernet 546 TAP/Bypass Server Adapter"; +static const char pci_device_1374_002b[] = "Silicom Dual port Copper Fast Ethernet 546 TAP/Bypass Server Adapter (PXE2TBI)"; +static const char pci_device_1374_002c[] = "Silicom Quad port Copper Giga Ethernet 546GB Bypass Server Adapter (PXG4BPI)"; +static const char pci_device_1374_002d[] = "Silicom Quad port Fiber-SX Giga Ethernet 546GB Bypass Server Adapter (PXG4BPFI)"; +static const char pci_device_1374_002e[] = "Silicom Quad port Fiber-LX Giga Ethernet 546GB Bypass Server Adapter (PXG4BPFI-LX)"; +static const char pci_device_1374_002f[] = "Silicom Dual port Fiber-SX Giga Ethernet 546GB Low profile Bypass Server Adapter (PXG2BPFIL)"; +static const char pci_device_1374_0030[] = "Silicom Dual port Fiber-LX Giga Ethernet 546GB Low profile Bypass Server Adapter"; +static const char pci_device_1374_0031[] = "Silicom Quad port Copper Giga Ethernet PCI-E Bypass Server Adapter"; +static const char pci_device_1374_0032[] = "Silicom Dual port Copper Fast Ethernet 546 TAP/Bypass Server Adapter"; +static const char pci_device_1374_0034[] = "Silicom Dual port Copper Giga Ethernet PCI-E BGE Bypass Server Adapter"; +static const char pci_device_1374_0035[] = "Silicom Quad port Copper Giga Ethernet PCI-E BGE Bypass Server Adapter"; +static const char pci_device_1374_0036[] = "Silicom Dual port Fiber Giga Ethernet PCI-E BGE Bypass Server Adapter"; +static const char pci_device_1374_0037[] = "Silicom Quad port Copper Ethernet PCI-E Intel based Bypass Server Adapter"; +static const char pci_device_1374_0038[] = "Silicom Quad port Copper Ethernet PCI-E Intel based Bypass Server Adapter"; +static const char pci_device_1374_0039[] = "Silicom Dual port Fiber-SX Ethernet PCI-E Intel based Bypass Server Adapter"; +static const char pci_device_1374_003a[] = "Silicom Dual port Fiber-LX Ethernet PCI-E Intel based Bypass Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1375[] = "Argosystems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1376[] = "LMC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1377[] = "Electronic Equipment Production & Distribution GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1378[] = "Telemann Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1379[] = "Asahi Kasei Microsystems Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137a[] = "Mark of the Unicorn Inc"; +static const char pci_device_137a_0001[] = "PCI-324 Audiowire Interface"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137b[] = "PPT Vision"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137c[] = "Iwatsu Electric Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137d[] = "Dynachip Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137e[] = "Patriot Scientific Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_137f[] = "Japan Satellite Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1380[] = "Sanritz Automation Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1381[] = "Brains Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1382[] = "Marian - Electronic & Software"; +static const char pci_device_1382_0001[] = "ARC88 audio recording card"; +static const char pci_device_1382_2008[] = "Prodif 96 Pro sound system"; +static const char pci_device_1382_2048[] = "Prodif Plus sound system"; +static const char pci_device_1382_2088[] = "Marc 8 Midi sound system"; +static const char pci_device_1382_20c8[] = "Marc A sound system"; +static const char pci_device_1382_4008[] = "Marc 2 sound system"; +static const char pci_device_1382_4010[] = "Marc 2 Pro sound system"; +static const char pci_device_1382_4048[] = "Marc 4 MIDI sound system"; +static const char pci_device_1382_4088[] = "Marc 4 Digi sound system"; +static const char pci_device_1382_4248[] = "Marc X sound system"; +static const char pci_device_1382_4424[] = "TRACE D4 Sound System"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1383[] = "Controlnet Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1384[] = "Reality Simulation Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1385[] = "Netgear"; +static const char pci_device_1385_0013[] = "WG311T 108 Mbps Wireless PCI Adapter"; +static const char pci_device_1385_311a[] = "GA511 Gigabit Ethernet"; +static const char pci_device_1385_4100[] = "802.11b Wireless Adapter (MA301)"; +static const char pci_device_1385_4105[] = "MA311 802.11b wireless adapter"; +static const char pci_device_1385_4251[] = "WG111T 108 Mbps Wireless USB 2.0 Adapter"; +static const char pci_device_1385_4400[] = "WAG511 802.11a/b/g Dual Band Wireless PC Card"; +static const char pci_device_1385_4600[] = "WAG511 802.11a/b/g Dual Band Wireless PC Card"; +static const char pci_device_1385_4601[] = "WAG511 802.11a/b/g Dual Band Wireless PC Card"; +static const char pci_device_1385_4610[] = "WAG511 802.11a/b/g Dual Band Wireless PC Card"; +static const char pci_device_1385_4800[] = "WG511(v1) 54 Mbps Wireless PC Card"; +static const char pci_device_1385_4900[] = "WG311v1 54 Mbps Wireless PCI Adapter"; +static const char pci_device_1385_4a00[] = "WAG311 802.11a/g Wireless PCI Adapter"; +static const char pci_device_1385_4b00[] = "WG511T 108 Mbps Wireless PC Card"; +static const char pci_device_1385_4c00[] = "WG311v2 54 Mbps Wireless PCI Adapter"; +static const char pci_device_1385_4d00[] = "WG311T 108 Mbps Wireless PCI Adapter"; +static const char pci_device_1385_4e00[] = "WG511v2 54 Mbps Wireless PC Card"; +static const char pci_device_1385_4f00[] = "WG511U Double 108 Mbps Wireless PC Card"; +static const char pci_device_1385_5200[] = "GA511 Gigabit PC Card"; +static const char pci_device_1385_620a[] = "GA620 Gigabit Ethernet"; +static const char pci_device_1385_622a[] = "GA622"; +static const char pci_device_1385_630a[] = "GA630 Gigabit Ethernet"; +static const char pci_device_1385_6b00[] = "WG311v3 54 Mbps Wireless PCI Adapter"; +static const char pci_device_1385_6d00[] = "WPNT511 RangeMax 240 Mbps Wireless PC Card"; +static const char pci_device_1385_7b00[] = "WN511B RangeMax Next 280 Mbps Wireless PC Card"; +static const char pci_device_1385_7c00[] = "WN511T RangeMax Next 300 Mbps Wireless PC Card"; +static const char pci_device_1385_7d00[] = "WN311B RangeMax Next 270 Mbps Wireless PCI Adapter"; +static const char pci_device_1385_7e00[] = "WN311T RangeMax Next 300 Mbps Wireless PCI Adapter"; +static const char pci_device_1385_f004[] = "FA310TX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1386[] = "Video Domain Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1387[] = "Systran Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1388[] = "Hitachi Information Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1389[] = "Applicom International"; +static const char pci_device_1389_0001[] = "PCI1500PFB [Intelligent fieldbus adaptor]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138a[] = "Fusion Micromedia Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138b[] = "Tokimec Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138c[] = "Silicon Reality"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138d[] = "Future Techno Designs pte Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138e[] = "Basler GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_138f[] = "Patapsco Designs Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1390[] = "Concept Development Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1391[] = "Development Concepts Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1392[] = "Medialight Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1393[] = "Moxa Technologies Co Ltd"; +static const char pci_device_1393_1040[] = "Smartio C104H/PCI"; +static const char pci_device_1393_1141[] = "Industrio CP-114"; +static const char pci_device_1393_1680[] = "Smartio C168H/PCI"; +static const char pci_device_1393_2040[] = "Intellio CP-204J"; +static const char pci_device_1393_2180[] = "Intellio C218 Turbo PCI"; +static const char pci_device_1393_3200[] = "Intellio C320 Turbo PCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1394[] = "Level One Communications"; +static const char pci_device_1394_0001[] = "LXT1001 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1394_0001_1394_0001[] = "NetCelerator Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1395[] = "Ambicom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1396[] = "Cipher Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1397[] = "Cologne Chip Designs GmbH"; +static const char pci_device_1397_08b4[] = "ISDN network Controller [HFC-4S]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1397_08b4_1397_b520[] = "HFC-4S [IOB4ST]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1397_08b4_1397_b540[] = "HFC-4S [Swyx 4xS0 SX2 QuadBri]"; +#endif +static const char pci_device_1397_16b8[] = "ISDN network Controller [HFC-8S]"; +static const char pci_device_1397_2bd0[] = "ISDN network controller [HFC-PCI]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1397_2bd0_0675_1704[] = "ISDN Adapter (PCI Bus, D, C)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1397_2bd0_0675_1708[] = "ISDN Adapter (PCI Bus, D, C, ACPI)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1397_2bd0_1397_2bd0[] = "ISDN Board"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1397_2bd0_e4bf_1000[] = "CI1-1-Harp"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1398[] = "Clarion co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1399[] = "Rios systems Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139a[] = "Alacritech Inc"; +static const char pci_device_139a_0001[] = "Quad Port 10/100 Server Accelerator"; +static const char pci_device_139a_0003[] = "Single Port 10/100 Server Accelerator"; +static const char pci_device_139a_0005[] = "Single Port Gigabit Server Accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139b[] = "Mediasonic Multimedia Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139c[] = "Quantum 3d Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139d[] = "EPL limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139e[] = "Media4"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_139f[] = "Aethra s.r.l."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a0[] = "Crystal Group Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a1[] = "Kawasaki Heavy Industries Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a2[] = "Ositech Communications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a3[] = "Hifn Inc."; +static const char pci_device_13a3_0005[] = "7751 Security Processor"; +static const char pci_device_13a3_0006[] = "6500 Public Key Processor"; +static const char pci_device_13a3_0007[] = "7811 Security Processor"; +static const char pci_device_13a3_0012[] = "7951 Security Processor"; +static const char pci_device_13a3_0014[] = "78XX Security Processor"; +static const char pci_device_13a3_0016[] = "8065 Security Processor"; +static const char pci_device_13a3_0017[] = "8165 Security Processor"; +static const char pci_device_13a3_0018[] = "8154 Security Processor"; +static const char pci_device_13a3_001d[] = "7956 Security Processor"; +static const char pci_device_13a3_0020[] = "7955 Security Processor"; +static const char pci_device_13a3_0026[] = "8155 Security Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a4[] = "Rascom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a5[] = "Audio Digital Imaging Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a6[] = "Videonics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a7[] = "Teles AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a8[] = "Exar Corp."; +static const char pci_device_13a8_0152[] = "XR17C/D152 Dual PCI UART"; +static const char pci_device_13a8_0154[] = "XR17C154 Quad UART"; +static const char pci_device_13a8_0158[] = "XR17C158 Octal UART"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13a9[] = "Siemens Medical Systems, Ultrasound Group"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13aa[] = "Broadband Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ab[] = "Arcom Control Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ac[] = "Motion Media Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ad[] = "Nexus Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ae[] = "ALD Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13af[] = "T.Sqware"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b0[] = "Maxspeed Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b1[] = "Tamura corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b2[] = "Techno Chips Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b3[] = "Lanart Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b4[] = "Wellbean Co Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b5[] = "ARM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b6[] = "Dlog GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b7[] = "Logic Devices Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b8[] = "Nokia Telecommunications oy"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13b9[] = "Elecom Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ba[] = "Oxford Instruments"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13bb[] = "Sanyo Technosound Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13bc[] = "Bitran Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13bd[] = "Sharp corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13be[] = "Miroku Jyoho Service Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13bf[] = "Sharewave Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c0[] = "Microgate Corporation"; +static const char pci_device_13c0_0010[] = "SyncLink Adapter v1"; +static const char pci_device_13c0_0020[] = "SyncLink SCC Adapter"; +static const char pci_device_13c0_0030[] = "SyncLink Multiport Adapter"; +static const char pci_device_13c0_0210[] = "SyncLink Adapter v2"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c1[] = "3ware Inc"; +static const char pci_device_13c1_1000[] = "5xxx/6xxx-series PATA-RAID"; +static const char pci_device_13c1_1001[] = "7xxx/8xxx-series PATA/SATA-RAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13c1_1001_13c1_1001[] = "7xxx/8xxx-series PATA/SATA-RAID"; +#endif +static const char pci_device_13c1_1002[] = "9xxx-series SATA-RAID"; +static const char pci_device_13c1_1003[] = "9550SX SATA-RAID"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c2[] = "Technotrend Systemtechnik GmbH"; +static const char pci_device_13c2_000e[] = "Technotrend/Hauppauge DVB card rev2.3"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c3[] = "Janz Computer AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c4[] = "Phase Metrics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c5[] = "Alphi Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c6[] = "Condor Engineering Inc"; +static const char pci_device_13c6_0520[] = "CEI-520 A429 Card"; +static const char pci_device_13c6_0620[] = "CEI-620 A429 Card"; +static const char pci_device_13c6_0820[] = "CEI-820 A429 Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c7[] = "Blue Chip Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c8[] = "Apptech Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13c9[] = "Eaton Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ca[] = "Iomega Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13cb[] = "Yano Electric Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13cc[] = "Metheus Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13cd[] = "Compatible Systems Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ce[] = "Cocom A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13cf[] = "Studio Audio & Video Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d0[] = "Techsan Electronics Co Ltd"; +static const char pci_device_13d0_2103[] = "B2C2 FlexCopII DVB chip / Technisat SkyStar2 DVB card"; +static const char pci_device_13d0_2200[] = "B2C2 FlexCopIII DVB chip / Technisat SkyStar2 DVB card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d1[] = "Abocom Systems Inc"; +static const char pci_device_13d1_ab02[] = "ADMtek Centaur-C rev 17 [D-Link DFE-680TX] CardBus Fast Ethernet Adapter"; +static const char pci_device_13d1_ab03[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_13d1_ab06[] = "RTL8139 [FE2000VX] CardBus Fast Ethernet Attached Port Adapter"; +static const char pci_device_13d1_ab08[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d2[] = "Shark Multimedia Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d3[] = "IMC Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d4[] = "Graphics Microsystems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d5[] = "Media 100 Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d6[] = "K.I. Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d7[] = "Toshiba Engineering Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d8[] = "Phobos corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13d9[] = "Apex PC Solutions Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13da[] = "Intresource Systems pte Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13db[] = "Janich & Klass Computertechnik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13dc[] = "Netboost Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13dd[] = "Multimedia Bundle Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13de[] = "ABB Robotics Products AB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13df[] = "E-Tech Inc"; +static const char pci_device_13df_0001[] = "PCI56RVP Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13df_0001_13df_0001[] = "PCI56RVP Modem"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e0[] = "GVC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e1[] = "Silicom Multimedia Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e2[] = "Dynamics Research Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e3[] = "Nest Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e4[] = "Calculex Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e5[] = "Telesoft Design Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e6[] = "Argosy research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e7[] = "NAC Incorporated"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e8[] = "Chip Express Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13e9[] = "Intraserver Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ea[] = "Dallas Semiconductor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13eb[] = "Hauppauge Computer Works Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ec[] = "Zydacron Inc"; +static const char pci_device_13ec_000a[] = "NPC-RC01 Remote control receiver"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ed[] = "Raytheion E-Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ee[] = "Hayes Microcomputer Products Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ef[] = "Coppercom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f0[] = "Sundance Technology Inc / IC Plus Corp"; +static const char pci_device_13f0_0200[] = "IC Plus IP100A Integrated 10/100 Ethernet MAC + PHY"; +static const char pci_device_13f0_0201[] = "ST201 Sundance Ethernet"; +static const char pci_device_13f0_1023[] = "IC Plus IP1000 Family Gigabit Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f1[] = "Oce' - Technologies B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f2[] = "Ford Microelectronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f3[] = "Mcdata Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f4[] = "Troika Networks, Inc."; +static const char pci_device_13f4_1401[] = "Zentai Fibre Channel Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f5[] = "Kansai Electric Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f6[] = "C-Media Electronics Inc"; +static const char pci_device_13f6_0011[] = "CMI8738"; +static const char pci_device_13f6_0100[] = "CM8338A"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0100_13f6_ffff[] = "CMI8338/C3DX PCI Audio Device"; +#endif +static const char pci_device_13f6_0101[] = "CM8338B"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0101_13f6_0101[] = "CMI8338-031 PCI Audio Device"; +#endif +static const char pci_device_13f6_0111[] = "CM8738"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_1019_0970[] = "P6STP-FL motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_1043_8035[] = "CUSI-FX motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_1043_8077[] = "CMI8738 6-channel audio controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_1043_80e2[] = "CMI8738 6ch-MX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_13f6_0111[] = "CMI8738/C3DX PCI Audio Device"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13f6_0111_1681_a000[] = "Gamesurround MUSE XL"; +#endif +static const char pci_device_13f6_0211[] = "CM8738"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f7[] = "Wildfire Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f8[] = "Ad Lib Multimedia Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13f9[] = "NTT Advanced Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fa[] = "Pentland Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fb[] = "Aydin Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fc[] = "Computer Peripherals International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fd[] = "Micro Science Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13fe[] = "Advantech Co. Ltd"; +static const char pci_device_13fe_1240[] = "PCI-1240 4-channel stepper motor controller card"; +static const char pci_device_13fe_1600[] = "PCI-16xx series PCI multiport serial board (function 0)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13fe_1600_1601_0002[] = "PCI-1601 2-port unisolated RS-422/485"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13fe_1600_1602_0002[] = "PCI-1602 2-port isolated RS-422/485"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13fe_1600_1612_0004[] = "PCI-1612 4-port RS-232/422/485"; +#endif +static const char pci_device_13fe_16ff[] = "PCI-16xx series PCI multiport serial board (function 1: RX/TX steering CPLD)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13fe_16ff_1601_0000[] = "PCI-1601 2-port unisolated RS-422/485 PCI communications card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13fe_16ff_1602_0000[] = "PCI-1602 2-port isolated RS-422/485"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_13fe_16ff_1612_0000[] = "PCI-1612 4-port RS-232/422/485"; +#endif +static const char pci_device_13fe_1733[] = "PCI-1733 32-channel isolated digital input card"; +static const char pci_device_13fe_1752[] = "PCI-1752"; +static const char pci_device_13fe_1754[] = "PCI-1754"; +static const char pci_device_13fe_1756[] = "PCI-1756"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_13ff[] = "Silicon Spice Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1400[] = "Artx Inc"; +static const char pci_device_1400_1401[] = "9432 TX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1401[] = "CR-Systems A/S"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1402[] = "Meilhaus Electronic GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1403[] = "Ascor Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1404[] = "Fundamental Software Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1405[] = "Excalibur Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1406[] = "Oce' Printing Systems GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1407[] = "Lava Computer mfg Inc"; +static const char pci_device_1407_0100[] = "Lava Dual Serial"; +static const char pci_device_1407_0101[] = "Lava Quatro A"; +static const char pci_device_1407_0102[] = "Lava Quatro B"; +static const char pci_device_1407_0110[] = "Lava DSerial-PCI Port A"; +static const char pci_device_1407_0111[] = "Lava DSerial-PCI Port B"; +static const char pci_device_1407_0120[] = "Quattro-PCI A"; +static const char pci_device_1407_0121[] = "Quattro-PCI B"; +static const char pci_device_1407_0180[] = "Lava Octo A"; +static const char pci_device_1407_0181[] = "Lava Octo B"; +static const char pci_device_1407_0200[] = "Lava Port Plus"; +static const char pci_device_1407_0201[] = "Lava Quad A"; +static const char pci_device_1407_0202[] = "Lava Quad B"; +static const char pci_device_1407_0220[] = "Lava Quattro PCI Ports A/B"; +static const char pci_device_1407_0221[] = "Lava Quattro PCI Ports C/D"; +static const char pci_device_1407_0500[] = "Lava Single Serial"; +static const char pci_device_1407_0600[] = "Lava Port 650"; +static const char pci_device_1407_8000[] = "Lava Parallel"; +static const char pci_device_1407_8001[] = "Dual parallel port controller A"; +static const char pci_device_1407_8002[] = "Lava Dual Parallel port A"; +static const char pci_device_1407_8003[] = "Lava Dual Parallel port B"; +static const char pci_device_1407_8800[] = "BOCA Research IOPPAR"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1408[] = "Aloka Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1409[] = "Timedia Technology Co Ltd"; +static const char pci_device_1409_7168[] = "PCI2S550 (Dual 16550 UART)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140a[] = "DSP Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140b[] = "Ramix Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140c[] = "Elmic Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140d[] = "Matsushita Electric Works Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140e[] = "Goepel Electronic GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_140f[] = "Salient Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1410[] = "Midas lab Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1411[] = "Ikos Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1412[] = "VIA Technologies Inc."; +static const char pci_device_1412_1712[] = "ICE1712 [Envy24] PCI Multi-Channel I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_1712[] = "Hoontech ST Audio DSP 24"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d630[] = "M-Audio Delta 1010"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d631[] = "M-Audio Delta DiO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d632[] = "M-Audio Delta 66"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d633[] = "M-Audio Delta 44"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d634[] = "M-Audio Delta Audiophile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d635[] = "M-Audio Delta TDIF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d637[] = "M-Audio Delta RBUS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d638[] = "M-Audio Delta 410"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d63b[] = "M-Audio Delta 1010LT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1412_d63c[] = "Digigram VX442"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_1416_1712[] = "Hoontech ST Audio DSP 24 Media 7.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_1115[] = "EWS88 MT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_1125[] = "EWS88 MT (Master)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_112b[] = "EWS88 D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_112c[] = "EWS88 D (Master)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_1130[] = "EWX 24/96"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_1138[] = "DMX 6fire 24/96"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_153b_1151[] = "PHASE88"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1712_16ce_1040[] = "Edirol DA-2496"; +#endif +static const char pci_device_1412_1724[] = "VT1720/24 [Envy24PT/HT] PCI Multi-Channel Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_1412_1724[] = "Albatron PX865PE 7.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_1412_3630[] = "M-Audio Revolution 7.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_1412_3631[] = "M-Audio Revolution 5.1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_153b_1145[] = "Aureon 7.1 Space"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_153b_1147[] = "Aureon 5.1 Sky"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_153b_1153[] = "Aureon 7.1 Universe"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_270f_f641[] = "ZNF3-150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1412_1724_270f_f645[] = "ZNF3-250"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1413[] = "Addonics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1414[] = "Microsoft Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1415[] = "Oxford Semiconductor Ltd"; +static const char pci_device_1415_8403[] = "VScom 011H-EP1 1 port parallel adaptor"; +static const char pci_device_1415_9500[] = "OX16PCI954 (Quad 16950 UART) function 0 (Disabled)"; +static const char pci_device_1415_9501[] = "OX16PCI954 (Quad 16950 UART) function 0 (Uart)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9501_12c4_0201[] = "Titan/cPCI (2 port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9501_12c4_0202[] = "Titan/cPCI (4 port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9501_12c4_0203[] = "Titan/cPCI (8 port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9501_12c4_0210[] = "Titan/104-Plus (8 port, p1-4)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9501_131f_2050[] = "CyberPro (4-port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9501_131f_2051[] = "CyberSerial 4S Plus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9501_15ed_2000[] = "MCCR Serial p0-3 of 8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9501_15ed_2001[] = "MCCR Serial p0-3 of 16"; +#endif +static const char pci_device_1415_950a[] = "EXSYS EX-41092 Dual 16950 Serial adapter"; +static const char pci_device_1415_950b[] = "OXCB950 Cardbus 16950 UART"; +static const char pci_device_1415_9510[] = "OX16PCI954 (Quad 16950 UART) function 1 (Disabled)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9510_12c4_0200[] = "Titan/cPCI (Unused)"; +#endif +static const char pci_device_1415_9511[] = "OX16PCI954 (Quad 16950 UART) function 1 (8bit bus)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9511_12c4_0211[] = "Titan/104-Plus (8 port, p5-8)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9511_15ed_2000[] = "MCCR Serial p4-7 of 8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1415_9511_15ed_2001[] = "MCCR Serial p4-15 of 16"; +#endif +static const char pci_device_1415_9512[] = "OX16PCI954 (Quad 16950 UART) function 1 (32bit bus)"; +static const char pci_device_1415_9513[] = "OX16PCI954 (Quad 16950 UART) function 1 (parallel port)"; +static const char pci_device_1415_9521[] = "OX16PCI952 (Dual 16950 UART)"; +static const char pci_device_1415_9523[] = "OX16PCI952 Integrated Parallel Port"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1416[] = "Multiwave Innovation pte Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1417[] = "Convergenet Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1418[] = "Kyushu electronics systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1419[] = "Excel Switching Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141a[] = "Apache Micro Peripherals Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141b[] = "Zoom Telephonics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141d[] = "Digitan Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141e[] = "Fanuc Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_141f[] = "Visiontech Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1420[] = "Psion Dacom plc"; +static const char pci_device_1420_8002[] = "Gold Card NetGlobal 56k+10/100Mb CardBus (Ethernet part)"; +static const char pci_device_1420_8003[] = "Gold Card NetGlobal 56k+10/100Mb CardBus (Modem part)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1421[] = "Ads Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1422[] = "Ygrec Systems Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1423[] = "Custom Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1424[] = "Videoserver Connections"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1425[] = "Chelsio Communications Inc"; +static const char pci_device_1425_000b[] = "T210 Protocol Engine"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1426[] = "Storage Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1427[] = "Better On-Line Solutions"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1428[] = "Edec Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1429[] = "Unex Technology Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142a[] = "Kingmax Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142b[] = "Radiolan"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142c[] = "Minton Optic Industry Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142d[] = "Pix stream Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142e[] = "Vitec Multimedia"; +static const char pci_device_142e_4020[] = "VM2-2 [Video Maker 2] MPEG1/2 Encoder"; +static const char pci_device_142e_4337[] = "VM2-2-C7 [Video Maker 2 rev. C7] MPEG1/2 Encoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_142f[] = "Radicom Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1430[] = "ITT Aerospace/Communications Division"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1431[] = "Gilat Satellite Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1432[] = "Edimax Computer Co."; +static const char pci_device_1432_9130[] = "RTL81xx Fast Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1433[] = "Eltec Elektronik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1435[] = "RTD Embedded Technologies, Inc."; +static const char pci_device_1435_4520[] = "PCI4520"; +static const char pci_device_1435_6020[] = "SPM6020"; +static const char pci_device_1435_6030[] = "SPM6030"; +static const char pci_device_1435_6420[] = "SPM186420"; +static const char pci_device_1435_6430[] = "SPM176430"; +static const char pci_device_1435_7520[] = "DM7520"; +static const char pci_device_1435_7820[] = "DM7820"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1436[] = "CIS Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1437[] = "Nissin Inc Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1438[] = "Atmel-dream"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1439[] = "Outsource Engineering & Mfg. Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143a[] = "Stargate Solutions Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143b[] = "Canon Research Center, America"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143c[] = "Amlogic Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143d[] = "Tamarack Microelectronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143e[] = "Jones Futurex Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_143f[] = "Lightwell Co Ltd - Zax Division"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1440[] = "ALGOL Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1441[] = "AGIE Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1442[] = "Phoenix Contact GmbH & Co."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1443[] = "Unibrain S.A."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1444[] = "TRW"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1445[] = "Logical DO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1446[] = "Graphin Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1447[] = "AIM GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1448[] = "Alesis Studio Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1449[] = "TUT Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144a[] = "Adlink Technology"; +static const char pci_device_144a_7296[] = "PCI-7296"; +static const char pci_device_144a_7432[] = "PCI-7432"; +static const char pci_device_144a_7433[] = "PCI-7433"; +static const char pci_device_144a_7434[] = "PCI-7434"; +static const char pci_device_144a_7841[] = "PCI-7841"; +static const char pci_device_144a_8133[] = "PCI-8133"; +static const char pci_device_144a_8164[] = "PCI-8164"; +static const char pci_device_144a_8554[] = "PCI-8554"; +static const char pci_device_144a_9111[] = "PCI-9111"; +static const char pci_device_144a_9113[] = "PCI-9113"; +static const char pci_device_144a_9114[] = "PCI-9114"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144b[] = "Loronix Information Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144c[] = "Catalina Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144d[] = "Samsung Electronics Co Ltd"; +static const char pci_device_144d_c00c[] = "P35 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144e[] = "OLITEC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_144f[] = "Askey Computer Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1450[] = "Octave Communications Ind."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1451[] = "SP3D Chip Design GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1453[] = "MYCOM Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1454[] = "Altiga Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1455[] = "Logic Plus Plus Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1456[] = "Advanced Hardware Architectures"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1457[] = "Nuera Communications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1458[] = "Giga-byte Technology"; +static const char pci_device_1458_0c11[] = "K8NS Pro Mainboard"; +static const char pci_device_1458_e911[] = "GN-WIAG02"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1459[] = "DOOIN Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145a[] = "Escalate Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145b[] = "PRAIM SRL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145c[] = "Cryptek"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145d[] = "Gallant Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145e[] = "Aashima Technology B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_145f[] = "Baldor Electric Company"; +static const char pci_device_145f_0001[] = "NextMove PCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1460[] = "DYNARC INC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1461[] = "Avermedia Technologies Inc"; +static const char pci_device_1461_f436[] = "AVerTV Hybrid+FM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1462[] = "Micro-Star International Co., Ltd."; +static const char pci_device_1462_5501[] = "nVidia NV15DDR [GeForce2 Ti]"; +static const char pci_device_1462_6819[] = "Broadcom Corporation BCM4306 802.11b/g Wireless LAN Controller [MSI CB54G]"; +static const char pci_device_1462_6825[] = "PCI Card wireless 11g [PC54G]"; +static const char pci_device_1462_6834[] = "RaLink RT2500 802.11g [PC54G2]"; +static const char pci_device_1462_7125[] = "K8N motherboard"; +static const char pci_device_1462_8725[] = "NVIDIA NV25 [GeForce4 Ti 4600] VGA Adapter"; +static const char pci_device_1462_9000[] = "NVIDIA NV28 [GeForce4 Ti 4800] VGA Adapter"; +static const char pci_device_1462_9110[] = "GeFORCE FX5200"; +static const char pci_device_1462_9119[] = "NVIDIA NV31 [GeForce FX 5600XT] VGA Adapter"; +static const char pci_device_1462_9123[] = "NVIDIA NV31 [GeForce FX 5600] FX5600-VTDR128 [MS-8912]"; +static const char pci_device_1462_9510[] = "Radeon 9600XT"; +static const char pci_device_1462_9511[] = "Radeon 9600XT"; +static const char pci_device_1462_9591[] = "nVidia Corporation NV36 [GeForce FX 5700LE]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1463[] = "Fast Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1464[] = "Interactive Circuits & Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1465[] = "GN NETTEST Telecom DIV."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1466[] = "Designpro Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1467[] = "DIGICOM SPA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1468[] = "AMBIT Microsystem Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1469[] = "Cleveland Motion Controls"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146a[] = "IFR"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146b[] = "Parascan Technologies Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146c[] = "Ruby Tech Corp."; +static const char pci_device_146c_1430[] = "FE-1430TX Fast Ethernet PCI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146d[] = "Tachyon, INC."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146e[] = "Williams Electronics Games, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_146f[] = "Multi Dimensional Consulting Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1470[] = "Bay Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1471[] = "Integrated Telecom Express Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1472[] = "DAIKIN Industries, Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1473[] = "ZAPEX Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1474[] = "Doug Carson & Associates"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1475[] = "PICAZO Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1476[] = "MORTARA Instrument Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1477[] = "Net Insight"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1478[] = "DIATREND Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1479[] = "TORAY Industries Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147a[] = "FORMOSA Industrial Computing"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147b[] = "ABIT Computer Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147c[] = "AWARE, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147d[] = "Interworks Computer Products"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147e[] = "Matsushita Graphic Communication Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_147f[] = "NIHON UNISYS, Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1480[] = "SCII Telecom"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1481[] = "BIOPAC Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1482[] = "ISYTEC - Integrierte Systemtechnik GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1483[] = "LABWAY Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1484[] = "Logic Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1485[] = "ERMA - Electronic GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1486[] = "L3 Communications Telemetry & Instrumentation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1487[] = "MARQUETTE Medical Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1488[] = "KONTRON Electronik GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1489[] = "KYE Systems Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148a[] = "OPTO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148b[] = "INNOMEDIALOGIC Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148c[] = "C.P. Technology Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148d[] = "DIGICOM Systems, Inc."; +static const char pci_device_148d_1003[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148e[] = "OSI Plus Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_148f[] = "Plant Equipment, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1490[] = "Stone Microsystems PTY Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1491[] = "ZEAL Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1492[] = "Time Logic Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1493[] = "MAKER Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1494[] = "WINTOP Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1495[] = "TOKAI Communications Industry Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1496[] = "JOYTECH Computer Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1497[] = "SMA Regelsysteme GmBH"; +static const char pci_device_1497_1497[] = "SMA Technologie AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1498[] = "TEWS Datentechnik GmBH"; +static const char pci_device_1498_0330[] = "TPMC816 2 Channel CAN bus controller."; +static const char pci_device_1498_0385[] = "TPMC901 Extended CAN bus with 2/4/6 CAN controller"; +static const char pci_device_1498_21cc[] = "TCP460 CompactPCI 16 Channel Serial Interface RS232/RS422"; +static const char pci_device_1498_21cd[] = "TCP461 CompactPCI 8 Channel Serial Interface RS232/RS422"; +static const char pci_device_1498_30c8[] = "TPCI200"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1499[] = "EMTEC CO., Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149a[] = "ANDOR Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149b[] = "SEIKO Instruments Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149c[] = "OVISLINK Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149d[] = "NEWTEK Inc"; +static const char pci_device_149d_0001[] = "Video Toaster for PC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149e[] = "Mapletree Networks Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_149f[] = "LECTRON Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a0[] = "SOFTING GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a1[] = "Systembase Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a2[] = "Millennium Engineering Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a3[] = "Maverick Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a4[] = "GVC/BCM Advanced Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a5[] = "XIONICS Document Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a6[] = "INOVA Computers GmBH & Co KG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a7[] = "MYTHOS Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a8[] = "FEATRON Technologies Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14a9[] = "HIVERTEC Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14aa[] = "Advanced MOS Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ab[] = "Mentor Graphics Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ac[] = "Novaweb Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ad[] = "Time Space Radio AB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ae[] = "CTI, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14af[] = "Guillemot Corporation"; +static const char pci_device_14af_7102[] = "3D Prophet II MX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b0[] = "BST Communication Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b1[] = "Nextcom K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b2[] = "ENNOVATE Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b3[] = "XPEED Inc"; +static const char pci_device_14b3_0000[] = "DSL NIC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b4[] = "PHILIPS Business Electronics B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b5[] = "Creamware GmBH"; +static const char pci_device_14b5_0200[] = "Scope"; +static const char pci_device_14b5_0300[] = "Pulsar"; +static const char pci_device_14b5_0400[] = "PulsarSRB"; +static const char pci_device_14b5_0600[] = "Pulsar2"; +static const char pci_device_14b5_0800[] = "DSP-Board"; +static const char pci_device_14b5_0900[] = "DSP-Board"; +static const char pci_device_14b5_0a00[] = "DSP-Board"; +static const char pci_device_14b5_0b00[] = "DSP-Board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b6[] = "Quantum Data Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b7[] = "PROXIM Inc"; +static const char pci_device_14b7_0001[] = "Symphony 4110"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b8[] = "Techsoft Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14b9[] = "AIRONET Wireless Communications"; +static const char pci_device_14b9_0001[] = "PC4800"; +static const char pci_device_14b9_0340[] = "PC4800"; +static const char pci_device_14b9_0350[] = "PC4800"; +static const char pci_device_14b9_4500[] = "PC4500"; +static const char pci_device_14b9_4800[] = "Cisco Aironet 340 802.11b Wireless LAN Adapter/Aironet PC4800"; +static const char pci_device_14b9_a504[] = "Cisco Aironet Wireless 802.11b"; +static const char pci_device_14b9_a505[] = "Cisco Aironet CB20a 802.11a Wireless LAN Adapter"; +static const char pci_device_14b9_a506[] = "Cisco Aironet Mini PCI b/g"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ba[] = "INTERNIX Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14bb[] = "SEMTECH Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14bc[] = "Globespan Semiconductor Inc."; +static const char pci_device_14bc_d002[] = "Pulsar [PCI ADSL Card]"; +static const char pci_device_14bc_d00f[] = "Pulsar [PCI ADSL Card]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14bd[] = "CARDIO Control N.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14be[] = "L3 Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14bf[] = "SPIDER Communications Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c0[] = "COMPAL Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c1[] = "MYRICOM Inc."; +static const char pci_device_14c1_0008[] = "Myri-10G Dual-Protocol NIC (10G-PCIE-8A)"; +static const char pci_device_14c1_8043[] = "Myrinet 2000 Scalable Cluster Interconnect"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14c1_8043_103c_1240[] = "Myrinet M2L-PCI64/2-3.0 LANai 7.4 (HP OEM)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c2[] = "DTK Computer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c3[] = "MEDIATEK Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c4[] = "IWASAKI Information Systems Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c5[] = "Automation Products AB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c6[] = "Data Race Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c7[] = "Modular Technology Holdings Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c8[] = "Turbocomm Tech. Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14c9[] = "ODIN Telesystems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ca[] = "PE Logic Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14cb[] = "Billionton Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14cc[] = "NAKAYO Telecommunications Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14cd[] = "Universal Scientific Ind."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ce[] = "Whistle Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14cf[] = "TEK Microsystems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d0[] = "Ericsson Axe R & D"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d1[] = "Computer Hi-Tech Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d2[] = "Titan Electronics Inc"; +static const char pci_device_14d2_8001[] = "VScom 010L 1 port parallel adaptor"; +static const char pci_device_14d2_8002[] = "VScom 020L 2 port parallel adaptor"; +static const char pci_device_14d2_8010[] = "VScom 100L 1 port serial adaptor"; +static const char pci_device_14d2_8011[] = "VScom 110L 1 port serial and 1 port parallel adaptor"; +static const char pci_device_14d2_8020[] = "VScom 200L 1 port serial adaptor"; +static const char pci_device_14d2_8021[] = "VScom 210L 2 port serial and 1 port parallel adaptor"; +static const char pci_device_14d2_8040[] = "VScom 400L 4 port serial adaptor"; +static const char pci_device_14d2_8080[] = "VScom 800L 8 port serial adaptor"; +static const char pci_device_14d2_a000[] = "VScom 010H 1 port parallel adaptor"; +static const char pci_device_14d2_a001[] = "VScom 100H 1 port serial adaptor"; +static const char pci_device_14d2_a003[] = "VScom 400H 4 port serial adaptor"; +static const char pci_device_14d2_a004[] = "VScom 400HF1 4 port serial adaptor"; +static const char pci_device_14d2_a005[] = "VScom 200H 2 port serial adaptor"; +static const char pci_device_14d2_e001[] = "VScom 010HV2 1 port parallel adaptor"; +static const char pci_device_14d2_e010[] = "VScom 100HV2 1 port serial adaptor"; +static const char pci_device_14d2_e020[] = "VScom 200HV2 2 port serial adaptor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d3[] = "CIRTECH (UK) Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d4[] = "Panacom Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d5[] = "Nitsuko Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d6[] = "Accusys Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d7[] = "Hirakawa Hewtech Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d8[] = "HOPF Elektronik GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14d9[] = "Alliance Semiconductor Corporation"; +static const char pci_device_14d9_0010[] = "AP1011/SP1011 HyperTransport-PCI Bridge [Sturgeon]"; +static const char pci_device_14d9_9000[] = "AS90L10204/10208 HyperTransport to PCI-X Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14da[] = "National Aerospace Laboratories"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14db[] = "AFAVLAB Technology Inc"; +static const char pci_device_14db_2120[] = "TK9902"; +static const char pci_device_14db_2182[] = "AFAVLAB Technology Inc. 8-port serial card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14dc[] = "Amplicon Liveline Ltd"; +static const char pci_device_14dc_0000[] = "PCI230"; +static const char pci_device_14dc_0001[] = "PCI242"; +static const char pci_device_14dc_0002[] = "PCI244"; +static const char pci_device_14dc_0003[] = "PCI247"; +static const char pci_device_14dc_0004[] = "PCI248"; +static const char pci_device_14dc_0005[] = "PCI249"; +static const char pci_device_14dc_0006[] = "PCI260"; +static const char pci_device_14dc_0007[] = "PCI224"; +static const char pci_device_14dc_0008[] = "PCI234"; +static const char pci_device_14dc_0009[] = "PCI236"; +static const char pci_device_14dc_000a[] = "PCI272"; +static const char pci_device_14dc_000b[] = "PCI215"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14dd[] = "Boulder Design Labs Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14de[] = "Applied Integration Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14df[] = "ASIC Communications Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e1[] = "INVERTEX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e2[] = "INFOLIBRIA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e3[] = "AMTELCO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e4[] = "Broadcom Corporation"; +static const char pci_device_14e4_0800[] = "Sentry5 Chipcommon I/O Controller"; +static const char pci_device_14e4_0804[] = "Sentry5 PCI Bridge"; +static const char pci_device_14e4_0805[] = "Sentry5 MIPS32 CPU"; +static const char pci_device_14e4_0806[] = "Sentry5 Ethernet Controller"; +static const char pci_device_14e4_080b[] = "Sentry5 Crypto Accelerator"; +static const char pci_device_14e4_080f[] = "Sentry5 DDR/SDR RAM Controller"; +static const char pci_device_14e4_0811[] = "Sentry5 External Interface Core"; +static const char pci_device_14e4_0816[] = "BCM3302 Sentry5 MIPS32 CPU"; +static const char pci_device_14e4_1600[] = "NetXtreme BCM5752 Gigabit Ethernet PCI Express"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1600_107b_5048[] = "E4500 Onboard"; +#endif +static const char pci_device_14e4_1601[] = "NetXtreme BCM5752M Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_1644[] = "NetXtreme BCM5700 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1014_0277[] = "Broadcom Vigil B5700 1000Base-T"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1028_00d1[] = "Broadcom BCM5700"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1028_0106[] = "Broadcom BCM5700"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1028_0109[] = "Broadcom BCM5700 1000Base-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_1028_010a[] = "Broadcom BCM5700 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1000[] = "3C996-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1001[] = "3C996B-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1002[] = "3C996C-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1003[] = "3C997-T 1000Base-T Dual Port"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1004[] = "3C996-SX 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1005[] = "3C997-SX 1000Base-SX Dual Port"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_10b7_1008[] = "3C942 Gigabit LOM (31X31)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_0002[] = "NetXtreme 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_0003[] = "NetXtreme 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_0004[] = "NetXtreme 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_1028[] = "NetXtreme 1000BaseTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1644_14e4_1644[] = "BCM5700 1000Base-T"; +#endif +static const char pci_device_14e4_1645[] = "NetXtreme BCM5701 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_007c[] = "NC7770 Gigabit Server Adapter (PCI-X, 10/100/1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_007d[] = "NC6770 Gigabit Server Adapter (PCI-X, 1000-SX)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_0085[] = "NC7780 Gigabit Server Adapter (embedded, WOL)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_0099[] = "NC7780 Gigabit Server Adapter (embedded, WOL)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_009a[] = "NC7770 Gigabit Server Adapter (PCI-X, 10/100/1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_0e11_00c1[] = "NC6770 Gigabit Server Adapter (PCI-X, 1000-SX)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_1028_0121[] = "Broadcom BCM5701 1000Base-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_103c_128a[] = "1000Base-T (PCI) [A7061A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_103c_128b[] = "1000Base-SX (PCI) [A7073A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_103c_12a4[] = "Core Lan 1000Base-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_103c_12c1[] = "IOX Core Lan 1000Base-T [A7109AX]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_103c_1300[] = "Core LAN/SCSI Combo [A6794A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10a9_8010[] = "IO9/IO10 Gigabit Ethernet (Copper)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10a9_8011[] = "Gigabit Ethernet (Copper)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10a9_8012[] = "Gigabit Ethernet (Fiber)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10b7_1004[] = "3C996-SX 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10b7_1006[] = "3C996B-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10b7_1007[] = "3C1000-T 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_10b7_1008[] = "3C940-BR01 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0001[] = "BCM5701 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0005[] = "BCM5701 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0006[] = "BCM5701 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0007[] = "BCM5701 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_0008[] = "BCM5701 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1645_14e4_8008[] = "BCM5701 1000Base-T"; +#endif +static const char pci_device_14e4_1646[] = "NetXtreme BCM5702 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1646_0e11_00bb[] = "NC7760 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1646_1028_0126[] = "Broadcom BCM5702 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1646_14e4_8009[] = "BCM5702 1000BaseTX"; +#endif +static const char pci_device_14e4_1647[] = "NetXtreme BCM5703 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_0e11_0099[] = "NC7780 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_0e11_009a[] = "NC7770 1000BaseTX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_10a9_8010[] = "SGI IO9 Gigabit Ethernet (Copper)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_0009[] = "BCM5703 1000BaseTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_000a[] = "BCM5703 1000BaseSX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_000b[] = "BCM5703 1000BaseTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_8009[] = "BCM5703 1000BaseTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1647_14e4_800a[] = "BCM5703 1000BaseTX"; +#endif +static const char pci_device_14e4_1648[] = "NetXtreme BCM5704 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_0e11_00cf[] = "NC7772 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_0e11_00d0[] = "NC7782 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_0e11_00d1[] = "NC7783 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_10a9_8013[] = "Dual Port Gigabit Ethernet (PCI-X,Copper)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_10a9_8018[] = "Dual Port Gigabit Ethernet (A330)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_10a9_801a[] = "Dual Port Gigabit Ethernet (IA-blade)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_10a9_801b[] = "Quad Port Gigabit Ethernet (PCI-E,Copper)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_10b7_2000[] = "3C998-T Dual Port 10/100/1000 PCI-X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_10b7_3000[] = "3C999-T Quad Port 10/100/1000 PCI-X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_1166_1648[] = "NetXtreme CIOB-E 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1648_1734_100b[] = "Primergy RX300"; +#endif +static const char pci_device_14e4_164a[] = "NetXtreme II BCM5706 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_164a_103c_3070[] = "NC380T PCI Express Dual Port Multifunction Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_164a_103c_3101[] = "NC370T MultifuNCtion Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_164c[] = "NetXtreme II BCM5708 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_164c_103c_7037[] = "NC373T PCI Express Multifunction Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_164c_103c_7038[] = "NC373i Integrated Multifunction Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_164d[] = "NetXtreme BCM5702FE Gigabit Ethernet"; +static const char pci_device_14e4_1653[] = "NetXtreme BCM5705 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1653_0e11_00e3[] = "NC7761 Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_1654[] = "NetXtreme BCM5705_2 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1654_0e11_00e3[] = "NC7761 Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1654_103c_3100[] = "NC1020 ProLiant Gigabit Server Adapter 32 PCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1654_103c_3226[] = "NC150T 4-port Gigabit Combo Switch & Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_1659[] = "NetXtreme BCM5721 Gigabit Ethernet PCI Express"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1659_1014_02c6[] = "eServer xSeries server mainboard"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1659_103c_7031[] = "NC320T PCIe Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1659_103c_7032[] = "NC320i PCIe Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1659_1734_1061[] = "Primergy RX300 S2"; +#endif +static const char pci_device_14e4_165d[] = "NetXtreme BCM5705M Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_165d_1028_865d[] = "Latitude D400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_165e[] = "NetXtreme BCM5705M_2 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_165e_103c_088c[] = "NC8000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_165e_103c_0890[] = "NC6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_165e_103c_099c[] = "NX6110/NC6120"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_1668[] = "NetXtreme BCM5714 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1668_103c_7039[] = "NC324i PCIe Dual Port Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_1669[] = "NetXtreme 5714S Gigabit Ethernet"; +static const char pci_device_14e4_166a[] = "NetXtreme BCM5780 Gigabit Ethernet"; +static const char pci_device_14e4_166b[] = "NetXtreme BCM5780S Gigabit Ethernet"; +static const char pci_device_14e4_166e[] = "570x 10/100 Integrated Controller"; +static const char pci_device_14e4_1672[] = "NetXtreme BCM5754M Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_1673[] = "NetXtreme BCM5755M Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_1677[] = "NetXtreme BCM5751 Gigabit Ethernet PCI Express"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1677_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1677_1028_0182[] = "Latitude D610"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1677_1028_0187[] = "Precision M70"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1677_1028_01ad[] = "Optiplex GX620"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1677_103c_3006[] = "DC7100 SFF(DX878AV)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1677_1734_105d[] = "Scenic W620"; +#endif +static const char pci_device_14e4_1678[] = "NetXtreme BCM5715 Gigabit Ethernet"; +static const char pci_device_14e4_1679[] = "NetXtreme BCM5715S Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1679_103c_1707[] = "NC326m PCIe Dual Port Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1679_103c_170c[] = "NC325m PCIe Quad Port Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1679_103c_703c[] = "NC326i PCIe Dual Port Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_167a[] = "NetXtreme BCM5754 Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_167b[] = "NetXtreme BCM5755 Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_167d[] = "NetXtreme BCM5751M Gigabit Ethernet PCI Express"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_167d_17aa_2081[] = "Thinkpad R60e model 0657"; +#endif +static const char pci_device_14e4_167e[] = "NetXtreme BCM5751F Fast Ethernet PCI Express"; +static const char pci_device_14e4_1693[] = "NetLink BCM5787M Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_1696[] = "NetXtreme BCM5782 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1696_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_1696_14e4_000d[] = "NetXtreme BCM5782 1000Base-T"; +#endif +static const char pci_device_14e4_169a[] = "NetLink BCM5786 Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_169b[] = "NetLink BCM5787 Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_169c[] = "NetXtreme BCM5788 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_169c_103c_308b[] = "MX6125"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_169d[] = "NetLink BCM5789 Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_16a6[] = "NetXtreme BCM5702X Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a6_0e11_00bb[] = "NC7760 Gigabit Server Adapter (PCI-X, 10/100/1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a6_1028_0126[] = "BCM5702 1000Base-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a6_14e4_000c[] = "BCM5702 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a6_14e4_8009[] = "BCM5702 1000Base-T"; +#endif +static const char pci_device_14e4_16a7[] = "NetXtreme BCM5703X Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_0e11_00ca[] = "NC7771 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_0e11_00cb[] = "NC7781 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_14e4_0009[] = "NetXtreme BCM5703 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_14e4_000a[] = "NetXtreme BCM5703 1000Base-SX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_14e4_000b[] = "NetXtreme BCM5703 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a7_14e4_800a[] = "NetXtreme BCM5703 1000Base-T"; +#endif +static const char pci_device_14e4_16a8[] = "NetXtreme BCM5704S Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a8_10a9_8014[] = "Dual Port Gigabit Ethernet (PCI-X,Fiber)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a8_10a9_801c[] = "Quad Port Gigabit Ethernet (PCI-E,Fiber)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16a8_10b7_2001[] = "3C998-SX Dual Port 1000-SX PCI-X"; +#endif +static const char pci_device_14e4_16aa[] = "NetXtreme II BCM5706S Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16aa_103c_3102[] = "NC370F MultifuNCtion Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_16ac[] = "NetXtreme II BCM5708S Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16ac_103c_1706[] = "NC373m Multifunction Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16ac_103c_703b[] = "NC373i Integrated Multifunction Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16ac_103c_703d[] = "NC373F PCI Express Multifunction Gigabit Server Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_16c6[] = "NetXtreme BCM5702A3 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c6_10b7_1100[] = "3C1000B-T 10/100/1000 PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c6_14e4_000c[] = "BCM5702 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c6_14e4_8009[] = "BCM5702 1000Base-T"; +#endif +static const char pci_device_14e4_16c7[] = "NetXtreme BCM5703 Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_0e11_00ca[] = "NC7771 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_0e11_00cb[] = "NC7781 Gigabit Server Adapter (PCI-X, 10,100,1000-T)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_103c_12c3[] = "Combo FC/GigE-SX [A9782A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_103c_12ca[] = "Combo FC/GigE-T [A9784A]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_14e4_0009[] = "NetXtreme BCM5703 1000Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_16c7_14e4_000a[] = "NetXtreme BCM5703 1000Base-SX"; +#endif +static const char pci_device_14e4_16dd[] = "NetLink BCM5781 Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_16f7[] = "NetXtreme BCM5753 Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_16fd[] = "NetXtreme BCM5753M Gigabit Ethernet PCI Express"; +static const char pci_device_14e4_16fe[] = "NetXtreme BCM5753F Fast Ethernet PCI Express"; +static const char pci_device_14e4_170c[] = "BCM4401-B0 100Base-TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_170c_1028_0188[] = "Inspiron 6000 laptop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_170c_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_170c_103c_099c[] = "NX6110/NC6120"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_170d[] = "NetXtreme BCM5901 100Base-TX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_170d_1014_0545[] = "ThinkPad R40e (2684-HVG) builtin ethernet controller"; +#endif +static const char pci_device_14e4_170e[] = "NetXtreme BCM5901 100Base-TX"; +static const char pci_device_14e4_3352[] = "BCM3352"; +static const char pci_device_14e4_3360[] = "BCM3360"; +static const char pci_device_14e4_4210[] = "BCM4210 iLine10 HomePNA 2.0"; +static const char pci_device_14e4_4211[] = "BCM4211 iLine10 HomePNA 2.0 + V.90 56k modem"; +static const char pci_device_14e4_4212[] = "BCM4212 v.90 56k modem"; +static const char pci_device_14e4_4301[] = "BCM4303 802.11b Wireless LAN Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4301_1028_0407[] = "TrueMobile 1180 Onboard WLAN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4301_1043_0120[] = "WL-103b Wireless LAN PC Card"; +#endif +static const char pci_device_14e4_4305[] = "BCM4307 V.90 56k Modem"; +static const char pci_device_14e4_4306[] = "BCM4307 Ethernet Controller"; +static const char pci_device_14e4_4307[] = "BCM4307 802.11b Wireless LAN Controller"; +static const char pci_device_14e4_4310[] = "BCM4310 Chipcommon I/OController"; +static const char pci_device_14e4_4311[] = "Dell Wireless 1390 WLAN Mini-PCI Card"; +static const char pci_device_14e4_4312[] = "BCM4310 UART"; +static const char pci_device_14e4_4313[] = "BCM4310 Ethernet Controller"; +static const char pci_device_14e4_4315[] = "BCM4310 USB Controller"; +static const char pci_device_14e4_4318[] = "BCM4318 [AirForce One 54g] 802.11g Wireless LAN Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_103c_1356[] = "MX6125"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_1043_120f[] = "A6U notebook embedded card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_1468_0311[] = "Aspire 3022WLMi, 5024WLMi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_1468_0312[] = "TravelMate 2410"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_14e4_0449[] = "Gateway 7510GX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_14e4_4318[] = "WPC54G version 3 [Wireless-G Notebook Adapter] 802.11g Wireless Lan Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_16ec_0119[] = "U.S.Robotics Wireless MAXg PC Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4318_1737_0048[] = "WPC54G-EU version 3 [Wireless-G Notebook Adapter]"; +#endif +static const char pci_device_14e4_4319[] = "BCM4311 [AirForce 54g] 802.11a/b/g PCI Express Transceiver"; +static const char pci_device_14e4_4320[] = "BCM4306 802.11b/g Wireless LAN Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1028_0001[] = "TrueMobile 1300 WLAN Mini-PCI Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1028_0003[] = "Wireless 1350 WLAN Mini-PCI Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_103c_12f4[] = "NX9500 Built-in Wireless"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_103c_12fa[] = "Presario R3000 802.11b/g"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1043_100f[] = "WL-100G"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1057_7025[] = "WN825G"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_106b_004e[] = "AirPort Extreme"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1154_0330[] = "Buffalo WLI2-PCI-G54S High Speed Mode Wireless Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_144f_7050[] = "eMachines M6805 802.11g Built-in Wireless"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_14e4_4320[] = "Linksys WMP54G PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1737_4320[] = "WPC54G"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1799_7001[] = "Belkin F5D7001 High-Speed Mode Wireless G Network Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1799_7010[] = "Belkin F5D7010 54g Wireless Network card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_1799_7011[] = "F5D7011 54g+ Wireless Network card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4320_185f_1220[] = "TravelMate 290E WLAN Mini-PCI Card"; +#endif +static const char pci_device_14e4_4321[] = "BCM4306 802.11a Wireless LAN Controller"; +static const char pci_device_14e4_4322[] = "BCM4306 UART"; +static const char pci_device_14e4_4324[] = "BCM4309 802.11a/b/g"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4324_1028_0001[] = "Truemobile 1400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4324_1028_0003[] = "Truemobile 1450 MiniPCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14e4_4325[] = "BCM43xG 802.11b/g"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4325_1414_0003[] = "Wireless Notebook Adapter MN-720"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4325_1414_0004[] = "Wireless PCI Adapter MN-730"; +#endif +static const char pci_device_14e4_4326[] = "BCM4307 Chipcommon I/O Controller?"; +static const char pci_device_14e4_4329[] = "BCM43XG"; +static const char pci_device_14e4_4401[] = "BCM4401 100Base-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4401_103c_08b0[] = "tc1100 tablet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14e4_4401_1043_80a8[] = "A7V8X motherboard"; +#endif +static const char pci_device_14e4_4402[] = "BCM4402 Integrated 10/100BaseT"; +static const char pci_device_14e4_4403[] = "BCM4402 V.90 56k Modem"; +static const char pci_device_14e4_4410[] = "BCM4413 iLine32 HomePNA 2.0"; +static const char pci_device_14e4_4411[] = "BCM4413 V.90 56k modem"; +static const char pci_device_14e4_4412[] = "BCM4412 10/100BaseT"; +static const char pci_device_14e4_4430[] = "BCM44xx CardBus iLine32 HomePNA 2.0"; +static const char pci_device_14e4_4432[] = "BCM4432 CardBus 10/100BaseT"; +static const char pci_device_14e4_4610[] = "BCM4610 Sentry5 PCI to SB Bridge"; +static const char pci_device_14e4_4611[] = "BCM4610 Sentry5 iLine32 HomePNA 1.0"; +static const char pci_device_14e4_4612[] = "BCM4610 Sentry5 V.90 56k Modem"; +static const char pci_device_14e4_4613[] = "BCM4610 Sentry5 Ethernet Controller"; +static const char pci_device_14e4_4614[] = "BCM4610 Sentry5 External Interface"; +static const char pci_device_14e4_4615[] = "BCM4610 Sentry5 USB Controller"; +static const char pci_device_14e4_4704[] = "BCM4704 PCI to SB Bridge"; +static const char pci_device_14e4_4705[] = "BCM4704 Sentry5 802.11b Wireless LAN Controller"; +static const char pci_device_14e4_4706[] = "BCM4704 Sentry5 Ethernet Controller"; +static const char pci_device_14e4_4707[] = "BCM4704 Sentry5 USB Controller"; +static const char pci_device_14e4_4708[] = "BCM4704 Crypto Accelerator"; +static const char pci_device_14e4_4710[] = "BCM4710 Sentry5 PCI to SB Bridge"; +static const char pci_device_14e4_4711[] = "BCM47xx Sentry5 iLine32 HomePNA 2.0"; +static const char pci_device_14e4_4712[] = "BCM47xx V.92 56k modem"; +static const char pci_device_14e4_4713[] = "Sentry5 Ethernet Controller"; +static const char pci_device_14e4_4714[] = "BCM47xx Sentry5 External Interface"; +static const char pci_device_14e4_4715[] = "Sentry5 USB Controller"; +static const char pci_device_14e4_4716[] = "BCM47xx Sentry5 USB Host Controller"; +static const char pci_device_14e4_4717[] = "BCM47xx Sentry5 USB Device Controller"; +static const char pci_device_14e4_4718[] = "Sentry5 Crypto Accelerator"; +static const char pci_device_14e4_4719[] = "BCM47xx/53xx RoboSwitch Core"; +static const char pci_device_14e4_4720[] = "BCM4712 MIPS CPU"; +static const char pci_device_14e4_5365[] = "BCM5365P Sentry5 Host Bridge"; +static const char pci_device_14e4_5600[] = "BCM5600 StrataSwitch 24+2 Ethernet Switch Controller"; +static const char pci_device_14e4_5605[] = "BCM5605 StrataSwitch 24+2 Ethernet Switch Controller"; +static const char pci_device_14e4_5615[] = "BCM5615 StrataSwitch 24+2 Ethernet Switch Controller"; +static const char pci_device_14e4_5625[] = "BCM5625 StrataSwitch 24+2 Ethernet Switch Controller"; +static const char pci_device_14e4_5645[] = "BCM5645 StrataSwitch 24+2 Ethernet Switch Controller"; +static const char pci_device_14e4_5670[] = "BCM5670 8-Port 10GE Ethernet Switch Fabric"; +static const char pci_device_14e4_5680[] = "BCM5680 G-Switch 8 Port Gigabit Ethernet Switch Controller"; +static const char pci_device_14e4_5690[] = "BCM5690 12-port Multi-Layer Gigabit Ethernet Switch"; +static const char pci_device_14e4_5691[] = "BCM5691 GE/10GE 8+2 Gigabit Ethernet Switch Controller"; +static const char pci_device_14e4_5692[] = "BCM5692 12-port Multi-Layer Gigabit Ethernet Switch"; +static const char pci_device_14e4_5820[] = "BCM5820 Crypto Accelerator"; +static const char pci_device_14e4_5821[] = "BCM5821 Crypto Accelerator"; +static const char pci_device_14e4_5822[] = "BCM5822 Crypto Accelerator"; +static const char pci_device_14e4_5823[] = "BCM5823 Crypto Accelerator"; +static const char pci_device_14e4_5824[] = "BCM5824 Crypto Accelerator"; +static const char pci_device_14e4_5840[] = "BCM5840 Crypto Accelerator"; +static const char pci_device_14e4_5841[] = "BCM5841 Crypto Accelerator"; +static const char pci_device_14e4_5850[] = "BCM5850 Crypto Accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e5[] = "Pixelfusion Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e6[] = "SHINING Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e7[] = "3CX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e8[] = "RAYCER Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14e9[] = "GARNETS System CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ea[] = "Planex Communications, Inc"; +static const char pci_device_14ea_ab06[] = "FNW-3603-TX CardBus Fast Ethernet"; +static const char pci_device_14ea_ab07[] = "RTL81xx RealTek Ethernet"; +static const char pci_device_14ea_ab08[] = "FNW-3602-TX CardBus Fast Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14eb[] = "SEIKO EPSON Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ec[] = "ACQIRIS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ed[] = "DATAKINETICS Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ee[] = "MASPRO KENKOH Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ef[] = "CARRY Computer ENG. CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f0[] = "CANON RESEACH CENTRE FRANCE"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f1[] = "Conexant"; +static const char pci_device_14f1_1002[] = "HCF 56k Modem"; +static const char pci_device_14f1_1003[] = "HCF 56k Modem"; +static const char pci_device_14f1_1004[] = "HCF 56k Modem"; +static const char pci_device_14f1_1005[] = "HCF 56k Modem"; +static const char pci_device_14f1_1006[] = "HCF 56k Modem"; +static const char pci_device_14f1_1022[] = "HCF 56k Modem"; +static const char pci_device_14f1_1023[] = "HCF 56k Modem"; +static const char pci_device_14f1_1024[] = "HCF 56k Modem"; +static const char pci_device_14f1_1025[] = "HCF 56k Modem"; +static const char pci_device_14f1_1026[] = "HCF 56k Modem"; +static const char pci_device_14f1_1032[] = "HCF 56k Modem"; +static const char pci_device_14f1_1033[] = "HCF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_1033_8077[] = "NEC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_122d_4027[] = "Dell Zeus - MDP3880-W(B) Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_122d_4030[] = "Dell Mercury - MDP3880-U(B) Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_122d_4034[] = "Dell Thor - MDP3880-W(U) Data Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_020d[] = "Dell Copper"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_020e[] = "Dell Silver"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_0261[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_0290[] = "Compaq Goldwing"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_02a0[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_02b0[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_02c0[] = "Compaq Scooter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_13e0_02d0[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_1500[] = "IBM P85-DF (1)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_1501[] = "IBM P85-DF (2)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_150a[] = "IBM P85-DF (3)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_150b[] = "IBM P85-DF Low Profile (1)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1033_144f_1510[] = "IBM P85-DF Low Profile (2)"; +#endif +static const char pci_device_14f1_1034[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_1035[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1035_10cf_1098[] = "Fujitsu P85-DFSV"; +#endif +static const char pci_device_14f1_1036[] = "HCF 56k Data/Fax/Voice/Spkp Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_104d_8067[] = "HCF 56k Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_122d_4029[] = "MDP3880SP-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_122d_4031[] = "MDP3880SP-U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_13e0_0209[] = "Dell Titanium"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_13e0_020a[] = "Dell Graphite"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_13e0_0260[] = "Gateway Red Owl"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1036_13e0_0270[] = "Gateway White Horse"; +#endif +static const char pci_device_14f1_1052[] = "HCF 56k Data/Fax Modem (Worldwide)"; +static const char pci_device_14f1_1053[] = "HCF 56k Data/Fax Modem (Worldwide)"; +static const char pci_device_14f1_1054[] = "HCF 56k Data/Fax/Voice Modem (Worldwide)"; +static const char pci_device_14f1_1055[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem (Worldwide)"; +static const char pci_device_14f1_1056[] = "HCF 56k Data/Fax/Voice/Spkp Modem (Worldwide)"; +static const char pci_device_14f1_1057[] = "HCF 56k Data/Fax/Voice/Spkp Modem (Worldwide)"; +static const char pci_device_14f1_1059[] = "HCF 56k Data/Fax/Voice Modem (Worldwide)"; +static const char pci_device_14f1_1063[] = "HCF 56k Data/Fax Modem"; +static const char pci_device_14f1_1064[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_1065[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_1066[] = "HCF 56k Data/Fax/Voice/Spkp Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1066_122d_4033[] = "Dell Athena - MDP3900V-U"; +#endif +static const char pci_device_14f1_1085[] = "HCF V90 56k Data/Fax/Voice/Spkp PCI Modem"; +static const char pci_device_14f1_1433[] = "HCF 56k Data/Fax Modem"; +static const char pci_device_14f1_1434[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_1435[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_1436[] = "HCF 56k Data/Fax Modem"; +static const char pci_device_14f1_1453[] = "HCF 56k Data/Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1453_13e0_0240[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1453_13e0_0250[] = "IBM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1453_144f_1502[] = "IBM P95-DF (1)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1453_144f_1503[] = "IBM P95-DF (2)"; +#endif +static const char pci_device_14f1_1454[] = "HCF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_1455[] = "HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_1456[] = "HCF 56k Data/Fax/Voice/Spkp Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1456_122d_4035[] = "Dell Europa - MDP3900V-W"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1456_122d_4302[] = "Dell MP3930V-W(C) MiniPCI"; +#endif +static const char pci_device_14f1_1610[] = "ADSL AccessRunner PCI Arbitration Device"; +static const char pci_device_14f1_1611[] = "AccessRunner PCI ADSL Interface Device"; +static const char pci_device_14f1_1620[] = "AccessRunner V2 PCI ADSL Arbitration Device"; +static const char pci_device_14f1_1621[] = "AccessRunner V2 PCI ADSL Interface Device"; +static const char pci_device_14f1_1622[] = "AccessRunner V2 PCI ADSL Yukon WAN Adapter"; +static const char pci_device_14f1_1803[] = "HCF 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1803_0e11_0023[] = "623-LAN Grizzly"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1803_0e11_0043[] = "623-LAN Yogi"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14f1_1811[] = "Conextant MiniPCI Network Adapter"; +static const char pci_device_14f1_1815[] = "HCF 56k Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1815_0e11_0022[] = "Grizzly"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_1815_0e11_0042[] = "Yogi"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14f1_2003[] = "HSF 56k Data/Fax Modem"; +static const char pci_device_14f1_2004[] = "HSF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_2005[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_2006[] = "HSF 56k Data/Fax/Voice/Spkp Modem"; +static const char pci_device_14f1_2013[] = "HSF 56k Data/Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_0e11_b195[] = "Bear"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_0e11_b196[] = "Seminole 1"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_0e11_b1be[] = "Seminole 2"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_1025_8013[] = "Acer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_1033_809d[] = "NEC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_1033_80bc[] = "NEC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_155d_6793[] = "HP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2013_155d_8850[] = "E Machines"; +#endif +static const char pci_device_14f1_2014[] = "HSF 56k Data/Fax/Voice Modem"; +static const char pci_device_14f1_2015[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem"; +static const char pci_device_14f1_2016[] = "HSF 56k Data/Fax/Voice/Spkp Modem"; +static const char pci_device_14f1_2043[] = "HSF 56k Data/Fax Modem (WorldW SmartDAA)"; +static const char pci_device_14f1_2044[] = "HSF 56k Data/Fax/Voice Modem (WorldW SmartDAA)"; +static const char pci_device_14f1_2045[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem (WorldW SmartDAA)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2045_14f1_2045[] = "Generic SoftK56"; +#endif +static const char pci_device_14f1_2046[] = "HSF 56k Data/Fax/Voice/Spkp Modem (WorldW SmartDAA)"; +static const char pci_device_14f1_2063[] = "HSF 56k Data/Fax Modem (SmartDAA)"; +static const char pci_device_14f1_2064[] = "HSF 56k Data/Fax/Voice Modem (SmartDAA)"; +static const char pci_device_14f1_2065[] = "HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem (SmartDAA)"; +static const char pci_device_14f1_2066[] = "HSF 56k Data/Fax/Voice/Spkp Modem (SmartDAA)"; +static const char pci_device_14f1_2093[] = "HSF 56k Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2093_155d_2f07[] = "Legend"; +#endif +static const char pci_device_14f1_2143[] = "HSF 56k Data/Fax/Cell Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2144[] = "HSF 56k Data/Fax/Voice/Cell Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2145[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS)/Cell Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2146[] = "HSF 56k Data/Fax/Voice/Spkp/Cell Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2163[] = "HSF 56k Data/Fax/Cell Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2164[] = "HSF 56k Data/Fax/Voice/Cell Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2165[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS)/Cell Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2166[] = "HSF 56k Data/Fax/Voice/Spkp/Cell Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2343[] = "HSF 56k Data/Fax CardBus Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2344[] = "HSF 56k Data/Fax/Voice CardBus Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2345[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS) CardBus Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2346[] = "HSF 56k Data/Fax/Voice/Spkp CardBus Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2363[] = "HSF 56k Data/Fax CardBus Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2364[] = "HSF 56k Data/Fax/Voice CardBus Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2365[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS) CardBus Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2366[] = "HSF 56k Data/Fax/Voice/Spkp CardBus Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2443[] = "HSF 56k Data/Fax Modem (Mob WorldW SmartDAA)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2443_104d_8075[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2443_104d_8083[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2443_104d_8097[] = "Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_14f1_2444[] = "HSF 56k Data/Fax/Voice Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2445[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS) Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2446[] = "HSF 56k Data/Fax/Voice/Spkp Modem (Mob WorldW SmartDAA)"; +static const char pci_device_14f1_2463[] = "HSF 56k Data/Fax Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2464[] = "HSF 56k Data/Fax/Voice Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2465[] = "HSF 56k Data/Fax/Voice/Spkp (w/HS) Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2466[] = "HSF 56k Data/Fax/Voice/Spkp Modem (Mob SmartDAA)"; +static const char pci_device_14f1_2bfa[] = "HDAudio Soft Data Fax Modem with SmartCP"; +static const char pci_device_14f1_2f00[] = "HSF 56k HSFi Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2f00_13e0_8d84[] = "IBM HSFi V.90"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2f00_13e0_8d85[] = "Compaq Stinger"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_2f00_14f1_2004[] = "Dynalink 56PMi"; +#endif +static const char pci_device_14f1_2f02[] = "HSF 56k HSFi Data/Fax"; +static const char pci_device_14f1_2f11[] = "HSF 56k HSFi Modem"; +static const char pci_device_14f1_2f20[] = "HSF 56k Data/Fax Modem"; +static const char pci_device_14f1_8234[] = "RS8234 ATM SAR Controller [ServiceSAR Plus]"; +static const char pci_device_14f1_8800[] = "CX23880/1/2/3 PCI Video and Audio Decoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_0070_2801[] = "Hauppauge WinTV 28xxx (Roslyn) models"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_0070_3401[] = "Hauppauge WinTV 34xxx models"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_0070_9001[] = "Nova-T DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_0070_9200[] = "Nova-SE2 DVB-S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_0070_9202[] = "Nova-S-Plus DVB-S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_0070_9402[] = "WinTV-HVR1100 DVB-T/Hybrid"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_0070_9802[] = "WinTV-HVR1100 DVB-T/Hybrid (Low Profile)"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1002_00f8[] = "ATI TV Wonder Pro"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1002_a101[] = "HDTV Wonder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1043_4823[] = "ASUS PVR-416"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_107d_6613[] = "Leadtek Winfast 2000XP Expert"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_107d_6620[] = "Leadtek Winfast DV2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_107d_663c[] = "Leadtek PVR 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_107d_665f[] = "WinFast DTV1000-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_10fc_d003[] = "IODATA GV-VCP3/PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_10fc_d035[] = "IODATA GV/BCTV7E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1421_0334[] = "Instant TV DVB-T PCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1461_000a[] = "AVerTV 303 (M126)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1461_000b[] = "AverTV Studio 303 (M126)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1461_8011[] = "UltraTV Media Center PCI 550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1462_8606[] = "MSI TV-@nywhere Master"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_14c7_0107[] = "GDI Black Gold"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_14f1_0187[] = "Conexant DVB-T reference design"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_14f1_0342[] = "Digital-Logic MICROSPACE Entertainment Center (MEC)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_153b_1166[] = "Cinergy 1400 DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1540_2580[] = "Provideo PV259"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1554_4811[] = "PixelView"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1554_4813[] = "Club 3D ZAP1000 MCE Edition"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_17de_08a1[] = "KWorld/VStream XPert DVB-T with cx22702"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_17de_08a6[] = "KWorld/VStream XPert DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_17de_08b2[] = "KWorld DVB-S 100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_17de_a8a6[] = "digitalnow DNTV Live! DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_1822_0025[] = "digitalnow DNTV Live! DVB-T Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_18ac_d500[] = "FusionHDTV 5 Gold"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_18ac_d810[] = "FusionHDTV 3 Gold-Q"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_18ac_d820[] = "FusionHDTV 3 Gold-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_18ac_db00[] = "FusionHDTV DVB-T1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_18ac_db11[] = "FusionHDTV DVB-T Plus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_18ac_db50[] = "FusionHDTV DVB-T Dual Digital"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8800_7063_3000[] = "pcHDTV HD3000 HDTV"; +#endif +static const char pci_device_14f1_8801[] = "CX23880/1/2/3 PCI Video and Audio Decoder [Audio Port]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8801_0070_2801[] = "Hauppauge WinTV 28xxx (Roslyn) models"; +#endif +static const char pci_device_14f1_8802[] = "CX23880/1/2/3 PCI Video and Audio Decoder [MPEG Port]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_0070_2801[] = "Hauppauge WinTV 28xxx (Roslyn) models"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_0070_9002[] = "Nova-T DVB-T Model 909"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_1043_4823[] = "ASUS PVR-416"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_107d_663c[] = "Leadtek PVR 2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_14f1_0187[] = "Conexant DVB-T reference design"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_17de_08a1[] = "XPert DVB-T PCI BDA DVBT 23880 Transport Stream Capture"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_17de_08a6[] = "KWorld/VStream XPert DVB-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_18ac_d500[] = "DViCO FusionHDTV5 Gold"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_18ac_d810[] = "DViCO FusionHDTV3 Gold-Q"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_18ac_d820[] = "DViCO FusionHDTV3 Gold-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_18ac_db00[] = "DVICO FusionHDTV DVB-T1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_18ac_db10[] = "DVICO FusionHDTV DVB-T Plus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8802_7063_3000[] = "pcHDTV HD3000 HDTV"; +#endif +static const char pci_device_14f1_8804[] = "CX23880/1/2/3 PCI Video and Audio Decoder [IR Port]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8804_0070_9002[] = "Nova-T DVB-T Model 909"; +#endif +static const char pci_device_14f1_8811[] = "CX23880/1/2/3 PCI Video and Audio Decoder [Audio Port]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_0070_3401[] = "Hauppauge WinTV 34xxx models"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_1462_8606[] = "MSI TV-@nywhere Master"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_18ac_d500[] = "DViCO FusionHDTV5 Gold"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_18ac_d810[] = "DViCO FusionHDTV3 Gold-Q"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_18ac_d820[] = "DViCO FusionHDTV3 Gold-T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_14f1_8811_18ac_db00[] = "DVICO FusionHDTV DVB-T1"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f2[] = "MOBILITY Electronics"; +static const char pci_device_14f2_0120[] = "EV1000 bridge"; +static const char pci_device_14f2_0121[] = "EV1000 Parallel port"; +static const char pci_device_14f2_0122[] = "EV1000 Serial port"; +static const char pci_device_14f2_0123[] = "EV1000 Keyboard controller"; +static const char pci_device_14f2_0124[] = "EV1000 Mouse controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f3[] = "BroadLogic"; +static const char pci_device_14f3_2030[] = "2030 DVB-S Satellite Reciever"; +static const char pci_device_14f3_2050[] = "2050 DVB-T Terrestrial (Cable) Reciever"; +static const char pci_device_14f3_2060[] = "2060 ATSC Terrestrial (Cable) Reciever"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f4[] = "TOKYO Electronic Industry CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f5[] = "SOPAC Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f6[] = "COYOTE Technologies LLC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f7[] = "WOLF Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f8[] = "AUDIOCODES Inc"; +static const char pci_device_14f8_2077[] = "TP-240 dual span E1 VoIP PCI card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14f9[] = "AG COMMUNICATIONS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fa[] = "WANDEL & GOLTERMANN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fb[] = "TRANSAS MARINE (UK) Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fc[] = "Quadrics Ltd"; +static const char pci_device_14fc_0000[] = "QsNet Elan3 Network Adapter"; +static const char pci_device_14fc_0001[] = "QsNetII Elan4 Network Adapter"; +static const char pci_device_14fc_0002[] = "QsNetIII Elan5 Network Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fd[] = "JAPAN Computer Industry Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14fe[] = "ARCHTEK TELECOM Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_14ff[] = "TWINHEAD INTERNATIONAL Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1500[] = "DELTA Electronics, Inc"; +static const char pci_device_1500_1360[] = "RTL81xx RealTek Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1501[] = "BANKSOFT CANADA Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1502[] = "MITSUBISHI ELECTRIC LOGISTICS SUPPORT Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1503[] = "KAWASAKI LSI USA Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1504[] = "KAISER Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1505[] = "ITA INGENIEURBURO FUR TESTAUFGABEN GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1506[] = "CHAMELEON Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1507[] = "Motorola ? / HTEC"; +static const char pci_device_1507_0001[] = "MPC105 [Eagle]"; +static const char pci_device_1507_0002[] = "MPC106 [Grackle]"; +static const char pci_device_1507_0003[] = "MPC8240 [Kahlua]"; +static const char pci_device_1507_0100[] = "MC145575 [HFC-PCI]"; +static const char pci_device_1507_0431[] = "KTI829c 100VG"; +static const char pci_device_1507_4801[] = "Raven"; +static const char pci_device_1507_4802[] = "Falcon"; +static const char pci_device_1507_4803[] = "Hawk"; +static const char pci_device_1507_4806[] = "CPX8216"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1508[] = "HONDA CONNECTORS/MHOTRONICS Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1509[] = "FIRST INTERNATIONAL Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150a[] = "FORVUS RESEARCH Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150b[] = "YAMASHITA Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150c[] = "KYOPAL CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150d[] = "WARPSPPED Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150e[] = "C-PORT Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_150f[] = "INTEC GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1510[] = "BEHAVIOR TECH Computer Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1511[] = "CENTILLIUM Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1512[] = "ROSUN Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1513[] = "Raychem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1514[] = "TFL LAN Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1515[] = "Advent design"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1516[] = "MYSON Technology Inc"; +static const char pci_device_1516_0800[] = "MTD-8xx 100/10M Ethernet PCI Adapter"; +static const char pci_device_1516_0803[] = "SURECOM EP-320X-S 100/10M Ethernet PCI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1516_0803_1320_10bd[] = "SURECOM EP-320X-S 100/10M Ethernet PCI Adapter"; +#endif +static const char pci_device_1516_0891[] = "MTD-8xx 100/10M Ethernet PCI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1517[] = "ECHOTEK Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1518[] = "PEP MODULAR Computers GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1519[] = "TELEFON AKTIEBOLAGET LM Ericsson"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151a[] = "Globetek"; +static const char pci_device_151a_1002[] = "PCI-1002"; +static const char pci_device_151a_1004[] = "PCI-1004"; +static const char pci_device_151a_1008[] = "PCI-1008"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151b[] = "COMBOX Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151c[] = "DIGITAL AUDIO LABS Inc"; +static const char pci_device_151c_0003[] = "Prodif T 2496"; +static const char pci_device_151c_4000[] = "Prodif 88"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151d[] = "Fujitsu Computer Products Of America"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151e[] = "MATRIX Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_151f[] = "TOPIC SEMICONDUCTOR Corp"; +static const char pci_device_151f_0000[] = "TP560 Data/Fax/Voice 56k modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1520[] = "CHAPLET System Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1521[] = "BELL Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1522[] = "MainPine Ltd"; +static const char pci_device_1522_0100[] = "PCI <-> IOBus Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0200[] = "RockForceDUO 2 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0300[] = "RockForceQUATRO 4 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0400[] = "RockForceDUO+ 2 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0500[] = "RockForceQUATRO+ 4 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0600[] = "RockForce+ 2 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0700[] = "RockForce+ 4 Port V.90 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0800[] = "RockForceOCTO+ 8 Port V.92/V.44 Data/Fax/Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0c00[] = "RockForceDUO+ 2 Port V.92/V.44 Data, V.34 Super-G3 Fax, Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_0d00[] = "RockForceQUATRO+ 4 Port V.92/V.44 Data, V.34 Super-G3 Fax, Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_1d00[] = "RockForceOCTO+ 8 Port V.92/V.44 Data, V.34 Super-G3 Fax, Voice Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2000[] = "RockForceD1 1 Port V.90 Data Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2100[] = "RockForceF1 1 Port V.34 Super-G3 Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2200[] = "RockForceD2 2 Port V.90 Data Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2300[] = "RockForceF2 2 Port V.34 Super-G3 Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2400[] = "RockForceD4 4 Port V.90 Data Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2500[] = "RockForceF4 4 Port V.34 Super-G3 Fax Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2600[] = "RockForceD8 8 Port V.90 Data Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1522_0100_1522_2700[] = "RockForceF8 8 Port V.34 Super-G3 Fax Modem"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1523[] = "MUSIC Semiconductors"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1524[] = "ENE Technology Inc"; +static const char pci_device_1524_0510[] = "CB710 Memory Card Reader Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1524_0510_103c_006a[] = "NX9500"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1524_0520[] = "FLASH memory: ENE Technology Inc:"; +static const char pci_device_1524_0530[] = "ENE PCI Memory Stick Card Reader Controller"; +static const char pci_device_1524_0550[] = "ENE PCI Secure Digital Card Reader Controller"; +static const char pci_device_1524_0610[] = "PCI Smart Card Reader Controller"; +static const char pci_device_1524_1211[] = "CB1211 Cardbus Controller"; +static const char pci_device_1524_1225[] = "CB1225 Cardbus Controller"; +static const char pci_device_1524_1410[] = "CB1410 Cardbus Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1524_1410_1025_003c[] = "CL50 motherboard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1524_1410_1025_005a[] = "TravelMate 290"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1524_1411[] = "CB-710/2/4 Cardbus Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1524_1411_103c_006a[] = "NX9500"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_1524_1412[] = "CB-712/4 Cardbus Controller"; +static const char pci_device_1524_1420[] = "CB1420 Cardbus Controller"; +static const char pci_device_1524_1421[] = "CB-720/2/4 Cardbus Controller"; +static const char pci_device_1524_1422[] = "CB-722/4 Cardbus Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1525[] = "IMPACT Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1526[] = "ISS, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1527[] = "SOLECTRON"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1528[] = "ACKSYS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1529[] = "AMERICAN MICROSystems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152a[] = "QUICKTURN DESIGN Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152b[] = "FLYTECH Technology CO Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152c[] = "MACRAIGOR Systems LLC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152d[] = "QUANTA Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152e[] = "MELEC Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_152f[] = "PHILIPS - CRYPTO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1530[] = "ACQIS Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1531[] = "CHRYON Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1532[] = "ECHELON Corp"; +static const char pci_device_1532_0020[] = "LonWorks PCLTA-20 PCI LonTalk Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1533[] = "BALTIMORE"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1534[] = "ROAD Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1535[] = "EVERGREEN Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1537[] = "DATALEX COMMUNCATIONS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1538[] = "ARALION Inc"; +static const char pci_device_1538_0303[] = "ARS106S Ultra ATA 133/100/66 Host Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1539[] = "ATELIER INFORMATIQUES et ELECTRONIQUE ETUDES S.A."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153a[] = "ONO SOKKI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153b[] = "TERRATEC Electronic GmbH"; +static const char pci_device_153b_1144[] = "Aureon 5.1"; +static const char pci_device_153b_1147[] = "Aureon 5.1 Sky"; +static const char pci_device_153b_1158[] = "Philips Semiconductors SAA7134 (rev 01) [Terratec Cinergy 600 TV]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153c[] = "ANTAL Electronic"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153d[] = "FILANET Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153e[] = "TECHWELL Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_153f[] = "MIPS Technologies, Inc."; +static const char pci_device_153f_0001[] = "SOC-it 101 System Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1540[] = "PROVIDEO MULTIMEDIA Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1541[] = "MACHONE Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1542[] = "Concurrent Computer Corporation"; +static const char pci_device_1542_9260[] = "RCIM-II Real-Time Clock & Interrupt Module"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1543[] = "SILICON Laboratories"; +static const char pci_device_1543_3052[] = "Intel 537 [Winmodem]"; +static const char pci_device_1543_4c22[] = "Si3036 MC'97 DAA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1544[] = "DCM DATA Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1545[] = "VISIONTEK"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1546[] = "IOI Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1547[] = "MITUTOYO Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1548[] = "JET PROPULSION Laboratory"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1549[] = "INTERCONNECT Systems Solutions"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154a[] = "MAX Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154b[] = "COMPUTEX Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154c[] = "VISUAL Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154d[] = "PAN INTERNATIONAL Industrial Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154e[] = "SERVOTEST Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_154f[] = "STRATABEAM Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1550[] = "OPEN NETWORK Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1551[] = "SMART Electronic DEVELOPMENT GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1552[] = "RACAL AIRTECH Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1553[] = "CHICONY Electronics Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1554[] = "PROLINK Microsystems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1555[] = "GESYTEC GmBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1556[] = "PLD APPLICATIONS"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1557[] = "MEDIASTAR Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1558[] = "CLEVO/KAPOK Computer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1559[] = "SI LOGIC Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155a[] = "INNOMEDIA Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155b[] = "PROTAC INTERNATIONAL Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155c[] = "Cemax-Icon Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155d[] = "Mac System Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155e[] = "LP Elektronik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_155f[] = "Perle Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1560[] = "Terayon Communications Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1561[] = "Viewgraphics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1562[] = "Symbol Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1563[] = "A-Trend Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1564[] = "Yamakatsu Electronics Industry Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1565[] = "Biostar Microtech Int'l Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1566[] = "Ardent Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1567[] = "Jungsoft"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1568[] = "DDK Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1569[] = "Palit Microsystems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156a[] = "Avtec Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156b[] = "2wire Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156c[] = "Vidac Electronics GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156d[] = "Alpha-Top Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156e[] = "Alfa Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_156f[] = "M-Systems Flash Disk Pioneers Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1570[] = "Lecroy Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1571[] = "Contemporary Controls"; +static const char pci_device_1571_a001[] = "CCSI PCI20-485 ARCnet"; +static const char pci_device_1571_a002[] = "CCSI PCI20-485D ARCnet"; +static const char pci_device_1571_a003[] = "CCSI PCI20-485X ARCnet"; +static const char pci_device_1571_a004[] = "CCSI PCI20-CXB ARCnet"; +static const char pci_device_1571_a005[] = "CCSI PCI20-CXS ARCnet"; +static const char pci_device_1571_a006[] = "CCSI PCI20-FOG-SMA ARCnet"; +static const char pci_device_1571_a007[] = "CCSI PCI20-FOG-ST ARCnet"; +static const char pci_device_1571_a008[] = "CCSI PCI20-TB5 ARCnet"; +static const char pci_device_1571_a009[] = "CCSI PCI20-5-485 5Mbit ARCnet"; +static const char pci_device_1571_a00a[] = "CCSI PCI20-5-485D 5Mbit ARCnet"; +static const char pci_device_1571_a00b[] = "CCSI PCI20-5-485X 5Mbit ARCnet"; +static const char pci_device_1571_a00c[] = "CCSI PCI20-5-FOG-ST 5Mbit ARCnet"; +static const char pci_device_1571_a00d[] = "CCSI PCI20-5-FOG-SMA 5Mbit ARCnet"; +static const char pci_device_1571_a201[] = "CCSI PCI22-485 10Mbit ARCnet"; +static const char pci_device_1571_a202[] = "CCSI PCI22-485D 10Mbit ARCnet"; +static const char pci_device_1571_a203[] = "CCSI PCI22-485X 10Mbit ARCnet"; +static const char pci_device_1571_a204[] = "CCSI PCI22-CHB 10Mbit ARCnet"; +static const char pci_device_1571_a205[] = "CCSI PCI22-FOG_ST 10Mbit ARCnet"; +static const char pci_device_1571_a206[] = "CCSI PCI22-THB 10Mbit ARCnet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1572[] = "Otis Elevator Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1573[] = "Lattice - Vantis"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1574[] = "Fairchild Semiconductor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1575[] = "Voltaire Advanced Data Security Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1576[] = "Viewcast COM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1578[] = "HITT"; +static const char pci_device_1578_5615[] = "VPMK3 [Video Processor Mk III]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1579[] = "Dual Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157a[] = "Japan Elecronics Ind Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157b[] = "Star Multimedia Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157c[] = "Eurosoft (UK)"; +static const char pci_device_157c_8001[] = "Fix2000 PCI Y2K Compliance Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157d[] = "Gemflex Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157e[] = "Transition Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_157f[] = "PX Instruments Technology Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1580[] = "Primex Aerospace Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1581[] = "SEH Computertechnik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1582[] = "Cytec Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1583[] = "Inet Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1584[] = "Uniwill Computer Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1585[] = "Logitron"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1586[] = "Lancast Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1587[] = "Konica Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1588[] = "Solidum Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1589[] = "Atlantek Microsystems Pty Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158a[] = "Digalog Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158b[] = "Allied Data Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158c[] = "Hitachi Semiconductor & Devices Sales Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158d[] = "Point Multimedia Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158e[] = "Lara Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_158f[] = "Ditect Coop"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1590[] = "3pardata Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1591[] = "ARN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1592[] = "Syba Tech Ltd"; +static const char pci_device_1592_0781[] = "Multi-IO Card"; +static const char pci_device_1592_0782[] = "Parallel Port Card 2xEPP"; +static const char pci_device_1592_0783[] = "Multi-IO Card"; +static const char pci_device_1592_0785[] = "Multi-IO Card"; +static const char pci_device_1592_0786[] = "Multi-IO Card"; +static const char pci_device_1592_0787[] = "Multi-IO Card"; +static const char pci_device_1592_0788[] = "Multi-IO Card"; +static const char pci_device_1592_078a[] = "Multi-IO Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1593[] = "Bops Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1594[] = "Netgame Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1595[] = "Diva Systems Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1596[] = "Folsom Research Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1597[] = "Memec Design Services"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1598[] = "Granite Microsystems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1599[] = "Delta Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159a[] = "General Instrument"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159b[] = "Faraday Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159c[] = "Stratus Computer Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159d[] = "Ningbo Harrison Electronics Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159e[] = "A-Max Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_159f[] = "Galea Network Security"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a0[] = "Compumaster SRL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a1[] = "Geocast Network Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a2[] = "Catalyst Enterprises Inc"; +static const char pci_device_15a2_0001[] = "TA700 PCI Bus Analyzer/Exerciser"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a3[] = "Italtel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a4[] = "X-Net OY"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a5[] = "Toyota Macs Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a6[] = "Sunlight Ultrasound Technologies Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a7[] = "SSE Telecom Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15a8[] = "Shanghai Communications Technologies Center"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15aa[] = "Moreton Bay"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ab[] = "Bluesteel Networks Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ac[] = "North Atlantic Instruments"; +#endif +static const char pci_vendor_15ad[] = "VMware Inc"; +static const char pci_device_15ad_0405[] = "[VMware SVGA II] PCI Display Adapter"; +static const char pci_device_15ad_0710[] = "Virtual SVGA"; +static const char pci_device_15ad_0720[] = "VMware High-Speed Virtual NIC [vmxnet]"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ae[] = "Amersham Pharmacia Biotech"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b0[] = "Zoltrix International Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b1[] = "Source Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b2[] = "Mosaid Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b3[] = "Mellanox Technologies"; +static const char pci_device_15b3_5274[] = "MT21108 InfiniBridge"; +static const char pci_device_15b3_5a44[] = "MT23108 InfiniHost"; +static const char pci_device_15b3_5a45[] = "MT23108 [Infinihost HCA Flash Recovery]"; +static const char pci_device_15b3_5a46[] = "MT23108 PCI Bridge"; +static const char pci_device_15b3_5e8d[] = "MT25204 [InfiniHost III Lx HCA Flash Recovery]"; +static const char pci_device_15b3_6274[] = "MT25204 [InfiniHost III Lx HCA]"; +static const char pci_device_15b3_6278[] = "MT25208 InfiniHost III Ex (Tavor compatibility mode)"; +static const char pci_device_15b3_6279[] = "MT25208 [InfiniHost III Ex HCA Flash Recovery]"; +static const char pci_device_15b3_6282[] = "MT25208 InfiniHost III Ex"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b4[] = "CCI/TRIAD"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b5[] = "Cimetrics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b6[] = "Texas Memory Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b7[] = "Sandisk Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b8[] = "ADDI-DATA GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15b9[] = "Maestro Digital Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ba[] = "Impacct Technology Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15bb[] = "Portwell Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15bc[] = "Agilent Technologies"; +static const char pci_device_15bc_1100[] = "E8001-66442 PCI Express CIC"; +static const char pci_device_15bc_2922[] = "64 Bit, 133MHz PCI-X Exerciser & Protocol Checker"; +static const char pci_device_15bc_2928[] = "64 Bit, 66MHz PCI Exerciser & Analyzer"; +static const char pci_device_15bc_2929[] = "64 Bit, 133MHz PCI-X Analyzer & Exerciser"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15bd[] = "DFI Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15be[] = "Sola Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15bf[] = "High Tech Computer Corp (HTC)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c0[] = "BVM Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c1[] = "Quantel"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c2[] = "Newer Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c3[] = "Taiwan Mycomp Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c4[] = "EVSX Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c5[] = "Procomp Informatics Ltd"; +static const char pci_device_15c5_8010[] = "1394b - 1394 Firewire 3-Port Host Adapter Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c6[] = "Technical University of Budapest"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c7[] = "Tateyama System Laboratory Co Ltd"; +static const char pci_device_15c7_0349[] = "Tateyama C-PCI PLC/NC card Rev.01A"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c8[] = "Penta Media Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15c9[] = "Serome Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ca[] = "Bitboys OY"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15cb[] = "AG Electronics Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15cc[] = "Hotrail Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15cd[] = "Dreamtech Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ce[] = "Genrad Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15cf[] = "Hilscher GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d1[] = "Infineon Technologies AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d2[] = "FIC (First International Computer Inc)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d3[] = "NDS Technologies Israel Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d4[] = "Iwill Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d5[] = "Tatung Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d6[] = "Entridia Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d7[] = "Rockwell-Collins Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d8[] = "Cybernetics Technology Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15d9[] = "Super Micro Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15da[] = "Cyberfirm Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15db[] = "Applied Computing Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15dc[] = "Litronic Inc"; +static const char pci_device_15dc_0001[] = "Argus 300 PCI Cryptography Module"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15dd[] = "Sigmatel Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15de[] = "Malleable Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15df[] = "Infinilink Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e0[] = "Cacheflow Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e1[] = "Voice Technologies Group Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e2[] = "Quicknet Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e3[] = "Networth Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e4[] = "VSN Systemen BV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e5[] = "Valley technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e6[] = "Agere Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e7[] = "Get Engineering Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e8[] = "National Datacomm Corp"; +static const char pci_device_15e8_0130[] = "Wireless PCI Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15e9[] = "Pacific Digital Corp"; +static const char pci_device_15e9_1841[] = "ADMA-100 DiscStaQ ATA Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ea[] = "Tokyo Denshi Sekei K.K."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15eb[] = "Drsearch GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ec[] = "Beckhoff GmbH"; +static const char pci_device_15ec_3101[] = "FC3101 Profibus DP 1 Channel PCI"; +static const char pci_device_15ec_5102[] = "FC5102"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ed[] = "Macrolink Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ee[] = "In Win Development Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ef[] = "Intelligent Paradigm Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f0[] = "B-Tree Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f1[] = "Times N Systems Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f2[] = "Diagnostic Instruments Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f3[] = "Digitmedia Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f4[] = "Valuesoft"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f5[] = "Power Micro Research"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f6[] = "Extreme Packet Device Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f7[] = "Banctec"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f8[] = "Koga Electronics Co"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15f9[] = "Zenith Electronics Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fa[] = "J.P. Axzam Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fb[] = "Zilog Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fc[] = "Techsan Electronics Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fd[] = "N-CUBED.NET"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15fe[] = "Kinpo Electronics Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_15ff[] = "Fastpoint Technologies Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1600[] = "Northrop Grumman - Canada Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1601[] = "Tenta Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1602[] = "Prosys-tec Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1603[] = "Nokia Wireless Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1604[] = "Central System Research Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1605[] = "Pairgain Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1606[] = "Europop AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1607[] = "Lava Semiconductor Manufacturing Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1608[] = "Automated Wagering International"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1609[] = "Scimetric Instruments Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1612[] = "Telesynergy Research Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1619[] = "FarSite Communications Ltd"; +static const char pci_device_1619_0400[] = "FarSync T2P (2 port X.21/V.35/V.24)"; +static const char pci_device_1619_0440[] = "FarSync T4P (4 port X.21/V.35/V.24)"; +static const char pci_device_1619_0610[] = "FarSync T1U (1 port X.21/V.35/V.24)"; +static const char pci_device_1619_0620[] = "FarSync T2U (2 port X.21/V.35/V.24)"; +static const char pci_device_1619_0640[] = "FarSync T4U (4 port X.21/V.35/V.24)"; +static const char pci_device_1619_1610[] = "FarSync TE1 (T1,E1)"; +static const char pci_device_1619_2610[] = "FarSync DSL-S1 (SHDSL)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_161f[] = "Rioworks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1626[] = "TDK Semiconductor Corp."; +static const char pci_device_1626_8410[] = "RTL81xx Fast Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1629[] = "Kongsberg Spacetec AS"; +static const char pci_device_1629_1003[] = "Format synchronizer v3.0"; +static const char pci_device_1629_2002[] = "Fast Universal Data Output"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1637[] = "Linksys"; +static const char pci_device_1637_3874[] = "Linksys 802.11b WMP11 PCI Wireless card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1638[] = "Standard Microsystems Corp [SMC]"; +static const char pci_device_1638_1100[] = "SMC2602W EZConnect / Addtron AWA-100 / Eumitcom PCI WL11000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_163c[] = "Smart Link Ltd."; +static const char pci_device_163c_3052[] = "SmartLink SmartPCI562 56K Modem"; +static const char pci_device_163c_5449[] = "SmartPCI561 Modem"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1657[] = "Brocade Communications Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_165a[] = "Epix Inc"; +static const char pci_device_165a_c100[] = "PIXCI(R) CL1 Camera Link Video Capture Board [custom QL5232]"; +static const char pci_device_165a_d200[] = "PIXCI(R) D2X Digital Video Capture Board [custom QL5232]"; +static const char pci_device_165a_d300[] = "PIXCI(R) D3X Digital Video Capture Board [custom QL5232]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_165d[] = "Hsing Tech. Enterprise Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_165f[] = "Linux Media Labs, LLC"; +static const char pci_device_165f_1020[] = "LMLM4 MPEG-4 encoder"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1661[] = "Worldspace Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1668[] = "Actiontec Electronics Inc"; +static const char pci_device_1668_0100[] = "Mini-PCI bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_166d[] = "Broadcom Corporation"; +static const char pci_device_166d_0001[] = "SiByte BCM1125/1125H/1250 System-on-a-Chip PCI"; +static const char pci_device_166d_0002[] = "SiByte BCM1125H/1250 System-on-a-Chip HyperTransport"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1677[] = "Bernecker + Rainer"; +static const char pci_device_1677_104e[] = "5LS172.6 B&R Dual CAN Interface Card"; +static const char pci_device_1677_12d7[] = "5LS172.61 B&R Dual CAN Interface Card"; +static const char pci_device_1677_20ad[] = "5ACPCI.MFIO-K01 Profibus DP / K-Feldbus / COM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_167b[] = "ZyDAS Technology Corp."; +static const char pci_device_167b_2102[] = "ZyDAS ZD1202"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_167b_2102_187e_3406[] = "ZyAIR B-122 CardBus 11Mbs Wireless LAN Card"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_167d[] = "Samsung Electro-Mechanics Co., Ltd."; +static const char pci_device_167d_a000[] = "IPW2200 miniPCI Wireless"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1681[] = "Hercules"; +static const char pci_device_1681_0010[] = "Hercules 3d Prophet II Ultra 64MB (350 MHz NV15BR core)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1682[] = "XFX Pine Group Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1688[] = "CastleNet Technology Inc."; +static const char pci_device_1688_1170[] = "WLAN 802.11b card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_168c[] = "Atheros Communications, Inc."; +static const char pci_device_168c_0007[] = "AR5000 802.11a Wireless Adapter"; +static const char pci_device_168c_0011[] = "AR5210 802.11a NIC"; +static const char pci_device_168c_0012[] = "AR5211 802.11ab NIC"; +static const char pci_device_168c_0013[] = "AR5212 802.11abg NIC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1113_d301[] = "Philips CPWNA100 Wireless CardBus adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3202[] = "D-link DWL-G650 (Rev B3,B5) Wireless cardbus adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3203[] = "DWL-G520 Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a12[] = "D-Link AirPlus DWL-G650 Wireless Cardbus Adapter(rev.C)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a13[] = "D-Link AirPlus DWL-G520 Wireless PCI Adapter(rev.B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a14[] = "D-Link AirPremier DWL-AG530 Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a17[] = "D-Link AirPremier DWL-G680 Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a18[] = "D-Link AirPremier DWL-G550 Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a63[] = "D-Link AirPremier DWL-AG660 Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a93[] = "Conceptronic C54I Wireless 801.11g PCI card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3a94[] = "C54C Wireless 801.11g cardbus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1186_3ab0[] = "Allnet ALL0281 Wireless PCI Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1385_4d00[] = "Netgear WG311T Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1458_e911[] = "Gigabyte GN-WIAG02"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_14b7_0a60[] = "8482-WD ORiNOCO 11a/b/g Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_1668_1026[] = "IBM HighRate 11 a/b/g Wireless CardBus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_0013[] = "AirPlus XtremeG DWL-G650 Wireless PCMCIA Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_1025[] = "DWL-G650B2 Wireless CardBus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_1027[] = "Engenius NL-3054CB ARIES b/g CardBus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_1042[] = "Ubiquiti Networks SuperRange a/b/g Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_2026[] = "Netgate 5354MP ARIES a(108Mb turbo)/b/g MiniPCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_2041[] = "Engenius 5354MP Plus ARIES2 b/g MiniPCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_2042[] = "Engenius 5354MP Plus ARIES2 a/b/g MiniPCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_168c_2051[] = "TRENDnet TEW-443PI Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_16ab_7302[] = "Trust Speedshare Turbo Pro Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_0013_185f_2012[] = "Wistron NeWeb WLAN a+b+g model CB9"; +#endif +static const char pci_device_168c_001a[] = "AR5005G 802.11abg NIC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001a_1113_ee20[] = "SMC Wireless CardBus Adapter 802.11g (SMCWCB-G EU)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001a_1113_ee24[] = "SMC Wireless PCI Card WPCI-G"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001a_1186_3a15[] = "D-Link AirPlus G DWL-G630 Wireless Cardbus Adapter(rev.D)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001a_1186_3a16[] = "D-Link AirPlus G DWL-G510 Wireless PCI Adapter(rev.B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001a_1186_3a23[] = "D-Link AirPlus G DWL-G520+A Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001a_1186_3a24[] = "D-Link AirPlus G DWL-G650+A Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001a_168c_001a[] = "Belkin FD7000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001a_168c_1052[] = "TP-Link TL-WN510G Wireless CardBus Adapter"; +#endif +static const char pci_device_168c_001b[] = "AR5006X 802.11abg NIC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001b_1186_3a19[] = "D-Link AirPremier AG DWL-AG660 Wireless Cardbus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001b_1186_3a22[] = "D-Link AirPremier AG DWL-AG530 Wireless PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001b_168c_2062[] = "EnGenius EMP-8602 (400mw) or Compex WLM54AG (SuperAG)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_001b_168c_2063[] = "EnGenius EMP-8602 (400mw) or Compex WLM54AG"; +#endif +static const char pci_device_168c_0020[] = "AR5005VL 802.11bg Wireless NIC"; +static const char pci_device_168c_1014[] = "AR5212 802.11abg NIC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_168c_1014_1014_058a[] = "ThinkPad 11a/b/g Wireless LAN Mini Express Adapter (AR5BXB6)"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1695[] = "EPoX Computer Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_169c[] = "Netcell Corporation"; +static const char pci_device_169c_0044[] = "Revolution Storage Processing Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16a5[] = "Tekram Technology Co.,Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ab[] = "Global Sun Technology Inc"; +static const char pci_device_16ab_1100[] = "GL24110P"; +static const char pci_device_16ab_1101[] = "PLX9052 PCMCIA-to-PCI Wireless LAN"; +static const char pci_device_16ab_1102[] = "PCMCIA-to-PCI Wireless Network Bridge"; +static const char pci_device_16ab_8501[] = "WL-8305 Wireless LAN PCI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ae[] = "Safenet Inc"; +static const char pci_device_16ae_1141[] = "SafeXcel-1141"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16af[] = "SparkLAN Communications, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16b4[] = "Aspex Semiconductor Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16b8[] = "Sonnet Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16be[] = "Creatix Polymedia GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16c6[] = "Micrel-Kendin"; +static const char pci_device_16c6_8695[] = "Centaur KS8695 ARM processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16c8[] = "Octasic Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16c9[] = "EONIC B.V. The Netherlands"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ca[] = "CENATEK Inc"; +static const char pci_device_16ca_0001[] = "Rocket Drive DL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16cd[] = "Densitron Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ce[] = "Roland Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16d5[] = "Acromag, Inc."; +static const char pci_device_16d5_4d4e[] = "PMC482, APC482, AcPC482 Counter Timer Board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16df[] = "PIKA Technologies Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16e3[] = "European Space Agency"; +static const char pci_device_16e3_1e0f[] = "LEON2FT Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16e5[] = "Intellon Corp."; +static const char pci_device_16e5_6000[] = "INT6000 Ethernet-to-Powerline Bridge [HomePlug AV]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ec[] = "U.S. Robotics"; +static const char pci_device_16ec_00ff[] = "USR997900 10/100 Mbps PCI Network Card"; +static const char pci_device_16ec_0116[] = "USR997902 10/100/1000 Mbps PCI Network Card"; +static const char pci_device_16ec_2f00[] = "USR5660A (USR265660A, USR5660A-BP) 56K PCI Faxmodem"; +static const char pci_device_16ec_3685[] = "Wireless Access PCI Adapter Model 022415"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16ed[] = "Sycron N. V."; +static const char pci_device_16ed_1001[] = "UMIO communication card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16f3[] = "Jetway Information Co., Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16f4[] = "Vweb Corp"; +static const char pci_device_16f4_8000[] = "VW2010"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_16f6[] = "VideoTele.com, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1702[] = "Internet Machines Corporation (IMC)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1705[] = "Digital First, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_170b[] = "NetOctave"; +static const char pci_device_170b_0100[] = "NSP2000-SSL crypto accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_170c[] = "YottaYotta Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1725[] = "Vitesse Semiconductor"; +static const char pci_device_1725_7174[] = "VSC7174 PCI/PCI-X Serial ATA Host Bus Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_172a[] = "Accelerated Encryption"; +static const char pci_device_172a_13c8[] = "AEP SureWare Runner 1000V3"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1734[] = "Fujitsu Siemens Computer GmbH"; +static const char pci_device_1734_1078[] = "Amilo Pro v2010"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1737[] = "Linksys"; +static const char pci_device_1737_0013[] = "WMP54G Wireless Pci Card"; +static const char pci_device_1737_0015[] = "WMP54GS Wireless Pci Card"; +static const char pci_device_1737_1032[] = "Gigabit Network Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1737_1032_1737_0015[] = "EG1032 v2 Instant Gigabit Network Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1737_1032_1737_0024[] = "EG1032 v3 Instant Gigabit Network Adapter"; +#endif +static const char pci_device_1737_1064[] = "Gigabit Network Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1737_1064_1737_0016[] = "EG1064 v2 Instant Gigabit Network Adapter"; +#endif +static const char pci_device_1737_ab08[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +static const char pci_device_1737_ab09[] = "21x4x DEC-Tulip compatible 10/100 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_173b[] = "Altima (nee Broadcom)"; +static const char pci_device_173b_03e8[] = "AC1000 Gigabit Ethernet"; +static const char pci_device_173b_03e9[] = "AC1001 Gigabit Ethernet"; +static const char pci_device_173b_03ea[] = "AC9100 Gigabit Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_173b_03ea_173b_0001[] = "AC1002"; +#endif +static const char pci_device_173b_03eb[] = "AC1003 Gigabit Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1743[] = "Peppercon AG"; +static const char pci_device_1743_8139[] = "ROL/F-100 Fast Ethernet Adapter with ROL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1749[] = "RLX Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_174b[] = "PC Partner Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_174d[] = "WellX Telecom SA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_175c[] = "AudioScience Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_175e[] = "Sanera Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1775[] = "SBS Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1787[] = "Hightech Information System Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1796[] = "Research Centre Juelich"; +static const char pci_device_1796_0001[] = "SIS1100 [Gigabit link]"; +static const char pci_device_1796_0002[] = "HOTlink"; +static const char pci_device_1796_0003[] = "Counter Timer"; +static const char pci_device_1796_0004[] = "CAMAC Controller"; +static const char pci_device_1796_0005[] = "PROFIBUS"; +static const char pci_device_1796_0006[] = "AMCC HOTlink"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1797[] = "JumpTec h, GMBH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1799[] = "Belkin"; +static const char pci_device_1799_6001[] = "Wireless PCI Card - F5D6001"; +static const char pci_device_1799_6020[] = "Wireless PCMCIA Card - F5D6020"; +static const char pci_device_1799_6060[] = "Wireless PDA Card - F5D6060"; +static const char pci_device_1799_7000[] = "Wireless PCI Card - F5D7000"; +static const char pci_device_1799_700a[] = "Wireless PCI Card - F5D7000UK"; +static const char pci_device_1799_7010[] = "BCM4306 802.11b/g Wireless Lan Controller F5D7010"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_179c[] = "Data Patterns"; +static const char pci_device_179c_0557[] = "DP-PCI-557 [PCI 1553B]"; +static const char pci_device_179c_0566[] = "DP-PCI-566 [Intelligent PCI 1553B]"; +static const char pci_device_179c_5031[] = "DP-CPCI-5031-Synchro Module"; +static const char pci_device_179c_5121[] = "DP-CPCI-5121-IP Carrier"; +static const char pci_device_179c_5211[] = "DP-CPCI-5211-IP Carrier"; +static const char pci_device_179c_5679[] = "AGE Display Module"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17a0[] = "Genesys Logic, Inc"; +static const char pci_device_17a0_8033[] = "GL880S USB 1.1 controller"; +static const char pci_device_17a0_8034[] = "GL880S USB 2.0 controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17aa[] = "Lenovo"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17af[] = "Hightech Information System Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17b3[] = "Hawking Technologies"; +static const char pci_device_17b3_ab08[] = "PN672TX 10/100 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17b4[] = "Indra Networks, Inc."; +static const char pci_device_17b4_0011[] = "WebEnhance 100 GZIP Compression Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17c0[] = "Wistron Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17c2[] = "Newisys, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17cb[] = "Airgo Networks Inc"; +static const char pci_device_17cb_0001[] = "AGN100 802.11 a/b/g True MIMO Wireless Card"; +static const char pci_device_17cb_0002[] = "AGN300 802.11 a/b/g True MIMO Wireless Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17cc[] = "NetChip Technology, Inc"; +static const char pci_device_17cc_2280[] = "USB 2.0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17cf[] = "Z-Com, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17d3[] = "Areca Technology Corp."; +static const char pci_device_17d3_1110[] = "ARC-1110 4-Port PCI-X to SATA RAID Controller"; +static const char pci_device_17d3_1120[] = "ARC-1120 8-Port PCI-X to SATA RAID Controller"; +static const char pci_device_17d3_1130[] = "ARC-1130 12-Port PCI-X to SATA RAID Controller"; +static const char pci_device_17d3_1160[] = "ARC-1160 16-Port PCI-X to SATA RAID Controller"; +static const char pci_device_17d3_1210[] = "ARC-1210 4-Port PCI-Express to SATA RAID Controller"; +static const char pci_device_17d3_1220[] = "ARC-1220 8-Port PCI-Express to SATA RAID Controller"; +static const char pci_device_17d3_1230[] = "ARC-1230 12-Port PCI-Express to SATA RAID Controller"; +static const char pci_device_17d3_1260[] = "ARC-1260 16-Port PCI-Express to SATA RAID Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17d5[] = "S2io Inc."; +static const char pci_device_17d5_5831[] = "Xframe 10 Gigabit Ethernet PCI-X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_17d5_5831_103c_12d5[] = "PCI-X 133MHz 10GbE SR Fiber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_17d5_5831_10a9_8020[] = "Single Port 10 Gigabit Ethernet (PCI-X, Fiber)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_17d5_5831_10a9_8024[] = "Single Port 10 Gigabit Ethernet (PCI-X, Fiber)"; +#endif +static const char pci_device_17d5_5832[] = "Xframe II 10Gbps Ethernet"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_17d5_5832_10a9_8021[] = "Single Port 10 Gigabit Ethernet II (PCI-X, Fiber)"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17db[] = "Cray Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17de[] = "KWorld Computer Co. Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17e4[] = "Sectra AB"; +static const char pci_device_17e4_0001[] = "KK671 Cardbus encryption board"; +static const char pci_device_17e4_0002[] = "KK672 Cardbus encryption board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17e6[] = "Entropic Communications Inc."; +static const char pci_device_17e6_0010[] = "EN2010 [c.Link] MoCA Network Controller (Coax, PCI interface)"; +static const char pci_device_17e6_0011[] = "EN2010 [c.Link] MoCA Network Controller (Coax, MPEG interface)"; +static const char pci_device_17e6_0021[] = "EN2210 [c.Link] MoCA Network Controller (Coax)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17ee[] = "Connect Components Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17f2[] = "Albatron Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17fe[] = "Linksys, A Division of Cisco Systems"; +static const char pci_device_17fe_2120[] = "WMP11v4 802.11b PCI card"; +static const char pci_device_17fe_2220[] = "[AirConn] INPROCOMM IPN 2220 Wireless LAN Adapter (rev 01)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_17fe_2220_17fe_2220[] = "WPC54G ver. 4"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_17ff[] = "Benq Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1809[] = "Lumanate, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1813[] = "Ambient Technologies Inc"; +static const char pci_device_1813_4000[] = "HaM controllerless modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1813_4000_16be_0001[] = "V9x HAM Data Fax Modem"; +#endif +static const char pci_device_1813_4100[] = "HaM plus Data Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1813_4100_16be_0002[] = "V9x HAM 1394"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1814[] = "RaLink"; +static const char pci_device_1814_0101[] = "Wireless PCI Adapter RT2400 / RT2460"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0101_1043_0127[] = "WiFi-b add-on Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0101_1462_6828[] = "PC11B2 (MS-6828) Wireless 11b PCI Card"; +#endif +static const char pci_device_1814_0200[] = "RT2500 802.11g PCI [PC54G2]"; +static const char pci_device_1814_0201[] = "RT2500 802.11g Cardbus/mini-PCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1043_130f[] = "WL-130g"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1371_001e[] = "CWC-854 Wireless-G CardBus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1371_001f[] = "CWM-854 Wireless-G Mini PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1371_0020[] = "CWP-854 Wireless-G PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1458_e381[] = "GN-WMKG 802.11b/g Wireless CardBus Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1458_e931[] = "GN-WIKG 802.11b/g mini-PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1462_6835[] = "Wireless 11G CardBus CB54G2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1737_0032[] = "WMP54G 2.0 PCI Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1799_700a[] = "F5D7000 Wireless G Desktop Network Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_1799_701a[] = "F5D7010 Wireless G Notebook Network Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0201_185f_22a0[] = "CN-WF513 Wireless Cardbus Adapter"; +#endif +static const char pci_device_1814_0301[] = "RT2561/RT61 802.11g PCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0301_1186_3c08[] = "DWL-G630 Rev E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0301_1186_3c09[] = "DWL-G510 Rev C"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0301_1737_0055[] = "WMP54G ver 4.1"; +#endif +static const char pci_device_1814_0302[] = "RT2561/RT61 rev B 802.11g"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0302_1186_3c08[] = "DWL-G630 Rev E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_1814_0302_1186_3c09[] = "DWL-G510 Rev C"; +#endif +static const char pci_device_1814_0401[] = "Ralink RT2600 802.11 MIMO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1820[] = "InfiniCon Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1822[] = "Twinhan Technology Co. Ltd"; +static const char pci_device_1822_4e35[] = "Mantis DTV PCI Bridge Controller [Ver 1.0]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_182d[] = "SiteCom Europe BV"; +static const char pci_device_182d_3069[] = "ISDN PCI DC-105V2"; +static const char pci_device_182d_9790[] = "WL-121 Wireless Network Adapter 100g+ [Ver.3]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_182e[] = "Raza Microelectronics, Inc."; +static const char pci_device_182e_0008[] = "XLR516 Processor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1830[] = "Credence Systems Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_183b[] = "MikroM GmbH"; +static const char pci_device_183b_08a7[] = "MVC100 DVI"; +static const char pci_device_183b_08a8[] = "MVC101 SDI"; +static const char pci_device_183b_08a9[] = "MVC102 DVI+Audio"; +static const char pci_device_183b_08b0[] = "MVC200-DC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1849[] = "ASRock Incorporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_184a[] = "Thales Computers"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1851[] = "Microtune, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1852[] = "Anritsu Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1853[] = "SMSC Automotive Infotainment System Group"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1854[] = "LG Electronics, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_185b[] = "Compro Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_185f[] = "Wistron NeWeb Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1864[] = "SilverBack"; +static const char pci_device_1864_2110[] = "ISNAP 2110"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1867[] = "Topspin Communications"; +static const char pci_device_1867_5a44[] = "MT23108 InfiniHost HCA"; +static const char pci_device_1867_5a45[] = "MT23108 InfiniHost HCA flash recovery"; +static const char pci_device_1867_5a46[] = "MT23108 InfiniHost HCA bridge"; +static const char pci_device_1867_6278[] = "MT25208 InfiniHost III Ex (Tavor compatibility mode)"; +static const char pci_device_1867_6282[] = "MT25208 InfiniHost III Ex"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_187e[] = "ZyXEL Communication Corporation"; +static const char pci_device_187e_3403[] = "ZyAir G-110 802.11g"; +static const char pci_device_187e_340e[] = "M-302 802.11g XtremeMIMO"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1885[] = "Avvida Systems Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1888[] = "Varisys Ltd"; +static const char pci_device_1888_0301[] = "VMFX1 FPGA PMC module"; +static const char pci_device_1888_0601[] = "VSM2 dual PMC carrier"; +static const char pci_device_1888_0710[] = "VS14x series PowerPC PCI board"; +static const char pci_device_1888_0720[] = "VS24x series PowerPC PCI board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_188a[] = "Ample Communications, Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1890[] = "Egenera, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1894[] = "KNC One"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1896[] = "B&B Electronics Manufacturing Company, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18a1[] = "Astute Networks Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18ac[] = "DViCO Corporation"; +static const char pci_device_18ac_d500[] = "FusionHDTV 5"; +static const char pci_device_18ac_d800[] = "FusionHDTV 3 Gold"; +static const char pci_device_18ac_d810[] = "FusionHDTV 3 Gold-Q"; +static const char pci_device_18ac_d820[] = "FusionHDTV 3 Gold-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18b8[] = "Ammasso"; +static const char pci_device_18b8_b001[] = "AMSO 1100 iWARP/RDMA Gigabit Ethernet Coprocessor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18bc[] = "Info-Tek Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18c3[] = "Micronas Semiconductor Holding AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18c8[] = "Cray Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18c9[] = "ARVOO Engineering BV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18ca[] = "XGI - Xabre Graphics Inc"; +static const char pci_device_18ca_0020[] = "Volari Z7"; +static const char pci_device_18ca_0040[] = "Volari V3XT/V5/V8"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18d2[] = "Sitecom"; +static const char pci_device_18d2_3069[] = "DC-105v2 ISDN controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18dd[] = "Artimi Inc"; +static const char pci_device_18dd_4c6f[] = "Artimi RTMI-100 UWB adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18e6[] = "MPL AG"; +static const char pci_device_18e6_0001[] = "OSCI [Octal Serial Communication Interface]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18ec[] = "Cesnet, z.s.p.o."; +static const char pci_device_18ec_c006[] = "COMBO6"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c006_18ec_d001[] = "COMBO-4MTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c006_18ec_d002[] = "COMBO-4SFP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c006_18ec_d003[] = "COMBO-4SFPRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c006_18ec_d004[] = "COMBO-2XFP"; +#endif +static const char pci_device_18ec_c045[] = "COMBO6E"; +static const char pci_device_18ec_c050[] = "COMBO-PTM"; +static const char pci_device_18ec_c058[] = "COMBO6X"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c058_18ec_d001[] = "COMBO-4MTX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c058_18ec_d002[] = "COMBO-4SFP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c058_18ec_d003[] = "COMBO-4SFPRO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_18ec_c058_18ec_d004[] = "COMBO-2XFP"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18f6[] = "NextIO"; +static const char pci_device_18f6_1000[] = "[Nexsis] Switch Virtual P2P PCIe Bridge"; +static const char pci_device_18f6_1050[] = "[Nexsis] Switch Virtual P2P PCI Bridge"; +static const char pci_device_18f6_2000[] = "[Nexsis] Switch Integrated Mgmt. Endpoint"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18f7[] = "Commtech, Inc."; +static const char pci_device_18f7_0001[] = "Fastcom ESCC-PCI-335"; +static const char pci_device_18f7_0002[] = "Fastcom 422/4-PCI-335"; +static const char pci_device_18f7_0004[] = "Fastcom 422/2-PCI-335"; +static const char pci_device_18f7_0005[] = "Fastcom IGESCC-PCI-ISO/1"; +static const char pci_device_18f7_000a[] = "Fastcom 232/4-PCI-335"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_18fb[] = "Resilience Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1904[] = "Hangzhou Silan Microelectronics Co., Ltd."; +static const char pci_device_1904_8139[] = "RTL8139D [Realtek] PCI 10/100BaseTX ethernet adaptor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1923[] = "Sangoma Technologies Corp."; +static const char pci_device_1923_0040[] = "A200/Remora FXO/FXS Analog AFT card"; +static const char pci_device_1923_0100[] = "A104d QUAD T1/E1 AFT card"; +static const char pci_device_1923_0300[] = "A101 single-port T1/E1"; +static const char pci_device_1923_0400[] = "A104u Quad T1/E1 AFT"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1924[] = "Level 5 Networks Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_192e[] = "TransDimension"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1931[] = "Option N.V."; +static const char pci_device_1931_000c[] = "Qualcomm MSM6275 UMTS chip"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1942[] = "ClearSpeed Technology plc"; +static const char pci_device_1942_e511[] = "CSX600 Advance Accelerator Board"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_194a[] = "DapTechnology B.V."; +static const char pci_device_194a_1111[] = "FireSpy3850"; +static const char pci_device_194a_1112[] = "FireSpy450b"; +static const char pci_device_194a_1113[] = "FireSpy450bT"; +static const char pci_device_194a_1114[] = "FireSpy850"; +static const char pci_device_194a_1115[] = "FireSpy850bT"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1957[] = "Freescale Semiconductor Inc"; +static const char pci_device_1957_0012[] = "MPC8548 [PowerQUICC III]"; +static const char pci_device_1957_0080[] = "MPC8349E"; +static const char pci_device_1957_0081[] = "MPC8349"; +static const char pci_device_1957_0082[] = "MPC8347E TBGA"; +static const char pci_device_1957_0083[] = "MPC8347 TBGA"; +static const char pci_device_1957_0084[] = "MPC8347E PBGA"; +static const char pci_device_1957_0085[] = "MPC8347 PBGA"; +static const char pci_device_1957_0086[] = "MPC8343E"; +static const char pci_device_1957_0087[] = "MPC8343"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1958[] = "Faster Technology, LLC."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1966[] = "Orad Hi-Tec Systems"; +static const char pci_device_1966_1975[] = "DVG64 family"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1969[] = "Attansic Technology Corp."; +static const char pci_device_1969_1048[] = "L1 Gigabit Ethernet Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_196a[] = "Sensory Networks Inc."; +static const char pci_device_196a_0101[] = "NodalCore C-1000 Content Classification Accelerator"; +static const char pci_device_196a_0102[] = "NodalCore C-2000 Content Classification Accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_196d[] = "Club-3D BV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_197b[] = "JMicron Technologies, Inc."; +static const char pci_device_197b_2360[] = "JMicron 20360/20363 AHCI Controller"; +static const char pci_device_197b_2361[] = "JMB361 AHCI/IDE"; +static const char pci_device_197b_2363[] = "JMicron 20360/20363 AHCI Controller"; +static const char pci_device_197b_2365[] = "JMB365 AHCI/IDE"; +static const char pci_device_197b_2366[] = "JMB366 AHCI/IDE"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1989[] = "Montilio Inc."; +static const char pci_device_1989_0001[] = "RapidFile Bridge"; +static const char pci_device_1989_8001[] = "RapidFile"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1993[] = "Innominate Security Technologies AG"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_199a[] = "Pulse-LINK, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_19a8[] = "DAQDATA GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_19ac[] = "Kasten Chase Applied Research"; +static const char pci_device_19ac_0001[] = "ACA2400 Crypto Accelerator"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_19ae[] = "Progeny Systems Corporation"; +static const char pci_device_19ae_0520[] = "4135 HFT Interface Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_19d4[] = "Quixant Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_19e2[] = "Vector Informatik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_19e7[] = "NET (Network Equipment Technologies)"; +static const char pci_device_19e7_1001[] = "STIX DSP Card"; +static const char pci_device_19e7_1002[] = "STIX - 1 Port T1/E1 Card"; +static const char pci_device_19e7_1003[] = "STIX - 2 Port T1/E1 Card"; +static const char pci_device_19e7_1004[] = "STIX - 4 Port T1/E1 Card"; +static const char pci_device_19e7_1005[] = "STIX - 4 Port FXS Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1a03[] = "ASPEED Technology, Inc."; +static const char pci_device_1a03_2000[] = "AST2000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1a08[] = "Sierra semiconductor"; +static const char pci_device_1a08_0000[] = "SC15064"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1a1d[] = "GFaI e.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1a29[] = "Fortinet, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1a51[] = "Hectronic AB"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1b13[] = "Jaton Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1c1c[] = "Symphony"; +static const char pci_device_1c1c_0001[] = "82C101"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1d44[] = "DPT"; +static const char pci_device_1d44_a400[] = "PM2x24/PM3224"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1de1[] = "Tekram Technology Co.,Ltd."; +static const char pci_device_1de1_0391[] = "TRM-S1040"; +static const char pci_device_1de1_2020[] = "DC-390"; +static const char pci_device_1de1_690c[] = "690c"; +static const char pci_device_1de1_dc29[] = "DC290"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1fc0[] = "Tumsan Oy"; +static const char pci_device_1fc0_0300[] = "E2200 Dual E1/Rawpipe Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1fc1[] = "PathScale, Inc"; +static const char pci_device_1fc1_000d[] = "InfiniPath HT-400"; +static const char pci_device_1fc1_0010[] = "InfiniPath PE-800"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_1fce[] = "Cognio Inc."; +static const char pci_device_1fce_0001[] = "Spectrum Analyzer PC Card (SAgE)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2000[] = "Smart Link Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2001[] = "Temporal Research Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2003[] = "Smart Link Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2004[] = "Smart Link Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_21c3[] = "21st Century Computer Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_22b8[] = "Motorola, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2348[] = "Racore"; +static const char pci_device_2348_2010[] = "8142 100VG/AnyLAN"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2646[] = "Kingston Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_270b[] = "Xantel Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_270f[] = "Chaintech Computer Co. Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2711[] = "AVID Technology Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_2a15[] = "3D Vision(?)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3000[] = "Hansol Electronics Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3142[] = "Post Impression Systems."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3388[] = "Hint Corp"; +static const char pci_device_3388_0013[] = "HiNT HC4 PCI to ISDN bridge, Multimedia audio controller"; +static const char pci_device_3388_0014[] = "HiNT HC4 PCI to ISDN bridge, Network controller"; +static const char pci_device_3388_0020[] = "HB6 Universal PCI-PCI bridge (transparent mode)"; +static const char pci_device_3388_0021[] = "HB6 Universal PCI-PCI bridge (non-transparent mode)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_1775_ce90[] = "CE9"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_1090[] = "Cx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_10a0[] = "CA3/CR3 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_3010[] = "PPCI mezzanine (32-bit PMC)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_3011[] = "PPCI mezzanine (64-bit PMC)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_0021_4c53_4000[] = "PMCCARR1 carrier board"; +#endif +static const char pci_device_3388_0022[] = "HiNT HB4 PCI-PCI Bridge (PCI6150)"; +static const char pci_device_3388_0026[] = "HB2 PCI-PCI Bridge"; +static const char pci_device_3388_101a[] = "E.Band [AudioTrak Inca88]"; +static const char pci_device_3388_101b[] = "E.Band [AudioTrak Inca88]"; +static const char pci_device_3388_8011[] = "VXPro II Chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_8011_3388_8011[] = "VXPro II Chipset CPU to PCI Bridge"; +#endif +static const char pci_device_3388_8012[] = "VXPro II Chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_8012_3388_8012[] = "VXPro II Chipset PCI to ISA Bridge"; +#endif +static const char pci_device_3388_8013[] = "VXPro II IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3388_8013_3388_8013[] = "VXPro II Chipset EIDE Controller"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3411[] = "Quantum Designs (H.K.) Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3513[] = "ARCOM Control Systems Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_3842[] = "eVga.com. Corp."; +static const char pci_device_3842_c370[] = "e-GeFORCE 6600 256 DDR PCI-e"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_38ef[] = "4Links"; +#endif +static const char pci_vendor_3d3d[] = "3DLabs"; +static const char pci_device_3d3d_0001[] = "GLINT 300SX"; +static const char pci_device_3d3d_0002[] = "GLINT 500TX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0002_0000_0000[] = "GLoria L"; +#endif +static const char pci_device_3d3d_0003[] = "GLINT Delta"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0003_0000_0000[] = "GLoria XL"; +#endif +static const char pci_device_3d3d_0004[] = "Permedia"; +static const char pci_device_3d3d_0005[] = "Permedia"; +static const char pci_device_3d3d_0006[] = "GLINT MX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0006_0000_0000[] = "GLoria XL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0006_1048_0a42[] = "GLoria XXL"; +#endif +static const char pci_device_3d3d_0007[] = "3D Extreme"; +static const char pci_device_3d3d_0008[] = "GLINT Gamma G1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0008_1048_0a42[] = "GLoria XXL"; +#endif +static const char pci_device_3d3d_0009[] = "Permedia II 2D+3D"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_1040_0011[] = "AccelStar II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_1048_0a42[] = "GLoria XXL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_13e9_1000[] = "6221L-4U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0100[] = "AccelStar II 3D Accelerator"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0111[] = "Permedia 3:16"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0114[] = "Santa Ana"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0116[] = "Oxygen GVX1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0119[] = "Scirocco"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0120[] = "Santa Ana PCL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0125[] = "Oxygen VX1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_0009_3d3d_0127[] = "Permedia3 Create!"; +#endif +static const char pci_device_3d3d_000a[] = "GLINT R3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_000a_3d3d_0121[] = "Oxygen VX1"; +#endif +static const char pci_device_3d3d_000c[] = "GLINT R3 [Oxygen VX1]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_3d3d_000c_3d3d_0144[] = "Oxygen VX1-4X AGP [Permedia 4]"; +#endif +static const char pci_device_3d3d_000d[] = "GLint R4 rev A"; +static const char pci_device_3d3d_0011[] = "GLint R4 rev B"; +static const char pci_device_3d3d_0012[] = "GLint R5 rev A"; +static const char pci_device_3d3d_0013[] = "GLint R5 rev B"; +static const char pci_device_3d3d_0020[] = "VP10 visual processor"; +static const char pci_device_3d3d_0022[] = "VP10 visual processor"; +static const char pci_device_3d3d_0024[] = "VP9 visual processor"; +static const char pci_device_3d3d_0100[] = "Permedia II 2D+3D"; +static const char pci_device_3d3d_07a1[] = "Wildcat III 6210"; +static const char pci_device_3d3d_07a2[] = "Sun XVR-500 Graphics Accelerator"; +static const char pci_device_3d3d_07a3[] = "Wildcat IV 7210"; +static const char pci_device_3d3d_1004[] = "Permedia"; +static const char pci_device_3d3d_3d04[] = "Permedia"; +static const char pci_device_3d3d_ffff[] = "Glint VGA"; +static const char pci_vendor_4005[] = "Avance Logic Inc."; +static const char pci_device_4005_0300[] = "ALS300 PCI Audio Device"; +static const char pci_device_4005_0308[] = "ALS300+ PCI Audio Device"; +static const char pci_device_4005_0309[] = "PCI Input Controller"; +static const char pci_device_4005_1064[] = "ALG-2064"; +static const char pci_device_4005_2064[] = "ALG-2064i"; +static const char pci_device_4005_2128[] = "ALG-2364A GUI Accelerator"; +static const char pci_device_4005_2301[] = "ALG-2301"; +static const char pci_device_4005_2302[] = "ALG-2302"; +static const char pci_device_4005_2303[] = "AVG-2302 GUI Accelerator"; +static const char pci_device_4005_2364[] = "ALG-2364A"; +static const char pci_device_4005_2464[] = "ALG-2464"; +static const char pci_device_4005_2501[] = "ALG-2564A/25128A"; +static const char pci_device_4005_4000[] = "ALS4000 Audio Chipset"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4005_4000_4005_4000[] = "ALS4000 Audio Chipset"; +#endif +static const char pci_device_4005_4710[] = "ALC200/200P"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4033[] = "Addtron Technology Co, Inc."; +static const char pci_device_4033_1360[] = "RTL8139 Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4143[] = "Digital Equipment Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4144[] = "Alpha Data"; +static const char pci_device_4144_0044[] = "ADM-XRCIIPro"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_416c[] = "Aladdin Knowledge Systems"; +static const char pci_device_416c_0100[] = "AladdinCARD"; +static const char pci_device_416c_0200[] = "CPC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4321[] = "Tata Power Strategic Electronics Division"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4444[] = "Internext Compression Inc"; +static const char pci_device_4444_0016[] = "iTVC16 (CX23416) MPEG-2 Encoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_0003[] = "WinTV PVR 250"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_0009[] = "WinTV PVR 150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_0801[] = "WinTV PVR 150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_0807[] = "WinTV PVR 150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_4001[] = "WinTV PVR 250"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_4009[] = "WinTV PVR 250"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_4801[] = "WinTV PVR 250"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_4803[] = "WinTV PVR 250"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_8003[] = "WinTV PVR 150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_8801[] = "WinTV PVR 150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_c801[] = "WinTV PVR 150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_e807[] = "WinTV PVR 500 (1st unit)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_e817[] = "WinTV PVR 500 (2nd unit)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0070_ff92[] = "WiNTV PVR-550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_0270_0801[] = "WinTV PVR 150"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_10fc_d038[] = "GV-MVP/RX2W (1st unit)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_10fc_d039[] = "GV-MVP/RX2W (2nd unit)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_12ab_fff3[] = "MPG600"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_12ab_ffff[] = "MPG600"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_1461_c019[] = "UltraTV 1500 MCE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_9005_0092[] = "VideOh! AVC-2010"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0016_9005_0093[] = "VideOh! AVC-2410"; +#endif +static const char pci_device_4444_0803[] = "iTVC15 MPEG-2 Encoder"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0803_0070_4000[] = "WinTV PVR-350"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0803_0070_4001[] = "WinTV PVR-250"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0803_0070_4800[] = "WinTV PVR-350 (V1)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0803_12ab_0000[] = "MPG160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0803_1461_a3ce[] = "M179"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4444_0803_1461_a3cf[] = "M179"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4468[] = "Bridgeport machines"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4594[] = "Cogetec Informatique Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_45fb[] = "Baldor Electric Company"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4680[] = "Umax Computer Corp"; +#endif +static const char pci_vendor_4843[] = "Hercules Computer Technology Inc"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4916[] = "RedCreek Communications Inc"; +static const char pci_device_4916_1960[] = "RedCreek PCI adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4943[] = "Growth Networks"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_494f[] = "ACCES I/O Products, Inc."; +static const char pci_device_494f_10e8[] = "LPCI-COM-8SM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4978[] = "Axil Computer Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4a14[] = "NetVin"; +static const char pci_device_4a14_5000[] = "NV5000SC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4a14_5000_4a14_5000[] = "RT8029-Based Ethernet Adapter"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4b10[] = "Buslogic Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4c48[] = "LUNG HWA Electronics"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4c53[] = "SBS Technologies"; +static const char pci_device_4c53_0000[] = "PLUSTEST device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4c53_0000_4c53_3000[] = "PLUSTEST card (PC104+)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4c53_0000_4c53_3001[] = "PLUSTEST card (PMC)"; +#endif +static const char pci_device_4c53_0001[] = "PLUSTEST-MM device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_4c53_0001_4c53_3002[] = "PLUSTEST-MM card (PMC)"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4ca1[] = "Seanix Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4d51[] = "MediaQ Inc."; +static const char pci_device_4d51_0200[] = "MQ-200"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4d54[] = "Microtechnica Co Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_4ddc[] = "ILC Data Device Corp"; +static const char pci_device_4ddc_0100[] = "DD-42924I5-300 (ARINC 429 Data Bus)"; +static const char pci_device_4ddc_0801[] = "BU-65570I1 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0802[] = "BU-65570I2 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0811[] = "BU-65572I1 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0812[] = "BU-65572I2 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0881[] = "BU-65570T1 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0882[] = "BU-65570T2 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0891[] = "BU-65572T1 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0892[] = "BU-65572T2 MIL-STD-1553 Test and Simulation"; +static const char pci_device_4ddc_0901[] = "BU-65565C1 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0902[] = "BU-65565C2 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0903[] = "BU-65565C3 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0904[] = "BU-65565C4 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0b01[] = "BU-65569I1 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0b02[] = "BU-65569I2 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0b03[] = "BU-65569I3 MIL-STD-1553 Data Bus"; +static const char pci_device_4ddc_0b04[] = "BU-65569I4 MIL-STD-1553 Data Bus"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5046[] = "GemTek Technology Corporation"; +static const char pci_device_5046_1001[] = "PCI Radio"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5053[] = "Voyetra Technologies"; +static const char pci_device_5053_2010[] = "Daytona Audio Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5136[] = "S S Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5143[] = "Qualcomm Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5145[] = "Ensoniq (Old)"; +static const char pci_device_5145_3031[] = "Concert AudioPCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5168[] = "Animation Technologies Inc."; +static const char pci_device_5168_0300[] = "FlyDVB-S"; +static const char pci_device_5168_0301[] = "FlyDVB-T"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5301[] = "Alliance Semiconductor Corp."; +static const char pci_device_5301_0001[] = "ProMotion aT3D"; +#endif +static const char pci_vendor_5333[] = "S3 Inc."; +static const char pci_device_5333_0551[] = "Plato/PX (system)"; +static const char pci_device_5333_5631[] = "86c325 [ViRGE]"; +static const char pci_device_5333_8800[] = "86c866 [Vision 866]"; +static const char pci_device_5333_8801[] = "86c964 [Vision 964]"; +static const char pci_device_5333_8810[] = "86c764_0 [Trio 32 vers 0]"; +static const char pci_device_5333_8811[] = "86c764/765 [Trio32/64/64V+]"; +static const char pci_device_5333_8812[] = "86cM65 [Aurora64V+]"; +static const char pci_device_5333_8813[] = "86c764_3 [Trio 32/64 vers 3]"; +static const char pci_device_5333_8814[] = "86c767 [Trio 64UV+]"; +static const char pci_device_5333_8815[] = "86cM65 [Aurora 128]"; +static const char pci_device_5333_883d[] = "86c988 [ViRGE/VX]"; +static const char pci_device_5333_8870[] = "FireGL"; +static const char pci_device_5333_8880[] = "86c868 [Vision 868 VRAM] vers 0"; +static const char pci_device_5333_8881[] = "86c868 [Vision 868 VRAM] vers 1"; +static const char pci_device_5333_8882[] = "86c868 [Vision 868 VRAM] vers 2"; +static const char pci_device_5333_8883[] = "86c868 [Vision 868 VRAM] vers 3"; +static const char pci_device_5333_88b0[] = "86c928 [Vision 928 VRAM] vers 0"; +static const char pci_device_5333_88b1[] = "86c928 [Vision 928 VRAM] vers 1"; +static const char pci_device_5333_88b2[] = "86c928 [Vision 928 VRAM] vers 2"; +static const char pci_device_5333_88b3[] = "86c928 [Vision 928 VRAM] vers 3"; +static const char pci_device_5333_88c0[] = "86c864 [Vision 864 DRAM] vers 0"; +static const char pci_device_5333_88c1[] = "86c864 [Vision 864 DRAM] vers 1"; +static const char pci_device_5333_88c2[] = "86c864 [Vision 864-P DRAM] vers 2"; +static const char pci_device_5333_88c3[] = "86c864 [Vision 864-P DRAM] vers 3"; +static const char pci_device_5333_88d0[] = "86c964 [Vision 964 VRAM] vers 0"; +static const char pci_device_5333_88d1[] = "86c964 [Vision 964 VRAM] vers 1"; +static const char pci_device_5333_88d2[] = "86c964 [Vision 964-P VRAM] vers 2"; +static const char pci_device_5333_88d3[] = "86c964 [Vision 964-P VRAM] vers 3"; +static const char pci_device_5333_88f0[] = "86c968 [Vision 968 VRAM] rev 0"; +static const char pci_device_5333_88f1[] = "86c968 [Vision 968 VRAM] rev 1"; +static const char pci_device_5333_88f2[] = "86c968 [Vision 968 VRAM] rev 2"; +static const char pci_device_5333_88f3[] = "86c968 [Vision 968 VRAM] rev 3"; +static const char pci_device_5333_8900[] = "86c755 [Trio 64V2/DX]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8900_5333_8900[] = "86C775 Trio64V2/DX"; +#endif +static const char pci_device_5333_8901[] = "86c775/86c785 [Trio 64V2/DX or /GX]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8901_5333_8901[] = "86C775 Trio64V2/DX, 86C785 Trio64V2/GX"; +#endif +static const char pci_device_5333_8902[] = "Plato/PX"; +static const char pci_device_5333_8903[] = "Trio 3D business multimedia"; +static const char pci_device_5333_8904[] = "Trio 64 3D"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8904_1014_00db[] = "Integrated Trio3D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8904_5333_8904[] = "86C365 Trio3D AGP"; +#endif +static const char pci_device_5333_8905[] = "Trio 64V+ family"; +static const char pci_device_5333_8906[] = "Trio 64V+ family"; +static const char pci_device_5333_8907[] = "Trio 64V+ family"; +static const char pci_device_5333_8908[] = "Trio 64V+ family"; +static const char pci_device_5333_8909[] = "Trio 64V+ family"; +static const char pci_device_5333_890a[] = "Trio 64V+ family"; +static const char pci_device_5333_890b[] = "Trio 64V+ family"; +static const char pci_device_5333_890c[] = "Trio 64V+ family"; +static const char pci_device_5333_890d[] = "Trio 64V+ family"; +static const char pci_device_5333_890e[] = "Trio 64V+ family"; +static const char pci_device_5333_890f[] = "Trio 64V+ family"; +static const char pci_device_5333_8a01[] = "ViRGE/DX or /GX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a01_0e11_b032[] = "ViRGE/GX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a01_10b4_1617[] = "Nitro 3D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a01_10b4_1717[] = "Nitro 3D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a01_5333_8a01[] = "ViRGE/DX"; +#endif +static const char pci_device_5333_8a10[] = "ViRGE/GX2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a10_1092_8a10[] = "Stealth 3D 4000"; +#endif +static const char pci_device_5333_8a13[] = "86c368 [Trio 3D/2X]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a13_5333_8a13[] = "Trio3D/2X"; +#endif +static const char pci_device_5333_8a20[] = "86c794 [Savage 3D]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a20_5333_8a20[] = "86C391 Savage3D"; +#endif +static const char pci_device_5333_8a21[] = "86c390 [Savage 3D/MV]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a21_5333_8a21[] = "86C390 Savage3D/MV"; +#endif +static const char pci_device_5333_8a22[] = "Savage 4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1033_8068[] = "Savage 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1033_8069[] = "Savage 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1033_8110[] = "Savage 4 LT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_105d_0018[] = "SR9 8Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_105d_002a[] = "SR9 Pro 16Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_105d_003a[] = "SR9 Pro 32Mb SDRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_105d_092f[] = "SR9 Pro+ 16Mb SGRAM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4207[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4800[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4807[] = "SpeedStar A90"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4808[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4809[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_480e[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4904[] = "Stealth III S520"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4905[] = "SpeedStar A200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4a09[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4a0b[] = "Stealth III S540 Xtreme"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4a0f[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1092_4e01[] = "Stealth III S540"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1102_101d[] = "3d Blaster Savage 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_1102_101e[] = "3d Blaster Savage 4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8100[] = "86C394-397 Savage4 SDRAM 100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8110[] = "86C394-397 Savage4 SDRAM 110"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8125[] = "86C394-397 Savage4 SDRAM 125"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8143[] = "86C394-397 Savage4 SDRAM 143"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8a22[] = "86C394-397 Savage4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_8a2e[] = "86C394-397 Savage4 32bit"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_9125[] = "86C394-397 Savage4 SGRAM 125"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8a22_5333_9143[] = "86C394-397 Savage4 SGRAM 143"; +#endif +static const char pci_device_5333_8a23[] = "Savage 4"; +static const char pci_device_5333_8a25[] = "ProSavage PM133"; +static const char pci_device_5333_8a26[] = "ProSavage KM133"; +static const char pci_device_5333_8c00[] = "ViRGE/M3"; +static const char pci_device_5333_8c01[] = "ViRGE/MX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8c01_1179_0001[] = "ViRGE/MX"; +#endif +static const char pci_device_5333_8c02[] = "ViRGE/MX+"; +static const char pci_device_5333_8c03[] = "ViRGE/MX+MV"; +static const char pci_device_5333_8c10[] = "86C270-294 Savage/MX-MV"; +static const char pci_device_5333_8c11[] = "82C270-294 Savage/MX"; +static const char pci_device_5333_8c12[] = "86C270-294 Savage/IX-MV"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8c12_1014_017f[] = "Thinkpad T20/T22"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8c12_1179_0001[] = "86C584 SuperSavage/IXC Toshiba"; +#endif +static const char pci_device_5333_8c13[] = "86C270-294 Savage/IX"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8c13_1179_0001[] = "Magnia Z310"; +#endif +static const char pci_device_5333_8c22[] = "SuperSavage MX/128"; +static const char pci_device_5333_8c24[] = "SuperSavage MX/64"; +static const char pci_device_5333_8c26[] = "SuperSavage MX/64C"; +static const char pci_device_5333_8c2a[] = "SuperSavage IX/128 SDR"; +static const char pci_device_5333_8c2b[] = "SuperSavage IX/128 DDR"; +static const char pci_device_5333_8c2c[] = "SuperSavage IX/64 SDR"; +static const char pci_device_5333_8c2d[] = "SuperSavage IX/64 DDR"; +static const char pci_device_5333_8c2e[] = "SuperSavage IX/C SDR"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_8c2e_1014_01fc[] = "ThinkPad T23 (2647-4MG)"; +#endif +static const char pci_device_5333_8c2f[] = "SuperSavage IX/C DDR"; +static const char pci_device_5333_8d01[] = "86C380 [ProSavageDDR K4M266]"; +static const char pci_device_5333_8d02[] = "VT8636A [ProSavage KN133] AGP4X VGA Controller (TwisterK)"; +static const char pci_device_5333_8d03[] = "VT8751 [ProSavageDDR P4M266]"; +static const char pci_device_5333_8d04[] = "VT8375 [ProSavage8 KM266/KL266]"; +static const char pci_device_5333_9102[] = "86C410 Savage 2000"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5932[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5934[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5952[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5954[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5a35[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5a37[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5a55[] = "Viper II Z200"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_5333_9102_1092_5a57[] = "Viper II Z200"; +#endif +static const char pci_device_5333_ca00[] = "SonicVibes"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_544c[] = "Teralogic Inc"; +static const char pci_device_544c_0350[] = "TL880-based HDTV/ATSC tuner"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5455[] = "Technische University Berlin"; +static const char pci_device_5455_4458[] = "S5933"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5519[] = "Cnet Technologies, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5544[] = "Dunord Technologies"; +static const char pci_device_5544_0001[] = "I-30xx Scanner Interface"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5555[] = "Genroco, Inc"; +static const char pci_device_5555_0003[] = "TURBOstor HFP-832 [HiPPI NIC]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5654[] = "VoiceTronix Pty Ltd"; +static const char pci_device_5654_3132[] = "OpenSwitch12"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5700[] = "Netpower"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_5851[] = "Exacq Technologies"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_6356[] = "UltraStor"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_6374[] = "c't Magazin fuer Computertechnik"; +static const char pci_device_6374_6773[] = "GPPCI"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_6409[] = "Logitec Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_6666[] = "Decision Computer International Co."; +static const char pci_device_6666_0001[] = "PCCOM4"; +static const char pci_device_6666_0002[] = "PCCOM8"; +static const char pci_device_6666_0004[] = "PCCOM2"; +static const char pci_device_6666_0101[] = "PCI 8255/8254 I/O Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_7063[] = "pcHDTV"; +static const char pci_device_7063_2000[] = "HD-2000"; +static const char pci_device_7063_3000[] = "HD-3000"; +static const char pci_device_7063_5500[] = "HD5500 HDTV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_7604[] = "O.N. Electronic Co Ltd."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_7bde[] = "MIDAC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_7fed[] = "PowerTV"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8008[] = "Quancom Electronic GmbH"; +static const char pci_device_8008_0010[] = "WDOG1 [PCI-Watchdog 1]"; +static const char pci_device_8008_0011[] = "PWDOG2 [PCI-Watchdog 2]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_807d[] = "Asustek Computer, Inc."; +#endif +static const char pci_vendor_8086[] = "Intel Corporation"; +static const char pci_device_8086_0007[] = "82379AB"; +static const char pci_device_8086_0008[] = "Extended Express System Support Controller"; +static const char pci_device_8086_0039[] = "21145 Fast Ethernet"; +static const char pci_device_8086_0122[] = "82437FX"; +static const char pci_device_8086_0309[] = "80303 I/O Processor PCI-to-PCI Bridge"; +static const char pci_device_8086_030d[] = "80312 I/O Companion Chip PCI-to-PCI Bridge"; +static const char pci_device_8086_0326[] = "6700/6702PXH I/OxAPIC Interrupt Controller A"; +static const char pci_device_8086_0327[] = "6700PXH I/OxAPIC Interrupt Controller B"; +static const char pci_device_8086_0329[] = "6700PXH PCI Express-to-PCI Bridge A"; +static const char pci_device_8086_032a[] = "6700PXH PCI Express-to-PCI Bridge B"; +static const char pci_device_8086_032c[] = "6702PXH PCI Express-to-PCI Bridge A"; +static const char pci_device_8086_0330[] = "80332 [Dobson] I/O processor (A-Segment Bridge)"; +static const char pci_device_8086_0331[] = "80332 [Dobson] I/O processor (A-Segment IOAPIC)"; +static const char pci_device_8086_0332[] = "80332 [Dobson] I/O processor (B-Segment Bridge)"; +static const char pci_device_8086_0333[] = "80332 [Dobson] I/O processor (B-Segment IOAPIC)"; +static const char pci_device_8086_0334[] = "80332 [Dobson] I/O processor (ATU)"; +static const char pci_device_8086_0335[] = "80331 [Lindsay] I/O processor (PCI-X Bridge)"; +static const char pci_device_8086_0336[] = "80331 [Lindsay] I/O processor (ATU)"; +static const char pci_device_8086_0340[] = "41210 [Lanai] Serial to Parallel PCI Bridge (A-Segment Bridge)"; +static const char pci_device_8086_0341[] = "41210 [Lanai] Serial to Parallel PCI Bridge (B-Segment Bridge)"; +static const char pci_device_8086_0370[] = "80333 Segment-A PCI Express-to-PCI Express Bridge"; +static const char pci_device_8086_0371[] = "80333 A-Bus IOAPIC"; +static const char pci_device_8086_0372[] = "80333 Segment-B PCI Express-to-PCI Express Bridge"; +static const char pci_device_8086_0373[] = "80333 B-Bus IOAPIC"; +static const char pci_device_8086_0374[] = "80333 Address Translation Unit"; +static const char pci_device_8086_0482[] = "82375EB/SB PCI to EISA Bridge"; +static const char pci_device_8086_0483[] = "82424TX/ZX [Saturn] CPU to PCI bridge"; +static const char pci_device_8086_0484[] = "82378ZB/IB, 82379AB (SIO, SIO.A) PCI to ISA Bridge"; +static const char pci_device_8086_0486[] = "82425EX/ZX [Aries] PCIset with ISA bridge"; +static const char pci_device_8086_04a3[] = "82434LX/NX [Mercury/Neptune] Processor to PCI bridge"; +static const char pci_device_8086_04d0[] = "82437FX [Triton FX]"; +static const char pci_device_8086_0500[] = "E8870 Processor bus control"; +static const char pci_device_8086_0501[] = "E8870 Memory controller"; +static const char pci_device_8086_0502[] = "E8870 Scalability Port 0"; +static const char pci_device_8086_0503[] = "E8870 Scalability Port 1"; +static const char pci_device_8086_0510[] = "E8870IO Hub Interface Port 0 registers (8-bit compatibility port)"; +static const char pci_device_8086_0511[] = "E8870IO Hub Interface Port 1 registers"; +static const char pci_device_8086_0512[] = "E8870IO Hub Interface Port 2 registers"; +static const char pci_device_8086_0513[] = "E8870IO Hub Interface Port 3 registers"; +static const char pci_device_8086_0514[] = "E8870IO Hub Interface Port 4 registers"; +static const char pci_device_8086_0515[] = "E8870IO General SIOH registers"; +static const char pci_device_8086_0516[] = "E8870IO RAS registers"; +static const char pci_device_8086_0530[] = "E8870SP Scalability Port 0 registers"; +static const char pci_device_8086_0531[] = "E8870SP Scalability Port 1 registers"; +static const char pci_device_8086_0532[] = "E8870SP Scalability Port 2 registers"; +static const char pci_device_8086_0533[] = "E8870SP Scalability Port 3 registers"; +static const char pci_device_8086_0534[] = "E8870SP Scalability Port 4 registers"; +static const char pci_device_8086_0535[] = "E8870SP Scalability Port 5 registers"; +static const char pci_device_8086_0536[] = "E8870SP Interleave registers 0 and 1"; +static const char pci_device_8086_0537[] = "E8870SP Interleave registers 2 and 3"; +static const char pci_device_8086_0600[] = "RAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_0600_8086_01af[] = "SRCZCR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_0600_8086_01c1[] = "ICP Vortex GDT8546RZ"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_0600_8086_01f7[] = "SCRU32"; +#endif +static const char pci_device_8086_061f[] = "80303 I/O Processor"; +static const char pci_device_8086_0960[] = "80960RP [i960 RP Microprocessor/Bridge]"; +static const char pci_device_8086_0962[] = "80960RM [i960RM Bridge]"; +static const char pci_device_8086_0964[] = "80960RP [i960 RP Microprocessor/Bridge]"; +static const char pci_device_8086_1000[] = "82542 Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_0e11_b0df[] = "NC1632 Gigabit Ethernet Adapter (1000-SX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_0e11_b0e0[] = "NC1633 Gigabit Ethernet Adapter (1000-LX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_0e11_b123[] = "NC1634 Gigabit Ethernet Adapter (1000-SX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_1014_0119[] = "Netfinity Gigabit Ethernet SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1000_8086_1000[] = "PRO/1000 Gigabit Server Adapter"; +#endif +static const char pci_device_8086_1001[] = "82543GC Gigabit Ethernet Controller (Fiber)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1001_0e11_004a[] = "NC6136 Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1001_1014_01ea[] = "Netfinity Gigabit Ethernet SX Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1001_8086_1002[] = "PRO/1000 F Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1001_8086_1003[] = "PRO/1000 F Server Adapter"; +#endif +static const char pci_device_8086_1002[] = "Pro 100 LAN+Modem 56 Cardbus II"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1002_8086_200e[] = "Pro 100 LAN+Modem 56 Cardbus II"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1002_8086_2013[] = "Pro 100 SR Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1002_8086_2017[] = "Pro 100 S Combo Mobile Adapter"; +#endif +static const char pci_device_8086_1004[] = "82543GC Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_0e11_0049[] = "NC7132 Gigabit Upgrade Module"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_0e11_b1a4[] = "NC7131 Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_1014_10f2[] = "Gigabit Ethernet Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_8086_1004[] = "PRO/1000 T Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1004_8086_2004[] = "PRO/1000 T Server Adapter"; +#endif +static const char pci_device_8086_1008[] = "82544EI Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_1014_0269[] = "iSeries 1000/100/10 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_1028_011c[] = "PRO/1000 XT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_8086_1107[] = "PRO/1000 XT Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_8086_2107[] = "PRO/1000 XT Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_8086_2110[] = "PRO/1000 XT Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1008_8086_3108[] = "PRO/1000 XT Network Connection"; +#endif +static const char pci_device_8086_1009[] = "82544EI Gigabit Ethernet Controller (Fiber)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1009_1014_0268[] = "iSeries Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1009_8086_1109[] = "PRO/1000 XF Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1009_8086_2109[] = "PRO/1000 XF Server Adapter"; +#endif +static const char pci_device_8086_100a[] = "82540EM Gigabit Ethernet Controller"; +static const char pci_device_8086_100c[] = "82544GC Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100c_8086_1112[] = "PRO/1000 T Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100c_8086_2112[] = "PRO/1000 T Desktop Adapter"; +#endif +static const char pci_device_8086_100d[] = "82544GC Gigabit Ethernet Controller (LOM)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100d_1028_0123[] = "PRO/1000 XT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100d_1079_891f[] = "82544GC Based Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100d_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100d_8086_110d[] = "82544GC Based Network Connection"; +#endif +static const char pci_device_8086_100e[] = "82540EM Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1014_0265[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1014_0267[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1014_026a[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1028_002e[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1028_0134[] = "PowerEdge 600SC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_1028_0151[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_107b_8920[] = "PRO/1000 MT Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_8086_001e[] = "PRO/1000 MT Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_8086_002e[] = "PRO/1000 MT Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_8086_1376[] = "PRO/1000 GT Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100e_8086_1476[] = "PRO/1000 GT Desktop Adapter"; +#endif +static const char pci_device_8086_100f[] = "82545EM Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100f_1014_0269[] = "iSeries 1000/100/10 Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100f_1014_028e[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100f_8086_1000[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_100f_8086_1001[] = "PRO/1000 MT Server Adapter"; +#endif +static const char pci_device_8086_1010[] = "82546EB Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_0e11_00db[] = "NC7170 Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_1014_027c[] = "PRO/1000 MT Dual Port Network Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_18fb_7872[] = "RESlink-X"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_1fc1_0026[] = "Niagara 2260 Bypass Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_4c53_10a0[] = "CA3/CR3 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_8086_1011[] = "PRO/1000 MT Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_8086_1012[] = "PRO/1000 MT Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_8086_101a[] = "PRO/1000 MT Dual Port Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1010_8086_3424[] = "SE7501HG2 Mainboard"; +#endif +static const char pci_device_8086_1011[] = "82545EM Gigabit Ethernet Controller (Fiber)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1011_1014_0268[] = "iSeries Gigabit Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1011_8086_1002[] = "PRO/1000 MF Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1011_8086_1003[] = "PRO/1000 MF Server Adapter (LX)"; +#endif +static const char pci_device_8086_1012[] = "82546EB Gigabit Ethernet Controller (Fiber)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1012_0e11_00dc[] = "NC6170 Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1012_8086_1012[] = "PRO/1000 MF Dual Port Server Adapter"; +#endif +static const char pci_device_8086_1013[] = "82541EI Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1013_8086_0013[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1013_8086_1013[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1013_8086_1113[] = "PRO/1000 MT Desktop Adapter"; +#endif +static const char pci_device_8086_1014[] = "82541ER Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1014_8086_0014[] = "PRO/1000 MT Desktop Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1014_8086_1014[] = "PRO/1000 MT Network Connection"; +#endif +static const char pci_device_8086_1015[] = "82540EM Gigabit Ethernet Controller (LOM)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1015_8086_1015[] = "PRO/1000 MT Mobile Connection"; +#endif +static const char pci_device_8086_1016[] = "82540EP Gigabit Ethernet Controller (Mobile)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1016_1014_052c[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1016_1179_0001[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1016_8086_1016[] = "PRO/1000 MT Mobile Connection"; +#endif +static const char pci_device_8086_1017[] = "82540EP Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1017_8086_1017[] = "PR0/1000 MT Desktop Connection"; +#endif +static const char pci_device_8086_1018[] = "82541EI Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1018_8086_1018[] = "PRO/1000 MT Mobile Connection"; +#endif +static const char pci_device_8086_1019[] = "82547EI Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1019_1458_1019[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1019_1458_e000[] = "Intel Gigabit Ethernet (Kenai II)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1019_8086_1019[] = "PRO/1000 CT Desktop Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1019_8086_301f[] = "D865PERL mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1019_8086_302c[] = "Intel 82865G Mainboard (D865GBF)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1019_8086_3427[] = "S875WP1-E mainboard"; +#endif +static const char pci_device_8086_101a[] = "82547EI Gigabit Ethernet Controller (Mobile)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_101a_8086_101a[] = "PRO/1000 CT Mobile Connection"; +#endif +static const char pci_device_8086_101d[] = "82546EB Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_101d_8086_1000[] = "PRO/1000 MT Quad Port Server Adapter"; +#endif +static const char pci_device_8086_101e[] = "82540EP Gigabit Ethernet Controller (Mobile)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_101e_1014_0549[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_101e_1179_0001[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_101e_8086_101e[] = "PRO/1000 MT Mobile Connection"; +#endif +static const char pci_device_8086_1026[] = "82545GM Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1026_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1026_8086_1000[] = "PRO/1000 MT Server Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1026_8086_1001[] = "PRO/1000 MT Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1026_8086_1002[] = "PRO/1000 MT Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1026_8086_1003[] = "PRO/1000 GT Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1026_8086_1026[] = "PRO/1000 MT Server Connection"; +#endif +static const char pci_device_8086_1027[] = "82545GM Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1027_103c_3103[] = "NC310F PCI-X Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1027_8086_1001[] = "PRO/1000 MF Server Adapter(LX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1027_8086_1002[] = "PRO/1000 MF Server Adapter(LX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1027_8086_1003[] = "PRO/1000 MF Server Adapter(LX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1027_8086_1027[] = "PRO/1000 MF Server Adapter"; +#endif +static const char pci_device_8086_1028[] = "82545GM Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1028_8086_1028[] = "PRO/1000 MB Server Connection"; +#endif +static const char pci_device_8086_1029[] = "82559 Ethernet Controller"; +static const char pci_device_8086_1030[] = "82559 InBusiness 10/100"; +static const char pci_device_8086_1031[] = "82801CAM (ICH3) PRO/100 VE (LOM) Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_1014_0209[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_104d_80e7[] = "Vaio PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_104d_813c[] = "Vaio PCG-GRV616G"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_107b_5350[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_1179_0001[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_144d_c000[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_144d_c001[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_144d_c003[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1031_144d_c006[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_8086_1032[] = "82801CAM (ICH3) PRO/100 VE Ethernet Controller"; +static const char pci_device_8086_1033[] = "82801CAM (ICH3) PRO/100 VM (LOM) Ethernet Controller"; +static const char pci_device_8086_1034[] = "82801CAM (ICH3) PRO/100 VM Ethernet Controller"; +static const char pci_device_8086_1035[] = "82801CAM (ICH3)/82562EH (LOM) Ethernet Controller"; +static const char pci_device_8086_1036[] = "82801CAM (ICH3) 82562EH Ethernet Controller"; +static const char pci_device_8086_1037[] = "82801CAM (ICH3) Chipset Ethernet Controller"; +static const char pci_device_8086_1038[] = "82801CAM (ICH3) PRO/100 VM (KM) Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1038_0e11_0098[] = "Evo N600c"; +#endif +static const char pci_device_8086_1039[] = "82801DB PRO/100 VE (LOM) Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1039_1014_0267[] = "NetVista A30p"; +#endif +static const char pci_device_8086_103a[] = "82801DB PRO/100 VE (CNR) Ethernet Controller"; +static const char pci_device_8086_103b[] = "82801DB PRO/100 VM (LOM) Ethernet Controller"; +static const char pci_device_8086_103c[] = "82801DB PRO/100 VM (CNR) Ethernet Controller"; +static const char pci_device_8086_103d[] = "82801DB PRO/100 VE (MOB) Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_103d_1014_0522[] = "Thinkpad R50e model 1634"; +#endif +static const char pci_device_8086_103e[] = "82801DB PRO/100 VM (MOB) Ethernet Controller"; +static const char pci_device_8086_1040[] = "536EP Data Fax Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1040_16be_1040[] = "V.9X DSP Data Fax Modem"; +#endif +static const char pci_device_8086_1043[] = "PRO/Wireless LAN 2100 3B Mini PCI Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1043_103c_08b0[] = "tc1100 tablet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1043_8086_2527[] = "MIM2000/Centrino"; +#endif +static const char pci_device_8086_1048[] = "PRO/10GbE LR Server Adapter"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1048_8086_a01f[] = "PRO/10GbE LR Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1048_8086_a11f[] = "PRO/10GbE LR Server Adapter"; +#endif +static const char pci_device_8086_1049[] = "82566MM Gigabit Network Connection"; +static const char pci_device_8086_104a[] = "82566DM Gigabit Network Connection"; +static const char pci_device_8086_104b[] = "82566DC Gigabit Network Connection"; +static const char pci_device_8086_104c[] = "82562V 10/100 Network Connection"; +static const char pci_device_8086_104d[] = "82566MC Gigabit Network Connection"; +static const char pci_device_8086_1050[] = "82562EZ 10/100 Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1050_1462_728c[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1050_1462_758c[] = "MS-6758 (875P Neo)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1050_8086_3020[] = "D865PERL mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1050_8086_302f[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1050_8086_3427[] = "S875WP1-E mainboard"; +#endif +static const char pci_device_8086_1051[] = "82801EB/ER (ICH5/ICH5R) integrated LAN Controller"; +static const char pci_device_8086_1052[] = "PRO/100 VM Network Connection"; +static const char pci_device_8086_1053[] = "PRO/100 VM Network Connection"; +static const char pci_device_8086_1059[] = "82551QM Ethernet Controller"; +static const char pci_device_8086_105b[] = "82546GB Gigabit Ethernet Controller (Copper)"; +static const char pci_device_8086_105e[] = "82571EB Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_105e_103c_7044[] = "NC360T PCI Express Dual Port Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_105e_1775_6003[] = "Telum GE-QT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_105e_8086_005e[] = "PRO/1000 PT Dual Port Server Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_105e_8086_105e[] = "PRO/1000 PT Dual Port Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_105e_8086_115e[] = "PRO/1000 PT Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_105e_8086_116e[] = "PRO/1000 PT Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_105e_8086_125e[] = "PRO/1000 PT Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_105e_8086_135e[] = "PRO/1000 PT Dual Port Server Adapter"; +#endif +static const char pci_device_8086_105f[] = "82571EB Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_105f_8086_115f[] = "PRO/1000 PF Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_105f_8086_116f[] = "PRO/1000 PF Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_105f_8086_125f[] = "PRO/1000 PF Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_105f_8086_135f[] = "PRO/1000 PF Dual Port Server Adapter"; +#endif +static const char pci_device_8086_1060[] = "82571EB Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1060_8086_0060[] = "PRO/1000 PB Dual Port Server Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1060_8086_1060[] = "PRO/1000 PB Dual Port Server Connection"; +#endif +static const char pci_device_8086_1064[] = "82562ET/EZ/GT/GZ - PRO/100 VE (LOM) Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1064_1043_80f8[] = "P5GD1-VW Mainboard"; +#endif +static const char pci_device_8086_1065[] = "82562ET/EZ/GT/GZ - PRO/100 VE Ethernet Controller"; +static const char pci_device_8086_1066[] = "82562 EM/EX/GX - PRO/100 VM (LOM) Ethernet Controller"; +static const char pci_device_8086_1067[] = "82562 EM/EX/GX - PRO/100 VM Ethernet Controller"; +static const char pci_device_8086_1068[] = "82562ET/EZ/GT/GZ - PRO/100 VE (LOM) Ethernet Controller Mobile"; +static const char pci_device_8086_1069[] = "82562EM/EX/GX - PRO/100 VM (LOM) Ethernet Controller Mobile"; +static const char pci_device_8086_106a[] = "82562G - PRO/100 VE (LOM) Ethernet Controller"; +static const char pci_device_8086_106b[] = "82562G - PRO/100 VE Ethernet Controller Mobile"; +static const char pci_device_8086_1075[] = "82547GI Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1075_1028_0165[] = "PowerEdge 750"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1075_8086_0075[] = "PRO/1000 CT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1075_8086_1075[] = "PRO/1000 CT Network Connection"; +#endif +static const char pci_device_8086_1076[] = "82541GI Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_1028_0165[] = "PowerEdge 750"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_8086_0076[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_8086_1076[] = "PRO/1000 MT Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_8086_1176[] = "PRO/1000 MT Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1076_8086_1276[] = "PRO/1000 MT Network Adapter"; +#endif +static const char pci_device_8086_1077[] = "82541GI Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1077_1179_0001[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1077_8086_0077[] = "PRO/1000 MT Mobile Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1077_8086_1077[] = "PRO/1000 MT Mobile Connection"; +#endif +static const char pci_device_8086_1078[] = "82541ER Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1078_8086_1078[] = "82541ER-based Network Connection"; +#endif +static const char pci_device_8086_1079[] = "82546GB Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_103c_12a6[] = "Dual Port 1000Base-T [A9900A]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_103c_12cf[] = "Core Dual Port 1000Base-T [AB352A]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_1775_10d0[] = "V5D Single Board Computer Gigabit Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_1775_ce90[] = "CE9"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_1fc1_0027[] = "Niagara 2261 Failover NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_8086_0079[] = "PRO/1000 MT Dual Port Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_8086_1079[] = "PRO/1000 MT Dual Port Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_8086_1179[] = "PRO/1000 MT Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1079_8086_117a[] = "PRO/1000 MT Dual Port Server Adapter"; +#endif +static const char pci_device_8086_107a[] = "82546GB Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107a_103c_12a8[] = "Dual Port 1000base-SX [A9899A]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107a_8086_107a[] = "PRO/1000 MF Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107a_8086_127a[] = "PRO/1000 MF Dual Port Server Adapter"; +#endif +static const char pci_device_8086_107b[] = "82546GB Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107b_8086_007b[] = "PRO/1000 MB Dual Port Server Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107b_8086_107b[] = "PRO/1000 MB Dual Port Server Connection"; +#endif +static const char pci_device_8086_107c[] = "82541PI Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107c_8086_1376[] = "PRO/1000 GT Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107c_8086_1476[] = "PRO/1000 GT Desktop Adapter"; +#endif +static const char pci_device_8086_107d[] = "82572EI Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107d_8086_1082[] = "PRO/1000 PT Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107d_8086_1092[] = "PRO/1000 PT Server Adapter"; +#endif +static const char pci_device_8086_107e[] = "82572EI Gigabit Ethernet Controller (Fiber)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107e_8086_1084[] = "PRO/1000 PF Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_107e_8086_1094[] = "PRO/1000 PF Server Adapter"; +#endif +static const char pci_device_8086_107f[] = "82572EI Gigabit Ethernet Controller"; +static const char pci_device_8086_1080[] = "FA82537EP 56K V.92 Data/Fax Modem PCI"; +static const char pci_device_8086_1081[] = "631xESB/632xESB LAN Controller Copper"; +static const char pci_device_8086_1082[] = "631xESB/632xESB LAN Controller fiber"; +static const char pci_device_8086_1083[] = "631xESB/632xESB LAN Controller SERDES"; +static const char pci_device_8086_1084[] = "631xESB/632xESB IDE Redirection"; +static const char pci_device_8086_1085[] = "631xESB/632xESB Serial Port Redirection"; +static const char pci_device_8086_1086[] = "631xESB/632xESB IPMI/KCS0"; +static const char pci_device_8086_1087[] = "631xESB/632xESB UHCI Redirection"; +static const char pci_device_8086_1089[] = "631xESB/632xESB BT"; +static const char pci_device_8086_108a[] = "82546GB Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_108a_8086_108a[] = "PRO/1000 P Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_108a_8086_118a[] = "PRO/1000 P Dual Port Server Adapter"; +#endif +static const char pci_device_8086_108b[] = "82573V Gigabit Ethernet Controller (Copper)"; +static const char pci_device_8086_108c[] = "82573E Gigabit Ethernet Controller (Copper)"; +static const char pci_device_8086_108e[] = "82573E KCS (Active Management)"; +static const char pci_device_8086_108f[] = "Active Management Technology - SOL"; +static const char pci_device_8086_1092[] = "PRO/100 VE Network Connection"; +static const char pci_device_8086_1096[] = "80003ES2LAN Gigabit Ethernet Controller (Copper)"; +static const char pci_device_8086_1097[] = "631xESB/632xESB DPT LAN Controller (Fiber)"; +static const char pci_device_8086_1098[] = "80003ES2LAN Gigabit Ethernet Controller (Serdes)"; +static const char pci_device_8086_1099[] = "82546GB Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1099_8086_1099[] = "PRO/1000 GT Quad Port Server Adapter"; +#endif +static const char pci_device_8086_109a[] = "82573L Gigabit Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_109a_17aa_2001[] = "ThinkPad T60"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_109a_17aa_207e[] = "Thinkpad X60s"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_109a_8086_109a[] = "PRO/1000 PL Network Connection"; +#endif +static const char pci_device_8086_109b[] = "82546GB PRO/1000 GF Quad Port Server Adapter"; +static const char pci_device_8086_10a0[] = "82571EB PRO/1000 AT Quad Port Bypass Adapter"; +static const char pci_device_8086_10a1[] = "82571EB PRO/1000 AF Quad Port Bypass Adapter"; +static const char pci_device_8086_10b0[] = "82573L PRO/1000 PL Network Connection"; +static const char pci_device_8086_10b2[] = "82573V PRO/1000 PM Network Connection"; +static const char pci_device_8086_10b3[] = "82573E PRO/1000 PM Network Connection"; +static const char pci_device_8086_10b4[] = "82573L PRO/1000 PL Network Connection"; +static const char pci_device_8086_10b5[] = "82546GB Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_10b5_103c_3109[] = "NC340T PCI-X Quad-port Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_10b5_8086_1099[] = "PRO/1000 GT Quad Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_10b5_8086_1199[] = "PRO/1000 GT Quad Port Server Adapter"; +#endif +static const char pci_device_8086_10b9[] = "82572EI Gigabit Ethernet Controller (Copper)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_10b9_8086_1083[] = "PRO/1000 PT Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_10b9_8086_1093[] = "PRO/1000 PT Desktop Adapter"; +#endif +static const char pci_device_8086_10ba[] = "80003ES2LAN Gigabit Ethernet Controller (Copper)"; +static const char pci_device_8086_10bb[] = "80003ES2LAN Gigabit Ethernet Controller (Serdes)"; +static const char pci_device_8086_1107[] = "PRO/1000 MF Server Adapter (LX)"; +static const char pci_device_8086_1130[] = "82815 815 Chipset Host Bridge and Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1130_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1130_1043_8027[] = "TUSL2-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1130_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1130_8086_4532[] = "D815EEA2 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1130_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_1131[] = "82815 815 Chipset AGP Bridge"; +static const char pci_device_8086_1132[] = "82815 CGC [Chipset Graphics Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1132_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1132_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1132_8086_4532[] = "D815EEA2 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1132_8086_4541[] = "D815EEA Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1132_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_1161[] = "82806AA PCI64 Hub Advanced Programmable Interrupt Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1161_8086_1161[] = "82806AA PCI64 Hub APIC"; +#endif +static const char pci_device_8086_1162[] = "Xscale 80200 Big Endian Companion Chip"; +static const char pci_device_8086_1200[] = "IXP1200 Network Processor"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1200_172a_0000[] = "AEP SSL Accelerator"; +#endif +static const char pci_device_8086_1209[] = "8255xER/82551IT Fast Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1209_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1209_4c53_1051[] = "CE7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1209_4c53_1070[] = "PC6 mainboard"; +#endif +static const char pci_device_8086_1221[] = "82092AA PCI to PCMCIA Bridge"; +static const char pci_device_8086_1222[] = "82092AA IDE Controller"; +static const char pci_device_8086_1223[] = "SAA7116"; +static const char pci_device_8086_1225[] = "82452KX/GX [Orion]"; +static const char pci_device_8086_1226[] = "82596 PRO/10 PCI"; +static const char pci_device_8086_1227[] = "82865 EtherExpress PRO/100A"; +static const char pci_device_8086_1228[] = "82556 EtherExpress PRO/100 Smart"; +static const char pci_device_8086_1229[] = "82557/8/9 [Ethernet Pro 100]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3001[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3002[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3003[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3004[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3005[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3006[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_3007[] = "82559 Fast Ethernet LOM with Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b01e[] = "NC3120 Fast Ethernet NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b01f[] = "NC3122 Fast Ethernet NIC (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b02f[] = "NC1120 Ethernet NIC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b04a[] = "Netelligent 10/100TX NIC with Wake on LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0c6[] = "NC3161 Fast Ethernet NIC (embedded, WOL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0c7[] = "NC3160 Fast Ethernet NIC (embedded)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0d7[] = "NC3121 Fast Ethernet NIC (WOL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0dd[] = "NC3131 Fast Ethernet NIC (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0de[] = "NC3132 Fast Ethernet Module (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b0e1[] = "NC3133 Fast Ethernet Module (100-FX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b134[] = "NC3163 Fast Ethernet NIC (embedded, WOL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b13c[] = "NC3162 Fast Ethernet NIC (embedded)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b144[] = "NC3123 Fast Ethernet NIC (WOL)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b163[] = "NC3134 Fast Ethernet NIC (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b164[] = "NC3135 Fast Ethernet Upgrade Module (dual port)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_0e11_b1a4[] = "NC7131 Gigabit Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_005c[] = "82558B Ethernet Pro 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_01bc[] = "82559 Fast Ethernet LAN On Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_01f1[] = "10/100 Ethernet Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_01f2[] = "10/100 Ethernet Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_0207[] = "Ethernet Pro/100 S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_0232[] = "10/100 Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_023a[] = "ThinkPad R30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_105c[] = "Netfinity 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_2205[] = "ThinkPad A22p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_305c[] = "10/100 EtherJet Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_405c[] = "10/100 EtherJet Adapter with Alert on LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_505c[] = "10/100 EtherJet Secure Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_605c[] = "10/100 EtherJet Secure Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_705c[] = "10/100 Netfinity 10/100 Ethernet Security Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1014_805c[] = "10/100 Netfinity 10/100 Ethernet Security Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1028_009b[] = "PowerEdge 2500/2550"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1028_00ce[] = "PowerEdge 1400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8000[] = "PC-9821X-B06"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8016[] = "PK-UG-X006"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_801f[] = "PK-UG-X006"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8026[] = "PK-UG-X006"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8063[] = "82559-based Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1033_8064[] = "82559-based Fast Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10c0[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10c3[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10ca[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10cb[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10e3[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_10e4[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_103c_1200[] = "NetServer 10/100TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_108e_10cf[] = "EtherExpress PRO/100(B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_10c3_1100[] = "SmartEther100 SC1100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_10cf_1115[] = "8255x-based Ethernet Adapter (10/100)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_10cf_1143[] = "8255x-based Ethernet Adapter (10/100)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_110a_008b[] = "82551QM Fast Ethernet Multifuction PCI/CardBus Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1179_0001[] = "8255x-based Ethernet Adapter (10/100)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1179_0002[] = "PCI FastEther LAN on Docker"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1179_0003[] = "8255x-based Fast Ethernet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1259_2560[] = "AT-2560 100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1259_2561[] = "AT-2560 100 FX Ethernet Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1266_0001[] = "NE10/100 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_13e9_1000[] = "6221L-4U"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_144d_2501[] = "SEM-2000 MiniPCI LAN Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_144d_2502[] = "SEM-2100IL MiniPCI LAN Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1668_1100[] = "EtherExpress PRO/100B (TX) (MiniPCI Ethernet+Modem)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_1775_ce90[] = "CE9"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_4c53_1080[] = "CT8 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_4c53_10e0[] = "PSL09 PrPMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0001[] = "EtherExpress PRO/100B (TX)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0002[] = "EtherExpress PRO/100B (T4)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0003[] = "EtherExpress PRO/10+"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0004[] = "EtherExpress PRO/100 WfM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0005[] = "82557 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0006[] = "82557 10/100 with Wake on LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0007[] = "82558 10/100 Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0008[] = "82558 10/100 with Wake on LAN"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000a[] = "EtherExpress PRO/100+ Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000b[] = "EtherExpress PRO/100+"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000c[] = "EtherExpress PRO/100+ Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000d[] = "EtherExpress PRO/100+ Alert On LAN II* Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000e[] = "EtherExpress PRO/100+ Management Adapter with Alert On LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_000f[] = "EtherExpress PRO/100 Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0010[] = "EtherExpress PRO/100 S Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0011[] = "EtherExpress PRO/100 S Management Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0012[] = "EtherExpress PRO/100 S Advanced Management Adapter (D)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0013[] = "EtherExpress PRO/100 S Advanced Management Adapter (E)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0030[] = "EtherExpress PRO/100 Management Adapter with Alert On LAN* GC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0031[] = "EtherExpress PRO/100 Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0040[] = "EtherExpress PRO/100 S Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0041[] = "EtherExpress PRO/100 S Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0042[] = "EtherExpress PRO/100 Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_0050[] = "EtherExpress PRO/100 S Desktop Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1009[] = "EtherExpress PRO/100+ Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_100c[] = "EtherExpress PRO/100+ Server Adapter (PILA8470B)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1012[] = "EtherExpress PRO/100 S Server Adapter (D)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1013[] = "EtherExpress PRO/100 S Server Adapter (E)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1015[] = "EtherExpress PRO/100 S Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1017[] = "EtherExpress PRO/100+ Dual Port Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1030[] = "EtherExpress PRO/100+ Management Adapter with Alert On LAN* G Server"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1040[] = "EtherExpress PRO/100 S Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1041[] = "EtherExpress PRO/100 S Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1042[] = "EtherExpress PRO/100 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1050[] = "EtherExpress PRO/100 S Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1051[] = "EtherExpress PRO/100 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_1052[] = "EtherExpress PRO/100 Server Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_10f0[] = "EtherExpress PRO/100+ Dual Port Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2009[] = "EtherExpress PRO/100 S Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_200d[] = "EtherExpress PRO/100 Cardbus"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_200e[] = "EtherExpress PRO/100 LAN+V90 Cardbus Modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_200f[] = "EtherExpress PRO/100 SR Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2010[] = "EtherExpress PRO/100 S Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2013[] = "EtherExpress PRO/100 SR Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2016[] = "EtherExpress PRO/100 S Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2017[] = "EtherExpress PRO/100 S Combo Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2018[] = "EtherExpress PRO/100 SR Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2019[] = "EtherExpress PRO/100 SR Combo Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2101[] = "EtherExpress PRO/100 P Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2102[] = "EtherExpress PRO/100 SP Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2103[] = "EtherExpress PRO/100 SP Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2104[] = "EtherExpress PRO/100 SP Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2105[] = "EtherExpress PRO/100 SP Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2106[] = "EtherExpress PRO/100 P Mobile Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2107[] = "EtherExpress PRO/100 Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2108[] = "EtherExpress PRO/100 Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2200[] = "EtherExpress PRO/100 P Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2201[] = "EtherExpress PRO/100 P Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2202[] = "EtherExpress PRO/100 SP Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2203[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2204[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2205[] = "EtherExpress PRO/100 SP Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2206[] = "EtherExpress PRO/100 SP Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2207[] = "EtherExpress PRO/100 SP Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2208[] = "EtherExpress PRO/100 P Mobile Combo Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2402[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2407[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2408[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2409[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_240f[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2410[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2411[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2412[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_2413[] = "EtherExpress PRO/100+ MiniPCI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3000[] = "82559 Fast Ethernet LAN on Motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3001[] = "82559 Fast Ethernet LOM with Basic Alert on LAN*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3002[] = "82559 Fast Ethernet LOM with Alert on LAN II*"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3006[] = "EtherExpress PRO/100 S Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3007[] = "EtherExpress PRO/100 S Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3008[] = "EtherExpress PRO/100 Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3010[] = "EtherExpress PRO/100 S Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3011[] = "EtherExpress PRO/100 S Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3012[] = "EtherExpress PRO/100 Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1229_8086_3411[] = "SDS2 Mainboard"; +#endif +static const char pci_device_8086_122d[] = "430FX - 82437FX TSC [Triton I]"; +static const char pci_device_8086_122e[] = "82371FB PIIX ISA [Triton I]"; +static const char pci_device_8086_1230[] = "82371FB PIIX IDE [Triton I]"; +static const char pci_device_8086_1231[] = "DSVD Modem"; +static const char pci_device_8086_1234[] = "430MX - 82371MX Mobile PCI I/O IDE Xcelerator (MPIIX)"; +static const char pci_device_8086_1235[] = "430MX - 82437MX Mob. System Ctrlr (MTSC) & 82438MX Data Path (MTDP)"; +static const char pci_device_8086_1237[] = "440FX - 82441FX PMC [Natoma]"; +static const char pci_device_8086_1239[] = "82371FB PIIX IDE Interface"; +static const char pci_device_8086_123b[] = "82380PB PCI to PCI Docking Bridge"; +static const char pci_device_8086_123c[] = "82380AB (MISA) Mobile PCI-to-ISA Bridge"; +static const char pci_device_8086_123d[] = "683053 Programmable Interrupt Device"; +static const char pci_device_8086_123e[] = "82466GX (IHPC) Integrated Hot-Plug Controller (hidden mode)"; +static const char pci_device_8086_123f[] = "82466GX Integrated Hot-Plug Controller (IHPC)"; +static const char pci_device_8086_1240[] = "82752 (752) AGP Graphics Accelerator"; +static const char pci_device_8086_124b[] = "82380FB (MPCI2) Mobile Docking Controller"; +static const char pci_device_8086_1250[] = "430HX - 82439HX TXC [Triton II]"; +static const char pci_device_8086_1360[] = "82806AA PCI64 Hub PCI Bridge"; +static const char pci_device_8086_1361[] = "82806AA PCI64 Hub Controller (HRes)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1361_8086_1361[] = "82806AA PCI64 Hub Controller (HRes)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1361_8086_8000[] = "82806AA PCI64 Hub Controller (HRes)"; +#endif +static const char pci_device_8086_1460[] = "82870P2 P64H2 Hub PCI Bridge"; +static const char pci_device_8086_1461[] = "82870P2 P64H2 I/OxAPIC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1461_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1461_4c53_1090[] = "Cx9/Vx9 mainboard"; +#endif +static const char pci_device_8086_1462[] = "82870P2 P64H2 Hot Plug Controller"; +static const char pci_device_8086_1960[] = "80960RP [i960RP Microprocessor]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0431[] = "MegaRAID 431 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0438[] = "MegaRAID 438 Ultra2 LVD RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0466[] = "MegaRAID 466 Express Plus RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0467[] = "MegaRAID 467 Enterprise 1500 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0490[] = "MegaRAID 490 Express 300 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_0762[] = "MegaRAID 762 Express RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_101e_09a0[] = "PowerEdge Expandable RAID Controller 2/SC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_1028_0467[] = "PowerEdge Expandable RAID Controller 2/DC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_1028_1111[] = "PowerEdge Expandable RAID Controller 2/SC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_03a2[] = "MegaRAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_10c6[] = "MegaRAID 438, NetRAID-3Si"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_10c7[] = "MegaRAID T5, Integrated NetRAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_10cc[] = "MegaRAID, Integrated NetRAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_103c_10cd[] = "NetRAID-1Si"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_105a_0000[] = "SuperTrak"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_105a_2168[] = "SuperTrak Pro"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_105a_5168[] = "SuperTrak66/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_1111_1111[] = "MegaRAID 466, PowerEdge Expandable RAID Controller 2/SC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_1111_1112[] = "PowerEdge Expandable RAID Controller 2/SC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_113c_03a2[] = "MegaRAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_e4bf_1010[] = "CG1-RADIO"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_e4bf_1020[] = "CU2-QUARTET"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_e4bf_1040[] = "CU1-CHORUS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1960_e4bf_3100[] = "CX1-BAND"; +#endif +static const char pci_device_8086_1962[] = "80960RM [i960RM Microprocessor]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1962_105a_0000[] = "SuperTrak SX6000 I2O CPU"; +#endif +static const char pci_device_8086_1a21[] = "82840 840 (Carmel) Chipset Host Bridge (Hub A)"; +static const char pci_device_8086_1a23[] = "82840 840 (Carmel) Chipset AGP Bridge"; +static const char pci_device_8086_1a24[] = "82840 840 (Carmel) Chipset PCI Bridge (Hub B)"; +static const char pci_device_8086_1a30[] = "82845 845 (Brookdale) Chipset Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_1a30_1028_010e[] = "Optiplex GX240"; +#endif +static const char pci_device_8086_1a31[] = "82845 845 (Brookdale) Chipset AGP Bridge"; +static const char pci_device_8086_1a38[] = "5000 Series Chipset DMA Engine"; +static const char pci_device_8086_1a48[] = "PRO/10GbE SR Server Adapter"; +static const char pci_device_8086_2410[] = "82801AA ISA Bridge (LPC)"; +static const char pci_device_8086_2411[] = "82801AA IDE"; +static const char pci_device_8086_2412[] = "82801AA USB"; +static const char pci_device_8086_2413[] = "82801AA SMBus"; +static const char pci_device_8086_2415[] = "82801AA AC'97 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_1028_0095[] = "Precision Workstation 220 Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_110a_0051[] = "Activy 2xx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_11d4_0040[] = "SoundMAX Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_11d4_0048[] = "SoundMAX Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_11d4_5340[] = "SoundMAX Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2415_1734_1025[] = "Activy 3xx"; +#endif +static const char pci_device_8086_2416[] = "82801AA AC'97 Modem"; +static const char pci_device_8086_2418[] = "82801AA PCI Bridge"; +static const char pci_device_8086_2420[] = "82801AB ISA Bridge (LPC)"; +static const char pci_device_8086_2421[] = "82801AB IDE"; +static const char pci_device_8086_2422[] = "82801AB USB"; +static const char pci_device_8086_2423[] = "82801AB SMBus"; +static const char pci_device_8086_2425[] = "82801AB AC'97 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2425_11d4_0040[] = "SoundMAX Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2425_11d4_0048[] = "SoundMAX Integrated Digital Audio"; +#endif +static const char pci_device_8086_2426[] = "82801AB AC'97 Modem"; +static const char pci_device_8086_2428[] = "82801AB PCI Bridge"; +static const char pci_device_8086_2440[] = "82801BA ISA Bridge (LPC)"; +static const char pci_device_8086_2442[] = "82801BA/BAM USB (Hub #1)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_1014_01c6[] = "Netvista A40/A40p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_1028_00c7[] = "Dimension 8100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_1028_010e[] = "Optiplex GX240"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_1043_8027[] = "TUSL2-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_147b_0507[] = "TH7II-RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_8086_4532[] = "D815EEA2 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2442_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_2443[] = "82801BA/BAM SMBus"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_1014_01c6[] = "Netvista A40/A40p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_1028_00c7[] = "Dimension 8100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_1028_010e[] = "Optiplex GX240"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_1043_8027[] = "TUSL2-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_147b_0507[] = "TH7II-RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_8086_4532[] = "D815EEA2 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2443_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_2444[] = "82801BA/BAM USB (Hub #2)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_1028_00c7[] = "Dimension 8100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_1028_010e[] = "Optiplex GX240"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_1043_8027[] = "TUSL2-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_147b_0507[] = "TH7II-RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2444_8086_4532[] = "D815EEA2 mainboard"; +#endif +static const char pci_device_8086_2445[] = "82801BA/BAM AC'97 Audio"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_0e11_0088[] = "Evo D500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_1014_01c6[] = "Netvista A40/A40p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_104d_80df[] = "Vaio PCG-FX403"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_1462_3370[] = "STAC9721 AC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_147b_0507[] = "TH7II-RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2445_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_2446[] = "82801BA/BAM AC'97 Modem"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2446_1025_1016[] = "Travelmate 612 TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2446_104d_80df[] = "Vaio PCG-FX403"; +#endif +static const char pci_device_8086_2448[] = "82801 Mobile PCI Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2448_103c_099c[] = "NX6110/NC6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2448_1734_1055[] = "Amilo M1420"; +#endif +static const char pci_device_8086_2449[] = "82801BA/BAM/CA/CAM Ethernet Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_0e11_0012[] = "EtherExpress PRO/100 VM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_0e11_0091[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_01ce[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_01dc[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_01eb[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_01ec[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0202[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0205[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0217[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0234[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_023d[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0244[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0245[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0265[] = "PRO/100 VE Desktop Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_0267[] = "PRO/100 VE Desktop Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1014_026a[] = "PRO/100 VE Desktop Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_109f_315d[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_109f_3181[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1179_ff01[] = "PRO/100 VE Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_1186_7801[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_144d_2602[] = "HomePNA 1M CNR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3010[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3011[] = "EtherExpress PRO/100 VM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3012[] = "82562EH based Phoneline"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3013[] = "EtherExpress PRO/100 VE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3014[] = "EtherExpress PRO/100 VM"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3015[] = "82562EH based Phoneline"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3016[] = "EtherExpress PRO/100 P Mobile Combo"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3017[] = "EtherExpress PRO/100 P Mobile"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2449_8086_3018[] = "EtherExpress PRO/100"; +#endif +static const char pci_device_8086_244a[] = "82801BAM IDE U100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244a_1025_1016[] = "Travelmate 612TX"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244a_104d_80df[] = "Vaio PCG-FX403"; +#endif +static const char pci_device_8086_244b[] = "82801BA IDE U100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_1014_01c6[] = "Netvista A40/A40p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_1028_00c7[] = "Dimension 8100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_1028_010e[] = "Optiplex GX240"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_1043_8027[] = "TUSL2-C Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_147b_0507[] = "TH7II-RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_8086_4532[] = "D815EEA2 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244b_8086_4557[] = "D815EGEW Mainboard"; +#endif +static const char pci_device_8086_244c[] = "82801BAM ISA Bridge (LPC)"; +static const char pci_device_8086_244e[] = "82801 PCI Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_244e_1014_0267[] = "NetVista A30p"; +#endif +static const char pci_device_8086_2450[] = "82801E ISA Bridge (LPC)"; +static const char pci_device_8086_2452[] = "82801E USB"; +static const char pci_device_8086_2453[] = "82801E SMBus"; +static const char pci_device_8086_2459[] = "82801E Ethernet Controller 0"; +static const char pci_device_8086_245b[] = "82801E IDE U100"; +static const char pci_device_8086_245d[] = "82801E Ethernet Controller 1"; +static const char pci_device_8086_245e[] = "82801E PCI Bridge"; +static const char pci_device_8086_2480[] = "82801CA LPC Interface Controller"; +static const char pci_device_8086_2482[] = "82801CA/CAM USB (Hub #1)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_0e11_0030[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_8086_1958[] = "vpr Matrix 170B4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_8086_3424[] = "SE7501HG2 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2482_8086_4541[] = "Latitude C640"; +#endif +static const char pci_device_8086_2483[] = "82801CA/CAM SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2483_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2483_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2483_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2483_8086_1958[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_8086_2484[] = "82801CA/CAM USB (Hub #2)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2484_0e11_0030[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2484_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2484_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2484_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2484_8086_1958[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_8086_2485[] = "82801CA/CAM AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_1013_5959[] = "Crystal WMD Audio Codec"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_1014_0222[] = "ThinkPad T23 (2647-4MG) or A30/A30p (2652/2653)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_1014_0508[] = "ThinkPad T30"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_1014_051c[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2485_144d_c006[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_8086_2486[] = "82801CA/CAM AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_1014_0223[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_1014_0503[] = "ThinkPad R31 2656BBG"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_1014_051a[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_101f_1025[] = "620 Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_134d_4c21[] = "Dell Inspiron 2100 internal modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_144d_2115[] = "vpr Matrix 170B4 internal modem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2486_14f1_5421[] = "MD56ORD V.92 MDC Modem"; +#endif +static const char pci_device_8086_2487[] = "82801CA/CAM USB (Hub #3)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2487_0e11_0030[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2487_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2487_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2487_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2487_8086_1958[] = "vpr Matrix 170B4"; +#endif +static const char pci_device_8086_248a[] = "82801CAM IDE U100"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248a_0e11_0030[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248a_1014_0220[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248a_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248a_8086_1958[] = "vpr Matrix 170B4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248a_8086_4541[] = "Latitude C640"; +#endif +static const char pci_device_8086_248b[] = "82801CA Ultra ATA Storage Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_248b_15d9_3480[] = "P4DP6"; +#endif +static const char pci_device_8086_248c[] = "82801CAM ISA Bridge (LPC)"; +static const char pci_device_8086_24c0[] = "82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c0_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c0_1462_5800[] = "845PE Max (MS-6580)"; +#endif +static const char pci_device_8086_24c1[] = "82801DBL (ICH4-L) IDE Controller"; +static const char pci_device_8086_24c2[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1014_052d[] = "Thinkpad R50e model 1634"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_103c_088c[] = "NC8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_103c_0890[] = "NC6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_103c_08b0[] = "tc1100 tablet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1509_2990[] = "Averatec 5110H laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1734_1004[] = "D1451 Mainboard (SCENIC N300, i845GV)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c2_8086_4541[] = "Latitude D400"; +#endif +static const char pci_device_8086_24c3[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1014_052d[] = "Thinkpad R50e model 1634"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_103c_088c[] = "NC8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_103c_0890[] = "NC6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_103c_08b0[] = "tc1100 tablet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1458_24c2[] = "GA-8PE667 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1734_1004[] = "D1451 Mainboard (SCENIC N300, i845GV)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c3_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +static const char pci_device_8086_24c4[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1014_052d[] = "Thinkpad R50e model 1634"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_103c_088c[] = "NC8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_103c_0890[] = "NC6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_103c_08b0[] = "tc1100 tablet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1509_2990[] = "Averatec 5110H"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_1734_1004[] = "D1451 Mainboard (SCENIC N300, i845GV)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c4_8086_4541[] = "Latitude D400"; +#endif +static const char pci_device_8086_24c5[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_0e11_00b8[] = "Analog Devices Inc. codec [SoundMAX]"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1014_055f[] = "Thinkpad R50e model 1634"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_103c_088c[] = "NC8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_103c_0890[] = "NC6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_103c_08b0[] = "tc1100 tablet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1458_a002[] = "GA-8PE667 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1734_1005[] = "D1451 (SCENIC N300, i845GV) Sigmatel STAC9750T"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c5_1734_1055[] = "Amilo M1420"; +#endif +static const char pci_device_8086_24c6[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c6_1014_0559[] = "Thinkpad R50e model 1634"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c6_1025_003c[] = "Aspire 2001WLCi (Compal CL50 motherboard) implementation"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c6_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c6_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c6_103c_088c[] = "NC8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c6_103c_0890[] = "NC6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c6_103c_08b0[] = "tc1100 tablet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c6_1071_8160[] = "MIM2000"; +#endif +static const char pci_device_8086_24c7[] = "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1014_052d[] = "Thinkpad R50e model 1634"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_103c_088c[] = "NC8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_103c_0890[] = "NC6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_103c_08b0[] = "tc1100 tablet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1509_2990[] = "Averatec 5110H"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_1734_1004[] = "D1451 Mainboard (SCENIC N300, i845GV)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24c7_8086_4541[] = "Latitude D400"; +#endif +static const char pci_device_8086_24ca[] = "82801DBM (ICH4-M) IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_1014_052d[] = "Thinkpad R50e model 1634"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_103c_088c[] = "NC8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_103c_0890[] = "NC6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_103c_08b0[] = "tc1100 tablet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24ca_8086_4541[] = "Latitude D400"; +#endif +static const char pci_device_8086_24cb[] = "82801DB (ICH4) IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cb_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cb_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cb_1458_24c2[] = "GA-8PE667 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cb_1462_5800[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cb_1734_1004[] = "D1451 Mainboard (SCENIC N300, i845GV)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cb_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +static const char pci_device_8086_24cc[] = "82801DBM (ICH4-M) LPC Interface Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cc_1734_1055[] = "Amilo M1420"; +#endif +static const char pci_device_8086_24cd[] = "82801DB/DBM (ICH4/ICH4-M) USB2 EHCI Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1014_052e[] = "Thinkpad R50e model 1634"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1028_011d[] = "Latitude D600"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_103c_088c[] = "NC8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_103c_0890[] = "NC6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_103c_08b0[] = "tc1100 tablet"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1071_8160[] = "MIM2000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1179_ff00[] = "Satellite 2430"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1462_3981[] = "845PE Max (MS-6580)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1509_1968[] = "Averatec 5110H"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1734_1004[] = "D1451 Mainboard (SCENIC N300, i845GV)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24cd_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +static const char pci_device_8086_24d0[] = "82801EB/ER (ICH5/ICH5R) LPC Interface Bridge"; +static const char pci_device_8086_24d1[] = "82801EB (ICH5) SATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_1043_80a6[] = "P4P800 SE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_1458_24d1[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_8086_4c43[] = "Desktop Board D865GLC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d1_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24d2[] = "82801EB/ER (ICH5/ICH5R) USB UHCI Controller #1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1014_02ed[] = "xSeries server mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1028_0183[] = "PowerEdge 1800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_103c_006a[] = "NX9500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1458_24d2[] = "GA-8IPE1000/8KNXP motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_8086_4c43[] = "Desktop Board D865GLC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d2_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24d3[] = "82801EB/ER (ICH5/ICH5R) SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_1014_02ed[] = "xSeries server mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_1028_0156[] = "Precision 360"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_1043_80a6[] = "P4P800 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_1458_24d2[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_8086_4c43[] = "Desktop Board D865GLC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d3_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24d4[] = "82801EB/ER (ICH5/ICH5R) USB UHCI Controller #2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1014_02ed[] = "xSeries server mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1028_0183[] = "PowerEdge 1800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_103c_006a[] = "NX9500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1458_24d2[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_8086_4c43[] = "Desktop Board D865GLC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d4_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24d5[] = "82801EB/ER (ICH5/ICH5R) AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_103c_006a[] = "NX9500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_103c_12bc[] = "d330 uT"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_1043_80f3[] = "P4P800 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_1043_810f[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_1458_a002[] = "GA-8IPE1000/8KNXP motherboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_1462_0080[] = "65PE Neo2-V (MS-6788) mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_8086_a000[] = "D865PERL mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_8086_e000[] = "D865PERL mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_8086_e001[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d5_8086_e002[] = "SoundMax Intergrated Digital Audio"; +#endif +static const char pci_device_8086_24d6[] = "82801EB/ER (ICH5/ICH5R) AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d6_103c_006a[] = "NX9500"; +#endif +static const char pci_device_8086_24d7[] = "82801EB/ER (ICH5/ICH5R) USB UHCI Controller #3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1014_02ed[] = "xSeries server mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1028_0183[] = "PowerEdge 1800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_103c_006a[] = "NX9500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1458_24d2[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_8086_4c43[] = "Desktop Board D865GLC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24d7_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24db[] = "82801EB/ER (ICH5/ICH5R) IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1014_02ed[] = "xSeries server mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_103c_006a[] = "NX9500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1458_24d2[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1462_7580[] = "MSI 875P"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_8086_24db[] = "P4C800 Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_8086_4c43[] = "Desktop Board D865GLC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24db_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24dc[] = "82801EB (ICH5) LPC Interface Bridge"; +static const char pci_device_8086_24dd[] = "82801EB/ER (ICH5/ICH5R) USB2 EHCI Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1014_02ed[] = "xSeries server mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1028_0183[] = "PowerEdge 1800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_103c_006a[] = "NX9500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_103c_12bc[] = "d530 CMT (DG746A)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1458_5006[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_8086_4c43[] = "Desktop Board D865GLC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24dd_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24de[] = "82801EB/ER (ICH5/ICH5R) USB UHCI Controller #4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_1014_02ed[] = "xSeries server mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_1043_80a6[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_1458_24d2[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_1462_7280[] = "865PE Neo2 (MS-6728)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_15d9_4580[] = "P4SCE Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_1734_101c[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_8086_3427[] = "S875WP1-E mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_8086_4c43[] = "Desktop Board D865GLC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_24de_8086_524c[] = "D865PERL mainboard"; +#endif +static const char pci_device_8086_24df[] = "82801ER (ICH5R) SATA Controller"; +static const char pci_device_8086_2500[] = "82820 820 (Camino) Chipset Host Bridge (MCH)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2500_1028_0095[] = "Precision Workstation 220 Chipset"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2500_1043_801c[] = "P3C-2000 system chipset"; +#endif +static const char pci_device_8086_2501[] = "82820 820 (Camino) Chipset Host Bridge (MCH)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2501_1043_801c[] = "P3C-2000 system chipset"; +#endif +static const char pci_device_8086_250b[] = "82820 820 (Camino) Chipset Host Bridge"; +static const char pci_device_8086_250f[] = "82820 820 (Camino) Chipset AGP Bridge"; +static const char pci_device_8086_2520[] = "82805AA MTH Memory Translator Hub"; +static const char pci_device_8086_2521[] = "82804AA MRH-S Memory Repeater Hub for SDRAM"; +static const char pci_device_8086_2530[] = "82850 850 (Tehama) Chipset Host Bridge (MCH)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2530_1028_00c7[] = "Dimension 8100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2530_147b_0507[] = "TH7II-RAID"; +#endif +static const char pci_device_8086_2531[] = "82860 860 (Wombat) Chipset Host Bridge (MCH)"; +static const char pci_device_8086_2532[] = "82850 850 (Tehama) Chipset AGP Bridge"; +static const char pci_device_8086_2533[] = "82860 860 (Wombat) Chipset AGP Bridge"; +static const char pci_device_8086_2534[] = "82860 860 (Wombat) Chipset PCI Bridge"; +static const char pci_device_8086_2540[] = "E7500 Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2540_15d9_3480[] = "P4DP6"; +#endif +static const char pci_device_8086_2541[] = "E7500/E7501 Host RASUM Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2541_15d9_3480[] = "P4DP6"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2541_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2541_8086_3424[] = "SE7501HG2 Mainboard"; +#endif +static const char pci_device_8086_2543[] = "E7500/E7501 Hub Interface B PCI-to-PCI Bridge"; +static const char pci_device_8086_2544[] = "E7500/E7501 Hub Interface B RASUM Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2544_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +static const char pci_device_8086_2545[] = "E7500/E7501 Hub Interface C PCI-to-PCI Bridge"; +static const char pci_device_8086_2546[] = "E7500/E7501 Hub Interface C RASUM Controller"; +static const char pci_device_8086_2547[] = "E7500/E7501 Hub Interface D PCI-to-PCI Bridge"; +static const char pci_device_8086_2548[] = "E7500/E7501 Hub Interface D RASUM Controller"; +static const char pci_device_8086_254c[] = "E7501 Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_254c_4c53_1090[] = "Cx9 / Vx9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_254c_8086_3424[] = "SE7501HG2 Mainboard"; +#endif +static const char pci_device_8086_2550[] = "E7505 Memory Controller Hub"; +static const char pci_device_8086_2551[] = "E7505/E7205 Series RAS Controller"; +static const char pci_device_8086_2552[] = "E7505/E7205 PCI-to-AGP Bridge"; +static const char pci_device_8086_2553[] = "E7505 Hub Interface B PCI-to-PCI Bridge"; +static const char pci_device_8086_2554[] = "E7505 Hub Interface B PCI-to-PCI Bridge RAS Controller"; +static const char pci_device_8086_255d[] = "E7205 Memory Controller Hub"; +static const char pci_device_8086_2560[] = "82845G/GL[Brookdale-G]/GE/PE DRAM Controller/Host-Hub Interface"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2560_1028_0126[] = "Optiplex GX260"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2560_1458_2560[] = "GA-8PE667 Ultra"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2560_1462_5800[] = "845PE Max (MS-6580)"; +#endif +static const char pci_device_8086_2561[] = "82845G/GL[Brookdale-G]/GE/PE Host-to-AGP Bridge"; +static const char pci_device_8086_2562[] = "82845G/GL[Brookdale-G]/GE Chipset Integrated Graphics Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2562_0e11_00b9[] = "Evo D510 SFF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2562_1014_0267[] = "NetVista A30p"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2562_1734_1004[] = "D1451 Mainboard (SCENIC N300, i845GV)"; +#endif +static const char pci_device_8086_2570[] = "82865G/PE/P DRAM Controller/Host-Hub Interface"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2570_103c_006a[] = "NX9500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2570_1043_80f2[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2570_1458_2570[] = "GA-8IPE1000 Pro2 motherboard (865PE)"; +#endif +static const char pci_device_8086_2571[] = "82865G/PE/P PCI to AGP Controller"; +static const char pci_device_8086_2572[] = "82865G Integrated Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2572_1028_019d[] = "Dimension 3000"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2572_103c_12bc[] = "D530 sff(dc578av)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2572_1043_80a5[] = "P5P800-MX Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2572_8086_4246[] = "Desktop Board D865GBF"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2572_8086_4c43[] = "Desktop Board D865GLC"; +#endif +static const char pci_device_8086_2573[] = "82865G/PE/P PCI to CSA Bridge"; +static const char pci_device_8086_2576[] = "82865G/PE/P Processor to I/O Memory Interface"; +static const char pci_device_8086_2578[] = "82875P/E7210 Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2578_1458_2578[] = "GA-8KNXP motherboard (875P)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2578_1462_7580[] = "MS-6758 (875P Neo)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2578_15d9_4580[] = "P4SCE Motherboard"; +#endif +static const char pci_device_8086_2579[] = "82875P Processor to AGP Controller"; +static const char pci_device_8086_257b[] = "82875P/E7210 Processor to PCI to CSA Bridge"; +static const char pci_device_8086_257e[] = "82875P/E7210 Processor to I/O Memory Interface"; +static const char pci_device_8086_2580[] = "82915G/P/GV/GL/PL/910GL Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2580_1458_2580[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2580_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2580_1734_105b[] = "Scenic W620"; +#endif +static const char pci_device_8086_2581[] = "82915G/P/GV/GL/PL/910GL PCI Express Root Port"; +static const char pci_device_8086_2582[] = "82915G/GV/910GL Integrated Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2582_1028_1079[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2582_103c_3006[] = "DC7100 SFF(DX878AV)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2582_1043_2582[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2582_1458_2582[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2582_1734_105b[] = "Scenic W620"; +#endif +static const char pci_device_8086_2584[] = "82925X/XE Memory Controller Hub"; +static const char pci_device_8086_2585[] = "82925X/XE PCI Express Root Port"; +static const char pci_device_8086_2588[] = "E7220/E7221 Memory Controller Hub"; +static const char pci_device_8086_2589[] = "E7220/E7221 PCI Express Root Port"; +static const char pci_device_8086_258a[] = "E7221 Integrated Graphics Controller"; +static const char pci_device_8086_2590[] = "Mobile 915GM/PM/GMS/910GML Express Processor to DRAM Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2590_1028_0182[] = "Dell Latidude C610"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2590_103c_099c[] = "NX6110/NC6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2590_a304_81b7[] = "Vaio VGN-S3XP"; +#endif +static const char pci_device_8086_2591[] = "Mobile 915GM/PM Express PCI Express Root Port"; +static const char pci_device_8086_2592[] = "Mobile 915GM/GMS/910GML Express Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2592_103c_099c[] = "NX6110/NC6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2592_103c_308a[] = "NC6220"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2592_1043_1881[] = "GMA 900 915GM Integrated Graphics"; +#endif +static const char pci_device_8086_25a1[] = "6300ESB LPC Interface Controller"; +static const char pci_device_8086_25a2[] = "6300ESB PATA Storage Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a2_1775_10d0[] = "V5D Single Board Computer IDE"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a2_1775_ce90[] = "CE9"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a2_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a2_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25a3[] = "6300ESB SATA Storage Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a3_1775_ce90[] = "CE9"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a3_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a3_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a3_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25a4[] = "6300ESB SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a4_1775_10d0[] = "V5D Single Board Computer"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a4_1775_ce90[] = "CE9"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a4_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a4_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a4_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25a6[] = "6300ESB AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a6_1775_ce90[] = "CE9"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a6_4c53_10b0[] = "CL9 mainboard"; +#endif +static const char pci_device_8086_25a7[] = "6300ESB AC'97 Modem Controller"; +static const char pci_device_8086_25a9[] = "6300ESB USB Universal Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a9_1775_10d0[] = "V5D Single Board Computer USB"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a9_1775_ce90[] = "CE9"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a9_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a9_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25a9_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25aa[] = "6300ESB USB Universal Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25aa_1775_ce90[] = "CE9"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25aa_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25aa_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25ab[] = "6300ESB Watchdog Timer"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ab_1775_10d0[] = "V5D Single Board Computer"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ab_1775_ce90[] = "CE9"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ab_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ab_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ab_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25ac[] = "6300ESB I/O Advanced Programmable Interrupt Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ac_1775_10d0[] = "V5D Single Board Computer"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ac_1775_ce90[] = "CE9"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ac_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ac_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ac_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25ad[] = "6300ESB USB2 Enhanced Host Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ad_1775_10d0[] = "V5D Single Board Computer USB 2.0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ad_1775_ce90[] = "CE9"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ad_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ad_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25ad_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25ae[] = "6300ESB 64-bit PCI-X Bridge"; +static const char pci_device_8086_25b0[] = "6300ESB SATA RAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25b0_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_25b0_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_25c0[] = "5000X Chipset Memory Controller Hub"; +static const char pci_device_8086_25d0[] = "5000Z Chipset Memory Controller Hub"; +static const char pci_device_8086_25d4[] = "5000V Chipset Memory Controller Hub"; +static const char pci_device_8086_25d8[] = "5000P Chipset Memory Controller Hub"; +static const char pci_device_8086_25e2[] = "5000 Series Chipset PCI Express x4 Port 2"; +static const char pci_device_8086_25e3[] = "5000 Series Chipset PCI Express x4 Port 3"; +static const char pci_device_8086_25e4[] = "5000 Series Chipset PCI Express x4 Port 4"; +static const char pci_device_8086_25e5[] = "5000 Series Chipset PCI Express x4 Port 5"; +static const char pci_device_8086_25e6[] = "5000 Series Chipset PCI Express x4 Port 6"; +static const char pci_device_8086_25e7[] = "5000 Series Chipset PCI Express x4 Port 7"; +static const char pci_device_8086_25f0[] = "5000 Series Chipset Error Reporting Registers"; +static const char pci_device_8086_25f1[] = "5000 Series Chipset Reserved Registers"; +static const char pci_device_8086_25f3[] = "5000 Series Chipset Reserved Registers"; +static const char pci_device_8086_25f5[] = "5000 Series Chipset FBD Registers"; +static const char pci_device_8086_25f6[] = "5000 Series Chipset FBD Registers"; +static const char pci_device_8086_25f7[] = "5000 Series Chipset PCI Express x8 Port 2-3"; +static const char pci_device_8086_25f8[] = "5000 Series Chipset PCI Express x8 Port 4-5"; +static const char pci_device_8086_25f9[] = "5000 Series Chipset PCI Express x8 Port 6-7"; +static const char pci_device_8086_25fa[] = "5000X Chipset PCI Express x16 Port 4-7"; +static const char pci_device_8086_2600[] = "E8500/E8501 Hub Interface 1.5"; +static const char pci_device_8086_2601[] = "E8500/E8501 PCI Express x4 Port D"; +static const char pci_device_8086_2602[] = "E8500/E8501 PCI Express x4 Port C0"; +static const char pci_device_8086_2603[] = "E8500/E8501 PCI Express x4 Port C1"; +static const char pci_device_8086_2604[] = "E8500/E8501 PCI Express x4 Port B0"; +static const char pci_device_8086_2605[] = "E8500/E8501 PCI Express x4 Port B1"; +static const char pci_device_8086_2606[] = "E8500/E8501 PCI Express x4 Port A0"; +static const char pci_device_8086_2607[] = "E8500/E8501 PCI Express x4 Port A1"; +static const char pci_device_8086_2608[] = "E8500/E8501 PCI Express x8 Port C"; +static const char pci_device_8086_2609[] = "E8500/E8501 PCI Express x8 Port B"; +static const char pci_device_8086_260a[] = "E8500/E8501 PCI Express x8 Port A"; +static const char pci_device_8086_260c[] = "E8500/E8501 IMI Registers"; +static const char pci_device_8086_2610[] = "E8500/E8501 Front Side Bus, Boot, and Interrupt Registers"; +static const char pci_device_8086_2611[] = "E8500/E8501 Address Mapping Registers"; +static const char pci_device_8086_2612[] = "E8500/E8501 RAS Registers"; +static const char pci_device_8086_2613[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_2614[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_2615[] = "E8500/E8501 Miscellaneous Registers"; +static const char pci_device_8086_2617[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_2618[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_2619[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_261a[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_261b[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_261c[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_261d[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_261e[] = "E8500/E8501 Reserved Registers"; +static const char pci_device_8086_2620[] = "E8500/E8501 eXternal Memory Bridge"; +static const char pci_device_8086_2621[] = "E8500/E8501 XMB Miscellaneous Registers"; +static const char pci_device_8086_2622[] = "E8500/E8501 XMB Memory Interleaving Registers"; +static const char pci_device_8086_2623[] = "E8500/E8501 XMB DDR Initialization and Calibration"; +static const char pci_device_8086_2624[] = "E8500/E8501 XMB Reserved Registers"; +static const char pci_device_8086_2625[] = "E8500/E8501 XMB Reserved Registers"; +static const char pci_device_8086_2626[] = "E8500/E8501 XMB Reserved Registers"; +static const char pci_device_8086_2627[] = "E8500/E8501 XMB Reserved Registers"; +static const char pci_device_8086_2640[] = "82801FB/FR (ICH6/ICH6R) LPC Interface Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2640_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2640_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_2641[] = "82801FBM (ICH6M) LPC Interface Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2641_103c_099c[] = "NX6110/NC6120"; +#endif +static const char pci_device_8086_2642[] = "82801FW/FRW (ICH6W/ICH6RW) LPC Interface Bridge"; +static const char pci_device_8086_2651[] = "82801FB/FW (ICH6/ICH6W) SATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2651_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2651_1043_2601[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2651_1734_105c[] = "Scenic W620"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2651_8086_4147[] = "D915GAG Motherboard"; +#endif +static const char pci_device_8086_2652[] = "82801FR/FRW (ICH6R/ICH6RW) SATA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2652_1462_7028[] = "915P/G Neo2"; +#endif +static const char pci_device_8086_2653[] = "82801FBM (ICH6M) SATA Controller"; +static const char pci_device_8086_2658[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2658_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2658_103c_099c[] = "NX6110/NC6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2658_1043_80a6[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2658_1458_2558[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2658_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2658_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_2659[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2659_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2659_103c_099c[] = "NX6110/NC6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2659_1043_80a6[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2659_1458_2659[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2659_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2659_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_265a[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265a_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265a_103c_099c[] = "NX6110/NC6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265a_1043_80a6[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265a_1458_265a[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265a_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265a_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_265b[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265b_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265b_103c_099c[] = "NX6110/NC6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265b_1043_80a6[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265b_1458_265a[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265b_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265b_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_265c[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265c_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265c_103c_099c[] = "NX6110/NC6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265c_1043_80a6[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265c_1458_5006[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265c_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265c_1734_105c[] = "Scenic W620"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_265c_8086_265c[] = "Dimension 3100"; +#endif +static const char pci_device_8086_2660[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2660_103c_099c[] = "NX6110/NC6120"; +#endif +static const char pci_device_8086_2662[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 2"; +static const char pci_device_8086_2664[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 3"; +static const char pci_device_8086_2666[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 4"; +static const char pci_device_8086_2668[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) High Definition Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2668_103c_2a09[] = "PufferM-UL8E"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2668_1043_814e[] = "P5GD1-VW Mainboard"; +#endif +static const char pci_device_8086_266a[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266a_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266a_1043_80a6[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266a_1458_266a[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266a_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266a_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_266c[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) LAN Controller"; +static const char pci_device_8086_266d[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Modem Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266d_1025_006a[] = "Conexant AC'97 CoDec (in Acer TravelMate 2410 serie laptop)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266d_103c_099c[] = "NX6110/NC6120"; +#endif +static const char pci_device_8086_266e[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_1025_006a[] = "Realtek ALC 655 codec (in Acer TravelMate 2410 serie laptop)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_1028_0179[] = "Optiplex GX280"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_1028_0182[] = "Latitude D610 Laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_1028_0188[] = "Inspiron 6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_103c_0944[] = "Compaq NC6220"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_103c_099c[] = "NX6110/NC6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_103c_3006[] = "DC7100 SFF(DX878AV)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_1458_a002[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_152d_0745[] = "Packard Bell A8550 Laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266e_1734_105a[] = "Scenic W620"; +#endif +static const char pci_device_8086_266f[] = "82801FB/FBM/FR/FW/FRW (ICH6 Family) IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266f_103c_099c[] = "NX6110/NC6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266f_1043_80a6[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266f_1458_266f[] = "GA-8I915ME-G Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266f_1462_7028[] = "915P/G Neo2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_266f_1734_105c[] = "Scenic W620"; +#endif +static const char pci_device_8086_2670[] = "631xESB/632xESB/3100 Chipset LPC Interface Controller"; +static const char pci_device_8086_2680[] = "631xESB/632xESB/3100 Chipset SATA Storage Controller IDE"; +static const char pci_device_8086_2681[] = "631xESB/632xESB SATA Storage Controller AHCI"; +static const char pci_device_8086_2682[] = "631xESB/632xESB SATA Storage Controller RAID"; +static const char pci_device_8086_2683[] = "631xESB/632xESB SATA Storage Controller RAID"; +static const char pci_device_8086_2688[] = "631xESB/632xESB/3100 Chipset UHCI USB Controller #1"; +static const char pci_device_8086_2689[] = "631xESB/632xESB/3100 Chipset UHCI USB Controller #2"; +static const char pci_device_8086_268a[] = "631xESB/632xESB/3100 Chipset UHCI USB Controller #3"; +static const char pci_device_8086_268b[] = "631xESB/632xESB/3100 Chipset UHCI USB Controller #4"; +static const char pci_device_8086_268c[] = "631xESB/632xESB/3100 Chipset EHCI USB2 Controller"; +static const char pci_device_8086_2690[] = "631xESB/632xESB/3100 Chipset PCI Express Root Port 1"; +static const char pci_device_8086_2692[] = "631xESB/632xESB/3100 Chipset PCI Express Root Port 2"; +static const char pci_device_8086_2694[] = "631xESB/632xESB/3100 Chipset PCI Express Root Port 3"; +static const char pci_device_8086_2696[] = "631xESB/632xESB/3100 Chipset PCI Express Root Port 4"; +static const char pci_device_8086_2698[] = "631xESB/632xESB AC '97 Audio Controller"; +static const char pci_device_8086_2699[] = "631xESB/632xESB AC '97 Modem Controller"; +static const char pci_device_8086_269a[] = "631xESB/632xESB High Definition Audio Controller"; +static const char pci_device_8086_269b[] = "631xESB/632xESB/3100 Chipset SMBus Controller"; +static const char pci_device_8086_269e[] = "631xESB/632xESB IDE Controller"; +static const char pci_device_8086_2770[] = "82945G/GZ/P/PL Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2770_107b_5048[] = "E4500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2770_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_2771[] = "82945G/GZ/P/PL PCI Express Root Port"; +static const char pci_device_8086_2772[] = "82945G/GZ Integrated Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2772_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_2774[] = "82955X Memory Controller Hub"; +static const char pci_device_8086_2775[] = "82955X PCI Express Root Port"; +static const char pci_device_8086_2776[] = "82945G/GZ Integrated Graphics Controller"; +static const char pci_device_8086_2778[] = "E7230/3000/3010 Memory Controller Hub"; +static const char pci_device_8086_2779[] = "E7230/3000/3010 PCI Express Root Port"; +static const char pci_device_8086_277a[] = "82975X/3010 PCI Express Root Port"; +static const char pci_device_8086_277c[] = "82975X Memory Controller Hub"; +static const char pci_device_8086_277d[] = "82975X PCI Express Root Port"; +static const char pci_device_8086_2782[] = "82915G Integrated Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2782_1043_2582[] = "P5GD1-VW Mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2782_1734_105b[] = "Scenic W620"; +#endif +static const char pci_device_8086_2792[] = "Mobile 915GM/GMS/910GML Express Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2792_103c_099c[] = "NX6110/NC6120"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_2792_1043_1881[] = "GMA 900 915GM Integrated Graphics"; +#endif +static const char pci_device_8086_27a0[] = "Mobile 945GM/PM/GMS/940GML and 945GT Express Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27a0_17aa_2017[] = "Thinkpad R60e model 0657"; +#endif +static const char pci_device_8086_27a1[] = "Mobile 945GM/PM/GMS/940GML and 945GT Express PCI Express Root Port"; +static const char pci_device_8086_27a2[] = "Mobile 945GM/GMS/940GML Express Integrated Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27a2_17aa_201a[] = "Thinkpad R60e model 0657"; +#endif +static const char pci_device_8086_27a6[] = "Mobile 945GM/GMS/940GML Express Integrated Graphics Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27a6_17aa_201a[] = "Thinkpad R60e model 0657"; +#endif +static const char pci_device_8086_27b0[] = "82801GH (ICH7DH) LPC Interface Bridge"; +static const char pci_device_8086_27b8[] = "82801GB/GR (ICH7 Family) LPC Interface Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27b8_107b_5048[] = "E4500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27b8_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27b9[] = "82801GBM (ICH7-M) LPC Interface Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27b9_17aa_2009[] = "ThinkPad T60/R60 series"; +#endif +static const char pci_device_8086_27bd[] = "82801GHM (ICH7-M DH) LPC Interface Bridge"; +static const char pci_device_8086_27c0[] = "82801GB/GR/GH (ICH7 Family) Serial ATA Storage Controller IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27c0_107b_5048[] = "E4500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27c0_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27c1[] = "82801GR/GH (ICH7 Family) Serial ATA Storage Controller AHCI"; +static const char pci_device_8086_27c3[] = "82801GR/GH (ICH7 Family) Serial ATA Storage Controller RAID"; +static const char pci_device_8086_27c4[] = "82801GBM/GHM (ICH7 Family) Serial ATA Storage Controller IDE"; +static const char pci_device_8086_27c5[] = "82801GBM/GHM (ICH7 Family) Serial ATA Storage Controller AHCI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27c5_17aa_200d[] = "Thinkpad R60e model 0657"; +#endif +static const char pci_device_8086_27c6[] = "82801GHM (ICH7-M DH) Serial ATA Storage Controller RAID"; +static const char pci_device_8086_27c8[] = "82801G (ICH7 Family) USB UHCI #1"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27c8_107b_5048[] = "E4500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27c8_17aa_200a[] = "ThinkPad T60/R60 series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27c8_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27c9[] = "82801G (ICH7 Family) USB UHCI #2"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27c9_107b_5048[] = "E4500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27c9_17aa_200a[] = "ThinkPad T60/R60 series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27c9_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27ca[] = "82801G (ICH7 Family) USB UHCI #3"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27ca_107b_5048[] = "E4500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27ca_17aa_200a[] = "ThinkPad T60/R60 series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27ca_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27cb[] = "82801G (ICH7 Family) USB UHCI #4"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27cb_107b_5048[] = "E4500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27cb_17aa_200a[] = "ThinkPad T60/R60 series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27cb_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27cc[] = "82801G (ICH7 Family) USB2 EHCI Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27cc_17aa_200b[] = "ThinkPad T60/R60 series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27cc_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27d0[] = "82801G (ICH7 Family) PCI Express Port 1"; +static const char pci_device_8086_27d2[] = "82801G (ICH7 Family) PCI Express Port 2"; +static const char pci_device_8086_27d4[] = "82801G (ICH7 Family) PCI Express Port 3"; +static const char pci_device_8086_27d6[] = "82801G (ICH7 Family) PCI Express Port 4"; +static const char pci_device_8086_27d8[] = "82801G (ICH7 Family) High Definition Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27d8_107b_5048[] = "E4500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27d8_152d_0753[] = "Softmodem"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27d8_17aa_2010[] = "ThinkPad T60/R60 series"; +#endif +static const char pci_device_8086_27da[] = "82801G (ICH7 Family) SMBus Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27da_17aa_200f[] = "ThinkPad T60/R60 series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27da_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27dc[] = "82801G (ICH7 Family) LAN Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27dc_8086_308d[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27dd[] = "82801G (ICH7 Family) AC'97 Modem Controller"; +static const char pci_device_8086_27de[] = "82801G (ICH7 Family) AC'97 Audio Controller"; +static const char pci_device_8086_27df[] = "82801G (ICH7 Family) IDE Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27df_107b_5048[] = "E4500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27df_17aa_200c[] = "Thinkpad R60e model 0657"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_27df_8086_544e[] = "DeskTop Board D945GTP"; +#endif +static const char pci_device_8086_27e0[] = "82801GR/GH/GHM (ICH7 Family) PCI Express Port 5"; +static const char pci_device_8086_27e2[] = "82801GR/GH/GHM (ICH7 Family) PCI Express Port 6"; +static const char pci_device_8086_2810[] = "82801HB/HR (ICH8/R) LPC Interface Controller"; +static const char pci_device_8086_2811[] = "Mobile LPC Interface Controller"; +static const char pci_device_8086_2812[] = "82801HH (ICH8DH) LPC Interface Controller"; +static const char pci_device_8086_2814[] = "82801HO (ICH8DO) LPC Interface Controller"; +static const char pci_device_8086_2815[] = "Mobile LPC Interface Controller"; +static const char pci_device_8086_2820[] = "82801H (ICH8 Family) 4 port SATA IDE Controller"; +static const char pci_device_8086_2821[] = "82801HB (ICH8) SATA AHCI Controller"; +static const char pci_device_8086_2822[] = "82801HR/HO/HH (ICH8R/DO/DH) SATA RAID Controller"; +static const char pci_device_8086_2824[] = "82801HR/HO/HH (ICH8R/DO/DH) SATA AHCI Controller"; +static const char pci_device_8086_2825[] = "82801H (ICH8 Family) 2 port SATA IDE Controller"; +static const char pci_device_8086_2828[] = "Mobile SATA IDE Controller"; +static const char pci_device_8086_2829[] = "Mobile SATA AHCI Controller"; +static const char pci_device_8086_282a[] = "Mobile SATA RAID Controller"; +static const char pci_device_8086_2830[] = "82801H (ICH8 Family) USB UHCI #1"; +static const char pci_device_8086_2831[] = "82801H (ICH8 Family) USB UHCI #2"; +static const char pci_device_8086_2832[] = "82801H (ICH8 Family) USB UHCI #3"; +static const char pci_device_8086_2834[] = "82801H (ICH8 Family) USB UHCI #4"; +static const char pci_device_8086_2835[] = "82801H (ICH8 Family) USB UHCI #5"; +static const char pci_device_8086_2836[] = "82801H (ICH8 Family) USB2 EHCI #1"; +static const char pci_device_8086_283a[] = "82801H (ICH8 Family) USB2 EHCI #2"; +static const char pci_device_8086_283e[] = "82801H (ICH8 Family) SMBus Controller"; +static const char pci_device_8086_283f[] = "82801H (ICH8 Family) PCI Express Port 1"; +static const char pci_device_8086_2841[] = "82801H (ICH8 Family) PCI Express Port 2"; +static const char pci_device_8086_2843[] = "82801H (ICH8 Family) PCI Express Port 3"; +static const char pci_device_8086_2845[] = "82801H (ICH8 Family) PCI Express Port 4"; +static const char pci_device_8086_2847[] = "82801H (ICH8 Family) PCI Express Port 5"; +static const char pci_device_8086_2849[] = "82801H (ICH8 Family) PCI Express Port 6"; +static const char pci_device_8086_284b[] = "82801H (ICH8 Family) HD Audio Controller"; +static const char pci_device_8086_284f[] = "82801H (ICH8 Family) Thermal Reporting Device"; +static const char pci_device_8086_2850[] = "Mobile IDE Controller"; +static const char pci_device_8086_2970[] = "82946GZ/PL/GL Memory Controller Hub"; +static const char pci_device_8086_2971[] = "82946GZ/PL/GL PCI Express Root Port"; +static const char pci_device_8086_2972[] = "82946GZ/GL Integrated Graphics Controller"; +static const char pci_device_8086_2973[] = "82946GZ/GL Integrated Graphics Controller"; +static const char pci_device_8086_2974[] = "82946GZ/GL HECI Controller"; +static const char pci_device_8086_2975[] = "82946GZ/GL HECI Controller"; +static const char pci_device_8086_2976[] = "82946GZ/GL PT IDER Controller"; +static const char pci_device_8086_2977[] = "82946GZ/GL KT Controller"; +static const char pci_device_8086_2980[] = "965 G1 Memory Controller Hub"; +static const char pci_device_8086_2981[] = "965 G1 PCI Express Root Port"; +static const char pci_device_8086_2982[] = "965 G1 Integrated Graphics Controller"; +static const char pci_device_8086_2990[] = "82Q963/Q965 Memory Controller Hub"; +static const char pci_device_8086_2991[] = "82Q963/Q965 PCI Express Root Port"; +static const char pci_device_8086_2992[] = "82Q963/Q965 Integrated Graphics Controller"; +static const char pci_device_8086_2993[] = "82Q963/Q965 Integrated Graphics Controller"; +static const char pci_device_8086_2994[] = "82Q963/Q965 HECI Controller"; +static const char pci_device_8086_2995[] = "82Q963/Q965 HECI Controller"; +static const char pci_device_8086_2996[] = "82Q963/Q965 PT IDER Controller"; +static const char pci_device_8086_2997[] = "82Q963/Q965 KT Controller"; +static const char pci_device_8086_29a0[] = "82P965/G965 Memory Controller Hub"; +static const char pci_device_8086_29a1[] = "82P965/G965 PCI Express Root Port"; +static const char pci_device_8086_29a2[] = "82G965 Integrated Graphics Controller"; +static const char pci_device_8086_29a3[] = "82G965 Integrated Graphics Controller"; +static const char pci_device_8086_29a4[] = "82P965/G965 HECI Controller"; +static const char pci_device_8086_29a5[] = "82P965/G965 HECI Controller"; +static const char pci_device_8086_29a6[] = "82P965/G965 PT IDER Controller"; +static const char pci_device_8086_29a7[] = "82P965/G965 KT Controller"; +static const char pci_device_8086_2a00[] = "Mobile Memory Controller Hub"; +static const char pci_device_8086_2a01[] = "Mobile PCI Express Root Port"; +static const char pci_device_8086_2a02[] = "Mobile Integrated Graphics Controller"; +static const char pci_device_8086_2a03[] = "Mobile Integrated Graphics Controller"; +static const char pci_device_8086_2a04[] = "Mobile HECI Controller"; +static const char pci_device_8086_2a05[] = "Mobile HECI Controller"; +static const char pci_device_8086_2a06[] = "Mobile PT IDER Controller"; +static const char pci_device_8086_2a07[] = "Mobile KT Controller"; +static const char pci_device_8086_3092[] = "Integrated RAID"; +static const char pci_device_8086_3200[] = "GD31244 PCI-X SATA HBA"; +static const char pci_device_8086_3340[] = "82855PM Processor to I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3340_1025_005a[] = "TravelMate 290"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3340_103c_088c[] = "NC8000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3340_103c_0890[] = "NC6000 laptop"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3340_103c_08b0[] = "tc1100 tablet"; +#endif +static const char pci_device_8086_3341[] = "82855PM Processor to AGP Controller"; +static const char pci_device_8086_3500[] = "6311ESB/6321ESB PCI Express Upstream Port"; +static const char pci_device_8086_3501[] = "6310ESB PCI Express Upstream Port"; +static const char pci_device_8086_3504[] = "6311ESB/6321ESB I/OxAPIC Interrupt Controller"; +static const char pci_device_8086_3505[] = "6310ESB I/OxAPIC Interrupt Controller"; +static const char pci_device_8086_350c[] = "6311ESB/6321ESB PCI Express to PCI-X Bridge"; +static const char pci_device_8086_350d[] = "6310ESB PCI Express to PCI-X Bridge"; +static const char pci_device_8086_3510[] = "6311ESB/6321ESB PCI Express Downstream Port E1"; +static const char pci_device_8086_3511[] = "6310ESB PCI Express Downstream Port E1"; +static const char pci_device_8086_3514[] = "6311ESB/6321ESB PCI Express Downstream Port E2"; +static const char pci_device_8086_3515[] = "6310ESB PCI Express Downstream Port E2"; +static const char pci_device_8086_3518[] = "6311ESB/6321ESB PCI Express Downstream Port E3"; +static const char pci_device_8086_3519[] = "6310ESB PCI Express Downstream Port E3"; +static const char pci_device_8086_3575[] = "82830 830 Chipset Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3575_0e11_0030[] = "Evo N600c"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3575_1014_021d[] = "ThinkPad A/T/X Series"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3575_104d_80e7[] = "VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP"; +#endif +static const char pci_device_8086_3576[] = "82830 830 Chipset AGP Bridge"; +static const char pci_device_8086_3577[] = "82830 CGC [Chipset Graphics Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3577_1014_0513[] = "ThinkPad A/T/X Series"; +#endif +static const char pci_device_8086_3578[] = "82830 830 Chipset Host Bridge"; +static const char pci_device_8086_3580[] = "82852/82855 GM/GME/PM/GMV Processor to I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_1014_055c[] = "Thinkpad R50e model 1634"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_1775_10d0[] = "V5D Single Board Computer"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_1775_ce90[] = "CE9"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3580_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_3581[] = "82852/82855 GM/GME/PM/GMV Processor to AGP Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3581_1734_1055[] = "Amilo M1420"; +#endif +static const char pci_device_8086_3582[] = "82852/855GM Integrated Graphics Device"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3582_1014_0562[] = "Thinkpad R50e model 1634"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3582_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3582_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3582_1775_10d0[] = "V5D Single Board Computer VGA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3582_1775_ce90[] = "CE9"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3582_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3582_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_3584[] = "82852/82855 GM/GME/PM/GMV Processor to I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_1014_055d[] = "Thinkpad R50e model 1634"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_1775_10d0[] = "V5D Single Board Computer"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_1775_ce90[] = "CE9"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3584_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_3585[] = "82852/82855 GM/GME/PM/GMV Processor to I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_1014_055e[] = "Thinkpad R50e model 1634"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_1028_0139[] = "Latitude D400"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_1028_0163[] = "Latitude D505"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_1028_0196[] = "Inspiron 5160"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_1734_1055[] = "Amilo M1420"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_1775_10d0[] = "V5D Single Board Computer"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_1775_ce90[] = "CE9"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_4c53_10b0[] = "CL9 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3585_4c53_10e0[] = "PSL09 PrPMC"; +#endif +static const char pci_device_8086_3590[] = "E7520 Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3590_1028_019a[] = "PowerEdge SC1425"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3590_1734_103e[] = "Primergy RX300 S2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3590_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +static const char pci_device_8086_3591[] = "E7525/E7520 Error Reporting Registers"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3591_1028_0169[] = "Precision 470"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3591_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +static const char pci_device_8086_3592[] = "E7320 Memory Controller Hub"; +static const char pci_device_8086_3593[] = "E7320 Error Reporting Registers"; +static const char pci_device_8086_3594[] = "E7520 DMA Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_3594_4c53_10d0[] = "Telum ASLP10 Processor AMC"; +#endif +static const char pci_device_8086_3595[] = "E7525/E7520/E7320 PCI Express Port A"; +static const char pci_device_8086_3596[] = "E7525/E7520/E7320 PCI Express Port A1"; +static const char pci_device_8086_3597[] = "E7525/E7520 PCI Express Port B"; +static const char pci_device_8086_3598[] = "E7520 PCI Express Port B1"; +static const char pci_device_8086_3599[] = "E7520 PCI Express Port C"; +static const char pci_device_8086_359a[] = "E7520 PCI Express Port C1"; +static const char pci_device_8086_359b[] = "E7525/E7520/E7320 Extended Configuration Registers"; +static const char pci_device_8086_359e[] = "E7525 Memory Controller Hub"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_359e_1028_0169[] = "Precision 470"; +#endif +static const char pci_device_8086_35b0[] = "3100 Chipset Memory I/O Controller Hub"; +static const char pci_device_8086_35b1[] = "3100 DRAM Controller Error Reporting Registers"; +static const char pci_device_8086_35b5[] = "3100 Chipset Enhanced DMA Controller"; +static const char pci_device_8086_35b6[] = "3100 Chipset PCI Express Port A"; +static const char pci_device_8086_35b7[] = "3100 Chipset PCI Express Port A1"; +static const char pci_device_8086_35c8[] = "3100 Extended Configuration Test Overflow Registers"; +static const char pci_device_8086_4220[] = "PRO/Wireless 2200BG Network Connection"; +static const char pci_device_8086_4222[] = "PRO/Wireless 3945ABG Network Connection"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_4222_8086_1005[] = "PRO/Wireless 3945BG Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_4222_8086_1034[] = "PRO/Wireless 3945BG Network Connection"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_4222_8086_1044[] = "PRO/Wireless 3945BG Network Connection"; +#endif +static const char pci_device_8086_4223[] = "PRO/Wireless 2915ABG Network Connection"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_4223_1351_103c[] = "Compaq NC6220"; +#endif +static const char pci_device_8086_4224[] = "PRO/Wireless 2915ABG Network Connection"; +static const char pci_device_8086_4227[] = "PRO/Wireless 3945ABG Network Connection"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_4227_8086_1011[] = "Thinkpad X60s, R60e model 0657"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_4227_8086_1014[] = "PRO/Wireless 3945BG Network Connection"; +#endif +static const char pci_device_8086_5001[] = "Pro/DSL 2100 Modem"; +static const char pci_device_8086_5200[] = "EtherExpress PRO/100 Intelligent Server"; +static const char pci_device_8086_5201[] = "EtherExpress PRO/100 Intelligent Server"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_5201_8086_0001[] = "EtherExpress PRO/100 Server Ethernet Adapter"; +#endif +static const char pci_device_8086_530d[] = "80310 IOP [IO Processor]"; +static const char pci_device_8086_7000[] = "82371SB PIIX3 ISA [Natoma/Triton II]"; +static const char pci_device_8086_7010[] = "82371SB PIIX3 IDE [Natoma/Triton II]"; +static const char pci_device_8086_7020[] = "82371SB PIIX3 USB [Natoma/Triton II]"; +static const char pci_device_8086_7030[] = "430VX - 82437VX TVX [Triton VX]"; +static const char pci_device_8086_7050[] = "Intercast Video Capture Card"; +static const char pci_device_8086_7051[] = "PB 642365-003 (Business Video Conferencing Card)"; +static const char pci_device_8086_7100[] = "430TX - 82439TX MTXC"; +static const char pci_device_8086_7110[] = "82371AB/EB/MB PIIX4 ISA"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7110_15ad_1976[] = "virtualHW v3"; +#endif +static const char pci_device_8086_7111[] = "82371AB/EB/MB PIIX4 IDE"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7111_15ad_1976[] = "virtualHW v3"; +#endif +static const char pci_device_8086_7112[] = "82371AB/EB/MB PIIX4 USB"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7112_15ad_1976[] = "virtualHW v3"; +#endif +static const char pci_device_8086_7113[] = "82371AB/EB/MB PIIX4 ACPI"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7113_15ad_1976[] = "virtualHW v3"; +#endif +static const char pci_device_8086_7120[] = "82810 GMCH [Graphics Memory Controller Hub]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7120_4c53_1040[] = "CL7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7120_4c53_1060[] = "PC7 mainboard"; +#endif +static const char pci_device_8086_7121[] = "82810 CGC [Chipset Graphics Controller]"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7121_4c53_1040[] = "CL7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7121_4c53_1060[] = "PC7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7121_8086_4341[] = "Cayman (CA810) Mainboard"; +#endif +static const char pci_device_8086_7122[] = "82810 DC-100 GMCH [Graphics Memory Controller Hub]"; +static const char pci_device_8086_7123[] = "82810 DC-100 CGC [Chipset Graphics Controller]"; +static const char pci_device_8086_7124[] = "82810E DC-133 GMCH [Graphics Memory Controller Hub]"; +static const char pci_device_8086_7125[] = "82810E DC-133 CGC [Chipset Graphics Controller]"; +static const char pci_device_8086_7126[] = "82810 DC-133 System and Graphics Controller"; +static const char pci_device_8086_7128[] = "82810-M DC-100 System and Graphics Controller"; +static const char pci_device_8086_712a[] = "82810-M DC-133 System and Graphics Controller"; +static const char pci_device_8086_7180[] = "440LX/EX - 82443LX/EX Host bridge"; +static const char pci_device_8086_7181[] = "440LX/EX - 82443LX/EX AGP bridge"; +static const char pci_device_8086_7190[] = "440BX/ZX/DX - 82443BX/ZX/DX Host bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_0e11_0500[] = "Armada 1750 Laptop System Chipset"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_0e11_b110[] = "Armada M700/E500"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_1028_008e[] = "PowerEdge 1300 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_1179_0001[] = "Toshiba Tecra 8100 Laptop System Chipset"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_15ad_1976[] = "virtualHW v3"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7190_4c53_1051[] = "CE7 mainboard"; +#endif +static const char pci_device_8086_7191[] = "440BX/ZX/DX - 82443BX/ZX/DX AGP bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7191_1028_008e[] = "PowerEdge 1300 mainboard"; +#endif +static const char pci_device_8086_7192[] = "440BX/ZX/DX - 82443BX/ZX/DX Host bridge (AGP disabled)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7192_0e11_0460[] = "Armada 1700 Laptop System Chipset"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7192_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +static const char pci_device_8086_7194[] = "82440MX Host Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7194_1033_0000[] = "Versa Note Vxi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7194_4c53_10a0[] = "CA3/CR3 mainboard"; +#endif +static const char pci_device_8086_7195[] = "82440MX AC'97 Audio Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7195_1033_80cc[] = "Versa Note VXi"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7195_10cf_1099[] = "QSound_SigmaTel Stac97 PCI Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7195_11d4_0040[] = "SoundMAX Integrated Digital Audio"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7195_11d4_0048[] = "SoundMAX Integrated Digital Audio"; +#endif +static const char pci_device_8086_7196[] = "82440MX AC'97 Modem Controller"; +static const char pci_device_8086_7198[] = "82440MX ISA Bridge"; +static const char pci_device_8086_7199[] = "82440MX EIDE Controller"; +static const char pci_device_8086_719a[] = "82440MX USB Universal Host Controller"; +static const char pci_device_8086_719b[] = "82440MX Power Management Controller"; +static const char pci_device_8086_71a0[] = "440GX - 82443GX Host bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_71a0_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_71a0_4c53_1051[] = "CE7 mainboard"; +#endif +static const char pci_device_8086_71a1[] = "440GX - 82443GX AGP bridge"; +static const char pci_device_8086_71a2[] = "440GX - 82443GX Host bridge (AGP disabled)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_71a2_4c53_1000[] = "CC7/CR7/CP7/VC7/VP7/VR7 mainboard"; +#endif +static const char pci_device_8086_7600[] = "82372FB PIIX5 ISA"; +static const char pci_device_8086_7601[] = "82372FB PIIX5 IDE"; +static const char pci_device_8086_7602[] = "82372FB PIIX5 USB"; +static const char pci_device_8086_7603[] = "82372FB PIIX5 SMBus"; +static const char pci_device_8086_7800[] = "82740 (i740) AGP Graphics Accelerator"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_003d_0008[] = "Starfighter AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_003d_000b[] = "Starfighter AGP"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_1092_0100[] = "Stealth II G460"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_10b4_201a[] = "Lightspeed 740"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_10b4_202f[] = "Lightspeed 740"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_8086_0000[] = "Terminator 2x/i"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_7800_8086_0100[] = "Intel740 Graphics Accelerator"; +#endif +static const char pci_device_8086_84c4[] = "450KX/GX [Orion] - 82454KX/GX PCI bridge"; +static const char pci_device_8086_84c5[] = "450KX/GX [Orion] - 82453KX/GX Memory controller"; +static const char pci_device_8086_84ca[] = "450NX - 82451NX Memory & I/O Controller"; +static const char pci_device_8086_84cb[] = "450NX - 82454NX/84460GX PCI Expander Bridge"; +static const char pci_device_8086_84e0[] = "460GX - 84460GX System Address Controller (SAC)"; +static const char pci_device_8086_84e1[] = "460GX - 84460GX System Data Controller (SDC)"; +static const char pci_device_8086_84e2[] = "460GX - 84460GX AGP Bridge (GXB function 2)"; +static const char pci_device_8086_84e3[] = "460GX - 84460GX Memory Address Controller (MAC)"; +static const char pci_device_8086_84e4[] = "460GX - 84460GX Memory Data Controller (MDC)"; +static const char pci_device_8086_84e6[] = "460GX - 82466GX Wide and fast PCI eXpander Bridge (WXB)"; +static const char pci_device_8086_84ea[] = "460GX - 84460GX AGP Bridge (GXB function 1)"; +static const char pci_device_8086_8500[] = "IXP4XX Network Processor (IXP420/421/422/425/IXC1100)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_8500_1993_0ded[] = "mGuard-PCI AV#2"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_8500_1993_0dee[] = "mGuard-PCI AV#1"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_8500_1993_0def[] = "mGuard-PCI AV#0"; +#endif +static const char pci_device_8086_9000[] = "IXP2000 Family Network Processor"; +static const char pci_device_8086_9001[] = "IXP2400 Network Processor"; +static const char pci_device_8086_9002[] = "IXP2300 Network Processor"; +static const char pci_device_8086_9004[] = "IXP2800 Network Processor"; +static const char pci_device_8086_9621[] = "Integrated RAID"; +static const char pci_device_8086_9622[] = "Integrated RAID"; +static const char pci_device_8086_9641[] = "Integrated RAID"; +static const char pci_device_8086_96a1[] = "Integrated RAID"; +static const char pci_device_8086_b152[] = "21152 PCI-to-PCI Bridge"; +static const char pci_device_8086_b154[] = "21154 PCI-to-PCI Bridge"; +static const char pci_device_8086_b555[] = "21555 Non transparent PCI-to-PCI Bridge"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_b555_12c7_5005[] = "SS7HD PCI Adaptor Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_b555_12c7_5006[] = "SS7HDC cPCI Adaptor Card"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_b555_12d9_000a[] = "PCI VoIP Gateway"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_b555_4c53_1050[] = "CT7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_b555_4c53_1051[] = "CE7 mainboard"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_8086_b555_e4bf_1000[] = "CC8-1-BLUES"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8401[] = "TRENDware International Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8686[] = "ScaleMP"; +static const char pci_device_8686_1010[] = "vSMPowered system controller [vSMP CTL]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8800[] = "Trigem Computer Inc."; +static const char pci_device_8800_2008[] = "Video assistent component"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8866[] = "T-Square Design Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8888[] = "Silicon Magic"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8912[] = "TRX"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8c4a[] = "Winbond"; +static const char pci_device_8c4a_1980[] = "W89C940 misprogrammed [ne2k]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8e0e[] = "Computone Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_8e2e[] = "KTI"; +static const char pci_device_8e2e_3000[] = "ET32P2"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_9004[] = "Adaptec"; +static const char pci_device_9004_0078[] = "AHA-2940U_CN"; +static const char pci_device_9004_1078[] = "AIC-7810"; +static const char pci_device_9004_1160[] = "AIC-1160 [Family Fibre Channel Adapter]"; +static const char pci_device_9004_2178[] = "AIC-7821"; +static const char pci_device_9004_3860[] = "AHA-2930CU"; +static const char pci_device_9004_3b78[] = "AHA-4844W/4844UW"; +static const char pci_device_9004_5075[] = "AIC-755x"; +static const char pci_device_9004_5078[] = "AHA-7850"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_5078_9004_7850[] = "AHA-2904/Integrated AIC-7850"; +#endif +static const char pci_device_9004_5175[] = "AIC-755x"; +static const char pci_device_9004_5178[] = "AIC-7851"; +static const char pci_device_9004_5275[] = "AIC-755x"; +static const char pci_device_9004_5278[] = "AIC-7852"; +static const char pci_device_9004_5375[] = "AIC-755x"; +static const char pci_device_9004_5378[] = "AIC-7850"; +static const char pci_device_9004_5475[] = "AIC-755x"; +static const char pci_device_9004_5478[] = "AIC-7850"; +static const char pci_device_9004_5575[] = "AVA-2930"; +static const char pci_device_9004_5578[] = "AIC-7855"; +static const char pci_device_9004_5647[] = "ANA-7711 TCP Offload Engine"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_5647_9004_7710[] = "ANA-7711F TCP Offload Engine - Optical"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_5647_9004_7711[] = "ANA-7711LP TCP Offload Engine - Copper"; +#endif +static const char pci_device_9004_5675[] = "AIC-755x"; +static const char pci_device_9004_5678[] = "AIC-7856"; +static const char pci_device_9004_5775[] = "AIC-755x"; +static const char pci_device_9004_5778[] = "AIC-7850"; +static const char pci_device_9004_5800[] = "AIC-5800"; +static const char pci_device_9004_5900[] = "ANA-5910/5930/5940 ATM155 & 25 LAN Adapter"; +static const char pci_device_9004_5905[] = "ANA-5910A/5930A/5940A ATM Adapter"; +static const char pci_device_9004_6038[] = "AIC-3860"; +static const char pci_device_9004_6075[] = "AIC-1480 / APA-1480"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6075_9004_7560[] = "AIC-1480 / APA-1480 Cardbus"; +#endif +static const char pci_device_9004_6078[] = "AIC-7860"; +static const char pci_device_9004_6178[] = "AIC-7861"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6178_9004_7861[] = "AHA-2940AU Single"; +#endif +static const char pci_device_9004_6278[] = "AIC-7860"; +static const char pci_device_9004_6378[] = "AIC-7860"; +static const char pci_device_9004_6478[] = "AIC-786x"; +static const char pci_device_9004_6578[] = "AIC-786x"; +static const char pci_device_9004_6678[] = "AIC-786x"; +static const char pci_device_9004_6778[] = "AIC-786x"; +static const char pci_device_9004_6915[] = "ANA620xx/ANA69011A"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0008[] = "ANA69011A/TX 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0009[] = "ANA69011A/TX 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0010[] = "ANA62022 2-port 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0018[] = "ANA62044 4-port 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0019[] = "ANA62044 4-port 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0020[] = "ANA62022 2-port 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_0028[] = "ANA69011A/TX 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8008[] = "ANA69011A/TX 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8009[] = "ANA69011A/TX 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8010[] = "ANA62022 2-port 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8018[] = "ANA62044 4-port 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8019[] = "ANA62044 4-port 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8020[] = "ANA62022 2-port 64 bit 10/100"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_6915_9004_8028[] = "ANA69011A/TX 64 bit 10/100"; +#endif +static const char pci_device_9004_7078[] = "AHA-294x / AIC-7870"; +static const char pci_device_9004_7178[] = "AHA-2940/2940W / AIC-7871"; +static const char pci_device_9004_7278[] = "AHA-3940/3940W / AIC-7872"; +static const char pci_device_9004_7378[] = "AHA-3985 / AIC-7873"; +static const char pci_device_9004_7478[] = "AHA-2944/2944W / AIC-7874"; +static const char pci_device_9004_7578[] = "AHA-3944/3944W / AIC-7875"; +static const char pci_device_9004_7678[] = "AHA-4944W/UW / AIC-7876"; +static const char pci_device_9004_7710[] = "ANA-7711F Network Accelerator Card (NAC) - Optical"; +static const char pci_device_9004_7711[] = "ANA-7711C Network Accelerator Card (NAC) - Copper"; +static const char pci_device_9004_7778[] = "AIC-787x"; +static const char pci_device_9004_7810[] = "AIC-7810"; +static const char pci_device_9004_7815[] = "AIC-7815 RAID+Memory Controller IC"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7815_9004_7815[] = "ARO-1130U2 RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7815_9004_7840[] = "AIC-7815 RAID+Memory Controller IC"; +#endif +static const char pci_device_9004_7850[] = "AIC-7850"; +static const char pci_device_9004_7855[] = "AHA-2930"; +static const char pci_device_9004_7860[] = "AIC-7860"; +static const char pci_device_9004_7870[] = "AIC-7870"; +static const char pci_device_9004_7871[] = "AHA-2940"; +static const char pci_device_9004_7872[] = "AHA-3940"; +static const char pci_device_9004_7873[] = "AHA-3980"; +static const char pci_device_9004_7874[] = "AHA-2944"; +static const char pci_device_9004_7880[] = "AIC-7880P"; +static const char pci_device_9004_7890[] = "AIC-7890"; +static const char pci_device_9004_7891[] = "AIC-789x"; +static const char pci_device_9004_7892[] = "AIC-789x"; +static const char pci_device_9004_7893[] = "AIC-789x"; +static const char pci_device_9004_7894[] = "AIC-789x"; +static const char pci_device_9004_7895[] = "AHA-2940U/UW / AHA-39xx / AIC-7895"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7890[] = "AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7891[] = "AHA-2940U/2940UW Dual"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7892[] = "AHA-3940AU/AUW/AUWD/UWD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7894[] = "AHA-3944AUWD"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7895[] = "AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7896[] = "AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_7895_9004_7897[] = "AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B"; +#endif +static const char pci_device_9004_7896[] = "AIC-789x"; +static const char pci_device_9004_7897[] = "AIC-789x"; +static const char pci_device_9004_8078[] = "AIC-7880U"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_8078_9004_7880[] = "AIC-7880P Ultra/Ultra Wide SCSI Chipset"; +#endif +static const char pci_device_9004_8178[] = "AHA-2940U/UW/D / AIC-7881U"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_8178_9004_7881[] = "AHA-2940UW SCSI Host Adapter"; +#endif +static const char pci_device_9004_8278[] = "AHA-3940U/UW/UWD / AIC-7882U"; +static const char pci_device_9004_8378[] = "AHA-3940U/UW / AIC-7883U"; +static const char pci_device_9004_8478[] = "AHA-2944UW / AIC-7884U"; +static const char pci_device_9004_8578[] = "AHA-3944U/UWD / AIC-7885"; +static const char pci_device_9004_8678[] = "AHA-4944UW / AIC-7886"; +static const char pci_device_9004_8778[] = "AHA-2940UW Pro / AIC-788x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_8778_9004_7887[] = "2940UW Pro Ultra-Wide SCSI Controller"; +#endif +static const char pci_device_9004_8878[] = "AHA-2930UW / AIC-7888"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9004_8878_9004_7888[] = "AHA-2930UW SCSI Controller"; +#endif +static const char pci_device_9004_8b78[] = "ABA-1030"; +static const char pci_device_9004_ec78[] = "AHA-4944W/UW"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_9005[] = "Adaptec"; +static const char pci_device_9005_0010[] = "AHA-2940U2/U2W"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0010_9005_2180[] = "AHA-2940U2 SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0010_9005_8100[] = "AHA-2940U2B SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0010_9005_a100[] = "AHA-2940U2B SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0010_9005_a180[] = "AHA-2940U2W SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0010_9005_e100[] = "AHA-2950U2B SCSI Controller"; +#endif +static const char pci_device_9005_0011[] = "AHA-2930U2"; +static const char pci_device_9005_0013[] = "78902"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0013_9005_0003[] = "AAA-131U2 Array1000 1 Channel RAID Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0013_9005_000f[] = "AIC7890_ARO"; +#endif +static const char pci_device_9005_001f[] = "AHA-2940U2/U2W / 7890/7891"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_001f_9005_000f[] = "2940U2W SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_001f_9005_a180[] = "2940U2W SCSI Controller"; +#endif +static const char pci_device_9005_0020[] = "AIC-7890"; +static const char pci_device_9005_002f[] = "AIC-7890"; +static const char pci_device_9005_0030[] = "AIC-7890"; +static const char pci_device_9005_003f[] = "AIC-7890"; +static const char pci_device_9005_0050[] = "AHA-3940U2x/395U2x"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0050_9005_f500[] = "AHA-3950U2B"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0050_9005_ffff[] = "AHA-3950U2B"; +#endif +static const char pci_device_9005_0051[] = "AHA-3950U2D"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0051_9005_b500[] = "AHA-3950U2D"; +#endif +static const char pci_device_9005_0053[] = "AIC-7896 SCSI Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0053_9005_ffff[] = "AIC-7896 SCSI Controller mainboard implementation"; +#endif +static const char pci_device_9005_005f[] = "AIC-7896U2/7897U2"; +static const char pci_device_9005_0080[] = "AIC-7892A U160/m"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0080_0e11_e2a0[] = "Compaq 64-Bit/66MHz Wide Ultra3 SCSI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0080_9005_6220[] = "AHA-29160C"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0080_9005_62a0[] = "29160N Ultra160 SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0080_9005_e220[] = "29160LP Low Profile Ultra160 SCSI Controller"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0080_9005_e2a0[] = "29160 Ultra160 SCSI Controller"; +#endif +static const char pci_device_9005_0081[] = "AIC-7892B U160/m"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0081_9005_62a1[] = "19160 Ultra160 SCSI Controller"; +#endif +static const char pci_device_9005_0083[] = "AIC-7892D U160/m"; +static const char pci_device_9005_008f[] = "AIC-7892P U160/m"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_008f_1179_0001[] = "Magnia Z310"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_008f_15d9_9005[] = "Onboard SCSI Host Adapter"; +#endif +static const char pci_device_9005_00c0[] = "AHA-3960D / AIC-7899A U160/m"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00c0_0e11_f620[] = "Compaq 64-Bit/66MHz Dual Channel Wide Ultra3 SCSI Adapter"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00c0_9005_f620[] = "AHA-3960D U160/m"; +#endif +static const char pci_device_9005_00c1[] = "AIC-7899B U160/m"; +static const char pci_device_9005_00c3[] = "AIC-7899D U160/m"; +static const char pci_device_9005_00c5[] = "RAID subsystem HBA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00c5_1028_00c5[] = "PowerEdge 2400,2500,2550,4400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_9005_00cf[] = "AIC-7899P U160/m"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00cf_1028_00ce[] = "PowerEdge 1400"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00cf_1028_00d1[] = "PowerEdge 2550"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00cf_1028_00d9[] = "PowerEdge 2500"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00cf_10f1_2462[] = "Thunder K7 S2462"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00cf_15d9_9005[] = "Onboard SCSI Host Adapter"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_00cf_8086_3411[] = "SDS2 Mainboard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_9005_0241[] = "Serial ATA II RAID 1420SA"; +static const char pci_device_9005_0250[] = "ServeRAID Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0250_1014_0279[] = "ServeRAID-xx"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0250_1014_028c[] = "ServeRAID-xx"; +#endif +static const char pci_device_9005_0279[] = "ServeRAID 6M"; +static const char pci_device_9005_0283[] = "AAC-RAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0283_9005_0283[] = "Catapult"; +#endif +static const char pci_device_9005_0284[] = "AAC-RAID"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0284_9005_0284[] = "Tomcat"; +#endif +static const char pci_device_9005_0285[] = "AAC-RAID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_0e11_0295[] = "SATA 6Ch (Bearcat)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_1014_02f2[] = "ServeRAID 8i"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_1028_0287[] = "PowerEdge Expandable RAID Controller 320/DC"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_1028_0291[] = "CERC SATA RAID 2 PCI SATA 6ch (DellCorsair)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_103c_3227[] = "AAR-2610SA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_17aa_0286[] = "Legend S220 (Legend Crusader)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_17aa_0287[] = "Legend S230 (Legend Vulcan)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0285[] = "2200S (Vulcan)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0286[] = "2120S (Crusader)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0287[] = "2200S (Vulcan-2m)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0288[] = "3230S (Harrier)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0289[] = "3240S (Tornado)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_028a[] = "ASR-2020ZCR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_028b[] = "ASR-2025ZCR (Terminator)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_028e[] = "ASR-2020SA (Skyhawk)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_028f[] = "ASR-2025SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0290[] = "AAR-2410SA PCI SATA 4ch (Jaguar II)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0292[] = "AAR-2810SA PCI SATA 8ch (Corsair-8)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0293[] = "AAR-21610SA PCI SATA 16ch (Corsair-16)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0294[] = "ESD SO-DIMM PCI-X SATA ZCR (Prowler)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0296[] = "ASR-2240S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0297[] = "ASR-4005SAS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0298[] = "ASR-4000SAS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_0299[] = "ASR-4800SAS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_029a[] = "4805SAS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_02b5[] = "ASR5800"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_02b6[] = "ASR5805"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0285_9005_02b7[] = "ASR5808"; +#endif +static const char pci_device_9005_0286[] = "AAC-RAID (Rocket)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_1014_034d[] = "8s"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_1014_9540[] = "ServeRAID 8k/8k-l4"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_1014_9580[] = "ServeRAID 8k/8k-l8"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_028c[] = "ASR-2230S + ASR-2230SLP PCI-X (Lancer)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_028d[] = "ASR-2130S"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_029b[] = "ASR-2820SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_029c[] = "ASR-2620SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_029d[] = "ASR-2420SA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_029e[] = "ICP ICP9024R0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_029f[] = "ICP ICP9014R0"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_02a0[] = "ICP ICP9047MA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_02a1[] = "ICP ICP9087MA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_02a2[] = "3800SAS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_02a3[] = "ICP ICP5445AU"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_02a4[] = "ICP ICP9085LI"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_02a5[] = "ICP ICP5085BR"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_02a6[] = "ICP9067MA"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_02a7[] = "3805SAS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_02a8[] = "3400SAS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_02a9[] = "ICP ICP5085AU"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_02aa[] = "ICP ICP5045AU"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_02ac[] = "1800SAS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_02b3[] = "ASR-2400SAS"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_02b4[] = "ICP ICP5045AL"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0286_9005_0800[] = "Callisto"; +#endif +static const char pci_device_9005_0410[] = "AIC-9410W SAS (Razor HBA RAID)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0410_9005_0410[] = "ASC-48300(Spirit RAID)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0410_9005_0411[] = "ASC-58300 (Oakmont RAID)"; +#endif +static const char pci_device_9005_0412[] = "AIC-9410W SAS (Razor HBA non-RAID)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0412_9005_0412[] = "ASC-48300 (Spirit non-RAID)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0412_9005_0413[] = "ASC-58300 (Oakmont non-RAID)"; +#endif +static const char pci_device_9005_041e[] = "AIC-9410W SAS (Razor ASIC non-RAID)"; +static const char pci_device_9005_041f[] = "AIC-9410W SAS (Razor ASIC RAID)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_041f_9005_041f[] = "AIC-9410W SAS (Razor ASIC RAID)"; +#endif +static const char pci_device_9005_0430[] = "AIC-9405W SAS (Razor-Lite HBA RAID)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0430_9005_0430[] = "ASC-44300 (Spirit-Lite RAID)"; +#endif +static const char pci_device_9005_0432[] = "AIC-9405W SAS (Razor-Lite HBA non-RAID)"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0432_9005_0432[] = "ASC-44300 (Spirit-Lite non-RAID)"; +#endif +static const char pci_device_9005_043e[] = "AIC-9405W SAS (Razor-Lite ASIC non-RAID)"; +static const char pci_device_9005_043f[] = "AIC-9405W SAS (Razor-Lite ASIC RAID)"; +static const char pci_device_9005_0500[] = "Obsidian chipset SCSI controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0500_1014_02c1[] = "PCI-X DDR 3Gb SAS Adapter (572A/572C)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0500_1014_02c2[] = "PCI-X DDR 3Gb SAS RAID Adapter (572B/572D)"; +#endif +static const char pci_device_9005_0503[] = "Scamp chipset SCSI controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0503_1014_02bf[] = "Quad Channel PCI-X DDR U320 SCSI RAID Adapter (571E)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_0503_1014_02d5[] = "Quad Channel PCI-X DDR U320 SCSI RAID Adapter (571F)"; +#endif +static const char pci_device_9005_0910[] = "AUA-3100B"; +static const char pci_device_9005_091e[] = "AUA-3100B"; +static const char pci_device_9005_8000[] = "ASC-29320A U320"; +static const char pci_device_9005_800f[] = "AIC-7901 U320"; +static const char pci_device_9005_8010[] = "ASC-39320 U320"; +static const char pci_device_9005_8011[] = "ASC-39320D"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_8011_0e11_00ac[] = "ASC-39320D U320"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_8011_9005_0041[] = "ASC-39320D U320"; +#endif +static const char pci_device_9005_8012[] = "ASC-29320 U320"; +static const char pci_device_9005_8013[] = "ASC-29320B U320"; +static const char pci_device_9005_8014[] = "ASC-29320LP U320"; +static const char pci_device_9005_8015[] = "ASC-39320B U320"; +static const char pci_device_9005_8016[] = "ASC-39320A U320"; +static const char pci_device_9005_8017[] = "ASC-29320ALP U320"; +static const char pci_device_9005_801c[] = "ASC-39320D U320"; +static const char pci_device_9005_801d[] = "AIC-7902B U320"; +static const char pci_device_9005_801e[] = "AIC-7901A U320"; +static const char pci_device_9005_801f[] = "AIC-7902 U320"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9005_801f_1734_1011[] = "Primergy RX300"; +#endif +static const char pci_device_9005_8080[] = "ASC-29320A U320 w/HostRAID"; +static const char pci_device_9005_808f[] = "AIC-7901 U320 w/HostRAID"; +static const char pci_device_9005_8090[] = "ASC-39320 U320 w/HostRAID"; +static const char pci_device_9005_8091[] = "ASC-39320D U320 w/HostRAID"; +static const char pci_device_9005_8092[] = "ASC-29320 U320 w/HostRAID"; +static const char pci_device_9005_8093[] = "ASC-29320B U320 w/HostRAID"; +static const char pci_device_9005_8094[] = "ASC-29320LP U320 w/HostRAID"; +static const char pci_device_9005_8095[] = "ASC-39320(B) U320 w/HostRAID"; +static const char pci_device_9005_8096[] = "ASC-39320A U320 w/HostRAID"; +static const char pci_device_9005_8097[] = "ASC-29320ALP U320 w/HostRAID"; +static const char pci_device_9005_809c[] = "ASC-39320D(B) U320 w/HostRAID"; +static const char pci_device_9005_809d[] = "AIC-7902(B) U320 w/HostRAID"; +static const char pci_device_9005_809e[] = "AIC-7901A U320 w/HostRAID"; +static const char pci_device_9005_809f[] = "AIC-7902 U320 w/HostRAID"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_907f[] = "Atronics"; +static const char pci_device_907f_2015[] = "IDE-2015PL"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_919a[] = "Gigapixel Corp"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_9412[] = "Holtek"; +static const char pci_device_9412_6565[] = "6565"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_9699[] = "Omni Media Technology Inc"; +static const char pci_device_9699_6565[] = "6565"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_9710[] = "NetMos Technology"; +static const char pci_device_9710_7780[] = "USB IRDA-port"; +static const char pci_device_9710_9805[] = "PCI 1 port parallel adapter"; +static const char pci_device_9710_9815[] = "PCI 9815 Multi-I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9710_9815_1000_0020[] = "2P0S (2 port parallel adaptor)"; +#endif +static const char pci_device_9710_9835[] = "PCI 9835 Multi-I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9710_9835_1000_0002[] = "2S (16C550 UART)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9710_9835_1000_0012[] = "1P2S"; +#endif +static const char pci_device_9710_9845[] = "PCI 9845 Multi-I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9710_9845_1000_0004[] = "0P4S (4 port 16550A serial card)"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9710_9845_1000_0006[] = "0P6S (6 port 16550a serial card)"; +#endif +static const char pci_device_9710_9855[] = "PCI 9855 Multi-I/O Controller"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_9710_9855_1000_0014[] = "1P4S"; +#endif +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_9902[] = "Stargen Inc."; +static const char pci_device_9902_0001[] = "SG2010 PCI over Starfabric Bridge"; +static const char pci_device_9902_0002[] = "SG2010 PCI to Starfabric Gateway"; +static const char pci_device_9902_0003[] = "SG1010 Starfabric Switch and PCI Bridge"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_a0a0[] = "AOPEN Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_a0f1[] = "UNISYS Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_a200[] = "NEC Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_a259[] = "Hewlett Packard"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_a25b[] = "Hewlett Packard GmbH PL24-MKT"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_a304[] = "Sony"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_a727[] = "3Com Corporation"; +static const char pci_device_a727_0013[] = "3CRPAG175 Wireless PC Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_aa42[] = "Scitex Digital Video"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ac1e[] = "Digital Receiver Technology Inc"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ac3d[] = "Actuality Systems"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_aecb[] = "Adrienne Electronics Corporation"; +static const char pci_device_aecb_6250[] = "VITC/LTC Timecode Reader card [PCI-VLTC/RDR]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_affe[] = "Sirrix AG security technologies"; +static const char pci_device_affe_02e1[] = "PCI2E1 2-port ISDN E1 interface"; +static const char pci_device_affe_dead[] = "Sirrix.PCI4S0 4-port ISDN S0 interface"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_b10b[] = "Uakron PCI Project"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_b1b3[] = "Shiva Europe Limited"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_bd11[] = "Pinnacle Systems, Inc. (Wrong ID)"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_c001[] = "TSI Telsys"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_c0a9[] = "Micron/Crucial Technology"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_c0de[] = "Motorola"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_c0fe[] = "Motion Engineering, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ca50[] = "Varian Australia Pty Ltd"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_cafe[] = "Chrysalis-ITS"; +static const char pci_device_cafe_0003[] = "Luna K3 Hardware Security Module"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_cccc[] = "Catapult Communications"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ccec[] = "Curtiss-Wright Controls Embedded Computing"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_cddd[] = "Tyzx, Inc."; +static const char pci_device_cddd_0101[] = "DeepSea 1 High Speed Stereo Vision Frame Grabber"; +static const char pci_device_cddd_0200[] = "DeepSea 2 High Speed Stereo Vision Frame Grabber"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_d161[] = "Digium, Inc."; +static const char pci_device_d161_0205[] = "Wildcard TE205P"; +static const char pci_device_d161_0210[] = "Wildcard TE210P"; +static const char pci_device_d161_0405[] = "Wildcard TE405P Quad-Span togglable E1/T1/J1 card 5.0v"; +static const char pci_device_d161_0406[] = "Wildcard TE406P Quad-Span togglable E1/T1/J1 echo cancellation card 5.0v"; +static const char pci_device_d161_0410[] = "Wildcard TE410P Quad-Span togglable E1/T1/J1 card 3.3v"; +static const char pci_device_d161_0411[] = "Wildcard TE411P Quad-Span togglable E1/T1/J1 echo cancellation card 3.3v"; +static const char pci_device_d161_2400[] = "Wildcard TDM2400P"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_d4d4[] = "Dy4 Systems Inc"; +static const char pci_device_d4d4_0601[] = "PCI Mezzanine Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_d531[] = "I+ME ACTIA GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_d84d[] = "Exsys"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_dead[] = "Indigita Corporation"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_deaf[] = "Middle Digital Inc."; +static const char pci_device_deaf_9050[] = "PC Weasel Virtual VGA"; +static const char pci_device_deaf_9051[] = "PC Weasel Serial Port"; +static const char pci_device_deaf_9052[] = "PC Weasel Watchdog Timer"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_e000[] = "Winbond"; +static const char pci_device_e000_e000[] = "W89C940"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_e159[] = "Tiger Jet Network Inc."; +static const char pci_device_e159_0001[] = "Tiger3XX Modem/ISDN interface"; +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_e159_0001_0059_0001[] = "128k ISDN-S/T Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_e159_0001_0059_0003[] = "128k ISDN-U Adapter"; +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_e159_0001_00a7_0001[] = "TELES.S0/PCI 2.x ISDN Adapter"; +#endif +#endif +#ifdef INIT_SUBSYS_INFO +static const char pci_subsys_e159_0001_8086_0003[] = "Digium X100P/X101P analogue PSTN FXO interface"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_device_e159_0002[] = "Tiger100APC ISDN chipset"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_e4bf[] = "EKF Elektronik GmbH"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_e55e[] = "Essence Technology, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ea01[] = "Eagle Technology"; +static const char pci_device_ea01_000a[] = "PCI-773 Temperature Card"; +static const char pci_device_ea01_0032[] = "PCI-730 & PC104P-30 Card"; +static const char pci_device_ea01_003e[] = "PCI-762 Opto-Isolator Card"; +static const char pci_device_ea01_0041[] = "PCI-763 Reed Relay Card"; +static const char pci_device_ea01_0043[] = "PCI-769 Opto-Isolator Reed Relay Combo Card"; +static const char pci_device_ea01_0046[] = "PCI-766 Analog Output Card"; +static const char pci_device_ea01_0052[] = "PCI-703 Analog I/O Card"; +static const char pci_device_ea01_0800[] = "PCI-800 Digital I/O Card"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ea60[] = "RME"; +static const char pci_device_ea60_9896[] = "Digi32"; +static const char pci_device_ea60_9897[] = "Digi32 Pro"; +static const char pci_device_ea60_9898[] = "Digi32/8"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_eabb[] = "Aashima Technology B.V."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_eace[] = "Endace Measurement Systems, Ltd"; +static const char pci_device_eace_3100[] = "DAG 3.10 OC-3/OC-12"; +static const char pci_device_eace_3200[] = "DAG 3.2x OC-3/OC-12"; +static const char pci_device_eace_320e[] = "DAG 3.2E Fast Ethernet"; +static const char pci_device_eace_340e[] = "DAG 3.4E Fast Ethernet"; +static const char pci_device_eace_341e[] = "DAG 3.41E Fast Ethernet"; +static const char pci_device_eace_3500[] = "DAG 3.5 OC-3/OC-12"; +static const char pci_device_eace_351c[] = "DAG 3.5ECM Fast Ethernet"; +static const char pci_device_eace_4100[] = "DAG 4.10 OC-48"; +static const char pci_device_eace_4110[] = "DAG 4.11 OC-48"; +static const char pci_device_eace_4220[] = "DAG 4.2 OC-48"; +static const char pci_device_eace_422e[] = "DAG 4.2E Dual Gigabit Ethernet"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ec80[] = "Belkin Corporation"; +static const char pci_device_ec80_ec00[] = "F5D6000"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ecc0[] = "Echo Digital Audio Corporation"; +#endif +static const char pci_vendor_edd8[] = "ARK Logic Inc"; +static const char pci_device_edd8_a091[] = "1000PV [Stingray]"; +static const char pci_device_edd8_a099[] = "2000PV [Stingray]"; +static const char pci_device_edd8_a0a1[] = "2000MT"; +static const char pci_device_edd8_a0a9[] = "2000MI"; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_f1d0[] = "AJA Video"; +static const char pci_device_f1d0_c0fe[] = "Xena HS/HD-R"; +static const char pci_device_f1d0_c0ff[] = "Kona/Xena 2"; +static const char pci_device_f1d0_cafe[] = "Kona SD"; +static const char pci_device_f1d0_cfee[] = "Xena LS/SD-22-DA/SD-DA"; +static const char pci_device_f1d0_dcaf[] = "Kona HD"; +static const char pci_device_f1d0_dfee[] = "Xena HD-DA"; +static const char pci_device_f1d0_efac[] = "Xena SD-MM/SD-22-MM"; +static const char pci_device_f1d0_facd[] = "Xena HD-MM"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_fa57[] = "Interagon AS"; +static const char pci_device_fa57_0001[] = "PMC [Pattern Matching Chip]"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_fab7[] = "Fabric7 Systems, Inc."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_febd[] = "Ultraview Corp."; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_feda[] = "Broadcom Inc"; +static const char pci_device_feda_a0fa[] = "BCM4210 iLine10 HomePNA 2.0"; +static const char pci_device_feda_a10e[] = "BCM4230 iLine10 HomePNA 2.0"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_fede[] = "Fedetec Inc."; +static const char pci_device_fede_0003[] = "TABIC PCI v3"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_fffd[] = "XenSource, Inc."; +static const char pci_device_fffd_0101[] = "PCI Event Channel Controller"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_fffe[] = "VMWare Inc"; +static const char pci_device_fffe_0405[] = "Virtual SVGA 4.0"; +static const char pci_device_fffe_0710[] = "Virtual SVGA"; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const char pci_vendor_ffff[] = "Illegal Vendor ID"; +#endif +#ifdef INIT_SUBSYS_INFO +static const pciSubsystemInfo pci_ss_info_0e11_0046_0e11_409a = + {0x0e11, 0x409a, pci_subsys_0e11_0046_0e11_409a, 0}; +#undef pci_ss_info_0e11_409a +#define pci_ss_info_0e11_409a pci_ss_info_0e11_0046_0e11_409a +static const pciSubsystemInfo pci_ss_info_0e11_0046_0e11_409b = + {0x0e11, 0x409b, pci_subsys_0e11_0046_0e11_409b, 0}; +#undef pci_ss_info_0e11_409b +#define pci_ss_info_0e11_409b pci_ss_info_0e11_0046_0e11_409b +static const pciSubsystemInfo pci_ss_info_0e11_0046_0e11_409c = + {0x0e11, 0x409c, pci_subsys_0e11_0046_0e11_409c, 0}; +#undef pci_ss_info_0e11_409c +#define pci_ss_info_0e11_409c pci_ss_info_0e11_0046_0e11_409c +static const pciSubsystemInfo pci_ss_info_0e11_0046_0e11_409d = + {0x0e11, 0x409d, pci_subsys_0e11_0046_0e11_409d, 0}; +#undef pci_ss_info_0e11_409d +#define pci_ss_info_0e11_409d pci_ss_info_0e11_0046_0e11_409d +static const pciSubsystemInfo pci_ss_info_0e11_a0f7_8086_002a = + {0x8086, 0x002a, pci_subsys_0e11_a0f7_8086_002a, 0}; +#undef pci_ss_info_8086_002a +#define pci_ss_info_8086_002a pci_ss_info_0e11_a0f7_8086_002a +static const pciSubsystemInfo pci_ss_info_0e11_a0f7_8086_002b = + {0x8086, 0x002b, pci_subsys_0e11_a0f7_8086_002b, 0}; +#undef pci_ss_info_8086_002b +#define pci_ss_info_8086_002b pci_ss_info_0e11_a0f7_8086_002b +static const pciSubsystemInfo pci_ss_info_0e11_ae10_0e11_4030 = + {0x0e11, 0x4030, pci_subsys_0e11_ae10_0e11_4030, 0}; +#undef pci_ss_info_0e11_4030 +#define pci_ss_info_0e11_4030 pci_ss_info_0e11_ae10_0e11_4030 +static const pciSubsystemInfo pci_ss_info_0e11_ae10_0e11_4031 = + {0x0e11, 0x4031, pci_subsys_0e11_ae10_0e11_4031, 0}; +#undef pci_ss_info_0e11_4031 +#define pci_ss_info_0e11_4031 pci_ss_info_0e11_ae10_0e11_4031 +static const pciSubsystemInfo pci_ss_info_0e11_ae10_0e11_4032 = + {0x0e11, 0x4032, pci_subsys_0e11_ae10_0e11_4032, 0}; +#undef pci_ss_info_0e11_4032 +#define pci_ss_info_0e11_4032 pci_ss_info_0e11_ae10_0e11_4032 +static const pciSubsystemInfo pci_ss_info_0e11_ae10_0e11_4033 = + {0x0e11, 0x4033, pci_subsys_0e11_ae10_0e11_4033, 0}; +#undef pci_ss_info_0e11_4033 +#define pci_ss_info_0e11_4033 pci_ss_info_0e11_ae10_0e11_4033 +static const pciSubsystemInfo pci_ss_info_0e11_b178_0e11_4080 = + {0x0e11, 0x4080, pci_subsys_0e11_b178_0e11_4080, 0}; +#undef pci_ss_info_0e11_4080 +#define pci_ss_info_0e11_4080 pci_ss_info_0e11_b178_0e11_4080 +static const pciSubsystemInfo pci_ss_info_0e11_b178_0e11_4082 = + {0x0e11, 0x4082, pci_subsys_0e11_b178_0e11_4082, 0}; +#undef pci_ss_info_0e11_4082 +#define pci_ss_info_0e11_4082 pci_ss_info_0e11_b178_0e11_4082 +static const pciSubsystemInfo pci_ss_info_0e11_b178_0e11_4083 = + {0x0e11, 0x4083, pci_subsys_0e11_b178_0e11_4083, 0}; +#undef pci_ss_info_0e11_4083 +#define pci_ss_info_0e11_4083 pci_ss_info_0e11_b178_0e11_4083 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0001_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0001_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0001_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0003_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0003_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0003_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0006_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0006_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0006_1000_1000 +#endif +static const pciSubsystemInfo pci_ss_info_1000_000a_0e11_b143 = + {0x0e11, 0xb143, pci_subsys_1000_000a_0e11_b143, 0}; +#undef pci_ss_info_0e11_b143 +#define pci_ss_info_0e11_b143 pci_ss_info_1000_000a_0e11_b143 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_000a_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_000a_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_000a_1000_1000 +#endif +static const pciSubsystemInfo pci_ss_info_1000_000b_0e11_6004 = + {0x0e11, 0x6004, pci_subsys_1000_000b_0e11_6004, 0}; +#undef pci_ss_info_0e11_6004 +#define pci_ss_info_0e11_6004 pci_ss_info_1000_000b_0e11_6004 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_000b_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_000b_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_000b_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_000b_1000_1010 = + {0x1000, 0x1010, pci_subsys_1000_000b_1000_1010, 0}; +#undef pci_ss_info_1000_1010 +#define pci_ss_info_1000_1010 pci_ss_info_1000_000b_1000_1010 +static const pciSubsystemInfo pci_ss_info_1000_000b_1000_1020 = + {0x1000, 0x1020, pci_subsys_1000_000b_1000_1020, 0}; +#undef pci_ss_info_1000_1020 +#define pci_ss_info_1000_1020 pci_ss_info_1000_000b_1000_1020 +static const pciSubsystemInfo pci_ss_info_1000_000b_13e9_1000 = + {0x13e9, 0x1000, pci_subsys_1000_000b_13e9_1000, 0}; +#undef pci_ss_info_13e9_1000 +#define pci_ss_info_13e9_1000 pci_ss_info_1000_000b_13e9_1000 +static const pciSubsystemInfo pci_ss_info_1000_000c_1000_1010 = + {0x1000, 0x1010, pci_subsys_1000_000c_1000_1010, 0}; +#undef pci_ss_info_1000_1010 +#define pci_ss_info_1000_1010 pci_ss_info_1000_000c_1000_1010 +static const pciSubsystemInfo pci_ss_info_1000_000c_1000_1020 = + {0x1000, 0x1020, pci_subsys_1000_000c_1000_1020, 0}; +#undef pci_ss_info_1000_1020 +#define pci_ss_info_1000_1020 pci_ss_info_1000_000c_1000_1020 +static const pciSubsystemInfo pci_ss_info_1000_000c_1de1_3906 = + {0x1de1, 0x3906, pci_subsys_1000_000c_1de1_3906, 0}; +#undef pci_ss_info_1de1_3906 +#define pci_ss_info_1de1_3906 pci_ss_info_1000_000c_1de1_3906 +static const pciSubsystemInfo pci_ss_info_1000_000c_1de1_3907 = + {0x1de1, 0x3907, pci_subsys_1000_000c_1de1_3907, 0}; +#undef pci_ss_info_1de1_3907 +#define pci_ss_info_1de1_3907 pci_ss_info_1000_000c_1de1_3907 +#endif +static const pciSubsystemInfo pci_ss_info_1000_000f_0e11_7004 = + {0x0e11, 0x7004, pci_subsys_1000_000f_0e11_7004, 0}; +#undef pci_ss_info_0e11_7004 +#define pci_ss_info_0e11_7004 pci_ss_info_1000_000f_0e11_7004 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_000f_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_000f_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_000f_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_000f_1000_1010 = + {0x1000, 0x1010, pci_subsys_1000_000f_1000_1010, 0}; +#undef pci_ss_info_1000_1010 +#define pci_ss_info_1000_1010 pci_ss_info_1000_000f_1000_1010 +static const pciSubsystemInfo pci_ss_info_1000_000f_1000_1020 = + {0x1000, 0x1020, pci_subsys_1000_000f_1000_1020, 0}; +#undef pci_ss_info_1000_1020 +#define pci_ss_info_1000_1020 pci_ss_info_1000_000f_1000_1020 +#endif +static const pciSubsystemInfo pci_ss_info_1000_000f_1092_8760 = + {0x1092, 0x8760, pci_subsys_1000_000f_1092_8760, 0}; +#undef pci_ss_info_1092_8760 +#define pci_ss_info_1092_8760 pci_ss_info_1000_000f_1092_8760 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_000f_1775_10d0 = + {0x1775, 0x10d0, pci_subsys_1000_000f_1775_10d0, 0}; +#undef pci_ss_info_1775_10d0 +#define pci_ss_info_1775_10d0 pci_ss_info_1000_000f_1775_10d0 +static const pciSubsystemInfo pci_ss_info_1000_000f_1775_10d1 = + {0x1775, 0x10d1, pci_subsys_1000_000f_1775_10d1, 0}; +#undef pci_ss_info_1775_10d1 +#define pci_ss_info_1775_10d1 pci_ss_info_1000_000f_1775_10d1 +static const pciSubsystemInfo pci_ss_info_1000_000f_1de1_3904 = + {0x1de1, 0x3904, pci_subsys_1000_000f_1de1_3904, 0}; +#undef pci_ss_info_1de1_3904 +#define pci_ss_info_1de1_3904 pci_ss_info_1000_000f_1de1_3904 +static const pciSubsystemInfo pci_ss_info_1000_000f_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_1000_000f_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_1000_000f_4c53_1000 +static const pciSubsystemInfo pci_ss_info_1000_000f_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_1000_000f_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_1000_000f_4c53_1050 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0010_0e11_4040 = + {0x0e11, 0x4040, pci_subsys_1000_0010_0e11_4040, 0}; +#undef pci_ss_info_0e11_4040 +#define pci_ss_info_0e11_4040 pci_ss_info_1000_0010_0e11_4040 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0010_0e11_4048 = + {0x0e11, 0x4048, pci_subsys_1000_0010_0e11_4048, 0}; +#undef pci_ss_info_0e11_4048 +#define pci_ss_info_0e11_4048 pci_ss_info_1000_0010_0e11_4048 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0010_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0010_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0010_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0012_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0012_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0012_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0013_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0013_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0013_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0020_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0020_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0020_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0020_107b_1040 = + {0x107b, 0x1040, pci_subsys_1000_0020_107b_1040, 0}; +#undef pci_ss_info_107b_1040 +#define pci_ss_info_107b_1040 pci_ss_info_1000_0020_107b_1040 +static const pciSubsystemInfo pci_ss_info_1000_0020_1de1_1020 = + {0x1de1, 0x1020, pci_subsys_1000_0020_1de1_1020, 0}; +#undef pci_ss_info_1de1_1020 +#define pci_ss_info_1de1_1020 pci_ss_info_1000_0020_1de1_1020 +static const pciSubsystemInfo pci_ss_info_1000_0021_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0021_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0021_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0021_1000_1010 = + {0x1000, 0x1010, pci_subsys_1000_0021_1000_1010, 0}; +#undef pci_ss_info_1000_1010 +#define pci_ss_info_1000_1010 pci_ss_info_1000_0021_1000_1010 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0021_103c_1330 = + {0x103c, 0x1330, pci_subsys_1000_0021_103c_1330, 0}; +#undef pci_ss_info_103c_1330 +#define pci_ss_info_103c_1330 pci_ss_info_1000_0021_103c_1330 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0021_103c_1340 = + {0x103c, 0x1340, pci_subsys_1000_0021_103c_1340, 0}; +#undef pci_ss_info_103c_1340 +#define pci_ss_info_103c_1340 pci_ss_info_1000_0021_103c_1340 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0021_124b_1070 = + {0x124b, 0x1070, pci_subsys_1000_0021_124b_1070, 0}; +#undef pci_ss_info_124b_1070 +#define pci_ss_info_124b_1070 pci_ss_info_1000_0021_124b_1070 +static const pciSubsystemInfo pci_ss_info_1000_0021_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_1000_0021_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_1000_0021_4c53_1080 +static const pciSubsystemInfo pci_ss_info_1000_0021_4c53_1300 = + {0x4c53, 0x1300, pci_subsys_1000_0021_4c53_1300, 0}; +#undef pci_ss_info_4c53_1300 +#define pci_ss_info_4c53_1300 pci_ss_info_1000_0021_4c53_1300 +static const pciSubsystemInfo pci_ss_info_1000_0021_4c53_1310 = + {0x4c53, 0x1310, pci_subsys_1000_0021_4c53_1310, 0}; +#undef pci_ss_info_4c53_1310 +#define pci_ss_info_4c53_1310 pci_ss_info_1000_0021_4c53_1310 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_0e11_00da = + {0x0e11, 0x00da, pci_subsys_1000_0030_0e11_00da, 0}; +#undef pci_ss_info_0e11_00da +#define pci_ss_info_0e11_00da pci_ss_info_1000_0030_0e11_00da +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_1028_0123 = + {0x1028, 0x0123, pci_subsys_1000_0030_1028_0123, 0}; +#undef pci_ss_info_1028_0123 +#define pci_ss_info_1028_0123 pci_ss_info_1000_0030_1028_0123 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_1028_014a = + {0x1028, 0x014a, pci_subsys_1000_0030_1028_014a, 0}; +#undef pci_ss_info_1028_014a +#define pci_ss_info_1028_014a pci_ss_info_1000_0030_1028_014a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_1028_016c = + {0x1028, 0x016c, pci_subsys_1000_0030_1028_016c, 0}; +#undef pci_ss_info_1028_016c +#define pci_ss_info_1028_016c pci_ss_info_1000_0030_1028_016c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_1028_0183 = + {0x1028, 0x0183, pci_subsys_1000_0030_1028_0183, 0}; +#undef pci_ss_info_1028_0183 +#define pci_ss_info_1028_0183 pci_ss_info_1000_0030_1028_0183 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_1028_1010 = + {0x1028, 0x1010, pci_subsys_1000_0030_1028_1010, 0}; +#undef pci_ss_info_1028_1010 +#define pci_ss_info_1028_1010 pci_ss_info_1000_0030_1028_1010 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0030_103c_12c5 = + {0x103c, 0x12c5, pci_subsys_1000_0030_103c_12c5, 0}; +#undef pci_ss_info_103c_12c5 +#define pci_ss_info_103c_12c5 pci_ss_info_1000_0030_103c_12c5 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0030_124b_1170 = + {0x124b, 0x1170, pci_subsys_1000_0030_124b_1170, 0}; +#undef pci_ss_info_124b_1170 +#define pci_ss_info_124b_1170 pci_ss_info_1000_0030_124b_1170 +static const pciSubsystemInfo pci_ss_info_1000_0030_1734_1052 = + {0x1734, 0x1052, pci_subsys_1000_0030_1734_1052, 0}; +#undef pci_ss_info_1734_1052 +#define pci_ss_info_1734_1052 pci_ss_info_1000_0030_1734_1052 +static const pciSubsystemInfo pci_ss_info_1000_0032_1000_1000 = + {0x1000, 0x1000, pci_subsys_1000_0032_1000_1000, 0}; +#undef pci_ss_info_1000_1000 +#define pci_ss_info_1000_1000 pci_ss_info_1000_0032_1000_1000 +static const pciSubsystemInfo pci_ss_info_1000_0040_1000_0033 = + {0x1000, 0x0033, pci_subsys_1000_0040_1000_0033, 0}; +#undef pci_ss_info_1000_0033 +#define pci_ss_info_1000_0033 pci_ss_info_1000_0040_1000_0033 +static const pciSubsystemInfo pci_ss_info_1000_0040_1000_0066 = + {0x1000, 0x0066, pci_subsys_1000_0040_1000_0066, 0}; +#undef pci_ss_info_1000_0066 +#define pci_ss_info_1000_0066 pci_ss_info_1000_0040_1000_0066 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0060_1028_1f0a = + {0x1028, 0x1f0a, pci_subsys_1000_0060_1028_1f0a, 0}; +#undef pci_ss_info_1028_1f0a +#define pci_ss_info_1028_1f0a pci_ss_info_1000_0060_1028_1f0a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0060_1028_1f0b = + {0x1028, 0x1f0b, pci_subsys_1000_0060_1028_1f0b, 0}; +#undef pci_ss_info_1028_1f0b +#define pci_ss_info_1028_1f0b pci_ss_info_1000_0060_1028_1f0b +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0060_1028_1f0c = + {0x1028, 0x1f0c, pci_subsys_1000_0060_1028_1f0c, 0}; +#undef pci_ss_info_1028_1f0c +#define pci_ss_info_1028_1f0c pci_ss_info_1000_0060_1028_1f0c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0060_1028_1f0d = + {0x1028, 0x1f0d, pci_subsys_1000_0060_1028_1f0d, 0}; +#undef pci_ss_info_1028_1f0d +#define pci_ss_info_1028_1f0d pci_ss_info_1000_0060_1028_1f0d +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0062_1000_0062 = + {0x1000, 0x0062, pci_subsys_1000_0062_1000_0062, 0}; +#undef pci_ss_info_1000_0062 +#define pci_ss_info_1000_0062 pci_ss_info_1000_0062_1000_0062 +#endif +static const pciSubsystemInfo pci_ss_info_1000_008f_1092_8000 = + {0x1092, 0x8000, pci_subsys_1000_008f_1092_8000, 0}; +#undef pci_ss_info_1092_8000 +#define pci_ss_info_1092_8000 pci_ss_info_1000_008f_1092_8000 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_008f_1092_8760 = + {0x1092, 0x8760, pci_subsys_1000_008f_1092_8760, 0}; +#undef pci_ss_info_1092_8760 +#define pci_ss_info_1092_8760 pci_ss_info_1000_008f_1092_8760 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0407_1000_0530 = + {0x1000, 0x0530, pci_subsys_1000_0407_1000_0530, 0}; +#undef pci_ss_info_1000_0530 +#define pci_ss_info_1000_0530 pci_ss_info_1000_0407_1000_0530 +static const pciSubsystemInfo pci_ss_info_1000_0407_1000_0531 = + {0x1000, 0x0531, pci_subsys_1000_0407_1000_0531, 0}; +#undef pci_ss_info_1000_0531 +#define pci_ss_info_1000_0531 pci_ss_info_1000_0407_1000_0531 +static const pciSubsystemInfo pci_ss_info_1000_0407_1000_0532 = + {0x1000, 0x0532, pci_subsys_1000_0407_1000_0532, 0}; +#undef pci_ss_info_1000_0532 +#define pci_ss_info_1000_0532 pci_ss_info_1000_0407_1000_0532 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0407_1028_0531 = + {0x1028, 0x0531, pci_subsys_1000_0407_1028_0531, 0}; +#undef pci_ss_info_1028_0531 +#define pci_ss_info_1028_0531 pci_ss_info_1000_0407_1028_0531 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0407_1028_0533 = + {0x1028, 0x0533, pci_subsys_1000_0407_1028_0533, 0}; +#undef pci_ss_info_1028_0533 +#define pci_ss_info_1028_0533 pci_ss_info_1000_0407_1028_0533 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0407_8086_0530 = + {0x8086, 0x0530, pci_subsys_1000_0407_8086_0530, 0}; +#undef pci_ss_info_8086_0530 +#define pci_ss_info_8086_0530 pci_ss_info_1000_0407_8086_0530 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0407_8086_0532 = + {0x8086, 0x0532, pci_subsys_1000_0407_8086_0532, 0}; +#undef pci_ss_info_8086_0532 +#define pci_ss_info_8086_0532 pci_ss_info_1000_0407_8086_0532 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0408_1000_0001 = + {0x1000, 0x0001, pci_subsys_1000_0408_1000_0001, 0}; +#undef pci_ss_info_1000_0001 +#define pci_ss_info_1000_0001 pci_ss_info_1000_0408_1000_0001 +static const pciSubsystemInfo pci_ss_info_1000_0408_1000_0002 = + {0x1000, 0x0002, pci_subsys_1000_0408_1000_0002, 0}; +#undef pci_ss_info_1000_0002 +#define pci_ss_info_1000_0002 pci_ss_info_1000_0408_1000_0002 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0408_1025_004d = + {0x1025, 0x004d, pci_subsys_1000_0408_1025_004d, 0}; +#undef pci_ss_info_1025_004d +#define pci_ss_info_1025_004d pci_ss_info_1000_0408_1025_004d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0408_1028_0001 = + {0x1028, 0x0001, pci_subsys_1000_0408_1028_0001, 0}; +#undef pci_ss_info_1028_0001 +#define pci_ss_info_1028_0001 pci_ss_info_1000_0408_1028_0001 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0408_1028_0002 = + {0x1028, 0x0002, pci_subsys_1000_0408_1028_0002, 0}; +#undef pci_ss_info_1028_0002 +#define pci_ss_info_1028_0002 pci_ss_info_1000_0408_1028_0002 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0408_1734_1065 = + {0x1734, 0x1065, pci_subsys_1000_0408_1734_1065, 0}; +#undef pci_ss_info_1734_1065 +#define pci_ss_info_1734_1065 pci_ss_info_1000_0408_1734_1065 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0408_8086_0002 = + {0x8086, 0x0002, pci_subsys_1000_0408_8086_0002, 0}; +#undef pci_ss_info_8086_0002 +#define pci_ss_info_8086_0002 pci_ss_info_1000_0408_8086_0002 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0409_1000_3004 = + {0x1000, 0x3004, pci_subsys_1000_0409_1000_3004, 0}; +#undef pci_ss_info_1000_3004 +#define pci_ss_info_1000_3004 pci_ss_info_1000_0409_1000_3004 +static const pciSubsystemInfo pci_ss_info_1000_0409_1000_3008 = + {0x1000, 0x3008, pci_subsys_1000_0409_1000_3008, 0}; +#undef pci_ss_info_1000_3008 +#define pci_ss_info_1000_3008 pci_ss_info_1000_0409_1000_3008 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0409_8086_3008 = + {0x8086, 0x3008, pci_subsys_1000_0409_8086_3008, 0}; +#undef pci_ss_info_8086_3008 +#define pci_ss_info_8086_3008 pci_ss_info_1000_0409_8086_3008 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0409_8086_3431 = + {0x8086, 0x3431, pci_subsys_1000_0409_8086_3431, 0}; +#undef pci_ss_info_8086_3431 +#define pci_ss_info_8086_3431 pci_ss_info_1000_0409_8086_3431 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0409_8086_3499 = + {0x8086, 0x3499, pci_subsys_1000_0409_8086_3499, 0}; +#undef pci_ss_info_8086_3499 +#define pci_ss_info_8086_3499 pci_ss_info_1000_0409_8086_3499 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0411_1000_1001 = + {0x1000, 0x1001, pci_subsys_1000_0411_1000_1001, 0}; +#undef pci_ss_info_1000_1001 +#define pci_ss_info_1000_1001 pci_ss_info_1000_0411_1000_1001 +static const pciSubsystemInfo pci_ss_info_1000_0411_1000_1002 = + {0x1000, 0x1002, pci_subsys_1000_0411_1000_1002, 0}; +#undef pci_ss_info_1000_1002 +#define pci_ss_info_1000_1002 pci_ss_info_1000_0411_1000_1002 +static const pciSubsystemInfo pci_ss_info_1000_0411_1000_1003 = + {0x1000, 0x1003, pci_subsys_1000_0411_1000_1003, 0}; +#undef pci_ss_info_1000_1003 +#define pci_ss_info_1000_1003 pci_ss_info_1000_0411_1000_1003 +static const pciSubsystemInfo pci_ss_info_1000_0411_1000_1004 = + {0x1000, 0x1004, pci_subsys_1000_0411_1000_1004, 0}; +#undef pci_ss_info_1000_1004 +#define pci_ss_info_1000_1004 pci_ss_info_1000_0411_1000_1004 +static const pciSubsystemInfo pci_ss_info_1000_0411_1000_100c = + {0x1000, 0x100c, pci_subsys_1000_0411_1000_100c, 0}; +#undef pci_ss_info_1000_100c +#define pci_ss_info_1000_100c pci_ss_info_1000_0411_1000_100c +static const pciSubsystemInfo pci_ss_info_1000_0411_1000_100d = + {0x1000, 0x100d, pci_subsys_1000_0411_1000_100d, 0}; +#undef pci_ss_info_1000_100d +#define pci_ss_info_1000_100d pci_ss_info_1000_0411_1000_100d +static const pciSubsystemInfo pci_ss_info_1000_0411_1000_2004 = + {0x1000, 0x2004, pci_subsys_1000_0411_1000_2004, 0}; +#undef pci_ss_info_1000_2004 +#define pci_ss_info_1000_2004 pci_ss_info_1000_0411_1000_2004 +static const pciSubsystemInfo pci_ss_info_1000_0411_1000_2005 = + {0x1000, 0x2005, pci_subsys_1000_0411_1000_2005, 0}; +#undef pci_ss_info_1000_2005 +#define pci_ss_info_1000_2005 pci_ss_info_1000_0411_1000_2005 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0411_1033_8287 = + {0x1033, 0x8287, pci_subsys_1000_0411_1033_8287, 0}; +#undef pci_ss_info_1033_8287 +#define pci_ss_info_1033_8287 pci_ss_info_1000_0411_1033_8287 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0411_1054_3016 = + {0x1054, 0x3016, pci_subsys_1000_0411_1054_3016, 0}; +#undef pci_ss_info_1054_3016 +#define pci_ss_info_1054_3016 pci_ss_info_1000_0411_1054_3016 +static const pciSubsystemInfo pci_ss_info_1000_0411_1734_1081 = + {0x1734, 0x1081, pci_subsys_1000_0411_1734_1081, 0}; +#undef pci_ss_info_1734_1081 +#define pci_ss_info_1734_1081 pci_ss_info_1000_0411_1734_1081 +static const pciSubsystemInfo pci_ss_info_1000_0411_1734_10a3 = + {0x1734, 0x10a3, pci_subsys_1000_0411_1734_10a3, 0}; +#undef pci_ss_info_1734_10a3 +#define pci_ss_info_1734_10a3 pci_ss_info_1000_0411_1734_10a3 +#endif +static const pciSubsystemInfo pci_ss_info_1000_0411_8086_1001 = + {0x8086, 0x1001, pci_subsys_1000_0411_8086_1001, 0}; +#undef pci_ss_info_8086_1001 +#define pci_ss_info_8086_1001 pci_ss_info_1000_0411_8086_1001 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0411_8086_1003 = + {0x8086, 0x1003, pci_subsys_1000_0411_8086_1003, 0}; +#undef pci_ss_info_8086_1003 +#define pci_ss_info_8086_1003 pci_ss_info_1000_0411_8086_1003 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0411_8086_3500 = + {0x8086, 0x3500, pci_subsys_1000_0411_8086_3500, 0}; +#undef pci_ss_info_8086_3500 +#define pci_ss_info_8086_3500 pci_ss_info_1000_0411_8086_3500 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0411_8086_3501 = + {0x8086, 0x3501, pci_subsys_1000_0411_8086_3501, 0}; +#undef pci_ss_info_8086_3501 +#define pci_ss_info_8086_3501 pci_ss_info_1000_0411_8086_3501 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_0411_8086_3504 = + {0x8086, 0x3504, pci_subsys_1000_0411_8086_3504, 0}; +#undef pci_ss_info_8086_3504 +#define pci_ss_info_8086_3504 pci_ss_info_1000_0411_8086_3504 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1000_0413_1000_1005 = + {0x1000, 0x1005, pci_subsys_1000_0413_1000_1005, 0}; +#undef pci_ss_info_1000_1005 +#define pci_ss_info_1000_1005 pci_ss_info_1000_0413_1000_1005 +static const pciSubsystemInfo pci_ss_info_1000_0622_1000_1020 = + {0x1000, 0x1020, pci_subsys_1000_0622_1000_1020, 0}; +#undef pci_ss_info_1000_1020 +#define pci_ss_info_1000_1020 pci_ss_info_1000_0622_1000_1020 +static const pciSubsystemInfo pci_ss_info_1000_0626_1000_1010 = + {0x1000, 0x1010, pci_subsys_1000_0626_1000_1010, 0}; +#undef pci_ss_info_1000_1010 +#define pci_ss_info_1000_1010 pci_ss_info_1000_0626_1000_1010 +static const pciSubsystemInfo pci_ss_info_1000_0702_1318_0000 = + {0x1318, 0x0000, pci_subsys_1000_0702_1318_0000, 0}; +#undef pci_ss_info_1318_0000 +#define pci_ss_info_1318_0000 pci_ss_info_1000_0702_1318_0000 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_0518 = + {0x1000, 0x0518, pci_subsys_1000_1960_1000_0518, 0}; +#undef pci_ss_info_1000_0518 +#define pci_ss_info_1000_0518 pci_ss_info_1000_1960_1000_0518 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_0520 = + {0x1000, 0x0520, pci_subsys_1000_1960_1000_0520, 0}; +#undef pci_ss_info_1000_0520 +#define pci_ss_info_1000_0520 pci_ss_info_1000_1960_1000_0520 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_0522 = + {0x1000, 0x0522, pci_subsys_1000_1960_1000_0522, 0}; +#undef pci_ss_info_1000_0522 +#define pci_ss_info_1000_0522 pci_ss_info_1000_1960_1000_0522 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_0523 = + {0x1000, 0x0523, pci_subsys_1000_1960_1000_0523, 0}; +#undef pci_ss_info_1000_0523 +#define pci_ss_info_1000_0523 pci_ss_info_1000_1960_1000_0523 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_4523 = + {0x1000, 0x4523, pci_subsys_1000_1960_1000_4523, 0}; +#undef pci_ss_info_1000_4523 +#define pci_ss_info_1000_4523 pci_ss_info_1000_1960_1000_4523 +static const pciSubsystemInfo pci_ss_info_1000_1960_1000_a520 = + {0x1000, 0xa520, pci_subsys_1000_1960_1000_a520, 0}; +#undef pci_ss_info_1000_a520 +#define pci_ss_info_1000_a520 pci_ss_info_1000_1960_1000_a520 +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_1028_0518 = + {0x1028, 0x0518, pci_subsys_1000_1960_1028_0518, 0}; +#undef pci_ss_info_1028_0518 +#define pci_ss_info_1028_0518 pci_ss_info_1000_1960_1028_0518 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_1028_0520 = + {0x1028, 0x0520, pci_subsys_1000_1960_1028_0520, 0}; +#undef pci_ss_info_1028_0520 +#define pci_ss_info_1028_0520 pci_ss_info_1000_1960_1028_0520 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_1028_0531 = + {0x1028, 0x0531, pci_subsys_1000_1960_1028_0531, 0}; +#undef pci_ss_info_1028_0531 +#define pci_ss_info_1028_0531 pci_ss_info_1000_1960_1028_0531 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_1028_0533 = + {0x1028, 0x0533, pci_subsys_1000_1960_1028_0533, 0}; +#undef pci_ss_info_1028_0533 +#define pci_ss_info_1028_0533 pci_ss_info_1000_1960_1028_0533 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_8086_0520 = + {0x8086, 0x0520, pci_subsys_1000_1960_8086_0520, 0}; +#undef pci_ss_info_8086_0520 +#define pci_ss_info_8086_0520 pci_ss_info_1000_1960_8086_0520 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1000_1960_8086_0523 = + {0x8086, 0x0523, pci_subsys_1000_1960_8086_0523, 0}; +#undef pci_ss_info_8086_0523 +#define pci_ss_info_8086_0523 pci_ss_info_1000_1960_8086_0523 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1002_4150_1002_0002 = + {0x1002, 0x0002, pci_subsys_1002_4150_1002_0002, 0}; +#undef pci_ss_info_1002_0002 +#define pci_ss_info_1002_0002 pci_ss_info_1002_4150_1002_0002 +static const pciSubsystemInfo pci_ss_info_1002_4150_1002_0003 = + {0x1002, 0x0003, pci_subsys_1002_4150_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_1002_4150_1002_0003 +static const pciSubsystemInfo pci_ss_info_1002_4150_1002_4722 = + {0x1002, 0x4722, pci_subsys_1002_4150_1002_4722, 0}; +#undef pci_ss_info_1002_4722 +#define pci_ss_info_1002_4722 pci_ss_info_1002_4150_1002_4722 +static const pciSubsystemInfo pci_ss_info_1002_4150_1458_4024 = + {0x1458, 0x4024, pci_subsys_1002_4150_1458_4024, 0}; +#undef pci_ss_info_1458_4024 +#define pci_ss_info_1458_4024 pci_ss_info_1002_4150_1458_4024 +static const pciSubsystemInfo pci_ss_info_1002_4150_148c_2064 = + {0x148c, 0x2064, pci_subsys_1002_4150_148c_2064, 0}; +#undef pci_ss_info_148c_2064 +#define pci_ss_info_148c_2064 pci_ss_info_1002_4150_148c_2064 +static const pciSubsystemInfo pci_ss_info_1002_4150_148c_2066 = + {0x148c, 0x2066, pci_subsys_1002_4150_148c_2066, 0}; +#undef pci_ss_info_148c_2066 +#define pci_ss_info_148c_2066 pci_ss_info_1002_4150_148c_2066 +static const pciSubsystemInfo pci_ss_info_1002_4150_174b_7c19 = + {0x174b, 0x7c19, pci_subsys_1002_4150_174b_7c19, 0}; +#undef pci_ss_info_174b_7c19 +#define pci_ss_info_174b_7c19 pci_ss_info_1002_4150_174b_7c19 +static const pciSubsystemInfo pci_ss_info_1002_4150_174b_7c29 = + {0x174b, 0x7c29, pci_subsys_1002_4150_174b_7c29, 0}; +#undef pci_ss_info_174b_7c29 +#define pci_ss_info_174b_7c29 pci_ss_info_1002_4150_174b_7c29 +static const pciSubsystemInfo pci_ss_info_1002_4150_17ee_2002 = + {0x17ee, 0x2002, pci_subsys_1002_4150_17ee_2002, 0}; +#undef pci_ss_info_17ee_2002 +#define pci_ss_info_17ee_2002 pci_ss_info_1002_4150_17ee_2002 +static const pciSubsystemInfo pci_ss_info_1002_4150_18bc_0101 = + {0x18bc, 0x0101, pci_subsys_1002_4150_18bc_0101, 0}; +#undef pci_ss_info_18bc_0101 +#define pci_ss_info_18bc_0101 pci_ss_info_1002_4150_18bc_0101 +static const pciSubsystemInfo pci_ss_info_1002_4151_1043_c004 = + {0x1043, 0xc004, pci_subsys_1002_4151_1043_c004, 0}; +#undef pci_ss_info_1043_c004 +#define pci_ss_info_1043_c004 pci_ss_info_1002_4151_1043_c004 +static const pciSubsystemInfo pci_ss_info_1002_4152_1002_0002 = + {0x1002, 0x0002, pci_subsys_1002_4152_1002_0002, 0}; +#undef pci_ss_info_1002_0002 +#define pci_ss_info_1002_0002 pci_ss_info_1002_4152_1002_0002 +static const pciSubsystemInfo pci_ss_info_1002_4152_1002_4772 = + {0x1002, 0x4772, pci_subsys_1002_4152_1002_4772, 0}; +#undef pci_ss_info_1002_4772 +#define pci_ss_info_1002_4772 pci_ss_info_1002_4152_1002_4772 +static const pciSubsystemInfo pci_ss_info_1002_4152_1043_c002 = + {0x1043, 0xc002, pci_subsys_1002_4152_1043_c002, 0}; +#undef pci_ss_info_1043_c002 +#define pci_ss_info_1043_c002 pci_ss_info_1002_4152_1043_c002 +static const pciSubsystemInfo pci_ss_info_1002_4152_1043_c01a = + {0x1043, 0xc01a, pci_subsys_1002_4152_1043_c01a, 0}; +#undef pci_ss_info_1043_c01a +#define pci_ss_info_1043_c01a pci_ss_info_1002_4152_1043_c01a +static const pciSubsystemInfo pci_ss_info_1002_4152_174b_7c29 = + {0x174b, 0x7c29, pci_subsys_1002_4152_174b_7c29, 0}; +#undef pci_ss_info_174b_7c29 +#define pci_ss_info_174b_7c29 pci_ss_info_1002_4152_174b_7c29 +static const pciSubsystemInfo pci_ss_info_1002_4152_1787_4002 = + {0x1787, 0x4002, pci_subsys_1002_4152_1787_4002, 0}; +#undef pci_ss_info_1787_4002 +#define pci_ss_info_1787_4002 pci_ss_info_1002_4152_1787_4002 +static const pciSubsystemInfo pci_ss_info_1002_4153_1043_010c = + {0x1043, 0x010c, pci_subsys_1002_4153_1043_010c, 0}; +#undef pci_ss_info_1043_010c +#define pci_ss_info_1043_010c pci_ss_info_1002_4153_1043_010c +static const pciSubsystemInfo pci_ss_info_1002_4153_1462_932c = + {0x1462, 0x932c, pci_subsys_1002_4153_1462_932c, 0}; +#undef pci_ss_info_1462_932c +#define pci_ss_info_1462_932c pci_ss_info_1002_4153_1462_932c +static const pciSubsystemInfo pci_ss_info_1002_4170_1002_0003 = + {0x1002, 0x0003, pci_subsys_1002_4170_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_1002_4170_1002_0003 +static const pciSubsystemInfo pci_ss_info_1002_4170_1002_4723 = + {0x1002, 0x4723, pci_subsys_1002_4170_1002_4723, 0}; +#undef pci_ss_info_1002_4723 +#define pci_ss_info_1002_4723 pci_ss_info_1002_4170_1002_4723 +static const pciSubsystemInfo pci_ss_info_1002_4170_1458_4025 = + {0x1458, 0x4025, pci_subsys_1002_4170_1458_4025, 0}; +#undef pci_ss_info_1458_4025 +#define pci_ss_info_1458_4025 pci_ss_info_1002_4170_1458_4025 +static const pciSubsystemInfo pci_ss_info_1002_4170_148c_2067 = + {0x148c, 0x2067, pci_subsys_1002_4170_148c_2067, 0}; +#undef pci_ss_info_148c_2067 +#define pci_ss_info_148c_2067 pci_ss_info_1002_4170_148c_2067 +static const pciSubsystemInfo pci_ss_info_1002_4170_174b_7c28 = + {0x174b, 0x7c28, pci_subsys_1002_4170_174b_7c28, 0}; +#undef pci_ss_info_174b_7c28 +#define pci_ss_info_174b_7c28 pci_ss_info_1002_4170_174b_7c28 +static const pciSubsystemInfo pci_ss_info_1002_4170_17ee_2003 = + {0x17ee, 0x2003, pci_subsys_1002_4170_17ee_2003, 0}; +#undef pci_ss_info_17ee_2003 +#define pci_ss_info_17ee_2003 pci_ss_info_1002_4170_17ee_2003 +static const pciSubsystemInfo pci_ss_info_1002_4170_18bc_0100 = + {0x18bc, 0x0100, pci_subsys_1002_4170_18bc_0100, 0}; +#undef pci_ss_info_18bc_0100 +#define pci_ss_info_18bc_0100 pci_ss_info_1002_4170_18bc_0100 +static const pciSubsystemInfo pci_ss_info_1002_4171_1043_c005 = + {0x1043, 0xc005, pci_subsys_1002_4171_1043_c005, 0}; +#undef pci_ss_info_1043_c005 +#define pci_ss_info_1043_c005 pci_ss_info_1002_4171_1043_c005 +static const pciSubsystemInfo pci_ss_info_1002_4172_1002_0003 = + {0x1002, 0x0003, pci_subsys_1002_4172_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_1002_4172_1002_0003 +static const pciSubsystemInfo pci_ss_info_1002_4172_1002_4773 = + {0x1002, 0x4773, pci_subsys_1002_4172_1002_4773, 0}; +#undef pci_ss_info_1002_4773 +#define pci_ss_info_1002_4773 pci_ss_info_1002_4172_1002_4773 +static const pciSubsystemInfo pci_ss_info_1002_4172_1043_c003 = + {0x1043, 0xc003, pci_subsys_1002_4172_1043_c003, 0}; +#undef pci_ss_info_1043_c003 +#define pci_ss_info_1043_c003 pci_ss_info_1002_4172_1043_c003 +static const pciSubsystemInfo pci_ss_info_1002_4172_1043_c01b = + {0x1043, 0xc01b, pci_subsys_1002_4172_1043_c01b, 0}; +#undef pci_ss_info_1043_c01b +#define pci_ss_info_1043_c01b pci_ss_info_1002_4172_1043_c01b +static const pciSubsystemInfo pci_ss_info_1002_4172_174b_7c28 = + {0x174b, 0x7c28, pci_subsys_1002_4172_174b_7c28, 0}; +#undef pci_ss_info_174b_7c28 +#define pci_ss_info_174b_7c28 pci_ss_info_1002_4172_174b_7c28 +static const pciSubsystemInfo pci_ss_info_1002_4172_1787_4003 = + {0x1787, 0x4003, pci_subsys_1002_4172_1787_4003, 0}; +#undef pci_ss_info_1787_4003 +#define pci_ss_info_1787_4003 pci_ss_info_1002_4172_1787_4003 +static const pciSubsystemInfo pci_ss_info_1002_4173_1043_010d = + {0x1043, 0x010d, pci_subsys_1002_4173_1043_010d, 0}; +#undef pci_ss_info_1043_010d +#define pci_ss_info_1043_010d pci_ss_info_1002_4173_1043_010d +static const pciSubsystemInfo pci_ss_info_1002_4242_1002_02aa = + {0x1002, 0x02aa, pci_subsys_1002_4242_1002_02aa, 0}; +#undef pci_ss_info_1002_02aa +#define pci_ss_info_1002_02aa pci_ss_info_1002_4242_1002_02aa +static const pciSubsystemInfo pci_ss_info_1002_4336_1002_4336 = + {0x1002, 0x4336, pci_subsys_1002_4336_1002_4336, 0}; +#undef pci_ss_info_1002_4336 +#define pci_ss_info_1002_4336 pci_ss_info_1002_4336_1002_4336 +static const pciSubsystemInfo pci_ss_info_1002_4336_103c_0024 = + {0x103c, 0x0024, pci_subsys_1002_4336_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_1002_4336_103c_0024 +static const pciSubsystemInfo pci_ss_info_1002_4336_161f_2029 = + {0x161f, 0x2029, pci_subsys_1002_4336_161f_2029, 0}; +#undef pci_ss_info_161f_2029 +#define pci_ss_info_161f_2029 pci_ss_info_1002_4336_161f_2029 +static const pciSubsystemInfo pci_ss_info_1002_4337_1014_053a = + {0x1014, 0x053a, pci_subsys_1002_4337_1014_053a, 0}; +#undef pci_ss_info_1014_053a +#define pci_ss_info_1014_053a pci_ss_info_1002_4337_1014_053a +static const pciSubsystemInfo pci_ss_info_1002_4337_103c_0850 = + {0x103c, 0x0850, pci_subsys_1002_4337_103c_0850, 0}; +#undef pci_ss_info_103c_0850 +#define pci_ss_info_103c_0850 pci_ss_info_1002_4337_103c_0850 +static const pciSubsystemInfo pci_ss_info_1002_4370_1025_0079 = + {0x1025, 0x0079, pci_subsys_1002_4370_1025_0079, 0}; +#undef pci_ss_info_1025_0079 +#define pci_ss_info_1025_0079 pci_ss_info_1002_4370_1025_0079 +static const pciSubsystemInfo pci_ss_info_1002_4370_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4370_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4370_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4370_107b_0300 = + {0x107b, 0x0300, pci_subsys_1002_4370_107b_0300, 0}; +#undef pci_ss_info_107b_0300 +#define pci_ss_info_107b_0300 pci_ss_info_1002_4370_107b_0300 +static const pciSubsystemInfo pci_ss_info_1002_4371_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4371_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4371_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4372_1025_0080 = + {0x1025, 0x0080, pci_subsys_1002_4372_1025_0080, 0}; +#undef pci_ss_info_1025_0080 +#define pci_ss_info_1025_0080 pci_ss_info_1002_4372_1025_0080 +static const pciSubsystemInfo pci_ss_info_1002_4372_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4372_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4372_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4373_1025_0080 = + {0x1025, 0x0080, pci_subsys_1002_4373_1025_0080, 0}; +#undef pci_ss_info_1025_0080 +#define pci_ss_info_1025_0080 pci_ss_info_1002_4373_1025_0080 +static const pciSubsystemInfo pci_ss_info_1002_4373_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4373_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4373_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4374_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4374_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4374_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4375_1025_0080 = + {0x1025, 0x0080, pci_subsys_1002_4375_1025_0080, 0}; +#undef pci_ss_info_1025_0080 +#define pci_ss_info_1025_0080 pci_ss_info_1002_4375_1025_0080 +static const pciSubsystemInfo pci_ss_info_1002_4375_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4375_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4375_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4376_1025_0080 = + {0x1025, 0x0080, pci_subsys_1002_4376_1025_0080, 0}; +#undef pci_ss_info_1025_0080 +#define pci_ss_info_1025_0080 pci_ss_info_1002_4376_1025_0080 +static const pciSubsystemInfo pci_ss_info_1002_4376_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4376_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4376_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4377_1025_0080 = + {0x1025, 0x0080, pci_subsys_1002_4377_1025_0080, 0}; +#undef pci_ss_info_1025_0080 +#define pci_ss_info_1025_0080 pci_ss_info_1002_4377_1025_0080 +static const pciSubsystemInfo pci_ss_info_1002_4377_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4377_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4377_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4378_1025_0080 = + {0x1025, 0x0080, pci_subsys_1002_4378_1025_0080, 0}; +#undef pci_ss_info_1025_0080 +#define pci_ss_info_1025_0080 pci_ss_info_1002_4378_1025_0080 +static const pciSubsystemInfo pci_ss_info_1002_4378_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_4378_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_4378_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0040 = + {0x1002, 0x0040, pci_subsys_1002_4742_1002_0040, 0}; +#undef pci_ss_info_1002_0040 +#define pci_ss_info_1002_0040 pci_ss_info_1002_4742_1002_0040 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_4742_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_4742_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0061 = + {0x1002, 0x0061, pci_subsys_1002_4742_1002_0061, 0}; +#undef pci_ss_info_1002_0061 +#define pci_ss_info_1002_0061 pci_ss_info_1002_4742_1002_0061 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0062 = + {0x1002, 0x0062, pci_subsys_1002_4742_1002_0062, 0}; +#undef pci_ss_info_1002_0062 +#define pci_ss_info_1002_0062 pci_ss_info_1002_4742_1002_0062 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0063 = + {0x1002, 0x0063, pci_subsys_1002_4742_1002_0063, 0}; +#undef pci_ss_info_1002_0063 +#define pci_ss_info_1002_0063 pci_ss_info_1002_4742_1002_0063 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0080 = + {0x1002, 0x0080, pci_subsys_1002_4742_1002_0080, 0}; +#undef pci_ss_info_1002_0080 +#define pci_ss_info_1002_0080 pci_ss_info_1002_4742_1002_0080 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_0084 = + {0x1002, 0x0084, pci_subsys_1002_4742_1002_0084, 0}; +#undef pci_ss_info_1002_0084 +#define pci_ss_info_1002_0084 pci_ss_info_1002_4742_1002_0084 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_4742 = + {0x1002, 0x4742, pci_subsys_1002_4742_1002_4742, 0}; +#undef pci_ss_info_1002_4742 +#define pci_ss_info_1002_4742 pci_ss_info_1002_4742_1002_4742 +static const pciSubsystemInfo pci_ss_info_1002_4742_1002_8001 = + {0x1002, 0x8001, pci_subsys_1002_4742_1002_8001, 0}; +#undef pci_ss_info_1002_8001 +#define pci_ss_info_1002_8001 pci_ss_info_1002_4742_1002_8001 +static const pciSubsystemInfo pci_ss_info_1002_4742_1028_0082 = + {0x1028, 0x0082, pci_subsys_1002_4742_1028_0082, 0}; +#undef pci_ss_info_1028_0082 +#define pci_ss_info_1028_0082 pci_ss_info_1002_4742_1028_0082 +static const pciSubsystemInfo pci_ss_info_1002_4742_1028_4082 = + {0x1028, 0x4082, pci_subsys_1002_4742_1028_4082, 0}; +#undef pci_ss_info_1028_4082 +#define pci_ss_info_1028_4082 pci_ss_info_1002_4742_1028_4082 +static const pciSubsystemInfo pci_ss_info_1002_4742_1028_8082 = + {0x1028, 0x8082, pci_subsys_1002_4742_1028_8082, 0}; +#undef pci_ss_info_1028_8082 +#define pci_ss_info_1028_8082 pci_ss_info_1002_4742_1028_8082 +static const pciSubsystemInfo pci_ss_info_1002_4742_1028_c082 = + {0x1028, 0xc082, pci_subsys_1002_4742_1028_c082, 0}; +#undef pci_ss_info_1028_c082 +#define pci_ss_info_1028_c082 pci_ss_info_1002_4742_1028_c082 +static const pciSubsystemInfo pci_ss_info_1002_4742_8086_4152 = + {0x8086, 0x4152, pci_subsys_1002_4742_8086_4152, 0}; +#undef pci_ss_info_8086_4152 +#define pci_ss_info_8086_4152 pci_ss_info_1002_4742_8086_4152 +static const pciSubsystemInfo pci_ss_info_1002_4742_8086_464a = + {0x8086, 0x464a, pci_subsys_1002_4742_8086_464a, 0}; +#undef pci_ss_info_8086_464a +#define pci_ss_info_8086_464a pci_ss_info_1002_4742_8086_464a +static const pciSubsystemInfo pci_ss_info_1002_4744_1002_4744 = + {0x1002, 0x4744, pci_subsys_1002_4744_1002_4744, 0}; +#undef pci_ss_info_1002_4744 +#define pci_ss_info_1002_4744 pci_ss_info_1002_4744_1002_4744 +static const pciSubsystemInfo pci_ss_info_1002_4749_1002_0061 = + {0x1002, 0x0061, pci_subsys_1002_4749_1002_0061, 0}; +#undef pci_ss_info_1002_0061 +#define pci_ss_info_1002_0061 pci_ss_info_1002_4749_1002_0061 +static const pciSubsystemInfo pci_ss_info_1002_4749_1002_0062 = + {0x1002, 0x0062, pci_subsys_1002_4749_1002_0062, 0}; +#undef pci_ss_info_1002_0062 +#define pci_ss_info_1002_0062 pci_ss_info_1002_4749_1002_0062 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_474d_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_474d_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_474d_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_474d_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_0080 = + {0x1002, 0x0080, pci_subsys_1002_474d_1002_0080, 0}; +#undef pci_ss_info_1002_0080 +#define pci_ss_info_1002_0080 pci_ss_info_1002_474d_1002_0080 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_0084 = + {0x1002, 0x0084, pci_subsys_1002_474d_1002_0084, 0}; +#undef pci_ss_info_1002_0084 +#define pci_ss_info_1002_0084 pci_ss_info_1002_474d_1002_0084 +static const pciSubsystemInfo pci_ss_info_1002_474d_1002_474d = + {0x1002, 0x474d, pci_subsys_1002_474d_1002_474d, 0}; +#undef pci_ss_info_1002_474d +#define pci_ss_info_1002_474d pci_ss_info_1002_474d_1002_474d +static const pciSubsystemInfo pci_ss_info_1002_474d_1033_806a = + {0x1033, 0x806a, pci_subsys_1002_474d_1033_806a, 0}; +#undef pci_ss_info_1033_806a +#define pci_ss_info_1033_806a pci_ss_info_1002_474d_1033_806a +static const pciSubsystemInfo pci_ss_info_1002_474e_1002_474e = + {0x1002, 0x474e, pci_subsys_1002_474e_1002_474e, 0}; +#undef pci_ss_info_1002_474e +#define pci_ss_info_1002_474e pci_ss_info_1002_474e_1002_474e +static const pciSubsystemInfo pci_ss_info_1002_474f_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_474f_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_474f_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_474f_1002_474f = + {0x1002, 0x474f, pci_subsys_1002_474f_1002_474f, 0}; +#undef pci_ss_info_1002_474f +#define pci_ss_info_1002_474f pci_ss_info_1002_474f_1002_474f +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_0040 = + {0x1002, 0x0040, pci_subsys_1002_4750_1002_0040, 0}; +#undef pci_ss_info_1002_0040 +#define pci_ss_info_1002_0040 pci_ss_info_1002_4750_1002_0040 +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_4750_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_4750_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_0080 = + {0x1002, 0x0080, pci_subsys_1002_4750_1002_0080, 0}; +#undef pci_ss_info_1002_0080 +#define pci_ss_info_1002_0080 pci_ss_info_1002_4750_1002_0080 +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_0084 = + {0x1002, 0x0084, pci_subsys_1002_4750_1002_0084, 0}; +#undef pci_ss_info_1002_0084 +#define pci_ss_info_1002_0084 pci_ss_info_1002_4750_1002_0084 +static const pciSubsystemInfo pci_ss_info_1002_4750_1002_4750 = + {0x1002, 0x4750, pci_subsys_1002_4750_1002_4750, 0}; +#undef pci_ss_info_1002_4750 +#define pci_ss_info_1002_4750 pci_ss_info_1002_4750_1002_4750 +static const pciSubsystemInfo pci_ss_info_1002_4752_0e11_001e = + {0x0e11, 0x001e, pci_subsys_1002_4752_0e11_001e, 0}; +#undef pci_ss_info_0e11_001e +#define pci_ss_info_0e11_001e pci_ss_info_1002_4752_0e11_001e +static const pciSubsystemInfo pci_ss_info_1002_4752_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_4752_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_4752_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_4752_1002_4752 = + {0x1002, 0x4752, pci_subsys_1002_4752_1002_4752, 0}; +#undef pci_ss_info_1002_4752 +#define pci_ss_info_1002_4752 pci_ss_info_1002_4752_1002_4752 +static const pciSubsystemInfo pci_ss_info_1002_4752_1002_8008 = + {0x1002, 0x8008, pci_subsys_1002_4752_1002_8008, 0}; +#undef pci_ss_info_1002_8008 +#define pci_ss_info_1002_8008 pci_ss_info_1002_4752_1002_8008 +static const pciSubsystemInfo pci_ss_info_1002_4752_1028_00ce = + {0x1028, 0x00ce, pci_subsys_1002_4752_1028_00ce, 0}; +#undef pci_ss_info_1028_00ce +#define pci_ss_info_1028_00ce pci_ss_info_1002_4752_1028_00ce +static const pciSubsystemInfo pci_ss_info_1002_4752_1028_00d1 = + {0x1028, 0x00d1, pci_subsys_1002_4752_1028_00d1, 0}; +#undef pci_ss_info_1028_00d1 +#define pci_ss_info_1028_00d1 pci_ss_info_1002_4752_1028_00d1 +static const pciSubsystemInfo pci_ss_info_1002_4752_1028_00d9 = + {0x1028, 0x00d9, pci_subsys_1002_4752_1028_00d9, 0}; +#undef pci_ss_info_1028_00d9 +#define pci_ss_info_1028_00d9 pci_ss_info_1002_4752_1028_00d9 +static const pciSubsystemInfo pci_ss_info_1002_4752_1028_0134 = + {0x1028, 0x0134, pci_subsys_1002_4752_1028_0134, 0}; +#undef pci_ss_info_1028_0134 +#define pci_ss_info_1028_0134 pci_ss_info_1002_4752_1028_0134 +static const pciSubsystemInfo pci_ss_info_1002_4752_103c_10e1 = + {0x103c, 0x10e1, pci_subsys_1002_4752_103c_10e1, 0}; +#undef pci_ss_info_103c_10e1 +#define pci_ss_info_103c_10e1 pci_ss_info_1002_4752_103c_10e1 +static const pciSubsystemInfo pci_ss_info_1002_4752_107b_6400 = + {0x107b, 0x6400, pci_subsys_1002_4752_107b_6400, 0}; +#undef pci_ss_info_107b_6400 +#define pci_ss_info_107b_6400 pci_ss_info_1002_4752_107b_6400 +static const pciSubsystemInfo pci_ss_info_1002_4752_1734_007a = + {0x1734, 0x007a, pci_subsys_1002_4752_1734_007a, 0}; +#undef pci_ss_info_1734_007a +#define pci_ss_info_1734_007a pci_ss_info_1002_4752_1734_007a +static const pciSubsystemInfo pci_ss_info_1002_4752_8086_3411 = + {0x8086, 0x3411, pci_subsys_1002_4752_8086_3411, 0}; +#undef pci_ss_info_8086_3411 +#define pci_ss_info_8086_3411 pci_ss_info_1002_4752_8086_3411 +static const pciSubsystemInfo pci_ss_info_1002_4752_8086_3427 = + {0x8086, 0x3427, pci_subsys_1002_4752_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_1002_4752_8086_3427 +static const pciSubsystemInfo pci_ss_info_1002_4753_1002_4753 = + {0x1002, 0x4753, pci_subsys_1002_4753_1002_4753, 0}; +#undef pci_ss_info_1002_4753 +#define pci_ss_info_1002_4753 pci_ss_info_1002_4753_1002_4753 +static const pciSubsystemInfo pci_ss_info_1002_4756_1002_4756 = + {0x1002, 0x4756, pci_subsys_1002_4756_1002_4756, 0}; +#undef pci_ss_info_1002_4756 +#define pci_ss_info_1002_4756 pci_ss_info_1002_4756_1002_4756 +static const pciSubsystemInfo pci_ss_info_1002_4757_1002_4757 = + {0x1002, 0x4757, pci_subsys_1002_4757_1002_4757, 0}; +#undef pci_ss_info_1002_4757 +#define pci_ss_info_1002_4757 pci_ss_info_1002_4757_1002_4757 +static const pciSubsystemInfo pci_ss_info_1002_4757_1028_0089 = + {0x1028, 0x0089, pci_subsys_1002_4757_1028_0089, 0}; +#undef pci_ss_info_1028_0089 +#define pci_ss_info_1028_0089 pci_ss_info_1002_4757_1028_0089 +static const pciSubsystemInfo pci_ss_info_1002_4757_1028_008e = + {0x1028, 0x008e, pci_subsys_1002_4757_1028_008e, 0}; +#undef pci_ss_info_1028_008e +#define pci_ss_info_1028_008e pci_ss_info_1002_4757_1028_008e +static const pciSubsystemInfo pci_ss_info_1002_4757_1028_4082 = + {0x1028, 0x4082, pci_subsys_1002_4757_1028_4082, 0}; +#undef pci_ss_info_1028_4082 +#define pci_ss_info_1028_4082 pci_ss_info_1002_4757_1028_4082 +static const pciSubsystemInfo pci_ss_info_1002_4757_1028_8082 = + {0x1028, 0x8082, pci_subsys_1002_4757_1028_8082, 0}; +#undef pci_ss_info_1028_8082 +#define pci_ss_info_1028_8082 pci_ss_info_1002_4757_1028_8082 +static const pciSubsystemInfo pci_ss_info_1002_4757_1028_c082 = + {0x1028, 0xc082, pci_subsys_1002_4757_1028_c082, 0}; +#undef pci_ss_info_1028_c082 +#define pci_ss_info_1028_c082 pci_ss_info_1002_4757_1028_c082 +static const pciSubsystemInfo pci_ss_info_1002_475a_1002_0084 = + {0x1002, 0x0084, pci_subsys_1002_475a_1002_0084, 0}; +#undef pci_ss_info_1002_0084 +#define pci_ss_info_1002_0084 pci_ss_info_1002_475a_1002_0084 +static const pciSubsystemInfo pci_ss_info_1002_475a_1002_0087 = + {0x1002, 0x0087, pci_subsys_1002_475a_1002_0087, 0}; +#undef pci_ss_info_1002_0087 +#define pci_ss_info_1002_0087 pci_ss_info_1002_475a_1002_0087 +static const pciSubsystemInfo pci_ss_info_1002_475a_1002_475a = + {0x1002, 0x475a, pci_subsys_1002_475a_1002_475a, 0}; +#undef pci_ss_info_1002_475a +#define pci_ss_info_1002_475a pci_ss_info_1002_475a_1002_475a +static const pciSubsystemInfo pci_ss_info_1002_4966_10f1_0002 = + {0x10f1, 0x0002, pci_subsys_1002_4966_10f1_0002, 0}; +#undef pci_ss_info_10f1_0002 +#define pci_ss_info_10f1_0002 pci_ss_info_1002_4966_10f1_0002 +static const pciSubsystemInfo pci_ss_info_1002_4966_148c_2039 = + {0x148c, 0x2039, pci_subsys_1002_4966_148c_2039, 0}; +#undef pci_ss_info_148c_2039 +#define pci_ss_info_148c_2039 pci_ss_info_1002_4966_148c_2039 +static const pciSubsystemInfo pci_ss_info_1002_4966_1509_9a00 = + {0x1509, 0x9a00, pci_subsys_1002_4966_1509_9a00, 0}; +#undef pci_ss_info_1509_9a00 +#define pci_ss_info_1509_9a00 pci_ss_info_1002_4966_1509_9a00 +static const pciSubsystemInfo pci_ss_info_1002_4966_1681_0040 = + {0x1681, 0x0040, pci_subsys_1002_4966_1681_0040, 0}; +#undef pci_ss_info_1681_0040 +#define pci_ss_info_1681_0040 pci_ss_info_1002_4966_1681_0040 +static const pciSubsystemInfo pci_ss_info_1002_4966_174b_7176 = + {0x174b, 0x7176, pci_subsys_1002_4966_174b_7176, 0}; +#undef pci_ss_info_174b_7176 +#define pci_ss_info_174b_7176 pci_ss_info_1002_4966_174b_7176 +static const pciSubsystemInfo pci_ss_info_1002_4966_174b_7192 = + {0x174b, 0x7192, pci_subsys_1002_4966_174b_7192, 0}; +#undef pci_ss_info_174b_7192 +#define pci_ss_info_174b_7192 pci_ss_info_1002_4966_174b_7192 +static const pciSubsystemInfo pci_ss_info_1002_4966_17af_2005 = + {0x17af, 0x2005, pci_subsys_1002_4966_17af_2005, 0}; +#undef pci_ss_info_17af_2005 +#define pci_ss_info_17af_2005 pci_ss_info_1002_4966_17af_2005 +static const pciSubsystemInfo pci_ss_info_1002_4966_17af_2006 = + {0x17af, 0x2006, pci_subsys_1002_4966_17af_2006, 0}; +#undef pci_ss_info_17af_2006 +#define pci_ss_info_17af_2006 pci_ss_info_1002_4966_17af_2006 +static const pciSubsystemInfo pci_ss_info_1002_4c42_0e11_b0e7 = + {0x0e11, 0xb0e7, pci_subsys_1002_4c42_0e11_b0e7, 0}; +#undef pci_ss_info_0e11_b0e7 +#define pci_ss_info_0e11_b0e7 pci_ss_info_1002_4c42_0e11_b0e7 +static const pciSubsystemInfo pci_ss_info_1002_4c42_0e11_b0e8 = + {0x0e11, 0xb0e8, pci_subsys_1002_4c42_0e11_b0e8, 0}; +#undef pci_ss_info_0e11_b0e8 +#define pci_ss_info_0e11_b0e8 pci_ss_info_1002_4c42_0e11_b0e8 +static const pciSubsystemInfo pci_ss_info_1002_4c42_0e11_b10e = + {0x0e11, 0xb10e, pci_subsys_1002_4c42_0e11_b10e, 0}; +#undef pci_ss_info_0e11_b10e +#define pci_ss_info_0e11_b10e pci_ss_info_1002_4c42_0e11_b10e +static const pciSubsystemInfo pci_ss_info_1002_4c42_1002_0040 = + {0x1002, 0x0040, pci_subsys_1002_4c42_1002_0040, 0}; +#undef pci_ss_info_1002_0040 +#define pci_ss_info_1002_0040 pci_ss_info_1002_4c42_1002_0040 +static const pciSubsystemInfo pci_ss_info_1002_4c42_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_4c42_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_4c42_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_4c42_1002_4c42 = + {0x1002, 0x4c42, pci_subsys_1002_4c42_1002_4c42, 0}; +#undef pci_ss_info_1002_4c42 +#define pci_ss_info_1002_4c42 pci_ss_info_1002_4c42_1002_4c42 +static const pciSubsystemInfo pci_ss_info_1002_4c42_1002_8001 = + {0x1002, 0x8001, pci_subsys_1002_4c42_1002_8001, 0}; +#undef pci_ss_info_1002_8001 +#define pci_ss_info_1002_8001 pci_ss_info_1002_4c42_1002_8001 +static const pciSubsystemInfo pci_ss_info_1002_4c42_1028_0085 = + {0x1028, 0x0085, pci_subsys_1002_4c42_1028_0085, 0}; +#undef pci_ss_info_1028_0085 +#define pci_ss_info_1028_0085 pci_ss_info_1002_4c42_1028_0085 +static const pciSubsystemInfo pci_ss_info_1002_4c46_1028_00b1 = + {0x1028, 0x00b1, pci_subsys_1002_4c46_1028_00b1, 0}; +#undef pci_ss_info_1028_00b1 +#define pci_ss_info_1028_00b1 pci_ss_info_1002_4c46_1028_00b1 +static const pciSubsystemInfo pci_ss_info_1002_4c49_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_4c49_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_4c49_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_4c49_1002_0040 = + {0x1002, 0x0040, pci_subsys_1002_4c49_1002_0040, 0}; +#undef pci_ss_info_1002_0040 +#define pci_ss_info_1002_0040 pci_ss_info_1002_4c49_1002_0040 +static const pciSubsystemInfo pci_ss_info_1002_4c49_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_4c49_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_4c49_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_4c49_1002_4c49 = + {0x1002, 0x4c49, pci_subsys_1002_4c49_1002_4c49, 0}; +#undef pci_ss_info_1002_4c49 +#define pci_ss_info_1002_4c49 pci_ss_info_1002_4c49_1002_4c49 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_0e11_b111 = + {0x0e11, 0xb111, pci_subsys_1002_4c4d_0e11_b111, 0}; +#undef pci_ss_info_0e11_b111 +#define pci_ss_info_0e11_b111 pci_ss_info_1002_4c4d_0e11_b111 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_0e11_b160 = + {0x0e11, 0xb160, pci_subsys_1002_4c4d_0e11_b160, 0}; +#undef pci_ss_info_0e11_b160 +#define pci_ss_info_0e11_b160 pci_ss_info_1002_4c4d_0e11_b160 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_1002_0084 = + {0x1002, 0x0084, pci_subsys_1002_4c4d_1002_0084, 0}; +#undef pci_ss_info_1002_0084 +#define pci_ss_info_1002_0084 pci_ss_info_1002_4c4d_1002_0084 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_1014_0154 = + {0x1014, 0x0154, pci_subsys_1002_4c4d_1014_0154, 0}; +#undef pci_ss_info_1014_0154 +#define pci_ss_info_1014_0154 pci_ss_info_1002_4c4d_1014_0154 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_1028_00aa = + {0x1028, 0x00aa, pci_subsys_1002_4c4d_1028_00aa, 0}; +#undef pci_ss_info_1028_00aa +#define pci_ss_info_1028_00aa pci_ss_info_1002_4c4d_1028_00aa +static const pciSubsystemInfo pci_ss_info_1002_4c4d_1028_00bb = + {0x1028, 0x00bb, pci_subsys_1002_4c4d_1028_00bb, 0}; +#undef pci_ss_info_1028_00bb +#define pci_ss_info_1028_00bb pci_ss_info_1002_4c4d_1028_00bb +static const pciSubsystemInfo pci_ss_info_1002_4c4d_10e1_10cf = + {0x10e1, 0x10cf, pci_subsys_1002_4c4d_10e1_10cf, 0}; +#undef pci_ss_info_10e1_10cf +#define pci_ss_info_10e1_10cf pci_ss_info_1002_4c4d_10e1_10cf +static const pciSubsystemInfo pci_ss_info_1002_4c4d_1179_ff00 = + {0x1179, 0xff00, pci_subsys_1002_4c4d_1179_ff00, 0}; +#undef pci_ss_info_1179_ff00 +#define pci_ss_info_1179_ff00 pci_ss_info_1002_4c4d_1179_ff00 +static const pciSubsystemInfo pci_ss_info_1002_4c4d_13bd_1019 = + {0x13bd, 0x1019, pci_subsys_1002_4c4d_13bd_1019, 0}; +#undef pci_ss_info_13bd_1019 +#define pci_ss_info_13bd_1019 pci_ss_info_1002_4c4d_13bd_1019 +static const pciSubsystemInfo pci_ss_info_1002_4c50_1002_4c50 = + {0x1002, 0x4c50, pci_subsys_1002_4c50_1002_4c50, 0}; +#undef pci_ss_info_1002_4c50 +#define pci_ss_info_1002_4c50 pci_ss_info_1002_4c50_1002_4c50 +static const pciSubsystemInfo pci_ss_info_1002_4c52_1033_8112 = + {0x1033, 0x8112, pci_subsys_1002_4c52_1033_8112, 0}; +#undef pci_ss_info_1033_8112 +#define pci_ss_info_1033_8112 pci_ss_info_1002_4c52_1033_8112 +static const pciSubsystemInfo pci_ss_info_1002_4c57_1014_0517 = + {0x1014, 0x0517, pci_subsys_1002_4c57_1014_0517, 0}; +#undef pci_ss_info_1014_0517 +#define pci_ss_info_1014_0517 pci_ss_info_1002_4c57_1014_0517 +static const pciSubsystemInfo pci_ss_info_1002_4c57_1028_00e6 = + {0x1028, 0x00e6, pci_subsys_1002_4c57_1028_00e6, 0}; +#undef pci_ss_info_1028_00e6 +#define pci_ss_info_1028_00e6 pci_ss_info_1002_4c57_1028_00e6 +static const pciSubsystemInfo pci_ss_info_1002_4c57_1028_012a = + {0x1028, 0x012a, pci_subsys_1002_4c57_1028_012a, 0}; +#undef pci_ss_info_1028_012a +#define pci_ss_info_1028_012a pci_ss_info_1002_4c57_1028_012a +static const pciSubsystemInfo pci_ss_info_1002_4c57_144d_c006 = + {0x144d, 0xc006, pci_subsys_1002_4c57_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_1002_4c57_144d_c006 +static const pciSubsystemInfo pci_ss_info_1002_4c59_0e11_b111 = + {0x0e11, 0xb111, pci_subsys_1002_4c59_0e11_b111, 0}; +#undef pci_ss_info_0e11_b111 +#define pci_ss_info_0e11_b111 pci_ss_info_1002_4c59_0e11_b111 +static const pciSubsystemInfo pci_ss_info_1002_4c59_1014_0235 = + {0x1014, 0x0235, pci_subsys_1002_4c59_1014_0235, 0}; +#undef pci_ss_info_1014_0235 +#define pci_ss_info_1014_0235 pci_ss_info_1002_4c59_1014_0235 +static const pciSubsystemInfo pci_ss_info_1002_4c59_1014_0239 = + {0x1014, 0x0239, pci_subsys_1002_4c59_1014_0239, 0}; +#undef pci_ss_info_1014_0239 +#define pci_ss_info_1014_0239 pci_ss_info_1002_4c59_1014_0239 +static const pciSubsystemInfo pci_ss_info_1002_4c59_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_1002_4c59_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_1002_4c59_104d_80e7 +static const pciSubsystemInfo pci_ss_info_1002_4c59_104d_8140 = + {0x104d, 0x8140, pci_subsys_1002_4c59_104d_8140, 0}; +#undef pci_ss_info_104d_8140 +#define pci_ss_info_104d_8140 pci_ss_info_1002_4c59_104d_8140 +static const pciSubsystemInfo pci_ss_info_1002_4c59_1509_1930 = + {0x1509, 0x1930, pci_subsys_1002_4c59_1509_1930, 0}; +#undef pci_ss_info_1509_1930 +#define pci_ss_info_1509_1930 pci_ss_info_1002_4c59_1509_1930 +static const pciSubsystemInfo pci_ss_info_1002_4e44_1002_515e = + {0x1002, 0x515e, pci_subsys_1002_4e44_1002_515e, 0}; +#undef pci_ss_info_1002_515e +#define pci_ss_info_1002_515e pci_ss_info_1002_4e44_1002_515e +static const pciSubsystemInfo pci_ss_info_1002_4e44_1002_5965 = + {0x1002, 0x5965, pci_subsys_1002_4e44_1002_5965, 0}; +#undef pci_ss_info_1002_5965 +#define pci_ss_info_1002_5965 pci_ss_info_1002_4e44_1002_5965 +static const pciSubsystemInfo pci_ss_info_1002_4e45_1002_0002 = + {0x1002, 0x0002, pci_subsys_1002_4e45_1002_0002, 0}; +#undef pci_ss_info_1002_0002 +#define pci_ss_info_1002_0002 pci_ss_info_1002_4e45_1002_0002 +static const pciSubsystemInfo pci_ss_info_1002_4e45_1681_0002 = + {0x1681, 0x0002, pci_subsys_1002_4e45_1681_0002, 0}; +#undef pci_ss_info_1681_0002 +#define pci_ss_info_1681_0002 pci_ss_info_1002_4e45_1681_0002 +static const pciSubsystemInfo pci_ss_info_1002_4e50_1025_005a = + {0x1025, 0x005a, pci_subsys_1002_4e50_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_1002_4e50_1025_005a +static const pciSubsystemInfo pci_ss_info_1002_4e50_103c_088c = + {0x103c, 0x088c, pci_subsys_1002_4e50_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_1002_4e50_103c_088c +static const pciSubsystemInfo pci_ss_info_1002_4e50_103c_0890 = + {0x103c, 0x0890, pci_subsys_1002_4e50_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_1002_4e50_103c_0890 +static const pciSubsystemInfo pci_ss_info_1002_4e50_1462_0311 = + {0x1462, 0x0311, pci_subsys_1002_4e50_1462_0311, 0}; +#undef pci_ss_info_1462_0311 +#define pci_ss_info_1462_0311 pci_ss_info_1002_4e50_1462_0311 +static const pciSubsystemInfo pci_ss_info_1002_4e50_1734_1055 = + {0x1734, 0x1055, pci_subsys_1002_4e50_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_1002_4e50_1734_1055 +static const pciSubsystemInfo pci_ss_info_1002_4e65_1002_0003 = + {0x1002, 0x0003, pci_subsys_1002_4e65_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_1002_4e65_1002_0003 +static const pciSubsystemInfo pci_ss_info_1002_4e65_1681_0003 = + {0x1681, 0x0003, pci_subsys_1002_4e65_1681_0003, 0}; +#undef pci_ss_info_1681_0003 +#define pci_ss_info_1681_0003 pci_ss_info_1002_4e65_1681_0003 +static const pciSubsystemInfo pci_ss_info_1002_4e6a_1002_4e71 = + {0x1002, 0x4e71, pci_subsys_1002_4e6a_1002_4e71, 0}; +#undef pci_ss_info_1002_4e71 +#define pci_ss_info_1002_4e71 pci_ss_info_1002_4e6a_1002_4e71 +static const pciSubsystemInfo pci_ss_info_1002_5044_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5044_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5044_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5044_1002_0029 = + {0x1002, 0x0029, pci_subsys_1002_5044_1002_0029, 0}; +#undef pci_ss_info_1002_0029 +#define pci_ss_info_1002_0029 pci_ss_info_1002_5044_1002_0029 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_5046_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_5046_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5046_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5046_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0014 = + {0x1002, 0x0014, pci_subsys_1002_5046_1002_0014, 0}; +#undef pci_ss_info_1002_0014 +#define pci_ss_info_1002_0014 pci_ss_info_1002_5046_1002_0014 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0018 = + {0x1002, 0x0018, pci_subsys_1002_5046_1002_0018, 0}; +#undef pci_ss_info_1002_0018 +#define pci_ss_info_1002_0018 pci_ss_info_1002_5046_1002_0018 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5046_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5046_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_002a = + {0x1002, 0x002a, pci_subsys_1002_5046_1002_002a, 0}; +#undef pci_ss_info_1002_002a +#define pci_ss_info_1002_002a pci_ss_info_1002_5046_1002_002a +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_0048 = + {0x1002, 0x0048, pci_subsys_1002_5046_1002_0048, 0}; +#undef pci_ss_info_1002_0048 +#define pci_ss_info_1002_0048 pci_ss_info_1002_5046_1002_0048 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_2000 = + {0x1002, 0x2000, pci_subsys_1002_5046_1002_2000, 0}; +#undef pci_ss_info_1002_2000 +#define pci_ss_info_1002_2000 pci_ss_info_1002_5046_1002_2000 +static const pciSubsystemInfo pci_ss_info_1002_5046_1002_2001 = + {0x1002, 0x2001, pci_subsys_1002_5046_1002_2001, 0}; +#undef pci_ss_info_1002_2001 +#define pci_ss_info_1002_2001 pci_ss_info_1002_5046_1002_2001 +static const pciSubsystemInfo pci_ss_info_1002_5050_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5050_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5050_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5144_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5144_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0009 = + {0x1002, 0x0009, pci_subsys_1002_5144_1002_0009, 0}; +#undef pci_ss_info_1002_0009 +#define pci_ss_info_1002_0009 pci_ss_info_1002_5144_1002_0009 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_000a = + {0x1002, 0x000a, pci_subsys_1002_5144_1002_000a, 0}; +#undef pci_ss_info_1002_000a +#define pci_ss_info_1002_000a pci_ss_info_1002_5144_1002_000a +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_001a = + {0x1002, 0x001a, pci_subsys_1002_5144_1002_001a, 0}; +#undef pci_ss_info_1002_001a +#define pci_ss_info_1002_001a pci_ss_info_1002_5144_1002_001a +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0029 = + {0x1002, 0x0029, pci_subsys_1002_5144_1002_0029, 0}; +#undef pci_ss_info_1002_0029 +#define pci_ss_info_1002_0029 pci_ss_info_1002_5144_1002_0029 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0038 = + {0x1002, 0x0038, pci_subsys_1002_5144_1002_0038, 0}; +#undef pci_ss_info_1002_0038 +#define pci_ss_info_1002_0038 pci_ss_info_1002_5144_1002_0038 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0039 = + {0x1002, 0x0039, pci_subsys_1002_5144_1002_0039, 0}; +#undef pci_ss_info_1002_0039 +#define pci_ss_info_1002_0039 pci_ss_info_1002_5144_1002_0039 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_008a = + {0x1002, 0x008a, pci_subsys_1002_5144_1002_008a, 0}; +#undef pci_ss_info_1002_008a +#define pci_ss_info_1002_008a pci_ss_info_1002_5144_1002_008a +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_00ba = + {0x1002, 0x00ba, pci_subsys_1002_5144_1002_00ba, 0}; +#undef pci_ss_info_1002_00ba +#define pci_ss_info_1002_00ba pci_ss_info_1002_5144_1002_00ba +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_0139 = + {0x1002, 0x0139, pci_subsys_1002_5144_1002_0139, 0}; +#undef pci_ss_info_1002_0139 +#define pci_ss_info_1002_0139 pci_ss_info_1002_5144_1002_0139 +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_028a = + {0x1002, 0x028a, pci_subsys_1002_5144_1002_028a, 0}; +#undef pci_ss_info_1002_028a +#define pci_ss_info_1002_028a pci_ss_info_1002_5144_1002_028a +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_02aa = + {0x1002, 0x02aa, pci_subsys_1002_5144_1002_02aa, 0}; +#undef pci_ss_info_1002_02aa +#define pci_ss_info_1002_02aa pci_ss_info_1002_5144_1002_02aa +static const pciSubsystemInfo pci_ss_info_1002_5144_1002_053a = + {0x1002, 0x053a, pci_subsys_1002_5144_1002_053a, 0}; +#undef pci_ss_info_1002_053a +#define pci_ss_info_1002_053a pci_ss_info_1002_5144_1002_053a +static const pciSubsystemInfo pci_ss_info_1002_5148_1002_010a = + {0x1002, 0x010a, pci_subsys_1002_5148_1002_010a, 0}; +#undef pci_ss_info_1002_010a +#define pci_ss_info_1002_010a pci_ss_info_1002_5148_1002_010a +static const pciSubsystemInfo pci_ss_info_1002_5148_1002_0152 = + {0x1002, 0x0152, pci_subsys_1002_5148_1002_0152, 0}; +#undef pci_ss_info_1002_0152 +#define pci_ss_info_1002_0152 pci_ss_info_1002_5148_1002_0152 +static const pciSubsystemInfo pci_ss_info_1002_5148_1002_0162 = + {0x1002, 0x0162, pci_subsys_1002_5148_1002_0162, 0}; +#undef pci_ss_info_1002_0162 +#define pci_ss_info_1002_0162 pci_ss_info_1002_5148_1002_0162 +static const pciSubsystemInfo pci_ss_info_1002_5148_1002_0172 = + {0x1002, 0x0172, pci_subsys_1002_5148_1002_0172, 0}; +#undef pci_ss_info_1002_0172 +#define pci_ss_info_1002_0172 pci_ss_info_1002_5148_1002_0172 +static const pciSubsystemInfo pci_ss_info_1002_514c_1002_003a = + {0x1002, 0x003a, pci_subsys_1002_514c_1002_003a, 0}; +#undef pci_ss_info_1002_003a +#define pci_ss_info_1002_003a pci_ss_info_1002_514c_1002_003a +static const pciSubsystemInfo pci_ss_info_1002_514c_1002_013a = + {0x1002, 0x013a, pci_subsys_1002_514c_1002_013a, 0}; +#undef pci_ss_info_1002_013a +#define pci_ss_info_1002_013a pci_ss_info_1002_514c_1002_013a +static const pciSubsystemInfo pci_ss_info_1002_514c_148c_2026 = + {0x148c, 0x2026, pci_subsys_1002_514c_148c_2026, 0}; +#undef pci_ss_info_148c_2026 +#define pci_ss_info_148c_2026 pci_ss_info_1002_514c_148c_2026 +static const pciSubsystemInfo pci_ss_info_1002_514c_1681_0010 = + {0x1681, 0x0010, pci_subsys_1002_514c_1681_0010, 0}; +#undef pci_ss_info_1681_0010 +#define pci_ss_info_1681_0010 pci_ss_info_1002_514c_1681_0010 +static const pciSubsystemInfo pci_ss_info_1002_514c_174b_7149 = + {0x174b, 0x7149, pci_subsys_1002_514c_174b_7149, 0}; +#undef pci_ss_info_174b_7149 +#define pci_ss_info_174b_7149 pci_ss_info_1002_514c_174b_7149 +static const pciSubsystemInfo pci_ss_info_1002_5157_1002_013a = + {0x1002, 0x013a, pci_subsys_1002_5157_1002_013a, 0}; +#undef pci_ss_info_1002_013a +#define pci_ss_info_1002_013a pci_ss_info_1002_5157_1002_013a +static const pciSubsystemInfo pci_ss_info_1002_5157_1002_103a = + {0x1002, 0x103a, pci_subsys_1002_5157_1002_103a, 0}; +#undef pci_ss_info_1002_103a +#define pci_ss_info_1002_103a pci_ss_info_1002_5157_1002_103a +static const pciSubsystemInfo pci_ss_info_1002_5157_1458_4000 = + {0x1458, 0x4000, pci_subsys_1002_5157_1458_4000, 0}; +#undef pci_ss_info_1458_4000 +#define pci_ss_info_1458_4000 pci_ss_info_1002_5157_1458_4000 +static const pciSubsystemInfo pci_ss_info_1002_5157_148c_2024 = + {0x148c, 0x2024, pci_subsys_1002_5157_148c_2024, 0}; +#undef pci_ss_info_148c_2024 +#define pci_ss_info_148c_2024 pci_ss_info_1002_5157_148c_2024 +static const pciSubsystemInfo pci_ss_info_1002_5157_148c_2025 = + {0x148c, 0x2025, pci_subsys_1002_5157_148c_2025, 0}; +#undef pci_ss_info_148c_2025 +#define pci_ss_info_148c_2025 pci_ss_info_1002_5157_148c_2025 +static const pciSubsystemInfo pci_ss_info_1002_5157_148c_2036 = + {0x148c, 0x2036, pci_subsys_1002_5157_148c_2036, 0}; +#undef pci_ss_info_148c_2036 +#define pci_ss_info_148c_2036 pci_ss_info_1002_5157_148c_2036 +static const pciSubsystemInfo pci_ss_info_1002_5157_174b_7146 = + {0x174b, 0x7146, pci_subsys_1002_5157_174b_7146, 0}; +#undef pci_ss_info_174b_7146 +#define pci_ss_info_174b_7146 pci_ss_info_1002_5157_174b_7146 +static const pciSubsystemInfo pci_ss_info_1002_5157_174b_7147 = + {0x174b, 0x7147, pci_subsys_1002_5157_174b_7147, 0}; +#undef pci_ss_info_174b_7147 +#define pci_ss_info_174b_7147 pci_ss_info_1002_5157_174b_7147 +static const pciSubsystemInfo pci_ss_info_1002_5157_174b_7161 = + {0x174b, 0x7161, pci_subsys_1002_5157_174b_7161, 0}; +#undef pci_ss_info_174b_7161 +#define pci_ss_info_174b_7161 pci_ss_info_1002_5157_174b_7161 +static const pciSubsystemInfo pci_ss_info_1002_5157_17af_0202 = + {0x17af, 0x0202, pci_subsys_1002_5157_17af_0202, 0}; +#undef pci_ss_info_17af_0202 +#define pci_ss_info_17af_0202 pci_ss_info_1002_5157_17af_0202 +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_000a = + {0x1002, 0x000a, pci_subsys_1002_5159_1002_000a, 0}; +#undef pci_ss_info_1002_000a +#define pci_ss_info_1002_000a pci_ss_info_1002_5159_1002_000a +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_000b = + {0x1002, 0x000b, pci_subsys_1002_5159_1002_000b, 0}; +#undef pci_ss_info_1002_000b +#define pci_ss_info_1002_000b pci_ss_info_1002_5159_1002_000b +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_0038 = + {0x1002, 0x0038, pci_subsys_1002_5159_1002_0038, 0}; +#undef pci_ss_info_1002_0038 +#define pci_ss_info_1002_0038 pci_ss_info_1002_5159_1002_0038 +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_003a = + {0x1002, 0x003a, pci_subsys_1002_5159_1002_003a, 0}; +#undef pci_ss_info_1002_003a +#define pci_ss_info_1002_003a pci_ss_info_1002_5159_1002_003a +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_00ba = + {0x1002, 0x00ba, pci_subsys_1002_5159_1002_00ba, 0}; +#undef pci_ss_info_1002_00ba +#define pci_ss_info_1002_00ba pci_ss_info_1002_5159_1002_00ba +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_013a = + {0x1002, 0x013a, pci_subsys_1002_5159_1002_013a, 0}; +#undef pci_ss_info_1002_013a +#define pci_ss_info_1002_013a pci_ss_info_1002_5159_1002_013a +static const pciSubsystemInfo pci_ss_info_1002_5159_1002_0908 = + {0x1002, 0x0908, pci_subsys_1002_5159_1002_0908, 0}; +#undef pci_ss_info_1002_0908 +#define pci_ss_info_1002_0908 pci_ss_info_1002_5159_1002_0908 +static const pciSubsystemInfo pci_ss_info_1002_5159_1014_029a = + {0x1014, 0x029a, pci_subsys_1002_5159_1014_029a, 0}; +#undef pci_ss_info_1014_029a +#define pci_ss_info_1014_029a pci_ss_info_1002_5159_1014_029a +static const pciSubsystemInfo pci_ss_info_1002_5159_1014_02c8 = + {0x1014, 0x02c8, pci_subsys_1002_5159_1014_02c8, 0}; +#undef pci_ss_info_1014_02c8 +#define pci_ss_info_1014_02c8 pci_ss_info_1002_5159_1014_02c8 +static const pciSubsystemInfo pci_ss_info_1002_5159_1028_019a = + {0x1028, 0x019a, pci_subsys_1002_5159_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_1002_5159_1028_019a +static const pciSubsystemInfo pci_ss_info_1002_5159_103c_1292 = + {0x103c, 0x1292, pci_subsys_1002_5159_103c_1292, 0}; +#undef pci_ss_info_103c_1292 +#define pci_ss_info_103c_1292 pci_ss_info_1002_5159_103c_1292 +static const pciSubsystemInfo pci_ss_info_1002_5159_1458_4002 = + {0x1458, 0x4002, pci_subsys_1002_5159_1458_4002, 0}; +#undef pci_ss_info_1458_4002 +#define pci_ss_info_1458_4002 pci_ss_info_1002_5159_1458_4002 +static const pciSubsystemInfo pci_ss_info_1002_5159_148c_2003 = + {0x148c, 0x2003, pci_subsys_1002_5159_148c_2003, 0}; +#undef pci_ss_info_148c_2003 +#define pci_ss_info_148c_2003 pci_ss_info_1002_5159_148c_2003 +static const pciSubsystemInfo pci_ss_info_1002_5159_148c_2023 = + {0x148c, 0x2023, pci_subsys_1002_5159_148c_2023, 0}; +#undef pci_ss_info_148c_2023 +#define pci_ss_info_148c_2023 pci_ss_info_1002_5159_148c_2023 +static const pciSubsystemInfo pci_ss_info_1002_5159_174b_7112 = + {0x174b, 0x7112, pci_subsys_1002_5159_174b_7112, 0}; +#undef pci_ss_info_174b_7112 +#define pci_ss_info_174b_7112 pci_ss_info_1002_5159_174b_7112 +static const pciSubsystemInfo pci_ss_info_1002_5159_174b_7c28 = + {0x174b, 0x7c28, pci_subsys_1002_5159_174b_7c28, 0}; +#undef pci_ss_info_174b_7c28 +#define pci_ss_info_174b_7c28 pci_ss_info_1002_5159_174b_7c28 +static const pciSubsystemInfo pci_ss_info_1002_5159_1787_0202 = + {0x1787, 0x0202, pci_subsys_1002_5159_1787_0202, 0}; +#undef pci_ss_info_1787_0202 +#define pci_ss_info_1787_0202 pci_ss_info_1002_5159_1787_0202 +static const pciSubsystemInfo pci_ss_info_1002_5159_17ee_1001 = + {0x17ee, 0x1001, pci_subsys_1002_5159_17ee_1001, 0}; +#undef pci_ss_info_17ee_1001 +#define pci_ss_info_17ee_1001 pci_ss_info_1002_5159_17ee_1001 +static const pciSubsystemInfo pci_ss_info_1002_5245_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5245_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5245_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5245_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5245_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5245_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5245_1002_0029 = + {0x1002, 0x0029, pci_subsys_1002_5245_1002_0029, 0}; +#undef pci_ss_info_1002_0029 +#define pci_ss_info_1002_0029 pci_ss_info_1002_5245_1002_0029 +static const pciSubsystemInfo pci_ss_info_1002_5245_1002_0068 = + {0x1002, 0x0068, pci_subsys_1002_5245_1002_0068, 0}; +#undef pci_ss_info_1002_0068 +#define pci_ss_info_1002_0068 pci_ss_info_1002_5245_1002_0068 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_5246_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_5246_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5246_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5246_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5246_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5246_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0044 = + {0x1002, 0x0044, pci_subsys_1002_5246_1002_0044, 0}; +#undef pci_ss_info_1002_0044 +#define pci_ss_info_1002_0044 pci_ss_info_1002_5246_1002_0044 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0068 = + {0x1002, 0x0068, pci_subsys_1002_5246_1002_0068, 0}; +#undef pci_ss_info_1002_0068 +#define pci_ss_info_1002_0068 pci_ss_info_1002_5246_1002_0068 +static const pciSubsystemInfo pci_ss_info_1002_5246_1002_0448 = + {0x1002, 0x0448, pci_subsys_1002_5246_1002_0448, 0}; +#undef pci_ss_info_1002_0448 +#define pci_ss_info_1002_0448 pci_ss_info_1002_5246_1002_0448 +static const pciSubsystemInfo pci_ss_info_1002_524c_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_524c_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_524c_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_524c_1002_0088 = + {0x1002, 0x0088, pci_subsys_1002_524c_1002_0088, 0}; +#undef pci_ss_info_1002_0088 +#define pci_ss_info_1002_0088 pci_ss_info_1002_524c_1002_0088 +static const pciSubsystemInfo pci_ss_info_1002_5346_1002_0048 = + {0x1002, 0x0048, pci_subsys_1002_5346_1002_0048, 0}; +#undef pci_ss_info_1002_0048 +#define pci_ss_info_1002_0048 pci_ss_info_1002_5346_1002_0048 +static const pciSubsystemInfo pci_ss_info_1002_534d_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_534d_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_534d_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_534d_1002_0018 = + {0x1002, 0x0018, pci_subsys_1002_534d_1002_0018, 0}; +#undef pci_ss_info_1002_0018 +#define pci_ss_info_1002_0018 pci_ss_info_1002_534d_1002_0018 +static const pciSubsystemInfo pci_ss_info_1002_5354_1002_5654 = + {0x1002, 0x5654, pci_subsys_1002_5354_1002_5654, 0}; +#undef pci_ss_info_1002_5654 +#define pci_ss_info_1002_5654 pci_ss_info_1002_5354_1002_5654 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0004 = + {0x1002, 0x0004, pci_subsys_1002_5446_1002_0004, 0}; +#undef pci_ss_info_1002_0004 +#define pci_ss_info_1002_0004 pci_ss_info_1002_5446_1002_0004 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0008 = + {0x1002, 0x0008, pci_subsys_1002_5446_1002_0008, 0}; +#undef pci_ss_info_1002_0008 +#define pci_ss_info_1002_0008 pci_ss_info_1002_5446_1002_0008 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0018 = + {0x1002, 0x0018, pci_subsys_1002_5446_1002_0018, 0}; +#undef pci_ss_info_1002_0018 +#define pci_ss_info_1002_0018 pci_ss_info_1002_5446_1002_0018 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0028 = + {0x1002, 0x0028, pci_subsys_1002_5446_1002_0028, 0}; +#undef pci_ss_info_1002_0028 +#define pci_ss_info_1002_0028 pci_ss_info_1002_5446_1002_0028 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0029 = + {0x1002, 0x0029, pci_subsys_1002_5446_1002_0029, 0}; +#undef pci_ss_info_1002_0029 +#define pci_ss_info_1002_0029 pci_ss_info_1002_5446_1002_0029 +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_002a = + {0x1002, 0x002a, pci_subsys_1002_5446_1002_002a, 0}; +#undef pci_ss_info_1002_002a +#define pci_ss_info_1002_002a pci_ss_info_1002_5446_1002_002a +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_002b = + {0x1002, 0x002b, pci_subsys_1002_5446_1002_002b, 0}; +#undef pci_ss_info_1002_002b +#define pci_ss_info_1002_002b pci_ss_info_1002_5446_1002_002b +static const pciSubsystemInfo pci_ss_info_1002_5446_1002_0048 = + {0x1002, 0x0048, pci_subsys_1002_5446_1002_0048, 0}; +#undef pci_ss_info_1002_0048 +#define pci_ss_info_1002_0048 pci_ss_info_1002_5446_1002_0048 +static const pciSubsystemInfo pci_ss_info_1002_5452_1002_001c = + {0x1002, 0x001c, pci_subsys_1002_5452_1002_001c, 0}; +#undef pci_ss_info_1002_001c +#define pci_ss_info_1002_001c pci_ss_info_1002_5452_1002_001c +static const pciSubsystemInfo pci_ss_info_1002_5452_103c_1279 = + {0x103c, 0x1279, pci_subsys_1002_5452_103c_1279, 0}; +#undef pci_ss_info_103c_1279 +#define pci_ss_info_103c_1279 pci_ss_info_1002_5452_103c_1279 +static const pciSubsystemInfo pci_ss_info_1002_5653_1025_0080 = + {0x1025, 0x0080, pci_subsys_1002_5653_1025_0080, 0}; +#undef pci_ss_info_1025_0080 +#define pci_ss_info_1025_0080 pci_ss_info_1002_5653_1025_0080 +static const pciSubsystemInfo pci_ss_info_1002_5654_1002_5654 = + {0x1002, 0x5654, pci_subsys_1002_5654_1002_5654, 0}; +#undef pci_ss_info_1002_5654 +#define pci_ss_info_1002_5654 pci_ss_info_1002_5654_1002_5654 +static const pciSubsystemInfo pci_ss_info_1002_5941_1458_4019 = + {0x1458, 0x4019, pci_subsys_1002_5941_1458_4019, 0}; +#undef pci_ss_info_1458_4019 +#define pci_ss_info_1458_4019 pci_ss_info_1002_5941_1458_4019 +static const pciSubsystemInfo pci_ss_info_1002_5941_174b_7c12 = + {0x174b, 0x7c12, pci_subsys_1002_5941_174b_7c12, 0}; +#undef pci_ss_info_174b_7c12 +#define pci_ss_info_174b_7c12 pci_ss_info_1002_5941_174b_7c12 +static const pciSubsystemInfo pci_ss_info_1002_5941_17af_200d = + {0x17af, 0x200d, pci_subsys_1002_5941_17af_200d, 0}; +#undef pci_ss_info_17af_200d +#define pci_ss_info_17af_200d pci_ss_info_1002_5941_17af_200d +static const pciSubsystemInfo pci_ss_info_1002_5941_18bc_0050 = + {0x18bc, 0x0050, pci_subsys_1002_5941_18bc_0050, 0}; +#undef pci_ss_info_18bc_0050 +#define pci_ss_info_18bc_0050 pci_ss_info_1002_5941_18bc_0050 +static const pciSubsystemInfo pci_ss_info_1002_5950_1025_0080 = + {0x1025, 0x0080, pci_subsys_1002_5950_1025_0080, 0}; +#undef pci_ss_info_1025_0080 +#define pci_ss_info_1025_0080 pci_ss_info_1002_5950_1025_0080 +static const pciSubsystemInfo pci_ss_info_1002_5950_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_5950_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_5950_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_5954_1002_5954 = + {0x1002, 0x5954, pci_subsys_1002_5954_1002_5954, 0}; +#undef pci_ss_info_1002_5954 +#define pci_ss_info_1002_5954 pci_ss_info_1002_5954_1002_5954 +static const pciSubsystemInfo pci_ss_info_1002_5955_1002_5955 = + {0x1002, 0x5955, pci_subsys_1002_5955_1002_5955, 0}; +#undef pci_ss_info_1002_5955 +#define pci_ss_info_1002_5955 pci_ss_info_1002_5955_1002_5955 +static const pciSubsystemInfo pci_ss_info_1002_5955_103c_308b = + {0x103c, 0x308b, pci_subsys_1002_5955_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_1002_5955_103c_308b +static const pciSubsystemInfo pci_ss_info_1002_5961_1002_2f72 = + {0x1002, 0x2f72, pci_subsys_1002_5961_1002_2f72, 0}; +#undef pci_ss_info_1002_2f72 +#define pci_ss_info_1002_2f72 pci_ss_info_1002_5961_1002_2f72 +static const pciSubsystemInfo pci_ss_info_1002_5961_1019_4c30 = + {0x1019, 0x4c30, pci_subsys_1002_5961_1019_4c30, 0}; +#undef pci_ss_info_1019_4c30 +#define pci_ss_info_1019_4c30 pci_ss_info_1002_5961_1019_4c30 +static const pciSubsystemInfo pci_ss_info_1002_5961_12ab_5961 = + {0x12ab, 0x5961, pci_subsys_1002_5961_12ab_5961, 0}; +#undef pci_ss_info_12ab_5961 +#define pci_ss_info_12ab_5961 pci_ss_info_1002_5961_12ab_5961 +static const pciSubsystemInfo pci_ss_info_1002_5961_1458_4018 = + {0x1458, 0x4018, pci_subsys_1002_5961_1458_4018, 0}; +#undef pci_ss_info_1458_4018 +#define pci_ss_info_1458_4018 pci_ss_info_1002_5961_1458_4018 +static const pciSubsystemInfo pci_ss_info_1002_5961_174b_7c13 = + {0x174b, 0x7c13, pci_subsys_1002_5961_174b_7c13, 0}; +#undef pci_ss_info_174b_7c13 +#define pci_ss_info_174b_7c13 pci_ss_info_1002_5961_174b_7c13 +static const pciSubsystemInfo pci_ss_info_1002_5961_17af_200c = + {0x17af, 0x200c, pci_subsys_1002_5961_17af_200c, 0}; +#undef pci_ss_info_17af_200c +#define pci_ss_info_17af_200c pci_ss_info_1002_5961_17af_200c +static const pciSubsystemInfo pci_ss_info_1002_5961_18bc_0050 = + {0x18bc, 0x0050, pci_subsys_1002_5961_18bc_0050, 0}; +#undef pci_ss_info_18bc_0050 +#define pci_ss_info_18bc_0050 pci_ss_info_1002_5961_18bc_0050 +static const pciSubsystemInfo pci_ss_info_1002_5961_18bc_0051 = + {0x18bc, 0x0051, pci_subsys_1002_5961_18bc_0051, 0}; +#undef pci_ss_info_18bc_0051 +#define pci_ss_info_18bc_0051 pci_ss_info_1002_5961_18bc_0051 +static const pciSubsystemInfo pci_ss_info_1002_5961_18bc_0053 = + {0x18bc, 0x0053, pci_subsys_1002_5961_18bc_0053, 0}; +#undef pci_ss_info_18bc_0053 +#define pci_ss_info_18bc_0053 pci_ss_info_1002_5961_18bc_0053 +static const pciSubsystemInfo pci_ss_info_1002_5964_1043_c006 = + {0x1043, 0xc006, pci_subsys_1002_5964_1043_c006, 0}; +#undef pci_ss_info_1043_c006 +#define pci_ss_info_1043_c006 pci_ss_info_1002_5964_1043_c006 +static const pciSubsystemInfo pci_ss_info_1002_5964_1458_4018 = + {0x1458, 0x4018, pci_subsys_1002_5964_1458_4018, 0}; +#undef pci_ss_info_1458_4018 +#define pci_ss_info_1458_4018 pci_ss_info_1002_5964_1458_4018 +static const pciSubsystemInfo pci_ss_info_1002_5964_1458_4032 = + {0x1458, 0x4032, pci_subsys_1002_5964_1458_4032, 0}; +#undef pci_ss_info_1458_4032 +#define pci_ss_info_1458_4032 pci_ss_info_1002_5964_1458_4032 +static const pciSubsystemInfo pci_ss_info_1002_5964_147b_6191 = + {0x147b, 0x6191, pci_subsys_1002_5964_147b_6191, 0}; +#undef pci_ss_info_147b_6191 +#define pci_ss_info_147b_6191 pci_ss_info_1002_5964_147b_6191 +static const pciSubsystemInfo pci_ss_info_1002_5964_148c_2073 = + {0x148c, 0x2073, pci_subsys_1002_5964_148c_2073, 0}; +#undef pci_ss_info_148c_2073 +#define pci_ss_info_148c_2073 pci_ss_info_1002_5964_148c_2073 +static const pciSubsystemInfo pci_ss_info_1002_5964_174b_7c13 = + {0x174b, 0x7c13, pci_subsys_1002_5964_174b_7c13, 0}; +#undef pci_ss_info_174b_7c13 +#define pci_ss_info_174b_7c13 pci_ss_info_1002_5964_174b_7c13 +static const pciSubsystemInfo pci_ss_info_1002_5964_1787_5964 = + {0x1787, 0x5964, pci_subsys_1002_5964_1787_5964, 0}; +#undef pci_ss_info_1787_5964 +#define pci_ss_info_1787_5964 pci_ss_info_1002_5964_1787_5964 +static const pciSubsystemInfo pci_ss_info_1002_5964_17af_2012 = + {0x17af, 0x2012, pci_subsys_1002_5964_17af_2012, 0}; +#undef pci_ss_info_17af_2012 +#define pci_ss_info_17af_2012 pci_ss_info_1002_5964_17af_2012 +static const pciSubsystemInfo pci_ss_info_1002_5964_18bc_0170 = + {0x18bc, 0x0170, pci_subsys_1002_5964_18bc_0170, 0}; +#undef pci_ss_info_18bc_0170 +#define pci_ss_info_18bc_0170 pci_ss_info_1002_5964_18bc_0170 +static const pciSubsystemInfo pci_ss_info_1002_5964_18bc_0173 = + {0x18bc, 0x0173, pci_subsys_1002_5964_18bc_0173, 0}; +#undef pci_ss_info_18bc_0173 +#define pci_ss_info_18bc_0173 pci_ss_info_1002_5964_18bc_0173 +static const pciSubsystemInfo pci_ss_info_1002_5b60_1043_002a = + {0x1043, 0x002a, pci_subsys_1002_5b60_1043_002a, 0}; +#undef pci_ss_info_1043_002a +#define pci_ss_info_1043_002a pci_ss_info_1002_5b60_1043_002a +static const pciSubsystemInfo pci_ss_info_1002_5b60_1043_032e = + {0x1043, 0x032e, pci_subsys_1002_5b60_1043_032e, 0}; +#undef pci_ss_info_1043_032e +#define pci_ss_info_1043_032e pci_ss_info_1002_5b60_1043_032e +static const pciSubsystemInfo pci_ss_info_1002_5b60_1462_0400 = + {0x1462, 0x0400, pci_subsys_1002_5b60_1462_0400, 0}; +#undef pci_ss_info_1462_0400 +#define pci_ss_info_1462_0400 pci_ss_info_1002_5b60_1462_0400 +static const pciSubsystemInfo pci_ss_info_1002_5b60_1462_0402 = + {0x1462, 0x0402, pci_subsys_1002_5b60_1462_0402, 0}; +#undef pci_ss_info_1462_0402 +#define pci_ss_info_1462_0402 pci_ss_info_1002_5b60_1462_0402 +static const pciSubsystemInfo pci_ss_info_1002_5b60_196d_1086 = + {0x196d, 0x1086, pci_subsys_1002_5b60_196d_1086, 0}; +#undef pci_ss_info_196d_1086 +#define pci_ss_info_196d_1086 pci_ss_info_1002_5b60_196d_1086 +static const pciSubsystemInfo pci_ss_info_1002_5b70_1462_0403 = + {0x1462, 0x0403, pci_subsys_1002_5b70_1462_0403, 0}; +#undef pci_ss_info_1462_0403 +#define pci_ss_info_1462_0403 pci_ss_info_1002_5b70_1462_0403 +static const pciSubsystemInfo pci_ss_info_1002_5b70_196d_1087 = + {0x196d, 0x1087, pci_subsys_1002_5b70_196d_1087, 0}; +#undef pci_ss_info_196d_1087 +#define pci_ss_info_196d_1087 pci_ss_info_1002_5b70_196d_1087 +static const pciSubsystemInfo pci_ss_info_1002_5c63_1002_5c63 = + {0x1002, 0x5c63, pci_subsys_1002_5c63_1002_5c63, 0}; +#undef pci_ss_info_1002_5c63 +#define pci_ss_info_1002_5c63 pci_ss_info_1002_5c63_1002_5c63 +static const pciSubsystemInfo pci_ss_info_1002_5d44_1458_4019 = + {0x1458, 0x4019, pci_subsys_1002_5d44_1458_4019, 0}; +#undef pci_ss_info_1458_4019 +#define pci_ss_info_1458_4019 pci_ss_info_1002_5d44_1458_4019 +static const pciSubsystemInfo pci_ss_info_1002_5d44_1458_4032 = + {0x1458, 0x4032, pci_subsys_1002_5d44_1458_4032, 0}; +#undef pci_ss_info_1458_4032 +#define pci_ss_info_1458_4032 pci_ss_info_1002_5d44_1458_4032 +static const pciSubsystemInfo pci_ss_info_1002_5d44_174b_7c12 = + {0x174b, 0x7c12, pci_subsys_1002_5d44_174b_7c12, 0}; +#undef pci_ss_info_174b_7c12 +#define pci_ss_info_174b_7c12 pci_ss_info_1002_5d44_174b_7c12 +static const pciSubsystemInfo pci_ss_info_1002_5d44_1787_5965 = + {0x1787, 0x5965, pci_subsys_1002_5d44_1787_5965, 0}; +#undef pci_ss_info_1787_5965 +#define pci_ss_info_1787_5965 pci_ss_info_1002_5d44_1787_5965 +static const pciSubsystemInfo pci_ss_info_1002_5d44_17af_2013 = + {0x17af, 0x2013, pci_subsys_1002_5d44_17af_2013, 0}; +#undef pci_ss_info_17af_2013 +#define pci_ss_info_17af_2013 pci_ss_info_1002_5d44_17af_2013 +static const pciSubsystemInfo pci_ss_info_1002_5d44_18bc_0171 = + {0x18bc, 0x0171, pci_subsys_1002_5d44_18bc_0171, 0}; +#undef pci_ss_info_18bc_0171 +#define pci_ss_info_18bc_0171 pci_ss_info_1002_5d44_18bc_0171 +static const pciSubsystemInfo pci_ss_info_1002_5d44_18bc_0172 = + {0x18bc, 0x0172, pci_subsys_1002_5d44_18bc_0172, 0}; +#undef pci_ss_info_18bc_0172 +#define pci_ss_info_18bc_0172 pci_ss_info_1002_5d44_18bc_0172 +static const pciSubsystemInfo pci_ss_info_1002_5d52_1002_0b12 = + {0x1002, 0x0b12, pci_subsys_1002_5d52_1002_0b12, 0}; +#undef pci_ss_info_1002_0b12 +#define pci_ss_info_1002_0b12 pci_ss_info_1002_5d52_1002_0b12 +static const pciSubsystemInfo pci_ss_info_1002_5d52_1002_0b13 = + {0x1002, 0x0b13, pci_subsys_1002_5d52_1002_0b13, 0}; +#undef pci_ss_info_1002_0b13 +#define pci_ss_info_1002_0b13 pci_ss_info_1002_5d52_1002_0b13 +static const pciSubsystemInfo pci_ss_info_1002_5e4d_148c_2116 = + {0x148c, 0x2116, pci_subsys_1002_5e4d_148c_2116, 0}; +#undef pci_ss_info_148c_2116 +#define pci_ss_info_148c_2116 pci_ss_info_1002_5e4d_148c_2116 +static const pciSubsystemInfo pci_ss_info_1002_5e6d_148c_2117 = + {0x148c, 0x2117, pci_subsys_1002_5e6d_148c_2117, 0}; +#undef pci_ss_info_148c_2117 +#define pci_ss_info_148c_2117 pci_ss_info_1002_5e6d_148c_2117 +static const pciSubsystemInfo pci_ss_info_1002_7109_1002_0322 = + {0x1002, 0x0322, pci_subsys_1002_7109_1002_0322, 0}; +#undef pci_ss_info_1002_0322 +#define pci_ss_info_1002_0322 pci_ss_info_1002_7109_1002_0322 +static const pciSubsystemInfo pci_ss_info_1002_7109_1002_0d02 = + {0x1002, 0x0d02, pci_subsys_1002_7109_1002_0d02, 0}; +#undef pci_ss_info_1002_0d02 +#define pci_ss_info_1002_0d02 pci_ss_info_1002_7109_1002_0d02 +static const pciSubsystemInfo pci_ss_info_1002_7129_1002_0323 = + {0x1002, 0x0323, pci_subsys_1002_7129_1002_0323, 0}; +#undef pci_ss_info_1002_0323 +#define pci_ss_info_1002_0323 pci_ss_info_1002_7129_1002_0323 +static const pciSubsystemInfo pci_ss_info_1002_7129_1002_0d03 = + {0x1002, 0x0d03, pci_subsys_1002_7129_1002_0d03, 0}; +#undef pci_ss_info_1002_0d03 +#define pci_ss_info_1002_0d03 pci_ss_info_1002_7129_1002_0d03 +static const pciSubsystemInfo pci_ss_info_1002_7142_1002_0322 = + {0x1002, 0x0322, pci_subsys_1002_7142_1002_0322, 0}; +#undef pci_ss_info_1002_0322 +#define pci_ss_info_1002_0322 pci_ss_info_1002_7142_1002_0322 +static const pciSubsystemInfo pci_ss_info_1002_7146_1002_0322 = + {0x1002, 0x0322, pci_subsys_1002_7146_1002_0322, 0}; +#undef pci_ss_info_1002_0322 +#define pci_ss_info_1002_0322 pci_ss_info_1002_7146_1002_0322 +static const pciSubsystemInfo pci_ss_info_1002_7162_1002_0323 = + {0x1002, 0x0323, pci_subsys_1002_7162_1002_0323, 0}; +#undef pci_ss_info_1002_0323 +#define pci_ss_info_1002_0323 pci_ss_info_1002_7162_1002_0323 +static const pciSubsystemInfo pci_ss_info_1002_7166_1002_0323 = + {0x1002, 0x0323, pci_subsys_1002_7166_1002_0323, 0}; +#undef pci_ss_info_1002_0323 +#define pci_ss_info_1002_0323 pci_ss_info_1002_7166_1002_0323 +static const pciSubsystemInfo pci_ss_info_1002_71c4_17aa_2007 = + {0x17aa, 0x2007, pci_subsys_1002_71c4_17aa_2007, 0}; +#undef pci_ss_info_17aa_2007 +#define pci_ss_info_17aa_2007 pci_ss_info_1002_71c4_17aa_2007 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1004_0304_1004_0304 = + {0x1004, 0x0304, pci_subsys_1004_0304_1004_0304, 0}; +#undef pci_ss_info_1004_0304 +#define pci_ss_info_1004_0304 pci_ss_info_1004_0304_1004_0304 +static const pciSubsystemInfo pci_ss_info_1004_0304_122d_1206 = + {0x122d, 0x1206, pci_subsys_1004_0304_122d_1206, 0}; +#undef pci_ss_info_122d_1206 +#define pci_ss_info_122d_1206 pci_ss_info_1004_0304_122d_1206 +static const pciSubsystemInfo pci_ss_info_1004_0304_1483_5020 = + {0x1483, 0x5020, pci_subsys_1004_0304_1483_5020, 0}; +#undef pci_ss_info_1483_5020 +#define pci_ss_info_1483_5020 pci_ss_info_1004_0304_1483_5020 +static const pciSubsystemInfo pci_ss_info_1004_0305_1004_0305 = + {0x1004, 0x0305, pci_subsys_1004_0305_1004_0305, 0}; +#undef pci_ss_info_1004_0305 +#define pci_ss_info_1004_0305 pci_ss_info_1004_0305_1004_0305 +static const pciSubsystemInfo pci_ss_info_1004_0305_122d_1207 = + {0x122d, 0x1207, pci_subsys_1004_0305_122d_1207, 0}; +#undef pci_ss_info_122d_1207 +#define pci_ss_info_122d_1207 pci_ss_info_1004_0305_122d_1207 +static const pciSubsystemInfo pci_ss_info_1004_0305_1483_5021 = + {0x1483, 0x5021, pci_subsys_1004_0305_1483_5021, 0}; +#undef pci_ss_info_1483_5021 +#define pci_ss_info_1483_5021 pci_ss_info_1004_0305_1483_5021 +static const pciSubsystemInfo pci_ss_info_1004_0306_1004_0306 = + {0x1004, 0x0306, pci_subsys_1004_0306_1004_0306, 0}; +#undef pci_ss_info_1004_0306 +#define pci_ss_info_1004_0306 pci_ss_info_1004_0306_1004_0306 +static const pciSubsystemInfo pci_ss_info_1004_0306_122d_1208 = + {0x122d, 0x1208, pci_subsys_1004_0306_122d_1208, 0}; +#undef pci_ss_info_122d_1208 +#define pci_ss_info_122d_1208 pci_ss_info_1004_0306_122d_1208 +static const pciSubsystemInfo pci_ss_info_1004_0306_1483_5022 = + {0x1483, 0x5022, pci_subsys_1004_0306_1483_5022, 0}; +#undef pci_ss_info_1483_5022 +#define pci_ss_info_1483_5022 pci_ss_info_1004_0306_1483_5022 +#endif +static const pciSubsystemInfo pci_ss_info_100b_0020_103c_0024 = + {0x103c, 0x0024, pci_subsys_100b_0020_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_100b_0020_103c_0024 +static const pciSubsystemInfo pci_ss_info_100b_0020_12d9_000c = + {0x12d9, 0x000c, pci_subsys_100b_0020_12d9_000c, 0}; +#undef pci_ss_info_12d9_000c +#define pci_ss_info_12d9_000c pci_ss_info_100b_0020_12d9_000c +static const pciSubsystemInfo pci_ss_info_100b_0020_1385_f311 = + {0x1385, 0xf311, pci_subsys_100b_0020_1385_f311, 0}; +#undef pci_ss_info_1385_f311 +#define pci_ss_info_1385_f311 pci_ss_info_100b_0020_1385_f311 +static const pciSubsystemInfo pci_ss_info_1011_0009_1025_0310 = + {0x1025, 0x0310, pci_subsys_1011_0009_1025_0310, 0}; +#undef pci_ss_info_1025_0310 +#define pci_ss_info_1025_0310 pci_ss_info_1011_0009_1025_0310 +static const pciSubsystemInfo pci_ss_info_1011_0009_10b8_2001 = + {0x10b8, 0x2001, pci_subsys_1011_0009_10b8_2001, 0}; +#undef pci_ss_info_10b8_2001 +#define pci_ss_info_10b8_2001 pci_ss_info_1011_0009_10b8_2001 +static const pciSubsystemInfo pci_ss_info_1011_0009_10b8_2002 = + {0x10b8, 0x2002, pci_subsys_1011_0009_10b8_2002, 0}; +#undef pci_ss_info_10b8_2002 +#define pci_ss_info_10b8_2002 pci_ss_info_1011_0009_10b8_2002 +static const pciSubsystemInfo pci_ss_info_1011_0009_10b8_2003 = + {0x10b8, 0x2003, pci_subsys_1011_0009_10b8_2003, 0}; +#undef pci_ss_info_10b8_2003 +#define pci_ss_info_10b8_2003 pci_ss_info_1011_0009_10b8_2003 +static const pciSubsystemInfo pci_ss_info_1011_0009_1109_2400 = + {0x1109, 0x2400, pci_subsys_1011_0009_1109_2400, 0}; +#undef pci_ss_info_1109_2400 +#define pci_ss_info_1109_2400 pci_ss_info_1011_0009_1109_2400 +static const pciSubsystemInfo pci_ss_info_1011_0009_1112_2300 = + {0x1112, 0x2300, pci_subsys_1011_0009_1112_2300, 0}; +#undef pci_ss_info_1112_2300 +#define pci_ss_info_1112_2300 pci_ss_info_1011_0009_1112_2300 +static const pciSubsystemInfo pci_ss_info_1011_0009_1112_2320 = + {0x1112, 0x2320, pci_subsys_1011_0009_1112_2320, 0}; +#undef pci_ss_info_1112_2320 +#define pci_ss_info_1112_2320 pci_ss_info_1011_0009_1112_2320 +static const pciSubsystemInfo pci_ss_info_1011_0009_1112_2340 = + {0x1112, 0x2340, pci_subsys_1011_0009_1112_2340, 0}; +#undef pci_ss_info_1112_2340 +#define pci_ss_info_1112_2340 pci_ss_info_1011_0009_1112_2340 +static const pciSubsystemInfo pci_ss_info_1011_0009_1113_1207 = + {0x1113, 0x1207, pci_subsys_1011_0009_1113_1207, 0}; +#undef pci_ss_info_1113_1207 +#define pci_ss_info_1113_1207 pci_ss_info_1011_0009_1113_1207 +static const pciSubsystemInfo pci_ss_info_1011_0009_1186_1100 = + {0x1186, 0x1100, pci_subsys_1011_0009_1186_1100, 0}; +#undef pci_ss_info_1186_1100 +#define pci_ss_info_1186_1100 pci_ss_info_1011_0009_1186_1100 +static const pciSubsystemInfo pci_ss_info_1011_0009_1186_1112 = + {0x1186, 0x1112, pci_subsys_1011_0009_1186_1112, 0}; +#undef pci_ss_info_1186_1112 +#define pci_ss_info_1186_1112 pci_ss_info_1011_0009_1186_1112 +static const pciSubsystemInfo pci_ss_info_1011_0009_1186_1140 = + {0x1186, 0x1140, pci_subsys_1011_0009_1186_1140, 0}; +#undef pci_ss_info_1186_1140 +#define pci_ss_info_1186_1140 pci_ss_info_1011_0009_1186_1140 +static const pciSubsystemInfo pci_ss_info_1011_0009_1186_1142 = + {0x1186, 0x1142, pci_subsys_1011_0009_1186_1142, 0}; +#undef pci_ss_info_1186_1142 +#define pci_ss_info_1186_1142 pci_ss_info_1011_0009_1186_1142 +static const pciSubsystemInfo pci_ss_info_1011_0009_11f6_0503 = + {0x11f6, 0x0503, pci_subsys_1011_0009_11f6_0503, 0}; +#undef pci_ss_info_11f6_0503 +#define pci_ss_info_11f6_0503 pci_ss_info_1011_0009_11f6_0503 +static const pciSubsystemInfo pci_ss_info_1011_0009_1282_9100 = + {0x1282, 0x9100, pci_subsys_1011_0009_1282_9100, 0}; +#undef pci_ss_info_1282_9100 +#define pci_ss_info_1282_9100 pci_ss_info_1011_0009_1282_9100 +static const pciSubsystemInfo pci_ss_info_1011_0009_1385_1100 = + {0x1385, 0x1100, pci_subsys_1011_0009_1385_1100, 0}; +#undef pci_ss_info_1385_1100 +#define pci_ss_info_1385_1100 pci_ss_info_1011_0009_1385_1100 +static const pciSubsystemInfo pci_ss_info_1011_0009_2646_0001 = + {0x2646, 0x0001, pci_subsys_1011_0009_2646_0001, 0}; +#undef pci_ss_info_2646_0001 +#define pci_ss_info_2646_0001 pci_ss_info_1011_0009_2646_0001 +static const pciSubsystemInfo pci_ss_info_1011_000f_1011_def1 = + {0x1011, 0xdef1, pci_subsys_1011_000f_1011_def1, 0}; +#undef pci_ss_info_1011_def1 +#define pci_ss_info_1011_def1 pci_ss_info_1011_000f_1011_def1 +static const pciSubsystemInfo pci_ss_info_1011_000f_103c_def1 = + {0x103c, 0xdef1, pci_subsys_1011_000f_103c_def1, 0}; +#undef pci_ss_info_103c_def1 +#define pci_ss_info_103c_def1 pci_ss_info_1011_000f_103c_def1 +static const pciSubsystemInfo pci_ss_info_1011_0014_1186_0100 = + {0x1186, 0x0100, pci_subsys_1011_0014_1186_0100, 0}; +#undef pci_ss_info_1186_0100 +#define pci_ss_info_1186_0100 pci_ss_info_1011_0014_1186_0100 +static const pciSubsystemInfo pci_ss_info_1011_0019_1011_500a = + {0x1011, 0x500a, pci_subsys_1011_0019_1011_500a, 0}; +#undef pci_ss_info_1011_500a +#define pci_ss_info_1011_500a pci_ss_info_1011_0019_1011_500a +static const pciSubsystemInfo pci_ss_info_1011_0019_1011_500b = + {0x1011, 0x500b, pci_subsys_1011_0019_1011_500b, 0}; +#undef pci_ss_info_1011_500b +#define pci_ss_info_1011_500b pci_ss_info_1011_0019_1011_500b +static const pciSubsystemInfo pci_ss_info_1011_0019_1014_0001 = + {0x1014, 0x0001, pci_subsys_1011_0019_1014_0001, 0}; +#undef pci_ss_info_1014_0001 +#define pci_ss_info_1014_0001 pci_ss_info_1011_0019_1014_0001 +static const pciSubsystemInfo pci_ss_info_1011_0019_1025_0315 = + {0x1025, 0x0315, pci_subsys_1011_0019_1025_0315, 0}; +#undef pci_ss_info_1025_0315 +#define pci_ss_info_1025_0315 pci_ss_info_1011_0019_1025_0315 +static const pciSubsystemInfo pci_ss_info_1011_0019_1033_800c = + {0x1033, 0x800c, pci_subsys_1011_0019_1033_800c, 0}; +#undef pci_ss_info_1033_800c +#define pci_ss_info_1033_800c pci_ss_info_1011_0019_1033_800c +static const pciSubsystemInfo pci_ss_info_1011_0019_1033_800d = + {0x1033, 0x800d, pci_subsys_1011_0019_1033_800d, 0}; +#undef pci_ss_info_1033_800d +#define pci_ss_info_1033_800d pci_ss_info_1011_0019_1033_800d +static const pciSubsystemInfo pci_ss_info_1011_0019_103c_125a = + {0x103c, 0x125a, pci_subsys_1011_0019_103c_125a, 0}; +#undef pci_ss_info_103c_125a +#define pci_ss_info_103c_125a pci_ss_info_1011_0019_103c_125a +static const pciSubsystemInfo pci_ss_info_1011_0019_108d_0016 = + {0x108d, 0x0016, pci_subsys_1011_0019_108d_0016, 0}; +#undef pci_ss_info_108d_0016 +#define pci_ss_info_108d_0016 pci_ss_info_1011_0019_108d_0016 +static const pciSubsystemInfo pci_ss_info_1011_0019_108d_0017 = + {0x108d, 0x0017, pci_subsys_1011_0019_108d_0017, 0}; +#undef pci_ss_info_108d_0017 +#define pci_ss_info_108d_0017 pci_ss_info_1011_0019_108d_0017 +static const pciSubsystemInfo pci_ss_info_1011_0019_10b8_2005 = + {0x10b8, 0x2005, pci_subsys_1011_0019_10b8_2005, 0}; +#undef pci_ss_info_10b8_2005 +#define pci_ss_info_10b8_2005 pci_ss_info_1011_0019_10b8_2005 +static const pciSubsystemInfo pci_ss_info_1011_0019_10b8_8034 = + {0x10b8, 0x8034, pci_subsys_1011_0019_10b8_8034, 0}; +#undef pci_ss_info_10b8_8034 +#define pci_ss_info_10b8_8034 pci_ss_info_1011_0019_10b8_8034 +static const pciSubsystemInfo pci_ss_info_1011_0019_10ef_8169 = + {0x10ef, 0x8169, pci_subsys_1011_0019_10ef_8169, 0}; +#undef pci_ss_info_10ef_8169 +#define pci_ss_info_10ef_8169 pci_ss_info_1011_0019_10ef_8169 +static const pciSubsystemInfo pci_ss_info_1011_0019_1109_2a00 = + {0x1109, 0x2a00, pci_subsys_1011_0019_1109_2a00, 0}; +#undef pci_ss_info_1109_2a00 +#define pci_ss_info_1109_2a00 pci_ss_info_1011_0019_1109_2a00 +static const pciSubsystemInfo pci_ss_info_1011_0019_1109_2b00 = + {0x1109, 0x2b00, pci_subsys_1011_0019_1109_2b00, 0}; +#undef pci_ss_info_1109_2b00 +#define pci_ss_info_1109_2b00 pci_ss_info_1011_0019_1109_2b00 +static const pciSubsystemInfo pci_ss_info_1011_0019_1109_3000 = + {0x1109, 0x3000, pci_subsys_1011_0019_1109_3000, 0}; +#undef pci_ss_info_1109_3000 +#define pci_ss_info_1109_3000 pci_ss_info_1011_0019_1109_3000 +static const pciSubsystemInfo pci_ss_info_1011_0019_1113_1207 = + {0x1113, 0x1207, pci_subsys_1011_0019_1113_1207, 0}; +#undef pci_ss_info_1113_1207 +#define pci_ss_info_1113_1207 pci_ss_info_1011_0019_1113_1207 +static const pciSubsystemInfo pci_ss_info_1011_0019_1113_2220 = + {0x1113, 0x2220, pci_subsys_1011_0019_1113_2220, 0}; +#undef pci_ss_info_1113_2220 +#define pci_ss_info_1113_2220 pci_ss_info_1011_0019_1113_2220 +static const pciSubsystemInfo pci_ss_info_1011_0019_115d_0002 = + {0x115d, 0x0002, pci_subsys_1011_0019_115d_0002, 0}; +#undef pci_ss_info_115d_0002 +#define pci_ss_info_115d_0002 pci_ss_info_1011_0019_115d_0002 +static const pciSubsystemInfo pci_ss_info_1011_0019_1179_0203 = + {0x1179, 0x0203, pci_subsys_1011_0019_1179_0203, 0}; +#undef pci_ss_info_1179_0203 +#define pci_ss_info_1179_0203 pci_ss_info_1011_0019_1179_0203 +static const pciSubsystemInfo pci_ss_info_1011_0019_1179_0204 = + {0x1179, 0x0204, pci_subsys_1011_0019_1179_0204, 0}; +#undef pci_ss_info_1179_0204 +#define pci_ss_info_1179_0204 pci_ss_info_1011_0019_1179_0204 +static const pciSubsystemInfo pci_ss_info_1011_0019_1186_1100 = + {0x1186, 0x1100, pci_subsys_1011_0019_1186_1100, 0}; +#undef pci_ss_info_1186_1100 +#define pci_ss_info_1186_1100 pci_ss_info_1011_0019_1186_1100 +static const pciSubsystemInfo pci_ss_info_1011_0019_1186_1101 = + {0x1186, 0x1101, pci_subsys_1011_0019_1186_1101, 0}; +#undef pci_ss_info_1186_1101 +#define pci_ss_info_1186_1101 pci_ss_info_1011_0019_1186_1101 +static const pciSubsystemInfo pci_ss_info_1011_0019_1186_1102 = + {0x1186, 0x1102, pci_subsys_1011_0019_1186_1102, 0}; +#undef pci_ss_info_1186_1102 +#define pci_ss_info_1186_1102 pci_ss_info_1011_0019_1186_1102 +static const pciSubsystemInfo pci_ss_info_1011_0019_1186_1112 = + {0x1186, 0x1112, pci_subsys_1011_0019_1186_1112, 0}; +#undef pci_ss_info_1186_1112 +#define pci_ss_info_1186_1112 pci_ss_info_1011_0019_1186_1112 +static const pciSubsystemInfo pci_ss_info_1011_0019_1259_2800 = + {0x1259, 0x2800, pci_subsys_1011_0019_1259_2800, 0}; +#undef pci_ss_info_1259_2800 +#define pci_ss_info_1259_2800 pci_ss_info_1011_0019_1259_2800 +static const pciSubsystemInfo pci_ss_info_1011_0019_1266_0004 = + {0x1266, 0x0004, pci_subsys_1011_0019_1266_0004, 0}; +#undef pci_ss_info_1266_0004 +#define pci_ss_info_1266_0004 pci_ss_info_1011_0019_1266_0004 +static const pciSubsystemInfo pci_ss_info_1011_0019_12af_0019 = + {0x12af, 0x0019, pci_subsys_1011_0019_12af_0019, 0}; +#undef pci_ss_info_12af_0019 +#define pci_ss_info_12af_0019 pci_ss_info_1011_0019_12af_0019 +static const pciSubsystemInfo pci_ss_info_1011_0019_1374_0001 = + {0x1374, 0x0001, pci_subsys_1011_0019_1374_0001, 0}; +#undef pci_ss_info_1374_0001 +#define pci_ss_info_1374_0001 pci_ss_info_1011_0019_1374_0001 +static const pciSubsystemInfo pci_ss_info_1011_0019_1374_0002 = + {0x1374, 0x0002, pci_subsys_1011_0019_1374_0002, 0}; +#undef pci_ss_info_1374_0002 +#define pci_ss_info_1374_0002 pci_ss_info_1011_0019_1374_0002 +static const pciSubsystemInfo pci_ss_info_1011_0019_1374_0007 = + {0x1374, 0x0007, pci_subsys_1011_0019_1374_0007, 0}; +#undef pci_ss_info_1374_0007 +#define pci_ss_info_1374_0007 pci_ss_info_1011_0019_1374_0007 +static const pciSubsystemInfo pci_ss_info_1011_0019_1374_0008 = + {0x1374, 0x0008, pci_subsys_1011_0019_1374_0008, 0}; +#undef pci_ss_info_1374_0008 +#define pci_ss_info_1374_0008 pci_ss_info_1011_0019_1374_0008 +static const pciSubsystemInfo pci_ss_info_1011_0019_1385_2100 = + {0x1385, 0x2100, pci_subsys_1011_0019_1385_2100, 0}; +#undef pci_ss_info_1385_2100 +#define pci_ss_info_1385_2100 pci_ss_info_1011_0019_1385_2100 +static const pciSubsystemInfo pci_ss_info_1011_0019_1395_0001 = + {0x1395, 0x0001, pci_subsys_1011_0019_1395_0001, 0}; +#undef pci_ss_info_1395_0001 +#define pci_ss_info_1395_0001 pci_ss_info_1011_0019_1395_0001 +static const pciSubsystemInfo pci_ss_info_1011_0019_13d1_ab01 = + {0x13d1, 0xab01, pci_subsys_1011_0019_13d1_ab01, 0}; +#undef pci_ss_info_13d1_ab01 +#define pci_ss_info_13d1_ab01 pci_ss_info_1011_0019_13d1_ab01 +static const pciSubsystemInfo pci_ss_info_1011_0019_1498_000a = + {0x1498, 0x000a, pci_subsys_1011_0019_1498_000a, 0}; +#undef pci_ss_info_1498_000a +#define pci_ss_info_1498_000a pci_ss_info_1011_0019_1498_000a +static const pciSubsystemInfo pci_ss_info_1011_0019_1498_000b = + {0x1498, 0x000b, pci_subsys_1011_0019_1498_000b, 0}; +#undef pci_ss_info_1498_000b +#define pci_ss_info_1498_000b pci_ss_info_1011_0019_1498_000b +static const pciSubsystemInfo pci_ss_info_1011_0019_1498_000c = + {0x1498, 0x000c, pci_subsys_1011_0019_1498_000c, 0}; +#undef pci_ss_info_1498_000c +#define pci_ss_info_1498_000c pci_ss_info_1011_0019_1498_000c +static const pciSubsystemInfo pci_ss_info_1011_0019_14cb_0100 = + {0x14cb, 0x0100, pci_subsys_1011_0019_14cb_0100, 0}; +#undef pci_ss_info_14cb_0100 +#define pci_ss_info_14cb_0100 pci_ss_info_1011_0019_14cb_0100 +static const pciSubsystemInfo pci_ss_info_1011_0019_8086_0001 = + {0x8086, 0x0001, pci_subsys_1011_0019_8086_0001, 0}; +#undef pci_ss_info_8086_0001 +#define pci_ss_info_8086_0001 pci_ss_info_1011_0019_8086_0001 +static const pciSubsystemInfo pci_ss_info_1011_0034_1374_0003 = + {0x1374, 0x0003, pci_subsys_1011_0034_1374_0003, 0}; +#undef pci_ss_info_1374_0003 +#define pci_ss_info_1374_0003 pci_ss_info_1011_0034_1374_0003 +static const pciSubsystemInfo pci_ss_info_1011_0046_0e11_4050 = + {0x0e11, 0x4050, pci_subsys_1011_0046_0e11_4050, 0}; +#undef pci_ss_info_0e11_4050 +#define pci_ss_info_0e11_4050 pci_ss_info_1011_0046_0e11_4050 +static const pciSubsystemInfo pci_ss_info_1011_0046_0e11_4051 = + {0x0e11, 0x4051, pci_subsys_1011_0046_0e11_4051, 0}; +#undef pci_ss_info_0e11_4051 +#define pci_ss_info_0e11_4051 pci_ss_info_1011_0046_0e11_4051 +static const pciSubsystemInfo pci_ss_info_1011_0046_0e11_4058 = + {0x0e11, 0x4058, pci_subsys_1011_0046_0e11_4058, 0}; +#undef pci_ss_info_0e11_4058 +#define pci_ss_info_0e11_4058 pci_ss_info_1011_0046_0e11_4058 +static const pciSubsystemInfo pci_ss_info_1011_0046_103c_10c2 = + {0x103c, 0x10c2, pci_subsys_1011_0046_103c_10c2, 0}; +#undef pci_ss_info_103c_10c2 +#define pci_ss_info_103c_10c2 pci_ss_info_1011_0046_103c_10c2 +static const pciSubsystemInfo pci_ss_info_1011_0046_12d9_000a = + {0x12d9, 0x000a, pci_subsys_1011_0046_12d9_000a, 0}; +#undef pci_ss_info_12d9_000a +#define pci_ss_info_12d9_000a pci_ss_info_1011_0046_12d9_000a +static const pciSubsystemInfo pci_ss_info_1011_0046_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_1011_0046_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_1011_0046_4c53_1050 +static const pciSubsystemInfo pci_ss_info_1011_0046_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_1011_0046_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_1011_0046_4c53_1051 +static const pciSubsystemInfo pci_ss_info_1011_0046_9005_0364 = + {0x9005, 0x0364, pci_subsys_1011_0046_9005_0364, 0}; +#undef pci_ss_info_9005_0364 +#define pci_ss_info_9005_0364 pci_ss_info_1011_0046_9005_0364 +static const pciSubsystemInfo pci_ss_info_1011_0046_9005_0365 = + {0x9005, 0x0365, pci_subsys_1011_0046_9005_0365, 0}; +#undef pci_ss_info_9005_0365 +#define pci_ss_info_9005_0365 pci_ss_info_1011_0046_9005_0365 +static const pciSubsystemInfo pci_ss_info_1011_0046_9005_1364 = + {0x9005, 0x1364, pci_subsys_1011_0046_9005_1364, 0}; +#undef pci_ss_info_9005_1364 +#define pci_ss_info_9005_1364 pci_ss_info_1011_0046_9005_1364 +static const pciSubsystemInfo pci_ss_info_1011_0046_9005_1365 = + {0x9005, 0x1365, pci_subsys_1011_0046_9005_1365, 0}; +#undef pci_ss_info_9005_1365 +#define pci_ss_info_9005_1365 pci_ss_info_1011_0046_9005_1365 +static const pciSubsystemInfo pci_ss_info_1011_0046_e4bf_1000 = + {0xe4bf, 0x1000, pci_subsys_1011_0046_e4bf_1000, 0}; +#undef pci_ss_info_e4bf_1000 +#define pci_ss_info_e4bf_1000 pci_ss_info_1011_0046_e4bf_1000 +static const pciSubsystemInfo pci_ss_info_1011_1065_1069_0020 = + {0x1069, 0x0020, pci_subsys_1011_1065_1069_0020, 0}; +#undef pci_ss_info_1069_0020 +#define pci_ss_info_1069_0020 pci_ss_info_1011_1065_1069_0020 +static const pciSubsystemInfo pci_ss_info_1013_00bc_1013_00bc = + {0x1013, 0x00bc, pci_subsys_1013_00bc_1013_00bc, 0}; +#undef pci_ss_info_1013_00bc +#define pci_ss_info_1013_00bc pci_ss_info_1013_00bc_1013_00bc +static const pciSubsystemInfo pci_ss_info_1013_00d6_13ce_8031 = + {0x13ce, 0x8031, pci_subsys_1013_00d6_13ce_8031, 0}; +#undef pci_ss_info_13ce_8031 +#define pci_ss_info_13ce_8031 pci_ss_info_1013_00d6_13ce_8031 +static const pciSubsystemInfo pci_ss_info_1013_00d6_13cf_8031 = + {0x13cf, 0x8031, pci_subsys_1013_00d6_13cf_8031, 0}; +#undef pci_ss_info_13cf_8031 +#define pci_ss_info_13cf_8031 pci_ss_info_1013_00d6_13cf_8031 +static const pciSubsystemInfo pci_ss_info_1013_6001_1014_1010 = + {0x1014, 0x1010, pci_subsys_1013_6001_1014_1010, 0}; +#undef pci_ss_info_1014_1010 +#define pci_ss_info_1014_1010 pci_ss_info_1013_6001_1014_1010 +static const pciSubsystemInfo pci_ss_info_1013_6003_1013_4280 = + {0x1013, 0x4280, pci_subsys_1013_6003_1013_4280, 0}; +#undef pci_ss_info_1013_4280 +#define pci_ss_info_1013_4280 pci_ss_info_1013_6003_1013_4280 +static const pciSubsystemInfo pci_ss_info_1013_6003_1014_0153 = + {0x1014, 0x0153, pci_subsys_1013_6003_1014_0153, 0}; +#undef pci_ss_info_1014_0153 +#define pci_ss_info_1014_0153 pci_ss_info_1013_6003_1014_0153 +static const pciSubsystemInfo pci_ss_info_1013_6003_153b_112e = + {0x153b, 0x112e, pci_subsys_1013_6003_153b_112e, 0}; +#undef pci_ss_info_153b_112e +#define pci_ss_info_153b_112e pci_ss_info_1013_6003_153b_112e +static const pciSubsystemInfo pci_ss_info_1013_6003_153b_1136 = + {0x153b, 0x1136, pci_subsys_1013_6003_153b_1136, 0}; +#undef pci_ss_info_153b_1136 +#define pci_ss_info_153b_1136 pci_ss_info_1013_6003_153b_1136 +static const pciSubsystemInfo pci_ss_info_1013_6003_1681_0050 = + {0x1681, 0x0050, pci_subsys_1013_6003_1681_0050, 0}; +#undef pci_ss_info_1681_0050 +#define pci_ss_info_1681_0050 pci_ss_info_1013_6003_1681_0050 +static const pciSubsystemInfo pci_ss_info_1013_6003_1681_a011 = + {0x1681, 0xa011, pci_subsys_1013_6003_1681_a011, 0}; +#undef pci_ss_info_1681_a011 +#define pci_ss_info_1681_a011 pci_ss_info_1013_6003_1681_a011 +static const pciSubsystemInfo pci_ss_info_1013_6003_5053_3357 = + {0x5053, 0x3357, pci_subsys_1013_6003_5053_3357, 0}; +#undef pci_ss_info_5053_3357 +#define pci_ss_info_5053_3357 pci_ss_info_1013_6003_5053_3357 +static const pciSubsystemInfo pci_ss_info_1013_6005_1013_4281 = + {0x1013, 0x4281, pci_subsys_1013_6005_1013_4281, 0}; +#undef pci_ss_info_1013_4281 +#define pci_ss_info_1013_4281 pci_ss_info_1013_6005_1013_4281 +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10a8 = + {0x10cf, 0x10a8, pci_subsys_1013_6005_10cf_10a8, 0}; +#undef pci_ss_info_10cf_10a8 +#define pci_ss_info_10cf_10a8 pci_ss_info_1013_6005_10cf_10a8 +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10a9 = + {0x10cf, 0x10a9, pci_subsys_1013_6005_10cf_10a9, 0}; +#undef pci_ss_info_10cf_10a9 +#define pci_ss_info_10cf_10a9 pci_ss_info_1013_6005_10cf_10a9 +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10aa = + {0x10cf, 0x10aa, pci_subsys_1013_6005_10cf_10aa, 0}; +#undef pci_ss_info_10cf_10aa +#define pci_ss_info_10cf_10aa pci_ss_info_1013_6005_10cf_10aa +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10ab = + {0x10cf, 0x10ab, pci_subsys_1013_6005_10cf_10ab, 0}; +#undef pci_ss_info_10cf_10ab +#define pci_ss_info_10cf_10ab pci_ss_info_1013_6005_10cf_10ab +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10ac = + {0x10cf, 0x10ac, pci_subsys_1013_6005_10cf_10ac, 0}; +#undef pci_ss_info_10cf_10ac +#define pci_ss_info_10cf_10ac pci_ss_info_1013_6005_10cf_10ac +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10ad = + {0x10cf, 0x10ad, pci_subsys_1013_6005_10cf_10ad, 0}; +#undef pci_ss_info_10cf_10ad +#define pci_ss_info_10cf_10ad pci_ss_info_1013_6005_10cf_10ad +static const pciSubsystemInfo pci_ss_info_1013_6005_10cf_10b4 = + {0x10cf, 0x10b4, pci_subsys_1013_6005_10cf_10b4, 0}; +#undef pci_ss_info_10cf_10b4 +#define pci_ss_info_10cf_10b4 pci_ss_info_1013_6005_10cf_10b4 +static const pciSubsystemInfo pci_ss_info_1013_6005_1179_0001 = + {0x1179, 0x0001, pci_subsys_1013_6005_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1013_6005_1179_0001 +static const pciSubsystemInfo pci_ss_info_1013_6005_14c0_000c = + {0x14c0, 0x000c, pci_subsys_1013_6005_14c0_000c, 0}; +#undef pci_ss_info_14c0_000c +#define pci_ss_info_14c0_000c pci_ss_info_1013_6005_14c0_000c +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1014_002e_1014_002e = + {0x1014, 0x002e, pci_subsys_1014_002e_1014_002e, 0}; +#undef pci_ss_info_1014_002e +#define pci_ss_info_1014_002e pci_ss_info_1014_002e_1014_002e +static const pciSubsystemInfo pci_ss_info_1014_002e_1014_022e = + {0x1014, 0x022e, pci_subsys_1014_002e_1014_022e, 0}; +#undef pci_ss_info_1014_022e +#define pci_ss_info_1014_022e pci_ss_info_1014_002e_1014_022e +static const pciSubsystemInfo pci_ss_info_1014_0031_1014_0031 = + {0x1014, 0x0031, pci_subsys_1014_0031_1014_0031, 0}; +#undef pci_ss_info_1014_0031 +#define pci_ss_info_1014_0031 pci_ss_info_1014_0031_1014_0031 +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_003e = + {0x1014, 0x003e, pci_subsys_1014_003e_1014_003e, 0}; +#undef pci_ss_info_1014_003e +#define pci_ss_info_1014_003e pci_ss_info_1014_003e_1014_003e +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00cd = + {0x1014, 0x00cd, pci_subsys_1014_003e_1014_00cd, 0}; +#undef pci_ss_info_1014_00cd +#define pci_ss_info_1014_00cd pci_ss_info_1014_003e_1014_00cd +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00ce = + {0x1014, 0x00ce, pci_subsys_1014_003e_1014_00ce, 0}; +#undef pci_ss_info_1014_00ce +#define pci_ss_info_1014_00ce pci_ss_info_1014_003e_1014_00ce +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00cf = + {0x1014, 0x00cf, pci_subsys_1014_003e_1014_00cf, 0}; +#undef pci_ss_info_1014_00cf +#define pci_ss_info_1014_00cf pci_ss_info_1014_003e_1014_00cf +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00e4 = + {0x1014, 0x00e4, pci_subsys_1014_003e_1014_00e4, 0}; +#undef pci_ss_info_1014_00e4 +#define pci_ss_info_1014_00e4 pci_ss_info_1014_003e_1014_00e4 +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_00e5 = + {0x1014, 0x00e5, pci_subsys_1014_003e_1014_00e5, 0}; +#undef pci_ss_info_1014_00e5 +#define pci_ss_info_1014_00e5 pci_ss_info_1014_003e_1014_00e5 +static const pciSubsystemInfo pci_ss_info_1014_003e_1014_016d = + {0x1014, 0x016d, pci_subsys_1014_003e_1014_016d, 0}; +#undef pci_ss_info_1014_016d +#define pci_ss_info_1014_016d pci_ss_info_1014_003e_1014_016d +static const pciSubsystemInfo pci_ss_info_1014_0090_1014_008e = + {0x1014, 0x008e, pci_subsys_1014_0090_1014_008e, 0}; +#undef pci_ss_info_1014_008e +#define pci_ss_info_1014_008e pci_ss_info_1014_0090_1014_008e +static const pciSubsystemInfo pci_ss_info_1014_0096_1014_0097 = + {0x1014, 0x0097, pci_subsys_1014_0096_1014_0097, 0}; +#undef pci_ss_info_1014_0097 +#define pci_ss_info_1014_0097 pci_ss_info_1014_0096_1014_0097 +static const pciSubsystemInfo pci_ss_info_1014_0096_1014_0098 = + {0x1014, 0x0098, pci_subsys_1014_0096_1014_0098, 0}; +#undef pci_ss_info_1014_0098 +#define pci_ss_info_1014_0098 pci_ss_info_1014_0096_1014_0098 +static const pciSubsystemInfo pci_ss_info_1014_0096_1014_0099 = + {0x1014, 0x0099, pci_subsys_1014_0096_1014_0099, 0}; +#undef pci_ss_info_1014_0099 +#define pci_ss_info_1014_0099 pci_ss_info_1014_0096_1014_0099 +#endif +static const pciSubsystemInfo pci_ss_info_1014_00b7_1092_00b8 = + {0x1092, 0x00b8, pci_subsys_1014_00b7_1092_00b8, 0}; +#undef pci_ss_info_1092_00b8 +#define pci_ss_info_1092_00b8 pci_ss_info_1014_00b7_1092_00b8 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1014_0142_1014_0143 = + {0x1014, 0x0143, pci_subsys_1014_0142_1014_0143, 0}; +#undef pci_ss_info_1014_0143 +#define pci_ss_info_1014_0143 pci_ss_info_1014_0142_1014_0143 +static const pciSubsystemInfo pci_ss_info_1014_0144_1014_0145 = + {0x1014, 0x0145, pci_subsys_1014_0144_1014_0145, 0}; +#undef pci_ss_info_1014_0145 +#define pci_ss_info_1014_0145 pci_ss_info_1014_0144_1014_0145 +static const pciSubsystemInfo pci_ss_info_1014_0180_1014_0241 = + {0x1014, 0x0241, pci_subsys_1014_0180_1014_0241, 0}; +#undef pci_ss_info_1014_0241 +#define pci_ss_info_1014_0241 pci_ss_info_1014_0180_1014_0241 +static const pciSubsystemInfo pci_ss_info_1014_0180_1014_0264 = + {0x1014, 0x0264, pci_subsys_1014_0180_1014_0264, 0}; +#undef pci_ss_info_1014_0264 +#define pci_ss_info_1014_0264 pci_ss_info_1014_0180_1014_0264 +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_01be = + {0x1014, 0x01be, pci_subsys_1014_01bd_1014_01be, 0}; +#undef pci_ss_info_1014_01be +#define pci_ss_info_1014_01be pci_ss_info_1014_01bd_1014_01be +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_01bf = + {0x1014, 0x01bf, pci_subsys_1014_01bd_1014_01bf, 0}; +#undef pci_ss_info_1014_01bf +#define pci_ss_info_1014_01bf pci_ss_info_1014_01bd_1014_01bf +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_0208 = + {0x1014, 0x0208, pci_subsys_1014_01bd_1014_0208, 0}; +#undef pci_ss_info_1014_0208 +#define pci_ss_info_1014_0208 pci_ss_info_1014_01bd_1014_0208 +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_020e = + {0x1014, 0x020e, pci_subsys_1014_01bd_1014_020e, 0}; +#undef pci_ss_info_1014_020e +#define pci_ss_info_1014_020e pci_ss_info_1014_01bd_1014_020e +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_022e = + {0x1014, 0x022e, pci_subsys_1014_01bd_1014_022e, 0}; +#undef pci_ss_info_1014_022e +#define pci_ss_info_1014_022e pci_ss_info_1014_01bd_1014_022e +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_0258 = + {0x1014, 0x0258, pci_subsys_1014_01bd_1014_0258, 0}; +#undef pci_ss_info_1014_0258 +#define pci_ss_info_1014_0258 pci_ss_info_1014_01bd_1014_0258 +static const pciSubsystemInfo pci_ss_info_1014_01bd_1014_0259 = + {0x1014, 0x0259, pci_subsys_1014_01bd_1014_0259, 0}; +#undef pci_ss_info_1014_0259 +#define pci_ss_info_1014_0259 pci_ss_info_1014_01bd_1014_0259 +static const pciSubsystemInfo pci_ss_info_1014_0219_1014_021a = + {0x1014, 0x021a, pci_subsys_1014_0219_1014_021a, 0}; +#undef pci_ss_info_1014_021a +#define pci_ss_info_1014_021a pci_ss_info_1014_0219_1014_021a +static const pciSubsystemInfo pci_ss_info_1014_0219_1014_0251 = + {0x1014, 0x0251, pci_subsys_1014_0219_1014_0251, 0}; +#undef pci_ss_info_1014_0251 +#define pci_ss_info_1014_0251 pci_ss_info_1014_0219_1014_0251 +static const pciSubsystemInfo pci_ss_info_1014_0219_1014_0252 = + {0x1014, 0x0252, pci_subsys_1014_0219_1014_0252, 0}; +#undef pci_ss_info_1014_0252 +#define pci_ss_info_1014_0252 pci_ss_info_1014_0219_1014_0252 +static const pciSubsystemInfo pci_ss_info_1014_028c_1014_028d = + {0x1014, 0x028d, pci_subsys_1014_028c_1014_028d, 0}; +#undef pci_ss_info_1014_028d +#define pci_ss_info_1014_028d pci_ss_info_1014_028c_1014_028d +static const pciSubsystemInfo pci_ss_info_1014_028c_1014_02be = + {0x1014, 0x02be, pci_subsys_1014_028c_1014_02be, 0}; +#undef pci_ss_info_1014_02be +#define pci_ss_info_1014_02be pci_ss_info_1014_028c_1014_02be +static const pciSubsystemInfo pci_ss_info_1014_028c_1014_02c0 = + {0x1014, 0x02c0, pci_subsys_1014_028c_1014_02c0, 0}; +#undef pci_ss_info_1014_02c0 +#define pci_ss_info_1014_02c0 pci_ss_info_1014_028c_1014_02c0 +static const pciSubsystemInfo pci_ss_info_1014_028c_1014_030d = + {0x1014, 0x030d, pci_subsys_1014_028c_1014_030d, 0}; +#undef pci_ss_info_1014_030d +#define pci_ss_info_1014_030d pci_ss_info_1014_028c_1014_030d +static const pciSubsystemInfo pci_ss_info_1014_02bd_1014_02c1 = + {0x1014, 0x02c1, pci_subsys_1014_02bd_1014_02c1, 0}; +#undef pci_ss_info_1014_02c1 +#define pci_ss_info_1014_02c1 pci_ss_info_1014_02bd_1014_02c1 +static const pciSubsystemInfo pci_ss_info_1014_02bd_1014_02c2 = + {0x1014, 0x02c2, pci_subsys_1014_02bd_1014_02c2, 0}; +#undef pci_ss_info_1014_02c2 +#define pci_ss_info_1014_02c2 pci_ss_info_1014_02bd_1014_02c2 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0471 = + {0x101e, 0x0471, pci_subsys_101e_1960_101e_0471, 0}; +#undef pci_ss_info_101e_0471 +#define pci_ss_info_101e_0471 pci_ss_info_101e_1960_101e_0471 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0475 = + {0x101e, 0x0475, pci_subsys_101e_1960_101e_0475, 0}; +#undef pci_ss_info_101e_0475 +#define pci_ss_info_101e_0475 pci_ss_info_101e_1960_101e_0475 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0477 = + {0x101e, 0x0477, pci_subsys_101e_1960_101e_0477, 0}; +#undef pci_ss_info_101e_0477 +#define pci_ss_info_101e_0477 pci_ss_info_101e_1960_101e_0477 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0493 = + {0x101e, 0x0493, pci_subsys_101e_1960_101e_0493, 0}; +#undef pci_ss_info_101e_0493 +#define pci_ss_info_101e_0493 pci_ss_info_101e_1960_101e_0493 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0494 = + {0x101e, 0x0494, pci_subsys_101e_1960_101e_0494, 0}; +#undef pci_ss_info_101e_0494 +#define pci_ss_info_101e_0494 pci_ss_info_101e_1960_101e_0494 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0503 = + {0x101e, 0x0503, pci_subsys_101e_1960_101e_0503, 0}; +#undef pci_ss_info_101e_0503 +#define pci_ss_info_101e_0503 pci_ss_info_101e_1960_101e_0503 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0511 = + {0x101e, 0x0511, pci_subsys_101e_1960_101e_0511, 0}; +#undef pci_ss_info_101e_0511 +#define pci_ss_info_101e_0511 pci_ss_info_101e_1960_101e_0511 +static const pciSubsystemInfo pci_ss_info_101e_1960_101e_0522 = + {0x101e, 0x0522, pci_subsys_101e_1960_101e_0522, 0}; +#undef pci_ss_info_101e_0522 +#define pci_ss_info_101e_0522 pci_ss_info_101e_1960_101e_0522 +#endif +static const pciSubsystemInfo pci_ss_info_101e_1960_1028_0471 = + {0x1028, 0x0471, pci_subsys_101e_1960_1028_0471, 0}; +#undef pci_ss_info_1028_0471 +#define pci_ss_info_1028_0471 pci_ss_info_101e_1960_1028_0471 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_101e_1960_1028_0475 = + {0x1028, 0x0475, pci_subsys_101e_1960_1028_0475, 0}; +#undef pci_ss_info_1028_0475 +#define pci_ss_info_1028_0475 pci_ss_info_101e_1960_1028_0475 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_101e_1960_1028_0493 = + {0x1028, 0x0493, pci_subsys_101e_1960_1028_0493, 0}; +#undef pci_ss_info_1028_0493 +#define pci_ss_info_1028_0493 pci_ss_info_101e_1960_1028_0493 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_101e_1960_1028_0511 = + {0x1028, 0x0511, pci_subsys_101e_1960_1028_0511, 0}; +#undef pci_ss_info_1028_0511 +#define pci_ss_info_1028_0511 pci_ss_info_101e_1960_1028_0511 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_101e_1960_103c_60e7 = + {0x103c, 0x60e7, pci_subsys_101e_1960_103c_60e7, 0}; +#undef pci_ss_info_103c_60e7 +#define pci_ss_info_103c_60e7 pci_ss_info_101e_1960_103c_60e7 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_101e_9063_101e_0767 = + {0x101e, 0x0767, pci_subsys_101e_9063_101e_0767, 0}; +#undef pci_ss_info_101e_0767 +#define pci_ss_info_101e_0767 pci_ss_info_101e_9063_101e_0767 +#endif +static const pciSubsystemInfo pci_ss_info_1022_2000_1014_2000 = + {0x1014, 0x2000, pci_subsys_1022_2000_1014_2000, 0}; +#undef pci_ss_info_1014_2000 +#define pci_ss_info_1014_2000 pci_ss_info_1022_2000_1014_2000 +static const pciSubsystemInfo pci_ss_info_1022_2000_1022_2000 = + {0x1022, 0x2000, pci_subsys_1022_2000_1022_2000, 0}; +#undef pci_ss_info_1022_2000 +#define pci_ss_info_1022_2000 pci_ss_info_1022_2000_1022_2000 +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_104c = + {0x103c, 0x104c, pci_subsys_1022_2000_103c_104c, 0}; +#undef pci_ss_info_103c_104c +#define pci_ss_info_103c_104c pci_ss_info_1022_2000_103c_104c +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_1064 = + {0x103c, 0x1064, pci_subsys_1022_2000_103c_1064, 0}; +#undef pci_ss_info_103c_1064 +#define pci_ss_info_103c_1064 pci_ss_info_1022_2000_103c_1064 +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_1065 = + {0x103c, 0x1065, pci_subsys_1022_2000_103c_1065, 0}; +#undef pci_ss_info_103c_1065 +#define pci_ss_info_103c_1065 pci_ss_info_1022_2000_103c_1065 +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_106c = + {0x103c, 0x106c, pci_subsys_1022_2000_103c_106c, 0}; +#undef pci_ss_info_103c_106c +#define pci_ss_info_103c_106c pci_ss_info_1022_2000_103c_106c +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_106e = + {0x103c, 0x106e, pci_subsys_1022_2000_103c_106e, 0}; +#undef pci_ss_info_103c_106e +#define pci_ss_info_103c_106e pci_ss_info_1022_2000_103c_106e +static const pciSubsystemInfo pci_ss_info_1022_2000_103c_10ea = + {0x103c, 0x10ea, pci_subsys_1022_2000_103c_10ea, 0}; +#undef pci_ss_info_103c_10ea +#define pci_ss_info_103c_10ea pci_ss_info_1022_2000_103c_10ea +static const pciSubsystemInfo pci_ss_info_1022_2000_1113_1220 = + {0x1113, 0x1220, pci_subsys_1022_2000_1113_1220, 0}; +#undef pci_ss_info_1113_1220 +#define pci_ss_info_1113_1220 pci_ss_info_1022_2000_1113_1220 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2450 = + {0x1259, 0x2450, pci_subsys_1022_2000_1259_2450, 0}; +#undef pci_ss_info_1259_2450 +#define pci_ss_info_1259_2450 pci_ss_info_1022_2000_1259_2450 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2454 = + {0x1259, 0x2454, pci_subsys_1022_2000_1259_2454, 0}; +#undef pci_ss_info_1259_2454 +#define pci_ss_info_1259_2454 pci_ss_info_1022_2000_1259_2454 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2700 = + {0x1259, 0x2700, pci_subsys_1022_2000_1259_2700, 0}; +#undef pci_ss_info_1259_2700 +#define pci_ss_info_1259_2700 pci_ss_info_1022_2000_1259_2700 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2701 = + {0x1259, 0x2701, pci_subsys_1022_2000_1259_2701, 0}; +#undef pci_ss_info_1259_2701 +#define pci_ss_info_1259_2701 pci_ss_info_1022_2000_1259_2701 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2702 = + {0x1259, 0x2702, pci_subsys_1022_2000_1259_2702, 0}; +#undef pci_ss_info_1259_2702 +#define pci_ss_info_1259_2702 pci_ss_info_1022_2000_1259_2702 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2703 = + {0x1259, 0x2703, pci_subsys_1022_2000_1259_2703, 0}; +#undef pci_ss_info_1259_2703 +#define pci_ss_info_1259_2703 pci_ss_info_1022_2000_1259_2703 +static const pciSubsystemInfo pci_ss_info_1022_2000_1259_2704 = + {0x1259, 0x2704, pci_subsys_1022_2000_1259_2704, 0}; +#undef pci_ss_info_1259_2704 +#define pci_ss_info_1259_2704 pci_ss_info_1022_2000_1259_2704 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_1022_2000_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_1022_2000_4c53_1000 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1010 = + {0x4c53, 0x1010, pci_subsys_1022_2000_4c53_1010, 0}; +#undef pci_ss_info_4c53_1010 +#define pci_ss_info_4c53_1010 pci_ss_info_1022_2000_4c53_1010 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1020 = + {0x4c53, 0x1020, pci_subsys_1022_2000_4c53_1020, 0}; +#undef pci_ss_info_4c53_1020 +#define pci_ss_info_4c53_1020 pci_ss_info_1022_2000_4c53_1020 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1030 = + {0x4c53, 0x1030, pci_subsys_1022_2000_4c53_1030, 0}; +#undef pci_ss_info_4c53_1030 +#define pci_ss_info_4c53_1030 pci_ss_info_1022_2000_4c53_1030 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1040 = + {0x4c53, 0x1040, pci_subsys_1022_2000_4c53_1040, 0}; +#undef pci_ss_info_4c53_1040 +#define pci_ss_info_4c53_1040 pci_ss_info_1022_2000_4c53_1040 +static const pciSubsystemInfo pci_ss_info_1022_2000_4c53_1060 = + {0x4c53, 0x1060, pci_subsys_1022_2000_4c53_1060, 0}; +#undef pci_ss_info_4c53_1060 +#define pci_ss_info_4c53_1060 pci_ss_info_1022_2000_4c53_1060 +static const pciSubsystemInfo pci_ss_info_1022_2001_1092_0a78 = + {0x1092, 0x0a78, pci_subsys_1022_2001_1092_0a78, 0}; +#undef pci_ss_info_1092_0a78 +#define pci_ss_info_1092_0a78 pci_ss_info_1022_2001_1092_0a78 +static const pciSubsystemInfo pci_ss_info_1022_2001_1668_0299 = + {0x1668, 0x0299, pci_subsys_1022_2001_1668_0299, 0}; +#undef pci_ss_info_1668_0299 +#define pci_ss_info_1668_0299 pci_ss_info_1022_2001_1668_0299 +static const pciSubsystemInfo pci_ss_info_1022_7440_1043_8044 = + {0x1043, 0x8044, pci_subsys_1022_7440_1043_8044, 0}; +#undef pci_ss_info_1043_8044 +#define pci_ss_info_1043_8044 pci_ss_info_1022_7440_1043_8044 +static const pciSubsystemInfo pci_ss_info_1022_7443_1043_8044 = + {0x1043, 0x8044, pci_subsys_1022_7443_1043_8044, 0}; +#undef pci_ss_info_1043_8044 +#define pci_ss_info_1043_8044 pci_ss_info_1022_7443_1043_8044 +static const pciSubsystemInfo pci_ss_info_1022_7460_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_7460_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_7460_161f_3017 +static const pciSubsystemInfo pci_ss_info_1022_7464_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_7464_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_7464_161f_3017 +static const pciSubsystemInfo pci_ss_info_1022_7468_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_7468_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_7468_161f_3017 +static const pciSubsystemInfo pci_ss_info_1022_7469_1022_2b80 = + {0x1022, 0x2b80, pci_subsys_1022_7469_1022_2b80, 0}; +#undef pci_ss_info_1022_2b80 +#define pci_ss_info_1022_2b80 pci_ss_info_1022_7469_1022_2b80 +static const pciSubsystemInfo pci_ss_info_1022_7469_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_7469_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_7469_161f_3017 +static const pciSubsystemInfo pci_ss_info_1022_746b_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_746b_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_746b_161f_3017 +static const pciSubsystemInfo pci_ss_info_1022_746d_161f_3017 = + {0x161f, 0x3017, pci_subsys_1022_746d_161f_3017, 0}; +#undef pci_ss_info_161f_3017 +#define pci_ss_info_161f_3017 pci_ss_info_1022_746d_161f_3017 +static const pciSubsystemInfo pci_ss_info_1023_2001_122d_1400 = + {0x122d, 0x1400, pci_subsys_1023_2001_122d_1400, 0}; +#undef pci_ss_info_122d_1400 +#define pci_ss_info_122d_1400 pci_ss_info_1023_2001_122d_1400 +static const pciSubsystemInfo pci_ss_info_1023_8400_1023_8400 = + {0x1023, 0x8400, pci_subsys_1023_8400_1023_8400, 0}; +#undef pci_ss_info_1023_8400 +#define pci_ss_info_1023_8400 pci_ss_info_1023_8400_1023_8400 +static const pciSubsystemInfo pci_ss_info_1023_8420_0e11_b15a = + {0x0e11, 0xb15a, pci_subsys_1023_8420_0e11_b15a, 0}; +#undef pci_ss_info_0e11_b15a +#define pci_ss_info_0e11_b15a pci_ss_info_1023_8420_0e11_b15a +static const pciSubsystemInfo pci_ss_info_1023_8520_0e11_b16e = + {0x0e11, 0xb16e, pci_subsys_1023_8520_0e11_b16e, 0}; +#undef pci_ss_info_0e11_b16e +#define pci_ss_info_0e11_b16e pci_ss_info_1023_8520_0e11_b16e +static const pciSubsystemInfo pci_ss_info_1023_8520_1023_8520 = + {0x1023, 0x8520, pci_subsys_1023_8520_1023_8520, 0}; +#undef pci_ss_info_1023_8520 +#define pci_ss_info_1023_8520 pci_ss_info_1023_8520_1023_8520 +static const pciSubsystemInfo pci_ss_info_1023_8620_1014_0502 = + {0x1014, 0x0502, pci_subsys_1023_8620_1014_0502, 0}; +#undef pci_ss_info_1014_0502 +#define pci_ss_info_1014_0502 pci_ss_info_1023_8620_1014_0502 +static const pciSubsystemInfo pci_ss_info_1023_8620_1014_1025 = + {0x1014, 0x1025, pci_subsys_1023_8620_1014_1025, 0}; +#undef pci_ss_info_1014_1025 +#define pci_ss_info_1014_1025 pci_ss_info_1023_8620_1014_1025 +static const pciSubsystemInfo pci_ss_info_1023_9525_10cf_1094 = + {0x10cf, 0x1094, pci_subsys_1023_9525_10cf_1094, 0}; +#undef pci_ss_info_10cf_1094 +#define pci_ss_info_10cf_1094 pci_ss_info_1023_9525_10cf_1094 +static const pciSubsystemInfo pci_ss_info_1023_9750_1014_9750 = + {0x1014, 0x9750, pci_subsys_1023_9750_1014_9750, 0}; +#undef pci_ss_info_1014_9750 +#define pci_ss_info_1014_9750 pci_ss_info_1023_9750_1014_9750 +static const pciSubsystemInfo pci_ss_info_1023_9750_1023_9750 = + {0x1023, 0x9750, pci_subsys_1023_9750_1023_9750, 0}; +#undef pci_ss_info_1023_9750 +#define pci_ss_info_1023_9750 pci_ss_info_1023_9750_1023_9750 +static const pciSubsystemInfo pci_ss_info_1023_9880_1023_9880 = + {0x1023, 0x9880, pci_subsys_1023_9880_1023_9880, 0}; +#undef pci_ss_info_1023_9880 +#define pci_ss_info_1023_9880 pci_ss_info_1023_9880_1023_9880 +static const pciSubsystemInfo pci_ss_info_1025_1521_10b9_1521 = + {0x10b9, 0x1521, pci_subsys_1025_1521_10b9_1521, 0}; +#undef pci_ss_info_10b9_1521 +#define pci_ss_info_10b9_1521 pci_ss_info_1025_1521_10b9_1521 +static const pciSubsystemInfo pci_ss_info_1025_1523_10b9_1523 = + {0x10b9, 0x1523, pci_subsys_1025_1523_10b9_1523, 0}; +#undef pci_ss_info_10b9_1523 +#define pci_ss_info_10b9_1523 pci_ss_info_1025_1523_10b9_1523 +static const pciSubsystemInfo pci_ss_info_1025_1533_10b9_1533 = + {0x10b9, 0x1533, pci_subsys_1025_1533_10b9_1533, 0}; +#undef pci_ss_info_10b9_1533 +#define pci_ss_info_10b9_1533 pci_ss_info_1025_1533_10b9_1533 +static const pciSubsystemInfo pci_ss_info_1025_1541_10b9_1541 = + {0x10b9, 0x1541, pci_subsys_1025_1541_10b9_1541, 0}; +#undef pci_ss_info_10b9_1541 +#define pci_ss_info_10b9_1541 pci_ss_info_1025_1541_10b9_1541 +static const pciSubsystemInfo pci_ss_info_1025_7101_10b9_7101 = + {0x10b9, 0x7101, pci_subsys_1025_7101_10b9_7101, 0}; +#undef pci_ss_info_10b9_7101 +#define pci_ss_info_10b9_7101 pci_ss_info_1025_7101_10b9_7101 +static const pciSubsystemInfo pci_ss_info_1028_0001_1028_0001 = + {0x1028, 0x0001, pci_subsys_1028_0001_1028_0001, 0}; +#undef pci_ss_info_1028_0001 +#define pci_ss_info_1028_0001 pci_ss_info_1028_0001_1028_0001 +static const pciSubsystemInfo pci_ss_info_1028_0002_1028_0002 = + {0x1028, 0x0002, pci_subsys_1028_0002_1028_0002, 0}; +#undef pci_ss_info_1028_0002 +#define pci_ss_info_1028_0002 pci_ss_info_1028_0002_1028_0002 +static const pciSubsystemInfo pci_ss_info_1028_0003_1028_0003 = + {0x1028, 0x0003, pci_subsys_1028_0003_1028_0003, 0}; +#undef pci_ss_info_1028_0003 +#define pci_ss_info_1028_0003 pci_ss_info_1028_0003_1028_0003 +static const pciSubsystemInfo pci_ss_info_1028_0013_1028_016c = + {0x1028, 0x016c, pci_subsys_1028_0013_1028_016c, 0}; +#undef pci_ss_info_1028_016c +#define pci_ss_info_1028_016c pci_ss_info_1028_0013_1028_016c +static const pciSubsystemInfo pci_ss_info_1028_0013_1028_016d = + {0x1028, 0x016d, pci_subsys_1028_0013_1028_016d, 0}; +#undef pci_ss_info_1028_016d +#define pci_ss_info_1028_016d pci_ss_info_1028_0013_1028_016d +static const pciSubsystemInfo pci_ss_info_1028_0013_1028_016e = + {0x1028, 0x016e, pci_subsys_1028_0013_1028_016e, 0}; +#undef pci_ss_info_1028_016e +#define pci_ss_info_1028_016e pci_ss_info_1028_0013_1028_016e +static const pciSubsystemInfo pci_ss_info_1028_0013_1028_016f = + {0x1028, 0x016f, pci_subsys_1028_0013_1028_016f, 0}; +#undef pci_ss_info_1028_016f +#define pci_ss_info_1028_016f pci_ss_info_1028_0013_1028_016f +static const pciSubsystemInfo pci_ss_info_1028_0013_1028_0170 = + {0x1028, 0x0170, pci_subsys_1028_0013_1028_0170, 0}; +#undef pci_ss_info_1028_0170 +#define pci_ss_info_1028_0170 pci_ss_info_1028_0013_1028_0170 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_102a_001f_9005_000f = + {0x9005, 0x000f, pci_subsys_102a_001f_9005_000f, 0}; +#undef pci_ss_info_9005_000f +#define pci_ss_info_9005_000f pci_ss_info_102a_001f_9005_000f +static const pciSubsystemInfo pci_ss_info_102a_001f_9005_0106 = + {0x9005, 0x0106, pci_subsys_102a_001f_9005_0106, 0}; +#undef pci_ss_info_9005_0106 +#define pci_ss_info_9005_0106 pci_ss_info_102a_001f_9005_0106 +static const pciSubsystemInfo pci_ss_info_102a_001f_9005_a180 = + {0x9005, 0xa180, pci_subsys_102a_001f_9005_a180, 0}; +#undef pci_ss_info_9005_a180 +#define pci_ss_info_9005_a180 pci_ss_info_102a_001f_9005_a180 +#endif +static const pciSubsystemInfo pci_ss_info_102a_00c5_1028_00c5 = + {0x1028, 0x00c5, pci_subsys_102a_00c5_1028_00c5, 0}; +#undef pci_ss_info_1028_00c5 +#define pci_ss_info_1028_00c5 pci_ss_info_102a_00c5_1028_00c5 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_102a_00cf_1028_0106 = + {0x1028, 0x0106, pci_subsys_102a_00cf_1028_0106, 0}; +#undef pci_ss_info_1028_0106 +#define pci_ss_info_1028_0106 pci_ss_info_102a_00cf_1028_0106 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_102a_00cf_1028_0121 = + {0x1028, 0x0121, pci_subsys_102a_00cf_1028_0121, 0}; +#undef pci_ss_info_1028_0121 +#define pci_ss_info_1028_0121 pci_ss_info_102a_00cf_1028_0121 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_102b_051a_102b_0100 = + {0x102b, 0x0100, pci_subsys_102b_051a_102b_0100, 0}; +#undef pci_ss_info_102b_0100 +#define pci_ss_info_102b_0100 pci_ss_info_102b_051a_102b_0100 +static const pciSubsystemInfo pci_ss_info_102b_051a_102b_1100 = + {0x102b, 0x1100, pci_subsys_102b_051a_102b_1100, 0}; +#undef pci_ss_info_102b_1100 +#define pci_ss_info_102b_1100 pci_ss_info_102b_051a_102b_1100 +static const pciSubsystemInfo pci_ss_info_102b_051a_102b_1200 = + {0x102b, 0x1200, pci_subsys_102b_051a_102b_1200, 0}; +#undef pci_ss_info_102b_1200 +#define pci_ss_info_102b_1200 pci_ss_info_102b_051a_102b_1200 +static const pciSubsystemInfo pci_ss_info_102b_051a_1100_102b = + {0x1100, 0x102b, pci_subsys_102b_051a_1100_102b, 0}; +#undef pci_ss_info_1100_102b +#define pci_ss_info_1100_102b pci_ss_info_102b_051a_1100_102b +static const pciSubsystemInfo pci_ss_info_102b_051a_110a_0018 = + {0x110a, 0x0018, pci_subsys_102b_051a_110a_0018, 0}; +#undef pci_ss_info_110a_0018 +#define pci_ss_info_110a_0018 pci_ss_info_102b_051a_110a_0018 +static const pciSubsystemInfo pci_ss_info_102b_051b_102b_051b = + {0x102b, 0x051b, pci_subsys_102b_051b_102b_051b, 0}; +#undef pci_ss_info_102b_051b +#define pci_ss_info_102b_051b pci_ss_info_102b_051b_102b_051b +static const pciSubsystemInfo pci_ss_info_102b_051b_102b_1100 = + {0x102b, 0x1100, pci_subsys_102b_051b_102b_1100, 0}; +#undef pci_ss_info_102b_1100 +#define pci_ss_info_102b_1100 pci_ss_info_102b_051b_102b_1100 +static const pciSubsystemInfo pci_ss_info_102b_051b_102b_1200 = + {0x102b, 0x1200, pci_subsys_102b_051b_102b_1200, 0}; +#undef pci_ss_info_102b_1200 +#define pci_ss_info_102b_1200 pci_ss_info_102b_051b_102b_1200 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_dbc2 = + {0x102b, 0xdbc2, pci_subsys_102b_0520_102b_dbc2, 0}; +#undef pci_ss_info_102b_dbc2 +#define pci_ss_info_102b_dbc2 pci_ss_info_102b_0520_102b_dbc2 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_dbc8 = + {0x102b, 0xdbc8, pci_subsys_102b_0520_102b_dbc8, 0}; +#undef pci_ss_info_102b_dbc8 +#define pci_ss_info_102b_dbc8 pci_ss_info_102b_0520_102b_dbc8 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_dbe2 = + {0x102b, 0xdbe2, pci_subsys_102b_0520_102b_dbe2, 0}; +#undef pci_ss_info_102b_dbe2 +#define pci_ss_info_102b_dbe2 pci_ss_info_102b_0520_102b_dbe2 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_dbe8 = + {0x102b, 0xdbe8, pci_subsys_102b_0520_102b_dbe8, 0}; +#undef pci_ss_info_102b_dbe8 +#define pci_ss_info_102b_dbe8 pci_ss_info_102b_0520_102b_dbe8 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_ff03 = + {0x102b, 0xff03, pci_subsys_102b_0520_102b_ff03, 0}; +#undef pci_ss_info_102b_ff03 +#define pci_ss_info_102b_ff03 pci_ss_info_102b_0520_102b_ff03 +static const pciSubsystemInfo pci_ss_info_102b_0520_102b_ff04 = + {0x102b, 0xff04, pci_subsys_102b_0520_102b_ff04, 0}; +#undef pci_ss_info_102b_ff04 +#define pci_ss_info_102b_ff04 pci_ss_info_102b_0520_102b_ff04 +static const pciSubsystemInfo pci_ss_info_102b_0521_1014_ff03 = + {0x1014, 0xff03, pci_subsys_102b_0521_1014_ff03, 0}; +#undef pci_ss_info_1014_ff03 +#define pci_ss_info_1014_ff03 pci_ss_info_102b_0521_1014_ff03 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_48e9 = + {0x102b, 0x48e9, pci_subsys_102b_0521_102b_48e9, 0}; +#undef pci_ss_info_102b_48e9 +#define pci_ss_info_102b_48e9 pci_ss_info_102b_0521_102b_48e9 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_48f8 = + {0x102b, 0x48f8, pci_subsys_102b_0521_102b_48f8, 0}; +#undef pci_ss_info_102b_48f8 +#define pci_ss_info_102b_48f8 pci_ss_info_102b_0521_102b_48f8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_4a60 = + {0x102b, 0x4a60, pci_subsys_102b_0521_102b_4a60, 0}; +#undef pci_ss_info_102b_4a60 +#define pci_ss_info_102b_4a60 pci_ss_info_102b_0521_102b_4a60 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_4a64 = + {0x102b, 0x4a64, pci_subsys_102b_0521_102b_4a64, 0}; +#undef pci_ss_info_102b_4a64 +#define pci_ss_info_102b_4a64 pci_ss_info_102b_0521_102b_4a64 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_c93c = + {0x102b, 0xc93c, pci_subsys_102b_0521_102b_c93c, 0}; +#undef pci_ss_info_102b_c93c +#define pci_ss_info_102b_c93c pci_ss_info_102b_0521_102b_c93c +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_c9b0 = + {0x102b, 0xc9b0, pci_subsys_102b_0521_102b_c9b0, 0}; +#undef pci_ss_info_102b_c9b0 +#define pci_ss_info_102b_c9b0 pci_ss_info_102b_0521_102b_c9b0 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_c9bc = + {0x102b, 0xc9bc, pci_subsys_102b_0521_102b_c9bc, 0}; +#undef pci_ss_info_102b_c9bc +#define pci_ss_info_102b_c9bc pci_ss_info_102b_0521_102b_c9bc +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ca60 = + {0x102b, 0xca60, pci_subsys_102b_0521_102b_ca60, 0}; +#undef pci_ss_info_102b_ca60 +#define pci_ss_info_102b_ca60 pci_ss_info_102b_0521_102b_ca60 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ca6c = + {0x102b, 0xca6c, pci_subsys_102b_0521_102b_ca6c, 0}; +#undef pci_ss_info_102b_ca6c +#define pci_ss_info_102b_ca6c pci_ss_info_102b_0521_102b_ca6c +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbbc = + {0x102b, 0xdbbc, pci_subsys_102b_0521_102b_dbbc, 0}; +#undef pci_ss_info_102b_dbbc +#define pci_ss_info_102b_dbbc pci_ss_info_102b_0521_102b_dbbc +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbc2 = + {0x102b, 0xdbc2, pci_subsys_102b_0521_102b_dbc2, 0}; +#undef pci_ss_info_102b_dbc2 +#define pci_ss_info_102b_dbc2 pci_ss_info_102b_0521_102b_dbc2 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbc3 = + {0x102b, 0xdbc3, pci_subsys_102b_0521_102b_dbc3, 0}; +#undef pci_ss_info_102b_dbc3 +#define pci_ss_info_102b_dbc3 pci_ss_info_102b_0521_102b_dbc3 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbc8 = + {0x102b, 0xdbc8, pci_subsys_102b_0521_102b_dbc8, 0}; +#undef pci_ss_info_102b_dbc8 +#define pci_ss_info_102b_dbc8 pci_ss_info_102b_0521_102b_dbc8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd2 = + {0x102b, 0xdbd2, pci_subsys_102b_0521_102b_dbd2, 0}; +#undef pci_ss_info_102b_dbd2 +#define pci_ss_info_102b_dbd2 pci_ss_info_102b_0521_102b_dbd2 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd3 = + {0x102b, 0xdbd3, pci_subsys_102b_0521_102b_dbd3, 0}; +#undef pci_ss_info_102b_dbd3 +#define pci_ss_info_102b_dbd3 pci_ss_info_102b_0521_102b_dbd3 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd4 = + {0x102b, 0xdbd4, pci_subsys_102b_0521_102b_dbd4, 0}; +#undef pci_ss_info_102b_dbd4 +#define pci_ss_info_102b_dbd4 pci_ss_info_102b_0521_102b_dbd4 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd5 = + {0x102b, 0xdbd5, pci_subsys_102b_0521_102b_dbd5, 0}; +#undef pci_ss_info_102b_dbd5 +#define pci_ss_info_102b_dbd5 pci_ss_info_102b_0521_102b_dbd5 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd8 = + {0x102b, 0xdbd8, pci_subsys_102b_0521_102b_dbd8, 0}; +#undef pci_ss_info_102b_dbd8 +#define pci_ss_info_102b_dbd8 pci_ss_info_102b_0521_102b_dbd8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbd9 = + {0x102b, 0xdbd9, pci_subsys_102b_0521_102b_dbd9, 0}; +#undef pci_ss_info_102b_dbd9 +#define pci_ss_info_102b_dbd9 pci_ss_info_102b_0521_102b_dbd9 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbe2 = + {0x102b, 0xdbe2, pci_subsys_102b_0521_102b_dbe2, 0}; +#undef pci_ss_info_102b_dbe2 +#define pci_ss_info_102b_dbe2 pci_ss_info_102b_0521_102b_dbe2 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbe3 = + {0x102b, 0xdbe3, pci_subsys_102b_0521_102b_dbe3, 0}; +#undef pci_ss_info_102b_dbe3 +#define pci_ss_info_102b_dbe3 pci_ss_info_102b_0521_102b_dbe3 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbe8 = + {0x102b, 0xdbe8, pci_subsys_102b_0521_102b_dbe8, 0}; +#undef pci_ss_info_102b_dbe8 +#define pci_ss_info_102b_dbe8 pci_ss_info_102b_0521_102b_dbe8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf2 = + {0x102b, 0xdbf2, pci_subsys_102b_0521_102b_dbf2, 0}; +#undef pci_ss_info_102b_dbf2 +#define pci_ss_info_102b_dbf2 pci_ss_info_102b_0521_102b_dbf2 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf3 = + {0x102b, 0xdbf3, pci_subsys_102b_0521_102b_dbf3, 0}; +#undef pci_ss_info_102b_dbf3 +#define pci_ss_info_102b_dbf3 pci_ss_info_102b_0521_102b_dbf3 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf4 = + {0x102b, 0xdbf4, pci_subsys_102b_0521_102b_dbf4, 0}; +#undef pci_ss_info_102b_dbf4 +#define pci_ss_info_102b_dbf4 pci_ss_info_102b_0521_102b_dbf4 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf5 = + {0x102b, 0xdbf5, pci_subsys_102b_0521_102b_dbf5, 0}; +#undef pci_ss_info_102b_dbf5 +#define pci_ss_info_102b_dbf5 pci_ss_info_102b_0521_102b_dbf5 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf8 = + {0x102b, 0xdbf8, pci_subsys_102b_0521_102b_dbf8, 0}; +#undef pci_ss_info_102b_dbf8 +#define pci_ss_info_102b_dbf8 pci_ss_info_102b_0521_102b_dbf8 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_dbf9 = + {0x102b, 0xdbf9, pci_subsys_102b_0521_102b_dbf9, 0}; +#undef pci_ss_info_102b_dbf9 +#define pci_ss_info_102b_dbf9 pci_ss_info_102b_0521_102b_dbf9 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_f806 = + {0x102b, 0xf806, pci_subsys_102b_0521_102b_f806, 0}; +#undef pci_ss_info_102b_f806 +#define pci_ss_info_102b_f806 pci_ss_info_102b_0521_102b_f806 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ff00 = + {0x102b, 0xff00, pci_subsys_102b_0521_102b_ff00, 0}; +#undef pci_ss_info_102b_ff00 +#define pci_ss_info_102b_ff00 pci_ss_info_102b_0521_102b_ff00 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ff02 = + {0x102b, 0xff02, pci_subsys_102b_0521_102b_ff02, 0}; +#undef pci_ss_info_102b_ff02 +#define pci_ss_info_102b_ff02 pci_ss_info_102b_0521_102b_ff02 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ff03 = + {0x102b, 0xff03, pci_subsys_102b_0521_102b_ff03, 0}; +#undef pci_ss_info_102b_ff03 +#define pci_ss_info_102b_ff03 pci_ss_info_102b_0521_102b_ff03 +static const pciSubsystemInfo pci_ss_info_102b_0521_102b_ff04 = + {0x102b, 0xff04, pci_subsys_102b_0521_102b_ff04, 0}; +#undef pci_ss_info_102b_ff04 +#define pci_ss_info_102b_ff04 pci_ss_info_102b_0521_102b_ff04 +static const pciSubsystemInfo pci_ss_info_102b_0521_110a_0032 = + {0x110a, 0x0032, pci_subsys_102b_0521_110a_0032, 0}; +#undef pci_ss_info_110a_0032 +#define pci_ss_info_110a_0032 pci_ss_info_102b_0521_110a_0032 +static const pciSubsystemInfo pci_ss_info_102b_0525_0e11_b16f = + {0x0e11, 0xb16f, pci_subsys_102b_0525_0e11_b16f, 0}; +#undef pci_ss_info_0e11_b16f +#define pci_ss_info_0e11_b16f pci_ss_info_102b_0525_0e11_b16f +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0328 = + {0x102b, 0x0328, pci_subsys_102b_0525_102b_0328, 0}; +#undef pci_ss_info_102b_0328 +#define pci_ss_info_102b_0328 pci_ss_info_102b_0525_102b_0328 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0338 = + {0x102b, 0x0338, pci_subsys_102b_0525_102b_0338, 0}; +#undef pci_ss_info_102b_0338 +#define pci_ss_info_102b_0338 pci_ss_info_102b_0525_102b_0338 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0378 = + {0x102b, 0x0378, pci_subsys_102b_0525_102b_0378, 0}; +#undef pci_ss_info_102b_0378 +#define pci_ss_info_102b_0378 pci_ss_info_102b_0525_102b_0378 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0541 = + {0x102b, 0x0541, pci_subsys_102b_0525_102b_0541, 0}; +#undef pci_ss_info_102b_0541 +#define pci_ss_info_102b_0541 pci_ss_info_102b_0525_102b_0541 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0542 = + {0x102b, 0x0542, pci_subsys_102b_0525_102b_0542, 0}; +#undef pci_ss_info_102b_0542 +#define pci_ss_info_102b_0542 pci_ss_info_102b_0525_102b_0542 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0543 = + {0x102b, 0x0543, pci_subsys_102b_0525_102b_0543, 0}; +#undef pci_ss_info_102b_0543 +#define pci_ss_info_102b_0543 pci_ss_info_102b_0525_102b_0543 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0641 = + {0x102b, 0x0641, pci_subsys_102b_0525_102b_0641, 0}; +#undef pci_ss_info_102b_0641 +#define pci_ss_info_102b_0641 pci_ss_info_102b_0525_102b_0641 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0642 = + {0x102b, 0x0642, pci_subsys_102b_0525_102b_0642, 0}; +#undef pci_ss_info_102b_0642 +#define pci_ss_info_102b_0642 pci_ss_info_102b_0525_102b_0642 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0643 = + {0x102b, 0x0643, pci_subsys_102b_0525_102b_0643, 0}; +#undef pci_ss_info_102b_0643 +#define pci_ss_info_102b_0643 pci_ss_info_102b_0525_102b_0643 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_07c0 = + {0x102b, 0x07c0, pci_subsys_102b_0525_102b_07c0, 0}; +#undef pci_ss_info_102b_07c0 +#define pci_ss_info_102b_07c0 pci_ss_info_102b_0525_102b_07c0 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_07c1 = + {0x102b, 0x07c1, pci_subsys_102b_0525_102b_07c1, 0}; +#undef pci_ss_info_102b_07c1 +#define pci_ss_info_102b_07c1 pci_ss_info_102b_0525_102b_07c1 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0d41 = + {0x102b, 0x0d41, pci_subsys_102b_0525_102b_0d41, 0}; +#undef pci_ss_info_102b_0d41 +#define pci_ss_info_102b_0d41 pci_ss_info_102b_0525_102b_0d41 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0d42 = + {0x102b, 0x0d42, pci_subsys_102b_0525_102b_0d42, 0}; +#undef pci_ss_info_102b_0d42 +#define pci_ss_info_102b_0d42 pci_ss_info_102b_0525_102b_0d42 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0d43 = + {0x102b, 0x0d43, pci_subsys_102b_0525_102b_0d43, 0}; +#undef pci_ss_info_102b_0d43 +#define pci_ss_info_102b_0d43 pci_ss_info_102b_0525_102b_0d43 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0e00 = + {0x102b, 0x0e00, pci_subsys_102b_0525_102b_0e00, 0}; +#undef pci_ss_info_102b_0e00 +#define pci_ss_info_102b_0e00 pci_ss_info_102b_0525_102b_0e00 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0e01 = + {0x102b, 0x0e01, pci_subsys_102b_0525_102b_0e01, 0}; +#undef pci_ss_info_102b_0e01 +#define pci_ss_info_102b_0e01 pci_ss_info_102b_0525_102b_0e01 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0e02 = + {0x102b, 0x0e02, pci_subsys_102b_0525_102b_0e02, 0}; +#undef pci_ss_info_102b_0e02 +#define pci_ss_info_102b_0e02 pci_ss_info_102b_0525_102b_0e02 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0e03 = + {0x102b, 0x0e03, pci_subsys_102b_0525_102b_0e03, 0}; +#undef pci_ss_info_102b_0e03 +#define pci_ss_info_102b_0e03 pci_ss_info_102b_0525_102b_0e03 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0f80 = + {0x102b, 0x0f80, pci_subsys_102b_0525_102b_0f80, 0}; +#undef pci_ss_info_102b_0f80 +#define pci_ss_info_102b_0f80 pci_ss_info_102b_0525_102b_0f80 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0f81 = + {0x102b, 0x0f81, pci_subsys_102b_0525_102b_0f81, 0}; +#undef pci_ss_info_102b_0f81 +#define pci_ss_info_102b_0f81 pci_ss_info_102b_0525_102b_0f81 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0f82 = + {0x102b, 0x0f82, pci_subsys_102b_0525_102b_0f82, 0}; +#undef pci_ss_info_102b_0f82 +#define pci_ss_info_102b_0f82 pci_ss_info_102b_0525_102b_0f82 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_0f83 = + {0x102b, 0x0f83, pci_subsys_102b_0525_102b_0f83, 0}; +#undef pci_ss_info_102b_0f83 +#define pci_ss_info_102b_0f83 pci_ss_info_102b_0525_102b_0f83 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_19d8 = + {0x102b, 0x19d8, pci_subsys_102b_0525_102b_19d8, 0}; +#undef pci_ss_info_102b_19d8 +#define pci_ss_info_102b_19d8 pci_ss_info_102b_0525_102b_19d8 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_19f8 = + {0x102b, 0x19f8, pci_subsys_102b_0525_102b_19f8, 0}; +#undef pci_ss_info_102b_19f8 +#define pci_ss_info_102b_19f8 pci_ss_info_102b_0525_102b_19f8 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_2159 = + {0x102b, 0x2159, pci_subsys_102b_0525_102b_2159, 0}; +#undef pci_ss_info_102b_2159 +#define pci_ss_info_102b_2159 pci_ss_info_102b_0525_102b_2159 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_2179 = + {0x102b, 0x2179, pci_subsys_102b_0525_102b_2179, 0}; +#undef pci_ss_info_102b_2179 +#define pci_ss_info_102b_2179 pci_ss_info_102b_0525_102b_2179 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_217d = + {0x102b, 0x217d, pci_subsys_102b_0525_102b_217d, 0}; +#undef pci_ss_info_102b_217d +#define pci_ss_info_102b_217d pci_ss_info_102b_0525_102b_217d +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_23c0 = + {0x102b, 0x23c0, pci_subsys_102b_0525_102b_23c0, 0}; +#undef pci_ss_info_102b_23c0 +#define pci_ss_info_102b_23c0 pci_ss_info_102b_0525_102b_23c0 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_23c1 = + {0x102b, 0x23c1, pci_subsys_102b_0525_102b_23c1, 0}; +#undef pci_ss_info_102b_23c1 +#define pci_ss_info_102b_23c1 pci_ss_info_102b_0525_102b_23c1 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_23c2 = + {0x102b, 0x23c2, pci_subsys_102b_0525_102b_23c2, 0}; +#undef pci_ss_info_102b_23c2 +#define pci_ss_info_102b_23c2 pci_ss_info_102b_0525_102b_23c2 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_23c3 = + {0x102b, 0x23c3, pci_subsys_102b_0525_102b_23c3, 0}; +#undef pci_ss_info_102b_23c3 +#define pci_ss_info_102b_23c3 pci_ss_info_102b_0525_102b_23c3 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_2f58 = + {0x102b, 0x2f58, pci_subsys_102b_0525_102b_2f58, 0}; +#undef pci_ss_info_102b_2f58 +#define pci_ss_info_102b_2f58 pci_ss_info_102b_0525_102b_2f58 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_2f78 = + {0x102b, 0x2f78, pci_subsys_102b_0525_102b_2f78, 0}; +#undef pci_ss_info_102b_2f78 +#define pci_ss_info_102b_2f78 pci_ss_info_102b_0525_102b_2f78 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_3693 = + {0x102b, 0x3693, pci_subsys_102b_0525_102b_3693, 0}; +#undef pci_ss_info_102b_3693 +#define pci_ss_info_102b_3693 pci_ss_info_102b_0525_102b_3693 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_5dd0 = + {0x102b, 0x5dd0, pci_subsys_102b_0525_102b_5dd0, 0}; +#undef pci_ss_info_102b_5dd0 +#define pci_ss_info_102b_5dd0 pci_ss_info_102b_0525_102b_5dd0 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_5f50 = + {0x102b, 0x5f50, pci_subsys_102b_0525_102b_5f50, 0}; +#undef pci_ss_info_102b_5f50 +#define pci_ss_info_102b_5f50 pci_ss_info_102b_0525_102b_5f50 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_5f51 = + {0x102b, 0x5f51, pci_subsys_102b_0525_102b_5f51, 0}; +#undef pci_ss_info_102b_5f51 +#define pci_ss_info_102b_5f51 pci_ss_info_102b_0525_102b_5f51 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_5f52 = + {0x102b, 0x5f52, pci_subsys_102b_0525_102b_5f52, 0}; +#undef pci_ss_info_102b_5f52 +#define pci_ss_info_102b_5f52 pci_ss_info_102b_0525_102b_5f52 +static const pciSubsystemInfo pci_ss_info_102b_0525_102b_9010 = + {0x102b, 0x9010, pci_subsys_102b_0525_102b_9010, 0}; +#undef pci_ss_info_102b_9010 +#define pci_ss_info_102b_9010 pci_ss_info_102b_0525_102b_9010 +static const pciSubsystemInfo pci_ss_info_102b_0525_1458_0400 = + {0x1458, 0x0400, pci_subsys_102b_0525_1458_0400, 0}; +#undef pci_ss_info_1458_0400 +#define pci_ss_info_1458_0400 pci_ss_info_102b_0525_1458_0400 +static const pciSubsystemInfo pci_ss_info_102b_0525_1705_0001 = + {0x1705, 0x0001, pci_subsys_102b_0525_1705_0001, 0}; +#undef pci_ss_info_1705_0001 +#define pci_ss_info_1705_0001 pci_ss_info_102b_0525_1705_0001 +static const pciSubsystemInfo pci_ss_info_102b_0525_1705_0002 = + {0x1705, 0x0002, pci_subsys_102b_0525_1705_0002, 0}; +#undef pci_ss_info_1705_0002 +#define pci_ss_info_1705_0002 pci_ss_info_102b_0525_1705_0002 +static const pciSubsystemInfo pci_ss_info_102b_0525_1705_0003 = + {0x1705, 0x0003, pci_subsys_102b_0525_1705_0003, 0}; +#undef pci_ss_info_1705_0003 +#define pci_ss_info_1705_0003 pci_ss_info_102b_0525_1705_0003 +static const pciSubsystemInfo pci_ss_info_102b_0525_1705_0004 = + {0x1705, 0x0004, pci_subsys_102b_0525_1705_0004, 0}; +#undef pci_ss_info_1705_0004 +#define pci_ss_info_1705_0004 pci_ss_info_102b_0525_1705_0004 +static const pciSubsystemInfo pci_ss_info_102b_0527_102b_0840 = + {0x102b, 0x0840, pci_subsys_102b_0527_102b_0840, 0}; +#undef pci_ss_info_102b_0840 +#define pci_ss_info_102b_0840 pci_ss_info_102b_0527_102b_0840 +static const pciSubsystemInfo pci_ss_info_102b_0527_102b_0850 = + {0x102b, 0x0850, pci_subsys_102b_0527_102b_0850, 0}; +#undef pci_ss_info_102b_0850 +#define pci_ss_info_102b_0850 pci_ss_info_102b_0527_102b_0850 +static const pciSubsystemInfo pci_ss_info_102b_0528_102b_1020 = + {0x102b, 0x1020, pci_subsys_102b_0528_102b_1020, 0}; +#undef pci_ss_info_102b_1020 +#define pci_ss_info_102b_1020 pci_ss_info_102b_0528_102b_1020 +static const pciSubsystemInfo pci_ss_info_102b_0528_102b_1030 = + {0x102b, 0x1030, pci_subsys_102b_0528_102b_1030, 0}; +#undef pci_ss_info_102b_1030 +#define pci_ss_info_102b_1030 pci_ss_info_102b_0528_102b_1030 +static const pciSubsystemInfo pci_ss_info_102b_0528_102b_14e1 = + {0x102b, 0x14e1, pci_subsys_102b_0528_102b_14e1, 0}; +#undef pci_ss_info_102b_14e1 +#define pci_ss_info_102b_14e1 pci_ss_info_102b_0528_102b_14e1 +static const pciSubsystemInfo pci_ss_info_102b_0528_102b_2021 = + {0x102b, 0x2021, pci_subsys_102b_0528_102b_2021, 0}; +#undef pci_ss_info_102b_2021 +#define pci_ss_info_102b_2021 pci_ss_info_102b_0528_102b_2021 +static const pciSubsystemInfo pci_ss_info_102b_1000_102b_ff01 = + {0x102b, 0xff01, pci_subsys_102b_1000_102b_ff01, 0}; +#undef pci_ss_info_102b_ff01 +#define pci_ss_info_102b_ff01 pci_ss_info_102b_1000_102b_ff01 +static const pciSubsystemInfo pci_ss_info_102b_1000_102b_ff05 = + {0x102b, 0xff05, pci_subsys_102b_1000_102b_ff05, 0}; +#undef pci_ss_info_102b_ff05 +#define pci_ss_info_102b_ff05 pci_ss_info_102b_1000_102b_ff05 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_1001 = + {0x102b, 0x1001, pci_subsys_102b_1001_102b_1001, 0}; +#undef pci_ss_info_102b_1001 +#define pci_ss_info_102b_1001 pci_ss_info_102b_1001_102b_1001 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff00 = + {0x102b, 0xff00, pci_subsys_102b_1001_102b_ff00, 0}; +#undef pci_ss_info_102b_ff00 +#define pci_ss_info_102b_ff00 pci_ss_info_102b_1001_102b_ff00 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff01 = + {0x102b, 0xff01, pci_subsys_102b_1001_102b_ff01, 0}; +#undef pci_ss_info_102b_ff01 +#define pci_ss_info_102b_ff01 pci_ss_info_102b_1001_102b_ff01 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff03 = + {0x102b, 0xff03, pci_subsys_102b_1001_102b_ff03, 0}; +#undef pci_ss_info_102b_ff03 +#define pci_ss_info_102b_ff03 pci_ss_info_102b_1001_102b_ff03 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff04 = + {0x102b, 0xff04, pci_subsys_102b_1001_102b_ff04, 0}; +#undef pci_ss_info_102b_ff04 +#define pci_ss_info_102b_ff04 pci_ss_info_102b_1001_102b_ff04 +static const pciSubsystemInfo pci_ss_info_102b_1001_102b_ff05 = + {0x102b, 0xff05, pci_subsys_102b_1001_102b_ff05, 0}; +#undef pci_ss_info_102b_ff05 +#define pci_ss_info_102b_ff05 pci_ss_info_102b_1001_102b_ff05 +static const pciSubsystemInfo pci_ss_info_102b_1001_110a_001e = + {0x110a, 0x001e, pci_subsys_102b_1001_110a_001e, 0}; +#undef pci_ss_info_110a_001e +#define pci_ss_info_110a_001e pci_ss_info_102b_1001_110a_001e +static const pciSubsystemInfo pci_ss_info_102b_2527_102b_0f83 = + {0x102b, 0x0f83, pci_subsys_102b_2527_102b_0f83, 0}; +#undef pci_ss_info_102b_0f83 +#define pci_ss_info_102b_0f83 pci_ss_info_102b_2527_102b_0f83 +static const pciSubsystemInfo pci_ss_info_102b_2527_102b_0f84 = + {0x102b, 0x0f84, pci_subsys_102b_2527_102b_0f84, 0}; +#undef pci_ss_info_102b_0f84 +#define pci_ss_info_102b_0f84 pci_ss_info_102b_2527_102b_0f84 +static const pciSubsystemInfo pci_ss_info_102b_2527_102b_1e41 = + {0x102b, 0x1e41, pci_subsys_102b_2527_102b_1e41, 0}; +#undef pci_ss_info_102b_1e41 +#define pci_ss_info_102b_1e41 pci_ss_info_102b_2527_102b_1e41 +static const pciSubsystemInfo pci_ss_info_102b_2537_102b_1820 = + {0x102b, 0x1820, pci_subsys_102b_2537_102b_1820, 0}; +#undef pci_ss_info_102b_1820 +#define pci_ss_info_102b_1820 pci_ss_info_102b_2537_102b_1820 +static const pciSubsystemInfo pci_ss_info_102b_2537_102b_1830 = + {0x102b, 0x1830, pci_subsys_102b_2537_102b_1830, 0}; +#undef pci_ss_info_102b_1830 +#define pci_ss_info_102b_1830 pci_ss_info_102b_2537_102b_1830 +static const pciSubsystemInfo pci_ss_info_102b_2537_102b_1c10 = + {0x102b, 0x1c10, pci_subsys_102b_2537_102b_1c10, 0}; +#undef pci_ss_info_102b_1c10 +#define pci_ss_info_102b_1c10 pci_ss_info_102b_2537_102b_1c10 +static const pciSubsystemInfo pci_ss_info_102b_2537_102b_2811 = + {0x102b, 0x2811, pci_subsys_102b_2537_102b_2811, 0}; +#undef pci_ss_info_102b_2811 +#define pci_ss_info_102b_2811 pci_ss_info_102b_2537_102b_2811 +static const pciSubsystemInfo pci_ss_info_102b_2537_102b_2c11 = + {0x102b, 0x2c11, pci_subsys_102b_2537_102b_2c11, 0}; +#undef pci_ss_info_102b_2c11 +#define pci_ss_info_102b_2c11 pci_ss_info_102b_2537_102b_2c11 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_08c7 = + {0x102b, 0x08c7, pci_subsys_102b_2538_102b_08c7, 0}; +#undef pci_ss_info_102b_08c7 +#define pci_ss_info_102b_08c7 pci_ss_info_102b_2538_102b_08c7 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_0907 = + {0x102b, 0x0907, pci_subsys_102b_2538_102b_0907, 0}; +#undef pci_ss_info_102b_0907 +#define pci_ss_info_102b_0907 pci_ss_info_102b_2538_102b_0907 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_1047 = + {0x102b, 0x1047, pci_subsys_102b_2538_102b_1047, 0}; +#undef pci_ss_info_102b_1047 +#define pci_ss_info_102b_1047 pci_ss_info_102b_2538_102b_1047 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_1087 = + {0x102b, 0x1087, pci_subsys_102b_2538_102b_1087, 0}; +#undef pci_ss_info_102b_1087 +#define pci_ss_info_102b_1087 pci_ss_info_102b_2538_102b_1087 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_2538 = + {0x102b, 0x2538, pci_subsys_102b_2538_102b_2538, 0}; +#undef pci_ss_info_102b_2538 +#define pci_ss_info_102b_2538 pci_ss_info_102b_2538_102b_2538 +static const pciSubsystemInfo pci_ss_info_102b_2538_102b_3007 = + {0x102b, 0x3007, pci_subsys_102b_2538_102b_3007, 0}; +#undef pci_ss_info_102b_3007 +#define pci_ss_info_102b_3007 pci_ss_info_102b_2538_102b_3007 +static const pciSubsystemInfo pci_ss_info_102c_00c0_102c_00c0 = + {0x102c, 0x00c0, pci_subsys_102c_00c0_102c_00c0, 0}; +#undef pci_ss_info_102c_00c0 +#define pci_ss_info_102c_00c0 pci_ss_info_102c_00c0_102c_00c0 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_102c_00c0_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_102c_00c0_4c53_1000 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1010 = + {0x4c53, 0x1010, pci_subsys_102c_00c0_4c53_1010, 0}; +#undef pci_ss_info_4c53_1010 +#define pci_ss_info_4c53_1010 pci_ss_info_102c_00c0_4c53_1010 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1020 = + {0x4c53, 0x1020, pci_subsys_102c_00c0_4c53_1020, 0}; +#undef pci_ss_info_4c53_1020 +#define pci_ss_info_4c53_1020 pci_ss_info_102c_00c0_4c53_1020 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1030 = + {0x4c53, 0x1030, pci_subsys_102c_00c0_4c53_1030, 0}; +#undef pci_ss_info_4c53_1030 +#define pci_ss_info_4c53_1030 pci_ss_info_102c_00c0_4c53_1030 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_102c_00c0_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_102c_00c0_4c53_1050 +static const pciSubsystemInfo pci_ss_info_102c_00c0_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_102c_00c0_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_102c_00c0_4c53_1051 +static const pciSubsystemInfo pci_ss_info_102c_00e5_0e11_b049 = + {0x0e11, 0xb049, pci_subsys_102c_00e5_0e11_b049, 0}; +#undef pci_ss_info_0e11_b049 +#define pci_ss_info_0e11_b049 pci_ss_info_102c_00e5_0e11_b049 +static const pciSubsystemInfo pci_ss_info_102c_00e5_1179_0001 = + {0x1179, 0x0001, pci_subsys_102c_00e5_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_102c_00e5_1179_0001 +static const pciSubsystemInfo pci_ss_info_102c_0c30_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_102c_0c30_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_102c_0c30_4c53_1000 +static const pciSubsystemInfo pci_ss_info_102c_0c30_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_102c_0c30_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_102c_0c30_4c53_1050 +static const pciSubsystemInfo pci_ss_info_102c_0c30_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_102c_0c30_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_102c_0c30_4c53_1051 +static const pciSubsystemInfo pci_ss_info_102c_0c30_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_102c_0c30_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_102c_0c30_4c53_1080 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_102f_0020_102f_00f8 = + {0x102f, 0x00f8, pci_subsys_102f_0020_102f_00f8, 0}; +#undef pci_ss_info_102f_00f8 +#define pci_ss_info_102f_00f8 pci_ss_info_102f_0020_102f_00f8 +#endif +static const pciSubsystemInfo pci_ss_info_1033_0035_1033_0035 = + {0x1033, 0x0035, pci_subsys_1033_0035_1033_0035, 0}; +#undef pci_ss_info_1033_0035 +#define pci_ss_info_1033_0035 pci_ss_info_1033_0035_1033_0035 +static const pciSubsystemInfo pci_ss_info_1033_0035_1179_0001 = + {0x1179, 0x0001, pci_subsys_1033_0035_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1033_0035_1179_0001 +static const pciSubsystemInfo pci_ss_info_1033_0035_12ee_7000 = + {0x12ee, 0x7000, pci_subsys_1033_0035_12ee_7000, 0}; +#undef pci_ss_info_12ee_7000 +#define pci_ss_info_12ee_7000 pci_ss_info_1033_0035_12ee_7000 +static const pciSubsystemInfo pci_ss_info_1033_0035_14c2_0105 = + {0x14c2, 0x0105, pci_subsys_1033_0035_14c2_0105, 0}; +#undef pci_ss_info_14c2_0105 +#define pci_ss_info_14c2_0105 pci_ss_info_1033_0035_14c2_0105 +static const pciSubsystemInfo pci_ss_info_1033_0035_1799_0001 = + {0x1799, 0x0001, pci_subsys_1033_0035_1799_0001, 0}; +#undef pci_ss_info_1799_0001 +#define pci_ss_info_1799_0001 pci_ss_info_1033_0035_1799_0001 +static const pciSubsystemInfo pci_ss_info_1033_0035_1931_000a = + {0x1931, 0x000a, pci_subsys_1033_0035_1931_000a, 0}; +#undef pci_ss_info_1931_000a +#define pci_ss_info_1931_000a pci_ss_info_1033_0035_1931_000a +static const pciSubsystemInfo pci_ss_info_1033_0035_1931_000b = + {0x1931, 0x000b, pci_subsys_1033_0035_1931_000b, 0}; +#undef pci_ss_info_1931_000b +#define pci_ss_info_1931_000b pci_ss_info_1033_0035_1931_000b +static const pciSubsystemInfo pci_ss_info_1033_0035_807d_0035 = + {0x807d, 0x0035, pci_subsys_1033_0035_807d_0035, 0}; +#undef pci_ss_info_807d_0035 +#define pci_ss_info_807d_0035 pci_ss_info_1033_0035_807d_0035 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0020 = + {0x1010, 0x0020, pci_subsys_1033_0067_1010_0020, 0}; +#undef pci_ss_info_1010_0020 +#define pci_ss_info_1010_0020 pci_ss_info_1033_0067_1010_0020 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0080 = + {0x1010, 0x0080, pci_subsys_1033_0067_1010_0080, 0}; +#undef pci_ss_info_1010_0080 +#define pci_ss_info_1010_0080 pci_ss_info_1033_0067_1010_0080 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0088 = + {0x1010, 0x0088, pci_subsys_1033_0067_1010_0088, 0}; +#undef pci_ss_info_1010_0088 +#define pci_ss_info_1010_0088 pci_ss_info_1033_0067_1010_0088 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0090 = + {0x1010, 0x0090, pci_subsys_1033_0067_1010_0090, 0}; +#undef pci_ss_info_1010_0090 +#define pci_ss_info_1010_0090 pci_ss_info_1033_0067_1010_0090 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0098 = + {0x1010, 0x0098, pci_subsys_1033_0067_1010_0098, 0}; +#undef pci_ss_info_1010_0098 +#define pci_ss_info_1010_0098 pci_ss_info_1033_0067_1010_0098 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_00a0 = + {0x1010, 0x00a0, pci_subsys_1033_0067_1010_00a0, 0}; +#undef pci_ss_info_1010_00a0 +#define pci_ss_info_1010_00a0 pci_ss_info_1033_0067_1010_00a0 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_00a8 = + {0x1010, 0x00a8, pci_subsys_1033_0067_1010_00a8, 0}; +#undef pci_ss_info_1010_00a8 +#define pci_ss_info_1010_00a8 pci_ss_info_1033_0067_1010_00a8 +static const pciSubsystemInfo pci_ss_info_1033_0067_1010_0120 = + {0x1010, 0x0120, pci_subsys_1033_0067_1010_0120, 0}; +#undef pci_ss_info_1010_0120 +#define pci_ss_info_1010_0120 pci_ss_info_1033_0067_1010_0120 +static const pciSubsystemInfo pci_ss_info_1033_0074_1033_8014 = + {0x1033, 0x8014, pci_subsys_1033_0074_1033_8014, 0}; +#undef pci_ss_info_1033_8014 +#define pci_ss_info_1033_8014 pci_ss_info_1033_0074_1033_8014 +static const pciSubsystemInfo pci_ss_info_1033_00cd_12ee_8011 = + {0x12ee, 0x8011, pci_subsys_1033_00cd_12ee_8011, 0}; +#undef pci_ss_info_12ee_8011 +#define pci_ss_info_12ee_8011 pci_ss_info_1033_00cd_12ee_8011 +static const pciSubsystemInfo pci_ss_info_1033_00e0_12ee_7001 = + {0x12ee, 0x7001, pci_subsys_1033_00e0_12ee_7001, 0}; +#undef pci_ss_info_12ee_7001 +#define pci_ss_info_12ee_7001 pci_ss_info_1033_00e0_12ee_7001 +static const pciSubsystemInfo pci_ss_info_1033_00e0_14c2_0205 = + {0x14c2, 0x0205, pci_subsys_1033_00e0_14c2_0205, 0}; +#undef pci_ss_info_14c2_0205 +#define pci_ss_info_14c2_0205 pci_ss_info_1033_00e0_14c2_0205 +static const pciSubsystemInfo pci_ss_info_1033_00e0_1799_0002 = + {0x1799, 0x0002, pci_subsys_1033_00e0_1799_0002, 0}; +#undef pci_ss_info_1799_0002 +#define pci_ss_info_1799_0002 pci_ss_info_1033_00e0_1799_0002 +static const pciSubsystemInfo pci_ss_info_1033_00e0_807d_1043 = + {0x807d, 0x1043, pci_subsys_1033_00e0_807d_1043, 0}; +#undef pci_ss_info_807d_1043 +#define pci_ss_info_807d_1043 pci_ss_info_1033_00e0_807d_1043 +static const pciSubsystemInfo pci_ss_info_1039_0200_1039_0000 = + {0x1039, 0x0000, pci_subsys_1039_0200_1039_0000, 0}; +#undef pci_ss_info_1039_0000 +#define pci_ss_info_1039_0000 pci_ss_info_1039_0200_1039_0000 +static const pciSubsystemInfo pci_ss_info_1039_0300_107d_2720 = + {0x107d, 0x2720, pci_subsys_1039_0300_107d_2720, 0}; +#undef pci_ss_info_107d_2720 +#define pci_ss_info_107d_2720 pci_ss_info_1039_0300_107d_2720 +static const pciSubsystemInfo pci_ss_info_1039_0900_1019_0a14 = + {0x1019, 0x0a14, pci_subsys_1039_0900_1019_0a14, 0}; +#undef pci_ss_info_1019_0a14 +#define pci_ss_info_1019_0a14 pci_ss_info_1039_0900_1019_0a14 +static const pciSubsystemInfo pci_ss_info_1039_0900_1039_0900 = + {0x1039, 0x0900, pci_subsys_1039_0900_1039_0900, 0}; +#undef pci_ss_info_1039_0900 +#define pci_ss_info_1039_0900 pci_ss_info_1039_0900_1039_0900 +static const pciSubsystemInfo pci_ss_info_1039_0900_1043_8035 = + {0x1043, 0x8035, pci_subsys_1039_0900_1043_8035, 0}; +#undef pci_ss_info_1043_8035 +#define pci_ss_info_1043_8035 pci_ss_info_1039_0900_1043_8035 +static const pciSubsystemInfo pci_ss_info_1039_5513_1019_0970 = + {0x1019, 0x0970, pci_subsys_1039_5513_1019_0970, 0}; +#undef pci_ss_info_1019_0970 +#define pci_ss_info_1019_0970 pci_ss_info_1039_5513_1019_0970 +static const pciSubsystemInfo pci_ss_info_1039_5513_1039_5513 = + {0x1039, 0x5513, pci_subsys_1039_5513_1039_5513, 0}; +#undef pci_ss_info_1039_5513 +#define pci_ss_info_1039_5513 pci_ss_info_1039_5513_1039_5513 +static const pciSubsystemInfo pci_ss_info_1039_5513_1043_8035 = + {0x1043, 0x8035, pci_subsys_1039_5513_1043_8035, 0}; +#undef pci_ss_info_1043_8035 +#define pci_ss_info_1043_8035 pci_ss_info_1039_5513_1043_8035 +static const pciSubsystemInfo pci_ss_info_1039_6300_1019_0970 = + {0x1019, 0x0970, pci_subsys_1039_6300_1019_0970, 0}; +#undef pci_ss_info_1019_0970 +#define pci_ss_info_1019_0970 pci_ss_info_1039_6300_1019_0970 +static const pciSubsystemInfo pci_ss_info_1039_6300_1043_8035 = + {0x1043, 0x8035, pci_subsys_1039_6300_1043_8035, 0}; +#undef pci_ss_info_1043_8035 +#define pci_ss_info_1043_8035 pci_ss_info_1039_6300_1043_8035 +static const pciSubsystemInfo pci_ss_info_1039_6306_1039_6306 = + {0x1039, 0x6306, pci_subsys_1039_6306_1039_6306, 0}; +#undef pci_ss_info_1039_6306 +#define pci_ss_info_1039_6306 pci_ss_info_1039_6306_1039_6306 +static const pciSubsystemInfo pci_ss_info_1039_6326_1039_6326 = + {0x1039, 0x6326, pci_subsys_1039_6326_1039_6326, 0}; +#undef pci_ss_info_1039_6326 +#define pci_ss_info_1039_6326 pci_ss_info_1039_6326_1039_6326 +static const pciSubsystemInfo pci_ss_info_1039_6326_1092_0a50 = + {0x1092, 0x0a50, pci_subsys_1039_6326_1092_0a50, 0}; +#undef pci_ss_info_1092_0a50 +#define pci_ss_info_1092_0a50 pci_ss_info_1039_6326_1092_0a50 +static const pciSubsystemInfo pci_ss_info_1039_6326_1092_0a70 = + {0x1092, 0x0a70, pci_subsys_1039_6326_1092_0a70, 0}; +#undef pci_ss_info_1092_0a70 +#define pci_ss_info_1092_0a70 pci_ss_info_1039_6326_1092_0a70 +static const pciSubsystemInfo pci_ss_info_1039_6326_1092_4910 = + {0x1092, 0x4910, pci_subsys_1039_6326_1092_4910, 0}; +#undef pci_ss_info_1092_4910 +#define pci_ss_info_1092_4910 pci_ss_info_1039_6326_1092_4910 +static const pciSubsystemInfo pci_ss_info_1039_6326_1092_4920 = + {0x1092, 0x4920, pci_subsys_1039_6326_1092_4920, 0}; +#undef pci_ss_info_1092_4920 +#define pci_ss_info_1092_4920 pci_ss_info_1039_6326_1092_4920 +static const pciSubsystemInfo pci_ss_info_1039_6326_1569_6326 = + {0x1569, 0x6326, pci_subsys_1039_6326_1569_6326, 0}; +#undef pci_ss_info_1569_6326 +#define pci_ss_info_1569_6326 pci_ss_info_1039_6326_1569_6326 +static const pciSubsystemInfo pci_ss_info_1039_6330_1039_6330 = + {0x1039, 0x6330, pci_subsys_1039_6330_1039_6330, 0}; +#undef pci_ss_info_1039_6330 +#define pci_ss_info_1039_6330 pci_ss_info_1039_6330_1039_6330 +static const pciSubsystemInfo pci_ss_info_1039_7001_1019_0a14 = + {0x1019, 0x0a14, pci_subsys_1039_7001_1019_0a14, 0}; +#undef pci_ss_info_1019_0a14 +#define pci_ss_info_1019_0a14 pci_ss_info_1039_7001_1019_0a14 +static const pciSubsystemInfo pci_ss_info_1039_7001_1039_7000 = + {0x1039, 0x7000, pci_subsys_1039_7001_1039_7000, 0}; +#undef pci_ss_info_1039_7000 +#define pci_ss_info_1039_7000 pci_ss_info_1039_7001_1039_7000 +static const pciSubsystemInfo pci_ss_info_1039_7001_1462_5470 = + {0x1462, 0x5470, pci_subsys_1039_7001_1462_5470, 0}; +#undef pci_ss_info_1462_5470 +#define pci_ss_info_1462_5470 pci_ss_info_1039_7001_1462_5470 +static const pciSubsystemInfo pci_ss_info_1039_7002_1509_7002 = + {0x1509, 0x7002, pci_subsys_1039_7002_1509_7002, 0}; +#undef pci_ss_info_1509_7002 +#define pci_ss_info_1509_7002 pci_ss_info_1039_7002_1509_7002 +static const pciSubsystemInfo pci_ss_info_1039_7012_15bd_1001 = + {0x15bd, 0x1001, pci_subsys_1039_7012_15bd_1001, 0}; +#undef pci_ss_info_15bd_1001 +#define pci_ss_info_15bd_1001 pci_ss_info_1039_7012_15bd_1001 +static const pciSubsystemInfo pci_ss_info_1039_7016_1039_7016 = + {0x1039, 0x7016, pci_subsys_1039_7016_1039_7016, 0}; +#undef pci_ss_info_1039_7016 +#define pci_ss_info_1039_7016 pci_ss_info_1039_7016_1039_7016 +static const pciSubsystemInfo pci_ss_info_1039_7018_1014_01b6 = + {0x1014, 0x01b6, pci_subsys_1039_7018_1014_01b6, 0}; +#undef pci_ss_info_1014_01b6 +#define pci_ss_info_1014_01b6 pci_ss_info_1039_7018_1014_01b6 +static const pciSubsystemInfo pci_ss_info_1039_7018_1014_01b7 = + {0x1014, 0x01b7, pci_subsys_1039_7018_1014_01b7, 0}; +#undef pci_ss_info_1014_01b7 +#define pci_ss_info_1014_01b7 pci_ss_info_1039_7018_1014_01b7 +static const pciSubsystemInfo pci_ss_info_1039_7018_1019_7018 = + {0x1019, 0x7018, pci_subsys_1039_7018_1019_7018, 0}; +#undef pci_ss_info_1019_7018 +#define pci_ss_info_1019_7018 pci_ss_info_1039_7018_1019_7018 +static const pciSubsystemInfo pci_ss_info_1039_7018_1025_000e = + {0x1025, 0x000e, pci_subsys_1039_7018_1025_000e, 0}; +#undef pci_ss_info_1025_000e +#define pci_ss_info_1025_000e pci_ss_info_1039_7018_1025_000e +static const pciSubsystemInfo pci_ss_info_1039_7018_1025_0018 = + {0x1025, 0x0018, pci_subsys_1039_7018_1025_0018, 0}; +#undef pci_ss_info_1025_0018 +#define pci_ss_info_1025_0018 pci_ss_info_1039_7018_1025_0018 +static const pciSubsystemInfo pci_ss_info_1039_7018_1039_7018 = + {0x1039, 0x7018, pci_subsys_1039_7018_1039_7018, 0}; +#undef pci_ss_info_1039_7018 +#define pci_ss_info_1039_7018 pci_ss_info_1039_7018_1039_7018 +static const pciSubsystemInfo pci_ss_info_1039_7018_1043_800b = + {0x1043, 0x800b, pci_subsys_1039_7018_1043_800b, 0}; +#undef pci_ss_info_1043_800b +#define pci_ss_info_1043_800b pci_ss_info_1039_7018_1043_800b +static const pciSubsystemInfo pci_ss_info_1039_7018_1054_7018 = + {0x1054, 0x7018, pci_subsys_1039_7018_1054_7018, 0}; +#undef pci_ss_info_1054_7018 +#define pci_ss_info_1054_7018 pci_ss_info_1039_7018_1054_7018 +static const pciSubsystemInfo pci_ss_info_1039_7018_107d_5330 = + {0x107d, 0x5330, pci_subsys_1039_7018_107d_5330, 0}; +#undef pci_ss_info_107d_5330 +#define pci_ss_info_107d_5330 pci_ss_info_1039_7018_107d_5330 +static const pciSubsystemInfo pci_ss_info_1039_7018_107d_5350 = + {0x107d, 0x5350, pci_subsys_1039_7018_107d_5350, 0}; +#undef pci_ss_info_107d_5350 +#define pci_ss_info_107d_5350 pci_ss_info_1039_7018_107d_5350 +static const pciSubsystemInfo pci_ss_info_1039_7018_1170_3209 = + {0x1170, 0x3209, pci_subsys_1039_7018_1170_3209, 0}; +#undef pci_ss_info_1170_3209 +#define pci_ss_info_1170_3209 pci_ss_info_1039_7018_1170_3209 +static const pciSubsystemInfo pci_ss_info_1039_7018_1462_400a = + {0x1462, 0x400a, pci_subsys_1039_7018_1462_400a, 0}; +#undef pci_ss_info_1462_400a +#define pci_ss_info_1462_400a pci_ss_info_1039_7018_1462_400a +static const pciSubsystemInfo pci_ss_info_1039_7018_14a4_2089 = + {0x14a4, 0x2089, pci_subsys_1039_7018_14a4_2089, 0}; +#undef pci_ss_info_14a4_2089 +#define pci_ss_info_14a4_2089 pci_ss_info_1039_7018_14a4_2089 +static const pciSubsystemInfo pci_ss_info_1039_7018_14cd_2194 = + {0x14cd, 0x2194, pci_subsys_1039_7018_14cd_2194, 0}; +#undef pci_ss_info_14cd_2194 +#define pci_ss_info_14cd_2194 pci_ss_info_1039_7018_14cd_2194 +static const pciSubsystemInfo pci_ss_info_1039_7018_14ff_1100 = + {0x14ff, 0x1100, pci_subsys_1039_7018_14ff_1100, 0}; +#undef pci_ss_info_14ff_1100 +#define pci_ss_info_14ff_1100 pci_ss_info_1039_7018_14ff_1100 +static const pciSubsystemInfo pci_ss_info_1039_7018_152d_8808 = + {0x152d, 0x8808, pci_subsys_1039_7018_152d_8808, 0}; +#undef pci_ss_info_152d_8808 +#define pci_ss_info_152d_8808 pci_ss_info_1039_7018_152d_8808 +static const pciSubsystemInfo pci_ss_info_1039_7018_1558_1103 = + {0x1558, 0x1103, pci_subsys_1039_7018_1558_1103, 0}; +#undef pci_ss_info_1558_1103 +#define pci_ss_info_1558_1103 pci_ss_info_1039_7018_1558_1103 +static const pciSubsystemInfo pci_ss_info_1039_7018_1558_2200 = + {0x1558, 0x2200, pci_subsys_1039_7018_1558_2200, 0}; +#undef pci_ss_info_1558_2200 +#define pci_ss_info_1558_2200 pci_ss_info_1039_7018_1558_2200 +static const pciSubsystemInfo pci_ss_info_1039_7018_1563_7018 = + {0x1563, 0x7018, pci_subsys_1039_7018_1563_7018, 0}; +#undef pci_ss_info_1563_7018 +#define pci_ss_info_1563_7018 pci_ss_info_1039_7018_1563_7018 +static const pciSubsystemInfo pci_ss_info_1039_7018_15c5_0111 = + {0x15c5, 0x0111, pci_subsys_1039_7018_15c5_0111, 0}; +#undef pci_ss_info_15c5_0111 +#define pci_ss_info_15c5_0111 pci_ss_info_1039_7018_15c5_0111 +static const pciSubsystemInfo pci_ss_info_1039_7018_270f_a171 = + {0x270f, 0xa171, pci_subsys_1039_7018_270f_a171, 0}; +#undef pci_ss_info_270f_a171 +#define pci_ss_info_270f_a171 pci_ss_info_1039_7018_270f_a171 +static const pciSubsystemInfo pci_ss_info_1039_7018_a0a0_0022 = + {0xa0a0, 0x0022, pci_subsys_1039_7018_a0a0_0022, 0}; +#undef pci_ss_info_a0a0_0022 +#define pci_ss_info_a0a0_0022 pci_ss_info_1039_7018_a0a0_0022 +static const pciSubsystemInfo pci_ss_info_103c_1029_107e_000f = + {0x107e, 0x000f, pci_subsys_103c_1029_107e_000f, 0}; +#undef pci_ss_info_107e_000f +#define pci_ss_info_107e_000f pci_ss_info_103c_1029_107e_000f +static const pciSubsystemInfo pci_ss_info_103c_1029_9004_9210 = + {0x9004, 0x9210, pci_subsys_103c_1029_9004_9210, 0}; +#undef pci_ss_info_9004_9210 +#define pci_ss_info_9004_9210 pci_ss_info_103c_1029_9004_9210 +static const pciSubsystemInfo pci_ss_info_103c_1029_9004_9211 = + {0x9004, 0x9211, pci_subsys_103c_1029_9004_9211, 0}; +#undef pci_ss_info_9004_9211 +#define pci_ss_info_9004_9211 pci_ss_info_103c_1029_9004_9211 +static const pciSubsystemInfo pci_ss_info_103c_102a_107e_000e = + {0x107e, 0x000e, pci_subsys_103c_102a_107e_000e, 0}; +#undef pci_ss_info_107e_000e +#define pci_ss_info_107e_000e pci_ss_info_103c_102a_107e_000e +static const pciSubsystemInfo pci_ss_info_103c_102a_9004_9110 = + {0x9004, 0x9110, pci_subsys_103c_102a_9004_9110, 0}; +#undef pci_ss_info_9004_9110 +#define pci_ss_info_9004_9110 pci_ss_info_103c_102a_9004_9110 +static const pciSubsystemInfo pci_ss_info_103c_102a_9004_9111 = + {0x9004, 0x9111, pci_subsys_103c_102a_9004_9111, 0}; +#undef pci_ss_info_9004_9111 +#define pci_ss_info_9004_9111 pci_ss_info_103c_102a_9004_9111 +static const pciSubsystemInfo pci_ss_info_103c_1031_103c_1040 = + {0x103c, 0x1040, pci_subsys_103c_1031_103c_1040, 0}; +#undef pci_ss_info_103c_1040 +#define pci_ss_info_103c_1040 pci_ss_info_103c_1031_103c_1040 +static const pciSubsystemInfo pci_ss_info_103c_1031_103c_1041 = + {0x103c, 0x1041, pci_subsys_103c_1031_103c_1041, 0}; +#undef pci_ss_info_103c_1041 +#define pci_ss_info_103c_1041 pci_ss_info_103c_1031_103c_1041 +static const pciSubsystemInfo pci_ss_info_103c_1031_103c_1042 = + {0x103c, 0x1042, pci_subsys_103c_1031_103c_1042, 0}; +#undef pci_ss_info_103c_1042 +#define pci_ss_info_103c_1042 pci_ss_info_103c_1031_103c_1042 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1049 = + {0x103c, 0x1049, pci_subsys_103c_1048_103c_1049, 0}; +#undef pci_ss_info_103c_1049 +#define pci_ss_info_103c_1049 pci_ss_info_103c_1048_103c_1049 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_104a = + {0x103c, 0x104a, pci_subsys_103c_1048_103c_104a, 0}; +#undef pci_ss_info_103c_104a +#define pci_ss_info_103c_104a pci_ss_info_103c_1048_103c_104a +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_104b = + {0x103c, 0x104b, pci_subsys_103c_1048_103c_104b, 0}; +#undef pci_ss_info_103c_104b +#define pci_ss_info_103c_104b pci_ss_info_103c_1048_103c_104b +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1223 = + {0x103c, 0x1223, pci_subsys_103c_1048_103c_1223, 0}; +#undef pci_ss_info_103c_1223 +#define pci_ss_info_103c_1223 pci_ss_info_103c_1048_103c_1223 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1226 = + {0x103c, 0x1226, pci_subsys_103c_1048_103c_1226, 0}; +#undef pci_ss_info_103c_1226 +#define pci_ss_info_103c_1226 pci_ss_info_103c_1048_103c_1226 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1227 = + {0x103c, 0x1227, pci_subsys_103c_1048_103c_1227, 0}; +#undef pci_ss_info_103c_1227 +#define pci_ss_info_103c_1227 pci_ss_info_103c_1048_103c_1227 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1282 = + {0x103c, 0x1282, pci_subsys_103c_1048_103c_1282, 0}; +#undef pci_ss_info_103c_1282 +#define pci_ss_info_103c_1282 pci_ss_info_103c_1048_103c_1282 +static const pciSubsystemInfo pci_ss_info_103c_1048_103c_1301 = + {0x103c, 0x1301, pci_subsys_103c_1048_103c_1301, 0}; +#undef pci_ss_info_103c_1301 +#define pci_ss_info_103c_1301 pci_ss_info_103c_1048_103c_1301 +static const pciSubsystemInfo pci_ss_info_103c_3220_103c_3225 = + {0x103c, 0x3225, pci_subsys_103c_3220_103c_3225, 0}; +#undef pci_ss_info_103c_3225 +#define pci_ss_info_103c_3225 pci_ss_info_103c_3220_103c_3225 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1043_0675_0675_1704 = + {0x0675, 0x1704, pci_subsys_1043_0675_0675_1704, 0}; +#undef pci_ss_info_0675_1704 +#define pci_ss_info_0675_1704 pci_ss_info_1043_0675_0675_1704 +static const pciSubsystemInfo pci_ss_info_1043_0675_0675_1707 = + {0x0675, 0x1707, pci_subsys_1043_0675_0675_1707, 0}; +#undef pci_ss_info_0675_1707 +#define pci_ss_info_0675_1707 pci_ss_info_1043_0675_0675_1707 +static const pciSubsystemInfo pci_ss_info_1043_0675_10cf_105e = + {0x10cf, 0x105e, pci_subsys_1043_0675_10cf_105e, 0}; +#undef pci_ss_info_10cf_105e +#define pci_ss_info_10cf_105e pci_ss_info_1043_0675_10cf_105e +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c001 = + {0x1044, 0xc001, pci_subsys_1044_a501_1044_c001, 0}; +#undef pci_ss_info_1044_c001 +#define pci_ss_info_1044_c001 pci_ss_info_1044_a501_1044_c001 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c002 = + {0x1044, 0xc002, pci_subsys_1044_a501_1044_c002, 0}; +#undef pci_ss_info_1044_c002 +#define pci_ss_info_1044_c002 pci_ss_info_1044_a501_1044_c002 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c003 = + {0x1044, 0xc003, pci_subsys_1044_a501_1044_c003, 0}; +#undef pci_ss_info_1044_c003 +#define pci_ss_info_1044_c003 pci_ss_info_1044_a501_1044_c003 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c004 = + {0x1044, 0xc004, pci_subsys_1044_a501_1044_c004, 0}; +#undef pci_ss_info_1044_c004 +#define pci_ss_info_1044_c004 pci_ss_info_1044_a501_1044_c004 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c005 = + {0x1044, 0xc005, pci_subsys_1044_a501_1044_c005, 0}; +#undef pci_ss_info_1044_c005 +#define pci_ss_info_1044_c005 pci_ss_info_1044_a501_1044_c005 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00a = + {0x1044, 0xc00a, pci_subsys_1044_a501_1044_c00a, 0}; +#undef pci_ss_info_1044_c00a +#define pci_ss_info_1044_c00a pci_ss_info_1044_a501_1044_c00a +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00b = + {0x1044, 0xc00b, pci_subsys_1044_a501_1044_c00b, 0}; +#undef pci_ss_info_1044_c00b +#define pci_ss_info_1044_c00b pci_ss_info_1044_a501_1044_c00b +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00c = + {0x1044, 0xc00c, pci_subsys_1044_a501_1044_c00c, 0}; +#undef pci_ss_info_1044_c00c +#define pci_ss_info_1044_c00c pci_ss_info_1044_a501_1044_c00c +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00d = + {0x1044, 0xc00d, pci_subsys_1044_a501_1044_c00d, 0}; +#undef pci_ss_info_1044_c00d +#define pci_ss_info_1044_c00d pci_ss_info_1044_a501_1044_c00d +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00e = + {0x1044, 0xc00e, pci_subsys_1044_a501_1044_c00e, 0}; +#undef pci_ss_info_1044_c00e +#define pci_ss_info_1044_c00e pci_ss_info_1044_a501_1044_c00e +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c00f = + {0x1044, 0xc00f, pci_subsys_1044_a501_1044_c00f, 0}; +#undef pci_ss_info_1044_c00f +#define pci_ss_info_1044_c00f pci_ss_info_1044_a501_1044_c00f +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c014 = + {0x1044, 0xc014, pci_subsys_1044_a501_1044_c014, 0}; +#undef pci_ss_info_1044_c014 +#define pci_ss_info_1044_c014 pci_ss_info_1044_a501_1044_c014 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c015 = + {0x1044, 0xc015, pci_subsys_1044_a501_1044_c015, 0}; +#undef pci_ss_info_1044_c015 +#define pci_ss_info_1044_c015 pci_ss_info_1044_a501_1044_c015 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c016 = + {0x1044, 0xc016, pci_subsys_1044_a501_1044_c016, 0}; +#undef pci_ss_info_1044_c016 +#define pci_ss_info_1044_c016 pci_ss_info_1044_a501_1044_c016 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c01e = + {0x1044, 0xc01e, pci_subsys_1044_a501_1044_c01e, 0}; +#undef pci_ss_info_1044_c01e +#define pci_ss_info_1044_c01e pci_ss_info_1044_a501_1044_c01e +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c01f = + {0x1044, 0xc01f, pci_subsys_1044_a501_1044_c01f, 0}; +#undef pci_ss_info_1044_c01f +#define pci_ss_info_1044_c01f pci_ss_info_1044_a501_1044_c01f +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c020 = + {0x1044, 0xc020, pci_subsys_1044_a501_1044_c020, 0}; +#undef pci_ss_info_1044_c020 +#define pci_ss_info_1044_c020 pci_ss_info_1044_a501_1044_c020 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c021 = + {0x1044, 0xc021, pci_subsys_1044_a501_1044_c021, 0}; +#undef pci_ss_info_1044_c021 +#define pci_ss_info_1044_c021 pci_ss_info_1044_a501_1044_c021 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c028 = + {0x1044, 0xc028, pci_subsys_1044_a501_1044_c028, 0}; +#undef pci_ss_info_1044_c028 +#define pci_ss_info_1044_c028 pci_ss_info_1044_a501_1044_c028 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c029 = + {0x1044, 0xc029, pci_subsys_1044_a501_1044_c029, 0}; +#undef pci_ss_info_1044_c029 +#define pci_ss_info_1044_c029 pci_ss_info_1044_a501_1044_c029 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c02a = + {0x1044, 0xc02a, pci_subsys_1044_a501_1044_c02a, 0}; +#undef pci_ss_info_1044_c02a +#define pci_ss_info_1044_c02a pci_ss_info_1044_a501_1044_c02a +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c03c = + {0x1044, 0xc03c, pci_subsys_1044_a501_1044_c03c, 0}; +#undef pci_ss_info_1044_c03c +#define pci_ss_info_1044_c03c pci_ss_info_1044_a501_1044_c03c +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c03d = + {0x1044, 0xc03d, pci_subsys_1044_a501_1044_c03d, 0}; +#undef pci_ss_info_1044_c03d +#define pci_ss_info_1044_c03d pci_ss_info_1044_a501_1044_c03d +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c03e = + {0x1044, 0xc03e, pci_subsys_1044_a501_1044_c03e, 0}; +#undef pci_ss_info_1044_c03e +#define pci_ss_info_1044_c03e pci_ss_info_1044_a501_1044_c03e +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c046 = + {0x1044, 0xc046, pci_subsys_1044_a501_1044_c046, 0}; +#undef pci_ss_info_1044_c046 +#define pci_ss_info_1044_c046 pci_ss_info_1044_a501_1044_c046 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c047 = + {0x1044, 0xc047, pci_subsys_1044_a501_1044_c047, 0}; +#undef pci_ss_info_1044_c047 +#define pci_ss_info_1044_c047 pci_ss_info_1044_a501_1044_c047 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c048 = + {0x1044, 0xc048, pci_subsys_1044_a501_1044_c048, 0}; +#undef pci_ss_info_1044_c048 +#define pci_ss_info_1044_c048 pci_ss_info_1044_a501_1044_c048 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c050 = + {0x1044, 0xc050, pci_subsys_1044_a501_1044_c050, 0}; +#undef pci_ss_info_1044_c050 +#define pci_ss_info_1044_c050 pci_ss_info_1044_a501_1044_c050 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c051 = + {0x1044, 0xc051, pci_subsys_1044_a501_1044_c051, 0}; +#undef pci_ss_info_1044_c051 +#define pci_ss_info_1044_c051 pci_ss_info_1044_a501_1044_c051 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c052 = + {0x1044, 0xc052, pci_subsys_1044_a501_1044_c052, 0}; +#undef pci_ss_info_1044_c052 +#define pci_ss_info_1044_c052 pci_ss_info_1044_a501_1044_c052 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c05a = + {0x1044, 0xc05a, pci_subsys_1044_a501_1044_c05a, 0}; +#undef pci_ss_info_1044_c05a +#define pci_ss_info_1044_c05a pci_ss_info_1044_a501_1044_c05a +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c05b = + {0x1044, 0xc05b, pci_subsys_1044_a501_1044_c05b, 0}; +#undef pci_ss_info_1044_c05b +#define pci_ss_info_1044_c05b pci_ss_info_1044_a501_1044_c05b +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c064 = + {0x1044, 0xc064, pci_subsys_1044_a501_1044_c064, 0}; +#undef pci_ss_info_1044_c064 +#define pci_ss_info_1044_c064 pci_ss_info_1044_a501_1044_c064 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c065 = + {0x1044, 0xc065, pci_subsys_1044_a501_1044_c065, 0}; +#undef pci_ss_info_1044_c065 +#define pci_ss_info_1044_c065 pci_ss_info_1044_a501_1044_c065 +static const pciSubsystemInfo pci_ss_info_1044_a501_1044_c066 = + {0x1044, 0xc066, pci_subsys_1044_a501_1044_c066, 0}; +#undef pci_ss_info_1044_c066 +#define pci_ss_info_1044_c066 pci_ss_info_1044_a501_1044_c066 +static const pciSubsystemInfo pci_ss_info_1044_a511_1044_c032 = + {0x1044, 0xc032, pci_subsys_1044_a511_1044_c032, 0}; +#undef pci_ss_info_1044_c032 +#define pci_ss_info_1044_c032 pci_ss_info_1044_a511_1044_c032 +static const pciSubsystemInfo pci_ss_info_1044_a511_1044_c035 = + {0x1044, 0xc035, pci_subsys_1044_a511_1044_c035, 0}; +#undef pci_ss_info_1044_c035 +#define pci_ss_info_1044_c035 pci_ss_info_1044_a511_1044_c035 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1048_8901_1048_0935 = + {0x1048, 0x0935, pci_subsys_1048_8901_1048_0935, 0}; +#undef pci_ss_info_1048_0935 +#define pci_ss_info_1048_0935 pci_ss_info_1048_8901_1048_0935 +#endif +static const pciSubsystemInfo pci_ss_info_104a_0500_104a_0500 = + {0x104a, 0x0500, pci_subsys_104a_0500_104a_0500, 0}; +#undef pci_ss_info_104a_0500 +#define pci_ss_info_104a_0500 pci_ss_info_104a_0500_104a_0500 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1011_4d10 = + {0x1011, 0x4d10, pci_subsys_104c_3d07_1011_4d10, 0}; +#undef pci_ss_info_1011_4d10 +#define pci_ss_info_1011_4d10 pci_ss_info_104c_3d07_1011_4d10 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1040_000f = + {0x1040, 0x000f, pci_subsys_104c_3d07_1040_000f, 0}; +#undef pci_ss_info_1040_000f +#define pci_ss_info_1040_000f pci_ss_info_104c_3d07_1040_000f +static const pciSubsystemInfo pci_ss_info_104c_3d07_1040_0011 = + {0x1040, 0x0011, pci_subsys_104c_3d07_1040_0011, 0}; +#undef pci_ss_info_1040_0011 +#define pci_ss_info_1040_0011 pci_ss_info_104c_3d07_1040_0011 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a31 = + {0x1048, 0x0a31, pci_subsys_104c_3d07_1048_0a31, 0}; +#undef pci_ss_info_1048_0a31 +#define pci_ss_info_1048_0a31 pci_ss_info_104c_3d07_1048_0a31 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a32 = + {0x1048, 0x0a32, pci_subsys_104c_3d07_1048_0a32, 0}; +#undef pci_ss_info_1048_0a32 +#define pci_ss_info_1048_0a32 pci_ss_info_104c_3d07_1048_0a32 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a34 = + {0x1048, 0x0a34, pci_subsys_104c_3d07_1048_0a34, 0}; +#undef pci_ss_info_1048_0a34 +#define pci_ss_info_1048_0a34 pci_ss_info_104c_3d07_1048_0a34 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a35 = + {0x1048, 0x0a35, pci_subsys_104c_3d07_1048_0a35, 0}; +#undef pci_ss_info_1048_0a35 +#define pci_ss_info_1048_0a35 pci_ss_info_104c_3d07_1048_0a35 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a36 = + {0x1048, 0x0a36, pci_subsys_104c_3d07_1048_0a36, 0}; +#undef pci_ss_info_1048_0a36 +#define pci_ss_info_1048_0a36 pci_ss_info_104c_3d07_1048_0a36 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a43 = + {0x1048, 0x0a43, pci_subsys_104c_3d07_1048_0a43, 0}; +#undef pci_ss_info_1048_0a43 +#define pci_ss_info_1048_0a43 pci_ss_info_104c_3d07_1048_0a43 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1048_0a44 = + {0x1048, 0x0a44, pci_subsys_104c_3d07_1048_0a44, 0}; +#undef pci_ss_info_1048_0a44 +#define pci_ss_info_1048_0a44 pci_ss_info_104c_3d07_1048_0a44 +static const pciSubsystemInfo pci_ss_info_104c_3d07_107d_2633 = + {0x107d, 0x2633, pci_subsys_104c_3d07_107d_2633, 0}; +#undef pci_ss_info_107d_2633 +#define pci_ss_info_107d_2633 pci_ss_info_104c_3d07_107d_2633 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0127 = + {0x1092, 0x0127, pci_subsys_104c_3d07_1092_0127, 0}; +#undef pci_ss_info_1092_0127 +#define pci_ss_info_1092_0127 pci_ss_info_104c_3d07_1092_0127 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0136 = + {0x1092, 0x0136, pci_subsys_104c_3d07_1092_0136, 0}; +#undef pci_ss_info_1092_0136 +#define pci_ss_info_1092_0136 pci_ss_info_104c_3d07_1092_0136 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0141 = + {0x1092, 0x0141, pci_subsys_104c_3d07_1092_0141, 0}; +#undef pci_ss_info_1092_0141 +#define pci_ss_info_1092_0141 pci_ss_info_104c_3d07_1092_0141 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0146 = + {0x1092, 0x0146, pci_subsys_104c_3d07_1092_0146, 0}; +#undef pci_ss_info_1092_0146 +#define pci_ss_info_1092_0146 pci_ss_info_104c_3d07_1092_0146 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0148 = + {0x1092, 0x0148, pci_subsys_104c_3d07_1092_0148, 0}; +#undef pci_ss_info_1092_0148 +#define pci_ss_info_1092_0148 pci_ss_info_104c_3d07_1092_0148 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0149 = + {0x1092, 0x0149, pci_subsys_104c_3d07_1092_0149, 0}; +#undef pci_ss_info_1092_0149 +#define pci_ss_info_1092_0149 pci_ss_info_104c_3d07_1092_0149 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0152 = + {0x1092, 0x0152, pci_subsys_104c_3d07_1092_0152, 0}; +#undef pci_ss_info_1092_0152 +#define pci_ss_info_1092_0152 pci_ss_info_104c_3d07_1092_0152 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0154 = + {0x1092, 0x0154, pci_subsys_104c_3d07_1092_0154, 0}; +#undef pci_ss_info_1092_0154 +#define pci_ss_info_1092_0154 pci_ss_info_104c_3d07_1092_0154 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0155 = + {0x1092, 0x0155, pci_subsys_104c_3d07_1092_0155, 0}; +#undef pci_ss_info_1092_0155 +#define pci_ss_info_1092_0155 pci_ss_info_104c_3d07_1092_0155 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0156 = + {0x1092, 0x0156, pci_subsys_104c_3d07_1092_0156, 0}; +#undef pci_ss_info_1092_0156 +#define pci_ss_info_1092_0156 pci_ss_info_104c_3d07_1092_0156 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1092_0157 = + {0x1092, 0x0157, pci_subsys_104c_3d07_1092_0157, 0}; +#undef pci_ss_info_1092_0157 +#define pci_ss_info_1092_0157 pci_ss_info_104c_3d07_1092_0157 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1097_3d01 = + {0x1097, 0x3d01, pci_subsys_104c_3d07_1097_3d01, 0}; +#undef pci_ss_info_1097_3d01 +#define pci_ss_info_1097_3d01 pci_ss_info_104c_3d07_1097_3d01 +static const pciSubsystemInfo pci_ss_info_104c_3d07_1102_100f = + {0x1102, 0x100f, pci_subsys_104c_3d07_1102_100f, 0}; +#undef pci_ss_info_1102_100f +#define pci_ss_info_1102_100f pci_ss_info_104c_3d07_1102_100f +static const pciSubsystemInfo pci_ss_info_104c_3d07_3d3d_0100 = + {0x3d3d, 0x0100, pci_subsys_104c_3d07_3d3d_0100, 0}; +#undef pci_ss_info_3d3d_0100 +#define pci_ss_info_3d3d_0100 pci_ss_info_104c_3d07_3d3d_0100 +static const pciSubsystemInfo pci_ss_info_104c_8000_e4bf_1010 = + {0xe4bf, 0x1010, pci_subsys_104c_8000_e4bf_1010, 0}; +#undef pci_ss_info_e4bf_1010 +#define pci_ss_info_e4bf_1010 pci_ss_info_104c_8000_e4bf_1010 +static const pciSubsystemInfo pci_ss_info_104c_8000_e4bf_1020 = + {0xe4bf, 0x1020, pci_subsys_104c_8000_e4bf_1020, 0}; +#undef pci_ss_info_e4bf_1020 +#define pci_ss_info_e4bf_1020 pci_ss_info_104c_8000_e4bf_1020 +static const pciSubsystemInfo pci_ss_info_104c_8009_104d_8032 = + {0x104d, 0x8032, pci_subsys_104c_8009_104d_8032, 0}; +#undef pci_ss_info_104d_8032 +#define pci_ss_info_104d_8032 pci_ss_info_104c_8009_104d_8032 +static const pciSubsystemInfo pci_ss_info_104c_8019_11bd_000a = + {0x11bd, 0x000a, pci_subsys_104c_8019_11bd_000a, 0}; +#undef pci_ss_info_11bd_000a +#define pci_ss_info_11bd_000a pci_ss_info_104c_8019_11bd_000a +static const pciSubsystemInfo pci_ss_info_104c_8019_11bd_000e = + {0x11bd, 0x000e, pci_subsys_104c_8019_11bd_000e, 0}; +#undef pci_ss_info_11bd_000e +#define pci_ss_info_11bd_000e pci_ss_info_104c_8019_11bd_000e +static const pciSubsystemInfo pci_ss_info_104c_8019_e4bf_1010 = + {0xe4bf, 0x1010, pci_subsys_104c_8019_e4bf_1010, 0}; +#undef pci_ss_info_e4bf_1010 +#define pci_ss_info_e4bf_1010 pci_ss_info_104c_8019_e4bf_1010 +static const pciSubsystemInfo pci_ss_info_104c_8020_11bd_000f = + {0x11bd, 0x000f, pci_subsys_104c_8020_11bd_000f, 0}; +#undef pci_ss_info_11bd_000f +#define pci_ss_info_11bd_000f pci_ss_info_104c_8020_11bd_000f +static const pciSubsystemInfo pci_ss_info_104c_8020_11bd_001c = + {0x11bd, 0x001c, pci_subsys_104c_8020_11bd_001c, 0}; +#undef pci_ss_info_11bd_001c +#define pci_ss_info_11bd_001c pci_ss_info_104c_8020_11bd_001c +static const pciSubsystemInfo pci_ss_info_104c_8021_104d_80df = + {0x104d, 0x80df, pci_subsys_104c_8021_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_104c_8021_104d_80df +static const pciSubsystemInfo pci_ss_info_104c_8021_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_104c_8021_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_104c_8021_104d_80e7 +static const pciSubsystemInfo pci_ss_info_104c_8023_103c_088c = + {0x103c, 0x088c, pci_subsys_104c_8023_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_104c_8023_103c_088c +static const pciSubsystemInfo pci_ss_info_104c_8023_1043_808b = + {0x1043, 0x808b, pci_subsys_104c_8023_1043_808b, 0}; +#undef pci_ss_info_1043_808b +#define pci_ss_info_1043_808b pci_ss_info_104c_8023_1043_808b +static const pciSubsystemInfo pci_ss_info_104c_8025_1458_1000 = + {0x1458, 0x1000, pci_subsys_104c_8025_1458_1000, 0}; +#undef pci_ss_info_1458_1000 +#define pci_ss_info_1458_1000 pci_ss_info_104c_8025_1458_1000 +static const pciSubsystemInfo pci_ss_info_104c_8026_1025_003c = + {0x1025, 0x003c, pci_subsys_104c_8026_1025_003c, 0}; +#undef pci_ss_info_1025_003c +#define pci_ss_info_1025_003c pci_ss_info_104c_8026_1025_003c +static const pciSubsystemInfo pci_ss_info_104c_8026_103c_006a = + {0x103c, 0x006a, pci_subsys_104c_8026_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_104c_8026_103c_006a +static const pciSubsystemInfo pci_ss_info_104c_8026_1043_808d = + {0x1043, 0x808d, pci_subsys_104c_8026_1043_808d, 0}; +#undef pci_ss_info_1043_808d +#define pci_ss_info_1043_808d pci_ss_info_104c_8026_1043_808d +static const pciSubsystemInfo pci_ss_info_104c_8027_1028_00e6 = + {0x1028, 0x00e6, pci_subsys_104c_8027_1028_00e6, 0}; +#undef pci_ss_info_1028_00e6 +#define pci_ss_info_1028_00e6 pci_ss_info_104c_8027_1028_00e6 +static const pciSubsystemInfo pci_ss_info_104c_8029_1028_0163 = + {0x1028, 0x0163, pci_subsys_104c_8029_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_104c_8029_1028_0163 +static const pciSubsystemInfo pci_ss_info_104c_8029_1028_0196 = + {0x1028, 0x0196, pci_subsys_104c_8029_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_104c_8029_1028_0196 +static const pciSubsystemInfo pci_ss_info_104c_8029_1071_8160 = + {0x1071, 0x8160, pci_subsys_104c_8029_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_104c_8029_1071_8160 +static const pciSubsystemInfo pci_ss_info_104c_802b_1028_0139 = + {0x1028, 0x0139, pci_subsys_104c_802b_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_104c_802b_1028_0139 +static const pciSubsystemInfo pci_ss_info_104c_802b_1028_014e = + {0x1028, 0x014e, pci_subsys_104c_802b_1028_014e, 0}; +#undef pci_ss_info_1028_014e +#define pci_ss_info_1028_014e pci_ss_info_104c_802b_1028_014e +static const pciSubsystemInfo pci_ss_info_104c_8031_1025_0080 = + {0x1025, 0x0080, pci_subsys_104c_8031_1025_0080, 0}; +#undef pci_ss_info_1025_0080 +#define pci_ss_info_1025_0080 pci_ss_info_104c_8031_1025_0080 +static const pciSubsystemInfo pci_ss_info_104c_8031_103c_099c = + {0x103c, 0x099c, pci_subsys_104c_8031_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_104c_8031_103c_099c +static const pciSubsystemInfo pci_ss_info_104c_8031_103c_308b = + {0x103c, 0x308b, pci_subsys_104c_8031_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_104c_8031_103c_308b +static const pciSubsystemInfo pci_ss_info_104c_8032_1025_0080 = + {0x1025, 0x0080, pci_subsys_104c_8032_1025_0080, 0}; +#undef pci_ss_info_1025_0080 +#define pci_ss_info_1025_0080 pci_ss_info_104c_8032_1025_0080 +static const pciSubsystemInfo pci_ss_info_104c_8032_103c_099c = + {0x103c, 0x099c, pci_subsys_104c_8032_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_104c_8032_103c_099c +static const pciSubsystemInfo pci_ss_info_104c_8032_103c_308b = + {0x103c, 0x308b, pci_subsys_104c_8032_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_104c_8032_103c_308b +static const pciSubsystemInfo pci_ss_info_104c_8033_1025_0080 = + {0x1025, 0x0080, pci_subsys_104c_8033_1025_0080, 0}; +#undef pci_ss_info_1025_0080 +#define pci_ss_info_1025_0080 pci_ss_info_104c_8033_1025_0080 +static const pciSubsystemInfo pci_ss_info_104c_8033_103c_099c = + {0x103c, 0x099c, pci_subsys_104c_8033_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_104c_8033_103c_099c +static const pciSubsystemInfo pci_ss_info_104c_8033_103c_308b = + {0x103c, 0x308b, pci_subsys_104c_8033_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_104c_8033_103c_308b +static const pciSubsystemInfo pci_ss_info_104c_8034_1025_0080 = + {0x1025, 0x0080, pci_subsys_104c_8034_1025_0080, 0}; +#undef pci_ss_info_1025_0080 +#define pci_ss_info_1025_0080 pci_ss_info_104c_8034_1025_0080 +static const pciSubsystemInfo pci_ss_info_104c_8034_103c_099c = + {0x103c, 0x099c, pci_subsys_104c_8034_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_104c_8034_103c_099c +static const pciSubsystemInfo pci_ss_info_104c_8034_103c_308b = + {0x103c, 0x308b, pci_subsys_104c_8034_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_104c_8034_103c_308b +static const pciSubsystemInfo pci_ss_info_104c_8035_103c_099c = + {0x103c, 0x099c, pci_subsys_104c_8035_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_104c_8035_103c_099c +static const pciSubsystemInfo pci_ss_info_104c_8039_103c_309f = + {0x103c, 0x309f, pci_subsys_104c_8039_103c_309f, 0}; +#undef pci_ss_info_103c_309f +#define pci_ss_info_103c_309f pci_ss_info_104c_8039_103c_309f +static const pciSubsystemInfo pci_ss_info_104c_803a_103c_309f = + {0x103c, 0x309f, pci_subsys_104c_803a_103c_309f, 0}; +#undef pci_ss_info_103c_309f +#define pci_ss_info_103c_309f pci_ss_info_104c_803a_103c_309f +static const pciSubsystemInfo pci_ss_info_104c_803b_103c_309f = + {0x103c, 0x309f, pci_subsys_104c_803b_103c_309f, 0}; +#undef pci_ss_info_103c_309f +#define pci_ss_info_103c_309f pci_ss_info_104c_803b_103c_309f +static const pciSubsystemInfo pci_ss_info_104c_803c_103c_309f = + {0x103c, 0x309f, pci_subsys_104c_803c_103c_309f, 0}; +#undef pci_ss_info_103c_309f +#define pci_ss_info_103c_309f pci_ss_info_104c_803c_103c_309f +static const pciSubsystemInfo pci_ss_info_104c_803d_103c_309f = + {0x103c, 0x309f, pci_subsys_104c_803d_103c_309f, 0}; +#undef pci_ss_info_103c_309f +#define pci_ss_info_103c_309f pci_ss_info_104c_803d_103c_309f +static const pciSubsystemInfo pci_ss_info_104c_8204_1028_0139 = + {0x1028, 0x0139, pci_subsys_104c_8204_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_104c_8204_1028_0139 +static const pciSubsystemInfo pci_ss_info_104c_8204_1028_014e = + {0x1028, 0x014e, pci_subsys_104c_8204_1028_014e, 0}; +#undef pci_ss_info_1028_014e +#define pci_ss_info_1028_014e pci_ss_info_104c_8204_1028_014e +static const pciSubsystemInfo pci_ss_info_104c_8400_1186_3b00 = + {0x1186, 0x3b00, pci_subsys_104c_8400_1186_3b00, 0}; +#undef pci_ss_info_1186_3b00 +#define pci_ss_info_1186_3b00 pci_ss_info_104c_8400_1186_3b00 +static const pciSubsystemInfo pci_ss_info_104c_8400_1186_3b01 = + {0x1186, 0x3b01, pci_subsys_104c_8400_1186_3b01, 0}; +#undef pci_ss_info_1186_3b01 +#define pci_ss_info_1186_3b01 pci_ss_info_104c_8400_1186_3b01 +static const pciSubsystemInfo pci_ss_info_104c_8400_16ab_8501 = + {0x16ab, 0x8501, pci_subsys_104c_8400_16ab_8501, 0}; +#undef pci_ss_info_16ab_8501 +#define pci_ss_info_16ab_8501 pci_ss_info_104c_8400_16ab_8501 +static const pciSubsystemInfo pci_ss_info_104c_9066_104c_9066 = + {0x104c, 0x9066, pci_subsys_104c_9066_104c_9066, 0}; +#undef pci_ss_info_104c_9066 +#define pci_ss_info_104c_9066 pci_ss_info_104c_9066_104c_9066 +static const pciSubsystemInfo pci_ss_info_104c_9066_1186_3b04 = + {0x1186, 0x3b04, pci_subsys_104c_9066_1186_3b04, 0}; +#undef pci_ss_info_1186_3b04 +#define pci_ss_info_1186_3b04 pci_ss_info_104c_9066_1186_3b04 +static const pciSubsystemInfo pci_ss_info_104c_9066_1186_3b05 = + {0x1186, 0x3b05, pci_subsys_104c_9066_1186_3b05, 0}; +#undef pci_ss_info_1186_3b05 +#define pci_ss_info_1186_3b05 pci_ss_info_104c_9066_1186_3b05 +static const pciSubsystemInfo pci_ss_info_104c_9066_13d1_aba0 = + {0x13d1, 0xaba0, pci_subsys_104c_9066_13d1_aba0, 0}; +#undef pci_ss_info_13d1_aba0 +#define pci_ss_info_13d1_aba0 pci_ss_info_104c_9066_13d1_aba0 +static const pciSubsystemInfo pci_ss_info_104c_9066_1737_0033 = + {0x1737, 0x0033, pci_subsys_104c_9066_1737_0033, 0}; +#undef pci_ss_info_1737_0033 +#define pci_ss_info_1737_0033 pci_ss_info_104c_9066_1737_0033 +static const pciSubsystemInfo pci_ss_info_104c_a106_175c_5000 = + {0x175c, 0x5000, pci_subsys_104c_a106_175c_5000, 0}; +#undef pci_ss_info_175c_5000 +#define pci_ss_info_175c_5000 pci_ss_info_104c_a106_175c_5000 +static const pciSubsystemInfo pci_ss_info_104c_a106_175c_6400 = + {0x175c, 0x6400, pci_subsys_104c_a106_175c_6400, 0}; +#undef pci_ss_info_175c_6400 +#define pci_ss_info_175c_6400 pci_ss_info_104c_a106_175c_6400 +static const pciSubsystemInfo pci_ss_info_104c_a106_175c_8700 = + {0x175c, 0x8700, pci_subsys_104c_a106_175c_8700, 0}; +#undef pci_ss_info_175c_8700 +#define pci_ss_info_175c_8700 pci_ss_info_104c_a106_175c_8700 +static const pciSubsystemInfo pci_ss_info_104c_ac16_1014_0092 = + {0x1014, 0x0092, pci_subsys_104c_ac16_1014_0092, 0}; +#undef pci_ss_info_1014_0092 +#define pci_ss_info_1014_0092 pci_ss_info_104c_ac16_1014_0092 +static const pciSubsystemInfo pci_ss_info_104c_ac1b_0e11_b113 = + {0x0e11, 0xb113, pci_subsys_104c_ac1b_0e11_b113, 0}; +#undef pci_ss_info_0e11_b113 +#define pci_ss_info_0e11_b113 pci_ss_info_104c_ac1b_0e11_b113 +static const pciSubsystemInfo pci_ss_info_104c_ac1b_1014_0130 = + {0x1014, 0x0130, pci_subsys_104c_ac1b_1014_0130, 0}; +#undef pci_ss_info_1014_0130 +#define pci_ss_info_1014_0130 pci_ss_info_104c_ac1b_1014_0130 +static const pciSubsystemInfo pci_ss_info_104c_ac1c_0e11_b121 = + {0x0e11, 0xb121, pci_subsys_104c_ac1c_0e11_b121, 0}; +#undef pci_ss_info_0e11_b121 +#define pci_ss_info_0e11_b121 pci_ss_info_104c_ac1c_0e11_b121 +static const pciSubsystemInfo pci_ss_info_104c_ac1c_1028_0088 = + {0x1028, 0x0088, pci_subsys_104c_ac1c_1028_0088, 0}; +#undef pci_ss_info_1028_0088 +#define pci_ss_info_1028_0088 pci_ss_info_104c_ac1c_1028_0088 +static const pciSubsystemInfo pci_ss_info_104c_ac42_1028_00e6 = + {0x1028, 0x00e6, pci_subsys_104c_ac42_1028_00e6, 0}; +#undef pci_ss_info_1028_00e6 +#define pci_ss_info_1028_00e6 pci_ss_info_104c_ac42_1028_00e6 +static const pciSubsystemInfo pci_ss_info_104c_ac44_1028_0163 = + {0x1028, 0x0163, pci_subsys_104c_ac44_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_104c_ac44_1028_0163 +static const pciSubsystemInfo pci_ss_info_104c_ac44_1028_0196 = + {0x1028, 0x0196, pci_subsys_104c_ac44_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_104c_ac44_1028_0196 +static const pciSubsystemInfo pci_ss_info_104c_ac44_1071_8160 = + {0x1071, 0x8160, pci_subsys_104c_ac44_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_104c_ac44_1071_8160 +static const pciSubsystemInfo pci_ss_info_104c_ac47_1028_0139 = + {0x1028, 0x0139, pci_subsys_104c_ac47_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_104c_ac47_1028_0139 +static const pciSubsystemInfo pci_ss_info_104c_ac47_1028_013f = + {0x1028, 0x013f, pci_subsys_104c_ac47_1028_013f, 0}; +#undef pci_ss_info_1028_013f +#define pci_ss_info_1028_013f pci_ss_info_104c_ac47_1028_013f +static const pciSubsystemInfo pci_ss_info_104c_ac47_1028_014e = + {0x1028, 0x014e, pci_subsys_104c_ac47_1028_014e, 0}; +#undef pci_ss_info_1028_014e +#define pci_ss_info_1028_014e pci_ss_info_104c_ac47_1028_014e +static const pciSubsystemInfo pci_ss_info_104c_ac4a_1028_0139 = + {0x1028, 0x0139, pci_subsys_104c_ac4a_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_104c_ac4a_1028_0139 +static const pciSubsystemInfo pci_ss_info_104c_ac4a_1028_014e = + {0x1028, 0x014e, pci_subsys_104c_ac4a_1028_014e, 0}; +#undef pci_ss_info_1028_014e +#define pci_ss_info_1028_014e pci_ss_info_104c_ac4a_1028_014e +static const pciSubsystemInfo pci_ss_info_104c_ac51_0e11_004e = + {0x0e11, 0x004e, pci_subsys_104c_ac51_0e11_004e, 0}; +#undef pci_ss_info_0e11_004e +#define pci_ss_info_0e11_004e pci_ss_info_104c_ac51_0e11_004e +static const pciSubsystemInfo pci_ss_info_104c_ac51_1014_0148 = + {0x1014, 0x0148, pci_subsys_104c_ac51_1014_0148, 0}; +#undef pci_ss_info_1014_0148 +#define pci_ss_info_1014_0148 pci_ss_info_104c_ac51_1014_0148 +static const pciSubsystemInfo pci_ss_info_104c_ac51_1014_023b = + {0x1014, 0x023b, pci_subsys_104c_ac51_1014_023b, 0}; +#undef pci_ss_info_1014_023b +#define pci_ss_info_1014_023b pci_ss_info_104c_ac51_1014_023b +static const pciSubsystemInfo pci_ss_info_104c_ac51_1028_00b1 = + {0x1028, 0x00b1, pci_subsys_104c_ac51_1028_00b1, 0}; +#undef pci_ss_info_1028_00b1 +#define pci_ss_info_1028_00b1 pci_ss_info_104c_ac51_1028_00b1 +static const pciSubsystemInfo pci_ss_info_104c_ac51_1028_012a = + {0x1028, 0x012a, pci_subsys_104c_ac51_1028_012a, 0}; +#undef pci_ss_info_1028_012a +#define pci_ss_info_1028_012a pci_ss_info_104c_ac51_1028_012a +static const pciSubsystemInfo pci_ss_info_104c_ac51_1033_80cd = + {0x1033, 0x80cd, pci_subsys_104c_ac51_1033_80cd, 0}; +#undef pci_ss_info_1033_80cd +#define pci_ss_info_1033_80cd pci_ss_info_104c_ac51_1033_80cd +static const pciSubsystemInfo pci_ss_info_104c_ac51_1095_10cf = + {0x1095, 0x10cf, pci_subsys_104c_ac51_1095_10cf, 0}; +#undef pci_ss_info_1095_10cf +#define pci_ss_info_1095_10cf pci_ss_info_104c_ac51_1095_10cf +static const pciSubsystemInfo pci_ss_info_104c_ac51_10cf_1095 = + {0x10cf, 0x1095, pci_subsys_104c_ac51_10cf_1095, 0}; +#undef pci_ss_info_10cf_1095 +#define pci_ss_info_10cf_1095 pci_ss_info_104c_ac51_10cf_1095 +static const pciSubsystemInfo pci_ss_info_104c_ac51_e4bf_1000 = + {0xe4bf, 0x1000, pci_subsys_104c_ac51_e4bf_1000, 0}; +#undef pci_ss_info_e4bf_1000 +#define pci_ss_info_e4bf_1000 pci_ss_info_104c_ac51_e4bf_1000 +static const pciSubsystemInfo pci_ss_info_104c_ac54_103c_08b0 = + {0x103c, 0x08b0, pci_subsys_104c_ac54_103c_08b0, 0}; +#undef pci_ss_info_103c_08b0 +#define pci_ss_info_103c_08b0 pci_ss_info_104c_ac54_103c_08b0 +static const pciSubsystemInfo pci_ss_info_104c_ac55_1014_0512 = + {0x1014, 0x0512, pci_subsys_104c_ac55_1014_0512, 0}; +#undef pci_ss_info_1014_0512 +#define pci_ss_info_1014_0512 pci_ss_info_104c_ac55_1014_0512 +static const pciSubsystemInfo pci_ss_info_104c_ac56_1014_0512 = + {0x1014, 0x0512, pci_subsys_104c_ac56_1014_0512, 0}; +#undef pci_ss_info_1014_0512 +#define pci_ss_info_1014_0512 pci_ss_info_104c_ac56_1014_0512 +static const pciSubsystemInfo pci_ss_info_104c_ac56_1014_0528 = + {0x1014, 0x0528, pci_subsys_104c_ac56_1014_0528, 0}; +#undef pci_ss_info_1014_0528 +#define pci_ss_info_1014_0528 pci_ss_info_104c_ac56_1014_0528 +static const pciSubsystemInfo pci_ss_info_104c_ac56_17aa_2012 = + {0x17aa, 0x2012, pci_subsys_104c_ac56_17aa_2012, 0}; +#undef pci_ss_info_17aa_2012 +#define pci_ss_info_17aa_2012 pci_ss_info_104c_ac56_17aa_2012 +static const pciSubsystemInfo pci_ss_info_104c_ac60_175c_5100 = + {0x175c, 0x5100, pci_subsys_104c_ac60_175c_5100, 0}; +#undef pci_ss_info_175c_5100 +#define pci_ss_info_175c_5100 pci_ss_info_104c_ac60_175c_5100 +static const pciSubsystemInfo pci_ss_info_104c_ac60_175c_6100 = + {0x175c, 0x6100, pci_subsys_104c_ac60_175c_6100, 0}; +#undef pci_ss_info_175c_6100 +#define pci_ss_info_175c_6100 pci_ss_info_104c_ac60_175c_6100 +static const pciSubsystemInfo pci_ss_info_104c_ac60_175c_6200 = + {0x175c, 0x6200, pci_subsys_104c_ac60_175c_6200, 0}; +#undef pci_ss_info_175c_6200 +#define pci_ss_info_175c_6200 pci_ss_info_104c_ac60_175c_6200 +static const pciSubsystemInfo pci_ss_info_104c_ac60_175c_8800 = + {0x175c, 0x8800, pci_subsys_104c_ac60_175c_8800, 0}; +#undef pci_ss_info_175c_8800 +#define pci_ss_info_175c_8800 pci_ss_info_104c_ac60_175c_8800 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1050_0840_1050_0001 = + {0x1050, 0x0001, pci_subsys_1050_0840_1050_0001, 0}; +#undef pci_ss_info_1050_0001 +#define pci_ss_info_1050_0001 pci_ss_info_1050_0840_1050_0001 +static const pciSubsystemInfo pci_ss_info_1050_0840_1050_0840 = + {0x1050, 0x0840, pci_subsys_1050_0840_1050_0840, 0}; +#undef pci_ss_info_1050_0840 +#define pci_ss_info_1050_0840 pci_ss_info_1050_0840_1050_0840 +static const pciSubsystemInfo pci_ss_info_1050_6692_1043_1702 = + {0x1043, 0x1702, pci_subsys_1050_6692_1043_1702, 0}; +#undef pci_ss_info_1043_1702 +#define pci_ss_info_1043_1702 pci_ss_info_1050_6692_1043_1702 +static const pciSubsystemInfo pci_ss_info_1050_6692_1043_1703 = + {0x1043, 0x1703, pci_subsys_1050_6692_1043_1703, 0}; +#undef pci_ss_info_1043_1703 +#define pci_ss_info_1043_1703 pci_ss_info_1050_6692_1043_1703 +static const pciSubsystemInfo pci_ss_info_1050_6692_1043_1707 = + {0x1043, 0x1707, pci_subsys_1050_6692_1043_1707, 0}; +#undef pci_ss_info_1043_1707 +#define pci_ss_info_1043_1707 pci_ss_info_1050_6692_1043_1707 +static const pciSubsystemInfo pci_ss_info_1050_6692_144f_1702 = + {0x144f, 0x1702, pci_subsys_1050_6692_144f_1702, 0}; +#undef pci_ss_info_144f_1702 +#define pci_ss_info_144f_1702 pci_ss_info_1050_6692_144f_1702 +static const pciSubsystemInfo pci_ss_info_1050_6692_144f_1703 = + {0x144f, 0x1703, pci_subsys_1050_6692_144f_1703, 0}; +#undef pci_ss_info_144f_1703 +#define pci_ss_info_144f_1703 pci_ss_info_1050_6692_144f_1703 +static const pciSubsystemInfo pci_ss_info_1050_6692_144f_1707 = + {0x144f, 0x1707, pci_subsys_1050_6692_144f_1707, 0}; +#undef pci_ss_info_144f_1707 +#define pci_ss_info_144f_1707 pci_ss_info_1050_6692_144f_1707 +#endif +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0101 = + {0x14fb, 0x0101, pci_subsys_1057_1801_14fb_0101, 0}; +#undef pci_ss_info_14fb_0101 +#define pci_ss_info_14fb_0101 pci_ss_info_1057_1801_14fb_0101 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0102 = + {0x14fb, 0x0102, pci_subsys_1057_1801_14fb_0102, 0}; +#undef pci_ss_info_14fb_0102 +#define pci_ss_info_14fb_0102 pci_ss_info_1057_1801_14fb_0102 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0202 = + {0x14fb, 0x0202, pci_subsys_1057_1801_14fb_0202, 0}; +#undef pci_ss_info_14fb_0202 +#define pci_ss_info_14fb_0202 pci_ss_info_1057_1801_14fb_0202 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0611 = + {0x14fb, 0x0611, pci_subsys_1057_1801_14fb_0611, 0}; +#undef pci_ss_info_14fb_0611 +#define pci_ss_info_14fb_0611 pci_ss_info_1057_1801_14fb_0611 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0612 = + {0x14fb, 0x0612, pci_subsys_1057_1801_14fb_0612, 0}; +#undef pci_ss_info_14fb_0612 +#define pci_ss_info_14fb_0612 pci_ss_info_1057_1801_14fb_0612 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0613 = + {0x14fb, 0x0613, pci_subsys_1057_1801_14fb_0613, 0}; +#undef pci_ss_info_14fb_0613 +#define pci_ss_info_14fb_0613 pci_ss_info_1057_1801_14fb_0613 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0614 = + {0x14fb, 0x0614, pci_subsys_1057_1801_14fb_0614, 0}; +#undef pci_ss_info_14fb_0614 +#define pci_ss_info_14fb_0614 pci_ss_info_1057_1801_14fb_0614 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0621 = + {0x14fb, 0x0621, pci_subsys_1057_1801_14fb_0621, 0}; +#undef pci_ss_info_14fb_0621 +#define pci_ss_info_14fb_0621 pci_ss_info_1057_1801_14fb_0621 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0622 = + {0x14fb, 0x0622, pci_subsys_1057_1801_14fb_0622, 0}; +#undef pci_ss_info_14fb_0622 +#define pci_ss_info_14fb_0622 pci_ss_info_1057_1801_14fb_0622 +static const pciSubsystemInfo pci_ss_info_1057_1801_14fb_0810 = + {0x14fb, 0x0810, pci_subsys_1057_1801_14fb_0810, 0}; +#undef pci_ss_info_14fb_0810 +#define pci_ss_info_14fb_0810 pci_ss_info_1057_1801_14fb_0810 +static const pciSubsystemInfo pci_ss_info_1057_1801_175c_4200 = + {0x175c, 0x4200, pci_subsys_1057_1801_175c_4200, 0}; +#undef pci_ss_info_175c_4200 +#define pci_ss_info_175c_4200 pci_ss_info_1057_1801_175c_4200 +static const pciSubsystemInfo pci_ss_info_1057_1801_175c_4300 = + {0x175c, 0x4300, pci_subsys_1057_1801_175c_4300, 0}; +#undef pci_ss_info_175c_4300 +#define pci_ss_info_175c_4300 pci_ss_info_1057_1801_175c_4300 +static const pciSubsystemInfo pci_ss_info_1057_1801_175c_4400 = + {0x175c, 0x4400, pci_subsys_1057_1801_175c_4400, 0}; +#undef pci_ss_info_175c_4400 +#define pci_ss_info_175c_4400 pci_ss_info_1057_1801_175c_4400 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0010 = + {0xecc0, 0x0010, pci_subsys_1057_1801_ecc0_0010, 0}; +#undef pci_ss_info_ecc0_0010 +#define pci_ss_info_ecc0_0010 pci_ss_info_1057_1801_ecc0_0010 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0020 = + {0xecc0, 0x0020, pci_subsys_1057_1801_ecc0_0020, 0}; +#undef pci_ss_info_ecc0_0020 +#define pci_ss_info_ecc0_0020 pci_ss_info_1057_1801_ecc0_0020 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0030 = + {0xecc0, 0x0030, pci_subsys_1057_1801_ecc0_0030, 0}; +#undef pci_ss_info_ecc0_0030 +#define pci_ss_info_ecc0_0030 pci_ss_info_1057_1801_ecc0_0030 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0031 = + {0xecc0, 0x0031, pci_subsys_1057_1801_ecc0_0031, 0}; +#undef pci_ss_info_ecc0_0031 +#define pci_ss_info_ecc0_0031 pci_ss_info_1057_1801_ecc0_0031 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0040 = + {0xecc0, 0x0040, pci_subsys_1057_1801_ecc0_0040, 0}; +#undef pci_ss_info_ecc0_0040 +#define pci_ss_info_ecc0_0040 pci_ss_info_1057_1801_ecc0_0040 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0041 = + {0xecc0, 0x0041, pci_subsys_1057_1801_ecc0_0041, 0}; +#undef pci_ss_info_ecc0_0041 +#define pci_ss_info_ecc0_0041 pci_ss_info_1057_1801_ecc0_0041 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0050 = + {0xecc0, 0x0050, pci_subsys_1057_1801_ecc0_0050, 0}; +#undef pci_ss_info_ecc0_0050 +#define pci_ss_info_ecc0_0050 pci_ss_info_1057_1801_ecc0_0050 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0051 = + {0xecc0, 0x0051, pci_subsys_1057_1801_ecc0_0051, 0}; +#undef pci_ss_info_ecc0_0051 +#define pci_ss_info_ecc0_0051 pci_ss_info_1057_1801_ecc0_0051 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0070 = + {0xecc0, 0x0070, pci_subsys_1057_1801_ecc0_0070, 0}; +#undef pci_ss_info_ecc0_0070 +#define pci_ss_info_ecc0_0070 pci_ss_info_1057_1801_ecc0_0070 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0071 = + {0xecc0, 0x0071, pci_subsys_1057_1801_ecc0_0071, 0}; +#undef pci_ss_info_ecc0_0071 +#define pci_ss_info_ecc0_0071 pci_ss_info_1057_1801_ecc0_0071 +static const pciSubsystemInfo pci_ss_info_1057_1801_ecc0_0072 = + {0xecc0, 0x0072, pci_subsys_1057_1801_ecc0_0072, 0}; +#undef pci_ss_info_ecc0_0072 +#define pci_ss_info_ecc0_0072 pci_ss_info_1057_1801_ecc0_0072 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0050 = + {0xecc0, 0x0050, pci_subsys_1057_3410_ecc0_0050, 0}; +#undef pci_ss_info_ecc0_0050 +#define pci_ss_info_ecc0_0050 pci_ss_info_1057_3410_ecc0_0050 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0051 = + {0xecc0, 0x0051, pci_subsys_1057_3410_ecc0_0051, 0}; +#undef pci_ss_info_ecc0_0051 +#define pci_ss_info_ecc0_0051 pci_ss_info_1057_3410_ecc0_0051 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0060 = + {0xecc0, 0x0060, pci_subsys_1057_3410_ecc0_0060, 0}; +#undef pci_ss_info_ecc0_0060 +#define pci_ss_info_ecc0_0060 pci_ss_info_1057_3410_ecc0_0060 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0070 = + {0xecc0, 0x0070, pci_subsys_1057_3410_ecc0_0070, 0}; +#undef pci_ss_info_ecc0_0070 +#define pci_ss_info_ecc0_0070 pci_ss_info_1057_3410_ecc0_0070 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0071 = + {0xecc0, 0x0071, pci_subsys_1057_3410_ecc0_0071, 0}; +#undef pci_ss_info_ecc0_0071 +#define pci_ss_info_ecc0_0071 pci_ss_info_1057_3410_ecc0_0071 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0072 = + {0xecc0, 0x0072, pci_subsys_1057_3410_ecc0_0072, 0}; +#undef pci_ss_info_ecc0_0072 +#define pci_ss_info_ecc0_0072 pci_ss_info_1057_3410_ecc0_0072 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0080 = + {0xecc0, 0x0080, pci_subsys_1057_3410_ecc0_0080, 0}; +#undef pci_ss_info_ecc0_0080 +#define pci_ss_info_ecc0_0080 pci_ss_info_1057_3410_ecc0_0080 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0081 = + {0xecc0, 0x0081, pci_subsys_1057_3410_ecc0_0081, 0}; +#undef pci_ss_info_ecc0_0081 +#define pci_ss_info_ecc0_0081 pci_ss_info_1057_3410_ecc0_0081 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0090 = + {0xecc0, 0x0090, pci_subsys_1057_3410_ecc0_0090, 0}; +#undef pci_ss_info_ecc0_0090 +#define pci_ss_info_ecc0_0090 pci_ss_info_1057_3410_ecc0_0090 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_00a0 = + {0xecc0, 0x00a0, pci_subsys_1057_3410_ecc0_00a0, 0}; +#undef pci_ss_info_ecc0_00a0 +#define pci_ss_info_ecc0_00a0 pci_ss_info_1057_3410_ecc0_00a0 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_00b0 = + {0xecc0, 0x00b0, pci_subsys_1057_3410_ecc0_00b0, 0}; +#undef pci_ss_info_ecc0_00b0 +#define pci_ss_info_ecc0_00b0 pci_ss_info_1057_3410_ecc0_00b0 +static const pciSubsystemInfo pci_ss_info_1057_3410_ecc0_0100 = + {0xecc0, 0x0100, pci_subsys_1057_3410_ecc0_0100, 0}; +#undef pci_ss_info_ecc0_0100 +#define pci_ss_info_ecc0_0100 pci_ss_info_1057_3410_ecc0_0100 +static const pciSubsystemInfo pci_ss_info_1057_5600_1057_0300 = + {0x1057, 0x0300, pci_subsys_1057_5600_1057_0300, 0}; +#undef pci_ss_info_1057_0300 +#define pci_ss_info_1057_0300 pci_ss_info_1057_5600_1057_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_1057_0301 = + {0x1057, 0x0301, pci_subsys_1057_5600_1057_0301, 0}; +#undef pci_ss_info_1057_0301 +#define pci_ss_info_1057_0301 pci_ss_info_1057_5600_1057_0301 +static const pciSubsystemInfo pci_ss_info_1057_5600_1057_0302 = + {0x1057, 0x0302, pci_subsys_1057_5600_1057_0302, 0}; +#undef pci_ss_info_1057_0302 +#define pci_ss_info_1057_0302 pci_ss_info_1057_5600_1057_0302 +static const pciSubsystemInfo pci_ss_info_1057_5600_1057_5600 = + {0x1057, 0x5600, pci_subsys_1057_5600_1057_5600, 0}; +#undef pci_ss_info_1057_5600 +#define pci_ss_info_1057_5600 pci_ss_info_1057_5600_1057_5600 +static const pciSubsystemInfo pci_ss_info_1057_5600_13d2_0300 = + {0x13d2, 0x0300, pci_subsys_1057_5600_13d2_0300, 0}; +#undef pci_ss_info_13d2_0300 +#define pci_ss_info_13d2_0300 pci_ss_info_1057_5600_13d2_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_13d2_0301 = + {0x13d2, 0x0301, pci_subsys_1057_5600_13d2_0301, 0}; +#undef pci_ss_info_13d2_0301 +#define pci_ss_info_13d2_0301 pci_ss_info_1057_5600_13d2_0301 +static const pciSubsystemInfo pci_ss_info_1057_5600_13d2_0302 = + {0x13d2, 0x0302, pci_subsys_1057_5600_13d2_0302, 0}; +#undef pci_ss_info_13d2_0302 +#define pci_ss_info_13d2_0302 pci_ss_info_1057_5600_13d2_0302 +static const pciSubsystemInfo pci_ss_info_1057_5600_1436_0300 = + {0x1436, 0x0300, pci_subsys_1057_5600_1436_0300, 0}; +#undef pci_ss_info_1436_0300 +#define pci_ss_info_1436_0300 pci_ss_info_1057_5600_1436_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_1436_0301 = + {0x1436, 0x0301, pci_subsys_1057_5600_1436_0301, 0}; +#undef pci_ss_info_1436_0301 +#define pci_ss_info_1436_0301 pci_ss_info_1057_5600_1436_0301 +static const pciSubsystemInfo pci_ss_info_1057_5600_1436_0302 = + {0x1436, 0x0302, pci_subsys_1057_5600_1436_0302, 0}; +#undef pci_ss_info_1436_0302 +#define pci_ss_info_1436_0302 pci_ss_info_1057_5600_1436_0302 +static const pciSubsystemInfo pci_ss_info_1057_5600_144f_100c = + {0x144f, 0x100c, pci_subsys_1057_5600_144f_100c, 0}; +#undef pci_ss_info_144f_100c +#define pci_ss_info_144f_100c pci_ss_info_1057_5600_144f_100c +static const pciSubsystemInfo pci_ss_info_1057_5600_1494_0300 = + {0x1494, 0x0300, pci_subsys_1057_5600_1494_0300, 0}; +#undef pci_ss_info_1494_0300 +#define pci_ss_info_1494_0300 pci_ss_info_1057_5600_1494_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_1494_0301 = + {0x1494, 0x0301, pci_subsys_1057_5600_1494_0301, 0}; +#undef pci_ss_info_1494_0301 +#define pci_ss_info_1494_0301 pci_ss_info_1057_5600_1494_0301 +static const pciSubsystemInfo pci_ss_info_1057_5600_14c8_0300 = + {0x14c8, 0x0300, pci_subsys_1057_5600_14c8_0300, 0}; +#undef pci_ss_info_14c8_0300 +#define pci_ss_info_14c8_0300 pci_ss_info_1057_5600_14c8_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_14c8_0302 = + {0x14c8, 0x0302, pci_subsys_1057_5600_14c8_0302, 0}; +#undef pci_ss_info_14c8_0302 +#define pci_ss_info_14c8_0302 pci_ss_info_1057_5600_14c8_0302 +static const pciSubsystemInfo pci_ss_info_1057_5600_1668_0300 = + {0x1668, 0x0300, pci_subsys_1057_5600_1668_0300, 0}; +#undef pci_ss_info_1668_0300 +#define pci_ss_info_1668_0300 pci_ss_info_1057_5600_1668_0300 +static const pciSubsystemInfo pci_ss_info_1057_5600_1668_0302 = + {0x1668, 0x0302, pci_subsys_1057_5600_1668_0302, 0}; +#undef pci_ss_info_1668_0302 +#define pci_ss_info_1668_0302 pci_ss_info_1057_5600_1668_0302 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_105a_0d30_105a_4d33 = + {0x105a, 0x4d33, pci_subsys_105a_0d30_105a_4d33, 0}; +#undef pci_ss_info_105a_4d33 +#define pci_ss_info_105a_4d33 pci_ss_info_105a_0d30_105a_4d33 +static const pciSubsystemInfo pci_ss_info_105a_0d38_105a_4d39 = + {0x105a, 0x4d39, pci_subsys_105a_0d38_105a_4d39, 0}; +#undef pci_ss_info_105a_4d39 +#define pci_ss_info_105a_4d39 pci_ss_info_105a_0d38_105a_4d39 +#endif +static const pciSubsystemInfo pci_ss_info_105a_3319_8086_3427 = + {0x8086, 0x3427, pci_subsys_105a_3319_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_105a_3319_8086_3427 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_105a_3373_1043_80f5 = + {0x1043, 0x80f5, pci_subsys_105a_3373_1043_80f5, 0}; +#undef pci_ss_info_1043_80f5 +#define pci_ss_info_1043_80f5 pci_ss_info_105a_3373_1043_80f5 +static const pciSubsystemInfo pci_ss_info_105a_3373_1462_702e = + {0x1462, 0x702e, pci_subsys_105a_3373_1462_702e, 0}; +#undef pci_ss_info_1462_702e +#define pci_ss_info_1462_702e pci_ss_info_105a_3373_1462_702e +static const pciSubsystemInfo pci_ss_info_105a_3376_1043_809e = + {0x1043, 0x809e, pci_subsys_105a_3376_1043_809e, 0}; +#undef pci_ss_info_1043_809e +#define pci_ss_info_1043_809e pci_ss_info_105a_3376_1043_809e +static const pciSubsystemInfo pci_ss_info_105a_4d30_105a_4d33 = + {0x105a, 0x4d33, pci_subsys_105a_4d30_105a_4d33, 0}; +#undef pci_ss_info_105a_4d33 +#define pci_ss_info_105a_4d33 pci_ss_info_105a_4d30_105a_4d33 +static const pciSubsystemInfo pci_ss_info_105a_4d30_105a_4d39 = + {0x105a, 0x4d39, pci_subsys_105a_4d30_105a_4d39, 0}; +#undef pci_ss_info_105a_4d39 +#define pci_ss_info_105a_4d39 pci_ss_info_105a_4d30_105a_4d39 +static const pciSubsystemInfo pci_ss_info_105a_4d33_105a_4d33 = + {0x105a, 0x4d33, pci_subsys_105a_4d33_105a_4d33, 0}; +#undef pci_ss_info_105a_4d33 +#define pci_ss_info_105a_4d33 pci_ss_info_105a_4d33_105a_4d33 +static const pciSubsystemInfo pci_ss_info_105a_4d38_105a_4d30 = + {0x105a, 0x4d30, pci_subsys_105a_4d38_105a_4d30, 0}; +#undef pci_ss_info_105a_4d30 +#define pci_ss_info_105a_4d30 pci_ss_info_105a_4d38_105a_4d30 +static const pciSubsystemInfo pci_ss_info_105a_4d38_105a_4d33 = + {0x105a, 0x4d33, pci_subsys_105a_4d38_105a_4d33, 0}; +#undef pci_ss_info_105a_4d33 +#define pci_ss_info_105a_4d33 pci_ss_info_105a_4d38_105a_4d33 +static const pciSubsystemInfo pci_ss_info_105a_4d38_105a_4d39 = + {0x105a, 0x4d39, pci_subsys_105a_4d38_105a_4d39, 0}; +#undef pci_ss_info_105a_4d39 +#define pci_ss_info_105a_4d39 pci_ss_info_105a_4d38_105a_4d39 +static const pciSubsystemInfo pci_ss_info_105a_4d68_105a_4d68 = + {0x105a, 0x4d68, pci_subsys_105a_4d68_105a_4d68, 0}; +#undef pci_ss_info_105a_4d68 +#define pci_ss_info_105a_4d68 pci_ss_info_105a_4d68_105a_4d68 +static const pciSubsystemInfo pci_ss_info_105a_4d69_105a_4d68 = + {0x105a, 0x4d68, pci_subsys_105a_4d69_105a_4d68, 0}; +#undef pci_ss_info_105a_4d68 +#define pci_ss_info_105a_4d68 pci_ss_info_105a_4d69_105a_4d68 +static const pciSubsystemInfo pci_ss_info_105a_5275_1043_807e = + {0x1043, 0x807e, pci_subsys_105a_5275_1043_807e, 0}; +#undef pci_ss_info_1043_807e +#define pci_ss_info_1043_807e pci_ss_info_105a_5275_1043_807e +static const pciSubsystemInfo pci_ss_info_105a_5275_105a_0275 = + {0x105a, 0x0275, pci_subsys_105a_5275_105a_0275, 0}; +#undef pci_ss_info_105a_0275 +#define pci_ss_info_105a_0275 pci_ss_info_105a_5275_105a_0275 +static const pciSubsystemInfo pci_ss_info_105a_5275_105a_1275 = + {0x105a, 0x1275, pci_subsys_105a_5275_105a_1275, 0}; +#undef pci_ss_info_105a_1275 +#define pci_ss_info_105a_1275 pci_ss_info_105a_5275_105a_1275 +static const pciSubsystemInfo pci_ss_info_105a_5275_1458_b001 = + {0x1458, 0xb001, pci_subsys_105a_5275_1458_b001, 0}; +#undef pci_ss_info_1458_b001 +#define pci_ss_info_1458_b001 pci_ss_info_105a_5275_1458_b001 +static const pciSubsystemInfo pci_ss_info_105a_6268_105a_4d68 = + {0x105a, 0x4d68, pci_subsys_105a_6268_105a_4d68, 0}; +#undef pci_ss_info_105a_4d68 +#define pci_ss_info_105a_4d68 pci_ss_info_105a_6268_105a_4d68 +static const pciSubsystemInfo pci_ss_info_105a_6269_105a_6269 = + {0x105a, 0x6269, pci_subsys_105a_6269_105a_6269, 0}; +#undef pci_ss_info_105a_6269 +#define pci_ss_info_105a_6269 pci_ss_info_105a_6269_105a_6269 +#endif +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0000 = + {0x105d, 0x0000, pci_subsys_105d_2339_105d_0000, 0}; +#undef pci_ss_info_105d_0000 +#define pci_ss_info_105d_0000 pci_ss_info_105d_2339_105d_0000 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0001 = + {0x105d, 0x0001, pci_subsys_105d_2339_105d_0001, 0}; +#undef pci_ss_info_105d_0001 +#define pci_ss_info_105d_0001 pci_ss_info_105d_2339_105d_0001 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0002 = + {0x105d, 0x0002, pci_subsys_105d_2339_105d_0002, 0}; +#undef pci_ss_info_105d_0002 +#define pci_ss_info_105d_0002 pci_ss_info_105d_2339_105d_0002 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0003 = + {0x105d, 0x0003, pci_subsys_105d_2339_105d_0003, 0}; +#undef pci_ss_info_105d_0003 +#define pci_ss_info_105d_0003 pci_ss_info_105d_2339_105d_0003 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0004 = + {0x105d, 0x0004, pci_subsys_105d_2339_105d_0004, 0}; +#undef pci_ss_info_105d_0004 +#define pci_ss_info_105d_0004 pci_ss_info_105d_2339_105d_0004 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0005 = + {0x105d, 0x0005, pci_subsys_105d_2339_105d_0005, 0}; +#undef pci_ss_info_105d_0005 +#define pci_ss_info_105d_0005 pci_ss_info_105d_2339_105d_0005 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0006 = + {0x105d, 0x0006, pci_subsys_105d_2339_105d_0006, 0}; +#undef pci_ss_info_105d_0006 +#define pci_ss_info_105d_0006 pci_ss_info_105d_2339_105d_0006 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0007 = + {0x105d, 0x0007, pci_subsys_105d_2339_105d_0007, 0}; +#undef pci_ss_info_105d_0007 +#define pci_ss_info_105d_0007 pci_ss_info_105d_2339_105d_0007 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0008 = + {0x105d, 0x0008, pci_subsys_105d_2339_105d_0008, 0}; +#undef pci_ss_info_105d_0008 +#define pci_ss_info_105d_0008 pci_ss_info_105d_2339_105d_0008 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_0009 = + {0x105d, 0x0009, pci_subsys_105d_2339_105d_0009, 0}; +#undef pci_ss_info_105d_0009 +#define pci_ss_info_105d_0009 pci_ss_info_105d_2339_105d_0009 +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_000a = + {0x105d, 0x000a, pci_subsys_105d_2339_105d_000a, 0}; +#undef pci_ss_info_105d_000a +#define pci_ss_info_105d_000a pci_ss_info_105d_2339_105d_000a +static const pciSubsystemInfo pci_ss_info_105d_2339_105d_000b = + {0x105d, 0x000b, pci_subsys_105d_2339_105d_000b, 0}; +#undef pci_ss_info_105d_000b +#define pci_ss_info_105d_000b pci_ss_info_105d_2339_105d_000b +static const pciSubsystemInfo pci_ss_info_105d_2339_11a4_000a = + {0x11a4, 0x000a, pci_subsys_105d_2339_11a4_000a, 0}; +#undef pci_ss_info_11a4_000a +#define pci_ss_info_11a4_000a pci_ss_info_105d_2339_11a4_000a +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0000 = + {0x13cc, 0x0000, pci_subsys_105d_2339_13cc_0000, 0}; +#undef pci_ss_info_13cc_0000 +#define pci_ss_info_13cc_0000 pci_ss_info_105d_2339_13cc_0000 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0004 = + {0x13cc, 0x0004, pci_subsys_105d_2339_13cc_0004, 0}; +#undef pci_ss_info_13cc_0004 +#define pci_ss_info_13cc_0004 pci_ss_info_105d_2339_13cc_0004 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0005 = + {0x13cc, 0x0005, pci_subsys_105d_2339_13cc_0005, 0}; +#undef pci_ss_info_13cc_0005 +#define pci_ss_info_13cc_0005 pci_ss_info_105d_2339_13cc_0005 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0006 = + {0x13cc, 0x0006, pci_subsys_105d_2339_13cc_0006, 0}; +#undef pci_ss_info_13cc_0006 +#define pci_ss_info_13cc_0006 pci_ss_info_105d_2339_13cc_0006 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0008 = + {0x13cc, 0x0008, pci_subsys_105d_2339_13cc_0008, 0}; +#undef pci_ss_info_13cc_0008 +#define pci_ss_info_13cc_0008 pci_ss_info_105d_2339_13cc_0008 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_0009 = + {0x13cc, 0x0009, pci_subsys_105d_2339_13cc_0009, 0}; +#undef pci_ss_info_13cc_0009 +#define pci_ss_info_13cc_0009 pci_ss_info_105d_2339_13cc_0009 +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_000a = + {0x13cc, 0x000a, pci_subsys_105d_2339_13cc_000a, 0}; +#undef pci_ss_info_13cc_000a +#define pci_ss_info_13cc_000a pci_ss_info_105d_2339_13cc_000a +static const pciSubsystemInfo pci_ss_info_105d_2339_13cc_000c = + {0x13cc, 0x000c, pci_subsys_105d_2339_13cc_000c, 0}; +#undef pci_ss_info_13cc_000c +#define pci_ss_info_13cc_000c pci_ss_info_105d_2339_13cc_000c +static const pciSubsystemInfo pci_ss_info_105d_493d_11a4_000a = + {0x11a4, 0x000a, pci_subsys_105d_493d_11a4_000a, 0}; +#undef pci_ss_info_11a4_000a +#define pci_ss_info_11a4_000a pci_ss_info_105d_493d_11a4_000a +static const pciSubsystemInfo pci_ss_info_105d_493d_11a4_000b = + {0x11a4, 0x000b, pci_subsys_105d_493d_11a4_000b, 0}; +#undef pci_ss_info_11a4_000b +#define pci_ss_info_11a4_000b pci_ss_info_105d_493d_11a4_000b +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0002 = + {0x13cc, 0x0002, pci_subsys_105d_493d_13cc_0002, 0}; +#undef pci_ss_info_13cc_0002 +#define pci_ss_info_13cc_0002 pci_ss_info_105d_493d_13cc_0002 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0003 = + {0x13cc, 0x0003, pci_subsys_105d_493d_13cc_0003, 0}; +#undef pci_ss_info_13cc_0003 +#define pci_ss_info_13cc_0003 pci_ss_info_105d_493d_13cc_0003 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0007 = + {0x13cc, 0x0007, pci_subsys_105d_493d_13cc_0007, 0}; +#undef pci_ss_info_13cc_0007 +#define pci_ss_info_13cc_0007 pci_ss_info_105d_493d_13cc_0007 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0008 = + {0x13cc, 0x0008, pci_subsys_105d_493d_13cc_0008, 0}; +#undef pci_ss_info_13cc_0008 +#define pci_ss_info_13cc_0008 pci_ss_info_105d_493d_13cc_0008 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_0009 = + {0x13cc, 0x0009, pci_subsys_105d_493d_13cc_0009, 0}; +#undef pci_ss_info_13cc_0009 +#define pci_ss_info_13cc_0009 pci_ss_info_105d_493d_13cc_0009 +static const pciSubsystemInfo pci_ss_info_105d_493d_13cc_000a = + {0x13cc, 0x000a, pci_subsys_105d_493d_13cc_000a, 0}; +#undef pci_ss_info_13cc_000a +#define pci_ss_info_13cc_000a pci_ss_info_105d_493d_13cc_000a +static const pciSubsystemInfo pci_ss_info_105d_5348_105d_0037 = + {0x105d, 0x0037, pci_subsys_105d_5348_105d_0037, 0}; +#undef pci_ss_info_105d_0037 +#define pci_ss_info_105d_0037 pci_ss_info_105d_5348_105d_0037 +static const pciSubsystemInfo pci_ss_info_105d_5348_11a4_0028 = + {0x11a4, 0x0028, pci_subsys_105d_5348_11a4_0028, 0}; +#undef pci_ss_info_11a4_0028 +#define pci_ss_info_11a4_0028 pci_ss_info_105d_5348_11a4_0028 +static const pciSubsystemInfo pci_ss_info_105d_5348_11a4_0038 = + {0x11a4, 0x0038, pci_subsys_105d_5348_11a4_0038, 0}; +#undef pci_ss_info_11a4_0038 +#define pci_ss_info_11a4_0038 pci_ss_info_105d_5348_11a4_0038 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1069_0050_1069_0050 = + {0x1069, 0x0050, pci_subsys_1069_0050_1069_0050, 0}; +#undef pci_ss_info_1069_0050 +#define pci_ss_info_1069_0050 pci_ss_info_1069_0050_1069_0050 +static const pciSubsystemInfo pci_ss_info_1069_0050_1069_0052 = + {0x1069, 0x0052, pci_subsys_1069_0050_1069_0052, 0}; +#undef pci_ss_info_1069_0052 +#define pci_ss_info_1069_0052 pci_ss_info_1069_0050_1069_0052 +static const pciSubsystemInfo pci_ss_info_1069_0050_1069_0054 = + {0x1069, 0x0054, pci_subsys_1069_0050_1069_0054, 0}; +#undef pci_ss_info_1069_0054 +#define pci_ss_info_1069_0054 pci_ss_info_1069_0050_1069_0054 +static const pciSubsystemInfo pci_ss_info_1069_b166_1014_0242 = + {0x1014, 0x0242, pci_subsys_1069_b166_1014_0242, 0}; +#undef pci_ss_info_1014_0242 +#define pci_ss_info_1014_0242 pci_ss_info_1069_b166_1014_0242 +static const pciSubsystemInfo pci_ss_info_1069_b166_1014_0266 = + {0x1014, 0x0266, pci_subsys_1069_b166_1014_0266, 0}; +#undef pci_ss_info_1014_0266 +#define pci_ss_info_1014_0266 pci_ss_info_1069_b166_1014_0266 +static const pciSubsystemInfo pci_ss_info_1069_b166_1014_0278 = + {0x1014, 0x0278, pci_subsys_1069_b166_1014_0278, 0}; +#undef pci_ss_info_1014_0278 +#define pci_ss_info_1014_0278 pci_ss_info_1069_b166_1014_0278 +static const pciSubsystemInfo pci_ss_info_1069_b166_1014_02d3 = + {0x1014, 0x02d3, pci_subsys_1069_b166_1014_02d3, 0}; +#undef pci_ss_info_1014_02d3 +#define pci_ss_info_1014_02d3 pci_ss_info_1069_b166_1014_02d3 +static const pciSubsystemInfo pci_ss_info_1069_b166_1014_02d4 = + {0x1014, 0x02d4, pci_subsys_1069_b166_1014_02d4, 0}; +#undef pci_ss_info_1014_02d4 +#define pci_ss_info_1014_02d4 pci_ss_info_1069_b166_1014_02d4 +static const pciSubsystemInfo pci_ss_info_1069_b166_1069_0200 = + {0x1069, 0x0200, pci_subsys_1069_b166_1069_0200, 0}; +#undef pci_ss_info_1069_0200 +#define pci_ss_info_1069_0200 pci_ss_info_1069_b166_1069_0200 +static const pciSubsystemInfo pci_ss_info_1069_b166_1069_0202 = + {0x1069, 0x0202, pci_subsys_1069_b166_1069_0202, 0}; +#undef pci_ss_info_1069_0202 +#define pci_ss_info_1069_0202 pci_ss_info_1069_b166_1069_0202 +static const pciSubsystemInfo pci_ss_info_1069_b166_1069_0204 = + {0x1069, 0x0204, pci_subsys_1069_b166_1069_0204, 0}; +#undef pci_ss_info_1069_0204 +#define pci_ss_info_1069_0204 pci_ss_info_1069_b166_1069_0204 +static const pciSubsystemInfo pci_ss_info_1069_b166_1069_0206 = + {0x1069, 0x0206, pci_subsys_1069_b166_1069_0206, 0}; +#undef pci_ss_info_1069_0206 +#define pci_ss_info_1069_0206 pci_ss_info_1069_b166_1069_0206 +static const pciSubsystemInfo pci_ss_info_1069_ba56_1069_0030 = + {0x1069, 0x0030, pci_subsys_1069_ba56_1069_0030, 0}; +#undef pci_ss_info_1069_0030 +#define pci_ss_info_1069_0030 pci_ss_info_1069_ba56_1069_0030 +static const pciSubsystemInfo pci_ss_info_1069_ba56_1069_0040 = + {0x1069, 0x0040, pci_subsys_1069_ba56_1069_0040, 0}; +#undef pci_ss_info_1069_0040 +#define pci_ss_info_1069_0040 pci_ss_info_1069_ba56_1069_0040 +static const pciSubsystemInfo pci_ss_info_1069_ba57_1069_0072 = + {0x1069, 0x0072, pci_subsys_1069_ba57_1069_0072, 0}; +#undef pci_ss_info_1069_0072 +#define pci_ss_info_1069_0072 pci_ss_info_1069_ba57_1069_0072 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_106b_0031_106b_5811 = + {0x106b, 0x5811, pci_subsys_106b_0031_106b_5811, 0}; +#undef pci_ss_info_106b_5811 +#define pci_ss_info_106b_5811 pci_ss_info_106b_0031_106b_5811 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1073_0004_1073_0004 = + {0x1073, 0x0004, pci_subsys_1073_0004_1073_0004, 0}; +#undef pci_ss_info_1073_0004 +#define pci_ss_info_1073_0004 pci_ss_info_1073_0004_1073_0004 +static const pciSubsystemInfo pci_ss_info_1073_0005_1073_0005 = + {0x1073, 0x0005, pci_subsys_1073_0005_1073_0005, 0}; +#undef pci_ss_info_1073_0005 +#define pci_ss_info_1073_0005 pci_ss_info_1073_0005_1073_0005 +static const pciSubsystemInfo pci_ss_info_1073_0008_1073_0008 = + {0x1073, 0x0008, pci_subsys_1073_0008_1073_0008, 0}; +#undef pci_ss_info_1073_0008 +#define pci_ss_info_1073_0008 pci_ss_info_1073_0008_1073_0008 +static const pciSubsystemInfo pci_ss_info_1073_000a_1073_0004 = + {0x1073, 0x0004, pci_subsys_1073_000a_1073_0004, 0}; +#undef pci_ss_info_1073_0004 +#define pci_ss_info_1073_0004 pci_ss_info_1073_000a_1073_0004 +static const pciSubsystemInfo pci_ss_info_1073_000a_1073_000a = + {0x1073, 0x000a, pci_subsys_1073_000a_1073_000a, 0}; +#undef pci_ss_info_1073_000a +#define pci_ss_info_1073_000a pci_ss_info_1073_000a_1073_000a +static const pciSubsystemInfo pci_ss_info_1073_000c_107a_000c = + {0x107a, 0x000c, pci_subsys_1073_000c_107a_000c, 0}; +#undef pci_ss_info_107a_000c +#define pci_ss_info_107a_000c pci_ss_info_1073_000c_107a_000c +static const pciSubsystemInfo pci_ss_info_1073_000d_1073_000d = + {0x1073, 0x000d, pci_subsys_1073_000d_1073_000d, 0}; +#undef pci_ss_info_1073_000d +#define pci_ss_info_1073_000d pci_ss_info_1073_000d_1073_000d +static const pciSubsystemInfo pci_ss_info_1073_0010_1073_0006 = + {0x1073, 0x0006, pci_subsys_1073_0010_1073_0006, 0}; +#undef pci_ss_info_1073_0006 +#define pci_ss_info_1073_0006 pci_ss_info_1073_0010_1073_0006 +static const pciSubsystemInfo pci_ss_info_1073_0010_1073_0010 = + {0x1073, 0x0010, pci_subsys_1073_0010_1073_0010, 0}; +#undef pci_ss_info_1073_0010 +#define pci_ss_info_1073_0010 pci_ss_info_1073_0010_1073_0010 +static const pciSubsystemInfo pci_ss_info_1073_0012_1073_0012 = + {0x1073, 0x0012, pci_subsys_1073_0012_1073_0012, 0}; +#undef pci_ss_info_1073_0012 +#define pci_ss_info_1073_0012 pci_ss_info_1073_0012_1073_0012 +static const pciSubsystemInfo pci_ss_info_1073_2000_1073_2000 = + {0x1073, 0x2000, pci_subsys_1073_2000_1073_2000, 0}; +#undef pci_ss_info_1073_2000 +#define pci_ss_info_1073_2000 pci_ss_info_1073_2000_1073_2000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1077_1216_101e_8471 = + {0x101e, 0x8471, pci_subsys_1077_1216_101e_8471, 0}; +#undef pci_ss_info_101e_8471 +#define pci_ss_info_101e_8471 pci_ss_info_1077_1216_101e_8471 +static const pciSubsystemInfo pci_ss_info_1077_1216_101e_8493 = + {0x101e, 0x8493, pci_subsys_1077_1216_101e_8493, 0}; +#undef pci_ss_info_101e_8493 +#define pci_ss_info_101e_8493 pci_ss_info_1077_1216_101e_8493 +static const pciSubsystemInfo pci_ss_info_1077_2100_1077_0001 = + {0x1077, 0x0001, pci_subsys_1077_2100_1077_0001, 0}; +#undef pci_ss_info_1077_0001 +#define pci_ss_info_1077_0001 pci_ss_info_1077_2100_1077_0001 +static const pciSubsystemInfo pci_ss_info_1077_2200_1077_0002 = + {0x1077, 0x0002, pci_subsys_1077_2200_1077_0002, 0}; +#undef pci_ss_info_1077_0002 +#define pci_ss_info_1077_0002 pci_ss_info_1077_2200_1077_0002 +#endif +static const pciSubsystemInfo pci_ss_info_1077_2312_103c_0131 = + {0x103c, 0x0131, pci_subsys_1077_2312_103c_0131, 0}; +#undef pci_ss_info_103c_0131 +#define pci_ss_info_103c_0131 pci_ss_info_1077_2312_103c_0131 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1077_2312_103c_12ba = + {0x103c, 0x12ba, pci_subsys_1077_2312_103c_12ba, 0}; +#undef pci_ss_info_103c_12ba +#define pci_ss_info_103c_12ba pci_ss_info_1077_2312_103c_12ba +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1077_2422_103c_12d7 = + {0x103c, 0x12d7, pci_subsys_1077_2422_103c_12d7, 0}; +#undef pci_ss_info_103c_12d7 +#define pci_ss_info_103c_12d7 pci_ss_info_1077_2422_103c_12d7 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1077_2422_103c_12dd = + {0x103c, 0x12dd, pci_subsys_1077_2422_103c_12dd, 0}; +#undef pci_ss_info_103c_12dd +#define pci_ss_info_103c_12dd pci_ss_info_1077_2422_103c_12dd +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_108d_0004_108d_0004 = + {0x108d, 0x0004, pci_subsys_108d_0004_108d_0004, 0}; +#undef pci_ss_info_108d_0004 +#define pci_ss_info_108d_0004 pci_ss_info_108d_0004_108d_0004 +static const pciSubsystemInfo pci_ss_info_108d_0007_108d_0007 = + {0x108d, 0x0007, pci_subsys_108d_0007_108d_0007, 0}; +#undef pci_ss_info_108d_0007 +#define pci_ss_info_108d_0007 pci_ss_info_108d_0007_108d_0007 +static const pciSubsystemInfo pci_ss_info_108d_0008_108d_0008 = + {0x108d, 0x0008, pci_subsys_108d_0008_108d_0008, 0}; +#undef pci_ss_info_108d_0008 +#define pci_ss_info_108d_0008 pci_ss_info_108d_0008_108d_0008 +static const pciSubsystemInfo pci_ss_info_108d_0019_108d_0016 = + {0x108d, 0x0016, pci_subsys_108d_0019_108d_0016, 0}; +#undef pci_ss_info_108d_0016 +#define pci_ss_info_108d_0016 pci_ss_info_108d_0019_108d_0016 +static const pciSubsystemInfo pci_ss_info_108d_0019_108d_0017 = + {0x108d, 0x0017, pci_subsys_108d_0019_108d_0017, 0}; +#undef pci_ss_info_108d_0017 +#define pci_ss_info_108d_0017 pci_ss_info_108d_0019_108d_0017 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1095_0648_1043_8025 = + {0x1043, 0x8025, pci_subsys_1095_0648_1043_8025, 0}; +#undef pci_ss_info_1043_8025 +#define pci_ss_info_1043_8025 pci_ss_info_1095_0648_1043_8025 +#endif +static const pciSubsystemInfo pci_ss_info_1095_0649_0e11_005d = + {0x0e11, 0x005d, pci_subsys_1095_0649_0e11_005d, 0}; +#undef pci_ss_info_0e11_005d +#define pci_ss_info_0e11_005d pci_ss_info_1095_0649_0e11_005d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1095_0649_0e11_007e = + {0x0e11, 0x007e, pci_subsys_1095_0649_0e11_007e, 0}; +#undef pci_ss_info_0e11_007e +#define pci_ss_info_0e11_007e pci_ss_info_1095_0649_0e11_007e +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1095_0649_101e_0649 = + {0x101e, 0x0649, pci_subsys_1095_0649_101e_0649, 0}; +#undef pci_ss_info_101e_0649 +#define pci_ss_info_101e_0649 pci_ss_info_1095_0649_101e_0649 +static const pciSubsystemInfo pci_ss_info_1095_0670_1095_0670 = + {0x1095, 0x0670, pci_subsys_1095_0670_1095_0670, 0}; +#undef pci_ss_info_1095_0670 +#define pci_ss_info_1095_0670 pci_ss_info_1095_0670_1095_0670 +static const pciSubsystemInfo pci_ss_info_1095_0680_1095_3680 = + {0x1095, 0x3680, pci_subsys_1095_0680_1095_3680, 0}; +#undef pci_ss_info_1095_3680 +#define pci_ss_info_1095_3680 pci_ss_info_1095_0680_1095_3680 +static const pciSubsystemInfo pci_ss_info_1095_3112_1095_3112 = + {0x1095, 0x3112, pci_subsys_1095_3112_1095_3112, 0}; +#undef pci_ss_info_1095_3112 +#define pci_ss_info_1095_3112 pci_ss_info_1095_3112_1095_3112 +static const pciSubsystemInfo pci_ss_info_1095_3112_1095_6112 = + {0x1095, 0x6112, pci_subsys_1095_3112_1095_6112, 0}; +#undef pci_ss_info_1095_6112 +#define pci_ss_info_1095_6112 pci_ss_info_1095_3112_1095_6112 +static const pciSubsystemInfo pci_ss_info_1095_3112_9005_0250 = + {0x9005, 0x0250, pci_subsys_1095_3112_9005_0250, 0}; +#undef pci_ss_info_9005_0250 +#define pci_ss_info_9005_0250 pci_ss_info_1095_3112_9005_0250 +static const pciSubsystemInfo pci_ss_info_1095_3114_1095_3114 = + {0x1095, 0x3114, pci_subsys_1095_3114_1095_3114, 0}; +#undef pci_ss_info_1095_3114 +#define pci_ss_info_1095_3114 pci_ss_info_1095_3114_1095_3114 +static const pciSubsystemInfo pci_ss_info_1095_3114_1095_6114 = + {0x1095, 0x6114, pci_subsys_1095_3114_1095_6114, 0}; +#undef pci_ss_info_1095_6114 +#define pci_ss_info_1095_6114 pci_ss_info_1095_3114_1095_6114 +static const pciSubsystemInfo pci_ss_info_1095_3124_1095_3124 = + {0x1095, 0x3124, pci_subsys_1095_3124_1095_3124, 0}; +#undef pci_ss_info_1095_3124 +#define pci_ss_info_1095_3124 pci_ss_info_1095_3124_1095_3124 +static const pciSubsystemInfo pci_ss_info_1095_3512_1095_3512 = + {0x1095, 0x3512, pci_subsys_1095_3512_1095_3512, 0}; +#undef pci_ss_info_1095_3512 +#define pci_ss_info_1095_3512 pci_ss_info_1095_3512_1095_3512 +static const pciSubsystemInfo pci_ss_info_1095_3512_1095_6512 = + {0x1095, 0x6512, pci_subsys_1095_3512_1095_6512, 0}; +#undef pci_ss_info_1095_6512 +#define pci_ss_info_1095_6512 pci_ss_info_1095_3512_1095_6512 +#endif +static const pciSubsystemInfo pci_ss_info_109e_0369_1002_0001 = + {0x1002, 0x0001, pci_subsys_109e_0369_1002_0001, 0}; +#undef pci_ss_info_1002_0001 +#define pci_ss_info_1002_0001 pci_ss_info_109e_0369_1002_0001 +static const pciSubsystemInfo pci_ss_info_109e_0369_1002_0003 = + {0x1002, 0x0003, pci_subsys_109e_0369_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_109e_0369_1002_0003 +static const pciSubsystemInfo pci_ss_info_109e_036c_13e9_0070 = + {0x13e9, 0x0070, pci_subsys_109e_036c_13e9_0070, 0}; +#undef pci_ss_info_13e9_0070 +#define pci_ss_info_13e9_0070 pci_ss_info_109e_036c_13e9_0070 +static const pciSubsystemInfo pci_ss_info_109e_036e_0070_13eb = + {0x0070, 0x13eb, pci_subsys_109e_036e_0070_13eb, 0}; +#undef pci_ss_info_0070_13eb +#define pci_ss_info_0070_13eb pci_ss_info_109e_036e_0070_13eb +static const pciSubsystemInfo pci_ss_info_109e_036e_0070_ff01 = + {0x0070, 0xff01, pci_subsys_109e_036e_0070_ff01, 0}; +#undef pci_ss_info_0070_ff01 +#define pci_ss_info_0070_ff01 pci_ss_info_109e_036e_0070_ff01 +static const pciSubsystemInfo pci_ss_info_109e_036e_0071_0101 = + {0x0071, 0x0101, pci_subsys_109e_036e_0071_0101, 0}; +#undef pci_ss_info_0071_0101 +#define pci_ss_info_0071_0101 pci_ss_info_109e_036e_0071_0101 +static const pciSubsystemInfo pci_ss_info_109e_036e_107d_6606 = + {0x107d, 0x6606, pci_subsys_109e_036e_107d_6606, 0}; +#undef pci_ss_info_107d_6606 +#define pci_ss_info_107d_6606 pci_ss_info_109e_036e_107d_6606 +static const pciSubsystemInfo pci_ss_info_109e_036e_11bd_0012 = + {0x11bd, 0x0012, pci_subsys_109e_036e_11bd_0012, 0}; +#undef pci_ss_info_11bd_0012 +#define pci_ss_info_11bd_0012 pci_ss_info_109e_036e_11bd_0012 +static const pciSubsystemInfo pci_ss_info_109e_036e_11bd_001c = + {0x11bd, 0x001c, pci_subsys_109e_036e_11bd_001c, 0}; +#undef pci_ss_info_11bd_001c +#define pci_ss_info_11bd_001c pci_ss_info_109e_036e_11bd_001c +static const pciSubsystemInfo pci_ss_info_109e_036e_127a_0001 = + {0x127a, 0x0001, pci_subsys_109e_036e_127a_0001, 0}; +#undef pci_ss_info_127a_0001 +#define pci_ss_info_127a_0001 pci_ss_info_109e_036e_127a_0001 +static const pciSubsystemInfo pci_ss_info_109e_036e_127a_0002 = + {0x127a, 0x0002, pci_subsys_109e_036e_127a_0002, 0}; +#undef pci_ss_info_127a_0002 +#define pci_ss_info_127a_0002 pci_ss_info_109e_036e_127a_0002 +static const pciSubsystemInfo pci_ss_info_109e_036e_127a_0003 = + {0x127a, 0x0003, pci_subsys_109e_036e_127a_0003, 0}; +#undef pci_ss_info_127a_0003 +#define pci_ss_info_127a_0003 pci_ss_info_109e_036e_127a_0003 +static const pciSubsystemInfo pci_ss_info_109e_036e_127a_0048 = + {0x127a, 0x0048, pci_subsys_109e_036e_127a_0048, 0}; +#undef pci_ss_info_127a_0048 +#define pci_ss_info_127a_0048 pci_ss_info_109e_036e_127a_0048 +static const pciSubsystemInfo pci_ss_info_109e_036e_144f_3000 = + {0x144f, 0x3000, pci_subsys_109e_036e_144f_3000, 0}; +#undef pci_ss_info_144f_3000 +#define pci_ss_info_144f_3000 pci_ss_info_109e_036e_144f_3000 +static const pciSubsystemInfo pci_ss_info_109e_036e_1461_0002 = + {0x1461, 0x0002, pci_subsys_109e_036e_1461_0002, 0}; +#undef pci_ss_info_1461_0002 +#define pci_ss_info_1461_0002 pci_ss_info_109e_036e_1461_0002 +static const pciSubsystemInfo pci_ss_info_109e_036e_1461_0003 = + {0x1461, 0x0003, pci_subsys_109e_036e_1461_0003, 0}; +#undef pci_ss_info_1461_0003 +#define pci_ss_info_1461_0003 pci_ss_info_109e_036e_1461_0003 +static const pciSubsystemInfo pci_ss_info_109e_036e_1461_0004 = + {0x1461, 0x0004, pci_subsys_109e_036e_1461_0004, 0}; +#undef pci_ss_info_1461_0004 +#define pci_ss_info_1461_0004 pci_ss_info_109e_036e_1461_0004 +static const pciSubsystemInfo pci_ss_info_109e_036e_1461_0761 = + {0x1461, 0x0761, pci_subsys_109e_036e_1461_0761, 0}; +#undef pci_ss_info_1461_0761 +#define pci_ss_info_1461_0761 pci_ss_info_109e_036e_1461_0761 +static const pciSubsystemInfo pci_ss_info_109e_036e_1461_0771 = + {0x1461, 0x0771, pci_subsys_109e_036e_1461_0771, 0}; +#undef pci_ss_info_1461_0771 +#define pci_ss_info_1461_0771 pci_ss_info_109e_036e_1461_0771 +static const pciSubsystemInfo pci_ss_info_109e_036e_14f1_0001 = + {0x14f1, 0x0001, pci_subsys_109e_036e_14f1_0001, 0}; +#undef pci_ss_info_14f1_0001 +#define pci_ss_info_14f1_0001 pci_ss_info_109e_036e_14f1_0001 +static const pciSubsystemInfo pci_ss_info_109e_036e_14f1_0002 = + {0x14f1, 0x0002, pci_subsys_109e_036e_14f1_0002, 0}; +#undef pci_ss_info_14f1_0002 +#define pci_ss_info_14f1_0002 pci_ss_info_109e_036e_14f1_0002 +static const pciSubsystemInfo pci_ss_info_109e_036e_14f1_0003 = + {0x14f1, 0x0003, pci_subsys_109e_036e_14f1_0003, 0}; +#undef pci_ss_info_14f1_0003 +#define pci_ss_info_14f1_0003 pci_ss_info_109e_036e_14f1_0003 +static const pciSubsystemInfo pci_ss_info_109e_036e_14f1_0048 = + {0x14f1, 0x0048, pci_subsys_109e_036e_14f1_0048, 0}; +#undef pci_ss_info_14f1_0048 +#define pci_ss_info_14f1_0048 pci_ss_info_109e_036e_14f1_0048 +static const pciSubsystemInfo pci_ss_info_109e_036e_1822_0001 = + {0x1822, 0x0001, pci_subsys_109e_036e_1822_0001, 0}; +#undef pci_ss_info_1822_0001 +#define pci_ss_info_1822_0001 pci_ss_info_109e_036e_1822_0001 +static const pciSubsystemInfo pci_ss_info_109e_036e_1851_1850 = + {0x1851, 0x1850, pci_subsys_109e_036e_1851_1850, 0}; +#undef pci_ss_info_1851_1850 +#define pci_ss_info_1851_1850 pci_ss_info_109e_036e_1851_1850 +static const pciSubsystemInfo pci_ss_info_109e_036e_1851_1851 = + {0x1851, 0x1851, pci_subsys_109e_036e_1851_1851, 0}; +#undef pci_ss_info_1851_1851 +#define pci_ss_info_1851_1851 pci_ss_info_109e_036e_1851_1851 +static const pciSubsystemInfo pci_ss_info_109e_036e_1852_1852 = + {0x1852, 0x1852, pci_subsys_109e_036e_1852_1852, 0}; +#undef pci_ss_info_1852_1852 +#define pci_ss_info_1852_1852 pci_ss_info_109e_036e_1852_1852 +static const pciSubsystemInfo pci_ss_info_109e_036e_18ac_d500 = + {0x18ac, 0xd500, pci_subsys_109e_036e_18ac_d500, 0}; +#undef pci_ss_info_18ac_d500 +#define pci_ss_info_18ac_d500 pci_ss_info_109e_036e_18ac_d500 +static const pciSubsystemInfo pci_ss_info_109e_036e_270f_fc00 = + {0x270f, 0xfc00, pci_subsys_109e_036e_270f_fc00, 0}; +#undef pci_ss_info_270f_fc00 +#define pci_ss_info_270f_fc00 pci_ss_info_109e_036e_270f_fc00 +static const pciSubsystemInfo pci_ss_info_109e_036e_bd11_1200 = + {0xbd11, 0x1200, pci_subsys_109e_036e_bd11_1200, 0}; +#undef pci_ss_info_bd11_1200 +#define pci_ss_info_bd11_1200 pci_ss_info_109e_036e_bd11_1200 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0044 = + {0x127a, 0x0044, pci_subsys_109e_036f_127a_0044, 0}; +#undef pci_ss_info_127a_0044 +#define pci_ss_info_127a_0044 pci_ss_info_109e_036f_127a_0044 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0122 = + {0x127a, 0x0122, pci_subsys_109e_036f_127a_0122, 0}; +#undef pci_ss_info_127a_0122 +#define pci_ss_info_127a_0122 pci_ss_info_109e_036f_127a_0122 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0144 = + {0x127a, 0x0144, pci_subsys_109e_036f_127a_0144, 0}; +#undef pci_ss_info_127a_0144 +#define pci_ss_info_127a_0144 pci_ss_info_109e_036f_127a_0144 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0222 = + {0x127a, 0x0222, pci_subsys_109e_036f_127a_0222, 0}; +#undef pci_ss_info_127a_0222 +#define pci_ss_info_127a_0222 pci_ss_info_109e_036f_127a_0222 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0244 = + {0x127a, 0x0244, pci_subsys_109e_036f_127a_0244, 0}; +#undef pci_ss_info_127a_0244 +#define pci_ss_info_127a_0244 pci_ss_info_109e_036f_127a_0244 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0322 = + {0x127a, 0x0322, pci_subsys_109e_036f_127a_0322, 0}; +#undef pci_ss_info_127a_0322 +#define pci_ss_info_127a_0322 pci_ss_info_109e_036f_127a_0322 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_0422 = + {0x127a, 0x0422, pci_subsys_109e_036f_127a_0422, 0}; +#undef pci_ss_info_127a_0422 +#define pci_ss_info_127a_0422 pci_ss_info_109e_036f_127a_0422 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1122 = + {0x127a, 0x1122, pci_subsys_109e_036f_127a_1122, 0}; +#undef pci_ss_info_127a_1122 +#define pci_ss_info_127a_1122 pci_ss_info_109e_036f_127a_1122 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1222 = + {0x127a, 0x1222, pci_subsys_109e_036f_127a_1222, 0}; +#undef pci_ss_info_127a_1222 +#define pci_ss_info_127a_1222 pci_ss_info_109e_036f_127a_1222 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1322 = + {0x127a, 0x1322, pci_subsys_109e_036f_127a_1322, 0}; +#undef pci_ss_info_127a_1322 +#define pci_ss_info_127a_1322 pci_ss_info_109e_036f_127a_1322 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1522 = + {0x127a, 0x1522, pci_subsys_109e_036f_127a_1522, 0}; +#undef pci_ss_info_127a_1522 +#define pci_ss_info_127a_1522 pci_ss_info_109e_036f_127a_1522 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1622 = + {0x127a, 0x1622, pci_subsys_109e_036f_127a_1622, 0}; +#undef pci_ss_info_127a_1622 +#define pci_ss_info_127a_1622 pci_ss_info_109e_036f_127a_1622 +static const pciSubsystemInfo pci_ss_info_109e_036f_127a_1722 = + {0x127a, 0x1722, pci_subsys_109e_036f_127a_1722, 0}; +#undef pci_ss_info_127a_1722 +#define pci_ss_info_127a_1722 pci_ss_info_109e_036f_127a_1722 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0044 = + {0x14f1, 0x0044, pci_subsys_109e_036f_14f1_0044, 0}; +#undef pci_ss_info_14f1_0044 +#define pci_ss_info_14f1_0044 pci_ss_info_109e_036f_14f1_0044 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0122 = + {0x14f1, 0x0122, pci_subsys_109e_036f_14f1_0122, 0}; +#undef pci_ss_info_14f1_0122 +#define pci_ss_info_14f1_0122 pci_ss_info_109e_036f_14f1_0122 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0144 = + {0x14f1, 0x0144, pci_subsys_109e_036f_14f1_0144, 0}; +#undef pci_ss_info_14f1_0144 +#define pci_ss_info_14f1_0144 pci_ss_info_109e_036f_14f1_0144 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0222 = + {0x14f1, 0x0222, pci_subsys_109e_036f_14f1_0222, 0}; +#undef pci_ss_info_14f1_0222 +#define pci_ss_info_14f1_0222 pci_ss_info_109e_036f_14f1_0222 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0244 = + {0x14f1, 0x0244, pci_subsys_109e_036f_14f1_0244, 0}; +#undef pci_ss_info_14f1_0244 +#define pci_ss_info_14f1_0244 pci_ss_info_109e_036f_14f1_0244 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0322 = + {0x14f1, 0x0322, pci_subsys_109e_036f_14f1_0322, 0}; +#undef pci_ss_info_14f1_0322 +#define pci_ss_info_14f1_0322 pci_ss_info_109e_036f_14f1_0322 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_0422 = + {0x14f1, 0x0422, pci_subsys_109e_036f_14f1_0422, 0}; +#undef pci_ss_info_14f1_0422 +#define pci_ss_info_14f1_0422 pci_ss_info_109e_036f_14f1_0422 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1122 = + {0x14f1, 0x1122, pci_subsys_109e_036f_14f1_1122, 0}; +#undef pci_ss_info_14f1_1122 +#define pci_ss_info_14f1_1122 pci_ss_info_109e_036f_14f1_1122 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1222 = + {0x14f1, 0x1222, pci_subsys_109e_036f_14f1_1222, 0}; +#undef pci_ss_info_14f1_1222 +#define pci_ss_info_14f1_1222 pci_ss_info_109e_036f_14f1_1222 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1322 = + {0x14f1, 0x1322, pci_subsys_109e_036f_14f1_1322, 0}; +#undef pci_ss_info_14f1_1322 +#define pci_ss_info_14f1_1322 pci_ss_info_109e_036f_14f1_1322 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1522 = + {0x14f1, 0x1522, pci_subsys_109e_036f_14f1_1522, 0}; +#undef pci_ss_info_14f1_1522 +#define pci_ss_info_14f1_1522 pci_ss_info_109e_036f_14f1_1522 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1622 = + {0x14f1, 0x1622, pci_subsys_109e_036f_14f1_1622, 0}; +#undef pci_ss_info_14f1_1622 +#define pci_ss_info_14f1_1622 pci_ss_info_109e_036f_14f1_1622 +static const pciSubsystemInfo pci_ss_info_109e_036f_14f1_1722 = + {0x14f1, 0x1722, pci_subsys_109e_036f_14f1_1722, 0}; +#undef pci_ss_info_14f1_1722 +#define pci_ss_info_14f1_1722 pci_ss_info_109e_036f_14f1_1722 +static const pciSubsystemInfo pci_ss_info_109e_036f_1851_1850 = + {0x1851, 0x1850, pci_subsys_109e_036f_1851_1850, 0}; +#undef pci_ss_info_1851_1850 +#define pci_ss_info_1851_1850 pci_ss_info_109e_036f_1851_1850 +static const pciSubsystemInfo pci_ss_info_109e_036f_1851_1851 = + {0x1851, 0x1851, pci_subsys_109e_036f_1851_1851, 0}; +#undef pci_ss_info_1851_1851 +#define pci_ss_info_1851_1851 pci_ss_info_109e_036f_1851_1851 +static const pciSubsystemInfo pci_ss_info_109e_036f_1852_1852 = + {0x1852, 0x1852, pci_subsys_109e_036f_1852_1852, 0}; +#undef pci_ss_info_1852_1852 +#define pci_ss_info_1852_1852 pci_ss_info_109e_036f_1852_1852 +static const pciSubsystemInfo pci_ss_info_109e_0370_1851_1850 = + {0x1851, 0x1850, pci_subsys_109e_0370_1851_1850, 0}; +#undef pci_ss_info_1851_1850 +#define pci_ss_info_1851_1850 pci_ss_info_109e_0370_1851_1850 +static const pciSubsystemInfo pci_ss_info_109e_0370_1851_1851 = + {0x1851, 0x1851, pci_subsys_109e_0370_1851_1851, 0}; +#undef pci_ss_info_1851_1851 +#define pci_ss_info_1851_1851 pci_ss_info_109e_0370_1851_1851 +static const pciSubsystemInfo pci_ss_info_109e_0370_1852_1852 = + {0x1852, 0x1852, pci_subsys_109e_0370_1852_1852, 0}; +#undef pci_ss_info_1852_1852 +#define pci_ss_info_1852_1852 pci_ss_info_109e_0370_1852_1852 +static const pciSubsystemInfo pci_ss_info_109e_0878_0070_13eb = + {0x0070, 0x13eb, pci_subsys_109e_0878_0070_13eb, 0}; +#undef pci_ss_info_0070_13eb +#define pci_ss_info_0070_13eb pci_ss_info_109e_0878_0070_13eb +static const pciSubsystemInfo pci_ss_info_109e_0878_0070_ff01 = + {0x0070, 0xff01, pci_subsys_109e_0878_0070_ff01, 0}; +#undef pci_ss_info_0070_ff01 +#define pci_ss_info_0070_ff01 pci_ss_info_109e_0878_0070_ff01 +static const pciSubsystemInfo pci_ss_info_109e_0878_0071_0101 = + {0x0071, 0x0101, pci_subsys_109e_0878_0071_0101, 0}; +#undef pci_ss_info_0071_0101 +#define pci_ss_info_0071_0101 pci_ss_info_109e_0878_0071_0101 +static const pciSubsystemInfo pci_ss_info_109e_0878_1002_0001 = + {0x1002, 0x0001, pci_subsys_109e_0878_1002_0001, 0}; +#undef pci_ss_info_1002_0001 +#define pci_ss_info_1002_0001 pci_ss_info_109e_0878_1002_0001 +static const pciSubsystemInfo pci_ss_info_109e_0878_1002_0003 = + {0x1002, 0x0003, pci_subsys_109e_0878_1002_0003, 0}; +#undef pci_ss_info_1002_0003 +#define pci_ss_info_1002_0003 pci_ss_info_109e_0878_1002_0003 +static const pciSubsystemInfo pci_ss_info_109e_0878_11bd_0012 = + {0x11bd, 0x0012, pci_subsys_109e_0878_11bd_0012, 0}; +#undef pci_ss_info_11bd_0012 +#define pci_ss_info_11bd_0012 pci_ss_info_109e_0878_11bd_0012 +static const pciSubsystemInfo pci_ss_info_109e_0878_11bd_001c = + {0x11bd, 0x001c, pci_subsys_109e_0878_11bd_001c, 0}; +#undef pci_ss_info_11bd_001c +#define pci_ss_info_11bd_001c pci_ss_info_109e_0878_11bd_001c +static const pciSubsystemInfo pci_ss_info_109e_0878_127a_0001 = + {0x127a, 0x0001, pci_subsys_109e_0878_127a_0001, 0}; +#undef pci_ss_info_127a_0001 +#define pci_ss_info_127a_0001 pci_ss_info_109e_0878_127a_0001 +static const pciSubsystemInfo pci_ss_info_109e_0878_127a_0002 = + {0x127a, 0x0002, pci_subsys_109e_0878_127a_0002, 0}; +#undef pci_ss_info_127a_0002 +#define pci_ss_info_127a_0002 pci_ss_info_109e_0878_127a_0002 +static const pciSubsystemInfo pci_ss_info_109e_0878_127a_0003 = + {0x127a, 0x0003, pci_subsys_109e_0878_127a_0003, 0}; +#undef pci_ss_info_127a_0003 +#define pci_ss_info_127a_0003 pci_ss_info_109e_0878_127a_0003 +static const pciSubsystemInfo pci_ss_info_109e_0878_127a_0048 = + {0x127a, 0x0048, pci_subsys_109e_0878_127a_0048, 0}; +#undef pci_ss_info_127a_0048 +#define pci_ss_info_127a_0048 pci_ss_info_109e_0878_127a_0048 +static const pciSubsystemInfo pci_ss_info_109e_0878_13e9_0070 = + {0x13e9, 0x0070, pci_subsys_109e_0878_13e9_0070, 0}; +#undef pci_ss_info_13e9_0070 +#define pci_ss_info_13e9_0070 pci_ss_info_109e_0878_13e9_0070 +static const pciSubsystemInfo pci_ss_info_109e_0878_144f_3000 = + {0x144f, 0x3000, pci_subsys_109e_0878_144f_3000, 0}; +#undef pci_ss_info_144f_3000 +#define pci_ss_info_144f_3000 pci_ss_info_109e_0878_144f_3000 +static const pciSubsystemInfo pci_ss_info_109e_0878_1461_0002 = + {0x1461, 0x0002, pci_subsys_109e_0878_1461_0002, 0}; +#undef pci_ss_info_1461_0002 +#define pci_ss_info_1461_0002 pci_ss_info_109e_0878_1461_0002 +static const pciSubsystemInfo pci_ss_info_109e_0878_1461_0004 = + {0x1461, 0x0004, pci_subsys_109e_0878_1461_0004, 0}; +#undef pci_ss_info_1461_0004 +#define pci_ss_info_1461_0004 pci_ss_info_109e_0878_1461_0004 +static const pciSubsystemInfo pci_ss_info_109e_0878_1461_0761 = + {0x1461, 0x0761, pci_subsys_109e_0878_1461_0761, 0}; +#undef pci_ss_info_1461_0761 +#define pci_ss_info_1461_0761 pci_ss_info_109e_0878_1461_0761 +static const pciSubsystemInfo pci_ss_info_109e_0878_1461_0771 = + {0x1461, 0x0771, pci_subsys_109e_0878_1461_0771, 0}; +#undef pci_ss_info_1461_0771 +#define pci_ss_info_1461_0771 pci_ss_info_109e_0878_1461_0771 +static const pciSubsystemInfo pci_ss_info_109e_0878_14f1_0001 = + {0x14f1, 0x0001, pci_subsys_109e_0878_14f1_0001, 0}; +#undef pci_ss_info_14f1_0001 +#define pci_ss_info_14f1_0001 pci_ss_info_109e_0878_14f1_0001 +static const pciSubsystemInfo pci_ss_info_109e_0878_14f1_0002 = + {0x14f1, 0x0002, pci_subsys_109e_0878_14f1_0002, 0}; +#undef pci_ss_info_14f1_0002 +#define pci_ss_info_14f1_0002 pci_ss_info_109e_0878_14f1_0002 +static const pciSubsystemInfo pci_ss_info_109e_0878_14f1_0003 = + {0x14f1, 0x0003, pci_subsys_109e_0878_14f1_0003, 0}; +#undef pci_ss_info_14f1_0003 +#define pci_ss_info_14f1_0003 pci_ss_info_109e_0878_14f1_0003 +static const pciSubsystemInfo pci_ss_info_109e_0878_14f1_0048 = + {0x14f1, 0x0048, pci_subsys_109e_0878_14f1_0048, 0}; +#undef pci_ss_info_14f1_0048 +#define pci_ss_info_14f1_0048 pci_ss_info_109e_0878_14f1_0048 +static const pciSubsystemInfo pci_ss_info_109e_0878_1822_0001 = + {0x1822, 0x0001, pci_subsys_109e_0878_1822_0001, 0}; +#undef pci_ss_info_1822_0001 +#define pci_ss_info_1822_0001 pci_ss_info_109e_0878_1822_0001 +static const pciSubsystemInfo pci_ss_info_109e_0878_18ac_d500 = + {0x18ac, 0xd500, pci_subsys_109e_0878_18ac_d500, 0}; +#undef pci_ss_info_18ac_d500 +#define pci_ss_info_18ac_d500 pci_ss_info_109e_0878_18ac_d500 +static const pciSubsystemInfo pci_ss_info_109e_0878_270f_fc00 = + {0x270f, 0xfc00, pci_subsys_109e_0878_270f_fc00, 0}; +#undef pci_ss_info_270f_fc00 +#define pci_ss_info_270f_fc00 pci_ss_info_109e_0878_270f_fc00 +static const pciSubsystemInfo pci_ss_info_109e_0878_bd11_1200 = + {0xbd11, 0x1200, pci_subsys_109e_0878_bd11_1200, 0}; +#undef pci_ss_info_bd11_1200 +#define pci_ss_info_bd11_1200 pci_ss_info_109e_0878_bd11_1200 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0044 = + {0x127a, 0x0044, pci_subsys_109e_0879_127a_0044, 0}; +#undef pci_ss_info_127a_0044 +#define pci_ss_info_127a_0044 pci_ss_info_109e_0879_127a_0044 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0122 = + {0x127a, 0x0122, pci_subsys_109e_0879_127a_0122, 0}; +#undef pci_ss_info_127a_0122 +#define pci_ss_info_127a_0122 pci_ss_info_109e_0879_127a_0122 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0144 = + {0x127a, 0x0144, pci_subsys_109e_0879_127a_0144, 0}; +#undef pci_ss_info_127a_0144 +#define pci_ss_info_127a_0144 pci_ss_info_109e_0879_127a_0144 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0222 = + {0x127a, 0x0222, pci_subsys_109e_0879_127a_0222, 0}; +#undef pci_ss_info_127a_0222 +#define pci_ss_info_127a_0222 pci_ss_info_109e_0879_127a_0222 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0244 = + {0x127a, 0x0244, pci_subsys_109e_0879_127a_0244, 0}; +#undef pci_ss_info_127a_0244 +#define pci_ss_info_127a_0244 pci_ss_info_109e_0879_127a_0244 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0322 = + {0x127a, 0x0322, pci_subsys_109e_0879_127a_0322, 0}; +#undef pci_ss_info_127a_0322 +#define pci_ss_info_127a_0322 pci_ss_info_109e_0879_127a_0322 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_0422 = + {0x127a, 0x0422, pci_subsys_109e_0879_127a_0422, 0}; +#undef pci_ss_info_127a_0422 +#define pci_ss_info_127a_0422 pci_ss_info_109e_0879_127a_0422 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1122 = + {0x127a, 0x1122, pci_subsys_109e_0879_127a_1122, 0}; +#undef pci_ss_info_127a_1122 +#define pci_ss_info_127a_1122 pci_ss_info_109e_0879_127a_1122 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1222 = + {0x127a, 0x1222, pci_subsys_109e_0879_127a_1222, 0}; +#undef pci_ss_info_127a_1222 +#define pci_ss_info_127a_1222 pci_ss_info_109e_0879_127a_1222 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1322 = + {0x127a, 0x1322, pci_subsys_109e_0879_127a_1322, 0}; +#undef pci_ss_info_127a_1322 +#define pci_ss_info_127a_1322 pci_ss_info_109e_0879_127a_1322 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1522 = + {0x127a, 0x1522, pci_subsys_109e_0879_127a_1522, 0}; +#undef pci_ss_info_127a_1522 +#define pci_ss_info_127a_1522 pci_ss_info_109e_0879_127a_1522 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1622 = + {0x127a, 0x1622, pci_subsys_109e_0879_127a_1622, 0}; +#undef pci_ss_info_127a_1622 +#define pci_ss_info_127a_1622 pci_ss_info_109e_0879_127a_1622 +static const pciSubsystemInfo pci_ss_info_109e_0879_127a_1722 = + {0x127a, 0x1722, pci_subsys_109e_0879_127a_1722, 0}; +#undef pci_ss_info_127a_1722 +#define pci_ss_info_127a_1722 pci_ss_info_109e_0879_127a_1722 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0044 = + {0x14f1, 0x0044, pci_subsys_109e_0879_14f1_0044, 0}; +#undef pci_ss_info_14f1_0044 +#define pci_ss_info_14f1_0044 pci_ss_info_109e_0879_14f1_0044 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0122 = + {0x14f1, 0x0122, pci_subsys_109e_0879_14f1_0122, 0}; +#undef pci_ss_info_14f1_0122 +#define pci_ss_info_14f1_0122 pci_ss_info_109e_0879_14f1_0122 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0144 = + {0x14f1, 0x0144, pci_subsys_109e_0879_14f1_0144, 0}; +#undef pci_ss_info_14f1_0144 +#define pci_ss_info_14f1_0144 pci_ss_info_109e_0879_14f1_0144 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0222 = + {0x14f1, 0x0222, pci_subsys_109e_0879_14f1_0222, 0}; +#undef pci_ss_info_14f1_0222 +#define pci_ss_info_14f1_0222 pci_ss_info_109e_0879_14f1_0222 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0244 = + {0x14f1, 0x0244, pci_subsys_109e_0879_14f1_0244, 0}; +#undef pci_ss_info_14f1_0244 +#define pci_ss_info_14f1_0244 pci_ss_info_109e_0879_14f1_0244 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0322 = + {0x14f1, 0x0322, pci_subsys_109e_0879_14f1_0322, 0}; +#undef pci_ss_info_14f1_0322 +#define pci_ss_info_14f1_0322 pci_ss_info_109e_0879_14f1_0322 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_0422 = + {0x14f1, 0x0422, pci_subsys_109e_0879_14f1_0422, 0}; +#undef pci_ss_info_14f1_0422 +#define pci_ss_info_14f1_0422 pci_ss_info_109e_0879_14f1_0422 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1122 = + {0x14f1, 0x1122, pci_subsys_109e_0879_14f1_1122, 0}; +#undef pci_ss_info_14f1_1122 +#define pci_ss_info_14f1_1122 pci_ss_info_109e_0879_14f1_1122 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1222 = + {0x14f1, 0x1222, pci_subsys_109e_0879_14f1_1222, 0}; +#undef pci_ss_info_14f1_1222 +#define pci_ss_info_14f1_1222 pci_ss_info_109e_0879_14f1_1222 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1322 = + {0x14f1, 0x1322, pci_subsys_109e_0879_14f1_1322, 0}; +#undef pci_ss_info_14f1_1322 +#define pci_ss_info_14f1_1322 pci_ss_info_109e_0879_14f1_1322 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1522 = + {0x14f1, 0x1522, pci_subsys_109e_0879_14f1_1522, 0}; +#undef pci_ss_info_14f1_1522 +#define pci_ss_info_14f1_1522 pci_ss_info_109e_0879_14f1_1522 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1622 = + {0x14f1, 0x1622, pci_subsys_109e_0879_14f1_1622, 0}; +#undef pci_ss_info_14f1_1622 +#define pci_ss_info_14f1_1622 pci_ss_info_109e_0879_14f1_1622 +static const pciSubsystemInfo pci_ss_info_109e_0879_14f1_1722 = + {0x14f1, 0x1722, pci_subsys_109e_0879_14f1_1722, 0}; +#undef pci_ss_info_14f1_1722 +#define pci_ss_info_14f1_1722 pci_ss_info_109e_0879_14f1_1722 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10a9_0009_10a9_8002 = + {0x10a9, 0x8002, pci_subsys_10a9_0009_10a9_8002, 0}; +#undef pci_ss_info_10a9_8002 +#define pci_ss_info_10a9_8002 pci_ss_info_10a9_0009_10a9_8002 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b4_1b1d_10b4_237e = + {0x10b4, 0x237e, pci_subsys_10b4_1b1d_10b4_237e, 0}; +#undef pci_ss_info_10b4_237e +#define pci_ss_info_10b4_237e pci_ss_info_10b4_1b1d_10b4_237e +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b5_6540_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_10b5_6540_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_10b5_6540_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_10b5_6541_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_10b5_6541_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_10b5_6541_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_10b5_6542_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_10b5_6542_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_10b5_6542_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_2862 = + {0x10b5, 0x2862, pci_subsys_10b5_9030_10b5_2862, 0}; +#undef pci_ss_info_10b5_2862 +#define pci_ss_info_10b5_2862 pci_ss_info_10b5_9030_10b5_2862 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_2906 = + {0x10b5, 0x2906, pci_subsys_10b5_9030_10b5_2906, 0}; +#undef pci_ss_info_10b5_2906 +#define pci_ss_info_10b5_2906 pci_ss_info_10b5_9030_10b5_2906 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_2940 = + {0x10b5, 0x2940, pci_subsys_10b5_9030_10b5_2940, 0}; +#undef pci_ss_info_10b5_2940 +#define pci_ss_info_10b5_2940 pci_ss_info_10b5_9030_10b5_2940 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_2977 = + {0x10b5, 0x2977, pci_subsys_10b5_9030_10b5_2977, 0}; +#undef pci_ss_info_10b5_2977 +#define pci_ss_info_10b5_2977 pci_ss_info_10b5_9030_10b5_2977 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_2978 = + {0x10b5, 0x2978, pci_subsys_10b5_9030_10b5_2978, 0}; +#undef pci_ss_info_10b5_2978 +#define pci_ss_info_10b5_2978 pci_ss_info_10b5_9030_10b5_2978 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_3025 = + {0x10b5, 0x3025, pci_subsys_10b5_9030_10b5_3025, 0}; +#undef pci_ss_info_10b5_3025 +#define pci_ss_info_10b5_3025 pci_ss_info_10b5_9030_10b5_3025 +static const pciSubsystemInfo pci_ss_info_10b5_9030_10b5_3068 = + {0x10b5, 0x3068, pci_subsys_10b5_9030_10b5_3068, 0}; +#undef pci_ss_info_10b5_3068 +#define pci_ss_info_10b5_3068 pci_ss_info_10b5_9030_10b5_3068 +static const pciSubsystemInfo pci_ss_info_10b5_9030_1397_3136 = + {0x1397, 0x3136, pci_subsys_10b5_9030_1397_3136, 0}; +#undef pci_ss_info_1397_3136 +#define pci_ss_info_1397_3136 pci_ss_info_10b5_9030_1397_3136 +static const pciSubsystemInfo pci_ss_info_10b5_9030_1397_3137 = + {0x1397, 0x3137, pci_subsys_10b5_9030_1397_3137, 0}; +#undef pci_ss_info_1397_3137 +#define pci_ss_info_1397_3137 pci_ss_info_10b5_9030_1397_3137 +static const pciSubsystemInfo pci_ss_info_10b5_9030_1518_0200 = + {0x1518, 0x0200, pci_subsys_10b5_9030_1518_0200, 0}; +#undef pci_ss_info_1518_0200 +#define pci_ss_info_1518_0200 pci_ss_info_10b5_9030_1518_0200 +static const pciSubsystemInfo pci_ss_info_10b5_9030_15ed_1002 = + {0x15ed, 0x1002, pci_subsys_10b5_9030_15ed_1002, 0}; +#undef pci_ss_info_15ed_1002 +#define pci_ss_info_15ed_1002 pci_ss_info_10b5_9030_15ed_1002 +static const pciSubsystemInfo pci_ss_info_10b5_9030_15ed_1003 = + {0x15ed, 0x1003, pci_subsys_10b5_9030_15ed_1003, 0}; +#undef pci_ss_info_15ed_1003 +#define pci_ss_info_15ed_1003 pci_ss_info_10b5_9030_15ed_1003 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_1067 = + {0x10b5, 0x1067, pci_subsys_10b5_9050_10b5_1067, 0}; +#undef pci_ss_info_10b5_1067 +#define pci_ss_info_10b5_1067 pci_ss_info_10b5_9050_10b5_1067 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_1172 = + {0x10b5, 0x1172, pci_subsys_10b5_9050_10b5_1172, 0}; +#undef pci_ss_info_10b5_1172 +#define pci_ss_info_10b5_1172 pci_ss_info_10b5_9050_10b5_1172 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_2036 = + {0x10b5, 0x2036, pci_subsys_10b5_9050_10b5_2036, 0}; +#undef pci_ss_info_10b5_2036 +#define pci_ss_info_10b5_2036 pci_ss_info_10b5_9050_10b5_2036 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_2221 = + {0x10b5, 0x2221, pci_subsys_10b5_9050_10b5_2221, 0}; +#undef pci_ss_info_10b5_2221 +#define pci_ss_info_10b5_2221 pci_ss_info_10b5_9050_10b5_2221 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_2273 = + {0x10b5, 0x2273, pci_subsys_10b5_9050_10b5_2273, 0}; +#undef pci_ss_info_10b5_2273 +#define pci_ss_info_10b5_2273 pci_ss_info_10b5_9050_10b5_2273 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_2431 = + {0x10b5, 0x2431, pci_subsys_10b5_9050_10b5_2431, 0}; +#undef pci_ss_info_10b5_2431 +#define pci_ss_info_10b5_2431 pci_ss_info_10b5_9050_10b5_2431 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_2905 = + {0x10b5, 0x2905, pci_subsys_10b5_9050_10b5_2905, 0}; +#undef pci_ss_info_10b5_2905 +#define pci_ss_info_10b5_2905 pci_ss_info_10b5_9050_10b5_2905 +static const pciSubsystemInfo pci_ss_info_10b5_9050_10b5_9050 = + {0x10b5, 0x9050, pci_subsys_10b5_9050_10b5_9050, 0}; +#undef pci_ss_info_10b5_9050 +#define pci_ss_info_10b5_9050 pci_ss_info_10b5_9050_10b5_9050 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1498_0362 = + {0x1498, 0x0362, pci_subsys_10b5_9050_1498_0362, 0}; +#undef pci_ss_info_1498_0362 +#define pci_ss_info_1498_0362 pci_ss_info_10b5_9050_1498_0362 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0001 = + {0x1522, 0x0001, pci_subsys_10b5_9050_1522_0001, 0}; +#undef pci_ss_info_1522_0001 +#define pci_ss_info_1522_0001 pci_ss_info_10b5_9050_1522_0001 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0002 = + {0x1522, 0x0002, pci_subsys_10b5_9050_1522_0002, 0}; +#undef pci_ss_info_1522_0002 +#define pci_ss_info_1522_0002 pci_ss_info_10b5_9050_1522_0002 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0003 = + {0x1522, 0x0003, pci_subsys_10b5_9050_1522_0003, 0}; +#undef pci_ss_info_1522_0003 +#define pci_ss_info_1522_0003 pci_ss_info_10b5_9050_1522_0003 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0004 = + {0x1522, 0x0004, pci_subsys_10b5_9050_1522_0004, 0}; +#undef pci_ss_info_1522_0004 +#define pci_ss_info_1522_0004 pci_ss_info_10b5_9050_1522_0004 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0010 = + {0x1522, 0x0010, pci_subsys_10b5_9050_1522_0010, 0}; +#undef pci_ss_info_1522_0010 +#define pci_ss_info_1522_0010 pci_ss_info_10b5_9050_1522_0010 +static const pciSubsystemInfo pci_ss_info_10b5_9050_1522_0020 = + {0x1522, 0x0020, pci_subsys_10b5_9050_1522_0020, 0}; +#undef pci_ss_info_1522_0020 +#define pci_ss_info_1522_0020 pci_ss_info_10b5_9050_1522_0020 +static const pciSubsystemInfo pci_ss_info_10b5_9050_15ed_1000 = + {0x15ed, 0x1000, pci_subsys_10b5_9050_15ed_1000, 0}; +#undef pci_ss_info_15ed_1000 +#define pci_ss_info_15ed_1000 pci_ss_info_10b5_9050_15ed_1000 +static const pciSubsystemInfo pci_ss_info_10b5_9050_15ed_1001 = + {0x15ed, 0x1001, pci_subsys_10b5_9050_15ed_1001, 0}; +#undef pci_ss_info_15ed_1001 +#define pci_ss_info_15ed_1001 pci_ss_info_10b5_9050_15ed_1001 +static const pciSubsystemInfo pci_ss_info_10b5_9050_15ed_1002 = + {0x15ed, 0x1002, pci_subsys_10b5_9050_15ed_1002, 0}; +#undef pci_ss_info_15ed_1002 +#define pci_ss_info_15ed_1002 pci_ss_info_10b5_9050_15ed_1002 +static const pciSubsystemInfo pci_ss_info_10b5_9050_15ed_1003 = + {0x15ed, 0x1003, pci_subsys_10b5_9050_15ed_1003, 0}; +#undef pci_ss_info_15ed_1003 +#define pci_ss_info_15ed_1003 pci_ss_info_10b5_9050_15ed_1003 +static const pciSubsystemInfo pci_ss_info_10b5_9050_5654_2036 = + {0x5654, 0x2036, pci_subsys_10b5_9050_5654_2036, 0}; +#undef pci_ss_info_5654_2036 +#define pci_ss_info_5654_2036 pci_ss_info_10b5_9050_5654_2036 +static const pciSubsystemInfo pci_ss_info_10b5_9050_5654_3132 = + {0x5654, 0x3132, pci_subsys_10b5_9050_5654_3132, 0}; +#undef pci_ss_info_5654_3132 +#define pci_ss_info_5654_3132 pci_ss_info_10b5_9050_5654_3132 +static const pciSubsystemInfo pci_ss_info_10b5_9050_5654_5634 = + {0x5654, 0x5634, pci_subsys_10b5_9050_5654_5634, 0}; +#undef pci_ss_info_5654_5634 +#define pci_ss_info_5654_5634 pci_ss_info_10b5_9050_5654_5634 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d531_c002 = + {0xd531, 0xc002, pci_subsys_10b5_9050_d531_c002, 0}; +#undef pci_ss_info_d531_c002 +#define pci_ss_info_d531_c002 pci_ss_info_10b5_9050_d531_c002 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4006 = + {0xd84d, 0x4006, pci_subsys_10b5_9050_d84d_4006, 0}; +#undef pci_ss_info_d84d_4006 +#define pci_ss_info_d84d_4006 pci_ss_info_10b5_9050_d84d_4006 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4008 = + {0xd84d, 0x4008, pci_subsys_10b5_9050_d84d_4008, 0}; +#undef pci_ss_info_d84d_4008 +#define pci_ss_info_d84d_4008 pci_ss_info_10b5_9050_d84d_4008 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4014 = + {0xd84d, 0x4014, pci_subsys_10b5_9050_d84d_4014, 0}; +#undef pci_ss_info_d84d_4014 +#define pci_ss_info_d84d_4014 pci_ss_info_10b5_9050_d84d_4014 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4018 = + {0xd84d, 0x4018, pci_subsys_10b5_9050_d84d_4018, 0}; +#undef pci_ss_info_d84d_4018 +#define pci_ss_info_d84d_4018 pci_ss_info_10b5_9050_d84d_4018 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4025 = + {0xd84d, 0x4025, pci_subsys_10b5_9050_d84d_4025, 0}; +#undef pci_ss_info_d84d_4025 +#define pci_ss_info_d84d_4025 pci_ss_info_10b5_9050_d84d_4025 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4027 = + {0xd84d, 0x4027, pci_subsys_10b5_9050_d84d_4027, 0}; +#undef pci_ss_info_d84d_4027 +#define pci_ss_info_d84d_4027 pci_ss_info_10b5_9050_d84d_4027 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4028 = + {0xd84d, 0x4028, pci_subsys_10b5_9050_d84d_4028, 0}; +#undef pci_ss_info_d84d_4028 +#define pci_ss_info_d84d_4028 pci_ss_info_10b5_9050_d84d_4028 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4036 = + {0xd84d, 0x4036, pci_subsys_10b5_9050_d84d_4036, 0}; +#undef pci_ss_info_d84d_4036 +#define pci_ss_info_d84d_4036 pci_ss_info_10b5_9050_d84d_4036 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4037 = + {0xd84d, 0x4037, pci_subsys_10b5_9050_d84d_4037, 0}; +#undef pci_ss_info_d84d_4037 +#define pci_ss_info_d84d_4037 pci_ss_info_10b5_9050_d84d_4037 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4038 = + {0xd84d, 0x4038, pci_subsys_10b5_9050_d84d_4038, 0}; +#undef pci_ss_info_d84d_4038 +#define pci_ss_info_d84d_4038 pci_ss_info_10b5_9050_d84d_4038 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4052 = + {0xd84d, 0x4052, pci_subsys_10b5_9050_d84d_4052, 0}; +#undef pci_ss_info_d84d_4052 +#define pci_ss_info_d84d_4052 pci_ss_info_10b5_9050_d84d_4052 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4053 = + {0xd84d, 0x4053, pci_subsys_10b5_9050_d84d_4053, 0}; +#undef pci_ss_info_d84d_4053 +#define pci_ss_info_d84d_4053 pci_ss_info_10b5_9050_d84d_4053 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4055 = + {0xd84d, 0x4055, pci_subsys_10b5_9050_d84d_4055, 0}; +#undef pci_ss_info_d84d_4055 +#define pci_ss_info_d84d_4055 pci_ss_info_10b5_9050_d84d_4055 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4058 = + {0xd84d, 0x4058, pci_subsys_10b5_9050_d84d_4058, 0}; +#undef pci_ss_info_d84d_4058 +#define pci_ss_info_d84d_4058 pci_ss_info_10b5_9050_d84d_4058 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4065 = + {0xd84d, 0x4065, pci_subsys_10b5_9050_d84d_4065, 0}; +#undef pci_ss_info_d84d_4065 +#define pci_ss_info_d84d_4065 pci_ss_info_10b5_9050_d84d_4065 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4068 = + {0xd84d, 0x4068, pci_subsys_10b5_9050_d84d_4068, 0}; +#undef pci_ss_info_d84d_4068 +#define pci_ss_info_d84d_4068 pci_ss_info_10b5_9050_d84d_4068 +static const pciSubsystemInfo pci_ss_info_10b5_9050_d84d_4078 = + {0xd84d, 0x4078, pci_subsys_10b5_9050_d84d_4078, 0}; +#undef pci_ss_info_d84d_4078 +#define pci_ss_info_d84d_4078 pci_ss_info_10b5_9050_d84d_4078 +static const pciSubsystemInfo pci_ss_info_10b5_9054_10b5_2455 = + {0x10b5, 0x2455, pci_subsys_10b5_9054_10b5_2455, 0}; +#undef pci_ss_info_10b5_2455 +#define pci_ss_info_10b5_2455 pci_ss_info_10b5_9054_10b5_2455 +static const pciSubsystemInfo pci_ss_info_10b5_9054_10b5_2696 = + {0x10b5, 0x2696, pci_subsys_10b5_9054_10b5_2696, 0}; +#undef pci_ss_info_10b5_2696 +#define pci_ss_info_10b5_2696 pci_ss_info_10b5_9054_10b5_2696 +static const pciSubsystemInfo pci_ss_info_10b5_9054_10b5_2717 = + {0x10b5, 0x2717, pci_subsys_10b5_9054_10b5_2717, 0}; +#undef pci_ss_info_10b5_2717 +#define pci_ss_info_10b5_2717 pci_ss_info_10b5_9054_10b5_2717 +static const pciSubsystemInfo pci_ss_info_10b5_9054_10b5_2844 = + {0x10b5, 0x2844, pci_subsys_10b5_9054_10b5_2844, 0}; +#undef pci_ss_info_10b5_2844 +#define pci_ss_info_10b5_2844 pci_ss_info_10b5_9054_10b5_2844 +static const pciSubsystemInfo pci_ss_info_10b5_9054_12c7_4001 = + {0x12c7, 0x4001, pci_subsys_10b5_9054_12c7_4001, 0}; +#undef pci_ss_info_12c7_4001 +#define pci_ss_info_12c7_4001 pci_ss_info_10b5_9054_12c7_4001 +static const pciSubsystemInfo pci_ss_info_10b5_9054_12d9_0002 = + {0x12d9, 0x0002, pci_subsys_10b5_9054_12d9_0002, 0}; +#undef pci_ss_info_12d9_0002 +#define pci_ss_info_12d9_0002 pci_ss_info_10b5_9054_12d9_0002 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0011 = + {0x16df, 0x0011, pci_subsys_10b5_9054_16df_0011, 0}; +#undef pci_ss_info_16df_0011 +#define pci_ss_info_16df_0011 pci_ss_info_10b5_9054_16df_0011 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0012 = + {0x16df, 0x0012, pci_subsys_10b5_9054_16df_0012, 0}; +#undef pci_ss_info_16df_0012 +#define pci_ss_info_16df_0012 pci_ss_info_10b5_9054_16df_0012 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0013 = + {0x16df, 0x0013, pci_subsys_10b5_9054_16df_0013, 0}; +#undef pci_ss_info_16df_0013 +#define pci_ss_info_16df_0013 pci_ss_info_10b5_9054_16df_0013 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0014 = + {0x16df, 0x0014, pci_subsys_10b5_9054_16df_0014, 0}; +#undef pci_ss_info_16df_0014 +#define pci_ss_info_16df_0014 pci_ss_info_10b5_9054_16df_0014 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0015 = + {0x16df, 0x0015, pci_subsys_10b5_9054_16df_0015, 0}; +#undef pci_ss_info_16df_0015 +#define pci_ss_info_16df_0015 pci_ss_info_10b5_9054_16df_0015 +static const pciSubsystemInfo pci_ss_info_10b5_9054_16df_0016 = + {0x16df, 0x0016, pci_subsys_10b5_9054_16df_0016, 0}; +#undef pci_ss_info_16df_0016 +#define pci_ss_info_16df_0016 pci_ss_info_10b5_9054_16df_0016 +static const pciSubsystemInfo pci_ss_info_10b5_9056_10b5_2979 = + {0x10b5, 0x2979, pci_subsys_10b5_9056_10b5_2979, 0}; +#undef pci_ss_info_10b5_2979 +#define pci_ss_info_10b5_2979 pci_ss_info_10b5_9056_10b5_2979 +static const pciSubsystemInfo pci_ss_info_10b5_906d_125c_0640 = + {0x125c, 0x0640, pci_subsys_10b5_906d_125c_0640, 0}; +#undef pci_ss_info_125c_0640 +#define pci_ss_info_125c_0640 pci_ss_info_10b5_906d_125c_0640 +#endif +static const pciSubsystemInfo pci_ss_info_10b5_9080_103c_10eb = + {0x103c, 0x10eb, pci_subsys_10b5_9080_103c_10eb, 0}; +#undef pci_ss_info_103c_10eb +#define pci_ss_info_103c_10eb pci_ss_info_10b5_9080_103c_10eb +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b5_9080_103c_10ec = + {0x103c, 0x10ec, pci_subsys_10b5_9080_103c_10ec, 0}; +#undef pci_ss_info_103c_10ec +#define pci_ss_info_103c_10ec pci_ss_info_10b5_9080_103c_10ec +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b5_9080_10b5_1123 = + {0x10b5, 0x1123, pci_subsys_10b5_9080_10b5_1123, 0}; +#undef pci_ss_info_10b5_1123 +#define pci_ss_info_10b5_1123 pci_ss_info_10b5_9080_10b5_1123 +static const pciSubsystemInfo pci_ss_info_10b5_9080_10b5_9080 = + {0x10b5, 0x9080, pci_subsys_10b5_9080_10b5_9080, 0}; +#undef pci_ss_info_10b5_9080 +#define pci_ss_info_10b5_9080 pci_ss_info_10b5_9080_10b5_9080 +static const pciSubsystemInfo pci_ss_info_10b5_9080_129d_0002 = + {0x129d, 0x0002, pci_subsys_10b5_9080_129d_0002, 0}; +#undef pci_ss_info_129d_0002 +#define pci_ss_info_129d_0002 pci_ss_info_10b5_9080_129d_0002 +static const pciSubsystemInfo pci_ss_info_10b5_9080_12d9_0002 = + {0x12d9, 0x0002, pci_subsys_10b5_9080_12d9_0002, 0}; +#undef pci_ss_info_12d9_0002 +#define pci_ss_info_12d9_0002 pci_ss_info_10b5_9080_12d9_0002 +static const pciSubsystemInfo pci_ss_info_10b5_9080_12df_4422 = + {0x12df, 0x4422, pci_subsys_10b5_9080_12df_4422, 0}; +#undef pci_ss_info_12df_4422 +#define pci_ss_info_12df_4422 pci_ss_info_10b5_9080_12df_4422 +static const pciSubsystemInfo pci_ss_info_10b5_9080_1517_000b = + {0x1517, 0x000b, pci_subsys_10b5_9080_1517_000b, 0}; +#undef pci_ss_info_1517_000b +#define pci_ss_info_1517_000b pci_ss_info_10b5_9080_1517_000b +static const pciSubsystemInfo pci_ss_info_10b5_9656_1517_000f = + {0x1517, 0x000f, pci_subsys_10b5_9656_1517_000f, 0}; +#undef pci_ss_info_1517_000f +#define pci_ss_info_1517_000f pci_ss_info_10b5_9656_1517_000f +static const pciSubsystemInfo pci_ss_info_10b5_9656_1885_0700 = + {0x1885, 0x0700, pci_subsys_10b5_9656_1885_0700, 0}; +#undef pci_ss_info_1885_0700 +#define pci_ss_info_1885_0700 pci_ss_info_10b5_9656_1885_0700 +static const pciSubsystemInfo pci_ss_info_10b5_9656_1885_0701 = + {0x1885, 0x0701, pci_subsys_10b5_9656_1885_0701, 0}; +#undef pci_ss_info_1885_0701 +#define pci_ss_info_1885_0701 pci_ss_info_10b5_9656_1885_0701 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b6_0002_10b6_0002 = + {0x10b6, 0x0002, pci_subsys_10b6_0002_10b6_0002, 0}; +#undef pci_ss_info_10b6_0002 +#define pci_ss_info_10b6_0002 pci_ss_info_10b6_0002_10b6_0002 +static const pciSubsystemInfo pci_ss_info_10b6_0002_10b6_0006 = + {0x10b6, 0x0006, pci_subsys_10b6_0002_10b6_0006, 0}; +#undef pci_ss_info_10b6_0006 +#define pci_ss_info_10b6_0006 pci_ss_info_10b6_0002_10b6_0006 +#endif +static const pciSubsystemInfo pci_ss_info_10b6_0003_0e11_b0fd = + {0x0e11, 0xb0fd, pci_subsys_10b6_0003_0e11_b0fd, 0}; +#undef pci_ss_info_0e11_b0fd +#define pci_ss_info_0e11_b0fd pci_ss_info_10b6_0003_0e11_b0fd +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b6_0003_10b6_0003 = + {0x10b6, 0x0003, pci_subsys_10b6_0003_10b6_0003, 0}; +#undef pci_ss_info_10b6_0003 +#define pci_ss_info_10b6_0003 pci_ss_info_10b6_0003_10b6_0003 +static const pciSubsystemInfo pci_ss_info_10b6_0003_10b6_0007 = + {0x10b6, 0x0007, pci_subsys_10b6_0003_10b6_0007, 0}; +#undef pci_ss_info_10b6_0007 +#define pci_ss_info_10b6_0007 pci_ss_info_10b6_0003_10b6_0007 +static const pciSubsystemInfo pci_ss_info_10b6_0006_10b6_0006 = + {0x10b6, 0x0006, pci_subsys_10b6_0006_10b6_0006, 0}; +#undef pci_ss_info_10b6_0006 +#define pci_ss_info_10b6_0006 pci_ss_info_10b6_0006_10b6_0006 +static const pciSubsystemInfo pci_ss_info_10b6_0007_10b6_0007 = + {0x10b6, 0x0007, pci_subsys_10b6_0007_10b6_0007, 0}; +#undef pci_ss_info_10b6_0007 +#define pci_ss_info_10b6_0007 pci_ss_info_10b6_0007_10b6_0007 +static const pciSubsystemInfo pci_ss_info_10b6_0009_10b6_0009 = + {0x10b6, 0x0009, pci_subsys_10b6_0009_10b6_0009, 0}; +#undef pci_ss_info_10b6_0009 +#define pci_ss_info_10b6_0009 pci_ss_info_10b6_0009_10b6_0009 +static const pciSubsystemInfo pci_ss_info_10b6_000a_10b6_000a = + {0x10b6, 0x000a, pci_subsys_10b6_000a_10b6_000a, 0}; +#undef pci_ss_info_10b6_000a +#define pci_ss_info_10b6_000a pci_ss_info_10b6_000a_10b6_000a +static const pciSubsystemInfo pci_ss_info_10b6_000b_10b6_0008 = + {0x10b6, 0x0008, pci_subsys_10b6_000b_10b6_0008, 0}; +#undef pci_ss_info_10b6_0008 +#define pci_ss_info_10b6_0008 pci_ss_info_10b6_000b_10b6_0008 +static const pciSubsystemInfo pci_ss_info_10b6_000b_10b6_000b = + {0x10b6, 0x000b, pci_subsys_10b6_000b_10b6_000b, 0}; +#undef pci_ss_info_10b6_000b +#define pci_ss_info_10b6_000b pci_ss_info_10b6_000b_10b6_000b +static const pciSubsystemInfo pci_ss_info_10b6_000c_10b6_000c = + {0x10b6, 0x000c, pci_subsys_10b6_000c_10b6_000c, 0}; +#undef pci_ss_info_10b6_000c +#define pci_ss_info_10b6_000c pci_ss_info_10b6_000c_10b6_000c +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b7_0013_10b7_2031 = + {0x10b7, 0x2031, pci_subsys_10b7_0013_10b7_2031, 0}; +#undef pci_ss_info_10b7_2031 +#define pci_ss_info_10b7_2031 pci_ss_info_10b7_0013_10b7_2031 +static const pciSubsystemInfo pci_ss_info_10b7_1007_10b7_615c = + {0x10b7, 0x615c, pci_subsys_10b7_1007_10b7_615c, 0}; +#undef pci_ss_info_10b7_615c +#define pci_ss_info_10b7_615c pci_ss_info_10b7_1007_10b7_615c +static const pciSubsystemInfo pci_ss_info_10b7_1700_1043_80eb = + {0x1043, 0x80eb, pci_subsys_10b7_1700_1043_80eb, 0}; +#undef pci_ss_info_1043_80eb +#define pci_ss_info_1043_80eb pci_ss_info_10b7_1700_1043_80eb +static const pciSubsystemInfo pci_ss_info_10b7_1700_10b7_0010 = + {0x10b7, 0x0010, pci_subsys_10b7_1700_10b7_0010, 0}; +#undef pci_ss_info_10b7_0010 +#define pci_ss_info_10b7_0010 pci_ss_info_10b7_1700_10b7_0010 +static const pciSubsystemInfo pci_ss_info_10b7_1700_10b7_0020 = + {0x10b7, 0x0020, pci_subsys_10b7_1700_10b7_0020, 0}; +#undef pci_ss_info_10b7_0020 +#define pci_ss_info_10b7_0020 pci_ss_info_10b7_1700_10b7_0020 +static const pciSubsystemInfo pci_ss_info_10b7_1700_147b_1407 = + {0x147b, 0x1407, pci_subsys_10b7_1700_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_10b7_1700_147b_1407 +static const pciSubsystemInfo pci_ss_info_10b7_3590_10b7_3590 = + {0x10b7, 0x3590, pci_subsys_10b7_3590_10b7_3590, 0}; +#undef pci_ss_info_10b7_3590 +#define pci_ss_info_10b7_3590 pci_ss_info_10b7_3590_10b7_3590 +static const pciSubsystemInfo pci_ss_info_10b7_5057_10b7_5a57 = + {0x10b7, 0x5a57, pci_subsys_10b7_5057_10b7_5a57, 0}; +#undef pci_ss_info_10b7_5a57 +#define pci_ss_info_10b7_5a57 pci_ss_info_10b7_5057_10b7_5a57 +static const pciSubsystemInfo pci_ss_info_10b7_5157_10b7_5b57 = + {0x10b7, 0x5b57, pci_subsys_10b7_5157_10b7_5b57, 0}; +#undef pci_ss_info_10b7_5b57 +#define pci_ss_info_10b7_5b57 pci_ss_info_10b7_5157_10b7_5b57 +static const pciSubsystemInfo pci_ss_info_10b7_5257_10b7_5c57 = + {0x10b7, 0x5c57, pci_subsys_10b7_5257_10b7_5c57, 0}; +#undef pci_ss_info_10b7_5c57 +#define pci_ss_info_10b7_5c57 pci_ss_info_10b7_5257_10b7_5c57 +static const pciSubsystemInfo pci_ss_info_10b7_5b57_10b7_5b57 = + {0x10b7, 0x5b57, pci_subsys_10b7_5b57_10b7_5b57, 0}; +#undef pci_ss_info_10b7_5b57 +#define pci_ss_info_10b7_5b57 pci_ss_info_10b7_5b57_10b7_5b57 +static const pciSubsystemInfo pci_ss_info_10b7_6056_10b7_6556 = + {0x10b7, 0x6556, pci_subsys_10b7_6056_10b7_6556, 0}; +#undef pci_ss_info_10b7_6556 +#define pci_ss_info_10b7_6556 pci_ss_info_10b7_6056_10b7_6556 +static const pciSubsystemInfo pci_ss_info_10b7_6560_10b7_656a = + {0x10b7, 0x656a, pci_subsys_10b7_6560_10b7_656a, 0}; +#undef pci_ss_info_10b7_656a +#define pci_ss_info_10b7_656a pci_ss_info_10b7_6560_10b7_656a +static const pciSubsystemInfo pci_ss_info_10b7_6561_10b7_656b = + {0x10b7, 0x656b, pci_subsys_10b7_6561_10b7_656b, 0}; +#undef pci_ss_info_10b7_656b +#define pci_ss_info_10b7_656b pci_ss_info_10b7_6561_10b7_656b +static const pciSubsystemInfo pci_ss_info_10b7_6562_10b7_656b = + {0x10b7, 0x656b, pci_subsys_10b7_6562_10b7_656b, 0}; +#undef pci_ss_info_10b7_656b +#define pci_ss_info_10b7_656b pci_ss_info_10b7_6562_10b7_656b +static const pciSubsystemInfo pci_ss_info_10b7_6563_10b7_656b = + {0x10b7, 0x656b, pci_subsys_10b7_6563_10b7_656b, 0}; +#undef pci_ss_info_10b7_656b +#define pci_ss_info_10b7_656b pci_ss_info_10b7_6563_10b7_656b +static const pciSubsystemInfo pci_ss_info_10b7_9004_10b7_9004 = + {0x10b7, 0x9004, pci_subsys_10b7_9004_10b7_9004, 0}; +#undef pci_ss_info_10b7_9004 +#define pci_ss_info_10b7_9004 pci_ss_info_10b7_9004_10b7_9004 +static const pciSubsystemInfo pci_ss_info_10b7_9005_10b7_9005 = + {0x10b7, 0x9005, pci_subsys_10b7_9005_10b7_9005, 0}; +#undef pci_ss_info_10b7_9005 +#define pci_ss_info_10b7_9005 pci_ss_info_10b7_9005_10b7_9005 +static const pciSubsystemInfo pci_ss_info_10b7_9054_10b7_9054 = + {0x10b7, 0x9054, pci_subsys_10b7_9054_10b7_9054, 0}; +#undef pci_ss_info_10b7_9054 +#define pci_ss_info_10b7_9054 pci_ss_info_10b7_9054_10b7_9054 +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0080 = + {0x1028, 0x0080, pci_subsys_10b7_9055_1028_0080, 0}; +#undef pci_ss_info_1028_0080 +#define pci_ss_info_1028_0080 pci_ss_info_10b7_9055_1028_0080 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0081 = + {0x1028, 0x0081, pci_subsys_10b7_9055_1028_0081, 0}; +#undef pci_ss_info_1028_0081 +#define pci_ss_info_1028_0081 pci_ss_info_10b7_9055_1028_0081 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0082 = + {0x1028, 0x0082, pci_subsys_10b7_9055_1028_0082, 0}; +#undef pci_ss_info_1028_0082 +#define pci_ss_info_1028_0082 pci_ss_info_10b7_9055_1028_0082 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0083 = + {0x1028, 0x0083, pci_subsys_10b7_9055_1028_0083, 0}; +#undef pci_ss_info_1028_0083 +#define pci_ss_info_1028_0083 pci_ss_info_10b7_9055_1028_0083 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0084 = + {0x1028, 0x0084, pci_subsys_10b7_9055_1028_0084, 0}; +#undef pci_ss_info_1028_0084 +#define pci_ss_info_1028_0084 pci_ss_info_10b7_9055_1028_0084 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0085 = + {0x1028, 0x0085, pci_subsys_10b7_9055_1028_0085, 0}; +#undef pci_ss_info_1028_0085 +#define pci_ss_info_1028_0085 pci_ss_info_10b7_9055_1028_0085 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0086 = + {0x1028, 0x0086, pci_subsys_10b7_9055_1028_0086, 0}; +#undef pci_ss_info_1028_0086 +#define pci_ss_info_1028_0086 pci_ss_info_10b7_9055_1028_0086 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0087 = + {0x1028, 0x0087, pci_subsys_10b7_9055_1028_0087, 0}; +#undef pci_ss_info_1028_0087 +#define pci_ss_info_1028_0087 pci_ss_info_10b7_9055_1028_0087 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0088 = + {0x1028, 0x0088, pci_subsys_10b7_9055_1028_0088, 0}; +#undef pci_ss_info_1028_0088 +#define pci_ss_info_1028_0088 pci_ss_info_10b7_9055_1028_0088 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0089 = + {0x1028, 0x0089, pci_subsys_10b7_9055_1028_0089, 0}; +#undef pci_ss_info_1028_0089 +#define pci_ss_info_1028_0089 pci_ss_info_10b7_9055_1028_0089 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0090 = + {0x1028, 0x0090, pci_subsys_10b7_9055_1028_0090, 0}; +#undef pci_ss_info_1028_0090 +#define pci_ss_info_1028_0090 pci_ss_info_10b7_9055_1028_0090 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0091 = + {0x1028, 0x0091, pci_subsys_10b7_9055_1028_0091, 0}; +#undef pci_ss_info_1028_0091 +#define pci_ss_info_1028_0091 pci_ss_info_10b7_9055_1028_0091 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0092 = + {0x1028, 0x0092, pci_subsys_10b7_9055_1028_0092, 0}; +#undef pci_ss_info_1028_0092 +#define pci_ss_info_1028_0092 pci_ss_info_10b7_9055_1028_0092 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0093 = + {0x1028, 0x0093, pci_subsys_10b7_9055_1028_0093, 0}; +#undef pci_ss_info_1028_0093 +#define pci_ss_info_1028_0093 pci_ss_info_10b7_9055_1028_0093 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0094 = + {0x1028, 0x0094, pci_subsys_10b7_9055_1028_0094, 0}; +#undef pci_ss_info_1028_0094 +#define pci_ss_info_1028_0094 pci_ss_info_10b7_9055_1028_0094 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0095 = + {0x1028, 0x0095, pci_subsys_10b7_9055_1028_0095, 0}; +#undef pci_ss_info_1028_0095 +#define pci_ss_info_1028_0095 pci_ss_info_10b7_9055_1028_0095 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0096 = + {0x1028, 0x0096, pci_subsys_10b7_9055_1028_0096, 0}; +#undef pci_ss_info_1028_0096 +#define pci_ss_info_1028_0096 pci_ss_info_10b7_9055_1028_0096 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0097 = + {0x1028, 0x0097, pci_subsys_10b7_9055_1028_0097, 0}; +#undef pci_ss_info_1028_0097 +#define pci_ss_info_1028_0097 pci_ss_info_10b7_9055_1028_0097 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0098 = + {0x1028, 0x0098, pci_subsys_10b7_9055_1028_0098, 0}; +#undef pci_ss_info_1028_0098 +#define pci_ss_info_1028_0098 pci_ss_info_10b7_9055_1028_0098 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9055_1028_0099 = + {0x1028, 0x0099, pci_subsys_10b7_9055_1028_0099, 0}; +#undef pci_ss_info_1028_0099 +#define pci_ss_info_1028_0099 pci_ss_info_10b7_9055_1028_0099 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b7_9055_10b7_9055 = + {0x10b7, 0x9055, pci_subsys_10b7_9055_10b7_9055, 0}; +#undef pci_ss_info_10b7_9055 +#define pci_ss_info_10b7_9055 pci_ss_info_10b7_9055_10b7_9055 +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9200_1028_0095 = + {0x1028, 0x0095, pci_subsys_10b7_9200_1028_0095, 0}; +#undef pci_ss_info_1028_0095 +#define pci_ss_info_1028_0095 pci_ss_info_10b7_9200_1028_0095 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9200_1028_0097 = + {0x1028, 0x0097, pci_subsys_10b7_9200_1028_0097, 0}; +#undef pci_ss_info_1028_0097 +#define pci_ss_info_1028_0097 pci_ss_info_10b7_9200_1028_0097 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9200_1028_00fe = + {0x1028, 0x00fe, pci_subsys_10b7_9200_1028_00fe, 0}; +#undef pci_ss_info_1028_00fe +#define pci_ss_info_1028_00fe pci_ss_info_10b7_9200_1028_00fe +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b7_9200_1028_012a = + {0x1028, 0x012a, pci_subsys_10b7_9200_1028_012a, 0}; +#undef pci_ss_info_1028_012a +#define pci_ss_info_1028_012a pci_ss_info_10b7_9200_1028_012a +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b7_9200_10b7_1000 = + {0x10b7, 0x1000, pci_subsys_10b7_9200_10b7_1000, 0}; +#undef pci_ss_info_10b7_1000 +#define pci_ss_info_10b7_1000 pci_ss_info_10b7_9200_10b7_1000 +static const pciSubsystemInfo pci_ss_info_10b7_9200_10b7_7000 = + {0x10b7, 0x7000, pci_subsys_10b7_9200_10b7_7000, 0}; +#undef pci_ss_info_10b7_7000 +#define pci_ss_info_10b7_7000 pci_ss_info_10b7_9200_10b7_7000 +static const pciSubsystemInfo pci_ss_info_10b7_9200_10f1_2466 = + {0x10f1, 0x2466, pci_subsys_10b7_9200_10f1_2466, 0}; +#undef pci_ss_info_10f1_2466 +#define pci_ss_info_10f1_2466 pci_ss_info_10b7_9200_10f1_2466 +static const pciSubsystemInfo pci_ss_info_10b7_9201_1043_80ab = + {0x1043, 0x80ab, pci_subsys_10b7_9201_1043_80ab, 0}; +#undef pci_ss_info_1043_80ab +#define pci_ss_info_1043_80ab pci_ss_info_10b7_9201_1043_80ab +static const pciSubsystemInfo pci_ss_info_10b7_9800_10b7_9800 = + {0x10b7, 0x9800, pci_subsys_10b7_9800_10b7_9800, 0}; +#undef pci_ss_info_10b7_9800 +#define pci_ss_info_10b7_9800 pci_ss_info_10b7_9800_10b7_9800 +static const pciSubsystemInfo pci_ss_info_10b7_9805_10b7_1201 = + {0x10b7, 0x1201, pci_subsys_10b7_9805_10b7_1201, 0}; +#undef pci_ss_info_10b7_1201 +#define pci_ss_info_10b7_1201 pci_ss_info_10b7_9805_10b7_1201 +static const pciSubsystemInfo pci_ss_info_10b7_9805_10b7_1202 = + {0x10b7, 0x1202, pci_subsys_10b7_9805_10b7_1202, 0}; +#undef pci_ss_info_10b7_1202 +#define pci_ss_info_10b7_1202 pci_ss_info_10b7_9805_10b7_1202 +static const pciSubsystemInfo pci_ss_info_10b7_9805_10b7_9805 = + {0x10b7, 0x9805, pci_subsys_10b7_9805_10b7_9805, 0}; +#undef pci_ss_info_10b7_9805 +#define pci_ss_info_10b7_9805 pci_ss_info_10b7_9805_10b7_9805 +static const pciSubsystemInfo pci_ss_info_10b7_9805_10f1_2462 = + {0x10f1, 0x2462, pci_subsys_10b7_9805_10f1_2462, 0}; +#undef pci_ss_info_10f1_2462 +#define pci_ss_info_10f1_2462 pci_ss_info_10b7_9805_10f1_2462 +static const pciSubsystemInfo pci_ss_info_10b7_9904_10b7_1000 = + {0x10b7, 0x1000, pci_subsys_10b7_9904_10b7_1000, 0}; +#undef pci_ss_info_10b7_1000 +#define pci_ss_info_10b7_1000 pci_ss_info_10b7_9904_10b7_1000 +static const pciSubsystemInfo pci_ss_info_10b7_9904_10b7_2000 = + {0x10b7, 0x2000, pci_subsys_10b7_9904_10b7_2000, 0}; +#undef pci_ss_info_10b7_2000 +#define pci_ss_info_10b7_2000 pci_ss_info_10b7_9904_10b7_2000 +static const pciSubsystemInfo pci_ss_info_10b7_9905_10b7_1101 = + {0x10b7, 0x1101, pci_subsys_10b7_9905_10b7_1101, 0}; +#undef pci_ss_info_10b7_1101 +#define pci_ss_info_10b7_1101 pci_ss_info_10b7_9905_10b7_1101 +static const pciSubsystemInfo pci_ss_info_10b7_9905_10b7_1102 = + {0x10b7, 0x1102, pci_subsys_10b7_9905_10b7_1102, 0}; +#undef pci_ss_info_10b7_1102 +#define pci_ss_info_10b7_1102 pci_ss_info_10b7_9905_10b7_1102 +static const pciSubsystemInfo pci_ss_info_10b7_9905_10b7_2101 = + {0x10b7, 0x2101, pci_subsys_10b7_9905_10b7_2101, 0}; +#undef pci_ss_info_10b7_2101 +#define pci_ss_info_10b7_2101 pci_ss_info_10b7_9905_10b7_2101 +static const pciSubsystemInfo pci_ss_info_10b7_9905_10b7_2102 = + {0x10b7, 0x2102, pci_subsys_10b7_9905_10b7_2102, 0}; +#undef pci_ss_info_10b7_2102 +#define pci_ss_info_10b7_2102 pci_ss_info_10b7_9905_10b7_2102 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b8_0005_1055_e000 = + {0x1055, 0xe000, pci_subsys_10b8_0005_1055_e000, 0}; +#undef pci_ss_info_1055_e000 +#define pci_ss_info_1055_e000 pci_ss_info_10b8_0005_1055_e000 +static const pciSubsystemInfo pci_ss_info_10b8_0005_1055_e002 = + {0x1055, 0xe002, pci_subsys_10b8_0005_1055_e002, 0}; +#undef pci_ss_info_1055_e002 +#define pci_ss_info_1055_e002 pci_ss_info_10b8_0005_1055_e002 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a011 = + {0x10b8, 0xa011, pci_subsys_10b8_0005_10b8_a011, 0}; +#undef pci_ss_info_10b8_a011 +#define pci_ss_info_10b8_a011 pci_ss_info_10b8_0005_10b8_a011 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a014 = + {0x10b8, 0xa014, pci_subsys_10b8_0005_10b8_a014, 0}; +#undef pci_ss_info_10b8_a014 +#define pci_ss_info_10b8_a014 pci_ss_info_10b8_0005_10b8_a014 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a015 = + {0x10b8, 0xa015, pci_subsys_10b8_0005_10b8_a015, 0}; +#undef pci_ss_info_10b8_a015 +#define pci_ss_info_10b8_a015 pci_ss_info_10b8_0005_10b8_a015 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a016 = + {0x10b8, 0xa016, pci_subsys_10b8_0005_10b8_a016, 0}; +#undef pci_ss_info_10b8_a016 +#define pci_ss_info_10b8_a016 pci_ss_info_10b8_0005_10b8_a016 +static const pciSubsystemInfo pci_ss_info_10b8_0005_10b8_a017 = + {0x10b8, 0xa017, pci_subsys_10b8_0005_10b8_a017, 0}; +#undef pci_ss_info_10b8_a017 +#define pci_ss_info_10b8_a017 pci_ss_info_10b8_0005_10b8_a017 +static const pciSubsystemInfo pci_ss_info_10b8_0006_1055_e100 = + {0x1055, 0xe100, pci_subsys_10b8_0006_1055_e100, 0}; +#undef pci_ss_info_1055_e100 +#define pci_ss_info_1055_e100 pci_ss_info_10b8_0006_1055_e100 +static const pciSubsystemInfo pci_ss_info_10b8_0006_1055_e102 = + {0x1055, 0xe102, pci_subsys_10b8_0006_1055_e102, 0}; +#undef pci_ss_info_1055_e102 +#define pci_ss_info_1055_e102 pci_ss_info_10b8_0006_1055_e102 +static const pciSubsystemInfo pci_ss_info_10b8_0006_1055_e300 = + {0x1055, 0xe300, pci_subsys_10b8_0006_1055_e300, 0}; +#undef pci_ss_info_1055_e300 +#define pci_ss_info_1055_e300 pci_ss_info_10b8_0006_1055_e300 +static const pciSubsystemInfo pci_ss_info_10b8_0006_1055_e302 = + {0x1055, 0xe302, pci_subsys_10b8_0006_1055_e302, 0}; +#undef pci_ss_info_1055_e302 +#define pci_ss_info_1055_e302 pci_ss_info_10b8_0006_1055_e302 +static const pciSubsystemInfo pci_ss_info_10b8_0006_10b8_a012 = + {0x10b8, 0xa012, pci_subsys_10b8_0006_10b8_a012, 0}; +#undef pci_ss_info_10b8_a012 +#define pci_ss_info_10b8_a012 pci_ss_info_10b8_0006_10b8_a012 +static const pciSubsystemInfo pci_ss_info_10b8_0006_13a2_8002 = + {0x13a2, 0x8002, pci_subsys_10b8_0006_13a2_8002, 0}; +#undef pci_ss_info_13a2_8002 +#define pci_ss_info_13a2_8002 pci_ss_info_10b8_0006_13a2_8002 +static const pciSubsystemInfo pci_ss_info_10b8_0006_13a2_8006 = + {0x13a2, 0x8006, pci_subsys_10b8_0006_13a2_8006, 0}; +#undef pci_ss_info_13a2_8006 +#define pci_ss_info_13a2_8006 pci_ss_info_10b8_0006_13a2_8006 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b9_0111_10b9_0111 = + {0x10b9, 0x0111, pci_subsys_10b9_0111_10b9_0111, 0}; +#undef pci_ss_info_10b9_0111 +#define pci_ss_info_10b9_0111 pci_ss_info_10b9_0111_10b9_0111 +static const pciSubsystemInfo pci_ss_info_10b9_1521_10b9_1521 = + {0x10b9, 0x1521, pci_subsys_10b9_1521_10b9_1521, 0}; +#undef pci_ss_info_10b9_1521 +#define pci_ss_info_10b9_1521 pci_ss_info_10b9_1521_10b9_1521 +static const pciSubsystemInfo pci_ss_info_10b9_1523_10b9_1523 = + {0x10b9, 0x1523, pci_subsys_10b9_1523_10b9_1523, 0}; +#undef pci_ss_info_10b9_1523 +#define pci_ss_info_10b9_1523 pci_ss_info_10b9_1523_10b9_1523 +static const pciSubsystemInfo pci_ss_info_10b9_1533_1014_053b = + {0x1014, 0x053b, pci_subsys_10b9_1533_1014_053b, 0}; +#undef pci_ss_info_1014_053b +#define pci_ss_info_1014_053b pci_ss_info_10b9_1533_1014_053b +static const pciSubsystemInfo pci_ss_info_10b9_1533_10b9_1533 = + {0x10b9, 0x1533, pci_subsys_10b9_1533_10b9_1533, 0}; +#undef pci_ss_info_10b9_1533 +#define pci_ss_info_10b9_1533 pci_ss_info_10b9_1533_10b9_1533 +static const pciSubsystemInfo pci_ss_info_10b9_1541_10b9_1541 = + {0x10b9, 0x1541, pci_subsys_10b9_1541_10b9_1541, 0}; +#undef pci_ss_info_10b9_1541 +#define pci_ss_info_10b9_1541 pci_ss_info_10b9_1541_10b9_1541 +static const pciSubsystemInfo pci_ss_info_10b9_5229_1014_050f = + {0x1014, 0x050f, pci_subsys_10b9_5229_1014_050f, 0}; +#undef pci_ss_info_1014_050f +#define pci_ss_info_1014_050f pci_ss_info_10b9_5229_1014_050f +static const pciSubsystemInfo pci_ss_info_10b9_5229_1014_053d = + {0x1014, 0x053d, pci_subsys_10b9_5229_1014_053d, 0}; +#undef pci_ss_info_1014_053d +#define pci_ss_info_1014_053d pci_ss_info_10b9_5229_1014_053d +#endif +static const pciSubsystemInfo pci_ss_info_10b9_5229_103c_0024 = + {0x103c, 0x0024, pci_subsys_10b9_5229_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_10b9_5229_103c_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b9_5229_1043_8053 = + {0x1043, 0x8053, pci_subsys_10b9_5229_1043_8053, 0}; +#undef pci_ss_info_1043_8053 +#define pci_ss_info_1043_8053 pci_ss_info_10b9_5229_1043_8053 +static const pciSubsystemInfo pci_ss_info_10b9_5229_1849_5229 = + {0x1849, 0x5229, pci_subsys_10b9_5229_1849_5229, 0}; +#undef pci_ss_info_1849_5229 +#define pci_ss_info_1849_5229 pci_ss_info_10b9_5229_1849_5229 +static const pciSubsystemInfo pci_ss_info_10b9_5237_1014_0540 = + {0x1014, 0x0540, pci_subsys_10b9_5237_1014_0540, 0}; +#undef pci_ss_info_1014_0540 +#define pci_ss_info_1014_0540 pci_ss_info_10b9_5237_1014_0540 +#endif +static const pciSubsystemInfo pci_ss_info_10b9_5237_103c_0024 = + {0x103c, 0x0024, pci_subsys_10b9_5237_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_10b9_5237_103c_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10b9_5237_104d_810f = + {0x104d, 0x810f, pci_subsys_10b9_5237_104d_810f, 0}; +#undef pci_ss_info_104d_810f +#define pci_ss_info_104d_810f pci_ss_info_10b9_5237_104d_810f +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b9_5451_1014_0506 = + {0x1014, 0x0506, pci_subsys_10b9_5451_1014_0506, 0}; +#undef pci_ss_info_1014_0506 +#define pci_ss_info_1014_0506 pci_ss_info_10b9_5451_1014_0506 +static const pciSubsystemInfo pci_ss_info_10b9_5451_1014_053e = + {0x1014, 0x053e, pci_subsys_10b9_5451_1014_053e, 0}; +#undef pci_ss_info_1014_053e +#define pci_ss_info_1014_053e pci_ss_info_10b9_5451_1014_053e +#endif +static const pciSubsystemInfo pci_ss_info_10b9_5451_103c_0024 = + {0x103c, 0x0024, pci_subsys_10b9_5451_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_10b9_5451_103c_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b9_5451_10b9_5451 = + {0x10b9, 0x5451, pci_subsys_10b9_5451_10b9_5451, 0}; +#undef pci_ss_info_10b9_5451 +#define pci_ss_info_10b9_5451 pci_ss_info_10b9_5451_10b9_5451 +static const pciSubsystemInfo pci_ss_info_10b9_5457_1014_0535 = + {0x1014, 0x0535, pci_subsys_10b9_5457_1014_0535, 0}; +#undef pci_ss_info_1014_0535 +#define pci_ss_info_1014_0535 pci_ss_info_10b9_5457_1014_0535 +#endif +static const pciSubsystemInfo pci_ss_info_10b9_5457_103c_0024 = + {0x103c, 0x0024, pci_subsys_10b9_5457_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_10b9_5457_103c_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10b9_7101_1014_0510 = + {0x1014, 0x0510, pci_subsys_10b9_7101_1014_0510, 0}; +#undef pci_ss_info_1014_0510 +#define pci_ss_info_1014_0510 pci_ss_info_10b9_7101_1014_0510 +static const pciSubsystemInfo pci_ss_info_10b9_7101_1014_053c = + {0x1014, 0x053c, pci_subsys_10b9_7101_1014_053c, 0}; +#undef pci_ss_info_1014_053c +#define pci_ss_info_1014_053c pci_ss_info_10b9_7101_1014_053c +#endif +static const pciSubsystemInfo pci_ss_info_10b9_7101_103c_0024 = + {0x103c, 0x0024, pci_subsys_10b9_7101_103c_0024, 0}; +#undef pci_ss_info_103c_0024 +#define pci_ss_info_103c_0024 pci_ss_info_10b9_7101_103c_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10c8_0004_1014_00ba = + {0x1014, 0x00ba, pci_subsys_10c8_0004_1014_00ba, 0}; +#undef pci_ss_info_1014_00ba +#define pci_ss_info_1014_00ba pci_ss_info_10c8_0004_1014_00ba +static const pciSubsystemInfo pci_ss_info_10c8_0004_1025_1007 = + {0x1025, 0x1007, pci_subsys_10c8_0004_1025_1007, 0}; +#undef pci_ss_info_1025_1007 +#define pci_ss_info_1025_1007 pci_ss_info_10c8_0004_1025_1007 +static const pciSubsystemInfo pci_ss_info_10c8_0004_1028_0074 = + {0x1028, 0x0074, pci_subsys_10c8_0004_1028_0074, 0}; +#undef pci_ss_info_1028_0074 +#define pci_ss_info_1028_0074 pci_ss_info_10c8_0004_1028_0074 +static const pciSubsystemInfo pci_ss_info_10c8_0004_1028_0075 = + {0x1028, 0x0075, pci_subsys_10c8_0004_1028_0075, 0}; +#undef pci_ss_info_1028_0075 +#define pci_ss_info_1028_0075 pci_ss_info_10c8_0004_1028_0075 +static const pciSubsystemInfo pci_ss_info_10c8_0004_1028_007d = + {0x1028, 0x007d, pci_subsys_10c8_0004_1028_007d, 0}; +#undef pci_ss_info_1028_007d +#define pci_ss_info_1028_007d pci_ss_info_10c8_0004_1028_007d +static const pciSubsystemInfo pci_ss_info_10c8_0004_1028_007e = + {0x1028, 0x007e, pci_subsys_10c8_0004_1028_007e, 0}; +#undef pci_ss_info_1028_007e +#define pci_ss_info_1028_007e pci_ss_info_10c8_0004_1028_007e +static const pciSubsystemInfo pci_ss_info_10c8_0004_1033_802f = + {0x1033, 0x802f, pci_subsys_10c8_0004_1033_802f, 0}; +#undef pci_ss_info_1033_802f +#define pci_ss_info_1033_802f pci_ss_info_10c8_0004_1033_802f +static const pciSubsystemInfo pci_ss_info_10c8_0004_104d_801b = + {0x104d, 0x801b, pci_subsys_10c8_0004_104d_801b, 0}; +#undef pci_ss_info_104d_801b +#define pci_ss_info_104d_801b pci_ss_info_10c8_0004_104d_801b +static const pciSubsystemInfo pci_ss_info_10c8_0004_104d_802f = + {0x104d, 0x802f, pci_subsys_10c8_0004_104d_802f, 0}; +#undef pci_ss_info_104d_802f +#define pci_ss_info_104d_802f pci_ss_info_10c8_0004_104d_802f +static const pciSubsystemInfo pci_ss_info_10c8_0004_104d_830b = + {0x104d, 0x830b, pci_subsys_10c8_0004_104d_830b, 0}; +#undef pci_ss_info_104d_830b +#define pci_ss_info_104d_830b pci_ss_info_10c8_0004_104d_830b +static const pciSubsystemInfo pci_ss_info_10c8_0004_10ba_0e00 = + {0x10ba, 0x0e00, pci_subsys_10c8_0004_10ba_0e00, 0}; +#undef pci_ss_info_10ba_0e00 +#define pci_ss_info_10ba_0e00 pci_ss_info_10c8_0004_10ba_0e00 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10c8_0004 = + {0x10c8, 0x0004, pci_subsys_10c8_0004_10c8_0004, 0}; +#undef pci_ss_info_10c8_0004 +#define pci_ss_info_10c8_0004 pci_ss_info_10c8_0004_10c8_0004 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10cf_1029 = + {0x10cf, 0x1029, pci_subsys_10c8_0004_10cf_1029, 0}; +#undef pci_ss_info_10cf_1029 +#define pci_ss_info_10cf_1029 pci_ss_info_10c8_0004_10cf_1029 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_8308 = + {0x10f7, 0x8308, pci_subsys_10c8_0004_10f7_8308, 0}; +#undef pci_ss_info_10f7_8308 +#define pci_ss_info_10f7_8308 pci_ss_info_10c8_0004_10f7_8308 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_8309 = + {0x10f7, 0x8309, pci_subsys_10c8_0004_10f7_8309, 0}; +#undef pci_ss_info_10f7_8309 +#define pci_ss_info_10f7_8309 pci_ss_info_10c8_0004_10f7_8309 +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_830b = + {0x10f7, 0x830b, pci_subsys_10c8_0004_10f7_830b, 0}; +#undef pci_ss_info_10f7_830b +#define pci_ss_info_10f7_830b pci_ss_info_10c8_0004_10f7_830b +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_830d = + {0x10f7, 0x830d, pci_subsys_10c8_0004_10f7_830d, 0}; +#undef pci_ss_info_10f7_830d +#define pci_ss_info_10f7_830d pci_ss_info_10c8_0004_10f7_830d +static const pciSubsystemInfo pci_ss_info_10c8_0004_10f7_8312 = + {0x10f7, 0x8312, pci_subsys_10c8_0004_10f7_8312, 0}; +#undef pci_ss_info_10f7_8312 +#define pci_ss_info_10f7_8312 pci_ss_info_10c8_0004_10f7_8312 +static const pciSubsystemInfo pci_ss_info_10c8_0005_1014_00dd = + {0x1014, 0x00dd, pci_subsys_10c8_0005_1014_00dd, 0}; +#undef pci_ss_info_1014_00dd +#define pci_ss_info_1014_00dd pci_ss_info_10c8_0005_1014_00dd +static const pciSubsystemInfo pci_ss_info_10c8_0005_1028_0088 = + {0x1028, 0x0088, pci_subsys_10c8_0005_1028_0088, 0}; +#undef pci_ss_info_1028_0088 +#define pci_ss_info_1028_0088 pci_ss_info_10c8_0005_1028_0088 +static const pciSubsystemInfo pci_ss_info_10c8_0016_10c8_0016 = + {0x10c8, 0x0016, pci_subsys_10c8_0016_10c8_0016, 0}; +#undef pci_ss_info_10c8_0016 +#define pci_ss_info_10c8_0016 pci_ss_info_10c8_0016_10c8_0016 +static const pciSubsystemInfo pci_ss_info_10c8_8005_0e11_b0d1 = + {0x0e11, 0xb0d1, pci_subsys_10c8_8005_0e11_b0d1, 0}; +#undef pci_ss_info_0e11_b0d1 +#define pci_ss_info_0e11_b0d1 pci_ss_info_10c8_8005_0e11_b0d1 +static const pciSubsystemInfo pci_ss_info_10c8_8005_0e11_b126 = + {0x0e11, 0xb126, pci_subsys_10c8_8005_0e11_b126, 0}; +#undef pci_ss_info_0e11_b126 +#define pci_ss_info_0e11_b126 pci_ss_info_10c8_8005_0e11_b126 +static const pciSubsystemInfo pci_ss_info_10c8_8005_1014_00dd = + {0x1014, 0x00dd, pci_subsys_10c8_8005_1014_00dd, 0}; +#undef pci_ss_info_1014_00dd +#define pci_ss_info_1014_00dd pci_ss_info_10c8_8005_1014_00dd +static const pciSubsystemInfo pci_ss_info_10c8_8005_1025_1003 = + {0x1025, 0x1003, pci_subsys_10c8_8005_1025_1003, 0}; +#undef pci_ss_info_1025_1003 +#define pci_ss_info_1025_1003 pci_ss_info_10c8_8005_1025_1003 +static const pciSubsystemInfo pci_ss_info_10c8_8005_1028_0088 = + {0x1028, 0x0088, pci_subsys_10c8_8005_1028_0088, 0}; +#undef pci_ss_info_1028_0088 +#define pci_ss_info_1028_0088 pci_ss_info_10c8_8005_1028_0088 +static const pciSubsystemInfo pci_ss_info_10c8_8005_1028_008f = + {0x1028, 0x008f, pci_subsys_10c8_8005_1028_008f, 0}; +#undef pci_ss_info_1028_008f +#define pci_ss_info_1028_008f pci_ss_info_10c8_8005_1028_008f +static const pciSubsystemInfo pci_ss_info_10c8_8005_103c_0007 = + {0x103c, 0x0007, pci_subsys_10c8_8005_103c_0007, 0}; +#undef pci_ss_info_103c_0007 +#define pci_ss_info_103c_0007 pci_ss_info_10c8_8005_103c_0007 +static const pciSubsystemInfo pci_ss_info_10c8_8005_103c_0008 = + {0x103c, 0x0008, pci_subsys_10c8_8005_103c_0008, 0}; +#undef pci_ss_info_103c_0008 +#define pci_ss_info_103c_0008 pci_ss_info_10c8_8005_103c_0008 +static const pciSubsystemInfo pci_ss_info_10c8_8005_103c_000d = + {0x103c, 0x000d, pci_subsys_10c8_8005_103c_000d, 0}; +#undef pci_ss_info_103c_000d +#define pci_ss_info_103c_000d pci_ss_info_10c8_8005_103c_000d +static const pciSubsystemInfo pci_ss_info_10c8_8005_10c8_8005 = + {0x10c8, 0x8005, pci_subsys_10c8_8005_10c8_8005, 0}; +#undef pci_ss_info_10c8_8005 +#define pci_ss_info_10c8_8005 pci_ss_info_10c8_8005_10c8_8005 +static const pciSubsystemInfo pci_ss_info_10c8_8005_110a_8005 = + {0x110a, 0x8005, pci_subsys_10c8_8005_110a_8005, 0}; +#undef pci_ss_info_110a_8005 +#define pci_ss_info_110a_8005 pci_ss_info_10c8_8005_110a_8005 +static const pciSubsystemInfo pci_ss_info_10c8_8005_14c0_0004 = + {0x14c0, 0x0004, pci_subsys_10c8_8005_14c0_0004, 0}; +#undef pci_ss_info_14c0_0004 +#define pci_ss_info_14c0_0004 pci_ss_info_10c8_8005_14c0_0004 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10cd_1300_10cd_1310 = + {0x10cd, 0x1310, pci_subsys_10cd_1300_10cd_1310, 0}; +#undef pci_ss_info_10cd_1310 +#define pci_ss_info_10cd_1310 pci_ss_info_10cd_1300_10cd_1310 +static const pciSubsystemInfo pci_ss_info_10cd_1300_1195_1320 = + {0x1195, 0x1320, pci_subsys_10cd_1300_1195_1320, 0}; +#undef pci_ss_info_1195_1320 +#define pci_ss_info_1195_1320 pci_ss_info_10cd_1300_1195_1320 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10d9_0531_1186_1200 = + {0x1186, 0x1200, pci_subsys_10d9_0531_1186_1200, 0}; +#undef pci_ss_info_1186_1200 +#define pci_ss_info_1186_1200 pci_ss_info_10d9_0531_1186_1200 +#endif +static const pciSubsystemInfo pci_ss_info_10de_0020_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_0020_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_0020_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_0020_1048_0c18 = + {0x1048, 0x0c18, pci_subsys_10de_0020_1048_0c18, 0}; +#undef pci_ss_info_1048_0c18 +#define pci_ss_info_1048_0c18 pci_ss_info_10de_0020_1048_0c18 +static const pciSubsystemInfo pci_ss_info_10de_0020_1048_0c19 = + {0x1048, 0x0c19, pci_subsys_10de_0020_1048_0c19, 0}; +#undef pci_ss_info_1048_0c19 +#define pci_ss_info_1048_0c19 pci_ss_info_10de_0020_1048_0c19 +static const pciSubsystemInfo pci_ss_info_10de_0020_1048_0c1b = + {0x1048, 0x0c1b, pci_subsys_10de_0020_1048_0c1b, 0}; +#undef pci_ss_info_1048_0c1b +#define pci_ss_info_1048_0c1b pci_ss_info_10de_0020_1048_0c1b +static const pciSubsystemInfo pci_ss_info_10de_0020_1048_0c1c = + {0x1048, 0x0c1c, pci_subsys_10de_0020_1048_0c1c, 0}; +#undef pci_ss_info_1048_0c1c +#define pci_ss_info_1048_0c1c pci_ss_info_10de_0020_1048_0c1c +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_0550 = + {0x1092, 0x0550, pci_subsys_10de_0020_1092_0550, 0}; +#undef pci_ss_info_1092_0550 +#define pci_ss_info_1092_0550 pci_ss_info_10de_0020_1092_0550 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_0552 = + {0x1092, 0x0552, pci_subsys_10de_0020_1092_0552, 0}; +#undef pci_ss_info_1092_0552 +#define pci_ss_info_1092_0552 pci_ss_info_10de_0020_1092_0552 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4804 = + {0x1092, 0x4804, pci_subsys_10de_0020_1092_4804, 0}; +#undef pci_ss_info_1092_4804 +#define pci_ss_info_1092_4804 pci_ss_info_10de_0020_1092_4804 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4808 = + {0x1092, 0x4808, pci_subsys_10de_0020_1092_4808, 0}; +#undef pci_ss_info_1092_4808 +#define pci_ss_info_1092_4808 pci_ss_info_10de_0020_1092_4808 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4810 = + {0x1092, 0x4810, pci_subsys_10de_0020_1092_4810, 0}; +#undef pci_ss_info_1092_4810 +#define pci_ss_info_1092_4810 pci_ss_info_10de_0020_1092_4810 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4812 = + {0x1092, 0x4812, pci_subsys_10de_0020_1092_4812, 0}; +#undef pci_ss_info_1092_4812 +#define pci_ss_info_1092_4812 pci_ss_info_10de_0020_1092_4812 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4815 = + {0x1092, 0x4815, pci_subsys_10de_0020_1092_4815, 0}; +#undef pci_ss_info_1092_4815 +#define pci_ss_info_1092_4815 pci_ss_info_10de_0020_1092_4815 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4820 = + {0x1092, 0x4820, pci_subsys_10de_0020_1092_4820, 0}; +#undef pci_ss_info_1092_4820 +#define pci_ss_info_1092_4820 pci_ss_info_10de_0020_1092_4820 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4822 = + {0x1092, 0x4822, pci_subsys_10de_0020_1092_4822, 0}; +#undef pci_ss_info_1092_4822 +#define pci_ss_info_1092_4822 pci_ss_info_10de_0020_1092_4822 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4904 = + {0x1092, 0x4904, pci_subsys_10de_0020_1092_4904, 0}; +#undef pci_ss_info_1092_4904 +#define pci_ss_info_1092_4904 pci_ss_info_10de_0020_1092_4904 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_4914 = + {0x1092, 0x4914, pci_subsys_10de_0020_1092_4914, 0}; +#undef pci_ss_info_1092_4914 +#define pci_ss_info_1092_4914 pci_ss_info_10de_0020_1092_4914 +static const pciSubsystemInfo pci_ss_info_10de_0020_1092_8225 = + {0x1092, 0x8225, pci_subsys_10de_0020_1092_8225, 0}; +#undef pci_ss_info_1092_8225 +#define pci_ss_info_1092_8225 pci_ss_info_10de_0020_1092_8225 +static const pciSubsystemInfo pci_ss_info_10de_0020_10b4_273d = + {0x10b4, 0x273d, pci_subsys_10de_0020_10b4_273d, 0}; +#undef pci_ss_info_10b4_273d +#define pci_ss_info_10b4_273d pci_ss_info_10de_0020_10b4_273d +static const pciSubsystemInfo pci_ss_info_10de_0020_10b4_273e = + {0x10b4, 0x273e, pci_subsys_10de_0020_10b4_273e, 0}; +#undef pci_ss_info_10b4_273e +#define pci_ss_info_10b4_273e pci_ss_info_10de_0020_10b4_273e +static const pciSubsystemInfo pci_ss_info_10de_0020_10b4_2740 = + {0x10b4, 0x2740, pci_subsys_10de_0020_10b4_2740, 0}; +#undef pci_ss_info_10b4_2740 +#define pci_ss_info_10b4_2740 pci_ss_info_10de_0020_10b4_2740 +static const pciSubsystemInfo pci_ss_info_10de_0020_10de_0020 = + {0x10de, 0x0020, pci_subsys_10de_0020_10de_0020, 0}; +#undef pci_ss_info_10de_0020 +#define pci_ss_info_10de_0020 pci_ss_info_10de_0020_10de_0020 +static const pciSubsystemInfo pci_ss_info_10de_0020_1102_1015 = + {0x1102, 0x1015, pci_subsys_10de_0020_1102_1015, 0}; +#undef pci_ss_info_1102_1015 +#define pci_ss_info_1102_1015 pci_ss_info_10de_0020_1102_1015 +static const pciSubsystemInfo pci_ss_info_10de_0020_1102_1016 = + {0x1102, 0x1016, pci_subsys_10de_0020_1102_1016, 0}; +#undef pci_ss_info_1102_1016 +#define pci_ss_info_1102_1016 pci_ss_info_10de_0020_1102_1016 +static const pciSubsystemInfo pci_ss_info_10de_0028_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_0028_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_0028_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_0028_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_0028_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_0028_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_0028_1043_0205 = + {0x1043, 0x0205, pci_subsys_10de_0028_1043_0205, 0}; +#undef pci_ss_info_1043_0205 +#define pci_ss_info_1043_0205 pci_ss_info_10de_0028_1043_0205 +static const pciSubsystemInfo pci_ss_info_10de_0028_1043_4000 = + {0x1043, 0x4000, pci_subsys_10de_0028_1043_4000, 0}; +#undef pci_ss_info_1043_4000 +#define pci_ss_info_1043_4000 pci_ss_info_10de_0028_1043_4000 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c21 = + {0x1048, 0x0c21, pci_subsys_10de_0028_1048_0c21, 0}; +#undef pci_ss_info_1048_0c21 +#define pci_ss_info_1048_0c21 pci_ss_info_10de_0028_1048_0c21 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c28 = + {0x1048, 0x0c28, pci_subsys_10de_0028_1048_0c28, 0}; +#undef pci_ss_info_1048_0c28 +#define pci_ss_info_1048_0c28 pci_ss_info_10de_0028_1048_0c28 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c29 = + {0x1048, 0x0c29, pci_subsys_10de_0028_1048_0c29, 0}; +#undef pci_ss_info_1048_0c29 +#define pci_ss_info_1048_0c29 pci_ss_info_10de_0028_1048_0c29 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c2a = + {0x1048, 0x0c2a, pci_subsys_10de_0028_1048_0c2a, 0}; +#undef pci_ss_info_1048_0c2a +#define pci_ss_info_1048_0c2a pci_ss_info_10de_0028_1048_0c2a +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c2b = + {0x1048, 0x0c2b, pci_subsys_10de_0028_1048_0c2b, 0}; +#undef pci_ss_info_1048_0c2b +#define pci_ss_info_1048_0c2b pci_ss_info_10de_0028_1048_0c2b +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c31 = + {0x1048, 0x0c31, pci_subsys_10de_0028_1048_0c31, 0}; +#undef pci_ss_info_1048_0c31 +#define pci_ss_info_1048_0c31 pci_ss_info_10de_0028_1048_0c31 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c32 = + {0x1048, 0x0c32, pci_subsys_10de_0028_1048_0c32, 0}; +#undef pci_ss_info_1048_0c32 +#define pci_ss_info_1048_0c32 pci_ss_info_10de_0028_1048_0c32 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c33 = + {0x1048, 0x0c33, pci_subsys_10de_0028_1048_0c33, 0}; +#undef pci_ss_info_1048_0c33 +#define pci_ss_info_1048_0c33 pci_ss_info_10de_0028_1048_0c33 +static const pciSubsystemInfo pci_ss_info_10de_0028_1048_0c34 = + {0x1048, 0x0c34, pci_subsys_10de_0028_1048_0c34, 0}; +#undef pci_ss_info_1048_0c34 +#define pci_ss_info_1048_0c34 pci_ss_info_10de_0028_1048_0c34 +static const pciSubsystemInfo pci_ss_info_10de_0028_107d_2134 = + {0x107d, 0x2134, pci_subsys_10de_0028_107d_2134, 0}; +#undef pci_ss_info_107d_2134 +#define pci_ss_info_107d_2134 pci_ss_info_10de_0028_107d_2134 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_4804 = + {0x1092, 0x4804, pci_subsys_10de_0028_1092_4804, 0}; +#undef pci_ss_info_1092_4804 +#define pci_ss_info_1092_4804 pci_ss_info_10de_0028_1092_4804 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_4a00 = + {0x1092, 0x4a00, pci_subsys_10de_0028_1092_4a00, 0}; +#undef pci_ss_info_1092_4a00 +#define pci_ss_info_1092_4a00 pci_ss_info_10de_0028_1092_4a00 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_4a02 = + {0x1092, 0x4a02, pci_subsys_10de_0028_1092_4a02, 0}; +#undef pci_ss_info_1092_4a02 +#define pci_ss_info_1092_4a02 pci_ss_info_10de_0028_1092_4a02 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_5a00 = + {0x1092, 0x5a00, pci_subsys_10de_0028_1092_5a00, 0}; +#undef pci_ss_info_1092_5a00 +#define pci_ss_info_1092_5a00 pci_ss_info_10de_0028_1092_5a00 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_6a02 = + {0x1092, 0x6a02, pci_subsys_10de_0028_1092_6a02, 0}; +#undef pci_ss_info_1092_6a02 +#define pci_ss_info_1092_6a02 pci_ss_info_10de_0028_1092_6a02 +static const pciSubsystemInfo pci_ss_info_10de_0028_1092_7a02 = + {0x1092, 0x7a02, pci_subsys_10de_0028_1092_7a02, 0}; +#undef pci_ss_info_1092_7a02 +#define pci_ss_info_1092_7a02 pci_ss_info_10de_0028_1092_7a02 +static const pciSubsystemInfo pci_ss_info_10de_0028_10de_0005 = + {0x10de, 0x0005, pci_subsys_10de_0028_10de_0005, 0}; +#undef pci_ss_info_10de_0005 +#define pci_ss_info_10de_0005 pci_ss_info_10de_0028_10de_0005 +static const pciSubsystemInfo pci_ss_info_10de_0028_10de_000f = + {0x10de, 0x000f, pci_subsys_10de_0028_10de_000f, 0}; +#undef pci_ss_info_10de_000f +#define pci_ss_info_10de_000f pci_ss_info_10de_0028_10de_000f +static const pciSubsystemInfo pci_ss_info_10de_0028_1102_1020 = + {0x1102, 0x1020, pci_subsys_10de_0028_1102_1020, 0}; +#undef pci_ss_info_1102_1020 +#define pci_ss_info_1102_1020 pci_ss_info_10de_0028_1102_1020 +static const pciSubsystemInfo pci_ss_info_10de_0028_1102_1026 = + {0x1102, 0x1026, pci_subsys_10de_0028_1102_1026, 0}; +#undef pci_ss_info_1102_1026 +#define pci_ss_info_1102_1026 pci_ss_info_10de_0028_1102_1026 +static const pciSubsystemInfo pci_ss_info_10de_0028_14af_5810 = + {0x14af, 0x5810, pci_subsys_10de_0028_14af_5810, 0}; +#undef pci_ss_info_14af_5810 +#define pci_ss_info_14af_5810 pci_ss_info_10de_0028_14af_5810 +static const pciSubsystemInfo pci_ss_info_10de_0029_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_0029_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_0029_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_0029_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_0029_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_0029_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_0029_1043_0205 = + {0x1043, 0x0205, pci_subsys_10de_0029_1043_0205, 0}; +#undef pci_ss_info_1043_0205 +#define pci_ss_info_1043_0205 pci_ss_info_10de_0029_1043_0205 +static const pciSubsystemInfo pci_ss_info_10de_0029_1048_0c2e = + {0x1048, 0x0c2e, pci_subsys_10de_0029_1048_0c2e, 0}; +#undef pci_ss_info_1048_0c2e +#define pci_ss_info_1048_0c2e pci_ss_info_10de_0029_1048_0c2e +static const pciSubsystemInfo pci_ss_info_10de_0029_1048_0c2f = + {0x1048, 0x0c2f, pci_subsys_10de_0029_1048_0c2f, 0}; +#undef pci_ss_info_1048_0c2f +#define pci_ss_info_1048_0c2f pci_ss_info_10de_0029_1048_0c2f +static const pciSubsystemInfo pci_ss_info_10de_0029_1048_0c30 = + {0x1048, 0x0c30, pci_subsys_10de_0029_1048_0c30, 0}; +#undef pci_ss_info_1048_0c30 +#define pci_ss_info_1048_0c30 pci_ss_info_10de_0029_1048_0c30 +static const pciSubsystemInfo pci_ss_info_10de_0029_1102_1021 = + {0x1102, 0x1021, pci_subsys_10de_0029_1102_1021, 0}; +#undef pci_ss_info_1102_1021 +#define pci_ss_info_1102_1021 pci_ss_info_10de_0029_1102_1021 +static const pciSubsystemInfo pci_ss_info_10de_0029_1102_1029 = + {0x1102, 0x1029, pci_subsys_10de_0029_1102_1029, 0}; +#undef pci_ss_info_1102_1029 +#define pci_ss_info_1102_1029 pci_ss_info_10de_0029_1102_1029 +static const pciSubsystemInfo pci_ss_info_10de_0029_1102_102f = + {0x1102, 0x102f, pci_subsys_10de_0029_1102_102f, 0}; +#undef pci_ss_info_1102_102f +#define pci_ss_info_1102_102f pci_ss_info_10de_0029_1102_102f +static const pciSubsystemInfo pci_ss_info_10de_0029_14af_5820 = + {0x14af, 0x5820, pci_subsys_10de_0029_14af_5820, 0}; +#undef pci_ss_info_14af_5820 +#define pci_ss_info_14af_5820 pci_ss_info_10de_0029_14af_5820 +static const pciSubsystemInfo pci_ss_info_10de_002c_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_002c_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_002c_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_002c_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_002c_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_002c_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_002c_1048_0c20 = + {0x1048, 0x0c20, pci_subsys_10de_002c_1048_0c20, 0}; +#undef pci_ss_info_1048_0c20 +#define pci_ss_info_1048_0c20 pci_ss_info_10de_002c_1048_0c20 +static const pciSubsystemInfo pci_ss_info_10de_002c_1048_0c21 = + {0x1048, 0x0c21, pci_subsys_10de_002c_1048_0c21, 0}; +#undef pci_ss_info_1048_0c21 +#define pci_ss_info_1048_0c21 pci_ss_info_10de_002c_1048_0c21 +static const pciSubsystemInfo pci_ss_info_10de_002c_1092_6820 = + {0x1092, 0x6820, pci_subsys_10de_002c_1092_6820, 0}; +#undef pci_ss_info_1092_6820 +#define pci_ss_info_1092_6820 pci_ss_info_10de_002c_1092_6820 +static const pciSubsystemInfo pci_ss_info_10de_002c_1102_1031 = + {0x1102, 0x1031, pci_subsys_10de_002c_1102_1031, 0}; +#undef pci_ss_info_1102_1031 +#define pci_ss_info_1102_1031 pci_ss_info_10de_002c_1102_1031 +static const pciSubsystemInfo pci_ss_info_10de_002c_1102_1034 = + {0x1102, 0x1034, pci_subsys_10de_002c_1102_1034, 0}; +#undef pci_ss_info_1102_1034 +#define pci_ss_info_1102_1034 pci_ss_info_10de_002c_1102_1034 +static const pciSubsystemInfo pci_ss_info_10de_002c_14af_5008 = + {0x14af, 0x5008, pci_subsys_10de_002c_14af_5008, 0}; +#undef pci_ss_info_14af_5008 +#define pci_ss_info_14af_5008 pci_ss_info_10de_002c_14af_5008 +static const pciSubsystemInfo pci_ss_info_10de_002d_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_002d_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_002d_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_002d_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_002d_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_002d_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_002d_1048_0c3a = + {0x1048, 0x0c3a, pci_subsys_10de_002d_1048_0c3a, 0}; +#undef pci_ss_info_1048_0c3a +#define pci_ss_info_1048_0c3a pci_ss_info_10de_002d_1048_0c3a +static const pciSubsystemInfo pci_ss_info_10de_002d_1048_0c3b = + {0x1048, 0x0c3b, pci_subsys_10de_002d_1048_0c3b, 0}; +#undef pci_ss_info_1048_0c3b +#define pci_ss_info_1048_0c3b pci_ss_info_10de_002d_1048_0c3b +static const pciSubsystemInfo pci_ss_info_10de_002d_10de_001e = + {0x10de, 0x001e, pci_subsys_10de_002d_10de_001e, 0}; +#undef pci_ss_info_10de_001e +#define pci_ss_info_10de_001e pci_ss_info_10de_002d_10de_001e +static const pciSubsystemInfo pci_ss_info_10de_002d_1102_1023 = + {0x1102, 0x1023, pci_subsys_10de_002d_1102_1023, 0}; +#undef pci_ss_info_1102_1023 +#define pci_ss_info_1102_1023 pci_ss_info_10de_002d_1102_1023 +static const pciSubsystemInfo pci_ss_info_10de_002d_1102_1024 = + {0x1102, 0x1024, pci_subsys_10de_002d_1102_1024, 0}; +#undef pci_ss_info_1102_1024 +#define pci_ss_info_1102_1024 pci_ss_info_10de_002d_1102_1024 +static const pciSubsystemInfo pci_ss_info_10de_002d_1102_102c = + {0x1102, 0x102c, pci_subsys_10de_002d_1102_102c, 0}; +#undef pci_ss_info_1102_102c +#define pci_ss_info_1102_102c pci_ss_info_10de_002d_1102_102c +static const pciSubsystemInfo pci_ss_info_10de_002d_1462_8808 = + {0x1462, 0x8808, pci_subsys_10de_002d_1462_8808, 0}; +#undef pci_ss_info_1462_8808 +#define pci_ss_info_1462_8808 pci_ss_info_10de_002d_1462_8808 +static const pciSubsystemInfo pci_ss_info_10de_002d_1554_1041 = + {0x1554, 0x1041, pci_subsys_10de_002d_1554_1041, 0}; +#undef pci_ss_info_1554_1041 +#define pci_ss_info_1554_1041 pci_ss_info_10de_002d_1554_1041 +static const pciSubsystemInfo pci_ss_info_10de_002d_1569_002d = + {0x1569, 0x002d, pci_subsys_10de_002d_1569_002d, 0}; +#undef pci_ss_info_1569_002d +#define pci_ss_info_1569_002d pci_ss_info_10de_002d_1569_002d +static const pciSubsystemInfo pci_ss_info_10de_0041_1043_817b = + {0x1043, 0x817b, pci_subsys_10de_0041_1043_817b, 0}; +#undef pci_ss_info_1043_817b +#define pci_ss_info_1043_817b pci_ss_info_10de_0041_1043_817b +static const pciSubsystemInfo pci_ss_info_10de_0047_1682_2109 = + {0x1682, 0x2109, pci_subsys_10de_0047_1682_2109, 0}; +#undef pci_ss_info_1682_2109 +#define pci_ss_info_1682_2109 pci_ss_info_10de_0047_1682_2109 +static const pciSubsystemInfo pci_ss_info_10de_0050_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_0050_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_0050_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_0050_1458_0c11 = + {0x1458, 0x0c11, pci_subsys_10de_0050_1458_0c11, 0}; +#undef pci_ss_info_1458_0c11 +#define pci_ss_info_1458_0c11 pci_ss_info_10de_0050_1458_0c11 +static const pciSubsystemInfo pci_ss_info_10de_0050_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_0050_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_0050_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_0050_147b_1c1a = + {0x147b, 0x1c1a, pci_subsys_10de_0050_147b_1c1a, 0}; +#undef pci_ss_info_147b_1c1a +#define pci_ss_info_147b_1c1a pci_ss_info_10de_0050_147b_1c1a +static const pciSubsystemInfo pci_ss_info_10de_0052_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_0052_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_0052_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_0052_1458_0c11 = + {0x1458, 0x0c11, pci_subsys_10de_0052_1458_0c11, 0}; +#undef pci_ss_info_1458_0c11 +#define pci_ss_info_1458_0c11 pci_ss_info_10de_0052_1458_0c11 +static const pciSubsystemInfo pci_ss_info_10de_0052_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_0052_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_0052_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_0052_147b_1c1a = + {0x147b, 0x1c1a, pci_subsys_10de_0052_147b_1c1a, 0}; +#undef pci_ss_info_147b_1c1a +#define pci_ss_info_147b_1c1a pci_ss_info_10de_0052_147b_1c1a +static const pciSubsystemInfo pci_ss_info_10de_0053_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_0053_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_0053_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_0053_1458_5002 = + {0x1458, 0x5002, pci_subsys_10de_0053_1458_5002, 0}; +#undef pci_ss_info_1458_5002 +#define pci_ss_info_1458_5002 pci_ss_info_10de_0053_1458_5002 +static const pciSubsystemInfo pci_ss_info_10de_0053_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_0053_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_0053_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_0053_147b_1c1a = + {0x147b, 0x1c1a, pci_subsys_10de_0053_147b_1c1a, 0}; +#undef pci_ss_info_147b_1c1a +#define pci_ss_info_147b_1c1a pci_ss_info_10de_0053_147b_1c1a +static const pciSubsystemInfo pci_ss_info_10de_0054_1458_b003 = + {0x1458, 0xb003, pci_subsys_10de_0054_1458_b003, 0}; +#undef pci_ss_info_1458_b003 +#define pci_ss_info_1458_b003 pci_ss_info_10de_0054_1458_b003 +static const pciSubsystemInfo pci_ss_info_10de_0054_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_0054_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_0054_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_0054_147b_1c1a = + {0x147b, 0x1c1a, pci_subsys_10de_0054_147b_1c1a, 0}; +#undef pci_ss_info_147b_1c1a +#define pci_ss_info_147b_1c1a pci_ss_info_10de_0054_147b_1c1a +static const pciSubsystemInfo pci_ss_info_10de_0055_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_0055_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_0055_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_0055_1458_b003 = + {0x1458, 0xb003, pci_subsys_10de_0055_1458_b003, 0}; +#undef pci_ss_info_1458_b003 +#define pci_ss_info_1458_b003 pci_ss_info_10de_0055_1458_b003 +static const pciSubsystemInfo pci_ss_info_10de_0055_147b_1c1a = + {0x147b, 0x1c1a, pci_subsys_10de_0055_147b_1c1a, 0}; +#undef pci_ss_info_147b_1c1a +#define pci_ss_info_147b_1c1a pci_ss_info_10de_0055_147b_1c1a +static const pciSubsystemInfo pci_ss_info_10de_0057_1043_8141 = + {0x1043, 0x8141, pci_subsys_10de_0057_1043_8141, 0}; +#undef pci_ss_info_1043_8141 +#define pci_ss_info_1043_8141 pci_ss_info_10de_0057_1043_8141 +static const pciSubsystemInfo pci_ss_info_10de_0057_1458_e000 = + {0x1458, 0xe000, pci_subsys_10de_0057_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_10de_0057_1458_e000 +static const pciSubsystemInfo pci_ss_info_10de_0057_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_0057_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_0057_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_0057_147b_1c1a = + {0x147b, 0x1c1a, pci_subsys_10de_0057_147b_1c1a, 0}; +#undef pci_ss_info_147b_1c1a +#define pci_ss_info_147b_1c1a pci_ss_info_10de_0057_147b_1c1a +static const pciSubsystemInfo pci_ss_info_10de_0059_1043_812a = + {0x1043, 0x812a, pci_subsys_10de_0059_1043_812a, 0}; +#undef pci_ss_info_1043_812a +#define pci_ss_info_1043_812a pci_ss_info_10de_0059_1043_812a +static const pciSubsystemInfo pci_ss_info_10de_0059_147b_1c1a = + {0x147b, 0x1c1a, pci_subsys_10de_0059_147b_1c1a, 0}; +#undef pci_ss_info_147b_1c1a +#define pci_ss_info_147b_1c1a pci_ss_info_10de_0059_147b_1c1a +static const pciSubsystemInfo pci_ss_info_10de_005a_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_005a_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_005a_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_005a_1458_5004 = + {0x1458, 0x5004, pci_subsys_10de_005a_1458_5004, 0}; +#undef pci_ss_info_1458_5004 +#define pci_ss_info_1458_5004 pci_ss_info_10de_005a_1458_5004 +static const pciSubsystemInfo pci_ss_info_10de_005a_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_005a_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_005a_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_005a_147b_1c1a = + {0x147b, 0x1c1a, pci_subsys_10de_005a_147b_1c1a, 0}; +#undef pci_ss_info_147b_1c1a +#define pci_ss_info_147b_1c1a pci_ss_info_10de_005a_147b_1c1a +static const pciSubsystemInfo pci_ss_info_10de_005b_1043_815a = + {0x1043, 0x815a, pci_subsys_10de_005b_1043_815a, 0}; +#undef pci_ss_info_1043_815a +#define pci_ss_info_1043_815a pci_ss_info_10de_005b_1043_815a +static const pciSubsystemInfo pci_ss_info_10de_005b_1458_5004 = + {0x1458, 0x5004, pci_subsys_10de_005b_1458_5004, 0}; +#undef pci_ss_info_1458_5004 +#define pci_ss_info_1458_5004 pci_ss_info_10de_005b_1458_5004 +static const pciSubsystemInfo pci_ss_info_10de_005b_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_005b_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_005b_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_005b_147b_1c1a = + {0x147b, 0x1c1a, pci_subsys_10de_005b_147b_1c1a, 0}; +#undef pci_ss_info_147b_1c1a +#define pci_ss_info_147b_1c1a pci_ss_info_10de_005b_147b_1c1a +static const pciSubsystemInfo pci_ss_info_10de_005e_10f1_2891 = + {0x10f1, 0x2891, pci_subsys_10de_005e_10f1_2891, 0}; +#undef pci_ss_info_10f1_2891 +#define pci_ss_info_10f1_2891 pci_ss_info_10de_005e_10f1_2891 +static const pciSubsystemInfo pci_ss_info_10de_005e_1458_5000 = + {0x1458, 0x5000, pci_subsys_10de_005e_1458_5000, 0}; +#undef pci_ss_info_1458_5000 +#define pci_ss_info_1458_5000 pci_ss_info_10de_005e_1458_5000 +static const pciSubsystemInfo pci_ss_info_10de_005e_1462_7100 = + {0x1462, 0x7100, pci_subsys_10de_005e_1462_7100, 0}; +#undef pci_ss_info_1462_7100 +#define pci_ss_info_1462_7100 pci_ss_info_10de_005e_1462_7100 +static const pciSubsystemInfo pci_ss_info_10de_005e_147b_1c1a = + {0x147b, 0x1c1a, pci_subsys_10de_005e_147b_1c1a, 0}; +#undef pci_ss_info_147b_1c1a +#define pci_ss_info_147b_1c1a pci_ss_info_10de_005e_147b_1c1a +static const pciSubsystemInfo pci_ss_info_10de_0060_1043_80ad = + {0x1043, 0x80ad, pci_subsys_10de_0060_1043_80ad, 0}; +#undef pci_ss_info_1043_80ad +#define pci_ss_info_1043_80ad pci_ss_info_10de_0060_1043_80ad +static const pciSubsystemInfo pci_ss_info_10de_0060_a0a0_03ba = + {0xa0a0, 0x03ba, pci_subsys_10de_0060_a0a0_03ba, 0}; +#undef pci_ss_info_a0a0_03ba +#define pci_ss_info_a0a0_03ba pci_ss_info_10de_0060_a0a0_03ba +static const pciSubsystemInfo pci_ss_info_10de_0064_a0a0_03bb = + {0xa0a0, 0x03bb, pci_subsys_10de_0064_a0a0_03bb, 0}; +#undef pci_ss_info_a0a0_03bb +#define pci_ss_info_a0a0_03bb pci_ss_info_10de_0064_a0a0_03bb +static const pciSubsystemInfo pci_ss_info_10de_0065_a0a0_03b2 = + {0xa0a0, 0x03b2, pci_subsys_10de_0065_a0a0_03b2, 0}; +#undef pci_ss_info_a0a0_03b2 +#define pci_ss_info_a0a0_03b2 pci_ss_info_10de_0065_a0a0_03b2 +static const pciSubsystemInfo pci_ss_info_10de_0066_1043_80a7 = + {0x1043, 0x80a7, pci_subsys_10de_0066_1043_80a7, 0}; +#undef pci_ss_info_1043_80a7 +#define pci_ss_info_1043_80a7 pci_ss_info_10de_0066_1043_80a7 +static const pciSubsystemInfo pci_ss_info_10de_0067_1043_0c11 = + {0x1043, 0x0c11, pci_subsys_10de_0067_1043_0c11, 0}; +#undef pci_ss_info_1043_0c11 +#define pci_ss_info_1043_0c11 pci_ss_info_10de_0067_1043_0c11 +static const pciSubsystemInfo pci_ss_info_10de_0068_1043_0c11 = + {0x1043, 0x0c11, pci_subsys_10de_0068_1043_0c11, 0}; +#undef pci_ss_info_1043_0c11 +#define pci_ss_info_1043_0c11 pci_ss_info_10de_0068_1043_0c11 +static const pciSubsystemInfo pci_ss_info_10de_0068_a0a0_03b4 = + {0xa0a0, 0x03b4, pci_subsys_10de_0068_a0a0_03b4, 0}; +#undef pci_ss_info_a0a0_03b4 +#define pci_ss_info_a0a0_03b4 pci_ss_info_10de_0068_a0a0_03b4 +static const pciSubsystemInfo pci_ss_info_10de_006a_1043_8095 = + {0x1043, 0x8095, pci_subsys_10de_006a_1043_8095, 0}; +#undef pci_ss_info_1043_8095 +#define pci_ss_info_1043_8095 pci_ss_info_10de_006a_1043_8095 +static const pciSubsystemInfo pci_ss_info_10de_006a_a0a0_0304 = + {0xa0a0, 0x0304, pci_subsys_10de_006a_a0a0_0304, 0}; +#undef pci_ss_info_a0a0_0304 +#define pci_ss_info_a0a0_0304 pci_ss_info_10de_006a_a0a0_0304 +static const pciSubsystemInfo pci_ss_info_10de_006b_10de_006b = + {0x10de, 0x006b, pci_subsys_10de_006b_10de_006b, 0}; +#undef pci_ss_info_10de_006b +#define pci_ss_info_10de_006b pci_ss_info_10de_006b_10de_006b +static const pciSubsystemInfo pci_ss_info_10de_006e_a0a0_0306 = + {0xa0a0, 0x0306, pci_subsys_10de_006e_a0a0_0306, 0}; +#undef pci_ss_info_a0a0_0306 +#define pci_ss_info_a0a0_0306 pci_ss_info_10de_006e_a0a0_0306 +static const pciSubsystemInfo pci_ss_info_10de_0080_147b_1c09 = + {0x147b, 0x1c09, pci_subsys_10de_0080_147b_1c09, 0}; +#undef pci_ss_info_147b_1c09 +#define pci_ss_info_147b_1c09 pci_ss_info_10de_0080_147b_1c09 +static const pciSubsystemInfo pci_ss_info_10de_0084_147b_1c09 = + {0x147b, 0x1c09, pci_subsys_10de_0084_147b_1c09, 0}; +#undef pci_ss_info_147b_1c09 +#define pci_ss_info_147b_1c09 pci_ss_info_10de_0084_147b_1c09 +static const pciSubsystemInfo pci_ss_info_10de_0085_147b_1c09 = + {0x147b, 0x1c09, pci_subsys_10de_0085_147b_1c09, 0}; +#undef pci_ss_info_147b_1c09 +#define pci_ss_info_147b_1c09 pci_ss_info_10de_0085_147b_1c09 +static const pciSubsystemInfo pci_ss_info_10de_0087_147b_1c09 = + {0x147b, 0x1c09, pci_subsys_10de_0087_147b_1c09, 0}; +#undef pci_ss_info_147b_1c09 +#define pci_ss_info_147b_1c09 pci_ss_info_10de_0087_147b_1c09 +static const pciSubsystemInfo pci_ss_info_10de_0088_147b_1c09 = + {0x147b, 0x1c09, pci_subsys_10de_0088_147b_1c09, 0}; +#undef pci_ss_info_147b_1c09 +#define pci_ss_info_147b_1c09 pci_ss_info_10de_0088_147b_1c09 +static const pciSubsystemInfo pci_ss_info_10de_008a_147b_1c09 = + {0x147b, 0x1c09, pci_subsys_10de_008a_147b_1c09, 0}; +#undef pci_ss_info_147b_1c09 +#define pci_ss_info_147b_1c09 pci_ss_info_10de_008a_147b_1c09 +static const pciSubsystemInfo pci_ss_info_10de_00a0_14af_5810 = + {0x14af, 0x5810, pci_subsys_10de_00a0_14af_5810, 0}; +#undef pci_ss_info_14af_5810 +#define pci_ss_info_14af_5810 pci_ss_info_10de_00a0_14af_5810 +static const pciSubsystemInfo pci_ss_info_10de_00cd_10de_029b = + {0x10de, 0x029b, pci_subsys_10de_00cd_10de_029b, 0}; +#undef pci_ss_info_10de_029b +#define pci_ss_info_10de_029b pci_ss_info_10de_00cd_10de_029b +static const pciSubsystemInfo pci_ss_info_10de_00df_105b_0c43 = + {0x105b, 0x0c43, pci_subsys_10de_00df_105b_0c43, 0}; +#undef pci_ss_info_105b_0c43 +#define pci_ss_info_105b_0c43 pci_ss_info_10de_00df_105b_0c43 +static const pciSubsystemInfo pci_ss_info_10de_00df_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00df_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00df_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e0_10de_0c11 = + {0x10de, 0x0c11, pci_subsys_10de_00e0_10de_0c11, 0}; +#undef pci_ss_info_10de_0c11 +#define pci_ss_info_10de_0c11 pci_ss_info_10de_00e0_10de_0c11 +static const pciSubsystemInfo pci_ss_info_10de_00e0_1462_7030 = + {0x1462, 0x7030, pci_subsys_10de_00e0_1462_7030, 0}; +#undef pci_ss_info_1462_7030 +#define pci_ss_info_1462_7030 pci_ss_info_10de_00e0_1462_7030 +static const pciSubsystemInfo pci_ss_info_10de_00e0_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e0_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e0_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e1_1462_7030 = + {0x1462, 0x7030, pci_subsys_10de_00e1_1462_7030, 0}; +#undef pci_ss_info_1462_7030 +#define pci_ss_info_1462_7030 pci_ss_info_10de_00e1_1462_7030 +static const pciSubsystemInfo pci_ss_info_10de_00e1_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e1_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e1_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e3_105b_0c43 = + {0x105b, 0x0c43, pci_subsys_10de_00e3_105b_0c43, 0}; +#undef pci_ss_info_105b_0c43 +#define pci_ss_info_105b_0c43 pci_ss_info_10de_00e3_105b_0c43 +static const pciSubsystemInfo pci_ss_info_10de_00e3_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e3_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e3_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e4_105b_0c43 = + {0x105b, 0x0c43, pci_subsys_10de_00e4_105b_0c43, 0}; +#undef pci_ss_info_105b_0c43 +#define pci_ss_info_105b_0c43 pci_ss_info_10de_00e4_105b_0c43 +static const pciSubsystemInfo pci_ss_info_10de_00e4_1462_7030 = + {0x1462, 0x7030, pci_subsys_10de_00e4_1462_7030, 0}; +#undef pci_ss_info_1462_7030 +#define pci_ss_info_1462_7030 pci_ss_info_10de_00e4_1462_7030 +static const pciSubsystemInfo pci_ss_info_10de_00e4_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e4_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e4_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e5_105b_0c43 = + {0x105b, 0x0c43, pci_subsys_10de_00e5_105b_0c43, 0}; +#undef pci_ss_info_105b_0c43 +#define pci_ss_info_105b_0c43 pci_ss_info_10de_00e5_105b_0c43 +static const pciSubsystemInfo pci_ss_info_10de_00e5_1462_7030 = + {0x1462, 0x7030, pci_subsys_10de_00e5_1462_7030, 0}; +#undef pci_ss_info_1462_7030 +#define pci_ss_info_1462_7030 pci_ss_info_10de_00e5_1462_7030 +static const pciSubsystemInfo pci_ss_info_10de_00e5_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e5_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e5_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e7_105b_0c43 = + {0x105b, 0x0c43, pci_subsys_10de_00e7_105b_0c43, 0}; +#undef pci_ss_info_105b_0c43 +#define pci_ss_info_105b_0c43 pci_ss_info_10de_00e7_105b_0c43 +static const pciSubsystemInfo pci_ss_info_10de_00e7_1462_7030 = + {0x1462, 0x7030, pci_subsys_10de_00e7_1462_7030, 0}; +#undef pci_ss_info_1462_7030 +#define pci_ss_info_1462_7030 pci_ss_info_10de_00e7_1462_7030 +static const pciSubsystemInfo pci_ss_info_10de_00e7_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e7_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e7_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00e8_105b_0c43 = + {0x105b, 0x0c43, pci_subsys_10de_00e8_105b_0c43, 0}; +#undef pci_ss_info_105b_0c43 +#define pci_ss_info_105b_0c43 pci_ss_info_10de_00e8_105b_0c43 +static const pciSubsystemInfo pci_ss_info_10de_00e8_1462_7030 = + {0x1462, 0x7030, pci_subsys_10de_00e8_1462_7030, 0}; +#undef pci_ss_info_1462_7030 +#define pci_ss_info_1462_7030 pci_ss_info_10de_00e8_1462_7030 +static const pciSubsystemInfo pci_ss_info_10de_00e8_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00e8_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00e8_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00ea_105b_0c43 = + {0x105b, 0x0c43, pci_subsys_10de_00ea_105b_0c43, 0}; +#undef pci_ss_info_105b_0c43 +#define pci_ss_info_105b_0c43 pci_ss_info_10de_00ea_105b_0c43 +static const pciSubsystemInfo pci_ss_info_10de_00ea_147b_1c0b = + {0x147b, 0x1c0b, pci_subsys_10de_00ea_147b_1c0b, 0}; +#undef pci_ss_info_147b_1c0b +#define pci_ss_info_147b_1c0b pci_ss_info_10de_00ea_147b_1c0b +static const pciSubsystemInfo pci_ss_info_10de_00f1_1043_81a6 = + {0x1043, 0x81a6, pci_subsys_10de_00f1_1043_81a6, 0}; +#undef pci_ss_info_1043_81a6 +#define pci_ss_info_1043_81a6 pci_ss_info_10de_00f1_1043_81a6 +static const pciSubsystemInfo pci_ss_info_10de_00f1_1682_2119 = + {0x1682, 0x2119, pci_subsys_10de_00f1_1682_2119, 0}; +#undef pci_ss_info_1682_2119 +#define pci_ss_info_1682_2119 pci_ss_info_10de_00f1_1682_2119 +static const pciSubsystemInfo pci_ss_info_10de_00f2_1682_211c = + {0x1682, 0x211c, pci_subsys_10de_00f2_1682_211c, 0}; +#undef pci_ss_info_1682_211c +#define pci_ss_info_1682_211c pci_ss_info_10de_00f2_1682_211c +static const pciSubsystemInfo pci_ss_info_10de_00f6_1682_217e = + {0x1682, 0x217e, pci_subsys_10de_00f6_1682_217e, 0}; +#undef pci_ss_info_1682_217e +#define pci_ss_info_1682_217e pci_ss_info_10de_00f6_1682_217e +static const pciSubsystemInfo pci_ss_info_10de_00f9_1682_2120 = + {0x1682, 0x2120, pci_subsys_10de_00f9_1682_2120, 0}; +#undef pci_ss_info_1682_2120 +#define pci_ss_info_1682_2120 pci_ss_info_10de_00f9_1682_2120 +static const pciSubsystemInfo pci_ss_info_10de_0100_1043_0200 = + {0x1043, 0x0200, pci_subsys_10de_0100_1043_0200, 0}; +#undef pci_ss_info_1043_0200 +#define pci_ss_info_1043_0200 pci_ss_info_10de_0100_1043_0200 +static const pciSubsystemInfo pci_ss_info_10de_0100_1043_0201 = + {0x1043, 0x0201, pci_subsys_10de_0100_1043_0201, 0}; +#undef pci_ss_info_1043_0201 +#define pci_ss_info_1043_0201 pci_ss_info_10de_0100_1043_0201 +static const pciSubsystemInfo pci_ss_info_10de_0100_1043_4008 = + {0x1043, 0x4008, pci_subsys_10de_0100_1043_4008, 0}; +#undef pci_ss_info_1043_4008 +#define pci_ss_info_1043_4008 pci_ss_info_10de_0100_1043_4008 +static const pciSubsystemInfo pci_ss_info_10de_0100_1043_4009 = + {0x1043, 0x4009, pci_subsys_10de_0100_1043_4009, 0}; +#undef pci_ss_info_1043_4009 +#define pci_ss_info_1043_4009 pci_ss_info_10de_0100_1043_4009 +static const pciSubsystemInfo pci_ss_info_10de_0100_1048_0c41 = + {0x1048, 0x0c41, pci_subsys_10de_0100_1048_0c41, 0}; +#undef pci_ss_info_1048_0c41 +#define pci_ss_info_1048_0c41 pci_ss_info_10de_0100_1048_0c41 +static const pciSubsystemInfo pci_ss_info_10de_0100_1048_0c43 = + {0x1048, 0x0c43, pci_subsys_10de_0100_1048_0c43, 0}; +#undef pci_ss_info_1048_0c43 +#define pci_ss_info_1048_0c43 pci_ss_info_10de_0100_1048_0c43 +static const pciSubsystemInfo pci_ss_info_10de_0100_1048_0c48 = + {0x1048, 0x0c48, pci_subsys_10de_0100_1048_0c48, 0}; +#undef pci_ss_info_1048_0c48 +#define pci_ss_info_1048_0c48 pci_ss_info_10de_0100_1048_0c48 +static const pciSubsystemInfo pci_ss_info_10de_0100_1102_102d = + {0x1102, 0x102d, pci_subsys_10de_0100_1102_102d, 0}; +#undef pci_ss_info_1102_102d +#define pci_ss_info_1102_102d pci_ss_info_10de_0100_1102_102d +static const pciSubsystemInfo pci_ss_info_10de_0100_14af_5022 = + {0x14af, 0x5022, pci_subsys_10de_0100_14af_5022, 0}; +#undef pci_ss_info_14af_5022 +#define pci_ss_info_14af_5022 pci_ss_info_10de_0100_14af_5022 +static const pciSubsystemInfo pci_ss_info_10de_0101_1043_0202 = + {0x1043, 0x0202, pci_subsys_10de_0101_1043_0202, 0}; +#undef pci_ss_info_1043_0202 +#define pci_ss_info_1043_0202 pci_ss_info_10de_0101_1043_0202 +static const pciSubsystemInfo pci_ss_info_10de_0101_1043_400a = + {0x1043, 0x400a, pci_subsys_10de_0101_1043_400a, 0}; +#undef pci_ss_info_1043_400a +#define pci_ss_info_1043_400a pci_ss_info_10de_0101_1043_400a +static const pciSubsystemInfo pci_ss_info_10de_0101_1043_400b = + {0x1043, 0x400b, pci_subsys_10de_0101_1043_400b, 0}; +#undef pci_ss_info_1043_400b +#define pci_ss_info_1043_400b pci_ss_info_10de_0101_1043_400b +static const pciSubsystemInfo pci_ss_info_10de_0101_1048_0c42 = + {0x1048, 0x0c42, pci_subsys_10de_0101_1048_0c42, 0}; +#undef pci_ss_info_1048_0c42 +#define pci_ss_info_1048_0c42 pci_ss_info_10de_0101_1048_0c42 +static const pciSubsystemInfo pci_ss_info_10de_0101_107d_2822 = + {0x107d, 0x2822, pci_subsys_10de_0101_107d_2822, 0}; +#undef pci_ss_info_107d_2822 +#define pci_ss_info_107d_2822 pci_ss_info_10de_0101_107d_2822 +static const pciSubsystemInfo pci_ss_info_10de_0101_1102_102e = + {0x1102, 0x102e, pci_subsys_10de_0101_1102_102e, 0}; +#undef pci_ss_info_1102_102e +#define pci_ss_info_1102_102e pci_ss_info_10de_0101_1102_102e +static const pciSubsystemInfo pci_ss_info_10de_0101_14af_5021 = + {0x14af, 0x5021, pci_subsys_10de_0101_14af_5021, 0}; +#undef pci_ss_info_14af_5021 +#define pci_ss_info_14af_5021 pci_ss_info_10de_0101_14af_5021 +static const pciSubsystemInfo pci_ss_info_10de_0103_1048_0c40 = + {0x1048, 0x0c40, pci_subsys_10de_0103_1048_0c40, 0}; +#undef pci_ss_info_1048_0c40 +#define pci_ss_info_1048_0c40 pci_ss_info_10de_0103_1048_0c40 +static const pciSubsystemInfo pci_ss_info_10de_0103_1048_0c44 = + {0x1048, 0x0c44, pci_subsys_10de_0103_1048_0c44, 0}; +#undef pci_ss_info_1048_0c44 +#define pci_ss_info_1048_0c44 pci_ss_info_10de_0103_1048_0c44 +static const pciSubsystemInfo pci_ss_info_10de_0103_1048_0c45 = + {0x1048, 0x0c45, pci_subsys_10de_0103_1048_0c45, 0}; +#undef pci_ss_info_1048_0c45 +#define pci_ss_info_1048_0c45 pci_ss_info_10de_0103_1048_0c45 +static const pciSubsystemInfo pci_ss_info_10de_0103_1048_0c4a = + {0x1048, 0x0c4a, pci_subsys_10de_0103_1048_0c4a, 0}; +#undef pci_ss_info_1048_0c4a +#define pci_ss_info_1048_0c4a pci_ss_info_10de_0103_1048_0c4a +static const pciSubsystemInfo pci_ss_info_10de_0103_1048_0c4b = + {0x1048, 0x0c4b, pci_subsys_10de_0103_1048_0c4b, 0}; +#undef pci_ss_info_1048_0c4b +#define pci_ss_info_1048_0c4b pci_ss_info_10de_0103_1048_0c4b +static const pciSubsystemInfo pci_ss_info_10de_0110_1043_4015 = + {0x1043, 0x4015, pci_subsys_10de_0110_1043_4015, 0}; +#undef pci_ss_info_1043_4015 +#define pci_ss_info_1043_4015 pci_ss_info_10de_0110_1043_4015 +static const pciSubsystemInfo pci_ss_info_10de_0110_1043_4031 = + {0x1043, 0x4031, pci_subsys_10de_0110_1043_4031, 0}; +#undef pci_ss_info_1043_4031 +#define pci_ss_info_1043_4031 pci_ss_info_10de_0110_1043_4031 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c60 = + {0x1048, 0x0c60, pci_subsys_10de_0110_1048_0c60, 0}; +#undef pci_ss_info_1048_0c60 +#define pci_ss_info_1048_0c60 pci_ss_info_10de_0110_1048_0c60 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c61 = + {0x1048, 0x0c61, pci_subsys_10de_0110_1048_0c61, 0}; +#undef pci_ss_info_1048_0c61 +#define pci_ss_info_1048_0c61 pci_ss_info_10de_0110_1048_0c61 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c63 = + {0x1048, 0x0c63, pci_subsys_10de_0110_1048_0c63, 0}; +#undef pci_ss_info_1048_0c63 +#define pci_ss_info_1048_0c63 pci_ss_info_10de_0110_1048_0c63 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c64 = + {0x1048, 0x0c64, pci_subsys_10de_0110_1048_0c64, 0}; +#undef pci_ss_info_1048_0c64 +#define pci_ss_info_1048_0c64 pci_ss_info_10de_0110_1048_0c64 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c65 = + {0x1048, 0x0c65, pci_subsys_10de_0110_1048_0c65, 0}; +#undef pci_ss_info_1048_0c65 +#define pci_ss_info_1048_0c65 pci_ss_info_10de_0110_1048_0c65 +static const pciSubsystemInfo pci_ss_info_10de_0110_1048_0c66 = + {0x1048, 0x0c66, pci_subsys_10de_0110_1048_0c66, 0}; +#undef pci_ss_info_1048_0c66 +#define pci_ss_info_1048_0c66 pci_ss_info_10de_0110_1048_0c66 +static const pciSubsystemInfo pci_ss_info_10de_0110_10de_0091 = + {0x10de, 0x0091, pci_subsys_10de_0110_10de_0091, 0}; +#undef pci_ss_info_10de_0091 +#define pci_ss_info_10de_0091 pci_ss_info_10de_0110_10de_0091 +static const pciSubsystemInfo pci_ss_info_10de_0110_10de_00a1 = + {0x10de, 0x00a1, pci_subsys_10de_0110_10de_00a1, 0}; +#undef pci_ss_info_10de_00a1 +#define pci_ss_info_10de_00a1 pci_ss_info_10de_0110_10de_00a1 +static const pciSubsystemInfo pci_ss_info_10de_0110_1462_8817 = + {0x1462, 0x8817, pci_subsys_10de_0110_1462_8817, 0}; +#undef pci_ss_info_1462_8817 +#define pci_ss_info_1462_8817 pci_ss_info_10de_0110_1462_8817 +static const pciSubsystemInfo pci_ss_info_10de_0110_14af_7102 = + {0x14af, 0x7102, pci_subsys_10de_0110_14af_7102, 0}; +#undef pci_ss_info_14af_7102 +#define pci_ss_info_14af_7102 pci_ss_info_10de_0110_14af_7102 +static const pciSubsystemInfo pci_ss_info_10de_0110_14af_7103 = + {0x14af, 0x7103, pci_subsys_10de_0110_14af_7103, 0}; +#undef pci_ss_info_14af_7103 +#define pci_ss_info_14af_7103 pci_ss_info_10de_0110_14af_7103 +static const pciSubsystemInfo pci_ss_info_10de_0141_1458_3124 = + {0x1458, 0x3124, pci_subsys_10de_0141_1458_3124, 0}; +#undef pci_ss_info_1458_3124 +#define pci_ss_info_1458_3124 pci_ss_info_10de_0141_1458_3124 +static const pciSubsystemInfo pci_ss_info_10de_0150_1043_4016 = + {0x1043, 0x4016, pci_subsys_10de_0150_1043_4016, 0}; +#undef pci_ss_info_1043_4016 +#define pci_ss_info_1043_4016 pci_ss_info_10de_0150_1043_4016 +static const pciSubsystemInfo pci_ss_info_10de_0150_1048_0c50 = + {0x1048, 0x0c50, pci_subsys_10de_0150_1048_0c50, 0}; +#undef pci_ss_info_1048_0c50 +#define pci_ss_info_1048_0c50 pci_ss_info_10de_0150_1048_0c50 +static const pciSubsystemInfo pci_ss_info_10de_0150_1048_0c52 = + {0x1048, 0x0c52, pci_subsys_10de_0150_1048_0c52, 0}; +#undef pci_ss_info_1048_0c52 +#define pci_ss_info_1048_0c52 pci_ss_info_10de_0150_1048_0c52 +static const pciSubsystemInfo pci_ss_info_10de_0150_107d_2840 = + {0x107d, 0x2840, pci_subsys_10de_0150_107d_2840, 0}; +#undef pci_ss_info_107d_2840 +#define pci_ss_info_107d_2840 pci_ss_info_10de_0150_107d_2840 +static const pciSubsystemInfo pci_ss_info_10de_0150_107d_2842 = + {0x107d, 0x2842, pci_subsys_10de_0150_107d_2842, 0}; +#undef pci_ss_info_107d_2842 +#define pci_ss_info_107d_2842 pci_ss_info_10de_0150_107d_2842 +static const pciSubsystemInfo pci_ss_info_10de_0150_10de_002e = + {0x10de, 0x002e, pci_subsys_10de_0150_10de_002e, 0}; +#undef pci_ss_info_10de_002e +#define pci_ss_info_10de_002e pci_ss_info_10de_0150_10de_002e +static const pciSubsystemInfo pci_ss_info_10de_0150_1462_8831 = + {0x1462, 0x8831, pci_subsys_10de_0150_1462_8831, 0}; +#undef pci_ss_info_1462_8831 +#define pci_ss_info_1462_8831 pci_ss_info_10de_0150_1462_8831 +static const pciSubsystemInfo pci_ss_info_10de_0151_1043_405f = + {0x1043, 0x405f, pci_subsys_10de_0151_1043_405f, 0}; +#undef pci_ss_info_1043_405f +#define pci_ss_info_1043_405f pci_ss_info_10de_0151_1043_405f +static const pciSubsystemInfo pci_ss_info_10de_0151_1462_5506 = + {0x1462, 0x5506, pci_subsys_10de_0151_1462_5506, 0}; +#undef pci_ss_info_1462_5506 +#define pci_ss_info_1462_5506 pci_ss_info_10de_0151_1462_5506 +static const pciSubsystemInfo pci_ss_info_10de_0152_1048_0c56 = + {0x1048, 0x0c56, pci_subsys_10de_0152_1048_0c56, 0}; +#undef pci_ss_info_1048_0c56 +#define pci_ss_info_1048_0c56 pci_ss_info_10de_0152_1048_0c56 +static const pciSubsystemInfo pci_ss_info_10de_0171_10b0_0002 = + {0x10b0, 0x0002, pci_subsys_10de_0171_10b0_0002, 0}; +#undef pci_ss_info_10b0_0002 +#define pci_ss_info_10b0_0002 pci_ss_info_10de_0171_10b0_0002 +static const pciSubsystemInfo pci_ss_info_10de_0171_10de_0008 = + {0x10de, 0x0008, pci_subsys_10de_0171_10de_0008, 0}; +#undef pci_ss_info_10de_0008 +#define pci_ss_info_10de_0008 pci_ss_info_10de_0171_10de_0008 +static const pciSubsystemInfo pci_ss_info_10de_0171_1462_8661 = + {0x1462, 0x8661, pci_subsys_10de_0171_1462_8661, 0}; +#undef pci_ss_info_1462_8661 +#define pci_ss_info_1462_8661 pci_ss_info_10de_0171_1462_8661 +static const pciSubsystemInfo pci_ss_info_10de_0171_1462_8730 = + {0x1462, 0x8730, pci_subsys_10de_0171_1462_8730, 0}; +#undef pci_ss_info_1462_8730 +#define pci_ss_info_1462_8730 pci_ss_info_10de_0171_1462_8730 +static const pciSubsystemInfo pci_ss_info_10de_0171_1462_8852 = + {0x1462, 0x8852, pci_subsys_10de_0171_1462_8852, 0}; +#undef pci_ss_info_1462_8852 +#define pci_ss_info_1462_8852 pci_ss_info_10de_0171_1462_8852 +static const pciSubsystemInfo pci_ss_info_10de_0171_147b_8f00 = + {0x147b, 0x8f00, pci_subsys_10de_0171_147b_8f00, 0}; +#undef pci_ss_info_147b_8f00 +#define pci_ss_info_147b_8f00 pci_ss_info_10de_0171_147b_8f00 +static const pciSubsystemInfo pci_ss_info_10de_0176_103c_08b0 = + {0x103c, 0x08b0, pci_subsys_10de_0176_103c_08b0, 0}; +#undef pci_ss_info_103c_08b0 +#define pci_ss_info_103c_08b0 pci_ss_info_10de_0176_103c_08b0 +static const pciSubsystemInfo pci_ss_info_10de_0176_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_10de_0176_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_10de_0176_4c53_1090 +static const pciSubsystemInfo pci_ss_info_10de_0179_10de_0179 = + {0x10de, 0x0179, pci_subsys_10de_0179_10de_0179, 0}; +#undef pci_ss_info_10de_0179 +#define pci_ss_info_10de_0179 pci_ss_info_10de_0179_10de_0179 +static const pciSubsystemInfo pci_ss_info_10de_0181_1043_8063 = + {0x1043, 0x8063, pci_subsys_10de_0181_1043_8063, 0}; +#undef pci_ss_info_1043_8063 +#define pci_ss_info_1043_8063 pci_ss_info_10de_0181_1043_8063 +static const pciSubsystemInfo pci_ss_info_10de_0181_1043_806f = + {0x1043, 0x806f, pci_subsys_10de_0181_1043_806f, 0}; +#undef pci_ss_info_1043_806f +#define pci_ss_info_1043_806f pci_ss_info_10de_0181_1043_806f +static const pciSubsystemInfo pci_ss_info_10de_0181_1462_8880 = + {0x1462, 0x8880, pci_subsys_10de_0181_1462_8880, 0}; +#undef pci_ss_info_1462_8880 +#define pci_ss_info_1462_8880 pci_ss_info_10de_0181_1462_8880 +static const pciSubsystemInfo pci_ss_info_10de_0181_1462_8900 = + {0x1462, 0x8900, pci_subsys_10de_0181_1462_8900, 0}; +#undef pci_ss_info_1462_8900 +#define pci_ss_info_1462_8900 pci_ss_info_10de_0181_1462_8900 +static const pciSubsystemInfo pci_ss_info_10de_0181_1462_9350 = + {0x1462, 0x9350, pci_subsys_10de_0181_1462_9350, 0}; +#undef pci_ss_info_1462_9350 +#define pci_ss_info_1462_9350 pci_ss_info_10de_0181_1462_9350 +static const pciSubsystemInfo pci_ss_info_10de_0181_147b_8f0d = + {0x147b, 0x8f0d, pci_subsys_10de_0181_147b_8f0d, 0}; +#undef pci_ss_info_147b_8f0d +#define pci_ss_info_147b_8f0d pci_ss_info_10de_0181_147b_8f0d +static const pciSubsystemInfo pci_ss_info_10de_01d1_1462_0345 = + {0x1462, 0x0345, pci_subsys_10de_01d1_1462_0345, 0}; +#undef pci_ss_info_1462_0345 +#define pci_ss_info_1462_0345 pci_ss_info_10de_01d1_1462_0345 +static const pciSubsystemInfo pci_ss_info_10de_01de_10de_01dc = + {0x10de, 0x01dc, pci_subsys_10de_01de_10de_01dc, 0}; +#undef pci_ss_info_10de_01dc +#define pci_ss_info_10de_01dc pci_ss_info_10de_01de_10de_01dc +static const pciSubsystemInfo pci_ss_info_10de_01e0_147b_1c09 = + {0x147b, 0x1c09, pci_subsys_10de_01e0_147b_1c09, 0}; +#undef pci_ss_info_147b_1c09 +#define pci_ss_info_147b_1c09 pci_ss_info_10de_01e0_147b_1c09 +static const pciSubsystemInfo pci_ss_info_10de_01ea_a0a0_03b9 = + {0xa0a0, 0x03b9, pci_subsys_10de_01ea_a0a0_03b9, 0}; +#undef pci_ss_info_a0a0_03b9 +#define pci_ss_info_a0a0_03b9 pci_ss_info_10de_01ea_a0a0_03b9 +static const pciSubsystemInfo pci_ss_info_10de_01eb_a0a0_03b9 = + {0xa0a0, 0x03b9, pci_subsys_10de_01eb_a0a0_03b9, 0}; +#undef pci_ss_info_a0a0_03b9 +#define pci_ss_info_a0a0_03b9 pci_ss_info_10de_01eb_a0a0_03b9 +static const pciSubsystemInfo pci_ss_info_10de_01ec_a0a0_03b9 = + {0xa0a0, 0x03b9, pci_subsys_10de_01ec_a0a0_03b9, 0}; +#undef pci_ss_info_a0a0_03b9 +#define pci_ss_info_a0a0_03b9 pci_ss_info_10de_01ec_a0a0_03b9 +static const pciSubsystemInfo pci_ss_info_10de_01ed_a0a0_03b9 = + {0xa0a0, 0x03b9, pci_subsys_10de_01ed_a0a0_03b9, 0}; +#undef pci_ss_info_a0a0_03b9 +#define pci_ss_info_a0a0_03b9 pci_ss_info_10de_01ed_a0a0_03b9 +static const pciSubsystemInfo pci_ss_info_10de_01ee_a0a0_03b9 = + {0xa0a0, 0x03b9, pci_subsys_10de_01ee_a0a0_03b9, 0}; +#undef pci_ss_info_a0a0_03b9 +#define pci_ss_info_a0a0_03b9 pci_ss_info_10de_01ee_a0a0_03b9 +static const pciSubsystemInfo pci_ss_info_10de_01ef_a0a0_03b9 = + {0xa0a0, 0x03b9, pci_subsys_10de_01ef_a0a0_03b9, 0}; +#undef pci_ss_info_a0a0_03b9 +#define pci_ss_info_a0a0_03b9 pci_ss_info_10de_01ef_a0a0_03b9 +static const pciSubsystemInfo pci_ss_info_10de_01f0_a0a0_03b5 = + {0xa0a0, 0x03b5, pci_subsys_10de_01f0_a0a0_03b5, 0}; +#undef pci_ss_info_a0a0_03b5 +#define pci_ss_info_a0a0_03b5 pci_ss_info_10de_01f0_a0a0_03b5 +static const pciSubsystemInfo pci_ss_info_10de_0200_1043_402f = + {0x1043, 0x402f, pci_subsys_10de_0200_1043_402f, 0}; +#undef pci_ss_info_1043_402f +#define pci_ss_info_1043_402f pci_ss_info_10de_0200_1043_402f +static const pciSubsystemInfo pci_ss_info_10de_0200_1048_0c70 = + {0x1048, 0x0c70, pci_subsys_10de_0200_1048_0c70, 0}; +#undef pci_ss_info_1048_0c70 +#define pci_ss_info_1048_0c70 pci_ss_info_10de_0200_1048_0c70 +static const pciSubsystemInfo pci_ss_info_10de_0202_1043_405b = + {0x1043, 0x405b, pci_subsys_10de_0202_1043_405b, 0}; +#undef pci_ss_info_1043_405b +#define pci_ss_info_1043_405b pci_ss_info_10de_0202_1043_405b +static const pciSubsystemInfo pci_ss_info_10de_0202_1545_002f = + {0x1545, 0x002f, pci_subsys_10de_0202_1545_002f, 0}; +#undef pci_ss_info_1545_002f +#define pci_ss_info_1545_002f pci_ss_info_10de_0202_1545_002f +static const pciSubsystemInfo pci_ss_info_10de_0240_1462_7207 = + {0x1462, 0x7207, pci_subsys_10de_0240_1462_7207, 0}; +#undef pci_ss_info_1462_7207 +#define pci_ss_info_1462_7207 pci_ss_info_10de_0240_1462_7207 +static const pciSubsystemInfo pci_ss_info_10de_0251_1043_8023 = + {0x1043, 0x8023, pci_subsys_10de_0251_1043_8023, 0}; +#undef pci_ss_info_1043_8023 +#define pci_ss_info_1043_8023 pci_ss_info_10de_0251_1043_8023 +static const pciSubsystemInfo pci_ss_info_10de_0253_107d_2896 = + {0x107d, 0x2896, pci_subsys_10de_0253_107d_2896, 0}; +#undef pci_ss_info_107d_2896 +#define pci_ss_info_107d_2896 pci_ss_info_10de_0253_107d_2896 +static const pciSubsystemInfo pci_ss_info_10de_0253_147b_8f09 = + {0x147b, 0x8f09, pci_subsys_10de_0253_147b_8f09, 0}; +#undef pci_ss_info_147b_8f09 +#define pci_ss_info_147b_8f09 pci_ss_info_10de_0253_147b_8f09 +static const pciSubsystemInfo pci_ss_info_10de_0260_1462_7207 = + {0x1462, 0x7207, pci_subsys_10de_0260_1462_7207, 0}; +#undef pci_ss_info_1462_7207 +#define pci_ss_info_1462_7207 pci_ss_info_10de_0260_1462_7207 +static const pciSubsystemInfo pci_ss_info_10de_0264_1462_7207 = + {0x1462, 0x7207, pci_subsys_10de_0264_1462_7207, 0}; +#undef pci_ss_info_1462_7207 +#define pci_ss_info_1462_7207 pci_ss_info_10de_0264_1462_7207 +static const pciSubsystemInfo pci_ss_info_10de_0265_1462_7207 = + {0x1462, 0x7207, pci_subsys_10de_0265_1462_7207, 0}; +#undef pci_ss_info_1462_7207 +#define pci_ss_info_1462_7207 pci_ss_info_10de_0265_1462_7207 +static const pciSubsystemInfo pci_ss_info_10de_0266_1462_7207 = + {0x1462, 0x7207, pci_subsys_10de_0266_1462_7207, 0}; +#undef pci_ss_info_1462_7207 +#define pci_ss_info_1462_7207 pci_ss_info_10de_0266_1462_7207 +static const pciSubsystemInfo pci_ss_info_10de_0267_1462_7207 = + {0x1462, 0x7207, pci_subsys_10de_0267_1462_7207, 0}; +#undef pci_ss_info_1462_7207 +#define pci_ss_info_1462_7207 pci_ss_info_10de_0267_1462_7207 +static const pciSubsystemInfo pci_ss_info_10de_0269_1462_7207 = + {0x1462, 0x7207, pci_subsys_10de_0269_1462_7207, 0}; +#undef pci_ss_info_1462_7207 +#define pci_ss_info_1462_7207 pci_ss_info_10de_0269_1462_7207 +static const pciSubsystemInfo pci_ss_info_10de_026c_1462_7207 = + {0x1462, 0x7207, pci_subsys_10de_026c_1462_7207, 0}; +#undef pci_ss_info_1462_7207 +#define pci_ss_info_1462_7207 pci_ss_info_10de_026c_1462_7207 +static const pciSubsystemInfo pci_ss_info_10de_026d_1462_7207 = + {0x1462, 0x7207, pci_subsys_10de_026d_1462_7207, 0}; +#undef pci_ss_info_1462_7207 +#define pci_ss_info_1462_7207 pci_ss_info_10de_026d_1462_7207 +static const pciSubsystemInfo pci_ss_info_10de_026e_1462_7207 = + {0x1462, 0x7207, pci_subsys_10de_026e_1462_7207, 0}; +#undef pci_ss_info_1462_7207 +#define pci_ss_info_1462_7207 pci_ss_info_10de_026e_1462_7207 +static const pciSubsystemInfo pci_ss_info_10de_0270_1462_7207 = + {0x1462, 0x7207, pci_subsys_10de_0270_1462_7207, 0}; +#undef pci_ss_info_1462_7207 +#define pci_ss_info_1462_7207 pci_ss_info_10de_0270_1462_7207 +static const pciSubsystemInfo pci_ss_info_10de_027e_1462_7207 = + {0x1462, 0x7207, pci_subsys_10de_027e_1462_7207, 0}; +#undef pci_ss_info_1462_7207 +#define pci_ss_info_1462_7207 pci_ss_info_10de_027e_1462_7207 +static const pciSubsystemInfo pci_ss_info_10de_027f_1462_7207 = + {0x1462, 0x7207, pci_subsys_10de_027f_1462_7207, 0}; +#undef pci_ss_info_1462_7207 +#define pci_ss_info_1462_7207 pci_ss_info_10de_027f_1462_7207 +static const pciSubsystemInfo pci_ss_info_10de_02f0_1462_7207 = + {0x1462, 0x7207, pci_subsys_10de_02f0_1462_7207, 0}; +#undef pci_ss_info_1462_7207 +#define pci_ss_info_1462_7207 pci_ss_info_10de_02f0_1462_7207 +static const pciSubsystemInfo pci_ss_info_10de_02f8_1462_7207 = + {0x1462, 0x7207, pci_subsys_10de_02f8_1462_7207, 0}; +#undef pci_ss_info_1462_7207 +#define pci_ss_info_1462_7207 pci_ss_info_10de_02f8_1462_7207 +static const pciSubsystemInfo pci_ss_info_10de_02f9_1462_7207 = + {0x1462, 0x7207, pci_subsys_10de_02f9_1462_7207, 0}; +#undef pci_ss_info_1462_7207 +#define pci_ss_info_1462_7207 pci_ss_info_10de_02f9_1462_7207 +static const pciSubsystemInfo pci_ss_info_10de_02fa_1462_7207 = + {0x1462, 0x7207, pci_subsys_10de_02fa_1462_7207, 0}; +#undef pci_ss_info_1462_7207 +#define pci_ss_info_1462_7207 pci_ss_info_10de_02fa_1462_7207 +static const pciSubsystemInfo pci_ss_info_10de_02fe_1462_7207 = + {0x1462, 0x7207, pci_subsys_10de_02fe_1462_7207, 0}; +#undef pci_ss_info_1462_7207 +#define pci_ss_info_1462_7207 pci_ss_info_10de_02fe_1462_7207 +static const pciSubsystemInfo pci_ss_info_10de_02ff_1462_7207 = + {0x1462, 0x7207, pci_subsys_10de_02ff_1462_7207, 0}; +#undef pci_ss_info_1462_7207 +#define pci_ss_info_1462_7207 pci_ss_info_10de_02ff_1462_7207 +static const pciSubsystemInfo pci_ss_info_10de_0314_1043_814a = + {0x1043, 0x814a, pci_subsys_10de_0314_1043_814a, 0}; +#undef pci_ss_info_1043_814a +#define pci_ss_info_1043_814a pci_ss_info_10de_0314_1043_814a +static const pciSubsystemInfo pci_ss_info_10de_0322_1462_9171 = + {0x1462, 0x9171, pci_subsys_10de_0322_1462_9171, 0}; +#undef pci_ss_info_1462_9171 +#define pci_ss_info_1462_9171 pci_ss_info_10de_0322_1462_9171 +static const pciSubsystemInfo pci_ss_info_10de_0322_1462_9360 = + {0x1462, 0x9360, pci_subsys_10de_0322_1462_9360, 0}; +#undef pci_ss_info_1462_9360 +#define pci_ss_info_1462_9360 pci_ss_info_10de_0322_1462_9360 +static const pciSubsystemInfo pci_ss_info_10de_0324_1028_0196 = + {0x1028, 0x0196, pci_subsys_10de_0324_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_10de_0324_1028_0196 +static const pciSubsystemInfo pci_ss_info_10de_0324_1071_8160 = + {0x1071, 0x8160, pci_subsys_10de_0324_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_10de_0324_1071_8160 +static const pciSubsystemInfo pci_ss_info_10de_0331_1043_8145 = + {0x1043, 0x8145, pci_subsys_10de_0331_1043_8145, 0}; +#undef pci_ss_info_1043_8145 +#define pci_ss_info_1043_8145 pci_ss_info_10de_0331_1043_8145 +static const pciSubsystemInfo pci_ss_info_10de_0347_103c_006a = + {0x103c, 0x006a, pci_subsys_10de_0347_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_10de_0347_103c_006a +static const pciSubsystemInfo pci_ss_info_10de_0392_1462_0622 = + {0x1462, 0x0622, pci_subsys_10de_0392_1462_0622, 0}; +#undef pci_ss_info_1462_0622 +#define pci_ss_info_1462_0622 pci_ss_info_10de_0392_1462_0622 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10e1_0391_10e1_0391 = + {0x10e1, 0x0391, pci_subsys_10e1_0391_10e1_0391, 0}; +#undef pci_ss_info_10e1_0391 +#define pci_ss_info_10e1_0391 pci_ss_info_10e1_0391_10e1_0391 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10ec_0883_1025_1605 = + {0x1025, 0x1605, pci_subsys_10ec_0883_1025_1605, 0}; +#undef pci_ss_info_1025_1605 +#define pci_ss_info_1025_1605 pci_ss_info_10ec_0883_1025_1605 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10ec_8029_10b8_2011 = + {0x10b8, 0x2011, pci_subsys_10ec_8029_10b8_2011, 0}; +#undef pci_ss_info_10b8_2011 +#define pci_ss_info_10b8_2011 pci_ss_info_10ec_8029_10b8_2011 +static const pciSubsystemInfo pci_ss_info_10ec_8029_10ec_8029 = + {0x10ec, 0x8029, pci_subsys_10ec_8029_10ec_8029, 0}; +#undef pci_ss_info_10ec_8029 +#define pci_ss_info_10ec_8029 pci_ss_info_10ec_8029_10ec_8029 +static const pciSubsystemInfo pci_ss_info_10ec_8029_1113_1208 = + {0x1113, 0x1208, pci_subsys_10ec_8029_1113_1208, 0}; +#undef pci_ss_info_1113_1208 +#define pci_ss_info_1113_1208 pci_ss_info_10ec_8029_1113_1208 +static const pciSubsystemInfo pci_ss_info_10ec_8029_1186_0300 = + {0x1186, 0x0300, pci_subsys_10ec_8029_1186_0300, 0}; +#undef pci_ss_info_1186_0300 +#define pci_ss_info_1186_0300 pci_ss_info_10ec_8029_1186_0300 +static const pciSubsystemInfo pci_ss_info_10ec_8029_1259_2400 = + {0x1259, 0x2400, pci_subsys_10ec_8029_1259_2400, 0}; +#undef pci_ss_info_1259_2400 +#define pci_ss_info_1259_2400 pci_ss_info_10ec_8029_1259_2400 +static const pciSubsystemInfo pci_ss_info_10ec_8129_10ec_8129 = + {0x10ec, 0x8129, pci_subsys_10ec_8129_10ec_8129, 0}; +#undef pci_ss_info_10ec_8129 +#define pci_ss_info_10ec_8129 pci_ss_info_10ec_8129_10ec_8129 +static const pciSubsystemInfo pci_ss_info_10ec_8138_10ec_8138 = + {0x10ec, 0x8138, pci_subsys_10ec_8138_10ec_8138, 0}; +#undef pci_ss_info_10ec_8138 +#define pci_ss_info_10ec_8138 pci_ss_info_10ec_8138_10ec_8138 +static const pciSubsystemInfo pci_ss_info_10ec_8139_0357_000a = + {0x0357, 0x000a, pci_subsys_10ec_8139_0357_000a, 0}; +#undef pci_ss_info_0357_000a +#define pci_ss_info_0357_000a pci_ss_info_10ec_8139_0357_000a +#endif +static const pciSubsystemInfo pci_ss_info_10ec_8139_1025_005a = + {0x1025, 0x005a, pci_subsys_10ec_8139_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_10ec_8139_1025_005a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10ec_8139_1025_8920 = + {0x1025, 0x8920, pci_subsys_10ec_8139_1025_8920, 0}; +#undef pci_ss_info_1025_8920 +#define pci_ss_info_1025_8920 pci_ss_info_10ec_8139_1025_8920 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10ec_8139_1025_8921 = + {0x1025, 0x8921, pci_subsys_10ec_8139_1025_8921, 0}; +#undef pci_ss_info_1025_8921 +#define pci_ss_info_1025_8921 pci_ss_info_10ec_8139_1025_8921 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_10ec_8139_103c_006a = + {0x103c, 0x006a, pci_subsys_10ec_8139_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_10ec_8139_103c_006a +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10ec_8139_1043_8109 = + {0x1043, 0x8109, pci_subsys_10ec_8139_1043_8109, 0}; +#undef pci_ss_info_1043_8109 +#define pci_ss_info_1043_8109 pci_ss_info_10ec_8139_1043_8109 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1071_8160 = + {0x1071, 0x8160, pci_subsys_10ec_8139_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_10ec_8139_1071_8160 +static const pciSubsystemInfo pci_ss_info_10ec_8139_10bd_0320 = + {0x10bd, 0x0320, pci_subsys_10ec_8139_10bd_0320, 0}; +#undef pci_ss_info_10bd_0320 +#define pci_ss_info_10bd_0320 pci_ss_info_10ec_8139_10bd_0320 +static const pciSubsystemInfo pci_ss_info_10ec_8139_10ec_8139 = + {0x10ec, 0x8139, pci_subsys_10ec_8139_10ec_8139, 0}; +#undef pci_ss_info_10ec_8139 +#define pci_ss_info_10ec_8139 pci_ss_info_10ec_8139_10ec_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1113_ec01 = + {0x1113, 0xec01, pci_subsys_10ec_8139_1113_ec01, 0}; +#undef pci_ss_info_1113_ec01 +#define pci_ss_info_1113_ec01 pci_ss_info_10ec_8139_1113_ec01 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1186_1300 = + {0x1186, 0x1300, pci_subsys_10ec_8139_1186_1300, 0}; +#undef pci_ss_info_1186_1300 +#define pci_ss_info_1186_1300 pci_ss_info_10ec_8139_1186_1300 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1186_1320 = + {0x1186, 0x1320, pci_subsys_10ec_8139_1186_1320, 0}; +#undef pci_ss_info_1186_1320 +#define pci_ss_info_1186_1320 pci_ss_info_10ec_8139_1186_1320 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1186_8139 = + {0x1186, 0x8139, pci_subsys_10ec_8139_1186_8139, 0}; +#undef pci_ss_info_1186_8139 +#define pci_ss_info_1186_8139 pci_ss_info_10ec_8139_1186_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_11f6_8139 = + {0x11f6, 0x8139, pci_subsys_10ec_8139_11f6_8139, 0}; +#undef pci_ss_info_11f6_8139 +#define pci_ss_info_11f6_8139 pci_ss_info_10ec_8139_11f6_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1259_2500 = + {0x1259, 0x2500, pci_subsys_10ec_8139_1259_2500, 0}; +#undef pci_ss_info_1259_2500 +#define pci_ss_info_1259_2500 pci_ss_info_10ec_8139_1259_2500 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1259_2503 = + {0x1259, 0x2503, pci_subsys_10ec_8139_1259_2503, 0}; +#undef pci_ss_info_1259_2503 +#define pci_ss_info_1259_2503 pci_ss_info_10ec_8139_1259_2503 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1429_d010 = + {0x1429, 0xd010, pci_subsys_10ec_8139_1429_d010, 0}; +#undef pci_ss_info_1429_d010 +#define pci_ss_info_1429_d010 pci_ss_info_10ec_8139_1429_d010 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1432_9130 = + {0x1432, 0x9130, pci_subsys_10ec_8139_1432_9130, 0}; +#undef pci_ss_info_1432_9130 +#define pci_ss_info_1432_9130 pci_ss_info_10ec_8139_1432_9130 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1436_8139 = + {0x1436, 0x8139, pci_subsys_10ec_8139_1436_8139, 0}; +#undef pci_ss_info_1436_8139 +#define pci_ss_info_1436_8139 pci_ss_info_10ec_8139_1436_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1458_e000 = + {0x1458, 0xe000, pci_subsys_10ec_8139_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_10ec_8139_1458_e000 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1462_788c = + {0x1462, 0x788c, pci_subsys_10ec_8139_1462_788c, 0}; +#undef pci_ss_info_1462_788c +#define pci_ss_info_1462_788c pci_ss_info_10ec_8139_1462_788c +static const pciSubsystemInfo pci_ss_info_10ec_8139_146c_1439 = + {0x146c, 0x1439, pci_subsys_10ec_8139_146c_1439, 0}; +#undef pci_ss_info_146c_1439 +#define pci_ss_info_146c_1439 pci_ss_info_10ec_8139_146c_1439 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1489_6001 = + {0x1489, 0x6001, pci_subsys_10ec_8139_1489_6001, 0}; +#undef pci_ss_info_1489_6001 +#define pci_ss_info_1489_6001 pci_ss_info_10ec_8139_1489_6001 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1489_6002 = + {0x1489, 0x6002, pci_subsys_10ec_8139_1489_6002, 0}; +#undef pci_ss_info_1489_6002 +#define pci_ss_info_1489_6002 pci_ss_info_10ec_8139_1489_6002 +static const pciSubsystemInfo pci_ss_info_10ec_8139_149c_139a = + {0x149c, 0x139a, pci_subsys_10ec_8139_149c_139a, 0}; +#undef pci_ss_info_149c_139a +#define pci_ss_info_149c_139a pci_ss_info_10ec_8139_149c_139a +static const pciSubsystemInfo pci_ss_info_10ec_8139_149c_8139 = + {0x149c, 0x8139, pci_subsys_10ec_8139_149c_8139, 0}; +#undef pci_ss_info_149c_8139 +#define pci_ss_info_149c_8139 pci_ss_info_10ec_8139_149c_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_14cb_0200 = + {0x14cb, 0x0200, pci_subsys_10ec_8139_14cb_0200, 0}; +#undef pci_ss_info_14cb_0200 +#define pci_ss_info_14cb_0200 pci_ss_info_10ec_8139_14cb_0200 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1695_9001 = + {0x1695, 0x9001, pci_subsys_10ec_8139_1695_9001, 0}; +#undef pci_ss_info_1695_9001 +#define pci_ss_info_1695_9001 pci_ss_info_10ec_8139_1695_9001 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1799_5000 = + {0x1799, 0x5000, pci_subsys_10ec_8139_1799_5000, 0}; +#undef pci_ss_info_1799_5000 +#define pci_ss_info_1799_5000 pci_ss_info_10ec_8139_1799_5000 +static const pciSubsystemInfo pci_ss_info_10ec_8139_1904_8139 = + {0x1904, 0x8139, pci_subsys_10ec_8139_1904_8139, 0}; +#undef pci_ss_info_1904_8139 +#define pci_ss_info_1904_8139 pci_ss_info_10ec_8139_1904_8139 +static const pciSubsystemInfo pci_ss_info_10ec_8139_2646_0001 = + {0x2646, 0x0001, pci_subsys_10ec_8139_2646_0001, 0}; +#undef pci_ss_info_2646_0001 +#define pci_ss_info_2646_0001 pci_ss_info_10ec_8139_2646_0001 +static const pciSubsystemInfo pci_ss_info_10ec_8139_8e2e_7000 = + {0x8e2e, 0x7000, pci_subsys_10ec_8139_8e2e_7000, 0}; +#undef pci_ss_info_8e2e_7000 +#define pci_ss_info_8e2e_7000 pci_ss_info_10ec_8139_8e2e_7000 +static const pciSubsystemInfo pci_ss_info_10ec_8139_8e2e_7100 = + {0x8e2e, 0x7100, pci_subsys_10ec_8139_8e2e_7100, 0}; +#undef pci_ss_info_8e2e_7100 +#define pci_ss_info_8e2e_7100 pci_ss_info_10ec_8139_8e2e_7100 +static const pciSubsystemInfo pci_ss_info_10ec_8139_a0a0_0007 = + {0xa0a0, 0x0007, pci_subsys_10ec_8139_a0a0_0007, 0}; +#undef pci_ss_info_a0a0_0007 +#define pci_ss_info_a0a0_0007 pci_ss_info_10ec_8139_a0a0_0007 +#endif +static const pciSubsystemInfo pci_ss_info_10ec_8169_1025_0079 = + {0x1025, 0x0079, pci_subsys_10ec_8169_1025_0079, 0}; +#undef pci_ss_info_1025_0079 +#define pci_ss_info_1025_0079 pci_ss_info_10ec_8169_1025_0079 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_10ec_8169_1259_c107 = + {0x1259, 0xc107, pci_subsys_10ec_8169_1259_c107, 0}; +#undef pci_ss_info_1259_c107 +#define pci_ss_info_1259_c107 pci_ss_info_10ec_8169_1259_c107 +static const pciSubsystemInfo pci_ss_info_10ec_8169_1371_434e = + {0x1371, 0x434e, pci_subsys_10ec_8169_1371_434e, 0}; +#undef pci_ss_info_1371_434e +#define pci_ss_info_1371_434e pci_ss_info_10ec_8169_1371_434e +static const pciSubsystemInfo pci_ss_info_10ec_8169_1458_e000 = + {0x1458, 0xe000, pci_subsys_10ec_8169_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_10ec_8169_1458_e000 +static const pciSubsystemInfo pci_ss_info_10ec_8169_1462_702c = + {0x1462, 0x702c, pci_subsys_10ec_8169_1462_702c, 0}; +#undef pci_ss_info_1462_702c +#define pci_ss_info_1462_702c pci_ss_info_10ec_8169_1462_702c +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_0020 = + {0x1102, 0x0020, pci_subsys_1102_0002_1102_0020, 0}; +#undef pci_ss_info_1102_0020 +#define pci_ss_info_1102_0020 pci_ss_info_1102_0002_1102_0020 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_0021 = + {0x1102, 0x0021, pci_subsys_1102_0002_1102_0021, 0}; +#undef pci_ss_info_1102_0021 +#define pci_ss_info_1102_0021 pci_ss_info_1102_0002_1102_0021 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_002f = + {0x1102, 0x002f, pci_subsys_1102_0002_1102_002f, 0}; +#undef pci_ss_info_1102_002f +#define pci_ss_info_1102_002f pci_ss_info_1102_0002_1102_002f +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_100a = + {0x1102, 0x100a, pci_subsys_1102_0002_1102_100a, 0}; +#undef pci_ss_info_1102_100a +#define pci_ss_info_1102_100a pci_ss_info_1102_0002_1102_100a +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_4001 = + {0x1102, 0x4001, pci_subsys_1102_0002_1102_4001, 0}; +#undef pci_ss_info_1102_4001 +#define pci_ss_info_1102_4001 pci_ss_info_1102_0002_1102_4001 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8022 = + {0x1102, 0x8022, pci_subsys_1102_0002_1102_8022, 0}; +#undef pci_ss_info_1102_8022 +#define pci_ss_info_1102_8022 pci_ss_info_1102_0002_1102_8022 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8023 = + {0x1102, 0x8023, pci_subsys_1102_0002_1102_8023, 0}; +#undef pci_ss_info_1102_8023 +#define pci_ss_info_1102_8023 pci_ss_info_1102_0002_1102_8023 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8024 = + {0x1102, 0x8024, pci_subsys_1102_0002_1102_8024, 0}; +#undef pci_ss_info_1102_8024 +#define pci_ss_info_1102_8024 pci_ss_info_1102_0002_1102_8024 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8025 = + {0x1102, 0x8025, pci_subsys_1102_0002_1102_8025, 0}; +#undef pci_ss_info_1102_8025 +#define pci_ss_info_1102_8025 pci_ss_info_1102_0002_1102_8025 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8026 = + {0x1102, 0x8026, pci_subsys_1102_0002_1102_8026, 0}; +#undef pci_ss_info_1102_8026 +#define pci_ss_info_1102_8026 pci_ss_info_1102_0002_1102_8026 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8027 = + {0x1102, 0x8027, pci_subsys_1102_0002_1102_8027, 0}; +#undef pci_ss_info_1102_8027 +#define pci_ss_info_1102_8027 pci_ss_info_1102_0002_1102_8027 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8028 = + {0x1102, 0x8028, pci_subsys_1102_0002_1102_8028, 0}; +#undef pci_ss_info_1102_8028 +#define pci_ss_info_1102_8028 pci_ss_info_1102_0002_1102_8028 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8031 = + {0x1102, 0x8031, pci_subsys_1102_0002_1102_8031, 0}; +#undef pci_ss_info_1102_8031 +#define pci_ss_info_1102_8031 pci_ss_info_1102_0002_1102_8031 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8040 = + {0x1102, 0x8040, pci_subsys_1102_0002_1102_8040, 0}; +#undef pci_ss_info_1102_8040 +#define pci_ss_info_1102_8040 pci_ss_info_1102_0002_1102_8040 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8051 = + {0x1102, 0x8051, pci_subsys_1102_0002_1102_8051, 0}; +#undef pci_ss_info_1102_8051 +#define pci_ss_info_1102_8051 pci_ss_info_1102_0002_1102_8051 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8061 = + {0x1102, 0x8061, pci_subsys_1102_0002_1102_8061, 0}; +#undef pci_ss_info_1102_8061 +#define pci_ss_info_1102_8061 pci_ss_info_1102_0002_1102_8061 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8064 = + {0x1102, 0x8064, pci_subsys_1102_0002_1102_8064, 0}; +#undef pci_ss_info_1102_8064 +#define pci_ss_info_1102_8064 pci_ss_info_1102_0002_1102_8064 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8065 = + {0x1102, 0x8065, pci_subsys_1102_0002_1102_8065, 0}; +#undef pci_ss_info_1102_8065 +#define pci_ss_info_1102_8065 pci_ss_info_1102_0002_1102_8065 +static const pciSubsystemInfo pci_ss_info_1102_0002_1102_8067 = + {0x1102, 0x8067, pci_subsys_1102_0002_1102_8067, 0}; +#undef pci_ss_info_1102_8067 +#define pci_ss_info_1102_8067 pci_ss_info_1102_0002_1102_8067 +static const pciSubsystemInfo pci_ss_info_1102_0004_1102_0051 = + {0x1102, 0x0051, pci_subsys_1102_0004_1102_0051, 0}; +#undef pci_ss_info_1102_0051 +#define pci_ss_info_1102_0051 pci_ss_info_1102_0004_1102_0051 +static const pciSubsystemInfo pci_ss_info_1102_0004_1102_0053 = + {0x1102, 0x0053, pci_subsys_1102_0004_1102_0053, 0}; +#undef pci_ss_info_1102_0053 +#define pci_ss_info_1102_0053 pci_ss_info_1102_0004_1102_0053 +static const pciSubsystemInfo pci_ss_info_1102_0004_1102_0058 = + {0x1102, 0x0058, pci_subsys_1102_0004_1102_0058, 0}; +#undef pci_ss_info_1102_0058 +#define pci_ss_info_1102_0058 pci_ss_info_1102_0004_1102_0058 +static const pciSubsystemInfo pci_ss_info_1102_0004_1102_1007 = + {0x1102, 0x1007, pci_subsys_1102_0004_1102_1007, 0}; +#undef pci_ss_info_1102_1007 +#define pci_ss_info_1102_1007 pci_ss_info_1102_0004_1102_1007 +static const pciSubsystemInfo pci_ss_info_1102_0004_1102_2002 = + {0x1102, 0x2002, pci_subsys_1102_0004_1102_2002, 0}; +#undef pci_ss_info_1102_2002 +#define pci_ss_info_1102_2002 pci_ss_info_1102_0004_1102_2002 +static const pciSubsystemInfo pci_ss_info_1102_0005_1102_0021 = + {0x1102, 0x0021, pci_subsys_1102_0005_1102_0021, 0}; +#undef pci_ss_info_1102_0021 +#define pci_ss_info_1102_0021 pci_ss_info_1102_0005_1102_0021 +static const pciSubsystemInfo pci_ss_info_1102_0005_1102_1003 = + {0x1102, 0x1003, pci_subsys_1102_0005_1102_1003, 0}; +#undef pci_ss_info_1102_1003 +#define pci_ss_info_1102_1003 pci_ss_info_1102_0005_1102_1003 +static const pciSubsystemInfo pci_ss_info_1102_0007_1102_0007 = + {0x1102, 0x0007, pci_subsys_1102_0007_1102_0007, 0}; +#undef pci_ss_info_1102_0007 +#define pci_ss_info_1102_0007 pci_ss_info_1102_0007_1102_0007 +static const pciSubsystemInfo pci_ss_info_1102_0007_1102_1001 = + {0x1102, 0x1001, pci_subsys_1102_0007_1102_1001, 0}; +#undef pci_ss_info_1102_1001 +#define pci_ss_info_1102_1001 pci_ss_info_1102_0007_1102_1001 +static const pciSubsystemInfo pci_ss_info_1102_0007_1102_1002 = + {0x1102, 0x1002, pci_subsys_1102_0007_1102_1002, 0}; +#undef pci_ss_info_1102_1002 +#define pci_ss_info_1102_1002 pci_ss_info_1102_0007_1102_1002 +static const pciSubsystemInfo pci_ss_info_1102_0007_1102_1006 = + {0x1102, 0x1006, pci_subsys_1102_0007_1102_1006, 0}; +#undef pci_ss_info_1102_1006 +#define pci_ss_info_1102_1006 pci_ss_info_1102_0007_1102_1006 +static const pciSubsystemInfo pci_ss_info_1102_0007_1462_1009 = + {0x1462, 0x1009, pci_subsys_1102_0007_1462_1009, 0}; +#undef pci_ss_info_1462_1009 +#define pci_ss_info_1462_1009 pci_ss_info_1102_0007_1462_1009 +static const pciSubsystemInfo pci_ss_info_1102_0008_1102_0008 = + {0x1102, 0x0008, pci_subsys_1102_0008_1102_0008, 0}; +#undef pci_ss_info_1102_0008 +#define pci_ss_info_1102_0008 pci_ss_info_1102_0008_1102_0008 +static const pciSubsystemInfo pci_ss_info_1102_4001_1102_0010 = + {0x1102, 0x0010, pci_subsys_1102_4001_1102_0010, 0}; +#undef pci_ss_info_1102_0010 +#define pci_ss_info_1102_0010 pci_ss_info_1102_4001_1102_0010 +static const pciSubsystemInfo pci_ss_info_1102_7002_1102_0020 = + {0x1102, 0x0020, pci_subsys_1102_7002_1102_0020, 0}; +#undef pci_ss_info_1102_0020 +#define pci_ss_info_1102_0020 pci_ss_info_1102_7002_1102_0020 +static const pciSubsystemInfo pci_ss_info_1102_7003_1102_0040 = + {0x1102, 0x0040, pci_subsys_1102_7003_1102_0040, 0}; +#undef pci_ss_info_1102_0040 +#define pci_ss_info_1102_0040 pci_ss_info_1102_7003_1102_0040 +static const pciSubsystemInfo pci_ss_info_1102_7005_1102_1001 = + {0x1102, 0x1001, pci_subsys_1102_7005_1102_1001, 0}; +#undef pci_ss_info_1102_1001 +#define pci_ss_info_1102_1001 pci_ss_info_1102_7005_1102_1001 +static const pciSubsystemInfo pci_ss_info_1102_7005_1102_1002 = + {0x1102, 0x1002, pci_subsys_1102_7005_1102_1002, 0}; +#undef pci_ss_info_1102_1002 +#define pci_ss_info_1102_1002 pci_ss_info_1102_7005_1102_1002 +#endif +static const pciSubsystemInfo pci_ss_info_1102_8938_1033_80e5 = + {0x1033, 0x80e5, pci_subsys_1102_8938_1033_80e5, 0}; +#undef pci_ss_info_1033_80e5 +#define pci_ss_info_1033_80e5 pci_ss_info_1102_8938_1033_80e5 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1102_8938_1071_7150 = + {0x1071, 0x7150, pci_subsys_1102_8938_1071_7150, 0}; +#undef pci_ss_info_1071_7150 +#define pci_ss_info_1071_7150 pci_ss_info_1102_8938_1071_7150 +static const pciSubsystemInfo pci_ss_info_1102_8938_110a_5938 = + {0x110a, 0x5938, pci_subsys_1102_8938_110a_5938, 0}; +#undef pci_ss_info_110a_5938 +#define pci_ss_info_110a_5938 pci_ss_info_1102_8938_110a_5938 +static const pciSubsystemInfo pci_ss_info_1102_8938_13bd_100c = + {0x13bd, 0x100c, pci_subsys_1102_8938_13bd_100c, 0}; +#undef pci_ss_info_13bd_100c +#define pci_ss_info_13bd_100c pci_ss_info_1102_8938_13bd_100c +static const pciSubsystemInfo pci_ss_info_1102_8938_13bd_100d = + {0x13bd, 0x100d, pci_subsys_1102_8938_13bd_100d, 0}; +#undef pci_ss_info_13bd_100d +#define pci_ss_info_13bd_100d pci_ss_info_1102_8938_13bd_100d +static const pciSubsystemInfo pci_ss_info_1102_8938_13bd_100e = + {0x13bd, 0x100e, pci_subsys_1102_8938_13bd_100e, 0}; +#undef pci_ss_info_13bd_100e +#define pci_ss_info_13bd_100e pci_ss_info_1102_8938_13bd_100e +static const pciSubsystemInfo pci_ss_info_1102_8938_13bd_f6f1 = + {0x13bd, 0xf6f1, pci_subsys_1102_8938_13bd_f6f1, 0}; +#undef pci_ss_info_13bd_f6f1 +#define pci_ss_info_13bd_f6f1 pci_ss_info_1102_8938_13bd_f6f1 +static const pciSubsystemInfo pci_ss_info_1102_8938_14ff_0e70 = + {0x14ff, 0x0e70, pci_subsys_1102_8938_14ff_0e70, 0}; +#undef pci_ss_info_14ff_0e70 +#define pci_ss_info_14ff_0e70 pci_ss_info_1102_8938_14ff_0e70 +static const pciSubsystemInfo pci_ss_info_1102_8938_14ff_c401 = + {0x14ff, 0xc401, pci_subsys_1102_8938_14ff_c401, 0}; +#undef pci_ss_info_14ff_c401 +#define pci_ss_info_14ff_c401 pci_ss_info_1102_8938_14ff_c401 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b400 = + {0x156d, 0xb400, pci_subsys_1102_8938_156d_b400, 0}; +#undef pci_ss_info_156d_b400 +#define pci_ss_info_156d_b400 pci_ss_info_1102_8938_156d_b400 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b550 = + {0x156d, 0xb550, pci_subsys_1102_8938_156d_b550, 0}; +#undef pci_ss_info_156d_b550 +#define pci_ss_info_156d_b550 pci_ss_info_1102_8938_156d_b550 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b560 = + {0x156d, 0xb560, pci_subsys_1102_8938_156d_b560, 0}; +#undef pci_ss_info_156d_b560 +#define pci_ss_info_156d_b560 pci_ss_info_1102_8938_156d_b560 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b700 = + {0x156d, 0xb700, pci_subsys_1102_8938_156d_b700, 0}; +#undef pci_ss_info_156d_b700 +#define pci_ss_info_156d_b700 pci_ss_info_1102_8938_156d_b700 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b795 = + {0x156d, 0xb795, pci_subsys_1102_8938_156d_b795, 0}; +#undef pci_ss_info_156d_b795 +#define pci_ss_info_156d_b795 pci_ss_info_1102_8938_156d_b795 +static const pciSubsystemInfo pci_ss_info_1102_8938_156d_b797 = + {0x156d, 0xb797, pci_subsys_1102_8938_156d_b797, 0}; +#undef pci_ss_info_156d_b797 +#define pci_ss_info_156d_b797 pci_ss_info_1102_8938_156d_b797 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0001 = + {0x1103, 0x0001, pci_subsys_1103_0004_1103_0001, 0}; +#undef pci_ss_info_1103_0001 +#define pci_ss_info_1103_0001 pci_ss_info_1103_0004_1103_0001 +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0004 = + {0x1103, 0x0004, pci_subsys_1103_0004_1103_0004, 0}; +#undef pci_ss_info_1103_0004 +#define pci_ss_info_1103_0004 pci_ss_info_1103_0004_1103_0004 +static const pciSubsystemInfo pci_ss_info_1103_0004_1103_0005 = + {0x1103, 0x0005, pci_subsys_1103_0004_1103_0005, 0}; +#undef pci_ss_info_1103_0005 +#define pci_ss_info_1103_0005 pci_ss_info_1103_0004_1103_0005 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1105_8475_1105_0001 = + {0x1105, 0x0001, pci_subsys_1105_8475_1105_0001, 0}; +#undef pci_ss_info_1105_0001 +#define pci_ss_info_1105_0001 pci_ss_info_1105_8475_1105_0001 +static const pciSubsystemInfo pci_ss_info_1105_8476_127d_0000 = + {0x127d, 0x0000, pci_subsys_1105_8476_127d_0000, 0}; +#undef pci_ss_info_127d_0000 +#define pci_ss_info_127d_0000 pci_ss_info_1105_8476_127d_0000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1106_0282_1043_80a3 = + {0x1043, 0x80a3, pci_subsys_1106_0282_1043_80a3, 0}; +#undef pci_ss_info_1043_80a3 +#define pci_ss_info_1043_80a3 pci_ss_info_1106_0282_1043_80a3 +static const pciSubsystemInfo pci_ss_info_1106_0305_1019_0987 = + {0x1019, 0x0987, pci_subsys_1106_0305_1019_0987, 0}; +#undef pci_ss_info_1019_0987 +#define pci_ss_info_1019_0987 pci_ss_info_1106_0305_1019_0987 +static const pciSubsystemInfo pci_ss_info_1106_0305_1043_8033 = + {0x1043, 0x8033, pci_subsys_1106_0305_1043_8033, 0}; +#undef pci_ss_info_1043_8033 +#define pci_ss_info_1043_8033 pci_ss_info_1106_0305_1043_8033 +static const pciSubsystemInfo pci_ss_info_1106_0305_1043_803e = + {0x1043, 0x803e, pci_subsys_1106_0305_1043_803e, 0}; +#undef pci_ss_info_1043_803e +#define pci_ss_info_1043_803e pci_ss_info_1106_0305_1043_803e +static const pciSubsystemInfo pci_ss_info_1106_0305_1043_8042 = + {0x1043, 0x8042, pci_subsys_1106_0305_1043_8042, 0}; +#undef pci_ss_info_1043_8042 +#define pci_ss_info_1043_8042 pci_ss_info_1106_0305_1043_8042 +static const pciSubsystemInfo pci_ss_info_1106_0305_147b_a401 = + {0x147b, 0xa401, pci_subsys_1106_0305_147b_a401, 0}; +#undef pci_ss_info_147b_a401 +#define pci_ss_info_147b_a401 pci_ss_info_1106_0305_147b_a401 +static const pciSubsystemInfo pci_ss_info_1106_0571_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_0571_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_0571_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_0571_1019_0a81 = + {0x1019, 0x0a81, pci_subsys_1106_0571_1019_0a81, 0}; +#undef pci_ss_info_1019_0a81 +#define pci_ss_info_1019_0a81 pci_ss_info_1106_0571_1019_0a81 +static const pciSubsystemInfo pci_ss_info_1106_0571_1043_8052 = + {0x1043, 0x8052, pci_subsys_1106_0571_1043_8052, 0}; +#undef pci_ss_info_1043_8052 +#define pci_ss_info_1043_8052 pci_ss_info_1106_0571_1043_8052 +static const pciSubsystemInfo pci_ss_info_1106_0571_1043_808c = + {0x1043, 0x808c, pci_subsys_1106_0571_1043_808c, 0}; +#undef pci_ss_info_1043_808c +#define pci_ss_info_1043_808c pci_ss_info_1106_0571_1043_808c +static const pciSubsystemInfo pci_ss_info_1106_0571_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_0571_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_0571_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_0571_1043_80ed = + {0x1043, 0x80ed, pci_subsys_1106_0571_1043_80ed, 0}; +#undef pci_ss_info_1043_80ed +#define pci_ss_info_1043_80ed pci_ss_info_1106_0571_1043_80ed +static const pciSubsystemInfo pci_ss_info_1106_0571_1106_0571 = + {0x1106, 0x0571, pci_subsys_1106_0571_1106_0571, 0}; +#undef pci_ss_info_1106_0571 +#define pci_ss_info_1106_0571 pci_ss_info_1106_0571_1106_0571 +static const pciSubsystemInfo pci_ss_info_1106_0571_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_0571_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_0571_1179_0001 +static const pciSubsystemInfo pci_ss_info_1106_0571_1297_f641 = + {0x1297, 0xf641, pci_subsys_1106_0571_1297_f641, 0}; +#undef pci_ss_info_1297_f641 +#define pci_ss_info_1297_f641 pci_ss_info_1106_0571_1297_f641 +static const pciSubsystemInfo pci_ss_info_1106_0571_1458_5002 = + {0x1458, 0x5002, pci_subsys_1106_0571_1458_5002, 0}; +#undef pci_ss_info_1458_5002 +#define pci_ss_info_1458_5002 pci_ss_info_1106_0571_1458_5002 +static const pciSubsystemInfo pci_ss_info_1106_0571_1462_7020 = + {0x1462, 0x7020, pci_subsys_1106_0571_1462_7020, 0}; +#undef pci_ss_info_1462_7020 +#define pci_ss_info_1462_7020 pci_ss_info_1106_0571_1462_7020 +static const pciSubsystemInfo pci_ss_info_1106_0571_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_0571_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_0571_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_0571_1849_0571 = + {0x1849, 0x0571, pci_subsys_1106_0571_1849_0571, 0}; +#undef pci_ss_info_1849_0571 +#define pci_ss_info_1849_0571 pci_ss_info_1106_0571_1849_0571 +static const pciSubsystemInfo pci_ss_info_1106_0586_1106_0000 = + {0x1106, 0x0000, pci_subsys_1106_0586_1106_0000, 0}; +#undef pci_ss_info_1106_0000 +#define pci_ss_info_1106_0000 pci_ss_info_1106_0586_1106_0000 +static const pciSubsystemInfo pci_ss_info_1106_0596_1106_0000 = + {0x1106, 0x0000, pci_subsys_1106_0596_1106_0000, 0}; +#undef pci_ss_info_1106_0000 +#define pci_ss_info_1106_0000 pci_ss_info_1106_0596_1106_0000 +static const pciSubsystemInfo pci_ss_info_1106_0596_1458_0596 = + {0x1458, 0x0596, pci_subsys_1106_0596_1458_0596, 0}; +#undef pci_ss_info_1458_0596 +#define pci_ss_info_1458_0596 pci_ss_info_1106_0596_1458_0596 +static const pciSubsystemInfo pci_ss_info_1106_0605_1043_802c = + {0x1043, 0x802c, pci_subsys_1106_0605_1043_802c, 0}; +#undef pci_ss_info_1043_802c +#define pci_ss_info_1043_802c pci_ss_info_1106_0605_1043_802c +static const pciSubsystemInfo pci_ss_info_1106_0686_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_0686_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_0686_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_0686_1043_802c = + {0x1043, 0x802c, pci_subsys_1106_0686_1043_802c, 0}; +#undef pci_ss_info_1043_802c +#define pci_ss_info_1043_802c pci_ss_info_1106_0686_1043_802c +static const pciSubsystemInfo pci_ss_info_1106_0686_1043_8033 = + {0x1043, 0x8033, pci_subsys_1106_0686_1043_8033, 0}; +#undef pci_ss_info_1043_8033 +#define pci_ss_info_1043_8033 pci_ss_info_1106_0686_1043_8033 +static const pciSubsystemInfo pci_ss_info_1106_0686_1043_803e = + {0x1043, 0x803e, pci_subsys_1106_0686_1043_803e, 0}; +#undef pci_ss_info_1043_803e +#define pci_ss_info_1043_803e pci_ss_info_1106_0686_1043_803e +static const pciSubsystemInfo pci_ss_info_1106_0686_1043_8040 = + {0x1043, 0x8040, pci_subsys_1106_0686_1043_8040, 0}; +#undef pci_ss_info_1043_8040 +#define pci_ss_info_1043_8040 pci_ss_info_1106_0686_1043_8040 +static const pciSubsystemInfo pci_ss_info_1106_0686_1043_8042 = + {0x1043, 0x8042, pci_subsys_1106_0686_1043_8042, 0}; +#undef pci_ss_info_1043_8042 +#define pci_ss_info_1043_8042 pci_ss_info_1106_0686_1043_8042 +static const pciSubsystemInfo pci_ss_info_1106_0686_1106_0000 = + {0x1106, 0x0000, pci_subsys_1106_0686_1106_0000, 0}; +#undef pci_ss_info_1106_0000 +#define pci_ss_info_1106_0000 pci_ss_info_1106_0686_1106_0000 +static const pciSubsystemInfo pci_ss_info_1106_0686_1106_0686 = + {0x1106, 0x0686, pci_subsys_1106_0686_1106_0686, 0}; +#undef pci_ss_info_1106_0686 +#define pci_ss_info_1106_0686 pci_ss_info_1106_0686_1106_0686 +static const pciSubsystemInfo pci_ss_info_1106_0686_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_0686_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_0686_1179_0001 +static const pciSubsystemInfo pci_ss_info_1106_0686_147b_a702 = + {0x147b, 0xa702, pci_subsys_1106_0686_147b_a702, 0}; +#undef pci_ss_info_147b_a702 +#define pci_ss_info_147b_a702 pci_ss_info_1106_0686_147b_a702 +static const pciSubsystemInfo pci_ss_info_1106_0691_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_0691_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_0691_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_0691_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_0691_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_0691_1179_0001 +static const pciSubsystemInfo pci_ss_info_1106_0691_1458_0691 = + {0x1458, 0x0691, pci_subsys_1106_0691_1458_0691, 0}; +#undef pci_ss_info_1458_0691 +#define pci_ss_info_1458_0691 pci_ss_info_1106_0691_1458_0691 +static const pciSubsystemInfo pci_ss_info_1106_3038_0925_1234 = + {0x0925, 0x1234, pci_subsys_1106_3038_0925_1234, 0}; +#undef pci_ss_info_0925_1234 +#define pci_ss_info_0925_1234 pci_ss_info_1106_3038_0925_1234 +static const pciSubsystemInfo pci_ss_info_1106_3038_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_3038_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_3038_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_3038_1019_0a81 = + {0x1019, 0x0a81, pci_subsys_1106_3038_1019_0a81, 0}; +#undef pci_ss_info_1019_0a81 +#define pci_ss_info_1019_0a81 pci_ss_info_1106_3038_1019_0a81 +static const pciSubsystemInfo pci_ss_info_1106_3038_1043_8080 = + {0x1043, 0x8080, pci_subsys_1106_3038_1043_8080, 0}; +#undef pci_ss_info_1043_8080 +#define pci_ss_info_1043_8080 pci_ss_info_1106_3038_1043_8080 +static const pciSubsystemInfo pci_ss_info_1106_3038_1043_808c = + {0x1043, 0x808c, pci_subsys_1106_3038_1043_808c, 0}; +#undef pci_ss_info_1043_808c +#define pci_ss_info_1043_808c pci_ss_info_1106_3038_1043_808c +static const pciSubsystemInfo pci_ss_info_1106_3038_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_3038_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_3038_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_3038_1043_80ed = + {0x1043, 0x80ed, pci_subsys_1106_3038_1043_80ed, 0}; +#undef pci_ss_info_1043_80ed +#define pci_ss_info_1043_80ed pci_ss_info_1106_3038_1043_80ed +static const pciSubsystemInfo pci_ss_info_1106_3038_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_3038_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_3038_1179_0001 +static const pciSubsystemInfo pci_ss_info_1106_3038_1458_5004 = + {0x1458, 0x5004, pci_subsys_1106_3038_1458_5004, 0}; +#undef pci_ss_info_1458_5004 +#define pci_ss_info_1458_5004 pci_ss_info_1106_3038_1458_5004 +static const pciSubsystemInfo pci_ss_info_1106_3038_1462_7020 = + {0x1462, 0x7020, pci_subsys_1106_3038_1462_7020, 0}; +#undef pci_ss_info_1462_7020 +#define pci_ss_info_1462_7020 pci_ss_info_1106_3038_1462_7020 +static const pciSubsystemInfo pci_ss_info_1106_3038_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3038_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3038_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3038_182d_201d = + {0x182d, 0x201d, pci_subsys_1106_3038_182d_201d, 0}; +#undef pci_ss_info_182d_201d +#define pci_ss_info_182d_201d pci_ss_info_1106_3038_182d_201d +static const pciSubsystemInfo pci_ss_info_1106_3038_1849_3038 = + {0x1849, 0x3038, pci_subsys_1106_3038_1849_3038, 0}; +#undef pci_ss_info_1849_3038 +#define pci_ss_info_1849_3038 pci_ss_info_1106_3038_1849_3038 +static const pciSubsystemInfo pci_ss_info_1106_3043_10bd_0000 = + {0x10bd, 0x0000, pci_subsys_1106_3043_10bd_0000, 0}; +#undef pci_ss_info_10bd_0000 +#define pci_ss_info_10bd_0000 pci_ss_info_1106_3043_10bd_0000 +static const pciSubsystemInfo pci_ss_info_1106_3043_1106_0100 = + {0x1106, 0x0100, pci_subsys_1106_3043_1106_0100, 0}; +#undef pci_ss_info_1106_0100 +#define pci_ss_info_1106_0100 pci_ss_info_1106_3043_1106_0100 +static const pciSubsystemInfo pci_ss_info_1106_3043_1186_1400 = + {0x1186, 0x1400, pci_subsys_1106_3043_1186_1400, 0}; +#undef pci_ss_info_1186_1400 +#define pci_ss_info_1186_1400 pci_ss_info_1106_3043_1186_1400 +#endif +static const pciSubsystemInfo pci_ss_info_1106_3044_1025_005a = + {0x1025, 0x005a, pci_subsys_1106_3044_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_1106_3044_1025_005a +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1106_3044_1043_808a = + {0x1043, 0x808a, pci_subsys_1106_3044_1043_808a, 0}; +#undef pci_ss_info_1043_808a +#define pci_ss_info_1043_808a pci_ss_info_1106_3044_1043_808a +static const pciSubsystemInfo pci_ss_info_1106_3044_1458_1000 = + {0x1458, 0x1000, pci_subsys_1106_3044_1458_1000, 0}; +#undef pci_ss_info_1458_1000 +#define pci_ss_info_1458_1000 pci_ss_info_1106_3044_1458_1000 +static const pciSubsystemInfo pci_ss_info_1106_3044_1462_207d = + {0x1462, 0x207d, pci_subsys_1106_3044_1462_207d, 0}; +#undef pci_ss_info_1462_207d +#define pci_ss_info_1462_207d pci_ss_info_1106_3044_1462_207d +static const pciSubsystemInfo pci_ss_info_1106_3044_1462_702d = + {0x1462, 0x702d, pci_subsys_1106_3044_1462_702d, 0}; +#undef pci_ss_info_1462_702d +#define pci_ss_info_1462_702d pci_ss_info_1106_3044_1462_702d +static const pciSubsystemInfo pci_ss_info_1106_3044_1462_971d = + {0x1462, 0x971d, pci_subsys_1106_3044_1462_971d, 0}; +#undef pci_ss_info_1462_971d +#define pci_ss_info_1462_971d pci_ss_info_1106_3044_1462_971d +static const pciSubsystemInfo pci_ss_info_1106_3057_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_3057_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_3057_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_3057_1019_0987 = + {0x1019, 0x0987, pci_subsys_1106_3057_1019_0987, 0}; +#undef pci_ss_info_1019_0987 +#define pci_ss_info_1019_0987 pci_ss_info_1106_3057_1019_0987 +static const pciSubsystemInfo pci_ss_info_1106_3057_1043_8033 = + {0x1043, 0x8033, pci_subsys_1106_3057_1043_8033, 0}; +#undef pci_ss_info_1043_8033 +#define pci_ss_info_1043_8033 pci_ss_info_1106_3057_1043_8033 +static const pciSubsystemInfo pci_ss_info_1106_3057_1043_803e = + {0x1043, 0x803e, pci_subsys_1106_3057_1043_803e, 0}; +#undef pci_ss_info_1043_803e +#define pci_ss_info_1043_803e pci_ss_info_1106_3057_1043_803e +static const pciSubsystemInfo pci_ss_info_1106_3057_1043_8040 = + {0x1043, 0x8040, pci_subsys_1106_3057_1043_8040, 0}; +#undef pci_ss_info_1043_8040 +#define pci_ss_info_1043_8040 pci_ss_info_1106_3057_1043_8040 +static const pciSubsystemInfo pci_ss_info_1106_3057_1043_8042 = + {0x1043, 0x8042, pci_subsys_1106_3057_1043_8042, 0}; +#undef pci_ss_info_1043_8042 +#define pci_ss_info_1043_8042 pci_ss_info_1106_3057_1043_8042 +static const pciSubsystemInfo pci_ss_info_1106_3057_1179_0001 = + {0x1179, 0x0001, pci_subsys_1106_3057_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1106_3057_1179_0001 +#endif +static const pciSubsystemInfo pci_ss_info_1106_3058_0e11_0097 = + {0x0e11, 0x0097, pci_subsys_1106_3058_0e11_0097, 0}; +#undef pci_ss_info_0e11_0097 +#define pci_ss_info_0e11_0097 pci_ss_info_1106_3058_0e11_0097 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1106_3058_0e11_b194 = + {0x0e11, 0xb194, pci_subsys_1106_3058_0e11_b194, 0}; +#undef pci_ss_info_0e11_b194 +#define pci_ss_info_0e11_b194 pci_ss_info_1106_3058_0e11_b194 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1106_3058_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_3058_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_3058_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_3058_1019_0987 = + {0x1019, 0x0987, pci_subsys_1106_3058_1019_0987, 0}; +#undef pci_ss_info_1019_0987 +#define pci_ss_info_1019_0987 pci_ss_info_1106_3058_1019_0987 +static const pciSubsystemInfo pci_ss_info_1106_3058_1043_1106 = + {0x1043, 0x1106, pci_subsys_1106_3058_1043_1106, 0}; +#undef pci_ss_info_1043_1106 +#define pci_ss_info_1043_1106 pci_ss_info_1106_3058_1043_1106 +static const pciSubsystemInfo pci_ss_info_1106_3058_1106_4511 = + {0x1106, 0x4511, pci_subsys_1106_3058_1106_4511, 0}; +#undef pci_ss_info_1106_4511 +#define pci_ss_info_1106_4511 pci_ss_info_1106_3058_1106_4511 +static const pciSubsystemInfo pci_ss_info_1106_3058_1458_7600 = + {0x1458, 0x7600, pci_subsys_1106_3058_1458_7600, 0}; +#undef pci_ss_info_1458_7600 +#define pci_ss_info_1458_7600 pci_ss_info_1106_3058_1458_7600 +static const pciSubsystemInfo pci_ss_info_1106_3058_1462_3091 = + {0x1462, 0x3091, pci_subsys_1106_3058_1462_3091, 0}; +#undef pci_ss_info_1462_3091 +#define pci_ss_info_1462_3091 pci_ss_info_1106_3058_1462_3091 +static const pciSubsystemInfo pci_ss_info_1106_3058_1462_3300 = + {0x1462, 0x3300, pci_subsys_1106_3058_1462_3300, 0}; +#undef pci_ss_info_1462_3300 +#define pci_ss_info_1462_3300 pci_ss_info_1106_3058_1462_3300 +static const pciSubsystemInfo pci_ss_info_1106_3058_15dd_7609 = + {0x15dd, 0x7609, pci_subsys_1106_3058_15dd_7609, 0}; +#undef pci_ss_info_15dd_7609 +#define pci_ss_info_15dd_7609 pci_ss_info_1106_3058_15dd_7609 +static const pciSubsystemInfo pci_ss_info_1106_3059_1019_0a81 = + {0x1019, 0x0a81, pci_subsys_1106_3059_1019_0a81, 0}; +#undef pci_ss_info_1019_0a81 +#define pci_ss_info_1019_0a81 pci_ss_info_1106_3059_1019_0a81 +static const pciSubsystemInfo pci_ss_info_1106_3059_1043_8095 = + {0x1043, 0x8095, pci_subsys_1106_3059_1043_8095, 0}; +#undef pci_ss_info_1043_8095 +#define pci_ss_info_1043_8095 pci_ss_info_1106_3059_1043_8095 +static const pciSubsystemInfo pci_ss_info_1106_3059_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_3059_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_3059_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_3059_1043_80b0 = + {0x1043, 0x80b0, pci_subsys_1106_3059_1043_80b0, 0}; +#undef pci_ss_info_1043_80b0 +#define pci_ss_info_1043_80b0 pci_ss_info_1106_3059_1043_80b0 +static const pciSubsystemInfo pci_ss_info_1106_3059_1043_812a = + {0x1043, 0x812a, pci_subsys_1106_3059_1043_812a, 0}; +#undef pci_ss_info_1043_812a +#define pci_ss_info_1043_812a pci_ss_info_1106_3059_1043_812a +static const pciSubsystemInfo pci_ss_info_1106_3059_1106_3059 = + {0x1106, 0x3059, pci_subsys_1106_3059_1106_3059, 0}; +#undef pci_ss_info_1106_3059 +#define pci_ss_info_1106_3059 pci_ss_info_1106_3059_1106_3059 +static const pciSubsystemInfo pci_ss_info_1106_3059_1106_4161 = + {0x1106, 0x4161, pci_subsys_1106_3059_1106_4161, 0}; +#undef pci_ss_info_1106_4161 +#define pci_ss_info_1106_4161 pci_ss_info_1106_3059_1106_4161 +static const pciSubsystemInfo pci_ss_info_1106_3059_1106_4170 = + {0x1106, 0x4170, pci_subsys_1106_3059_1106_4170, 0}; +#undef pci_ss_info_1106_4170 +#define pci_ss_info_1106_4170 pci_ss_info_1106_3059_1106_4170 +static const pciSubsystemInfo pci_ss_info_1106_3059_1106_4552 = + {0x1106, 0x4552, pci_subsys_1106_3059_1106_4552, 0}; +#undef pci_ss_info_1106_4552 +#define pci_ss_info_1106_4552 pci_ss_info_1106_3059_1106_4552 +static const pciSubsystemInfo pci_ss_info_1106_3059_1297_c160 = + {0x1297, 0xc160, pci_subsys_1106_3059_1297_c160, 0}; +#undef pci_ss_info_1297_c160 +#define pci_ss_info_1297_c160 pci_ss_info_1106_3059_1297_c160 +static const pciSubsystemInfo pci_ss_info_1106_3059_1458_a002 = + {0x1458, 0xa002, pci_subsys_1106_3059_1458_a002, 0}; +#undef pci_ss_info_1458_a002 +#define pci_ss_info_1458_a002 pci_ss_info_1106_3059_1458_a002 +static const pciSubsystemInfo pci_ss_info_1106_3059_1462_0080 = + {0x1462, 0x0080, pci_subsys_1106_3059_1462_0080, 0}; +#undef pci_ss_info_1462_0080 +#define pci_ss_info_1462_0080 pci_ss_info_1106_3059_1462_0080 +static const pciSubsystemInfo pci_ss_info_1106_3059_1462_3800 = + {0x1462, 0x3800, pci_subsys_1106_3059_1462_3800, 0}; +#undef pci_ss_info_1462_3800 +#define pci_ss_info_1462_3800 pci_ss_info_1106_3059_1462_3800 +static const pciSubsystemInfo pci_ss_info_1106_3059_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3059_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3059_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3059_1849_9761 = + {0x1849, 0x9761, pci_subsys_1106_3059_1849_9761, 0}; +#undef pci_ss_info_1849_9761 +#define pci_ss_info_1849_9761 pci_ss_info_1106_3059_1849_9761 +#endif +static const pciSubsystemInfo pci_ss_info_1106_3059_4005_4710 = + {0x4005, 0x4710, pci_subsys_1106_3059_4005_4710, 0}; +#undef pci_ss_info_4005_4710 +#define pci_ss_info_4005_4710 pci_ss_info_1106_3059_4005_4710 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1106_3059_a0a0_01b6 = + {0xa0a0, 0x01b6, pci_subsys_1106_3059_a0a0_01b6, 0}; +#undef pci_ss_info_a0a0_01b6 +#define pci_ss_info_a0a0_01b6 pci_ss_info_1106_3059_a0a0_01b6 +static const pciSubsystemInfo pci_ss_info_1106_3065_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_3065_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_3065_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_3065_1106_0102 = + {0x1106, 0x0102, pci_subsys_1106_3065_1106_0102, 0}; +#undef pci_ss_info_1106_0102 +#define pci_ss_info_1106_0102 pci_ss_info_1106_3065_1106_0102 +static const pciSubsystemInfo pci_ss_info_1106_3065_1186_1400 = + {0x1186, 0x1400, pci_subsys_1106_3065_1186_1400, 0}; +#undef pci_ss_info_1186_1400 +#define pci_ss_info_1186_1400 pci_ss_info_1106_3065_1186_1400 +static const pciSubsystemInfo pci_ss_info_1106_3065_1186_1401 = + {0x1186, 0x1401, pci_subsys_1106_3065_1186_1401, 0}; +#undef pci_ss_info_1186_1401 +#define pci_ss_info_1186_1401 pci_ss_info_1106_3065_1186_1401 +static const pciSubsystemInfo pci_ss_info_1106_3065_13b9_1421 = + {0x13b9, 0x1421, pci_subsys_1106_3065_13b9_1421, 0}; +#undef pci_ss_info_13b9_1421 +#define pci_ss_info_13b9_1421 pci_ss_info_1106_3065_13b9_1421 +static const pciSubsystemInfo pci_ss_info_1106_3065_147b_1c09 = + {0x147b, 0x1c09, pci_subsys_1106_3065_147b_1c09, 0}; +#undef pci_ss_info_147b_1c09 +#define pci_ss_info_147b_1c09 pci_ss_info_1106_3065_147b_1c09 +static const pciSubsystemInfo pci_ss_info_1106_3065_1695_3005 = + {0x1695, 0x3005, pci_subsys_1106_3065_1695_3005, 0}; +#undef pci_ss_info_1695_3005 +#define pci_ss_info_1695_3005 pci_ss_info_1106_3065_1695_3005 +static const pciSubsystemInfo pci_ss_info_1106_3065_1695_300c = + {0x1695, 0x300c, pci_subsys_1106_3065_1695_300c, 0}; +#undef pci_ss_info_1695_300c +#define pci_ss_info_1695_300c pci_ss_info_1106_3065_1695_300c +static const pciSubsystemInfo pci_ss_info_1106_3065_1849_3065 = + {0x1849, 0x3065, pci_subsys_1106_3065_1849_3065, 0}; +#undef pci_ss_info_1849_3065 +#define pci_ss_info_1849_3065 pci_ss_info_1106_3065_1849_3065 +static const pciSubsystemInfo pci_ss_info_1106_3068_1462_309e = + {0x1462, 0x309e, pci_subsys_1106_3068_1462_309e, 0}; +#undef pci_ss_info_1462_309e +#define pci_ss_info_1462_309e pci_ss_info_1106_3068_1462_309e +static const pciSubsystemInfo pci_ss_info_1106_3074_1043_8052 = + {0x1043, 0x8052, pci_subsys_1106_3074_1043_8052, 0}; +#undef pci_ss_info_1043_8052 +#define pci_ss_info_1043_8052 pci_ss_info_1106_3074_1043_8052 +static const pciSubsystemInfo pci_ss_info_1106_3099_1043_8064 = + {0x1043, 0x8064, pci_subsys_1106_3099_1043_8064, 0}; +#undef pci_ss_info_1043_8064 +#define pci_ss_info_1043_8064 pci_ss_info_1106_3099_1043_8064 +static const pciSubsystemInfo pci_ss_info_1106_3099_1043_807f = + {0x1043, 0x807f, pci_subsys_1106_3099_1043_807f, 0}; +#undef pci_ss_info_1043_807f +#define pci_ss_info_1043_807f pci_ss_info_1106_3099_1043_807f +static const pciSubsystemInfo pci_ss_info_1106_3099_1849_3099 = + {0x1849, 0x3099, pci_subsys_1106_3099_1849_3099, 0}; +#undef pci_ss_info_1849_3099 +#define pci_ss_info_1849_3099 pci_ss_info_1106_3099_1849_3099 +static const pciSubsystemInfo pci_ss_info_1106_3104_1019_0a81 = + {0x1019, 0x0a81, pci_subsys_1106_3104_1019_0a81, 0}; +#undef pci_ss_info_1019_0a81 +#define pci_ss_info_1019_0a81 pci_ss_info_1106_3104_1019_0a81 +static const pciSubsystemInfo pci_ss_info_1106_3104_1043_808c = + {0x1043, 0x808c, pci_subsys_1106_3104_1043_808c, 0}; +#undef pci_ss_info_1043_808c +#define pci_ss_info_1043_808c pci_ss_info_1106_3104_1043_808c +static const pciSubsystemInfo pci_ss_info_1106_3104_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_3104_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_3104_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_3104_1043_80ed = + {0x1043, 0x80ed, pci_subsys_1106_3104_1043_80ed, 0}; +#undef pci_ss_info_1043_80ed +#define pci_ss_info_1043_80ed pci_ss_info_1106_3104_1043_80ed +static const pciSubsystemInfo pci_ss_info_1106_3104_1297_f641 = + {0x1297, 0xf641, pci_subsys_1106_3104_1297_f641, 0}; +#undef pci_ss_info_1297_f641 +#define pci_ss_info_1297_f641 pci_ss_info_1106_3104_1297_f641 +static const pciSubsystemInfo pci_ss_info_1106_3104_1458_5004 = + {0x1458, 0x5004, pci_subsys_1106_3104_1458_5004, 0}; +#undef pci_ss_info_1458_5004 +#define pci_ss_info_1458_5004 pci_ss_info_1106_3104_1458_5004 +static const pciSubsystemInfo pci_ss_info_1106_3104_1462_7020 = + {0x1462, 0x7020, pci_subsys_1106_3104_1462_7020, 0}; +#undef pci_ss_info_1462_7020 +#define pci_ss_info_1462_7020 pci_ss_info_1106_3104_1462_7020 +static const pciSubsystemInfo pci_ss_info_1106_3104_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3104_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3104_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3104_182d_201d = + {0x182d, 0x201d, pci_subsys_1106_3104_182d_201d, 0}; +#undef pci_ss_info_182d_201d +#define pci_ss_info_182d_201d pci_ss_info_1106_3104_182d_201d +static const pciSubsystemInfo pci_ss_info_1106_3104_1849_3104 = + {0x1849, 0x3104, pci_subsys_1106_3104_1849_3104, 0}; +#undef pci_ss_info_1849_3104 +#define pci_ss_info_1849_3104 pci_ss_info_1106_3104_1849_3104 +static const pciSubsystemInfo pci_ss_info_1106_3106_1186_1403 = + {0x1186, 0x1403, pci_subsys_1106_3106_1186_1403, 0}; +#undef pci_ss_info_1186_1403 +#define pci_ss_info_1186_1403 pci_ss_info_1106_3106_1186_1403 +static const pciSubsystemInfo pci_ss_info_1106_3116_1297_f641 = + {0x1297, 0xf641, pci_subsys_1106_3116_1297_f641, 0}; +#undef pci_ss_info_1297_f641 +#define pci_ss_info_1297_f641 pci_ss_info_1106_3116_1297_f641 +static const pciSubsystemInfo pci_ss_info_1106_3147_1043_808c = + {0x1043, 0x808c, pci_subsys_1106_3147_1043_808c, 0}; +#undef pci_ss_info_1043_808c +#define pci_ss_info_1043_808c pci_ss_info_1106_3147_1043_808c +static const pciSubsystemInfo pci_ss_info_1106_3149_1043_80ed = + {0x1043, 0x80ed, pci_subsys_1106_3149_1043_80ed, 0}; +#undef pci_ss_info_1043_80ed +#define pci_ss_info_1043_80ed pci_ss_info_1106_3149_1043_80ed +static const pciSubsystemInfo pci_ss_info_1106_3149_1458_b003 = + {0x1458, 0xb003, pci_subsys_1106_3149_1458_b003, 0}; +#undef pci_ss_info_1458_b003 +#define pci_ss_info_1458_b003 pci_ss_info_1106_3149_1458_b003 +static const pciSubsystemInfo pci_ss_info_1106_3149_1462_7020 = + {0x1462, 0x7020, pci_subsys_1106_3149_1462_7020, 0}; +#undef pci_ss_info_1462_7020 +#define pci_ss_info_1462_7020 pci_ss_info_1106_3149_1462_7020 +static const pciSubsystemInfo pci_ss_info_1106_3149_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3149_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3149_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3149_147b_1408 = + {0x147b, 0x1408, pci_subsys_1106_3149_147b_1408, 0}; +#undef pci_ss_info_147b_1408 +#define pci_ss_info_147b_1408 pci_ss_info_1106_3149_147b_1408 +static const pciSubsystemInfo pci_ss_info_1106_3149_1849_3149 = + {0x1849, 0x3149, pci_subsys_1106_3149_1849_3149, 0}; +#undef pci_ss_info_1849_3149 +#define pci_ss_info_1849_3149 pci_ss_info_1106_3149_1849_3149 +static const pciSubsystemInfo pci_ss_info_1106_3164_1043_80f4 = + {0x1043, 0x80f4, pci_subsys_1106_3164_1043_80f4, 0}; +#undef pci_ss_info_1043_80f4 +#define pci_ss_info_1043_80f4 pci_ss_info_1106_3164_1043_80f4 +static const pciSubsystemInfo pci_ss_info_1106_3164_1462_7028 = + {0x1462, 0x7028, pci_subsys_1106_3164_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_1106_3164_1462_7028 +static const pciSubsystemInfo pci_ss_info_1106_3177_1019_0a81 = + {0x1019, 0x0a81, pci_subsys_1106_3177_1019_0a81, 0}; +#undef pci_ss_info_1019_0a81 +#define pci_ss_info_1019_0a81 pci_ss_info_1106_3177_1019_0a81 +static const pciSubsystemInfo pci_ss_info_1106_3177_1043_808c = + {0x1043, 0x808c, pci_subsys_1106_3177_1043_808c, 0}; +#undef pci_ss_info_1043_808c +#define pci_ss_info_1043_808c pci_ss_info_1106_3177_1043_808c +static const pciSubsystemInfo pci_ss_info_1106_3177_1043_80a1 = + {0x1043, 0x80a1, pci_subsys_1106_3177_1043_80a1, 0}; +#undef pci_ss_info_1043_80a1 +#define pci_ss_info_1043_80a1 pci_ss_info_1106_3177_1043_80a1 +static const pciSubsystemInfo pci_ss_info_1106_3177_1297_f641 = + {0x1297, 0xf641, pci_subsys_1106_3177_1297_f641, 0}; +#undef pci_ss_info_1297_f641 +#define pci_ss_info_1297_f641 pci_ss_info_1106_3177_1297_f641 +static const pciSubsystemInfo pci_ss_info_1106_3177_1458_5001 = + {0x1458, 0x5001, pci_subsys_1106_3177_1458_5001, 0}; +#undef pci_ss_info_1458_5001 +#define pci_ss_info_1458_5001 pci_ss_info_1106_3177_1458_5001 +static const pciSubsystemInfo pci_ss_info_1106_3177_1849_3177 = + {0x1849, 0x3177, pci_subsys_1106_3177_1849_3177, 0}; +#undef pci_ss_info_1849_3177 +#define pci_ss_info_1849_3177 pci_ss_info_1106_3177_1849_3177 +static const pciSubsystemInfo pci_ss_info_1106_3188_1043_80a3 = + {0x1043, 0x80a3, pci_subsys_1106_3188_1043_80a3, 0}; +#undef pci_ss_info_1043_80a3 +#define pci_ss_info_1043_80a3 pci_ss_info_1106_3188_1043_80a3 +static const pciSubsystemInfo pci_ss_info_1106_3188_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3188_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3188_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3189_1043_807f = + {0x1043, 0x807f, pci_subsys_1106_3189_1043_807f, 0}; +#undef pci_ss_info_1043_807f +#define pci_ss_info_1043_807f pci_ss_info_1106_3189_1043_807f +static const pciSubsystemInfo pci_ss_info_1106_3189_1458_5000 = + {0x1458, 0x5000, pci_subsys_1106_3189_1458_5000, 0}; +#undef pci_ss_info_1458_5000 +#define pci_ss_info_1458_5000 pci_ss_info_1106_3189_1458_5000 +static const pciSubsystemInfo pci_ss_info_1106_3189_1849_3189 = + {0x1849, 0x3189, pci_subsys_1106_3189_1849_3189, 0}; +#undef pci_ss_info_1849_3189 +#define pci_ss_info_1849_3189 pci_ss_info_1106_3189_1849_3189 +static const pciSubsystemInfo pci_ss_info_1106_3205_1458_5000 = + {0x1458, 0x5000, pci_subsys_1106_3205_1458_5000, 0}; +#undef pci_ss_info_1458_5000 +#define pci_ss_info_1458_5000 pci_ss_info_1106_3205_1458_5000 +static const pciSubsystemInfo pci_ss_info_1106_3227_1043_80ed = + {0x1043, 0x80ed, pci_subsys_1106_3227_1043_80ed, 0}; +#undef pci_ss_info_1043_80ed +#define pci_ss_info_1043_80ed pci_ss_info_1106_3227_1043_80ed +static const pciSubsystemInfo pci_ss_info_1106_3227_1106_3227 = + {0x1106, 0x3227, pci_subsys_1106_3227_1106_3227, 0}; +#undef pci_ss_info_1106_3227 +#define pci_ss_info_1106_3227 pci_ss_info_1106_3227_1106_3227 +static const pciSubsystemInfo pci_ss_info_1106_3227_1458_5001 = + {0x1458, 0x5001, pci_subsys_1106_3227_1458_5001, 0}; +#undef pci_ss_info_1458_5001 +#define pci_ss_info_1458_5001 pci_ss_info_1106_3227_1458_5001 +static const pciSubsystemInfo pci_ss_info_1106_3227_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_3227_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_3227_147b_1407 +static const pciSubsystemInfo pci_ss_info_1106_3227_1849_3227 = + {0x1849, 0x3227, pci_subsys_1106_3227_1849_3227, 0}; +#undef pci_ss_info_1849_3227 +#define pci_ss_info_1849_3227 pci_ss_info_1106_3227_1849_3227 +static const pciSubsystemInfo pci_ss_info_1106_7205_1458_d000 = + {0x1458, 0xd000, pci_subsys_1106_7205_1458_d000, 0}; +#undef pci_ss_info_1458_d000 +#define pci_ss_info_1458_d000 pci_ss_info_1106_7205_1458_d000 +static const pciSubsystemInfo pci_ss_info_1106_8598_1019_0985 = + {0x1019, 0x0985, pci_subsys_1106_8598_1019_0985, 0}; +#undef pci_ss_info_1019_0985 +#define pci_ss_info_1019_0985 pci_ss_info_1106_8598_1019_0985 +static const pciSubsystemInfo pci_ss_info_1106_b188_147b_1407 = + {0x147b, 0x1407, pci_subsys_1106_b188_147b_1407, 0}; +#undef pci_ss_info_147b_1407 +#define pci_ss_info_147b_1407 pci_ss_info_1106_b188_147b_1407 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1113_1211_103c_1207 = + {0x103c, 0x1207, pci_subsys_1113_1211_103c_1207, 0}; +#undef pci_ss_info_103c_1207 +#define pci_ss_info_103c_1207 pci_ss_info_1113_1211_103c_1207 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1113_1211_1113_1211 = + {0x1113, 0x1211, pci_subsys_1113_1211_1113_1211, 0}; +#undef pci_ss_info_1113_1211 +#define pci_ss_info_1113_1211 pci_ss_info_1113_1211_1113_1211 +static const pciSubsystemInfo pci_ss_info_1113_1216_1113_2242 = + {0x1113, 0x2242, pci_subsys_1113_1216_1113_2242, 0}; +#undef pci_ss_info_1113_2242 +#define pci_ss_info_1113_2242 pci_ss_info_1113_1216_1113_2242 +static const pciSubsystemInfo pci_ss_info_1113_1216_111a_1020 = + {0x111a, 0x1020, pci_subsys_1113_1216_111a_1020, 0}; +#undef pci_ss_info_111a_1020 +#define pci_ss_info_111a_1020 pci_ss_info_1113_1216_111a_1020 +static const pciSubsystemInfo pci_ss_info_1113_9211_1113_9211 = + {0x1113, 0x9211, pci_subsys_1113_9211_1113_9211, 0}; +#undef pci_ss_info_1113_9211 +#define pci_ss_info_1113_9211 pci_ss_info_1113_9211_1113_9211 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_111a_0003_111a_0000 = + {0x111a, 0x0000, pci_subsys_111a_0003_111a_0000, 0}; +#undef pci_ss_info_111a_0000 +#define pci_ss_info_111a_0000 pci_ss_info_111a_0003_111a_0000 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0001 = + {0x111a, 0x0001, pci_subsys_111a_0005_111a_0001, 0}; +#undef pci_ss_info_111a_0001 +#define pci_ss_info_111a_0001 pci_ss_info_111a_0005_111a_0001 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0009 = + {0x111a, 0x0009, pci_subsys_111a_0005_111a_0009, 0}; +#undef pci_ss_info_111a_0009 +#define pci_ss_info_111a_0009 pci_ss_info_111a_0005_111a_0009 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0101 = + {0x111a, 0x0101, pci_subsys_111a_0005_111a_0101, 0}; +#undef pci_ss_info_111a_0101 +#define pci_ss_info_111a_0101 pci_ss_info_111a_0005_111a_0101 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0109 = + {0x111a, 0x0109, pci_subsys_111a_0005_111a_0109, 0}; +#undef pci_ss_info_111a_0109 +#define pci_ss_info_111a_0109 pci_ss_info_111a_0005_111a_0109 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0809 = + {0x111a, 0x0809, pci_subsys_111a_0005_111a_0809, 0}; +#undef pci_ss_info_111a_0809 +#define pci_ss_info_111a_0809 pci_ss_info_111a_0005_111a_0809 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0909 = + {0x111a, 0x0909, pci_subsys_111a_0005_111a_0909, 0}; +#undef pci_ss_info_111a_0909 +#define pci_ss_info_111a_0909 pci_ss_info_111a_0005_111a_0909 +static const pciSubsystemInfo pci_ss_info_111a_0005_111a_0a09 = + {0x111a, 0x0a09, pci_subsys_111a_0005_111a_0a09, 0}; +#undef pci_ss_info_111a_0a09 +#define pci_ss_info_111a_0a09 pci_ss_info_111a_0005_111a_0a09 +static const pciSubsystemInfo pci_ss_info_111a_0007_111a_1001 = + {0x111a, 0x1001, pci_subsys_111a_0007_111a_1001, 0}; +#undef pci_ss_info_111a_1001 +#define pci_ss_info_111a_1001 pci_ss_info_111a_0007_111a_1001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1127_0400_1127_0400 = + {0x1127, 0x0400, pci_subsys_1127_0400_1127_0400, 0}; +#undef pci_ss_info_1127_0400 +#define pci_ss_info_1127_0400 pci_ss_info_1127_0400_1127_0400 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1131_5402_1244_0f00 = + {0x1244, 0x0f00, pci_subsys_1131_5402_1244_0f00, 0}; +#undef pci_ss_info_1244_0f00 +#define pci_ss_info_1244_0f00 pci_ss_info_1131_5402_1244_0f00 +#endif +static const pciSubsystemInfo pci_ss_info_1131_7130_102b_48d0 = + {0x102b, 0x48d0, pci_subsys_1131_7130_102b_48d0, 0}; +#undef pci_ss_info_102b_48d0 +#define pci_ss_info_102b_48d0 pci_ss_info_1131_7130_102b_48d0 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1131_7130_1048_226b = + {0x1048, 0x226b, pci_subsys_1131_7130_1048_226b, 0}; +#undef pci_ss_info_1048_226b +#define pci_ss_info_1048_226b pci_ss_info_1131_7130_1048_226b +static const pciSubsystemInfo pci_ss_info_1131_7130_1131_2001 = + {0x1131, 0x2001, pci_subsys_1131_7130_1131_2001, 0}; +#undef pci_ss_info_1131_2001 +#define pci_ss_info_1131_2001 pci_ss_info_1131_7130_1131_2001 +static const pciSubsystemInfo pci_ss_info_1131_7130_1131_2005 = + {0x1131, 0x2005, pci_subsys_1131_7130_1131_2005, 0}; +#undef pci_ss_info_1131_2005 +#define pci_ss_info_1131_2005 pci_ss_info_1131_7130_1131_2005 +static const pciSubsystemInfo pci_ss_info_1131_7130_1461_050c = + {0x1461, 0x050c, pci_subsys_1131_7130_1461_050c, 0}; +#undef pci_ss_info_1461_050c +#define pci_ss_info_1461_050c pci_ss_info_1131_7130_1461_050c +static const pciSubsystemInfo pci_ss_info_1131_7130_1461_10ff = + {0x1461, 0x10ff, pci_subsys_1131_7130_1461_10ff, 0}; +#undef pci_ss_info_1461_10ff +#define pci_ss_info_1461_10ff pci_ss_info_1131_7130_1461_10ff +static const pciSubsystemInfo pci_ss_info_1131_7130_1461_2108 = + {0x1461, 0x2108, pci_subsys_1131_7130_1461_2108, 0}; +#undef pci_ss_info_1461_2108 +#define pci_ss_info_1461_2108 pci_ss_info_1131_7130_1461_2108 +static const pciSubsystemInfo pci_ss_info_1131_7130_1461_2115 = + {0x1461, 0x2115, pci_subsys_1131_7130_1461_2115, 0}; +#undef pci_ss_info_1461_2115 +#define pci_ss_info_1461_2115 pci_ss_info_1131_7130_1461_2115 +static const pciSubsystemInfo pci_ss_info_1131_7130_153b_1152 = + {0x153b, 0x1152, pci_subsys_1131_7130_153b_1152, 0}; +#undef pci_ss_info_153b_1152 +#define pci_ss_info_153b_1152 pci_ss_info_1131_7130_153b_1152 +static const pciSubsystemInfo pci_ss_info_1131_7130_185b_c100 = + {0x185b, 0xc100, pci_subsys_1131_7130_185b_c100, 0}; +#undef pci_ss_info_185b_c100 +#define pci_ss_info_185b_c100 pci_ss_info_1131_7130_185b_c100 +static const pciSubsystemInfo pci_ss_info_1131_7130_185b_c901 = + {0x185b, 0xc901, pci_subsys_1131_7130_185b_c901, 0}; +#undef pci_ss_info_185b_c901 +#define pci_ss_info_185b_c901 pci_ss_info_1131_7130_185b_c901 +static const pciSubsystemInfo pci_ss_info_1131_7130_5168_0138 = + {0x5168, 0x0138, pci_subsys_1131_7130_5168_0138, 0}; +#undef pci_ss_info_5168_0138 +#define pci_ss_info_5168_0138 pci_ss_info_1131_7130_5168_0138 +static const pciSubsystemInfo pci_ss_info_1131_7133_0000_4091 = + {0x0000, 0x4091, pci_subsys_1131_7133_0000_4091, 0}; +#undef pci_ss_info_0000_4091 +#define pci_ss_info_0000_4091 pci_ss_info_1131_7133_0000_4091 +static const pciSubsystemInfo pci_ss_info_1131_7133_1019_4cb5 = + {0x1019, 0x4cb5, pci_subsys_1131_7133_1019_4cb5, 0}; +#undef pci_ss_info_1019_4cb5 +#define pci_ss_info_1019_4cb5 pci_ss_info_1131_7133_1019_4cb5 +static const pciSubsystemInfo pci_ss_info_1131_7133_1043_0210 = + {0x1043, 0x0210, pci_subsys_1131_7133_1043_0210, 0}; +#undef pci_ss_info_1043_0210 +#define pci_ss_info_1043_0210 pci_ss_info_1131_7133_1043_0210 +static const pciSubsystemInfo pci_ss_info_1131_7133_1043_4843 = + {0x1043, 0x4843, pci_subsys_1131_7133_1043_4843, 0}; +#undef pci_ss_info_1043_4843 +#define pci_ss_info_1043_4843 pci_ss_info_1131_7133_1043_4843 +static const pciSubsystemInfo pci_ss_info_1131_7133_1043_4845 = + {0x1043, 0x4845, pci_subsys_1131_7133_1043_4845, 0}; +#undef pci_ss_info_1043_4845 +#define pci_ss_info_1043_4845 pci_ss_info_1131_7133_1043_4845 +static const pciSubsystemInfo pci_ss_info_1131_7133_1043_4862 = + {0x1043, 0x4862, pci_subsys_1131_7133_1043_4862, 0}; +#undef pci_ss_info_1043_4862 +#define pci_ss_info_1043_4862 pci_ss_info_1131_7133_1043_4862 +static const pciSubsystemInfo pci_ss_info_1131_7133_1131_2001 = + {0x1131, 0x2001, pci_subsys_1131_7133_1131_2001, 0}; +#undef pci_ss_info_1131_2001 +#define pci_ss_info_1131_2001 pci_ss_info_1131_7133_1131_2001 +static const pciSubsystemInfo pci_ss_info_1131_7133_1131_2018 = + {0x1131, 0x2018, pci_subsys_1131_7133_1131_2018, 0}; +#undef pci_ss_info_1131_2018 +#define pci_ss_info_1131_2018 pci_ss_info_1131_7133_1131_2018 +static const pciSubsystemInfo pci_ss_info_1131_7133_1131_4ee9 = + {0x1131, 0x4ee9, pci_subsys_1131_7133_1131_4ee9, 0}; +#undef pci_ss_info_1131_4ee9 +#define pci_ss_info_1131_4ee9 pci_ss_info_1131_7133_1131_4ee9 +static const pciSubsystemInfo pci_ss_info_1131_7133_11bd_002b = + {0x11bd, 0x002b, pci_subsys_1131_7133_11bd_002b, 0}; +#undef pci_ss_info_11bd_002b +#define pci_ss_info_11bd_002b pci_ss_info_1131_7133_11bd_002b +static const pciSubsystemInfo pci_ss_info_1131_7133_11bd_002e = + {0x11bd, 0x002e, pci_subsys_1131_7133_11bd_002e, 0}; +#undef pci_ss_info_11bd_002e +#define pci_ss_info_11bd_002e pci_ss_info_1131_7133_11bd_002e +static const pciSubsystemInfo pci_ss_info_1131_7133_12ab_0800 = + {0x12ab, 0x0800, pci_subsys_1131_7133_12ab_0800, 0}; +#undef pci_ss_info_12ab_0800 +#define pci_ss_info_12ab_0800 pci_ss_info_1131_7133_12ab_0800 +static const pciSubsystemInfo pci_ss_info_1131_7133_1421_0335 = + {0x1421, 0x0335, pci_subsys_1131_7133_1421_0335, 0}; +#undef pci_ss_info_1421_0335 +#define pci_ss_info_1421_0335 pci_ss_info_1131_7133_1421_0335 +static const pciSubsystemInfo pci_ss_info_1131_7133_1421_1370 = + {0x1421, 0x1370, pci_subsys_1131_7133_1421_1370, 0}; +#undef pci_ss_info_1421_1370 +#define pci_ss_info_1421_1370 pci_ss_info_1131_7133_1421_1370 +static const pciSubsystemInfo pci_ss_info_1131_7133_1435_7330 = + {0x1435, 0x7330, pci_subsys_1131_7133_1435_7330, 0}; +#undef pci_ss_info_1435_7330 +#define pci_ss_info_1435_7330 pci_ss_info_1131_7133_1435_7330 +static const pciSubsystemInfo pci_ss_info_1131_7133_1435_7350 = + {0x1435, 0x7350, pci_subsys_1131_7133_1435_7350, 0}; +#undef pci_ss_info_1435_7350 +#define pci_ss_info_1435_7350 pci_ss_info_1131_7133_1435_7350 +static const pciSubsystemInfo pci_ss_info_1131_7133_1461_1044 = + {0x1461, 0x1044, pci_subsys_1131_7133_1461_1044, 0}; +#undef pci_ss_info_1461_1044 +#define pci_ss_info_1461_1044 pci_ss_info_1131_7133_1461_1044 +static const pciSubsystemInfo pci_ss_info_1131_7133_1461_f31f = + {0x1461, 0xf31f, pci_subsys_1131_7133_1461_f31f, 0}; +#undef pci_ss_info_1461_f31f +#define pci_ss_info_1461_f31f pci_ss_info_1131_7133_1461_f31f +static const pciSubsystemInfo pci_ss_info_1131_7133_1462_6231 = + {0x1462, 0x6231, pci_subsys_1131_7133_1462_6231, 0}; +#undef pci_ss_info_1462_6231 +#define pci_ss_info_1462_6231 pci_ss_info_1131_7133_1462_6231 +static const pciSubsystemInfo pci_ss_info_1131_7133_1489_0214 = + {0x1489, 0x0214, pci_subsys_1131_7133_1489_0214, 0}; +#undef pci_ss_info_1489_0214 +#define pci_ss_info_1489_0214 pci_ss_info_1131_7133_1489_0214 +static const pciSubsystemInfo pci_ss_info_1131_7133_14c0_1212 = + {0x14c0, 0x1212, pci_subsys_1131_7133_14c0_1212, 0}; +#undef pci_ss_info_14c0_1212 +#define pci_ss_info_14c0_1212 pci_ss_info_1131_7133_14c0_1212 +static const pciSubsystemInfo pci_ss_info_1131_7133_153b_1160 = + {0x153b, 0x1160, pci_subsys_1131_7133_153b_1160, 0}; +#undef pci_ss_info_153b_1160 +#define pci_ss_info_153b_1160 pci_ss_info_1131_7133_153b_1160 +static const pciSubsystemInfo pci_ss_info_1131_7133_153b_1162 = + {0x153b, 0x1162, pci_subsys_1131_7133_153b_1162, 0}; +#undef pci_ss_info_153b_1162 +#define pci_ss_info_153b_1162 pci_ss_info_1131_7133_153b_1162 +static const pciSubsystemInfo pci_ss_info_1131_7133_185b_c100 = + {0x185b, 0xc100, pci_subsys_1131_7133_185b_c100, 0}; +#undef pci_ss_info_185b_c100 +#define pci_ss_info_185b_c100 pci_ss_info_1131_7133_185b_c100 +static const pciSubsystemInfo pci_ss_info_1131_7133_5168_0306 = + {0x5168, 0x0306, pci_subsys_1131_7133_5168_0306, 0}; +#undef pci_ss_info_5168_0306 +#define pci_ss_info_5168_0306 pci_ss_info_1131_7133_5168_0306 +static const pciSubsystemInfo pci_ss_info_1131_7133_5168_0319 = + {0x5168, 0x0319, pci_subsys_1131_7133_5168_0319, 0}; +#undef pci_ss_info_5168_0319 +#define pci_ss_info_5168_0319 pci_ss_info_1131_7133_5168_0319 +static const pciSubsystemInfo pci_ss_info_1131_7133_5168_0502 = + {0x5168, 0x0502, pci_subsys_1131_7133_5168_0502, 0}; +#undef pci_ss_info_5168_0502 +#define pci_ss_info_5168_0502 pci_ss_info_1131_7133_5168_0502 +static const pciSubsystemInfo pci_ss_info_1131_7133_5168_0520 = + {0x5168, 0x0520, pci_subsys_1131_7133_5168_0520, 0}; +#undef pci_ss_info_5168_0520 +#define pci_ss_info_5168_0520 pci_ss_info_1131_7133_5168_0520 +static const pciSubsystemInfo pci_ss_info_1131_7133_5168_1502 = + {0x5168, 0x1502, pci_subsys_1131_7133_5168_1502, 0}; +#undef pci_ss_info_5168_1502 +#define pci_ss_info_5168_1502 pci_ss_info_1131_7133_5168_1502 +static const pciSubsystemInfo pci_ss_info_1131_7133_5168_2502 = + {0x5168, 0x2502, pci_subsys_1131_7133_5168_2502, 0}; +#undef pci_ss_info_5168_2502 +#define pci_ss_info_5168_2502 pci_ss_info_1131_7133_5168_2502 +static const pciSubsystemInfo pci_ss_info_1131_7133_5168_2520 = + {0x5168, 0x2520, pci_subsys_1131_7133_5168_2520, 0}; +#undef pci_ss_info_5168_2520 +#define pci_ss_info_5168_2520 pci_ss_info_1131_7133_5168_2520 +static const pciSubsystemInfo pci_ss_info_1131_7133_5168_3502 = + {0x5168, 0x3502, pci_subsys_1131_7133_5168_3502, 0}; +#undef pci_ss_info_5168_3502 +#define pci_ss_info_5168_3502 pci_ss_info_1131_7133_5168_3502 +static const pciSubsystemInfo pci_ss_info_1131_7133_5168_3520 = + {0x5168, 0x3520, pci_subsys_1131_7133_5168_3520, 0}; +#undef pci_ss_info_5168_3520 +#define pci_ss_info_5168_3520 pci_ss_info_1131_7133_5168_3520 +static const pciSubsystemInfo pci_ss_info_1131_7134_1019_4cb4 = + {0x1019, 0x4cb4, pci_subsys_1131_7134_1019_4cb4, 0}; +#undef pci_ss_info_1019_4cb4 +#define pci_ss_info_1019_4cb4 pci_ss_info_1131_7134_1019_4cb4 +static const pciSubsystemInfo pci_ss_info_1131_7134_1043_0210 = + {0x1043, 0x0210, pci_subsys_1131_7134_1043_0210, 0}; +#undef pci_ss_info_1043_0210 +#define pci_ss_info_1043_0210 pci_ss_info_1131_7134_1043_0210 +static const pciSubsystemInfo pci_ss_info_1131_7134_1043_4840 = + {0x1043, 0x4840, pci_subsys_1131_7134_1043_4840, 0}; +#undef pci_ss_info_1043_4840 +#define pci_ss_info_1043_4840 pci_ss_info_1131_7134_1043_4840 +static const pciSubsystemInfo pci_ss_info_1131_7134_1043_4842 = + {0x1043, 0x4842, pci_subsys_1131_7134_1043_4842, 0}; +#undef pci_ss_info_1043_4842 +#define pci_ss_info_1043_4842 pci_ss_info_1131_7134_1043_4842 +static const pciSubsystemInfo pci_ss_info_1131_7134_1131_2004 = + {0x1131, 0x2004, pci_subsys_1131_7134_1131_2004, 0}; +#undef pci_ss_info_1131_2004 +#define pci_ss_info_1131_2004 pci_ss_info_1131_7134_1131_2004 +static const pciSubsystemInfo pci_ss_info_1131_7134_1131_4e85 = + {0x1131, 0x4e85, pci_subsys_1131_7134_1131_4e85, 0}; +#undef pci_ss_info_1131_4e85 +#define pci_ss_info_1131_4e85 pci_ss_info_1131_7134_1131_4e85 +static const pciSubsystemInfo pci_ss_info_1131_7134_1131_6752 = + {0x1131, 0x6752, pci_subsys_1131_7134_1131_6752, 0}; +#undef pci_ss_info_1131_6752 +#define pci_ss_info_1131_6752 pci_ss_info_1131_7134_1131_6752 +static const pciSubsystemInfo pci_ss_info_1131_7134_11bd_002b = + {0x11bd, 0x002b, pci_subsys_1131_7134_11bd_002b, 0}; +#undef pci_ss_info_11bd_002b +#define pci_ss_info_11bd_002b pci_ss_info_1131_7134_11bd_002b +static const pciSubsystemInfo pci_ss_info_1131_7134_11bd_002d = + {0x11bd, 0x002d, pci_subsys_1131_7134_11bd_002d, 0}; +#undef pci_ss_info_11bd_002d +#define pci_ss_info_11bd_002d pci_ss_info_1131_7134_11bd_002d +static const pciSubsystemInfo pci_ss_info_1131_7134_1461_2c00 = + {0x1461, 0x2c00, pci_subsys_1131_7134_1461_2c00, 0}; +#undef pci_ss_info_1461_2c00 +#define pci_ss_info_1461_2c00 pci_ss_info_1131_7134_1461_2c00 +static const pciSubsystemInfo pci_ss_info_1131_7134_1461_9715 = + {0x1461, 0x9715, pci_subsys_1131_7134_1461_9715, 0}; +#undef pci_ss_info_1461_9715 +#define pci_ss_info_1461_9715 pci_ss_info_1131_7134_1461_9715 +static const pciSubsystemInfo pci_ss_info_1131_7134_1461_a70a = + {0x1461, 0xa70a, pci_subsys_1131_7134_1461_a70a, 0}; +#undef pci_ss_info_1461_a70a +#define pci_ss_info_1461_a70a pci_ss_info_1131_7134_1461_a70a +static const pciSubsystemInfo pci_ss_info_1131_7134_1461_a70b = + {0x1461, 0xa70b, pci_subsys_1131_7134_1461_a70b, 0}; +#undef pci_ss_info_1461_a70b +#define pci_ss_info_1461_a70b pci_ss_info_1131_7134_1461_a70b +static const pciSubsystemInfo pci_ss_info_1131_7134_1461_d6ee = + {0x1461, 0xd6ee, pci_subsys_1131_7134_1461_d6ee, 0}; +#undef pci_ss_info_1461_d6ee +#define pci_ss_info_1461_d6ee pci_ss_info_1131_7134_1461_d6ee +static const pciSubsystemInfo pci_ss_info_1131_7134_1471_b7e9 = + {0x1471, 0xb7e9, pci_subsys_1131_7134_1471_b7e9, 0}; +#undef pci_ss_info_1471_b7e9 +#define pci_ss_info_1471_b7e9 pci_ss_info_1131_7134_1471_b7e9 +static const pciSubsystemInfo pci_ss_info_1131_7134_153b_1142 = + {0x153b, 0x1142, pci_subsys_1131_7134_153b_1142, 0}; +#undef pci_ss_info_153b_1142 +#define pci_ss_info_153b_1142 pci_ss_info_1131_7134_153b_1142 +static const pciSubsystemInfo pci_ss_info_1131_7134_153b_1143 = + {0x153b, 0x1143, pci_subsys_1131_7134_153b_1143, 0}; +#undef pci_ss_info_153b_1143 +#define pci_ss_info_153b_1143 pci_ss_info_1131_7134_153b_1143 +static const pciSubsystemInfo pci_ss_info_1131_7134_153b_1158 = + {0x153b, 0x1158, pci_subsys_1131_7134_153b_1158, 0}; +#undef pci_ss_info_153b_1158 +#define pci_ss_info_153b_1158 pci_ss_info_1131_7134_153b_1158 +static const pciSubsystemInfo pci_ss_info_1131_7134_1540_9524 = + {0x1540, 0x9524, pci_subsys_1131_7134_1540_9524, 0}; +#undef pci_ss_info_1540_9524 +#define pci_ss_info_1540_9524 pci_ss_info_1131_7134_1540_9524 +static const pciSubsystemInfo pci_ss_info_1131_7134_16be_0003 = + {0x16be, 0x0003, pci_subsys_1131_7134_16be_0003, 0}; +#undef pci_ss_info_16be_0003 +#define pci_ss_info_16be_0003 pci_ss_info_1131_7134_16be_0003 +static const pciSubsystemInfo pci_ss_info_1131_7134_185b_c200 = + {0x185b, 0xc200, pci_subsys_1131_7134_185b_c200, 0}; +#undef pci_ss_info_185b_c200 +#define pci_ss_info_185b_c200 pci_ss_info_1131_7134_185b_c200 +static const pciSubsystemInfo pci_ss_info_1131_7134_185b_c900 = + {0x185b, 0xc900, pci_subsys_1131_7134_185b_c900, 0}; +#undef pci_ss_info_185b_c900 +#define pci_ss_info_185b_c900 pci_ss_info_1131_7134_185b_c900 +static const pciSubsystemInfo pci_ss_info_1131_7134_1894_a006 = + {0x1894, 0xa006, pci_subsys_1131_7134_1894_a006, 0}; +#undef pci_ss_info_1894_a006 +#define pci_ss_info_1894_a006 pci_ss_info_1131_7134_1894_a006 +static const pciSubsystemInfo pci_ss_info_1131_7134_1894_fe01 = + {0x1894, 0xfe01, pci_subsys_1131_7134_1894_fe01, 0}; +#undef pci_ss_info_1894_fe01 +#define pci_ss_info_1894_fe01 pci_ss_info_1131_7134_1894_fe01 +static const pciSubsystemInfo pci_ss_info_1131_7146_110a_0000 = + {0x110a, 0x0000, pci_subsys_1131_7146_110a_0000, 0}; +#undef pci_ss_info_110a_0000 +#define pci_ss_info_110a_0000 pci_ss_info_1131_7146_110a_0000 +static const pciSubsystemInfo pci_ss_info_1131_7146_110a_ffff = + {0x110a, 0xffff, pci_subsys_1131_7146_110a_ffff, 0}; +#undef pci_ss_info_110a_ffff +#define pci_ss_info_110a_ffff pci_ss_info_1131_7146_110a_ffff +static const pciSubsystemInfo pci_ss_info_1131_7146_1131_4f56 = + {0x1131, 0x4f56, pci_subsys_1131_7146_1131_4f56, 0}; +#undef pci_ss_info_1131_4f56 +#define pci_ss_info_1131_4f56 pci_ss_info_1131_7146_1131_4f56 +static const pciSubsystemInfo pci_ss_info_1131_7146_1131_4f60 = + {0x1131, 0x4f60, pci_subsys_1131_7146_1131_4f60, 0}; +#undef pci_ss_info_1131_4f60 +#define pci_ss_info_1131_4f60 pci_ss_info_1131_7146_1131_4f60 +static const pciSubsystemInfo pci_ss_info_1131_7146_1131_4f61 = + {0x1131, 0x4f61, pci_subsys_1131_7146_1131_4f61, 0}; +#undef pci_ss_info_1131_4f61 +#define pci_ss_info_1131_4f61 pci_ss_info_1131_7146_1131_4f61 +static const pciSubsystemInfo pci_ss_info_1131_7146_1131_5f61 = + {0x1131, 0x5f61, pci_subsys_1131_7146_1131_5f61, 0}; +#undef pci_ss_info_1131_5f61 +#define pci_ss_info_1131_5f61 pci_ss_info_1131_7146_1131_5f61 +static const pciSubsystemInfo pci_ss_info_1131_7146_114b_2003 = + {0x114b, 0x2003, pci_subsys_1131_7146_114b_2003, 0}; +#undef pci_ss_info_114b_2003 +#define pci_ss_info_114b_2003 pci_ss_info_1131_7146_114b_2003 +static const pciSubsystemInfo pci_ss_info_1131_7146_11bd_0006 = + {0x11bd, 0x0006, pci_subsys_1131_7146_11bd_0006, 0}; +#undef pci_ss_info_11bd_0006 +#define pci_ss_info_11bd_0006 pci_ss_info_1131_7146_11bd_0006 +static const pciSubsystemInfo pci_ss_info_1131_7146_11bd_000a = + {0x11bd, 0x000a, pci_subsys_1131_7146_11bd_000a, 0}; +#undef pci_ss_info_11bd_000a +#define pci_ss_info_11bd_000a pci_ss_info_1131_7146_11bd_000a +static const pciSubsystemInfo pci_ss_info_1131_7146_11bd_000f = + {0x11bd, 0x000f, pci_subsys_1131_7146_11bd_000f, 0}; +#undef pci_ss_info_11bd_000f +#define pci_ss_info_11bd_000f pci_ss_info_1131_7146_11bd_000f +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0000 = + {0x13c2, 0x0000, pci_subsys_1131_7146_13c2_0000, 0}; +#undef pci_ss_info_13c2_0000 +#define pci_ss_info_13c2_0000 pci_ss_info_1131_7146_13c2_0000 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0001 = + {0x13c2, 0x0001, pci_subsys_1131_7146_13c2_0001, 0}; +#undef pci_ss_info_13c2_0001 +#define pci_ss_info_13c2_0001 pci_ss_info_1131_7146_13c2_0001 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0002 = + {0x13c2, 0x0002, pci_subsys_1131_7146_13c2_0002, 0}; +#undef pci_ss_info_13c2_0002 +#define pci_ss_info_13c2_0002 pci_ss_info_1131_7146_13c2_0002 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0003 = + {0x13c2, 0x0003, pci_subsys_1131_7146_13c2_0003, 0}; +#undef pci_ss_info_13c2_0003 +#define pci_ss_info_13c2_0003 pci_ss_info_1131_7146_13c2_0003 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0004 = + {0x13c2, 0x0004, pci_subsys_1131_7146_13c2_0004, 0}; +#undef pci_ss_info_13c2_0004 +#define pci_ss_info_13c2_0004 pci_ss_info_1131_7146_13c2_0004 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0006 = + {0x13c2, 0x0006, pci_subsys_1131_7146_13c2_0006, 0}; +#undef pci_ss_info_13c2_0006 +#define pci_ss_info_13c2_0006 pci_ss_info_1131_7146_13c2_0006 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_0008 = + {0x13c2, 0x0008, pci_subsys_1131_7146_13c2_0008, 0}; +#undef pci_ss_info_13c2_0008 +#define pci_ss_info_13c2_0008 pci_ss_info_1131_7146_13c2_0008 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_000a = + {0x13c2, 0x000a, pci_subsys_1131_7146_13c2_000a, 0}; +#undef pci_ss_info_13c2_000a +#define pci_ss_info_13c2_000a pci_ss_info_1131_7146_13c2_000a +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1003 = + {0x13c2, 0x1003, pci_subsys_1131_7146_13c2_1003, 0}; +#undef pci_ss_info_13c2_1003 +#define pci_ss_info_13c2_1003 pci_ss_info_1131_7146_13c2_1003 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1004 = + {0x13c2, 0x1004, pci_subsys_1131_7146_13c2_1004, 0}; +#undef pci_ss_info_13c2_1004 +#define pci_ss_info_13c2_1004 pci_ss_info_1131_7146_13c2_1004 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1005 = + {0x13c2, 0x1005, pci_subsys_1131_7146_13c2_1005, 0}; +#undef pci_ss_info_13c2_1005 +#define pci_ss_info_13c2_1005 pci_ss_info_1131_7146_13c2_1005 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_100c = + {0x13c2, 0x100c, pci_subsys_1131_7146_13c2_100c, 0}; +#undef pci_ss_info_13c2_100c +#define pci_ss_info_13c2_100c pci_ss_info_1131_7146_13c2_100c +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_100f = + {0x13c2, 0x100f, pci_subsys_1131_7146_13c2_100f, 0}; +#undef pci_ss_info_13c2_100f +#define pci_ss_info_13c2_100f pci_ss_info_1131_7146_13c2_100f +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1011 = + {0x13c2, 0x1011, pci_subsys_1131_7146_13c2_1011, 0}; +#undef pci_ss_info_13c2_1011 +#define pci_ss_info_13c2_1011 pci_ss_info_1131_7146_13c2_1011 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1013 = + {0x13c2, 0x1013, pci_subsys_1131_7146_13c2_1013, 0}; +#undef pci_ss_info_13c2_1013 +#define pci_ss_info_13c2_1013 pci_ss_info_1131_7146_13c2_1013 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1016 = + {0x13c2, 0x1016, pci_subsys_1131_7146_13c2_1016, 0}; +#undef pci_ss_info_13c2_1016 +#define pci_ss_info_13c2_1016 pci_ss_info_1131_7146_13c2_1016 +static const pciSubsystemInfo pci_ss_info_1131_7146_13c2_1102 = + {0x13c2, 0x1102, pci_subsys_1131_7146_13c2_1102, 0}; +#undef pci_ss_info_13c2_1102 +#define pci_ss_info_13c2_1102 pci_ss_info_1131_7146_13c2_1102 +static const pciSubsystemInfo pci_ss_info_1131_7146_153b_1156 = + {0x153b, 0x1156, pci_subsys_1131_7146_153b_1156, 0}; +#undef pci_ss_info_153b_1156 +#define pci_ss_info_153b_1156 pci_ss_info_1131_7146_153b_1156 +static const pciSubsystemInfo pci_ss_info_1131_9730_1131_0000 = + {0x1131, 0x0000, pci_subsys_1131_9730_1131_0000, 0}; +#undef pci_ss_info_1131_0000 +#define pci_ss_info_1131_0000 pci_ss_info_1131_9730_1131_0000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1133_e010_110a_0021 = + {0x110a, 0x0021, pci_subsys_1133_e010_110a_0021, 0}; +#undef pci_ss_info_110a_0021 +#define pci_ss_info_110a_0021 pci_ss_info_1133_e010_110a_0021 +static const pciSubsystemInfo pci_ss_info_1133_e013_1133_1300 = + {0x1133, 0x1300, pci_subsys_1133_e013_1133_1300, 0}; +#undef pci_ss_info_1133_1300 +#define pci_ss_info_1133_1300 pci_ss_info_1133_e013_1133_1300 +static const pciSubsystemInfo pci_ss_info_1133_e013_1133_e013 = + {0x1133, 0xe013, pci_subsys_1133_e013_1133_e013, 0}; +#undef pci_ss_info_1133_e013 +#define pci_ss_info_1133_e013 pci_ss_info_1133_e013_1133_e013 +static const pciSubsystemInfo pci_ss_info_1133_e015_1133_e015 = + {0x1133, 0xe015, pci_subsys_1133_e015_1133_e015, 0}; +#undef pci_ss_info_1133_e015 +#define pci_ss_info_1133_e015 pci_ss_info_1133_e015_1133_e015 +static const pciSubsystemInfo pci_ss_info_1133_e017_1133_e017 = + {0x1133, 0xe017, pci_subsys_1133_e017_1133_e017, 0}; +#undef pci_ss_info_1133_e017 +#define pci_ss_info_1133_e017 pci_ss_info_1133_e017_1133_e017 +static const pciSubsystemInfo pci_ss_info_1133_e018_1133_1800 = + {0x1133, 0x1800, pci_subsys_1133_e018_1133_1800, 0}; +#undef pci_ss_info_1133_1800 +#define pci_ss_info_1133_1800 pci_ss_info_1133_e018_1133_1800 +static const pciSubsystemInfo pci_ss_info_1133_e018_1133_e018 = + {0x1133, 0xe018, pci_subsys_1133_e018_1133_e018, 0}; +#undef pci_ss_info_1133_e018 +#define pci_ss_info_1133_e018 pci_ss_info_1133_e018_1133_e018 +static const pciSubsystemInfo pci_ss_info_1133_e019_1133_e019 = + {0x1133, 0xe019, pci_subsys_1133_e019_1133_e019, 0}; +#undef pci_ss_info_1133_e019 +#define pci_ss_info_1133_e019 pci_ss_info_1133_e019_1133_e019 +static const pciSubsystemInfo pci_ss_info_1133_e01b_1133_e01b = + {0x1133, 0xe01b, pci_subsys_1133_e01b_1133_e01b, 0}; +#undef pci_ss_info_1133_e01b +#define pci_ss_info_1133_e01b pci_ss_info_1133_e01b_1133_e01b +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c01 = + {0x1133, 0x1c01, pci_subsys_1133_e01c_1133_1c01, 0}; +#undef pci_ss_info_1133_1c01 +#define pci_ss_info_1133_1c01 pci_ss_info_1133_e01c_1133_1c01 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c02 = + {0x1133, 0x1c02, pci_subsys_1133_e01c_1133_1c02, 0}; +#undef pci_ss_info_1133_1c02 +#define pci_ss_info_1133_1c02 pci_ss_info_1133_e01c_1133_1c02 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c03 = + {0x1133, 0x1c03, pci_subsys_1133_e01c_1133_1c03, 0}; +#undef pci_ss_info_1133_1c03 +#define pci_ss_info_1133_1c03 pci_ss_info_1133_e01c_1133_1c03 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c04 = + {0x1133, 0x1c04, pci_subsys_1133_e01c_1133_1c04, 0}; +#undef pci_ss_info_1133_1c04 +#define pci_ss_info_1133_1c04 pci_ss_info_1133_e01c_1133_1c04 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c05 = + {0x1133, 0x1c05, pci_subsys_1133_e01c_1133_1c05, 0}; +#undef pci_ss_info_1133_1c05 +#define pci_ss_info_1133_1c05 pci_ss_info_1133_e01c_1133_1c05 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c06 = + {0x1133, 0x1c06, pci_subsys_1133_e01c_1133_1c06, 0}; +#undef pci_ss_info_1133_1c06 +#define pci_ss_info_1133_1c06 pci_ss_info_1133_e01c_1133_1c06 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c07 = + {0x1133, 0x1c07, pci_subsys_1133_e01c_1133_1c07, 0}; +#undef pci_ss_info_1133_1c07 +#define pci_ss_info_1133_1c07 pci_ss_info_1133_e01c_1133_1c07 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c08 = + {0x1133, 0x1c08, pci_subsys_1133_e01c_1133_1c08, 0}; +#undef pci_ss_info_1133_1c08 +#define pci_ss_info_1133_1c08 pci_ss_info_1133_e01c_1133_1c08 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c09 = + {0x1133, 0x1c09, pci_subsys_1133_e01c_1133_1c09, 0}; +#undef pci_ss_info_1133_1c09 +#define pci_ss_info_1133_1c09 pci_ss_info_1133_e01c_1133_1c09 +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c0a = + {0x1133, 0x1c0a, pci_subsys_1133_e01c_1133_1c0a, 0}; +#undef pci_ss_info_1133_1c0a +#define pci_ss_info_1133_1c0a pci_ss_info_1133_e01c_1133_1c0a +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c0b = + {0x1133, 0x1c0b, pci_subsys_1133_e01c_1133_1c0b, 0}; +#undef pci_ss_info_1133_1c0b +#define pci_ss_info_1133_1c0b pci_ss_info_1133_e01c_1133_1c0b +static const pciSubsystemInfo pci_ss_info_1133_e01c_1133_1c0c = + {0x1133, 0x1c0c, pci_subsys_1133_e01c_1133_1c0c, 0}; +#undef pci_ss_info_1133_1c0c +#define pci_ss_info_1133_1c0c pci_ss_info_1133_e01c_1133_1c0c +static const pciSubsystemInfo pci_ss_info_1133_e024_1133_2400 = + {0x1133, 0x2400, pci_subsys_1133_e024_1133_2400, 0}; +#undef pci_ss_info_1133_2400 +#define pci_ss_info_1133_2400 pci_ss_info_1133_e024_1133_2400 +static const pciSubsystemInfo pci_ss_info_1133_e024_1133_e024 = + {0x1133, 0xe024, pci_subsys_1133_e024_1133_e024, 0}; +#undef pci_ss_info_1133_e024 +#define pci_ss_info_1133_e024 pci_ss_info_1133_e024_1133_e024 +static const pciSubsystemInfo pci_ss_info_1133_e028_1133_2800 = + {0x1133, 0x2800, pci_subsys_1133_e028_1133_2800, 0}; +#undef pci_ss_info_1133_2800 +#define pci_ss_info_1133_2800 pci_ss_info_1133_e028_1133_2800 +static const pciSubsystemInfo pci_ss_info_1133_e028_1133_e028 = + {0x1133, 0xe028, pci_subsys_1133_e028_1133_e028, 0}; +#undef pci_ss_info_1133_e028 +#define pci_ss_info_1133_e028 pci_ss_info_1133_e028_1133_e028 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03b = + {0x0e11, 0xb03b, pci_subsys_1148_4000_0e11_b03b, 0}; +#undef pci_ss_info_0e11_b03b +#define pci_ss_info_0e11_b03b pci_ss_info_1148_4000_0e11_b03b +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03c = + {0x0e11, 0xb03c, pci_subsys_1148_4000_0e11_b03c, 0}; +#undef pci_ss_info_0e11_b03c +#define pci_ss_info_0e11_b03c pci_ss_info_1148_4000_0e11_b03c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03d = + {0x0e11, 0xb03d, pci_subsys_1148_4000_0e11_b03d, 0}; +#undef pci_ss_info_0e11_b03d +#define pci_ss_info_0e11_b03d pci_ss_info_1148_4000_0e11_b03d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03e = + {0x0e11, 0xb03e, pci_subsys_1148_4000_0e11_b03e, 0}; +#undef pci_ss_info_0e11_b03e +#define pci_ss_info_0e11_b03e pci_ss_info_1148_4000_0e11_b03e +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1148_4000_0e11_b03f = + {0x0e11, 0xb03f, pci_subsys_1148_4000_0e11_b03f, 0}; +#undef pci_ss_info_0e11_b03f +#define pci_ss_info_0e11_b03f pci_ss_info_1148_4000_0e11_b03f +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5521 = + {0x1148, 0x5521, pci_subsys_1148_4000_1148_5521, 0}; +#undef pci_ss_info_1148_5521 +#define pci_ss_info_1148_5521 pci_ss_info_1148_4000_1148_5521 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5522 = + {0x1148, 0x5522, pci_subsys_1148_4000_1148_5522, 0}; +#undef pci_ss_info_1148_5522 +#define pci_ss_info_1148_5522 pci_ss_info_1148_4000_1148_5522 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5541 = + {0x1148, 0x5541, pci_subsys_1148_4000_1148_5541, 0}; +#undef pci_ss_info_1148_5541 +#define pci_ss_info_1148_5541 pci_ss_info_1148_4000_1148_5541 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5543 = + {0x1148, 0x5543, pci_subsys_1148_4000_1148_5543, 0}; +#undef pci_ss_info_1148_5543 +#define pci_ss_info_1148_5543 pci_ss_info_1148_4000_1148_5543 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5544 = + {0x1148, 0x5544, pci_subsys_1148_4000_1148_5544, 0}; +#undef pci_ss_info_1148_5544 +#define pci_ss_info_1148_5544 pci_ss_info_1148_4000_1148_5544 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5821 = + {0x1148, 0x5821, pci_subsys_1148_4000_1148_5821, 0}; +#undef pci_ss_info_1148_5821 +#define pci_ss_info_1148_5821 pci_ss_info_1148_4000_1148_5821 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5822 = + {0x1148, 0x5822, pci_subsys_1148_4000_1148_5822, 0}; +#undef pci_ss_info_1148_5822 +#define pci_ss_info_1148_5822 pci_ss_info_1148_4000_1148_5822 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5841 = + {0x1148, 0x5841, pci_subsys_1148_4000_1148_5841, 0}; +#undef pci_ss_info_1148_5841 +#define pci_ss_info_1148_5841 pci_ss_info_1148_4000_1148_5841 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5843 = + {0x1148, 0x5843, pci_subsys_1148_4000_1148_5843, 0}; +#undef pci_ss_info_1148_5843 +#define pci_ss_info_1148_5843 pci_ss_info_1148_4000_1148_5843 +static const pciSubsystemInfo pci_ss_info_1148_4000_1148_5844 = + {0x1148, 0x5844, pci_subsys_1148_4000_1148_5844, 0}; +#undef pci_ss_info_1148_5844 +#define pci_ss_info_1148_5844 pci_ss_info_1148_4000_1148_5844 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9821 = + {0x1148, 0x9821, pci_subsys_1148_4300_1148_9821, 0}; +#undef pci_ss_info_1148_9821 +#define pci_ss_info_1148_9821 pci_ss_info_1148_4300_1148_9821 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9822 = + {0x1148, 0x9822, pci_subsys_1148_4300_1148_9822, 0}; +#undef pci_ss_info_1148_9822 +#define pci_ss_info_1148_9822 pci_ss_info_1148_4300_1148_9822 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9841 = + {0x1148, 0x9841, pci_subsys_1148_4300_1148_9841, 0}; +#undef pci_ss_info_1148_9841 +#define pci_ss_info_1148_9841 pci_ss_info_1148_4300_1148_9841 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9842 = + {0x1148, 0x9842, pci_subsys_1148_4300_1148_9842, 0}; +#undef pci_ss_info_1148_9842 +#define pci_ss_info_1148_9842 pci_ss_info_1148_4300_1148_9842 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9843 = + {0x1148, 0x9843, pci_subsys_1148_4300_1148_9843, 0}; +#undef pci_ss_info_1148_9843 +#define pci_ss_info_1148_9843 pci_ss_info_1148_4300_1148_9843 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9844 = + {0x1148, 0x9844, pci_subsys_1148_4300_1148_9844, 0}; +#undef pci_ss_info_1148_9844 +#define pci_ss_info_1148_9844 pci_ss_info_1148_4300_1148_9844 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9861 = + {0x1148, 0x9861, pci_subsys_1148_4300_1148_9861, 0}; +#undef pci_ss_info_1148_9861 +#define pci_ss_info_1148_9861 pci_ss_info_1148_4300_1148_9861 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9862 = + {0x1148, 0x9862, pci_subsys_1148_4300_1148_9862, 0}; +#undef pci_ss_info_1148_9862 +#define pci_ss_info_1148_9862 pci_ss_info_1148_4300_1148_9862 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9871 = + {0x1148, 0x9871, pci_subsys_1148_4300_1148_9871, 0}; +#undef pci_ss_info_1148_9871 +#define pci_ss_info_1148_9871 pci_ss_info_1148_4300_1148_9871 +static const pciSubsystemInfo pci_ss_info_1148_4300_1148_9872 = + {0x1148, 0x9872, pci_subsys_1148_4300_1148_9872, 0}; +#undef pci_ss_info_1148_9872 +#define pci_ss_info_1148_9872 pci_ss_info_1148_4300_1148_9872 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2970 = + {0x1259, 0x2970, pci_subsys_1148_4300_1259_2970, 0}; +#undef pci_ss_info_1259_2970 +#define pci_ss_info_1259_2970 pci_ss_info_1148_4300_1259_2970 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2971 = + {0x1259, 0x2971, pci_subsys_1148_4300_1259_2971, 0}; +#undef pci_ss_info_1259_2971 +#define pci_ss_info_1259_2971 pci_ss_info_1148_4300_1259_2971 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2972 = + {0x1259, 0x2972, pci_subsys_1148_4300_1259_2972, 0}; +#undef pci_ss_info_1259_2972 +#define pci_ss_info_1259_2972 pci_ss_info_1148_4300_1259_2972 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2973 = + {0x1259, 0x2973, pci_subsys_1148_4300_1259_2973, 0}; +#undef pci_ss_info_1259_2973 +#define pci_ss_info_1259_2973 pci_ss_info_1148_4300_1259_2973 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2974 = + {0x1259, 0x2974, pci_subsys_1148_4300_1259_2974, 0}; +#undef pci_ss_info_1259_2974 +#define pci_ss_info_1259_2974 pci_ss_info_1148_4300_1259_2974 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2975 = + {0x1259, 0x2975, pci_subsys_1148_4300_1259_2975, 0}; +#undef pci_ss_info_1259_2975 +#define pci_ss_info_1259_2975 pci_ss_info_1148_4300_1259_2975 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2976 = + {0x1259, 0x2976, pci_subsys_1148_4300_1259_2976, 0}; +#undef pci_ss_info_1259_2976 +#define pci_ss_info_1259_2976 pci_ss_info_1148_4300_1259_2976 +static const pciSubsystemInfo pci_ss_info_1148_4300_1259_2977 = + {0x1259, 0x2977, pci_subsys_1148_4300_1259_2977, 0}; +#undef pci_ss_info_1259_2977 +#define pci_ss_info_1259_2977 pci_ss_info_1148_4300_1259_2977 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0121 = + {0x1148, 0x0121, pci_subsys_1148_4320_1148_0121, 0}; +#undef pci_ss_info_1148_0121 +#define pci_ss_info_1148_0121 pci_ss_info_1148_4320_1148_0121 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0221 = + {0x1148, 0x0221, pci_subsys_1148_4320_1148_0221, 0}; +#undef pci_ss_info_1148_0221 +#define pci_ss_info_1148_0221 pci_ss_info_1148_4320_1148_0221 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0321 = + {0x1148, 0x0321, pci_subsys_1148_4320_1148_0321, 0}; +#undef pci_ss_info_1148_0321 +#define pci_ss_info_1148_0321 pci_ss_info_1148_4320_1148_0321 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0421 = + {0x1148, 0x0421, pci_subsys_1148_4320_1148_0421, 0}; +#undef pci_ss_info_1148_0421 +#define pci_ss_info_1148_0421 pci_ss_info_1148_4320_1148_0421 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0621 = + {0x1148, 0x0621, pci_subsys_1148_4320_1148_0621, 0}; +#undef pci_ss_info_1148_0621 +#define pci_ss_info_1148_0621 pci_ss_info_1148_4320_1148_0621 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0721 = + {0x1148, 0x0721, pci_subsys_1148_4320_1148_0721, 0}; +#undef pci_ss_info_1148_0721 +#define pci_ss_info_1148_0721 pci_ss_info_1148_4320_1148_0721 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0821 = + {0x1148, 0x0821, pci_subsys_1148_4320_1148_0821, 0}; +#undef pci_ss_info_1148_0821 +#define pci_ss_info_1148_0821 pci_ss_info_1148_4320_1148_0821 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_0921 = + {0x1148, 0x0921, pci_subsys_1148_4320_1148_0921, 0}; +#undef pci_ss_info_1148_0921 +#define pci_ss_info_1148_0921 pci_ss_info_1148_4320_1148_0921 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_1121 = + {0x1148, 0x1121, pci_subsys_1148_4320_1148_1121, 0}; +#undef pci_ss_info_1148_1121 +#define pci_ss_info_1148_1121 pci_ss_info_1148_4320_1148_1121 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_1221 = + {0x1148, 0x1221, pci_subsys_1148_4320_1148_1221, 0}; +#undef pci_ss_info_1148_1221 +#define pci_ss_info_1148_1221 pci_ss_info_1148_4320_1148_1221 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_3221 = + {0x1148, 0x3221, pci_subsys_1148_4320_1148_3221, 0}; +#undef pci_ss_info_1148_3221 +#define pci_ss_info_1148_3221 pci_ss_info_1148_4320_1148_3221 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5021 = + {0x1148, 0x5021, pci_subsys_1148_4320_1148_5021, 0}; +#undef pci_ss_info_1148_5021 +#define pci_ss_info_1148_5021 pci_ss_info_1148_4320_1148_5021 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5041 = + {0x1148, 0x5041, pci_subsys_1148_4320_1148_5041, 0}; +#undef pci_ss_info_1148_5041 +#define pci_ss_info_1148_5041 pci_ss_info_1148_4320_1148_5041 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5043 = + {0x1148, 0x5043, pci_subsys_1148_4320_1148_5043, 0}; +#undef pci_ss_info_1148_5043 +#define pci_ss_info_1148_5043 pci_ss_info_1148_4320_1148_5043 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5051 = + {0x1148, 0x5051, pci_subsys_1148_4320_1148_5051, 0}; +#undef pci_ss_info_1148_5051 +#define pci_ss_info_1148_5051 pci_ss_info_1148_4320_1148_5051 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5061 = + {0x1148, 0x5061, pci_subsys_1148_4320_1148_5061, 0}; +#undef pci_ss_info_1148_5061 +#define pci_ss_info_1148_5061 pci_ss_info_1148_4320_1148_5061 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_5071 = + {0x1148, 0x5071, pci_subsys_1148_4320_1148_5071, 0}; +#undef pci_ss_info_1148_5071 +#define pci_ss_info_1148_5071 pci_ss_info_1148_4320_1148_5071 +static const pciSubsystemInfo pci_ss_info_1148_4320_1148_9521 = + {0x1148, 0x9521, pci_subsys_1148_4320_1148_9521, 0}; +#undef pci_ss_info_1148_9521 +#define pci_ss_info_1148_9521 pci_ss_info_1148_4320_1148_9521 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_2100 = + {0x1148, 0x2100, pci_subsys_1148_9e00_1148_2100, 0}; +#undef pci_ss_info_1148_2100 +#define pci_ss_info_1148_2100 pci_ss_info_1148_9e00_1148_2100 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_21d0 = + {0x1148, 0x21d0, pci_subsys_1148_9e00_1148_21d0, 0}; +#undef pci_ss_info_1148_21d0 +#define pci_ss_info_1148_21d0 pci_ss_info_1148_9e00_1148_21d0 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_2200 = + {0x1148, 0x2200, pci_subsys_1148_9e00_1148_2200, 0}; +#undef pci_ss_info_1148_2200 +#define pci_ss_info_1148_2200 pci_ss_info_1148_9e00_1148_2200 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_8100 = + {0x1148, 0x8100, pci_subsys_1148_9e00_1148_8100, 0}; +#undef pci_ss_info_1148_8100 +#define pci_ss_info_1148_8100 pci_ss_info_1148_9e00_1148_8100 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_8200 = + {0x1148, 0x8200, pci_subsys_1148_9e00_1148_8200, 0}; +#undef pci_ss_info_1148_8200 +#define pci_ss_info_1148_8200 pci_ss_info_1148_9e00_1148_8200 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_9100 = + {0x1148, 0x9100, pci_subsys_1148_9e00_1148_9100, 0}; +#undef pci_ss_info_1148_9100 +#define pci_ss_info_1148_9100 pci_ss_info_1148_9e00_1148_9100 +static const pciSubsystemInfo pci_ss_info_1148_9e00_1148_9200 = + {0x1148, 0x9200, pci_subsys_1148_9e00_1148_9200, 0}; +#undef pci_ss_info_1148_9200 +#define pci_ss_info_1148_9200 pci_ss_info_1148_9e00_1148_9200 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_114f_001d_114f_0050 = + {0x114f, 0x0050, pci_subsys_114f_001d_114f_0050, 0}; +#undef pci_ss_info_114f_0050 +#define pci_ss_info_114f_0050 pci_ss_info_114f_001d_114f_0050 +static const pciSubsystemInfo pci_ss_info_114f_001d_114f_0051 = + {0x114f, 0x0051, pci_subsys_114f_001d_114f_0051, 0}; +#undef pci_ss_info_114f_0051 +#define pci_ss_info_114f_0051 pci_ss_info_114f_001d_114f_0051 +static const pciSubsystemInfo pci_ss_info_114f_001d_114f_0052 = + {0x114f, 0x0052, pci_subsys_114f_001d_114f_0052, 0}; +#undef pci_ss_info_114f_0052 +#define pci_ss_info_114f_0052 pci_ss_info_114f_001d_114f_0052 +static const pciSubsystemInfo pci_ss_info_114f_001d_114f_0053 = + {0x114f, 0x0053, pci_subsys_114f_001d_114f_0053, 0}; +#undef pci_ss_info_114f_0053 +#define pci_ss_info_114f_0053 pci_ss_info_114f_001d_114f_0053 +static const pciSubsystemInfo pci_ss_info_114f_0024_114f_0030 = + {0x114f, 0x0030, pci_subsys_114f_0024_114f_0030, 0}; +#undef pci_ss_info_114f_0030 +#define pci_ss_info_114f_0030 pci_ss_info_114f_0024_114f_0030 +static const pciSubsystemInfo pci_ss_info_114f_0024_114f_0031 = + {0x114f, 0x0031, pci_subsys_114f_0024_114f_0031, 0}; +#undef pci_ss_info_114f_0031 +#define pci_ss_info_114f_0031 pci_ss_info_114f_0024_114f_0031 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_115d_0003_1014_0181 = + {0x1014, 0x0181, pci_subsys_115d_0003_1014_0181, 0}; +#undef pci_ss_info_1014_0181 +#define pci_ss_info_1014_0181 pci_ss_info_115d_0003_1014_0181 +static const pciSubsystemInfo pci_ss_info_115d_0003_1014_1181 = + {0x1014, 0x1181, pci_subsys_115d_0003_1014_1181, 0}; +#undef pci_ss_info_1014_1181 +#define pci_ss_info_1014_1181 pci_ss_info_115d_0003_1014_1181 +static const pciSubsystemInfo pci_ss_info_115d_0003_1014_8181 = + {0x1014, 0x8181, pci_subsys_115d_0003_1014_8181, 0}; +#undef pci_ss_info_1014_8181 +#define pci_ss_info_1014_8181 pci_ss_info_115d_0003_1014_8181 +static const pciSubsystemInfo pci_ss_info_115d_0003_1014_9181 = + {0x1014, 0x9181, pci_subsys_115d_0003_1014_9181, 0}; +#undef pci_ss_info_1014_9181 +#define pci_ss_info_1014_9181 pci_ss_info_115d_0003_1014_9181 +static const pciSubsystemInfo pci_ss_info_115d_0003_115d_0181 = + {0x115d, 0x0181, pci_subsys_115d_0003_115d_0181, 0}; +#undef pci_ss_info_115d_0181 +#define pci_ss_info_115d_0181 pci_ss_info_115d_0003_115d_0181 +static const pciSubsystemInfo pci_ss_info_115d_0003_115d_0182 = + {0x115d, 0x0182, pci_subsys_115d_0003_115d_0182, 0}; +#undef pci_ss_info_115d_0182 +#define pci_ss_info_115d_0182 pci_ss_info_115d_0003_115d_0182 +static const pciSubsystemInfo pci_ss_info_115d_0003_115d_1181 = + {0x115d, 0x1181, pci_subsys_115d_0003_115d_1181, 0}; +#undef pci_ss_info_115d_1181 +#define pci_ss_info_115d_1181 pci_ss_info_115d_0003_115d_1181 +static const pciSubsystemInfo pci_ss_info_115d_0003_1179_0181 = + {0x1179, 0x0181, pci_subsys_115d_0003_1179_0181, 0}; +#undef pci_ss_info_1179_0181 +#define pci_ss_info_1179_0181 pci_ss_info_115d_0003_1179_0181 +#endif +static const pciSubsystemInfo pci_ss_info_115d_0003_8086_8181 = + {0x8086, 0x8181, pci_subsys_115d_0003_8086_8181, 0}; +#undef pci_ss_info_8086_8181 +#define pci_ss_info_8086_8181 pci_ss_info_115d_0003_8086_8181 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_115d_0003_8086_9181 = + {0x8086, 0x9181, pci_subsys_115d_0003_8086_9181, 0}; +#undef pci_ss_info_8086_9181 +#define pci_ss_info_8086_9181 pci_ss_info_115d_0003_8086_9181 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_115d_0005_1014_0182 = + {0x1014, 0x0182, pci_subsys_115d_0005_1014_0182, 0}; +#undef pci_ss_info_1014_0182 +#define pci_ss_info_1014_0182 pci_ss_info_115d_0005_1014_0182 +static const pciSubsystemInfo pci_ss_info_115d_0005_1014_1182 = + {0x1014, 0x1182, pci_subsys_115d_0005_1014_1182, 0}; +#undef pci_ss_info_1014_1182 +#define pci_ss_info_1014_1182 pci_ss_info_115d_0005_1014_1182 +static const pciSubsystemInfo pci_ss_info_115d_0005_115d_0182 = + {0x115d, 0x0182, pci_subsys_115d_0005_115d_0182, 0}; +#undef pci_ss_info_115d_0182 +#define pci_ss_info_115d_0182 pci_ss_info_115d_0005_115d_0182 +static const pciSubsystemInfo pci_ss_info_115d_0005_115d_1182 = + {0x115d, 0x1182, pci_subsys_115d_0005_115d_1182, 0}; +#undef pci_ss_info_115d_1182 +#define pci_ss_info_115d_1182 pci_ss_info_115d_0005_115d_1182 +static const pciSubsystemInfo pci_ss_info_115d_0007_1014_0182 = + {0x1014, 0x0182, pci_subsys_115d_0007_1014_0182, 0}; +#undef pci_ss_info_1014_0182 +#define pci_ss_info_1014_0182 pci_ss_info_115d_0007_1014_0182 +static const pciSubsystemInfo pci_ss_info_115d_0007_1014_1182 = + {0x1014, 0x1182, pci_subsys_115d_0007_1014_1182, 0}; +#undef pci_ss_info_1014_1182 +#define pci_ss_info_1014_1182 pci_ss_info_115d_0007_1014_1182 +static const pciSubsystemInfo pci_ss_info_115d_0007_115d_0182 = + {0x115d, 0x0182, pci_subsys_115d_0007_115d_0182, 0}; +#undef pci_ss_info_115d_0182 +#define pci_ss_info_115d_0182 pci_ss_info_115d_0007_115d_0182 +static const pciSubsystemInfo pci_ss_info_115d_0007_115d_1182 = + {0x115d, 0x1182, pci_subsys_115d_0007_115d_1182, 0}; +#undef pci_ss_info_115d_1182 +#define pci_ss_info_115d_1182 pci_ss_info_115d_0007_115d_1182 +static const pciSubsystemInfo pci_ss_info_115d_000b_1014_0183 = + {0x1014, 0x0183, pci_subsys_115d_000b_1014_0183, 0}; +#undef pci_ss_info_1014_0183 +#define pci_ss_info_1014_0183 pci_ss_info_115d_000b_1014_0183 +static const pciSubsystemInfo pci_ss_info_115d_000b_115d_0183 = + {0x115d, 0x0183, pci_subsys_115d_000b_115d_0183, 0}; +#undef pci_ss_info_115d_0183 +#define pci_ss_info_115d_0183 pci_ss_info_115d_000b_115d_0183 +static const pciSubsystemInfo pci_ss_info_115d_000f_1014_0183 = + {0x1014, 0x0183, pci_subsys_115d_000f_1014_0183, 0}; +#undef pci_ss_info_1014_0183 +#define pci_ss_info_1014_0183 pci_ss_info_115d_000f_1014_0183 +static const pciSubsystemInfo pci_ss_info_115d_000f_115d_0183 = + {0x115d, 0x0183, pci_subsys_115d_000f_115d_0183, 0}; +#undef pci_ss_info_115d_0183 +#define pci_ss_info_115d_0183 pci_ss_info_115d_000f_115d_0183 +static const pciSubsystemInfo pci_ss_info_115d_0101_115d_1081 = + {0x115d, 0x1081, pci_subsys_115d_0101_115d_1081, 0}; +#undef pci_ss_info_115d_1081 +#define pci_ss_info_115d_1081 pci_ss_info_115d_0101_115d_1081 +static const pciSubsystemInfo pci_ss_info_115d_0103_1014_9181 = + {0x1014, 0x9181, pci_subsys_115d_0103_1014_9181, 0}; +#undef pci_ss_info_1014_9181 +#define pci_ss_info_1014_9181 pci_ss_info_115d_0103_1014_9181 +static const pciSubsystemInfo pci_ss_info_115d_0103_1115_1181 = + {0x1115, 0x1181, pci_subsys_115d_0103_1115_1181, 0}; +#undef pci_ss_info_1115_1181 +#define pci_ss_info_1115_1181 pci_ss_info_115d_0103_1115_1181 +static const pciSubsystemInfo pci_ss_info_115d_0103_115d_1181 = + {0x115d, 0x1181, pci_subsys_115d_0103_115d_1181, 0}; +#undef pci_ss_info_115d_1181 +#define pci_ss_info_115d_1181 pci_ss_info_115d_0103_115d_1181 +#endif +static const pciSubsystemInfo pci_ss_info_115d_0103_8086_9181 = + {0x8086, 0x9181, pci_subsys_115d_0103_8086_9181, 0}; +#undef pci_ss_info_8086_9181 +#define pci_ss_info_8086_9181 pci_ss_info_115d_0103_8086_9181 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1163_2000_1092_2000 = + {0x1092, 0x2000, pci_subsys_1163_2000_1092_2000, 0}; +#undef pci_ss_info_1092_2000 +#define pci_ss_info_1092_2000 pci_ss_info_1163_2000_1092_2000 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1166_0132_1166_0132 = + {0x1166, 0x0132, pci_subsys_1166_0132_1166_0132, 0}; +#undef pci_ss_info_1166_0132 +#define pci_ss_info_1166_0132 pci_ss_info_1166_0132_1166_0132 +static const pciSubsystemInfo pci_ss_info_1166_0201_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_1166_0201_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_1166_0201_4c53_1080 +static const pciSubsystemInfo pci_ss_info_1166_0203_1734_1012 = + {0x1734, 0x1012, pci_subsys_1166_0203_1734_1012, 0}; +#undef pci_ss_info_1734_1012 +#define pci_ss_info_1734_1012 pci_ss_info_1166_0203_1734_1012 +static const pciSubsystemInfo pci_ss_info_1166_0212_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_1166_0212_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_1166_0212_4c53_1080 +#endif +static const pciSubsystemInfo pci_ss_info_1166_0213_1028_4134 = + {0x1028, 0x4134, pci_subsys_1166_0213_1028_4134, 0}; +#undef pci_ss_info_1028_4134 +#define pci_ss_info_1028_4134 pci_ss_info_1166_0213_1028_4134 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1166_0213_1028_c134 = + {0x1028, 0xc134, pci_subsys_1166_0213_1028_c134, 0}; +#undef pci_ss_info_1028_c134 +#define pci_ss_info_1028_c134 pci_ss_info_1166_0213_1028_c134 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1166_0213_1734_1012 = + {0x1734, 0x1012, pci_subsys_1166_0213_1734_1012, 0}; +#undef pci_ss_info_1734_1012 +#define pci_ss_info_1734_1012 pci_ss_info_1166_0213_1734_1012 +#endif +static const pciSubsystemInfo pci_ss_info_1166_0217_1028_4134 = + {0x1028, 0x4134, pci_subsys_1166_0217_1028_4134, 0}; +#undef pci_ss_info_1028_4134 +#define pci_ss_info_1028_4134 pci_ss_info_1166_0217_1028_4134 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1166_0220_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_1166_0220_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_1166_0220_4c53_1080 +static const pciSubsystemInfo pci_ss_info_1166_0221_1734_1012 = + {0x1734, 0x1012, pci_subsys_1166_0221_1734_1012, 0}; +#undef pci_ss_info_1734_1012 +#define pci_ss_info_1734_1012 pci_ss_info_1166_0221_1734_1012 +static const pciSubsystemInfo pci_ss_info_1166_0227_1734_1012 = + {0x1734, 0x1012, pci_subsys_1166_0227_1734_1012, 0}; +#undef pci_ss_info_1734_1012 +#define pci_ss_info_1734_1012 pci_ss_info_1166_0227_1734_1012 +static const pciSubsystemInfo pci_ss_info_1166_0230_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_1166_0230_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_1166_0230_4c53_1080 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1179_0601_1179_0001 = + {0x1179, 0x0001, pci_subsys_1179_0601_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1179_0601_1179_0001 +static const pciSubsystemInfo pci_ss_info_1179_060a_1179_0001 = + {0x1179, 0x0001, pci_subsys_1179_060a_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1179_060a_1179_0001 +static const pciSubsystemInfo pci_ss_info_1179_0d01_1179_0001 = + {0x1179, 0x0001, pci_subsys_1179_0d01_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1179_0d01_1179_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_117c_0030_117c_8013 = + {0x117c, 0x8013, pci_subsys_117c_0030_117c_8013, 0}; +#undef pci_ss_info_117c_8013 +#define pci_ss_info_117c_8013 pci_ss_info_117c_0030_117c_8013 +static const pciSubsystemInfo pci_ss_info_117c_0030_117c_8014 = + {0x117c, 0x8014, pci_subsys_117c_0030_117c_8014, 0}; +#undef pci_ss_info_117c_8014 +#define pci_ss_info_117c_8014 pci_ss_info_117c_0030_117c_8014 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1180_0475_144d_c006 = + {0x144d, 0xc006, pci_subsys_1180_0475_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_1180_0475_144d_c006 +static const pciSubsystemInfo pci_ss_info_1180_0476_1014_0185 = + {0x1014, 0x0185, pci_subsys_1180_0476_1014_0185, 0}; +#undef pci_ss_info_1014_0185 +#define pci_ss_info_1014_0185 pci_ss_info_1180_0476_1014_0185 +#endif +static const pciSubsystemInfo pci_ss_info_1180_0476_1028_0188 = + {0x1028, 0x0188, pci_subsys_1180_0476_1028_0188, 0}; +#undef pci_ss_info_1028_0188 +#define pci_ss_info_1028_0188 pci_ss_info_1180_0476_1028_0188 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1180_0476_1043_1967 = + {0x1043, 0x1967, pci_subsys_1180_0476_1043_1967, 0}; +#undef pci_ss_info_1043_1967 +#define pci_ss_info_1043_1967 pci_ss_info_1180_0476_1043_1967 +static const pciSubsystemInfo pci_ss_info_1180_0476_1043_1987 = + {0x1043, 0x1987, pci_subsys_1180_0476_1043_1987, 0}; +#undef pci_ss_info_1043_1987 +#define pci_ss_info_1043_1987 pci_ss_info_1180_0476_1043_1987 +#endif +static const pciSubsystemInfo pci_ss_info_1180_0476_104d_80df = + {0x104d, 0x80df, pci_subsys_1180_0476_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_1180_0476_104d_80df +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1180_0476_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_1180_0476_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_1180_0476_104d_80e7 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1180_0476_144d_c00c = + {0x144d, 0xc00c, pci_subsys_1180_0476_144d_c00c, 0}; +#undef pci_ss_info_144d_c00c +#define pci_ss_info_144d_c00c pci_ss_info_1180_0476_144d_c00c +static const pciSubsystemInfo pci_ss_info_1180_0476_14ef_0220 = + {0x14ef, 0x0220, pci_subsys_1180_0476_14ef_0220, 0}; +#undef pci_ss_info_14ef_0220 +#define pci_ss_info_14ef_0220 pci_ss_info_1180_0476_14ef_0220 +static const pciSubsystemInfo pci_ss_info_1180_0476_17aa_201c = + {0x17aa, 0x201c, pci_subsys_1180_0476_17aa_201c, 0}; +#undef pci_ss_info_17aa_201c +#define pci_ss_info_17aa_201c pci_ss_info_1180_0476_17aa_201c +static const pciSubsystemInfo pci_ss_info_1180_0478_1014_0184 = + {0x1014, 0x0184, pci_subsys_1180_0478_1014_0184, 0}; +#undef pci_ss_info_1014_0184 +#define pci_ss_info_1014_0184 pci_ss_info_1180_0478_1014_0184 +static const pciSubsystemInfo pci_ss_info_1180_0522_1014_01cf = + {0x1014, 0x01cf, pci_subsys_1180_0522_1014_01cf, 0}; +#undef pci_ss_info_1014_01cf +#define pci_ss_info_1014_01cf pci_ss_info_1180_0522_1014_01cf +static const pciSubsystemInfo pci_ss_info_1180_0522_1043_1967 = + {0x1043, 0x1967, pci_subsys_1180_0522_1043_1967, 0}; +#undef pci_ss_info_1043_1967 +#define pci_ss_info_1043_1967 pci_ss_info_1180_0522_1043_1967 +static const pciSubsystemInfo pci_ss_info_1180_0551_144d_c006 = + {0x144d, 0xc006, pci_subsys_1180_0551_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_1180_0551_144d_c006 +static const pciSubsystemInfo pci_ss_info_1180_0552_1014_0511 = + {0x1014, 0x0511, pci_subsys_1180_0552_1014_0511, 0}; +#undef pci_ss_info_1014_0511 +#define pci_ss_info_1014_0511 pci_ss_info_1180_0552_1014_0511 +#endif +static const pciSubsystemInfo pci_ss_info_1180_0552_1028_0188 = + {0x1028, 0x0188, pci_subsys_1180_0552_1028_0188, 0}; +#undef pci_ss_info_1028_0188 +#define pci_ss_info_1028_0188 pci_ss_info_1180_0552_1028_0188 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1180_0552_144d_c00c = + {0x144d, 0xc00c, pci_subsys_1180_0552_144d_c00c, 0}; +#undef pci_ss_info_144d_c00c +#define pci_ss_info_144d_c00c pci_ss_info_1180_0552_144d_c00c +static const pciSubsystemInfo pci_ss_info_1180_0552_17aa_201e = + {0x17aa, 0x201e, pci_subsys_1180_0552_17aa_201e, 0}; +#undef pci_ss_info_17aa_201e +#define pci_ss_info_17aa_201e pci_ss_info_1180_0552_17aa_201e +static const pciSubsystemInfo pci_ss_info_1180_0592_1043_1967 = + {0x1043, 0x1967, pci_subsys_1180_0592_1043_1967, 0}; +#undef pci_ss_info_1043_1967 +#define pci_ss_info_1043_1967 pci_ss_info_1180_0592_1043_1967 +static const pciSubsystemInfo pci_ss_info_1180_0592_144d_c018 = + {0x144d, 0xc018, pci_subsys_1180_0592_144d_c018, 0}; +#undef pci_ss_info_144d_c018 +#define pci_ss_info_144d_c018 pci_ss_info_1180_0592_144d_c018 +static const pciSubsystemInfo pci_ss_info_1180_0822_1014_0556 = + {0x1014, 0x0556, pci_subsys_1180_0822_1014_0556, 0}; +#undef pci_ss_info_1014_0556 +#define pci_ss_info_1014_0556 pci_ss_info_1180_0822_1014_0556 +static const pciSubsystemInfo pci_ss_info_1180_0822_1014_0598 = + {0x1014, 0x0598, pci_subsys_1180_0822_1014_0598, 0}; +#undef pci_ss_info_1014_0598 +#define pci_ss_info_1014_0598 pci_ss_info_1180_0822_1014_0598 +#endif +static const pciSubsystemInfo pci_ss_info_1180_0822_1028_0188 = + {0x1028, 0x0188, pci_subsys_1180_0822_1028_0188, 0}; +#undef pci_ss_info_1028_0188 +#define pci_ss_info_1028_0188 pci_ss_info_1180_0822_1028_0188 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1180_0822_1028_01a2 = + {0x1028, 0x01a2, pci_subsys_1180_0822_1028_01a2, 0}; +#undef pci_ss_info_1028_01a2 +#define pci_ss_info_1028_01a2 pci_ss_info_1180_0822_1028_01a2 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1180_0822_1043_1967 = + {0x1043, 0x1967, pci_subsys_1180_0822_1043_1967, 0}; +#undef pci_ss_info_1043_1967 +#define pci_ss_info_1043_1967 pci_ss_info_1180_0822_1043_1967 +static const pciSubsystemInfo pci_ss_info_1180_0822_144d_c018 = + {0x144d, 0xc018, pci_subsys_1180_0822_144d_c018, 0}; +#undef pci_ss_info_144d_c018 +#define pci_ss_info_144d_c018 pci_ss_info_1180_0822_144d_c018 +static const pciSubsystemInfo pci_ss_info_1180_0822_17aa_201d = + {0x17aa, 0x201d, pci_subsys_1180_0822_17aa_201d, 0}; +#undef pci_ss_info_17aa_201d +#define pci_ss_info_17aa_201d pci_ss_info_1180_0822_17aa_201d +static const pciSubsystemInfo pci_ss_info_1180_0852_1043_1967 = + {0x1043, 0x1967, pci_subsys_1180_0852_1043_1967, 0}; +#undef pci_ss_info_1043_1967 +#define pci_ss_info_1043_1967 pci_ss_info_1180_0852_1043_1967 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1186_1002_1186_1002 = + {0x1186, 0x1002, pci_subsys_1186_1002_1186_1002, 0}; +#undef pci_ss_info_1186_1002 +#define pci_ss_info_1186_1002 pci_ss_info_1186_1002_1186_1002 +static const pciSubsystemInfo pci_ss_info_1186_1002_1186_1012 = + {0x1186, 0x1012, pci_subsys_1186_1002_1186_1012, 0}; +#undef pci_ss_info_1186_1012 +#define pci_ss_info_1186_1012 pci_ss_info_1186_1002_1186_1012 +static const pciSubsystemInfo pci_ss_info_1186_1300_1186_1300 = + {0x1186, 0x1300, pci_subsys_1186_1300_1186_1300, 0}; +#undef pci_ss_info_1186_1300 +#define pci_ss_info_1186_1300 pci_ss_info_1186_1300_1186_1300 +static const pciSubsystemInfo pci_ss_info_1186_1300_1186_1301 = + {0x1186, 0x1301, pci_subsys_1186_1300_1186_1301, 0}; +#undef pci_ss_info_1186_1301 +#define pci_ss_info_1186_1301 pci_ss_info_1186_1300_1186_1301 +static const pciSubsystemInfo pci_ss_info_1186_1300_1186_1303 = + {0x1186, 0x1303, pci_subsys_1186_1300_1186_1303, 0}; +#undef pci_ss_info_1186_1303 +#define pci_ss_info_1186_1303 pci_ss_info_1186_1300_1186_1303 +static const pciSubsystemInfo pci_ss_info_1186_4c00_1186_4c00 = + {0x1186, 0x4c00, pci_subsys_1186_4c00_1186_4c00, 0}; +#undef pci_ss_info_1186_4c00 +#define pci_ss_info_1186_4c00 pci_ss_info_1186_4c00_1186_4c00 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11ab_1faa_1385_4e00 = + {0x1385, 0x4e00, pci_subsys_11ab_1faa_1385_4e00, 0}; +#undef pci_ss_info_1385_4e00 +#define pci_ss_info_1385_4e00 pci_ss_info_11ab_1faa_1385_4e00 +static const pciSubsystemInfo pci_ss_info_11ab_4320_1019_0f38 = + {0x1019, 0x0f38, pci_subsys_11ab_4320_1019_0f38, 0}; +#undef pci_ss_info_1019_0f38 +#define pci_ss_info_1019_0f38 pci_ss_info_11ab_4320_1019_0f38 +static const pciSubsystemInfo pci_ss_info_11ab_4320_1019_8001 = + {0x1019, 0x8001, pci_subsys_11ab_4320_1019_8001, 0}; +#undef pci_ss_info_1019_8001 +#define pci_ss_info_1019_8001 pci_ss_info_11ab_4320_1019_8001 +static const pciSubsystemInfo pci_ss_info_11ab_4320_1043_173c = + {0x1043, 0x173c, pci_subsys_11ab_4320_1043_173c, 0}; +#undef pci_ss_info_1043_173c +#define pci_ss_info_1043_173c pci_ss_info_11ab_4320_1043_173c +static const pciSubsystemInfo pci_ss_info_11ab_4320_1043_811a = + {0x1043, 0x811a, pci_subsys_11ab_4320_1043_811a, 0}; +#undef pci_ss_info_1043_811a +#define pci_ss_info_1043_811a pci_ss_info_11ab_4320_1043_811a +static const pciSubsystemInfo pci_ss_info_11ab_4320_105b_0c19 = + {0x105b, 0x0c19, pci_subsys_11ab_4320_105b_0c19, 0}; +#undef pci_ss_info_105b_0c19 +#define pci_ss_info_105b_0c19 pci_ss_info_11ab_4320_105b_0c19 +static const pciSubsystemInfo pci_ss_info_11ab_4320_10b8_b452 = + {0x10b8, 0xb452, pci_subsys_11ab_4320_10b8_b452, 0}; +#undef pci_ss_info_10b8_b452 +#define pci_ss_info_10b8_b452 pci_ss_info_11ab_4320_10b8_b452 +static const pciSubsystemInfo pci_ss_info_11ab_4320_11ab_0121 = + {0x11ab, 0x0121, pci_subsys_11ab_4320_11ab_0121, 0}; +#undef pci_ss_info_11ab_0121 +#define pci_ss_info_11ab_0121 pci_ss_info_11ab_4320_11ab_0121 +static const pciSubsystemInfo pci_ss_info_11ab_4320_11ab_0321 = + {0x11ab, 0x0321, pci_subsys_11ab_4320_11ab_0321, 0}; +#undef pci_ss_info_11ab_0321 +#define pci_ss_info_11ab_0321 pci_ss_info_11ab_4320_11ab_0321 +static const pciSubsystemInfo pci_ss_info_11ab_4320_11ab_1021 = + {0x11ab, 0x1021, pci_subsys_11ab_4320_11ab_1021, 0}; +#undef pci_ss_info_11ab_1021 +#define pci_ss_info_11ab_1021 pci_ss_info_11ab_4320_11ab_1021 +static const pciSubsystemInfo pci_ss_info_11ab_4320_11ab_4320 = + {0x11ab, 0x4320, pci_subsys_11ab_4320_11ab_4320, 0}; +#undef pci_ss_info_11ab_4320 +#define pci_ss_info_11ab_4320 pci_ss_info_11ab_4320_11ab_4320 +static const pciSubsystemInfo pci_ss_info_11ab_4320_11ab_5021 = + {0x11ab, 0x5021, pci_subsys_11ab_4320_11ab_5021, 0}; +#undef pci_ss_info_11ab_5021 +#define pci_ss_info_11ab_5021 pci_ss_info_11ab_4320_11ab_5021 +static const pciSubsystemInfo pci_ss_info_11ab_4320_11ab_9521 = + {0x11ab, 0x9521, pci_subsys_11ab_4320_11ab_9521, 0}; +#undef pci_ss_info_11ab_9521 +#define pci_ss_info_11ab_9521 pci_ss_info_11ab_4320_11ab_9521 +static const pciSubsystemInfo pci_ss_info_11ab_4320_1458_e000 = + {0x1458, 0xe000, pci_subsys_11ab_4320_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_11ab_4320_1458_e000 +static const pciSubsystemInfo pci_ss_info_11ab_4320_147b_1406 = + {0x147b, 0x1406, pci_subsys_11ab_4320_147b_1406, 0}; +#undef pci_ss_info_147b_1406 +#define pci_ss_info_147b_1406 pci_ss_info_11ab_4320_147b_1406 +static const pciSubsystemInfo pci_ss_info_11ab_4320_15d4_0047 = + {0x15d4, 0x0047, pci_subsys_11ab_4320_15d4_0047, 0}; +#undef pci_ss_info_15d4_0047 +#define pci_ss_info_15d4_0047 pci_ss_info_11ab_4320_15d4_0047 +static const pciSubsystemInfo pci_ss_info_11ab_4320_1695_9025 = + {0x1695, 0x9025, pci_subsys_11ab_4320_1695_9025, 0}; +#undef pci_ss_info_1695_9025 +#define pci_ss_info_1695_9025 pci_ss_info_11ab_4320_1695_9025 +static const pciSubsystemInfo pci_ss_info_11ab_4320_17f2_1c03 = + {0x17f2, 0x1c03, pci_subsys_11ab_4320_17f2_1c03, 0}; +#undef pci_ss_info_17f2_1c03 +#define pci_ss_info_17f2_1c03 pci_ss_info_11ab_4320_17f2_1c03 +static const pciSubsystemInfo pci_ss_info_11ab_4320_270f_2803 = + {0x270f, 0x2803, pci_subsys_11ab_4320_270f_2803, 0}; +#undef pci_ss_info_270f_2803 +#define pci_ss_info_270f_2803 pci_ss_info_11ab_4320_270f_2803 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1179_0001 = + {0x1179, 0x0001, pci_subsys_11ab_4350_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_11ab_4350_1179_0001 +static const pciSubsystemInfo pci_ss_info_11ab_4350_11ab_3521 = + {0x11ab, 0x3521, pci_subsys_11ab_4350_11ab_3521, 0}; +#undef pci_ss_info_11ab_3521 +#define pci_ss_info_11ab_3521 pci_ss_info_11ab_4350_11ab_3521 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_000d = + {0x1854, 0x000d, pci_subsys_11ab_4350_1854_000d, 0}; +#undef pci_ss_info_1854_000d +#define pci_ss_info_1854_000d pci_ss_info_11ab_4350_1854_000d +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_000e = + {0x1854, 0x000e, pci_subsys_11ab_4350_1854_000e, 0}; +#undef pci_ss_info_1854_000e +#define pci_ss_info_1854_000e pci_ss_info_11ab_4350_1854_000e +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_000f = + {0x1854, 0x000f, pci_subsys_11ab_4350_1854_000f, 0}; +#undef pci_ss_info_1854_000f +#define pci_ss_info_1854_000f pci_ss_info_11ab_4350_1854_000f +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0011 = + {0x1854, 0x0011, pci_subsys_11ab_4350_1854_0011, 0}; +#undef pci_ss_info_1854_0011 +#define pci_ss_info_1854_0011 pci_ss_info_11ab_4350_1854_0011 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0012 = + {0x1854, 0x0012, pci_subsys_11ab_4350_1854_0012, 0}; +#undef pci_ss_info_1854_0012 +#define pci_ss_info_1854_0012 pci_ss_info_11ab_4350_1854_0012 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0016 = + {0x1854, 0x0016, pci_subsys_11ab_4350_1854_0016, 0}; +#undef pci_ss_info_1854_0016 +#define pci_ss_info_1854_0016 pci_ss_info_11ab_4350_1854_0016 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0017 = + {0x1854, 0x0017, pci_subsys_11ab_4350_1854_0017, 0}; +#undef pci_ss_info_1854_0017 +#define pci_ss_info_1854_0017 pci_ss_info_11ab_4350_1854_0017 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0018 = + {0x1854, 0x0018, pci_subsys_11ab_4350_1854_0018, 0}; +#undef pci_ss_info_1854_0018 +#define pci_ss_info_1854_0018 pci_ss_info_11ab_4350_1854_0018 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0019 = + {0x1854, 0x0019, pci_subsys_11ab_4350_1854_0019, 0}; +#undef pci_ss_info_1854_0019 +#define pci_ss_info_1854_0019 pci_ss_info_11ab_4350_1854_0019 +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_001c = + {0x1854, 0x001c, pci_subsys_11ab_4350_1854_001c, 0}; +#undef pci_ss_info_1854_001c +#define pci_ss_info_1854_001c pci_ss_info_11ab_4350_1854_001c +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_001e = + {0x1854, 0x001e, pci_subsys_11ab_4350_1854_001e, 0}; +#undef pci_ss_info_1854_001e +#define pci_ss_info_1854_001e pci_ss_info_11ab_4350_1854_001e +static const pciSubsystemInfo pci_ss_info_11ab_4350_1854_0020 = + {0x1854, 0x0020, pci_subsys_11ab_4350_1854_0020, 0}; +#undef pci_ss_info_1854_0020 +#define pci_ss_info_1854_0020 pci_ss_info_11ab_4350_1854_0020 +static const pciSubsystemInfo pci_ss_info_11ab_4351_107b_4009 = + {0x107b, 0x4009, pci_subsys_11ab_4351_107b_4009, 0}; +#undef pci_ss_info_107b_4009 +#define pci_ss_info_107b_4009 pci_ss_info_11ab_4351_107b_4009 +static const pciSubsystemInfo pci_ss_info_11ab_4351_10f7_8338 = + {0x10f7, 0x8338, pci_subsys_11ab_4351_10f7_8338, 0}; +#undef pci_ss_info_10f7_8338 +#define pci_ss_info_10f7_8338 pci_ss_info_11ab_4351_10f7_8338 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1179_0001 = + {0x1179, 0x0001, pci_subsys_11ab_4351_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_11ab_4351_1179_0001 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1179_ff00 = + {0x1179, 0xff00, pci_subsys_11ab_4351_1179_ff00, 0}; +#undef pci_ss_info_1179_ff00 +#define pci_ss_info_1179_ff00 pci_ss_info_11ab_4351_1179_ff00 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1179_ff10 = + {0x1179, 0xff10, pci_subsys_11ab_4351_1179_ff10, 0}; +#undef pci_ss_info_1179_ff10 +#define pci_ss_info_1179_ff10 pci_ss_info_11ab_4351_1179_ff10 +static const pciSubsystemInfo pci_ss_info_11ab_4351_11ab_3621 = + {0x11ab, 0x3621, pci_subsys_11ab_4351_11ab_3621, 0}; +#undef pci_ss_info_11ab_3621 +#define pci_ss_info_11ab_3621 pci_ss_info_11ab_4351_11ab_3621 +static const pciSubsystemInfo pci_ss_info_11ab_4351_13d1_ac12 = + {0x13d1, 0xac12, pci_subsys_11ab_4351_13d1_ac12, 0}; +#undef pci_ss_info_13d1_ac12 +#define pci_ss_info_13d1_ac12 pci_ss_info_11ab_4351_13d1_ac12 +static const pciSubsystemInfo pci_ss_info_11ab_4351_161f_203d = + {0x161f, 0x203d, pci_subsys_11ab_4351_161f_203d, 0}; +#undef pci_ss_info_161f_203d +#define pci_ss_info_161f_203d pci_ss_info_11ab_4351_161f_203d +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_000d = + {0x1854, 0x000d, pci_subsys_11ab_4351_1854_000d, 0}; +#undef pci_ss_info_1854_000d +#define pci_ss_info_1854_000d pci_ss_info_11ab_4351_1854_000d +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_000e = + {0x1854, 0x000e, pci_subsys_11ab_4351_1854_000e, 0}; +#undef pci_ss_info_1854_000e +#define pci_ss_info_1854_000e pci_ss_info_11ab_4351_1854_000e +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_000f = + {0x1854, 0x000f, pci_subsys_11ab_4351_1854_000f, 0}; +#undef pci_ss_info_1854_000f +#define pci_ss_info_1854_000f pci_ss_info_11ab_4351_1854_000f +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0011 = + {0x1854, 0x0011, pci_subsys_11ab_4351_1854_0011, 0}; +#undef pci_ss_info_1854_0011 +#define pci_ss_info_1854_0011 pci_ss_info_11ab_4351_1854_0011 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0012 = + {0x1854, 0x0012, pci_subsys_11ab_4351_1854_0012, 0}; +#undef pci_ss_info_1854_0012 +#define pci_ss_info_1854_0012 pci_ss_info_11ab_4351_1854_0012 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0016 = + {0x1854, 0x0016, pci_subsys_11ab_4351_1854_0016, 0}; +#undef pci_ss_info_1854_0016 +#define pci_ss_info_1854_0016 pci_ss_info_11ab_4351_1854_0016 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0017 = + {0x1854, 0x0017, pci_subsys_11ab_4351_1854_0017, 0}; +#undef pci_ss_info_1854_0017 +#define pci_ss_info_1854_0017 pci_ss_info_11ab_4351_1854_0017 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0018 = + {0x1854, 0x0018, pci_subsys_11ab_4351_1854_0018, 0}; +#undef pci_ss_info_1854_0018 +#define pci_ss_info_1854_0018 pci_ss_info_11ab_4351_1854_0018 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0019 = + {0x1854, 0x0019, pci_subsys_11ab_4351_1854_0019, 0}; +#undef pci_ss_info_1854_0019 +#define pci_ss_info_1854_0019 pci_ss_info_11ab_4351_1854_0019 +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_001c = + {0x1854, 0x001c, pci_subsys_11ab_4351_1854_001c, 0}; +#undef pci_ss_info_1854_001c +#define pci_ss_info_1854_001c pci_ss_info_11ab_4351_1854_001c +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_001e = + {0x1854, 0x001e, pci_subsys_11ab_4351_1854_001e, 0}; +#undef pci_ss_info_1854_001e +#define pci_ss_info_1854_001e pci_ss_info_11ab_4351_1854_001e +static const pciSubsystemInfo pci_ss_info_11ab_4351_1854_0020 = + {0x1854, 0x0020, pci_subsys_11ab_4351_1854_0020, 0}; +#undef pci_ss_info_1854_0020 +#define pci_ss_info_1854_0020 pci_ss_info_11ab_4351_1854_0020 +static const pciSubsystemInfo pci_ss_info_11ab_4360_1043_8134 = + {0x1043, 0x8134, pci_subsys_11ab_4360_1043_8134, 0}; +#undef pci_ss_info_1043_8134 +#define pci_ss_info_1043_8134 pci_ss_info_11ab_4360_1043_8134 +static const pciSubsystemInfo pci_ss_info_11ab_4360_107b_4009 = + {0x107b, 0x4009, pci_subsys_11ab_4360_107b_4009, 0}; +#undef pci_ss_info_107b_4009 +#define pci_ss_info_107b_4009 pci_ss_info_11ab_4360_107b_4009 +static const pciSubsystemInfo pci_ss_info_11ab_4360_11ab_5221 = + {0x11ab, 0x5221, pci_subsys_11ab_4360_11ab_5221, 0}; +#undef pci_ss_info_11ab_5221 +#define pci_ss_info_11ab_5221 pci_ss_info_11ab_4360_11ab_5221 +static const pciSubsystemInfo pci_ss_info_11ab_4360_1458_e000 = + {0x1458, 0xe000, pci_subsys_11ab_4360_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_11ab_4360_1458_e000 +static const pciSubsystemInfo pci_ss_info_11ab_4360_1462_052c = + {0x1462, 0x052c, pci_subsys_11ab_4360_1462_052c, 0}; +#undef pci_ss_info_1462_052c +#define pci_ss_info_1462_052c pci_ss_info_11ab_4360_1462_052c +static const pciSubsystemInfo pci_ss_info_11ab_4360_1849_8052 = + {0x1849, 0x8052, pci_subsys_11ab_4360_1849_8052, 0}; +#undef pci_ss_info_1849_8052 +#define pci_ss_info_1849_8052 pci_ss_info_11ab_4360_1849_8052 +static const pciSubsystemInfo pci_ss_info_11ab_4360_a0a0_0509 = + {0xa0a0, 0x0509, pci_subsys_11ab_4360_a0a0_0509, 0}; +#undef pci_ss_info_a0a0_0509 +#define pci_ss_info_a0a0_0509 pci_ss_info_11ab_4360_a0a0_0509 +static const pciSubsystemInfo pci_ss_info_11ab_4361_107b_3015 = + {0x107b, 0x3015, pci_subsys_11ab_4361_107b_3015, 0}; +#undef pci_ss_info_107b_3015 +#define pci_ss_info_107b_3015 pci_ss_info_11ab_4361_107b_3015 +static const pciSubsystemInfo pci_ss_info_11ab_4361_11ab_5021 = + {0x11ab, 0x5021, pci_subsys_11ab_4361_11ab_5021, 0}; +#undef pci_ss_info_11ab_5021 +#define pci_ss_info_11ab_5021 pci_ss_info_11ab_4361_11ab_5021 +#endif +static const pciSubsystemInfo pci_ss_info_11ab_4361_8086_3063 = + {0x8086, 0x3063, pci_subsys_11ab_4361_8086_3063, 0}; +#undef pci_ss_info_8086_3063 +#define pci_ss_info_8086_3063 pci_ss_info_11ab_4361_8086_3063 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11ab_4361_8086_3439 = + {0x8086, 0x3439, pci_subsys_11ab_4361_8086_3439, 0}; +#undef pci_ss_info_8086_3439 +#define pci_ss_info_8086_3439 pci_ss_info_11ab_4361_8086_3439 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11ab_4362_103c_2a0d = + {0x103c, 0x2a0d, pci_subsys_11ab_4362_103c_2a0d, 0}; +#undef pci_ss_info_103c_2a0d +#define pci_ss_info_103c_2a0d pci_ss_info_11ab_4362_103c_2a0d +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11ab_4362_1043_8142 = + {0x1043, 0x8142, pci_subsys_11ab_4362_1043_8142, 0}; +#undef pci_ss_info_1043_8142 +#define pci_ss_info_1043_8142 pci_ss_info_11ab_4362_1043_8142 +static const pciSubsystemInfo pci_ss_info_11ab_4362_109f_3197 = + {0x109f, 0x3197, pci_subsys_11ab_4362_109f_3197, 0}; +#undef pci_ss_info_109f_3197 +#define pci_ss_info_109f_3197 pci_ss_info_11ab_4362_109f_3197 +static const pciSubsystemInfo pci_ss_info_11ab_4362_10f7_8338 = + {0x10f7, 0x8338, pci_subsys_11ab_4362_10f7_8338, 0}; +#undef pci_ss_info_10f7_8338 +#define pci_ss_info_10f7_8338 pci_ss_info_11ab_4362_10f7_8338 +static const pciSubsystemInfo pci_ss_info_11ab_4362_10fd_a430 = + {0x10fd, 0xa430, pci_subsys_11ab_4362_10fd_a430, 0}; +#undef pci_ss_info_10fd_a430 +#define pci_ss_info_10fd_a430 pci_ss_info_11ab_4362_10fd_a430 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1179_0001 = + {0x1179, 0x0001, pci_subsys_11ab_4362_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_11ab_4362_1179_0001 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1179_ff00 = + {0x1179, 0xff00, pci_subsys_11ab_4362_1179_ff00, 0}; +#undef pci_ss_info_1179_ff00 +#define pci_ss_info_1179_ff00 pci_ss_info_11ab_4362_1179_ff00 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1179_ff10 = + {0x1179, 0xff10, pci_subsys_11ab_4362_1179_ff10, 0}; +#undef pci_ss_info_1179_ff10 +#define pci_ss_info_1179_ff10 pci_ss_info_11ab_4362_1179_ff10 +static const pciSubsystemInfo pci_ss_info_11ab_4362_11ab_5321 = + {0x11ab, 0x5321, pci_subsys_11ab_4362_11ab_5321, 0}; +#undef pci_ss_info_11ab_5321 +#define pci_ss_info_11ab_5321 pci_ss_info_11ab_4362_11ab_5321 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1297_c240 = + {0x1297, 0xc240, pci_subsys_11ab_4362_1297_c240, 0}; +#undef pci_ss_info_1297_c240 +#define pci_ss_info_1297_c240 pci_ss_info_11ab_4362_1297_c240 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1297_c241 = + {0x1297, 0xc241, pci_subsys_11ab_4362_1297_c241, 0}; +#undef pci_ss_info_1297_c241 +#define pci_ss_info_1297_c241 pci_ss_info_11ab_4362_1297_c241 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1297_c242 = + {0x1297, 0xc242, pci_subsys_11ab_4362_1297_c242, 0}; +#undef pci_ss_info_1297_c242 +#define pci_ss_info_1297_c242 pci_ss_info_11ab_4362_1297_c242 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1297_c243 = + {0x1297, 0xc243, pci_subsys_11ab_4362_1297_c243, 0}; +#undef pci_ss_info_1297_c243 +#define pci_ss_info_1297_c243 pci_ss_info_11ab_4362_1297_c243 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1297_c244 = + {0x1297, 0xc244, pci_subsys_11ab_4362_1297_c244, 0}; +#undef pci_ss_info_1297_c244 +#define pci_ss_info_1297_c244 pci_ss_info_11ab_4362_1297_c244 +static const pciSubsystemInfo pci_ss_info_11ab_4362_13d1_ac11 = + {0x13d1, 0xac11, pci_subsys_11ab_4362_13d1_ac11, 0}; +#undef pci_ss_info_13d1_ac11 +#define pci_ss_info_13d1_ac11 pci_ss_info_11ab_4362_13d1_ac11 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1458_e000 = + {0x1458, 0xe000, pci_subsys_11ab_4362_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_11ab_4362_1458_e000 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1462_058c = + {0x1462, 0x058c, pci_subsys_11ab_4362_1462_058c, 0}; +#undef pci_ss_info_1462_058c +#define pci_ss_info_1462_058c pci_ss_info_11ab_4362_1462_058c +static const pciSubsystemInfo pci_ss_info_11ab_4362_14c0_0012 = + {0x14c0, 0x0012, pci_subsys_11ab_4362_14c0_0012, 0}; +#undef pci_ss_info_14c0_0012 +#define pci_ss_info_14c0_0012 pci_ss_info_11ab_4362_14c0_0012 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1558_04a0 = + {0x1558, 0x04a0, pci_subsys_11ab_4362_1558_04a0, 0}; +#undef pci_ss_info_1558_04a0 +#define pci_ss_info_1558_04a0 pci_ss_info_11ab_4362_1558_04a0 +static const pciSubsystemInfo pci_ss_info_11ab_4362_15bd_1003 = + {0x15bd, 0x1003, pci_subsys_11ab_4362_15bd_1003, 0}; +#undef pci_ss_info_15bd_1003 +#define pci_ss_info_15bd_1003 pci_ss_info_11ab_4362_15bd_1003 +static const pciSubsystemInfo pci_ss_info_11ab_4362_161f_203c = + {0x161f, 0x203c, pci_subsys_11ab_4362_161f_203c, 0}; +#undef pci_ss_info_161f_203c +#define pci_ss_info_161f_203c pci_ss_info_11ab_4362_161f_203c +static const pciSubsystemInfo pci_ss_info_11ab_4362_161f_203d = + {0x161f, 0x203d, pci_subsys_11ab_4362_161f_203d, 0}; +#undef pci_ss_info_161f_203d +#define pci_ss_info_161f_203d pci_ss_info_11ab_4362_161f_203d +static const pciSubsystemInfo pci_ss_info_11ab_4362_1695_9029 = + {0x1695, 0x9029, pci_subsys_11ab_4362_1695_9029, 0}; +#undef pci_ss_info_1695_9029 +#define pci_ss_info_1695_9029 pci_ss_info_11ab_4362_1695_9029 +static const pciSubsystemInfo pci_ss_info_11ab_4362_17f2_2c08 = + {0x17f2, 0x2c08, pci_subsys_11ab_4362_17f2_2c08, 0}; +#undef pci_ss_info_17f2_2c08 +#define pci_ss_info_17f2_2c08 pci_ss_info_11ab_4362_17f2_2c08 +static const pciSubsystemInfo pci_ss_info_11ab_4362_17ff_0585 = + {0x17ff, 0x0585, pci_subsys_11ab_4362_17ff_0585, 0}; +#undef pci_ss_info_17ff_0585 +#define pci_ss_info_17ff_0585 pci_ss_info_11ab_4362_17ff_0585 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1849_8053 = + {0x1849, 0x8053, pci_subsys_11ab_4362_1849_8053, 0}; +#undef pci_ss_info_1849_8053 +#define pci_ss_info_1849_8053 pci_ss_info_11ab_4362_1849_8053 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_000b = + {0x1854, 0x000b, pci_subsys_11ab_4362_1854_000b, 0}; +#undef pci_ss_info_1854_000b +#define pci_ss_info_1854_000b pci_ss_info_11ab_4362_1854_000b +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_000c = + {0x1854, 0x000c, pci_subsys_11ab_4362_1854_000c, 0}; +#undef pci_ss_info_1854_000c +#define pci_ss_info_1854_000c pci_ss_info_11ab_4362_1854_000c +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0010 = + {0x1854, 0x0010, pci_subsys_11ab_4362_1854_0010, 0}; +#undef pci_ss_info_1854_0010 +#define pci_ss_info_1854_0010 pci_ss_info_11ab_4362_1854_0010 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0013 = + {0x1854, 0x0013, pci_subsys_11ab_4362_1854_0013, 0}; +#undef pci_ss_info_1854_0013 +#define pci_ss_info_1854_0013 pci_ss_info_11ab_4362_1854_0013 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0014 = + {0x1854, 0x0014, pci_subsys_11ab_4362_1854_0014, 0}; +#undef pci_ss_info_1854_0014 +#define pci_ss_info_1854_0014 pci_ss_info_11ab_4362_1854_0014 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0015 = + {0x1854, 0x0015, pci_subsys_11ab_4362_1854_0015, 0}; +#undef pci_ss_info_1854_0015 +#define pci_ss_info_1854_0015 pci_ss_info_11ab_4362_1854_0015 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_001a = + {0x1854, 0x001a, pci_subsys_11ab_4362_1854_001a, 0}; +#undef pci_ss_info_1854_001a +#define pci_ss_info_1854_001a pci_ss_info_11ab_4362_1854_001a +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_001b = + {0x1854, 0x001b, pci_subsys_11ab_4362_1854_001b, 0}; +#undef pci_ss_info_1854_001b +#define pci_ss_info_1854_001b pci_ss_info_11ab_4362_1854_001b +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_001d = + {0x1854, 0x001d, pci_subsys_11ab_4362_1854_001d, 0}; +#undef pci_ss_info_1854_001d +#define pci_ss_info_1854_001d pci_ss_info_11ab_4362_1854_001d +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_001f = + {0x1854, 0x001f, pci_subsys_11ab_4362_1854_001f, 0}; +#undef pci_ss_info_1854_001f +#define pci_ss_info_1854_001f pci_ss_info_11ab_4362_1854_001f +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0021 = + {0x1854, 0x0021, pci_subsys_11ab_4362_1854_0021, 0}; +#undef pci_ss_info_1854_0021 +#define pci_ss_info_1854_0021 pci_ss_info_11ab_4362_1854_0021 +static const pciSubsystemInfo pci_ss_info_11ab_4362_1854_0022 = + {0x1854, 0x0022, pci_subsys_11ab_4362_1854_0022, 0}; +#undef pci_ss_info_1854_0022 +#define pci_ss_info_1854_0022 pci_ss_info_11ab_4362_1854_0022 +static const pciSubsystemInfo pci_ss_info_11ab_4362_270f_2801 = + {0x270f, 0x2801, pci_subsys_11ab_4362_270f_2801, 0}; +#undef pci_ss_info_270f_2801 +#define pci_ss_info_270f_2801 pci_ss_info_11ab_4362_270f_2801 +static const pciSubsystemInfo pci_ss_info_11ab_4362_a0a0_0506 = + {0xa0a0, 0x0506, pci_subsys_11ab_4362_a0a0_0506, 0}; +#undef pci_ss_info_a0a0_0506 +#define pci_ss_info_a0a0_0506 pci_ss_info_11ab_4362_a0a0_0506 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11ad_0002_11ad_0002 = + {0x11ad, 0x0002, pci_subsys_11ad_0002_11ad_0002, 0}; +#undef pci_ss_info_11ad_0002 +#define pci_ss_info_11ad_0002 pci_ss_info_11ad_0002_11ad_0002 +static const pciSubsystemInfo pci_ss_info_11ad_0002_11ad_0003 = + {0x11ad, 0x0003, pci_subsys_11ad_0002_11ad_0003, 0}; +#undef pci_ss_info_11ad_0003 +#define pci_ss_info_11ad_0003 pci_ss_info_11ad_0002_11ad_0003 +static const pciSubsystemInfo pci_ss_info_11ad_0002_11ad_f003 = + {0x11ad, 0xf003, pci_subsys_11ad_0002_11ad_f003, 0}; +#undef pci_ss_info_11ad_f003 +#define pci_ss_info_11ad_f003 pci_ss_info_11ad_0002_11ad_f003 +static const pciSubsystemInfo pci_ss_info_11ad_0002_11ad_ffff = + {0x11ad, 0xffff, pci_subsys_11ad_0002_11ad_ffff, 0}; +#undef pci_ss_info_11ad_ffff +#define pci_ss_info_11ad_ffff pci_ss_info_11ad_0002_11ad_ffff +static const pciSubsystemInfo pci_ss_info_11ad_0002_1385_f004 = + {0x1385, 0xf004, pci_subsys_11ad_0002_1385_f004, 0}; +#undef pci_ss_info_1385_f004 +#define pci_ss_info_1385_f004 pci_ss_info_11ad_0002_1385_f004 +static const pciSubsystemInfo pci_ss_info_11ad_c115_11ad_c001 = + {0x11ad, 0xc001, pci_subsys_11ad_c115_11ad_c001, 0}; +#undef pci_ss_info_11ad_c001 +#define pci_ss_info_11ad_c001 pci_ss_info_11ad_c115_11ad_c001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0440_1033_8015 = + {0x1033, 0x8015, pci_subsys_11c1_0440_1033_8015, 0}; +#undef pci_ss_info_1033_8015 +#define pci_ss_info_1033_8015 pci_ss_info_11c1_0440_1033_8015 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0440_1033_8047 = + {0x1033, 0x8047, pci_subsys_11c1_0440_1033_8047, 0}; +#undef pci_ss_info_1033_8047 +#define pci_ss_info_1033_8047 pci_ss_info_11c1_0440_1033_8047 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0440_1033_804f = + {0x1033, 0x804f, pci_subsys_11c1_0440_1033_804f, 0}; +#undef pci_ss_info_1033_804f +#define pci_ss_info_1033_804f pci_ss_info_11c1_0440_1033_804f +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0440_10cf_102c = + {0x10cf, 0x102c, pci_subsys_11c1_0440_10cf_102c, 0}; +#undef pci_ss_info_10cf_102c +#define pci_ss_info_10cf_102c pci_ss_info_11c1_0440_10cf_102c +static const pciSubsystemInfo pci_ss_info_11c1_0440_10cf_104a = + {0x10cf, 0x104a, pci_subsys_11c1_0440_10cf_104a, 0}; +#undef pci_ss_info_10cf_104a +#define pci_ss_info_10cf_104a pci_ss_info_11c1_0440_10cf_104a +static const pciSubsystemInfo pci_ss_info_11c1_0440_10cf_105f = + {0x10cf, 0x105f, pci_subsys_11c1_0440_10cf_105f, 0}; +#undef pci_ss_info_10cf_105f +#define pci_ss_info_10cf_105f pci_ss_info_11c1_0440_10cf_105f +static const pciSubsystemInfo pci_ss_info_11c1_0440_1179_0001 = + {0x1179, 0x0001, pci_subsys_11c1_0440_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_11c1_0440_1179_0001 +static const pciSubsystemInfo pci_ss_info_11c1_0440_11c1_0440 = + {0x11c1, 0x0440, pci_subsys_11c1_0440_11c1_0440, 0}; +#undef pci_ss_info_11c1_0440 +#define pci_ss_info_11c1_0440 pci_ss_info_11c1_0440_11c1_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0440_122d_4101 = + {0x122d, 0x4101, pci_subsys_11c1_0440_122d_4101, 0}; +#undef pci_ss_info_122d_4101 +#define pci_ss_info_122d_4101 pci_ss_info_11c1_0440_122d_4101 +static const pciSubsystemInfo pci_ss_info_11c1_0440_122d_4102 = + {0x122d, 0x4102, pci_subsys_11c1_0440_122d_4102, 0}; +#undef pci_ss_info_122d_4102 +#define pci_ss_info_122d_4102 pci_ss_info_11c1_0440_122d_4102 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_0040 = + {0x13e0, 0x0040, pci_subsys_11c1_0440_13e0_0040, 0}; +#undef pci_ss_info_13e0_0040 +#define pci_ss_info_13e0_0040 pci_ss_info_11c1_0440_13e0_0040 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_0440 = + {0x13e0, 0x0440, pci_subsys_11c1_0440_13e0_0440, 0}; +#undef pci_ss_info_13e0_0440 +#define pci_ss_info_13e0_0440 pci_ss_info_11c1_0440_13e0_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_0441 = + {0x13e0, 0x0441, pci_subsys_11c1_0440_13e0_0441, 0}; +#undef pci_ss_info_13e0_0441 +#define pci_ss_info_13e0_0441 pci_ss_info_11c1_0440_13e0_0441 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_0450 = + {0x13e0, 0x0450, pci_subsys_11c1_0440_13e0_0450, 0}; +#undef pci_ss_info_13e0_0450 +#define pci_ss_info_13e0_0450 pci_ss_info_11c1_0440_13e0_0450 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_f100 = + {0x13e0, 0xf100, pci_subsys_11c1_0440_13e0_f100, 0}; +#undef pci_ss_info_13e0_f100 +#define pci_ss_info_13e0_f100 pci_ss_info_11c1_0440_13e0_f100 +static const pciSubsystemInfo pci_ss_info_11c1_0440_13e0_f101 = + {0x13e0, 0xf101, pci_subsys_11c1_0440_13e0_f101, 0}; +#undef pci_ss_info_13e0_f101 +#define pci_ss_info_13e0_f101 pci_ss_info_11c1_0440_13e0_f101 +static const pciSubsystemInfo pci_ss_info_11c1_0440_144d_2101 = + {0x144d, 0x2101, pci_subsys_11c1_0440_144d_2101, 0}; +#undef pci_ss_info_144d_2101 +#define pci_ss_info_144d_2101 pci_ss_info_11c1_0440_144d_2101 +static const pciSubsystemInfo pci_ss_info_11c1_0440_149f_0440 = + {0x149f, 0x0440, pci_subsys_11c1_0440_149f_0440, 0}; +#undef pci_ss_info_149f_0440 +#define pci_ss_info_149f_0440 pci_ss_info_11c1_0440_149f_0440 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0441_1033_804d = + {0x1033, 0x804d, pci_subsys_11c1_0441_1033_804d, 0}; +#undef pci_ss_info_1033_804d +#define pci_ss_info_1033_804d pci_ss_info_11c1_0441_1033_804d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0441_1033_8065 = + {0x1033, 0x8065, pci_subsys_11c1_0441_1033_8065, 0}; +#undef pci_ss_info_1033_8065 +#define pci_ss_info_1033_8065 pci_ss_info_11c1_0441_1033_8065 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0441_1092_0440 = + {0x1092, 0x0440, pci_subsys_11c1_0441_1092_0440, 0}; +#undef pci_ss_info_1092_0440 +#define pci_ss_info_1092_0440 pci_ss_info_11c1_0441_1092_0440 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0441_1179_0001 = + {0x1179, 0x0001, pci_subsys_11c1_0441_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_11c1_0441_1179_0001 +static const pciSubsystemInfo pci_ss_info_11c1_0441_11c1_0440 = + {0x11c1, 0x0440, pci_subsys_11c1_0441_11c1_0440, 0}; +#undef pci_ss_info_11c1_0440 +#define pci_ss_info_11c1_0440 pci_ss_info_11c1_0441_11c1_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0441_11c1_0441 = + {0x11c1, 0x0441, pci_subsys_11c1_0441_11c1_0441, 0}; +#undef pci_ss_info_11c1_0441 +#define pci_ss_info_11c1_0441 pci_ss_info_11c1_0441_11c1_0441 +static const pciSubsystemInfo pci_ss_info_11c1_0441_122d_4100 = + {0x122d, 0x4100, pci_subsys_11c1_0441_122d_4100, 0}; +#undef pci_ss_info_122d_4100 +#define pci_ss_info_122d_4100 pci_ss_info_11c1_0441_122d_4100 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0040 = + {0x13e0, 0x0040, pci_subsys_11c1_0441_13e0_0040, 0}; +#undef pci_ss_info_13e0_0040 +#define pci_ss_info_13e0_0040 pci_ss_info_11c1_0441_13e0_0040 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0100 = + {0x13e0, 0x0100, pci_subsys_11c1_0441_13e0_0100, 0}; +#undef pci_ss_info_13e0_0100 +#define pci_ss_info_13e0_0100 pci_ss_info_11c1_0441_13e0_0100 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0410 = + {0x13e0, 0x0410, pci_subsys_11c1_0441_13e0_0410, 0}; +#undef pci_ss_info_13e0_0410 +#define pci_ss_info_13e0_0410 pci_ss_info_11c1_0441_13e0_0410 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0420 = + {0x13e0, 0x0420, pci_subsys_11c1_0441_13e0_0420, 0}; +#undef pci_ss_info_13e0_0420 +#define pci_ss_info_13e0_0420 pci_ss_info_11c1_0441_13e0_0420 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0440 = + {0x13e0, 0x0440, pci_subsys_11c1_0441_13e0_0440, 0}; +#undef pci_ss_info_13e0_0440 +#define pci_ss_info_13e0_0440 pci_ss_info_11c1_0441_13e0_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_0443 = + {0x13e0, 0x0443, pci_subsys_11c1_0441_13e0_0443, 0}; +#undef pci_ss_info_13e0_0443 +#define pci_ss_info_13e0_0443 pci_ss_info_11c1_0441_13e0_0443 +static const pciSubsystemInfo pci_ss_info_11c1_0441_13e0_f102 = + {0x13e0, 0xf102, pci_subsys_11c1_0441_13e0_f102, 0}; +#undef pci_ss_info_13e0_f102 +#define pci_ss_info_13e0_f102 pci_ss_info_11c1_0441_13e0_f102 +static const pciSubsystemInfo pci_ss_info_11c1_0441_1416_9804 = + {0x1416, 0x9804, pci_subsys_11c1_0441_1416_9804, 0}; +#undef pci_ss_info_1416_9804 +#define pci_ss_info_1416_9804 pci_ss_info_11c1_0441_1416_9804 +static const pciSubsystemInfo pci_ss_info_11c1_0441_141d_0440 = + {0x141d, 0x0440, pci_subsys_11c1_0441_141d_0440, 0}; +#undef pci_ss_info_141d_0440 +#define pci_ss_info_141d_0440 pci_ss_info_11c1_0441_141d_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0441_144f_0441 = + {0x144f, 0x0441, pci_subsys_11c1_0441_144f_0441, 0}; +#undef pci_ss_info_144f_0441 +#define pci_ss_info_144f_0441 pci_ss_info_11c1_0441_144f_0441 +static const pciSubsystemInfo pci_ss_info_11c1_0441_144f_0449 = + {0x144f, 0x0449, pci_subsys_11c1_0441_144f_0449, 0}; +#undef pci_ss_info_144f_0449 +#define pci_ss_info_144f_0449 pci_ss_info_11c1_0441_144f_0449 +static const pciSubsystemInfo pci_ss_info_11c1_0441_144f_110d = + {0x144f, 0x110d, pci_subsys_11c1_0441_144f_110d, 0}; +#undef pci_ss_info_144f_110d +#define pci_ss_info_144f_110d pci_ss_info_11c1_0441_144f_110d +static const pciSubsystemInfo pci_ss_info_11c1_0441_1468_0441 = + {0x1468, 0x0441, pci_subsys_11c1_0441_1468_0441, 0}; +#undef pci_ss_info_1468_0441 +#define pci_ss_info_1468_0441 pci_ss_info_11c1_0441_1468_0441 +static const pciSubsystemInfo pci_ss_info_11c1_0441_1668_0440 = + {0x1668, 0x0440, pci_subsys_11c1_0441_1668_0440, 0}; +#undef pci_ss_info_1668_0440 +#define pci_ss_info_1668_0440 pci_ss_info_11c1_0441_1668_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0442_11c1_0440 = + {0x11c1, 0x0440, pci_subsys_11c1_0442_11c1_0440, 0}; +#undef pci_ss_info_11c1_0440 +#define pci_ss_info_11c1_0440 pci_ss_info_11c1_0442_11c1_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0442_11c1_0442 = + {0x11c1, 0x0442, pci_subsys_11c1_0442_11c1_0442, 0}; +#undef pci_ss_info_11c1_0442 +#define pci_ss_info_11c1_0442 pci_ss_info_11c1_0442_11c1_0442 +static const pciSubsystemInfo pci_ss_info_11c1_0442_13e0_0412 = + {0x13e0, 0x0412, pci_subsys_11c1_0442_13e0_0412, 0}; +#undef pci_ss_info_13e0_0412 +#define pci_ss_info_13e0_0412 pci_ss_info_11c1_0442_13e0_0412 +static const pciSubsystemInfo pci_ss_info_11c1_0442_13e0_0442 = + {0x13e0, 0x0442, pci_subsys_11c1_0442_13e0_0442, 0}; +#undef pci_ss_info_13e0_0442 +#define pci_ss_info_13e0_0442 pci_ss_info_11c1_0442_13e0_0442 +static const pciSubsystemInfo pci_ss_info_11c1_0442_13fc_2471 = + {0x13fc, 0x2471, pci_subsys_11c1_0442_13fc_2471, 0}; +#undef pci_ss_info_13fc_2471 +#define pci_ss_info_13fc_2471 pci_ss_info_11c1_0442_13fc_2471 +static const pciSubsystemInfo pci_ss_info_11c1_0442_144d_2104 = + {0x144d, 0x2104, pci_subsys_11c1_0442_144d_2104, 0}; +#undef pci_ss_info_144d_2104 +#define pci_ss_info_144d_2104 pci_ss_info_11c1_0442_144d_2104 +static const pciSubsystemInfo pci_ss_info_11c1_0442_144f_1104 = + {0x144f, 0x1104, pci_subsys_11c1_0442_144f_1104, 0}; +#undef pci_ss_info_144f_1104 +#define pci_ss_info_144f_1104 pci_ss_info_11c1_0442_144f_1104 +static const pciSubsystemInfo pci_ss_info_11c1_0442_149f_0440 = + {0x149f, 0x0440, pci_subsys_11c1_0442_149f_0440, 0}; +#undef pci_ss_info_149f_0440 +#define pci_ss_info_149f_0440 pci_ss_info_11c1_0442_149f_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0442_1668_0440 = + {0x1668, 0x0440, pci_subsys_11c1_0442_1668_0440, 0}; +#undef pci_ss_info_1668_0440 +#define pci_ss_info_1668_0440 pci_ss_info_11c1_0442_1668_0440 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0445_8086_2203 = + {0x8086, 0x2203, pci_subsys_11c1_0445_8086_2203, 0}; +#undef pci_ss_info_8086_2203 +#define pci_ss_info_8086_2203 pci_ss_info_11c1_0445_8086_2203 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0445_8086_2204 = + {0x8086, 0x2204, pci_subsys_11c1_0445_8086_2204, 0}; +#undef pci_ss_info_8086_2204 +#define pci_ss_info_8086_2204 pci_ss_info_11c1_0445_8086_2204 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0448_1014_0131 = + {0x1014, 0x0131, pci_subsys_11c1_0448_1014_0131, 0}; +#undef pci_ss_info_1014_0131 +#define pci_ss_info_1014_0131 pci_ss_info_11c1_0448_1014_0131 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0448_1033_8066 = + {0x1033, 0x8066, pci_subsys_11c1_0448_1033_8066, 0}; +#undef pci_ss_info_1033_8066 +#define pci_ss_info_1033_8066 pci_ss_info_11c1_0448_1033_8066 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0448_13e0_0030 = + {0x13e0, 0x0030, pci_subsys_11c1_0448_13e0_0030, 0}; +#undef pci_ss_info_13e0_0030 +#define pci_ss_info_13e0_0030 pci_ss_info_11c1_0448_13e0_0030 +static const pciSubsystemInfo pci_ss_info_11c1_0448_13e0_0040 = + {0x13e0, 0x0040, pci_subsys_11c1_0448_13e0_0040, 0}; +#undef pci_ss_info_13e0_0040 +#define pci_ss_info_13e0_0040 pci_ss_info_11c1_0448_13e0_0040 +static const pciSubsystemInfo pci_ss_info_11c1_0448_1668_2400 = + {0x1668, 0x2400, pci_subsys_11c1_0448_1668_2400, 0}; +#undef pci_ss_info_1668_2400 +#define pci_ss_info_1668_2400 pci_ss_info_11c1_0448_1668_2400 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0449_0e11_b14d = + {0x0e11, 0xb14d, pci_subsys_11c1_0449_0e11_b14d, 0}; +#undef pci_ss_info_0e11_b14d +#define pci_ss_info_0e11_b14d pci_ss_info_11c1_0449_0e11_b14d +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0449_13e0_0020 = + {0x13e0, 0x0020, pci_subsys_11c1_0449_13e0_0020, 0}; +#undef pci_ss_info_13e0_0020 +#define pci_ss_info_13e0_0020 pci_ss_info_11c1_0449_13e0_0020 +static const pciSubsystemInfo pci_ss_info_11c1_0449_13e0_0041 = + {0x13e0, 0x0041, pci_subsys_11c1_0449_13e0_0041, 0}; +#undef pci_ss_info_13e0_0041 +#define pci_ss_info_13e0_0041 pci_ss_info_11c1_0449_13e0_0041 +static const pciSubsystemInfo pci_ss_info_11c1_0449_1436_0440 = + {0x1436, 0x0440, pci_subsys_11c1_0449_1436_0440, 0}; +#undef pci_ss_info_1436_0440 +#define pci_ss_info_1436_0440 pci_ss_info_11c1_0449_1436_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0449_144f_0449 = + {0x144f, 0x0449, pci_subsys_11c1_0449_144f_0449, 0}; +#undef pci_ss_info_144f_0449 +#define pci_ss_info_144f_0449 pci_ss_info_11c1_0449_144f_0449 +static const pciSubsystemInfo pci_ss_info_11c1_0449_1468_0410 = + {0x1468, 0x0410, pci_subsys_11c1_0449_1468_0410, 0}; +#undef pci_ss_info_1468_0410 +#define pci_ss_info_1468_0410 pci_ss_info_11c1_0449_1468_0410 +static const pciSubsystemInfo pci_ss_info_11c1_0449_1468_0440 = + {0x1468, 0x0440, pci_subsys_11c1_0449_1468_0440, 0}; +#undef pci_ss_info_1468_0440 +#define pci_ss_info_1468_0440 pci_ss_info_11c1_0449_1468_0440 +static const pciSubsystemInfo pci_ss_info_11c1_0449_1468_0449 = + {0x1468, 0x0449, pci_subsys_11c1_0449_1468_0449, 0}; +#undef pci_ss_info_1468_0449 +#define pci_ss_info_1468_0449 pci_ss_info_11c1_0449_1468_0449 +static const pciSubsystemInfo pci_ss_info_11c1_044a_10cf_1072 = + {0x10cf, 0x1072, pci_subsys_11c1_044a_10cf_1072, 0}; +#undef pci_ss_info_10cf_1072 +#define pci_ss_info_10cf_1072 pci_ss_info_11c1_044a_10cf_1072 +static const pciSubsystemInfo pci_ss_info_11c1_044a_13e0_0012 = + {0x13e0, 0x0012, pci_subsys_11c1_044a_13e0_0012, 0}; +#undef pci_ss_info_13e0_0012 +#define pci_ss_info_13e0_0012 pci_ss_info_11c1_044a_13e0_0012 +static const pciSubsystemInfo pci_ss_info_11c1_044a_13e0_0042 = + {0x13e0, 0x0042, pci_subsys_11c1_044a_13e0_0042, 0}; +#undef pci_ss_info_13e0_0042 +#define pci_ss_info_13e0_0042 pci_ss_info_11c1_044a_13e0_0042 +static const pciSubsystemInfo pci_ss_info_11c1_044a_144f_1005 = + {0x144f, 0x1005, pci_subsys_11c1_044a_144f_1005, 0}; +#undef pci_ss_info_144f_1005 +#define pci_ss_info_144f_1005 pci_ss_info_11c1_044a_144f_1005 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0450_1033_80a8 = + {0x1033, 0x80a8, pci_subsys_11c1_0450_1033_80a8, 0}; +#undef pci_ss_info_1033_80a8 +#define pci_ss_info_1033_80a8 pci_ss_info_11c1_0450_1033_80a8 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_0450_144f_4005 = + {0x144f, 0x4005, pci_subsys_11c1_0450_144f_4005, 0}; +#undef pci_ss_info_144f_4005 +#define pci_ss_info_144f_4005 pci_ss_info_11c1_0450_144f_4005 +static const pciSubsystemInfo pci_ss_info_11c1_0450_1468_0450 = + {0x1468, 0x0450, pci_subsys_11c1_0450_1468_0450, 0}; +#undef pci_ss_info_1468_0450 +#define pci_ss_info_1468_0450 pci_ss_info_11c1_0450_1468_0450 +#endif +static const pciSubsystemInfo pci_ss_info_11c1_0450_4005_144f = + {0x4005, 0x144f, pci_subsys_11c1_0450_4005_144f, 0}; +#undef pci_ss_info_4005_144f +#define pci_ss_info_4005_144f pci_ss_info_11c1_0450_4005_144f +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11c1_5811_8086_524c = + {0x8086, 0x524c, pci_subsys_11c1_5811_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_11c1_5811_8086_524c +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11c1_5811_dead_0800 = + {0xdead, 0x0800, pci_subsys_11c1_5811_dead_0800, 0}; +#undef pci_ss_info_dead_0800 +#define pci_ss_info_dead_0800 pci_ss_info_11c1_5811_dead_0800 +static const pciSubsystemInfo pci_ss_info_11c1_8110_12d9_000c = + {0x12d9, 0x000c, pci_subsys_11c1_8110_12d9_000c, 0}; +#undef pci_ss_info_12d9_000c +#define pci_ss_info_12d9_000c pci_ss_info_11c1_8110_12d9_000c +static const pciSubsystemInfo pci_ss_info_11c1_ab11_11c1_ab12 = + {0x11c1, 0xab12, pci_subsys_11c1_ab11_11c1_ab12, 0}; +#undef pci_ss_info_11c1_ab12 +#define pci_ss_info_11c1_ab12 pci_ss_info_11c1_ab11_11c1_ab12 +static const pciSubsystemInfo pci_ss_info_11c1_ab11_11c1_ab13 = + {0x11c1, 0xab13, pci_subsys_11c1_ab11_11c1_ab13, 0}; +#undef pci_ss_info_11c1_ab13 +#define pci_ss_info_11c1_ab13 pci_ss_info_11c1_ab11_11c1_ab13 +static const pciSubsystemInfo pci_ss_info_11c1_ab11_11c1_ab15 = + {0x11c1, 0xab15, pci_subsys_11c1_ab11_11c1_ab15, 0}; +#undef pci_ss_info_11c1_ab15 +#define pci_ss_info_11c1_ab15 pci_ss_info_11c1_ab11_11c1_ab15 +static const pciSubsystemInfo pci_ss_info_11c1_ab11_11c1_ab16 = + {0x11c1, 0xab16, pci_subsys_11c1_ab11_11c1_ab16, 0}; +#undef pci_ss_info_11c1_ab16 +#define pci_ss_info_11c1_ab16 pci_ss_info_11c1_ab11_11c1_ab16 +static const pciSubsystemInfo pci_ss_info_11c1_ab30_14cd_2012 = + {0x14cd, 0x2012, pci_subsys_11c1_ab30_14cd_2012, 0}; +#undef pci_ss_info_14cd_2012 +#define pci_ss_info_14cd_2012 pci_ss_info_11c1_ab30_14cd_2012 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11cb_2000_11cb_0200 = + {0x11cb, 0x0200, pci_subsys_11cb_2000_11cb_0200, 0}; +#undef pci_ss_info_11cb_0200 +#define pci_ss_info_11cb_0200 pci_ss_info_11cb_2000_11cb_0200 +static const pciSubsystemInfo pci_ss_info_11cb_2000_11cb_b008 = + {0x11cb, 0xb008, pci_subsys_11cb_2000_11cb_b008, 0}; +#undef pci_ss_info_11cb_b008 +#define pci_ss_info_11cb_b008 pci_ss_info_11cb_2000_11cb_b008 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11de_6057_1031_7efe = + {0x1031, 0x7efe, pci_subsys_11de_6057_1031_7efe, 0}; +#undef pci_ss_info_1031_7efe +#define pci_ss_info_1031_7efe pci_ss_info_11de_6057_1031_7efe +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_11de_6057_1031_fc00 = + {0x1031, 0xfc00, pci_subsys_11de_6057_1031_fc00, 0}; +#undef pci_ss_info_1031_fc00 +#define pci_ss_info_1031_fc00 pci_ss_info_11de_6057_1031_fc00 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11de_6057_12f8_8a02 = + {0x12f8, 0x8a02, pci_subsys_11de_6057_12f8_8a02, 0}; +#undef pci_ss_info_12f8_8a02 +#define pci_ss_info_12f8_8a02 pci_ss_info_11de_6057_12f8_8a02 +static const pciSubsystemInfo pci_ss_info_11de_6057_13ca_4231 = + {0x13ca, 0x4231, pci_subsys_11de_6057_13ca_4231, 0}; +#undef pci_ss_info_13ca_4231 +#define pci_ss_info_13ca_4231 pci_ss_info_11de_6057_13ca_4231 +static const pciSubsystemInfo pci_ss_info_11de_6120_1328_f001 = + {0x1328, 0xf001, pci_subsys_11de_6120_1328_f001, 0}; +#undef pci_ss_info_1328_f001 +#define pci_ss_info_1328_f001 pci_ss_info_11de_6120_1328_f001 +static const pciSubsystemInfo pci_ss_info_11de_6120_13c2_0000 = + {0x13c2, 0x0000, pci_subsys_11de_6120_13c2_0000, 0}; +#undef pci_ss_info_13c2_0000 +#define pci_ss_info_13c2_0000 pci_ss_info_11de_6120_13c2_0000 +static const pciSubsystemInfo pci_ss_info_11de_6120_1de1_9fff = + {0x1de1, 0x9fff, pci_subsys_11de_6120_1de1_9fff, 0}; +#undef pci_ss_info_1de1_9fff +#define pci_ss_info_1de1_9fff pci_ss_info_11de_6120_1de1_9fff +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_11f6_2011_11f6_2011 = + {0x11f6, 0x2011, pci_subsys_11f6_2011_11f6_2011, 0}; +#undef pci_ss_info_11f6_2011 +#define pci_ss_info_11f6_2011 pci_ss_info_11f6_2011_11f6_2011 +static const pciSubsystemInfo pci_ss_info_11f6_2201_11f6_2011 = + {0x11f6, 0x2011, pci_subsys_11f6_2201_11f6_2011, 0}; +#undef pci_ss_info_11f6_2011 +#define pci_ss_info_11f6_2011 pci_ss_info_11f6_2201_11f6_2011 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1202_4300_1202_9841 = + {0x1202, 0x9841, pci_subsys_1202_4300_1202_9841, 0}; +#undef pci_ss_info_1202_9841 +#define pci_ss_info_1202_9841 pci_ss_info_1202_4300_1202_9841 +static const pciSubsystemInfo pci_ss_info_1202_4300_1202_9842 = + {0x1202, 0x9842, pci_subsys_1202_4300_1202_9842, 0}; +#undef pci_ss_info_1202_9842 +#define pci_ss_info_1202_9842 pci_ss_info_1202_4300_1202_9842 +static const pciSubsystemInfo pci_ss_info_1202_4300_1202_9843 = + {0x1202, 0x9843, pci_subsys_1202_4300_1202_9843, 0}; +#undef pci_ss_info_1202_9843 +#define pci_ss_info_1202_9843 pci_ss_info_1202_4300_1202_9843 +static const pciSubsystemInfo pci_ss_info_1202_4300_1202_9844 = + {0x1202, 0x9844, pci_subsys_1202_4300_1202_9844, 0}; +#undef pci_ss_info_1202_9844 +#define pci_ss_info_1202_9844 pci_ss_info_1202_4300_1202_9844 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1217_6933_1025_1016 = + {0x1025, 0x1016, pci_subsys_1217_6933_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_1217_6933_1025_1016 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1217_6972_1014_020c = + {0x1014, 0x020c, pci_subsys_1217_6972_1014_020c, 0}; +#undef pci_ss_info_1014_020c +#define pci_ss_info_1014_020c pci_ss_info_1217_6972_1014_020c +static const pciSubsystemInfo pci_ss_info_1217_6972_1179_0001 = + {0x1179, 0x0001, pci_subsys_1217_6972_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_1217_6972_1179_0001 +#endif +static const pciSubsystemInfo pci_ss_info_1217_7110_103c_088c = + {0x103c, 0x088c, pci_subsys_1217_7110_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_1217_7110_103c_088c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1217_7110_103c_0890 = + {0x103c, 0x0890, pci_subsys_1217_7110_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_1217_7110_103c_0890 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1217_7110_1734_106c = + {0x1734, 0x106c, pci_subsys_1217_7110_1734_106c, 0}; +#undef pci_ss_info_1734_106c +#define pci_ss_info_1734_106c pci_ss_info_1217_7110_1734_106c +#endif +static const pciSubsystemInfo pci_ss_info_1217_7223_103c_088c = + {0x103c, 0x088c, pci_subsys_1217_7223_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_1217_7223_103c_088c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1217_7223_103c_0890 = + {0x103c, 0x0890, pci_subsys_1217_7223_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_1217_7223_103c_0890 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_0003 = + {0x1092, 0x0003, pci_subsys_121a_0003_1092_0003, 0}; +#undef pci_ss_info_1092_0003 +#define pci_ss_info_1092_0003 pci_ss_info_121a_0003_1092_0003 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_4000 = + {0x1092, 0x4000, pci_subsys_121a_0003_1092_4000, 0}; +#undef pci_ss_info_1092_4000 +#define pci_ss_info_1092_4000 pci_ss_info_121a_0003_1092_4000 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_4002 = + {0x1092, 0x4002, pci_subsys_121a_0003_1092_4002, 0}; +#undef pci_ss_info_1092_4002 +#define pci_ss_info_1092_4002 pci_ss_info_121a_0003_1092_4002 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_4801 = + {0x1092, 0x4801, pci_subsys_121a_0003_1092_4801, 0}; +#undef pci_ss_info_1092_4801 +#define pci_ss_info_1092_4801 pci_ss_info_121a_0003_1092_4801 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_4803 = + {0x1092, 0x4803, pci_subsys_121a_0003_1092_4803, 0}; +#undef pci_ss_info_1092_4803 +#define pci_ss_info_1092_4803 pci_ss_info_121a_0003_1092_4803 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_8030 = + {0x1092, 0x8030, pci_subsys_121a_0003_1092_8030, 0}; +#undef pci_ss_info_1092_8030 +#define pci_ss_info_1092_8030 pci_ss_info_121a_0003_1092_8030 +static const pciSubsystemInfo pci_ss_info_121a_0003_1092_8035 = + {0x1092, 0x8035, pci_subsys_121a_0003_1092_8035, 0}; +#undef pci_ss_info_1092_8035 +#define pci_ss_info_1092_8035 pci_ss_info_121a_0003_1092_8035 +static const pciSubsystemInfo pci_ss_info_121a_0003_10b0_0001 = + {0x10b0, 0x0001, pci_subsys_121a_0003_10b0_0001, 0}; +#undef pci_ss_info_10b0_0001 +#define pci_ss_info_10b0_0001 pci_ss_info_121a_0003_10b0_0001 +static const pciSubsystemInfo pci_ss_info_121a_0003_1102_1018 = + {0x1102, 0x1018, pci_subsys_121a_0003_1102_1018, 0}; +#undef pci_ss_info_1102_1018 +#define pci_ss_info_1102_1018 pci_ss_info_121a_0003_1102_1018 +static const pciSubsystemInfo pci_ss_info_121a_0003_121a_0001 = + {0x121a, 0x0001, pci_subsys_121a_0003_121a_0001, 0}; +#undef pci_ss_info_121a_0001 +#define pci_ss_info_121a_0001 pci_ss_info_121a_0003_121a_0001 +static const pciSubsystemInfo pci_ss_info_121a_0003_121a_0003 = + {0x121a, 0x0003, pci_subsys_121a_0003_121a_0003, 0}; +#undef pci_ss_info_121a_0003 +#define pci_ss_info_121a_0003 pci_ss_info_121a_0003_121a_0003 +static const pciSubsystemInfo pci_ss_info_121a_0003_121a_0004 = + {0x121a, 0x0004, pci_subsys_121a_0003_121a_0004, 0}; +#undef pci_ss_info_121a_0004 +#define pci_ss_info_121a_0004 pci_ss_info_121a_0003_121a_0004 +static const pciSubsystemInfo pci_ss_info_121a_0003_139c_0016 = + {0x139c, 0x0016, pci_subsys_121a_0003_139c_0016, 0}; +#undef pci_ss_info_139c_0016 +#define pci_ss_info_139c_0016 pci_ss_info_121a_0003_139c_0016 +static const pciSubsystemInfo pci_ss_info_121a_0003_139c_0017 = + {0x139c, 0x0017, pci_subsys_121a_0003_139c_0017, 0}; +#undef pci_ss_info_139c_0017 +#define pci_ss_info_139c_0017 pci_ss_info_121a_0003_139c_0017 +static const pciSubsystemInfo pci_ss_info_121a_0003_14af_0002 = + {0x14af, 0x0002, pci_subsys_121a_0003_14af_0002, 0}; +#undef pci_ss_info_14af_0002 +#define pci_ss_info_14af_0002 pci_ss_info_121a_0003_14af_0002 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0004 = + {0x121a, 0x0004, pci_subsys_121a_0005_121a_0004, 0}; +#undef pci_ss_info_121a_0004 +#define pci_ss_info_121a_0004 pci_ss_info_121a_0005_121a_0004 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0030 = + {0x121a, 0x0030, pci_subsys_121a_0005_121a_0030, 0}; +#undef pci_ss_info_121a_0030 +#define pci_ss_info_121a_0030 pci_ss_info_121a_0005_121a_0030 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0031 = + {0x121a, 0x0031, pci_subsys_121a_0005_121a_0031, 0}; +#undef pci_ss_info_121a_0031 +#define pci_ss_info_121a_0031 pci_ss_info_121a_0005_121a_0031 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0034 = + {0x121a, 0x0034, pci_subsys_121a_0005_121a_0034, 0}; +#undef pci_ss_info_121a_0034 +#define pci_ss_info_121a_0034 pci_ss_info_121a_0005_121a_0034 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0036 = + {0x121a, 0x0036, pci_subsys_121a_0005_121a_0036, 0}; +#undef pci_ss_info_121a_0036 +#define pci_ss_info_121a_0036 pci_ss_info_121a_0005_121a_0036 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0037 = + {0x121a, 0x0037, pci_subsys_121a_0005_121a_0037, 0}; +#undef pci_ss_info_121a_0037 +#define pci_ss_info_121a_0037 pci_ss_info_121a_0005_121a_0037 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0038 = + {0x121a, 0x0038, pci_subsys_121a_0005_121a_0038, 0}; +#undef pci_ss_info_121a_0038 +#define pci_ss_info_121a_0038 pci_ss_info_121a_0005_121a_0038 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_003a = + {0x121a, 0x003a, pci_subsys_121a_0005_121a_003a, 0}; +#undef pci_ss_info_121a_003a +#define pci_ss_info_121a_003a pci_ss_info_121a_0005_121a_003a +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0044 = + {0x121a, 0x0044, pci_subsys_121a_0005_121a_0044, 0}; +#undef pci_ss_info_121a_0044 +#define pci_ss_info_121a_0044 pci_ss_info_121a_0005_121a_0044 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_004b = + {0x121a, 0x004b, pci_subsys_121a_0005_121a_004b, 0}; +#undef pci_ss_info_121a_004b +#define pci_ss_info_121a_004b pci_ss_info_121a_0005_121a_004b +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_004c = + {0x121a, 0x004c, pci_subsys_121a_0005_121a_004c, 0}; +#undef pci_ss_info_121a_004c +#define pci_ss_info_121a_004c pci_ss_info_121a_0005_121a_004c +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_004d = + {0x121a, 0x004d, pci_subsys_121a_0005_121a_004d, 0}; +#undef pci_ss_info_121a_004d +#define pci_ss_info_121a_004d pci_ss_info_121a_0005_121a_004d +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_004e = + {0x121a, 0x004e, pci_subsys_121a_0005_121a_004e, 0}; +#undef pci_ss_info_121a_004e +#define pci_ss_info_121a_004e pci_ss_info_121a_0005_121a_004e +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0051 = + {0x121a, 0x0051, pci_subsys_121a_0005_121a_0051, 0}; +#undef pci_ss_info_121a_0051 +#define pci_ss_info_121a_0051 pci_ss_info_121a_0005_121a_0051 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0052 = + {0x121a, 0x0052, pci_subsys_121a_0005_121a_0052, 0}; +#undef pci_ss_info_121a_0052 +#define pci_ss_info_121a_0052 pci_ss_info_121a_0005_121a_0052 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0057 = + {0x121a, 0x0057, pci_subsys_121a_0005_121a_0057, 0}; +#undef pci_ss_info_121a_0057 +#define pci_ss_info_121a_0057 pci_ss_info_121a_0005_121a_0057 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0060 = + {0x121a, 0x0060, pci_subsys_121a_0005_121a_0060, 0}; +#undef pci_ss_info_121a_0060 +#define pci_ss_info_121a_0060 pci_ss_info_121a_0005_121a_0060 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0061 = + {0x121a, 0x0061, pci_subsys_121a_0005_121a_0061, 0}; +#undef pci_ss_info_121a_0061 +#define pci_ss_info_121a_0061 pci_ss_info_121a_0005_121a_0061 +static const pciSubsystemInfo pci_ss_info_121a_0005_121a_0062 = + {0x121a, 0x0062, pci_subsys_121a_0005_121a_0062, 0}; +#undef pci_ss_info_121a_0062 +#define pci_ss_info_121a_0062 pci_ss_info_121a_0005_121a_0062 +static const pciSubsystemInfo pci_ss_info_121a_0009_121a_0003 = + {0x121a, 0x0003, pci_subsys_121a_0009_121a_0003, 0}; +#undef pci_ss_info_121a_0003 +#define pci_ss_info_121a_0003 pci_ss_info_121a_0009_121a_0003 +static const pciSubsystemInfo pci_ss_info_121a_0009_121a_0009 = + {0x121a, 0x0009, pci_subsys_121a_0009_121a_0009, 0}; +#undef pci_ss_info_121a_0009 +#define pci_ss_info_121a_0009 pci_ss_info_121a_0009_121a_0009 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_122d_50dc_122d_0001 = + {0x122d, 0x0001, pci_subsys_122d_50dc_122d_0001, 0}; +#undef pci_ss_info_122d_0001 +#define pci_ss_info_122d_0001 pci_ss_info_122d_50dc_122d_0001 +static const pciSubsystemInfo pci_ss_info_122d_80da_122d_0001 = + {0x122d, 0x0001, pci_subsys_122d_80da_122d_0001, 0}; +#undef pci_ss_info_122d_0001 +#define pci_ss_info_122d_0001 pci_ss_info_122d_80da_122d_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_123f_8120_11bd_0006 = + {0x11bd, 0x0006, pci_subsys_123f_8120_11bd_0006, 0}; +#undef pci_ss_info_11bd_0006 +#define pci_ss_info_11bd_0006 pci_ss_info_123f_8120_11bd_0006 +static const pciSubsystemInfo pci_ss_info_123f_8120_11bd_000a = + {0x11bd, 0x000a, pci_subsys_123f_8120_11bd_000a, 0}; +#undef pci_ss_info_11bd_000a +#define pci_ss_info_11bd_000a pci_ss_info_123f_8120_11bd_000a +static const pciSubsystemInfo pci_ss_info_123f_8120_11bd_000f = + {0x11bd, 0x000f, pci_subsys_123f_8120_11bd_000f, 0}; +#undef pci_ss_info_11bd_000f +#define pci_ss_info_11bd_000f pci_ss_info_123f_8120_11bd_000f +static const pciSubsystemInfo pci_ss_info_123f_8120_1809_0016 = + {0x1809, 0x0016, pci_subsys_123f_8120_1809_0016, 0}; +#undef pci_ss_info_1809_0016 +#define pci_ss_info_1809_0016 pci_ss_info_123f_8120_1809_0016 +#endif +static const pciSubsystemInfo pci_ss_info_123f_8888_1002_0001 = + {0x1002, 0x0001, pci_subsys_123f_8888_1002_0001, 0}; +#undef pci_ss_info_1002_0001 +#define pci_ss_info_1002_0001 pci_ss_info_123f_8888_1002_0001 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_123f_8888_1002_0002 = + {0x1002, 0x0002, pci_subsys_123f_8888_1002_0002, 0}; +#undef pci_ss_info_1002_0002 +#define pci_ss_info_1002_0002 pci_ss_info_123f_8888_1002_0002 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_123f_8888_1328_0001 = + {0x1328, 0x0001, pci_subsys_123f_8888_1328_0001, 0}; +#undef pci_ss_info_1328_0001 +#define pci_ss_info_1328_0001 pci_ss_info_123f_8888_1328_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1242_1560_1242_6562 = + {0x1242, 0x6562, pci_subsys_1242_1560_1242_6562, 0}; +#undef pci_ss_info_1242_6562 +#define pci_ss_info_1242_6562 pci_ss_info_1242_1560_1242_6562 +static const pciSubsystemInfo pci_ss_info_1242_1560_1242_656a = + {0x1242, 0x656a, pci_subsys_1242_1560_1242_656a, 0}; +#undef pci_ss_info_1242_656a +#define pci_ss_info_1242_656a pci_ss_info_1242_1560_1242_656a +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1244_0a00_1244_0a00 = + {0x1244, 0x0a00, pci_subsys_1244_0a00_1244_0a00, 0}; +#undef pci_ss_info_1244_0a00 +#define pci_ss_info_1244_0a00 pci_ss_info_1244_0a00_1244_0a00 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_124b_0040_124b_9080 = + {0x124b, 0x9080, pci_subsys_124b_0040_124b_9080, 0}; +#undef pci_ss_info_124b_9080 +#define pci_ss_info_124b_9080 pci_ss_info_124b_0040_124b_9080 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_125b_1400_1186_1100 = + {0x1186, 0x1100, pci_subsys_125b_1400_1186_1100, 0}; +#undef pci_ss_info_1186_1100 +#define pci_ss_info_1186_1100 pci_ss_info_125b_1400_1186_1100 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1968_1028_0085 = + {0x1028, 0x0085, pci_subsys_125d_1968_1028_0085, 0}; +#undef pci_ss_info_1028_0085 +#define pci_ss_info_1028_0085 pci_ss_info_125d_1968_1028_0085 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1968_1033_8051 = + {0x1033, 0x8051, pci_subsys_125d_1968_1033_8051, 0}; +#undef pci_ss_info_1033_8051 +#define pci_ss_info_1033_8051 pci_ss_info_125d_1968_1033_8051 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_125d_1969_1014_0166 = + {0x1014, 0x0166, pci_subsys_125d_1969_1014_0166, 0}; +#undef pci_ss_info_1014_0166 +#define pci_ss_info_1014_0166 pci_ss_info_125d_1969_1014_0166 +static const pciSubsystemInfo pci_ss_info_125d_1969_125d_8888 = + {0x125d, 0x8888, pci_subsys_125d_1969_125d_8888, 0}; +#undef pci_ss_info_125d_8888 +#define pci_ss_info_125d_8888 pci_ss_info_125d_1969_125d_8888 +static const pciSubsystemInfo pci_ss_info_125d_1969_153b_111b = + {0x153b, 0x111b, pci_subsys_125d_1969_153b_111b, 0}; +#undef pci_ss_info_153b_111b +#define pci_ss_info_153b_111b pci_ss_info_125d_1969_153b_111b +#endif +static const pciSubsystemInfo pci_ss_info_125d_1978_0e11_b112 = + {0x0e11, 0xb112, pci_subsys_125d_1978_0e11_b112, 0}; +#undef pci_ss_info_0e11_b112 +#define pci_ss_info_0e11_b112 pci_ss_info_125d_1978_0e11_b112 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1978_1033_803c = + {0x1033, 0x803c, pci_subsys_125d_1978_1033_803c, 0}; +#undef pci_ss_info_1033_803c +#define pci_ss_info_1033_803c pci_ss_info_125d_1978_1033_803c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1978_1033_8058 = + {0x1033, 0x8058, pci_subsys_125d_1978_1033_8058, 0}; +#undef pci_ss_info_1033_8058 +#define pci_ss_info_1033_8058 pci_ss_info_125d_1978_1033_8058 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1978_1092_4000 = + {0x1092, 0x4000, pci_subsys_125d_1978_1092_4000, 0}; +#undef pci_ss_info_1092_4000 +#define pci_ss_info_1092_4000 pci_ss_info_125d_1978_1092_4000 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_125d_1978_1179_0001 = + {0x1179, 0x0001, pci_subsys_125d_1978_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_125d_1978_1179_0001 +#endif +static const pciSubsystemInfo pci_ss_info_125d_1988_0e11_0098 = + {0x0e11, 0x0098, pci_subsys_125d_1988_0e11_0098, 0}; +#undef pci_ss_info_0e11_0098 +#define pci_ss_info_0e11_0098 pci_ss_info_125d_1988_0e11_0098 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1988_1092_4100 = + {0x1092, 0x4100, pci_subsys_125d_1988_1092_4100, 0}; +#undef pci_ss_info_1092_4100 +#define pci_ss_info_1092_4100 pci_ss_info_125d_1988_1092_4100 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_125d_1988_125d_1988 = + {0x125d, 0x1988, pci_subsys_125d_1988_125d_1988, 0}; +#undef pci_ss_info_125d_1988 +#define pci_ss_info_125d_1988 pci_ss_info_125d_1988_125d_1988 +static const pciSubsystemInfo pci_ss_info_125d_1989_125d_1989 = + {0x125d, 0x1989, pci_subsys_125d_1989_125d_1989, 0}; +#undef pci_ss_info_125d_1989 +#define pci_ss_info_125d_1989 pci_ss_info_125d_1989_125d_1989 +#endif +static const pciSubsystemInfo pci_ss_info_125d_1998_1028_00b1 = + {0x1028, 0x00b1, pci_subsys_125d_1998_1028_00b1, 0}; +#undef pci_ss_info_1028_00b1 +#define pci_ss_info_1028_00b1 pci_ss_info_125d_1998_1028_00b1 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_125d_1998_1028_00e6 = + {0x1028, 0x00e6, pci_subsys_125d_1998_1028_00e6, 0}; +#undef pci_ss_info_1028_00e6 +#define pci_ss_info_1028_00e6 pci_ss_info_125d_1998_1028_00e6 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0424 = + {0x125d, 0x0424, pci_subsys_125d_2898_125d_0424, 0}; +#undef pci_ss_info_125d_0424 +#define pci_ss_info_125d_0424 pci_ss_info_125d_2898_125d_0424 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0425 = + {0x125d, 0x0425, pci_subsys_125d_2898_125d_0425, 0}; +#undef pci_ss_info_125d_0425 +#define pci_ss_info_125d_0425 pci_ss_info_125d_2898_125d_0425 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0426 = + {0x125d, 0x0426, pci_subsys_125d_2898_125d_0426, 0}; +#undef pci_ss_info_125d_0426 +#define pci_ss_info_125d_0426 pci_ss_info_125d_2898_125d_0426 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0427 = + {0x125d, 0x0427, pci_subsys_125d_2898_125d_0427, 0}; +#undef pci_ss_info_125d_0427 +#define pci_ss_info_125d_0427 pci_ss_info_125d_2898_125d_0427 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0428 = + {0x125d, 0x0428, pci_subsys_125d_2898_125d_0428, 0}; +#undef pci_ss_info_125d_0428 +#define pci_ss_info_125d_0428 pci_ss_info_125d_2898_125d_0428 +static const pciSubsystemInfo pci_ss_info_125d_2898_125d_0429 = + {0x125d, 0x0429, pci_subsys_125d_2898_125d_0429, 0}; +#undef pci_ss_info_125d_0429 +#define pci_ss_info_125d_0429 pci_ss_info_125d_2898_125d_0429 +static const pciSubsystemInfo pci_ss_info_125d_2898_147a_c001 = + {0x147a, 0xc001, pci_subsys_125d_2898_147a_c001, 0}; +#undef pci_ss_info_147a_c001 +#define pci_ss_info_147a_c001 pci_ss_info_125d_2898_147a_c001 +static const pciSubsystemInfo pci_ss_info_125d_2898_14fe_0428 = + {0x14fe, 0x0428, pci_subsys_125d_2898_14fe_0428, 0}; +#undef pci_ss_info_14fe_0428 +#define pci_ss_info_14fe_0428 pci_ss_info_125d_2898_14fe_0428 +static const pciSubsystemInfo pci_ss_info_125d_2898_14fe_0429 = + {0x14fe, 0x0429, pci_subsys_125d_2898_14fe_0429, 0}; +#undef pci_ss_info_14fe_0429 +#define pci_ss_info_14fe_0429 pci_ss_info_125d_2898_14fe_0429 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1260_3872_1468_0202 = + {0x1468, 0x0202, pci_subsys_1260_3872_1468_0202, 0}; +#undef pci_ss_info_1468_0202 +#define pci_ss_info_1468_0202 pci_ss_info_1260_3872_1468_0202 +static const pciSubsystemInfo pci_ss_info_1260_3873_1186_3501 = + {0x1186, 0x3501, pci_subsys_1260_3873_1186_3501, 0}; +#undef pci_ss_info_1186_3501 +#define pci_ss_info_1186_3501 pci_ss_info_1260_3873_1186_3501 +static const pciSubsystemInfo pci_ss_info_1260_3873_1186_3700 = + {0x1186, 0x3700, pci_subsys_1260_3873_1186_3700, 0}; +#undef pci_ss_info_1186_3700 +#define pci_ss_info_1186_3700 pci_ss_info_1260_3873_1186_3700 +static const pciSubsystemInfo pci_ss_info_1260_3873_1385_4105 = + {0x1385, 0x4105, pci_subsys_1260_3873_1385_4105, 0}; +#undef pci_ss_info_1385_4105 +#define pci_ss_info_1385_4105 pci_ss_info_1260_3873_1385_4105 +static const pciSubsystemInfo pci_ss_info_1260_3873_1668_0414 = + {0x1668, 0x0414, pci_subsys_1260_3873_1668_0414, 0}; +#undef pci_ss_info_1668_0414 +#define pci_ss_info_1668_0414 pci_ss_info_1260_3873_1668_0414 +static const pciSubsystemInfo pci_ss_info_1260_3873_16a5_1601 = + {0x16a5, 0x1601, pci_subsys_1260_3873_16a5_1601, 0}; +#undef pci_ss_info_16a5_1601 +#define pci_ss_info_16a5_1601 pci_ss_info_1260_3873_16a5_1601 +static const pciSubsystemInfo pci_ss_info_1260_3873_1737_3874 = + {0x1737, 0x3874, pci_subsys_1260_3873_1737_3874, 0}; +#undef pci_ss_info_1737_3874 +#define pci_ss_info_1737_3874 pci_ss_info_1260_3873_1737_3874 +#endif +static const pciSubsystemInfo pci_ss_info_1260_3873_8086_2513 = + {0x8086, 0x2513, pci_subsys_1260_3873_8086_2513, 0}; +#undef pci_ss_info_8086_2513 +#define pci_ss_info_8086_2513 pci_ss_info_1260_3873_8086_2513 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1260_3886_17cf_0037 = + {0x17cf, 0x0037, pci_subsys_1260_3886_17cf_0037, 0}; +#undef pci_ss_info_17cf_0037 +#define pci_ss_info_17cf_0037 pci_ss_info_1260_3886_17cf_0037 +static const pciSubsystemInfo pci_ss_info_1260_3890_10b8_2802 = + {0x10b8, 0x2802, pci_subsys_1260_3890_10b8_2802, 0}; +#undef pci_ss_info_10b8_2802 +#define pci_ss_info_10b8_2802 pci_ss_info_1260_3890_10b8_2802 +static const pciSubsystemInfo pci_ss_info_1260_3890_10b8_2835 = + {0x10b8, 0x2835, pci_subsys_1260_3890_10b8_2835, 0}; +#undef pci_ss_info_10b8_2835 +#define pci_ss_info_10b8_2835 pci_ss_info_1260_3890_10b8_2835 +static const pciSubsystemInfo pci_ss_info_1260_3890_10b8_a835 = + {0x10b8, 0xa835, pci_subsys_1260_3890_10b8_a835, 0}; +#undef pci_ss_info_10b8_a835 +#define pci_ss_info_10b8_a835 pci_ss_info_1260_3890_10b8_a835 +static const pciSubsystemInfo pci_ss_info_1260_3890_1113_4203 = + {0x1113, 0x4203, pci_subsys_1260_3890_1113_4203, 0}; +#undef pci_ss_info_1113_4203 +#define pci_ss_info_1113_4203 pci_ss_info_1260_3890_1113_4203 +static const pciSubsystemInfo pci_ss_info_1260_3890_1113_ee03 = + {0x1113, 0xee03, pci_subsys_1260_3890_1113_ee03, 0}; +#undef pci_ss_info_1113_ee03 +#define pci_ss_info_1113_ee03 pci_ss_info_1260_3890_1113_ee03 +static const pciSubsystemInfo pci_ss_info_1260_3890_1113_ee08 = + {0x1113, 0xee08, pci_subsys_1260_3890_1113_ee08, 0}; +#undef pci_ss_info_1113_ee08 +#define pci_ss_info_1113_ee08 pci_ss_info_1260_3890_1113_ee08 +static const pciSubsystemInfo pci_ss_info_1260_3890_1186_3202 = + {0x1186, 0x3202, pci_subsys_1260_3890_1186_3202, 0}; +#undef pci_ss_info_1186_3202 +#define pci_ss_info_1186_3202 pci_ss_info_1260_3890_1186_3202 +static const pciSubsystemInfo pci_ss_info_1260_3890_1259_c104 = + {0x1259, 0xc104, pci_subsys_1260_3890_1259_c104, 0}; +#undef pci_ss_info_1259_c104 +#define pci_ss_info_1259_c104 pci_ss_info_1260_3890_1259_c104 +static const pciSubsystemInfo pci_ss_info_1260_3890_1260_0000 = + {0x1260, 0x0000, pci_subsys_1260_3890_1260_0000, 0}; +#undef pci_ss_info_1260_0000 +#define pci_ss_info_1260_0000 pci_ss_info_1260_3890_1260_0000 +static const pciSubsystemInfo pci_ss_info_1260_3890_1385_4800 = + {0x1385, 0x4800, pci_subsys_1260_3890_1385_4800, 0}; +#undef pci_ss_info_1385_4800 +#define pci_ss_info_1385_4800 pci_ss_info_1260_3890_1385_4800 +static const pciSubsystemInfo pci_ss_info_1260_3890_16a5_1605 = + {0x16a5, 0x1605, pci_subsys_1260_3890_16a5_1605, 0}; +#undef pci_ss_info_16a5_1605 +#define pci_ss_info_16a5_1605 pci_ss_info_1260_3890_16a5_1605 +static const pciSubsystemInfo pci_ss_info_1260_3890_17cf_0014 = + {0x17cf, 0x0014, pci_subsys_1260_3890_17cf_0014, 0}; +#undef pci_ss_info_17cf_0014 +#define pci_ss_info_17cf_0014 pci_ss_info_1260_3890_17cf_0014 +static const pciSubsystemInfo pci_ss_info_1260_3890_17cf_0020 = + {0x17cf, 0x0020, pci_subsys_1260_3890_17cf_0020, 0}; +#undef pci_ss_info_17cf_0020 +#define pci_ss_info_17cf_0020 pci_ss_info_1260_3890_17cf_0020 +static const pciSubsystemInfo pci_ss_info_1260_ffff_1260_0000 = + {0x1260, 0x0000, pci_subsys_1260_ffff_1260_0000, 0}; +#undef pci_ss_info_1260_0000 +#define pci_ss_info_1260_0000 pci_ss_info_1260_ffff_1260_0000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1266_1910_1266_1910 = + {0x1266, 0x1910, pci_subsys_1266_1910_1266_1910, 0}; +#undef pci_ss_info_1266_1910 +#define pci_ss_info_1266_1910 pci_ss_info_1266_1910_1266_1910 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_0e11_0024 = + {0x0e11, 0x0024, pci_subsys_1274_1371_0e11_0024, 0}; +#undef pci_ss_info_0e11_0024 +#define pci_ss_info_0e11_0024 pci_ss_info_1274_1371_0e11_0024 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_0e11_b1a7 = + {0x0e11, 0xb1a7, pci_subsys_1274_1371_0e11_b1a7, 0}; +#undef pci_ss_info_0e11_b1a7 +#define pci_ss_info_0e11_b1a7 pci_ss_info_1274_1371_0e11_b1a7 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_1033_80ac = + {0x1033, 0x80ac, pci_subsys_1274_1371_1033_80ac, 0}; +#undef pci_ss_info_1033_80ac +#define pci_ss_info_1033_80ac pci_ss_info_1274_1371_1033_80ac +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1274_1371_1042_1854 = + {0x1042, 0x1854, pci_subsys_1274_1371_1042_1854, 0}; +#undef pci_ss_info_1042_1854 +#define pci_ss_info_1042_1854 pci_ss_info_1274_1371_1042_1854 +static const pciSubsystemInfo pci_ss_info_1274_1371_107b_8054 = + {0x107b, 0x8054, pci_subsys_1274_1371_107b_8054, 0}; +#undef pci_ss_info_107b_8054 +#define pci_ss_info_107b_8054 pci_ss_info_1274_1371_107b_8054 +static const pciSubsystemInfo pci_ss_info_1274_1371_1274_1371 = + {0x1274, 0x1371, pci_subsys_1274_1371_1274_1371, 0}; +#undef pci_ss_info_1274_1371 +#define pci_ss_info_1274_1371 pci_ss_info_1274_1371_1274_1371 +static const pciSubsystemInfo pci_ss_info_1274_1371_1274_8001 = + {0x1274, 0x8001, pci_subsys_1274_1371_1274_8001, 0}; +#undef pci_ss_info_1274_8001 +#define pci_ss_info_1274_8001 pci_ss_info_1274_1371_1274_8001 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6470 = + {0x1462, 0x6470, pci_subsys_1274_1371_1462_6470, 0}; +#undef pci_ss_info_1462_6470 +#define pci_ss_info_1462_6470 pci_ss_info_1274_1371_1462_6470 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6560 = + {0x1462, 0x6560, pci_subsys_1274_1371_1462_6560, 0}; +#undef pci_ss_info_1462_6560 +#define pci_ss_info_1462_6560 pci_ss_info_1274_1371_1462_6560 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6630 = + {0x1462, 0x6630, pci_subsys_1274_1371_1462_6630, 0}; +#undef pci_ss_info_1462_6630 +#define pci_ss_info_1462_6630 pci_ss_info_1274_1371_1462_6630 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6631 = + {0x1462, 0x6631, pci_subsys_1274_1371_1462_6631, 0}; +#undef pci_ss_info_1462_6631 +#define pci_ss_info_1462_6631 pci_ss_info_1274_1371_1462_6631 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6632 = + {0x1462, 0x6632, pci_subsys_1274_1371_1462_6632, 0}; +#undef pci_ss_info_1462_6632 +#define pci_ss_info_1462_6632 pci_ss_info_1274_1371_1462_6632 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6633 = + {0x1462, 0x6633, pci_subsys_1274_1371_1462_6633, 0}; +#undef pci_ss_info_1462_6633 +#define pci_ss_info_1462_6633 pci_ss_info_1274_1371_1462_6633 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6820 = + {0x1462, 0x6820, pci_subsys_1274_1371_1462_6820, 0}; +#undef pci_ss_info_1462_6820 +#define pci_ss_info_1462_6820 pci_ss_info_1274_1371_1462_6820 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6822 = + {0x1462, 0x6822, pci_subsys_1274_1371_1462_6822, 0}; +#undef pci_ss_info_1462_6822 +#define pci_ss_info_1462_6822 pci_ss_info_1274_1371_1462_6822 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6830 = + {0x1462, 0x6830, pci_subsys_1274_1371_1462_6830, 0}; +#undef pci_ss_info_1462_6830 +#define pci_ss_info_1462_6830 pci_ss_info_1274_1371_1462_6830 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6880 = + {0x1462, 0x6880, pci_subsys_1274_1371_1462_6880, 0}; +#undef pci_ss_info_1462_6880 +#define pci_ss_info_1462_6880 pci_ss_info_1274_1371_1462_6880 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6900 = + {0x1462, 0x6900, pci_subsys_1274_1371_1462_6900, 0}; +#undef pci_ss_info_1462_6900 +#define pci_ss_info_1462_6900 pci_ss_info_1274_1371_1462_6900 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6910 = + {0x1462, 0x6910, pci_subsys_1274_1371_1462_6910, 0}; +#undef pci_ss_info_1462_6910 +#define pci_ss_info_1462_6910 pci_ss_info_1274_1371_1462_6910 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6930 = + {0x1462, 0x6930, pci_subsys_1274_1371_1462_6930, 0}; +#undef pci_ss_info_1462_6930 +#define pci_ss_info_1462_6930 pci_ss_info_1274_1371_1462_6930 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6990 = + {0x1462, 0x6990, pci_subsys_1274_1371_1462_6990, 0}; +#undef pci_ss_info_1462_6990 +#define pci_ss_info_1462_6990 pci_ss_info_1274_1371_1462_6990 +static const pciSubsystemInfo pci_ss_info_1274_1371_1462_6991 = + {0x1462, 0x6991, pci_subsys_1274_1371_1462_6991, 0}; +#undef pci_ss_info_1462_6991 +#define pci_ss_info_1462_6991 pci_ss_info_1274_1371_1462_6991 +static const pciSubsystemInfo pci_ss_info_1274_1371_14a4_2077 = + {0x14a4, 0x2077, pci_subsys_1274_1371_14a4_2077, 0}; +#undef pci_ss_info_14a4_2077 +#define pci_ss_info_14a4_2077 pci_ss_info_1274_1371_14a4_2077 +static const pciSubsystemInfo pci_ss_info_1274_1371_14a4_2105 = + {0x14a4, 0x2105, pci_subsys_1274_1371_14a4_2105, 0}; +#undef pci_ss_info_14a4_2105 +#define pci_ss_info_14a4_2105 pci_ss_info_1274_1371_14a4_2105 +static const pciSubsystemInfo pci_ss_info_1274_1371_14a4_2107 = + {0x14a4, 0x2107, pci_subsys_1274_1371_14a4_2107, 0}; +#undef pci_ss_info_14a4_2107 +#define pci_ss_info_14a4_2107 pci_ss_info_1274_1371_14a4_2107 +static const pciSubsystemInfo pci_ss_info_1274_1371_14a4_2172 = + {0x14a4, 0x2172, pci_subsys_1274_1371_14a4_2172, 0}; +#undef pci_ss_info_14a4_2172 +#define pci_ss_info_14a4_2172 pci_ss_info_1274_1371_14a4_2172 +static const pciSubsystemInfo pci_ss_info_1274_1371_1509_9902 = + {0x1509, 0x9902, pci_subsys_1274_1371_1509_9902, 0}; +#undef pci_ss_info_1509_9902 +#define pci_ss_info_1509_9902 pci_ss_info_1274_1371_1509_9902 +static const pciSubsystemInfo pci_ss_info_1274_1371_1509_9903 = + {0x1509, 0x9903, pci_subsys_1274_1371_1509_9903, 0}; +#undef pci_ss_info_1509_9903 +#define pci_ss_info_1509_9903 pci_ss_info_1274_1371_1509_9903 +static const pciSubsystemInfo pci_ss_info_1274_1371_1509_9904 = + {0x1509, 0x9904, pci_subsys_1274_1371_1509_9904, 0}; +#undef pci_ss_info_1509_9904 +#define pci_ss_info_1509_9904 pci_ss_info_1274_1371_1509_9904 +static const pciSubsystemInfo pci_ss_info_1274_1371_1509_9905 = + {0x1509, 0x9905, pci_subsys_1274_1371_1509_9905, 0}; +#undef pci_ss_info_1509_9905 +#define pci_ss_info_1509_9905 pci_ss_info_1274_1371_1509_9905 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8801 = + {0x152d, 0x8801, pci_subsys_1274_1371_152d_8801, 0}; +#undef pci_ss_info_152d_8801 +#define pci_ss_info_152d_8801 pci_ss_info_1274_1371_152d_8801 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8802 = + {0x152d, 0x8802, pci_subsys_1274_1371_152d_8802, 0}; +#undef pci_ss_info_152d_8802 +#define pci_ss_info_152d_8802 pci_ss_info_1274_1371_152d_8802 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8803 = + {0x152d, 0x8803, pci_subsys_1274_1371_152d_8803, 0}; +#undef pci_ss_info_152d_8803 +#define pci_ss_info_152d_8803 pci_ss_info_1274_1371_152d_8803 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8804 = + {0x152d, 0x8804, pci_subsys_1274_1371_152d_8804, 0}; +#undef pci_ss_info_152d_8804 +#define pci_ss_info_152d_8804 pci_ss_info_1274_1371_152d_8804 +static const pciSubsystemInfo pci_ss_info_1274_1371_152d_8805 = + {0x152d, 0x8805, pci_subsys_1274_1371_152d_8805, 0}; +#undef pci_ss_info_152d_8805 +#define pci_ss_info_152d_8805 pci_ss_info_1274_1371_152d_8805 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_2001 = + {0x270f, 0x2001, pci_subsys_1274_1371_270f_2001, 0}; +#undef pci_ss_info_270f_2001 +#define pci_ss_info_270f_2001 pci_ss_info_1274_1371_270f_2001 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_2200 = + {0x270f, 0x2200, pci_subsys_1274_1371_270f_2200, 0}; +#undef pci_ss_info_270f_2200 +#define pci_ss_info_270f_2200 pci_ss_info_1274_1371_270f_2200 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_3000 = + {0x270f, 0x3000, pci_subsys_1274_1371_270f_3000, 0}; +#undef pci_ss_info_270f_3000 +#define pci_ss_info_270f_3000 pci_ss_info_1274_1371_270f_3000 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_3100 = + {0x270f, 0x3100, pci_subsys_1274_1371_270f_3100, 0}; +#undef pci_ss_info_270f_3100 +#define pci_ss_info_270f_3100 pci_ss_info_1274_1371_270f_3100 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_3102 = + {0x270f, 0x3102, pci_subsys_1274_1371_270f_3102, 0}; +#undef pci_ss_info_270f_3102 +#define pci_ss_info_270f_3102 pci_ss_info_1274_1371_270f_3102 +static const pciSubsystemInfo pci_ss_info_1274_1371_270f_7060 = + {0x270f, 0x7060, pci_subsys_1274_1371_270f_7060, 0}; +#undef pci_ss_info_270f_7060 +#define pci_ss_info_270f_7060 pci_ss_info_1274_1371_270f_7060 +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4249 = + {0x8086, 0x4249, pci_subsys_1274_1371_8086_4249, 0}; +#undef pci_ss_info_8086_4249 +#define pci_ss_info_8086_4249 pci_ss_info_1274_1371_8086_4249 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_424c = + {0x8086, 0x424c, pci_subsys_1274_1371_8086_424c, 0}; +#undef pci_ss_info_8086_424c +#define pci_ss_info_8086_424c pci_ss_info_1274_1371_8086_424c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_425a = + {0x8086, 0x425a, pci_subsys_1274_1371_8086_425a, 0}; +#undef pci_ss_info_8086_425a +#define pci_ss_info_8086_425a pci_ss_info_1274_1371_8086_425a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4341 = + {0x8086, 0x4341, pci_subsys_1274_1371_8086_4341, 0}; +#undef pci_ss_info_8086_4341 +#define pci_ss_info_8086_4341 pci_ss_info_1274_1371_8086_4341 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4343 = + {0x8086, 0x4343, pci_subsys_1274_1371_8086_4343, 0}; +#undef pci_ss_info_8086_4343 +#define pci_ss_info_8086_4343 pci_ss_info_1274_1371_8086_4343 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4541 = + {0x8086, 0x4541, pci_subsys_1274_1371_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_1274_1371_8086_4541 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4649 = + {0x8086, 0x4649, pci_subsys_1274_1371_8086_4649, 0}; +#undef pci_ss_info_8086_4649 +#define pci_ss_info_8086_4649 pci_ss_info_1274_1371_8086_4649 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_464a = + {0x8086, 0x464a, pci_subsys_1274_1371_8086_464a, 0}; +#undef pci_ss_info_8086_464a +#define pci_ss_info_8086_464a pci_ss_info_1274_1371_8086_464a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4d4f = + {0x8086, 0x4d4f, pci_subsys_1274_1371_8086_4d4f, 0}; +#undef pci_ss_info_8086_4d4f +#define pci_ss_info_8086_4d4f pci_ss_info_1274_1371_8086_4d4f +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_4f43 = + {0x8086, 0x4f43, pci_subsys_1274_1371_8086_4f43, 0}; +#undef pci_ss_info_8086_4f43 +#define pci_ss_info_8086_4f43 pci_ss_info_1274_1371_8086_4f43 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_5243 = + {0x8086, 0x5243, pci_subsys_1274_1371_8086_5243, 0}; +#undef pci_ss_info_8086_5243 +#define pci_ss_info_8086_5243 pci_ss_info_1274_1371_8086_5243 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_5352 = + {0x8086, 0x5352, pci_subsys_1274_1371_8086_5352, 0}; +#undef pci_ss_info_8086_5352 +#define pci_ss_info_8086_5352 pci_ss_info_1274_1371_8086_5352 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_5643 = + {0x8086, 0x5643, pci_subsys_1274_1371_8086_5643, 0}; +#undef pci_ss_info_8086_5643 +#define pci_ss_info_8086_5643 pci_ss_info_1274_1371_8086_5643 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1274_1371_8086_5753 = + {0x8086, 0x5753, pci_subsys_1274_1371_8086_5753, 0}; +#undef pci_ss_info_8086_5753 +#define pci_ss_info_8086_5753 pci_ss_info_1274_1371_8086_5753 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1274_5880_1274_2000 = + {0x1274, 0x2000, pci_subsys_1274_5880_1274_2000, 0}; +#undef pci_ss_info_1274_2000 +#define pci_ss_info_1274_2000 pci_ss_info_1274_5880_1274_2000 +static const pciSubsystemInfo pci_ss_info_1274_5880_1274_2003 = + {0x1274, 0x2003, pci_subsys_1274_5880_1274_2003, 0}; +#undef pci_ss_info_1274_2003 +#define pci_ss_info_1274_2003 pci_ss_info_1274_5880_1274_2003 +static const pciSubsystemInfo pci_ss_info_1274_5880_1274_5880 = + {0x1274, 0x5880, pci_subsys_1274_5880_1274_5880, 0}; +#undef pci_ss_info_1274_5880 +#define pci_ss_info_1274_5880 pci_ss_info_1274_5880_1274_5880 +static const pciSubsystemInfo pci_ss_info_1274_5880_1274_8001 = + {0x1274, 0x8001, pci_subsys_1274_5880_1274_8001, 0}; +#undef pci_ss_info_1274_8001 +#define pci_ss_info_1274_8001 pci_ss_info_1274_5880_1274_8001 +static const pciSubsystemInfo pci_ss_info_1274_5880_1458_a000 = + {0x1458, 0xa000, pci_subsys_1274_5880_1458_a000, 0}; +#undef pci_ss_info_1458_a000 +#define pci_ss_info_1458_a000 pci_ss_info_1274_5880_1458_a000 +static const pciSubsystemInfo pci_ss_info_1274_5880_1462_6880 = + {0x1462, 0x6880, pci_subsys_1274_5880_1462_6880, 0}; +#undef pci_ss_info_1462_6880 +#define pci_ss_info_1462_6880 pci_ss_info_1274_5880_1462_6880 +static const pciSubsystemInfo pci_ss_info_1274_5880_270f_2001 = + {0x270f, 0x2001, pci_subsys_1274_5880_270f_2001, 0}; +#undef pci_ss_info_270f_2001 +#define pci_ss_info_270f_2001 pci_ss_info_1274_5880_270f_2001 +static const pciSubsystemInfo pci_ss_info_1274_5880_270f_2200 = + {0x270f, 0x2200, pci_subsys_1274_5880_270f_2200, 0}; +#undef pci_ss_info_270f_2200 +#define pci_ss_info_270f_2200 pci_ss_info_1274_5880_270f_2200 +static const pciSubsystemInfo pci_ss_info_1274_5880_270f_7040 = + {0x270f, 0x7040, pci_subsys_1274_5880_270f_7040, 0}; +#undef pci_ss_info_270f_7040 +#define pci_ss_info_270f_7040 pci_ss_info_1274_5880_270f_7040 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_1002_1092_094c = + {0x1092, 0x094c, pci_subsys_127a_1002_1092_094c, 0}; +#undef pci_ss_info_1092_094c +#define pci_ss_info_1092_094c pci_ss_info_127a_1002_1092_094c +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4002 = + {0x122d, 0x4002, pci_subsys_127a_1002_122d_4002, 0}; +#undef pci_ss_info_122d_4002 +#define pci_ss_info_122d_4002 pci_ss_info_127a_1002_122d_4002 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4005 = + {0x122d, 0x4005, pci_subsys_127a_1002_122d_4005, 0}; +#undef pci_ss_info_122d_4005 +#define pci_ss_info_122d_4005 pci_ss_info_127a_1002_122d_4005 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4007 = + {0x122d, 0x4007, pci_subsys_127a_1002_122d_4007, 0}; +#undef pci_ss_info_122d_4007 +#define pci_ss_info_122d_4007 pci_ss_info_127a_1002_122d_4007 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4012 = + {0x122d, 0x4012, pci_subsys_127a_1002_122d_4012, 0}; +#undef pci_ss_info_122d_4012 +#define pci_ss_info_122d_4012 pci_ss_info_127a_1002_122d_4012 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4017 = + {0x122d, 0x4017, pci_subsys_127a_1002_122d_4017, 0}; +#undef pci_ss_info_122d_4017 +#define pci_ss_info_122d_4017 pci_ss_info_127a_1002_122d_4017 +static const pciSubsystemInfo pci_ss_info_127a_1002_122d_4018 = + {0x122d, 0x4018, pci_subsys_127a_1002_122d_4018, 0}; +#undef pci_ss_info_122d_4018 +#define pci_ss_info_122d_4018 pci_ss_info_127a_1002_122d_4018 +static const pciSubsystemInfo pci_ss_info_127a_1002_127a_1002 = + {0x127a, 0x1002, pci_subsys_127a_1002_127a_1002, 0}; +#undef pci_ss_info_127a_1002 +#define pci_ss_info_127a_1002 pci_ss_info_127a_1002_127a_1002 +#endif +static const pciSubsystemInfo pci_ss_info_127a_1003_0e11_b0bc = + {0x0e11, 0xb0bc, pci_subsys_127a_1003_0e11_b0bc, 0}; +#undef pci_ss_info_0e11_b0bc +#define pci_ss_info_0e11_b0bc pci_ss_info_127a_1003_0e11_b0bc +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_1003_0e11_b114 = + {0x0e11, 0xb114, pci_subsys_127a_1003_0e11_b114, 0}; +#undef pci_ss_info_0e11_b114 +#define pci_ss_info_0e11_b114 pci_ss_info_127a_1003_0e11_b114 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_1003_1033_802b = + {0x1033, 0x802b, pci_subsys_127a_1003_1033_802b, 0}; +#undef pci_ss_info_1033_802b +#define pci_ss_info_1033_802b pci_ss_info_127a_1003_1033_802b +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_127a_1003_13df_1003 = + {0x13df, 0x1003, pci_subsys_127a_1003_13df_1003, 0}; +#undef pci_ss_info_13df_1003 +#define pci_ss_info_13df_1003 pci_ss_info_127a_1003_13df_1003 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_0117 = + {0x13e0, 0x0117, pci_subsys_127a_1003_13e0_0117, 0}; +#undef pci_ss_info_13e0_0117 +#define pci_ss_info_13e0_0117 pci_ss_info_127a_1003_13e0_0117 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_0147 = + {0x13e0, 0x0147, pci_subsys_127a_1003_13e0_0147, 0}; +#undef pci_ss_info_13e0_0147 +#define pci_ss_info_13e0_0147 pci_ss_info_127a_1003_13e0_0147 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_0197 = + {0x13e0, 0x0197, pci_subsys_127a_1003_13e0_0197, 0}; +#undef pci_ss_info_13e0_0197 +#define pci_ss_info_13e0_0197 pci_ss_info_127a_1003_13e0_0197 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_01c7 = + {0x13e0, 0x01c7, pci_subsys_127a_1003_13e0_01c7, 0}; +#undef pci_ss_info_13e0_01c7 +#define pci_ss_info_13e0_01c7 pci_ss_info_127a_1003_13e0_01c7 +static const pciSubsystemInfo pci_ss_info_127a_1003_13e0_01f7 = + {0x13e0, 0x01f7, pci_subsys_127a_1003_13e0_01f7, 0}; +#undef pci_ss_info_13e0_01f7 +#define pci_ss_info_13e0_01f7 pci_ss_info_127a_1003_13e0_01f7 +static const pciSubsystemInfo pci_ss_info_127a_1003_1436_1003 = + {0x1436, 0x1003, pci_subsys_127a_1003_1436_1003, 0}; +#undef pci_ss_info_1436_1003 +#define pci_ss_info_1436_1003 pci_ss_info_127a_1003_1436_1003 +static const pciSubsystemInfo pci_ss_info_127a_1003_1436_1103 = + {0x1436, 0x1103, pci_subsys_127a_1003_1436_1103, 0}; +#undef pci_ss_info_1436_1103 +#define pci_ss_info_1436_1103 pci_ss_info_127a_1003_1436_1103 +static const pciSubsystemInfo pci_ss_info_127a_1003_1436_1602 = + {0x1436, 0x1602, pci_subsys_127a_1003_1436_1602, 0}; +#undef pci_ss_info_1436_1602 +#define pci_ss_info_1436_1602 pci_ss_info_127a_1003_1436_1602 +static const pciSubsystemInfo pci_ss_info_127a_1004_1048_1500 = + {0x1048, 0x1500, pci_subsys_127a_1004_1048_1500, 0}; +#undef pci_ss_info_1048_1500 +#define pci_ss_info_1048_1500 pci_ss_info_127a_1004_1048_1500 +static const pciSubsystemInfo pci_ss_info_127a_1004_10cf_1059 = + {0x10cf, 0x1059, pci_subsys_127a_1004_10cf_1059, 0}; +#undef pci_ss_info_10cf_1059 +#define pci_ss_info_10cf_1059 pci_ss_info_127a_1004_10cf_1059 +#endif +static const pciSubsystemInfo pci_ss_info_127a_1005_1005_127a = + {0x1005, 0x127a, pci_subsys_127a_1005_1005_127a, 0}; +#undef pci_ss_info_1005_127a +#define pci_ss_info_1005_127a pci_ss_info_127a_1005_1005_127a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_1005_1033_8029 = + {0x1033, 0x8029, pci_subsys_127a_1005_1033_8029, 0}; +#undef pci_ss_info_1033_8029 +#define pci_ss_info_1033_8029 pci_ss_info_127a_1005_1033_8029 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_1005_1033_8054 = + {0x1033, 0x8054, pci_subsys_127a_1005_1033_8054, 0}; +#undef pci_ss_info_1033_8054 +#define pci_ss_info_1033_8054 pci_ss_info_127a_1005_1033_8054 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_127a_1005_10cf_103c = + {0x10cf, 0x103c, pci_subsys_127a_1005_10cf_103c, 0}; +#undef pci_ss_info_10cf_103c +#define pci_ss_info_10cf_103c pci_ss_info_127a_1005_10cf_103c +static const pciSubsystemInfo pci_ss_info_127a_1005_10cf_1055 = + {0x10cf, 0x1055, pci_subsys_127a_1005_10cf_1055, 0}; +#undef pci_ss_info_10cf_1055 +#define pci_ss_info_10cf_1055 pci_ss_info_127a_1005_10cf_1055 +static const pciSubsystemInfo pci_ss_info_127a_1005_10cf_1056 = + {0x10cf, 0x1056, pci_subsys_127a_1005_10cf_1056, 0}; +#undef pci_ss_info_10cf_1056 +#define pci_ss_info_10cf_1056 pci_ss_info_127a_1005_10cf_1056 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4003 = + {0x122d, 0x4003, pci_subsys_127a_1005_122d_4003, 0}; +#undef pci_ss_info_122d_4003 +#define pci_ss_info_122d_4003 pci_ss_info_127a_1005_122d_4003 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4006 = + {0x122d, 0x4006, pci_subsys_127a_1005_122d_4006, 0}; +#undef pci_ss_info_122d_4006 +#define pci_ss_info_122d_4006 pci_ss_info_127a_1005_122d_4006 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4008 = + {0x122d, 0x4008, pci_subsys_127a_1005_122d_4008, 0}; +#undef pci_ss_info_122d_4008 +#define pci_ss_info_122d_4008 pci_ss_info_127a_1005_122d_4008 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4009 = + {0x122d, 0x4009, pci_subsys_127a_1005_122d_4009, 0}; +#undef pci_ss_info_122d_4009 +#define pci_ss_info_122d_4009 pci_ss_info_127a_1005_122d_4009 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4010 = + {0x122d, 0x4010, pci_subsys_127a_1005_122d_4010, 0}; +#undef pci_ss_info_122d_4010 +#define pci_ss_info_122d_4010 pci_ss_info_127a_1005_122d_4010 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4011 = + {0x122d, 0x4011, pci_subsys_127a_1005_122d_4011, 0}; +#undef pci_ss_info_122d_4011 +#define pci_ss_info_122d_4011 pci_ss_info_127a_1005_122d_4011 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4013 = + {0x122d, 0x4013, pci_subsys_127a_1005_122d_4013, 0}; +#undef pci_ss_info_122d_4013 +#define pci_ss_info_122d_4013 pci_ss_info_127a_1005_122d_4013 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4015 = + {0x122d, 0x4015, pci_subsys_127a_1005_122d_4015, 0}; +#undef pci_ss_info_122d_4015 +#define pci_ss_info_122d_4015 pci_ss_info_127a_1005_122d_4015 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4016 = + {0x122d, 0x4016, pci_subsys_127a_1005_122d_4016, 0}; +#undef pci_ss_info_122d_4016 +#define pci_ss_info_122d_4016 pci_ss_info_127a_1005_122d_4016 +static const pciSubsystemInfo pci_ss_info_127a_1005_122d_4019 = + {0x122d, 0x4019, pci_subsys_127a_1005_122d_4019, 0}; +#undef pci_ss_info_122d_4019 +#define pci_ss_info_122d_4019 pci_ss_info_127a_1005_122d_4019 +static const pciSubsystemInfo pci_ss_info_127a_1005_13df_1005 = + {0x13df, 0x1005, pci_subsys_127a_1005_13df_1005, 0}; +#undef pci_ss_info_13df_1005 +#define pci_ss_info_13df_1005 pci_ss_info_127a_1005_13df_1005 +static const pciSubsystemInfo pci_ss_info_127a_1005_13e0_0187 = + {0x13e0, 0x0187, pci_subsys_127a_1005_13e0_0187, 0}; +#undef pci_ss_info_13e0_0187 +#define pci_ss_info_13e0_0187 pci_ss_info_127a_1005_13e0_0187 +static const pciSubsystemInfo pci_ss_info_127a_1005_13e0_01a7 = + {0x13e0, 0x01a7, pci_subsys_127a_1005_13e0_01a7, 0}; +#undef pci_ss_info_13e0_01a7 +#define pci_ss_info_13e0_01a7 pci_ss_info_127a_1005_13e0_01a7 +static const pciSubsystemInfo pci_ss_info_127a_1005_13e0_01b7 = + {0x13e0, 0x01b7, pci_subsys_127a_1005_13e0_01b7, 0}; +#undef pci_ss_info_13e0_01b7 +#define pci_ss_info_13e0_01b7 pci_ss_info_127a_1005_13e0_01b7 +static const pciSubsystemInfo pci_ss_info_127a_1005_13e0_01d7 = + {0x13e0, 0x01d7, pci_subsys_127a_1005_13e0_01d7, 0}; +#undef pci_ss_info_13e0_01d7 +#define pci_ss_info_13e0_01d7 pci_ss_info_127a_1005_13e0_01d7 +static const pciSubsystemInfo pci_ss_info_127a_1005_1436_1005 = + {0x1436, 0x1005, pci_subsys_127a_1005_1436_1005, 0}; +#undef pci_ss_info_1436_1005 +#define pci_ss_info_1436_1005 pci_ss_info_127a_1005_1436_1005 +static const pciSubsystemInfo pci_ss_info_127a_1005_1436_1105 = + {0x1436, 0x1105, pci_subsys_127a_1005_1436_1105, 0}; +#undef pci_ss_info_1436_1105 +#define pci_ss_info_1436_1105 pci_ss_info_127a_1005_1436_1105 +static const pciSubsystemInfo pci_ss_info_127a_1005_1437_1105 = + {0x1437, 0x1105, pci_subsys_127a_1005_1437_1105, 0}; +#undef pci_ss_info_1437_1105 +#define pci_ss_info_1437_1105 pci_ss_info_127a_1005_1437_1105 +static const pciSubsystemInfo pci_ss_info_127a_1022_1436_1303 = + {0x1436, 0x1303, pci_subsys_127a_1022_1436_1303, 0}; +#undef pci_ss_info_1436_1303 +#define pci_ss_info_1436_1303 pci_ss_info_127a_1022_1436_1303 +static const pciSubsystemInfo pci_ss_info_127a_1023_122d_4020 = + {0x122d, 0x4020, pci_subsys_127a_1023_122d_4020, 0}; +#undef pci_ss_info_122d_4020 +#define pci_ss_info_122d_4020 pci_ss_info_127a_1023_122d_4020 +static const pciSubsystemInfo pci_ss_info_127a_1023_122d_4023 = + {0x122d, 0x4023, pci_subsys_127a_1023_122d_4023, 0}; +#undef pci_ss_info_122d_4023 +#define pci_ss_info_122d_4023 pci_ss_info_127a_1023_122d_4023 +static const pciSubsystemInfo pci_ss_info_127a_1023_13e0_0247 = + {0x13e0, 0x0247, pci_subsys_127a_1023_13e0_0247, 0}; +#undef pci_ss_info_13e0_0247 +#define pci_ss_info_13e0_0247 pci_ss_info_127a_1023_13e0_0247 +static const pciSubsystemInfo pci_ss_info_127a_1023_13e0_0297 = + {0x13e0, 0x0297, pci_subsys_127a_1023_13e0_0297, 0}; +#undef pci_ss_info_13e0_0297 +#define pci_ss_info_13e0_0297 pci_ss_info_127a_1023_13e0_0297 +static const pciSubsystemInfo pci_ss_info_127a_1023_13e0_02c7 = + {0x13e0, 0x02c7, pci_subsys_127a_1023_13e0_02c7, 0}; +#undef pci_ss_info_13e0_02c7 +#define pci_ss_info_13e0_02c7 pci_ss_info_127a_1023_13e0_02c7 +static const pciSubsystemInfo pci_ss_info_127a_1023_1436_1203 = + {0x1436, 0x1203, pci_subsys_127a_1023_1436_1203, 0}; +#undef pci_ss_info_1436_1203 +#define pci_ss_info_1436_1203 pci_ss_info_127a_1023_1436_1203 +static const pciSubsystemInfo pci_ss_info_127a_1023_1436_1303 = + {0x1436, 0x1303, pci_subsys_127a_1023_1436_1303, 0}; +#undef pci_ss_info_1436_1303 +#define pci_ss_info_1436_1303 pci_ss_info_127a_1023_1436_1303 +static const pciSubsystemInfo pci_ss_info_127a_1025_10cf_106a = + {0x10cf, 0x106a, pci_subsys_127a_1025_10cf_106a, 0}; +#undef pci_ss_info_10cf_106a +#define pci_ss_info_10cf_106a pci_ss_info_127a_1025_10cf_106a +static const pciSubsystemInfo pci_ss_info_127a_1025_122d_4021 = + {0x122d, 0x4021, pci_subsys_127a_1025_122d_4021, 0}; +#undef pci_ss_info_122d_4021 +#define pci_ss_info_122d_4021 pci_ss_info_127a_1025_122d_4021 +static const pciSubsystemInfo pci_ss_info_127a_1025_122d_4022 = + {0x122d, 0x4022, pci_subsys_127a_1025_122d_4022, 0}; +#undef pci_ss_info_122d_4022 +#define pci_ss_info_122d_4022 pci_ss_info_127a_1025_122d_4022 +static const pciSubsystemInfo pci_ss_info_127a_1025_122d_4024 = + {0x122d, 0x4024, pci_subsys_127a_1025_122d_4024, 0}; +#undef pci_ss_info_122d_4024 +#define pci_ss_info_122d_4024 pci_ss_info_127a_1025_122d_4024 +static const pciSubsystemInfo pci_ss_info_127a_1025_122d_4025 = + {0x122d, 0x4025, pci_subsys_127a_1025_122d_4025, 0}; +#undef pci_ss_info_122d_4025 +#define pci_ss_info_122d_4025 pci_ss_info_127a_1025_122d_4025 +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8044 = + {0x104d, 0x8044, pci_subsys_127a_2005_104d_8044, 0}; +#undef pci_ss_info_104d_8044 +#define pci_ss_info_104d_8044 pci_ss_info_127a_2005_104d_8044 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8045 = + {0x104d, 0x8045, pci_subsys_127a_2005_104d_8045, 0}; +#undef pci_ss_info_104d_8045 +#define pci_ss_info_104d_8045 pci_ss_info_127a_2005_104d_8045 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8055 = + {0x104d, 0x8055, pci_subsys_127a_2005_104d_8055, 0}; +#undef pci_ss_info_104d_8055 +#define pci_ss_info_104d_8055 pci_ss_info_127a_2005_104d_8055 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8056 = + {0x104d, 0x8056, pci_subsys_127a_2005_104d_8056, 0}; +#undef pci_ss_info_104d_8056 +#define pci_ss_info_104d_8056 pci_ss_info_127a_2005_104d_8056 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_805a = + {0x104d, 0x805a, pci_subsys_127a_2005_104d_805a, 0}; +#undef pci_ss_info_104d_805a +#define pci_ss_info_104d_805a pci_ss_info_127a_2005_104d_805a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_805f = + {0x104d, 0x805f, pci_subsys_127a_2005_104d_805f, 0}; +#undef pci_ss_info_104d_805f +#define pci_ss_info_104d_805f pci_ss_info_127a_2005_104d_805f +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_127a_2005_104d_8074 = + {0x104d, 0x8074, pci_subsys_127a_2005_104d_8074, 0}; +#undef pci_ss_info_104d_8074 +#define pci_ss_info_104d_8074 pci_ss_info_127a_2005_104d_8074 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_127a_2013_1179_0001 = + {0x1179, 0x0001, pci_subsys_127a_2013_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_127a_2013_1179_0001 +static const pciSubsystemInfo pci_ss_info_127a_2013_1179_ff00 = + {0x1179, 0xff00, pci_subsys_127a_2013_1179_ff00, 0}; +#undef pci_ss_info_1179_ff00 +#define pci_ss_info_1179_ff00 pci_ss_info_127a_2013_1179_ff00 +static const pciSubsystemInfo pci_ss_info_127a_2014_10cf_1057 = + {0x10cf, 0x1057, pci_subsys_127a_2014_10cf_1057, 0}; +#undef pci_ss_info_10cf_1057 +#define pci_ss_info_10cf_1057 pci_ss_info_127a_2014_10cf_1057 +static const pciSubsystemInfo pci_ss_info_127a_2014_122d_4050 = + {0x122d, 0x4050, pci_subsys_127a_2014_122d_4050, 0}; +#undef pci_ss_info_122d_4050 +#define pci_ss_info_122d_4050 pci_ss_info_127a_2014_122d_4050 +static const pciSubsystemInfo pci_ss_info_127a_2014_122d_4055 = + {0x122d, 0x4055, pci_subsys_127a_2014_122d_4055, 0}; +#undef pci_ss_info_122d_4055 +#define pci_ss_info_122d_4055 pci_ss_info_127a_2014_122d_4055 +static const pciSubsystemInfo pci_ss_info_127a_2015_10cf_1063 = + {0x10cf, 0x1063, pci_subsys_127a_2015_10cf_1063, 0}; +#undef pci_ss_info_10cf_1063 +#define pci_ss_info_10cf_1063 pci_ss_info_127a_2015_10cf_1063 +static const pciSubsystemInfo pci_ss_info_127a_2015_10cf_1064 = + {0x10cf, 0x1064, pci_subsys_127a_2015_10cf_1064, 0}; +#undef pci_ss_info_10cf_1064 +#define pci_ss_info_10cf_1064 pci_ss_info_127a_2015_10cf_1064 +static const pciSubsystemInfo pci_ss_info_127a_2015_1468_2015 = + {0x1468, 0x2015, pci_subsys_127a_2015_1468_2015, 0}; +#undef pci_ss_info_1468_2015 +#define pci_ss_info_1468_2015 pci_ss_info_127a_2015_1468_2015 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4051 = + {0x122d, 0x4051, pci_subsys_127a_2016_122d_4051, 0}; +#undef pci_ss_info_122d_4051 +#define pci_ss_info_122d_4051 pci_ss_info_127a_2016_122d_4051 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4052 = + {0x122d, 0x4052, pci_subsys_127a_2016_122d_4052, 0}; +#undef pci_ss_info_122d_4052 +#define pci_ss_info_122d_4052 pci_ss_info_127a_2016_122d_4052 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4054 = + {0x122d, 0x4054, pci_subsys_127a_2016_122d_4054, 0}; +#undef pci_ss_info_122d_4054 +#define pci_ss_info_122d_4054 pci_ss_info_127a_2016_122d_4054 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4056 = + {0x122d, 0x4056, pci_subsys_127a_2016_122d_4056, 0}; +#undef pci_ss_info_122d_4056 +#define pci_ss_info_122d_4056 pci_ss_info_127a_2016_122d_4056 +static const pciSubsystemInfo pci_ss_info_127a_2016_122d_4057 = + {0x122d, 0x4057, pci_subsys_127a_2016_122d_4057, 0}; +#undef pci_ss_info_122d_4057 +#define pci_ss_info_122d_4057 pci_ss_info_127a_2016_122d_4057 +static const pciSubsystemInfo pci_ss_info_127a_4311_127a_4311 = + {0x127a, 0x4311, pci_subsys_127a_4311_127a_4311, 0}; +#undef pci_ss_info_127a_4311 +#define pci_ss_info_127a_4311 pci_ss_info_127a_4311_127a_4311 +static const pciSubsystemInfo pci_ss_info_127a_4311_13e0_0210 = + {0x13e0, 0x0210, pci_subsys_127a_4311_13e0_0210, 0}; +#undef pci_ss_info_13e0_0210 +#define pci_ss_info_13e0_0210 pci_ss_info_127a_4311_13e0_0210 +static const pciSubsystemInfo pci_ss_info_127a_4320_1235_4320 = + {0x1235, 0x4320, pci_subsys_127a_4320_1235_4320, 0}; +#undef pci_ss_info_1235_4320 +#define pci_ss_info_1235_4320 pci_ss_info_127a_4320_1235_4320 +static const pciSubsystemInfo pci_ss_info_127a_4321_1235_4321 = + {0x1235, 0x4321, pci_subsys_127a_4321_1235_4321, 0}; +#undef pci_ss_info_1235_4321 +#define pci_ss_info_1235_4321 pci_ss_info_127a_4321_1235_4321 +static const pciSubsystemInfo pci_ss_info_127a_4321_1235_4324 = + {0x1235, 0x4324, pci_subsys_127a_4321_1235_4324, 0}; +#undef pci_ss_info_1235_4324 +#define pci_ss_info_1235_4324 pci_ss_info_127a_4321_1235_4324 +static const pciSubsystemInfo pci_ss_info_127a_4321_13e0_0210 = + {0x13e0, 0x0210, pci_subsys_127a_4321_13e0_0210, 0}; +#undef pci_ss_info_13e0_0210 +#define pci_ss_info_13e0_0210 pci_ss_info_127a_4321_13e0_0210 +static const pciSubsystemInfo pci_ss_info_127a_4321_144d_2321 = + {0x144d, 0x2321, pci_subsys_127a_4321_144d_2321, 0}; +#undef pci_ss_info_144d_2321 +#define pci_ss_info_144d_2321 pci_ss_info_127a_4321_144d_2321 +static const pciSubsystemInfo pci_ss_info_127a_4322_1235_4322 = + {0x1235, 0x4322, pci_subsys_127a_4322_1235_4322, 0}; +#undef pci_ss_info_1235_4322 +#define pci_ss_info_1235_4322 pci_ss_info_127a_4322_1235_4322 +static const pciSubsystemInfo pci_ss_info_127a_8234_108d_0022 = + {0x108d, 0x0022, pci_subsys_127a_8234_108d_0022, 0}; +#undef pci_ss_info_108d_0022 +#define pci_ss_info_108d_0022 pci_ss_info_127a_8234_108d_0022 +static const pciSubsystemInfo pci_ss_info_127a_8234_108d_0027 = + {0x108d, 0x0027, pci_subsys_127a_8234_108d_0027, 0}; +#undef pci_ss_info_108d_0027 +#define pci_ss_info_108d_0027 pci_ss_info_127a_8234_108d_0027 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1283_8211_1043_8138 = + {0x1043, 0x8138, pci_subsys_1283_8211_1043_8138, 0}; +#undef pci_ss_info_1043_8138 +#define pci_ss_info_1043_8138 pci_ss_info_1283_8211_1043_8138 +static const pciSubsystemInfo pci_ss_info_1283_8212_1283_0001 = + {0x1283, 0x0001, pci_subsys_1283_8212_1283_0001, 0}; +#undef pci_ss_info_1283_0001 +#define pci_ss_info_1283_0001 pci_ss_info_1283_8212_1283_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12ae_0001_1014_0104 = + {0x1014, 0x0104, pci_subsys_12ae_0001_1014_0104, 0}; +#undef pci_ss_info_1014_0104 +#define pci_ss_info_1014_0104 pci_ss_info_12ae_0001_1014_0104 +static const pciSubsystemInfo pci_ss_info_12ae_0001_12ae_0001 = + {0x12ae, 0x0001, pci_subsys_12ae_0001_12ae_0001, 0}; +#undef pci_ss_info_12ae_0001 +#define pci_ss_info_12ae_0001 pci_ss_info_12ae_0001_12ae_0001 +static const pciSubsystemInfo pci_ss_info_12ae_0001_1410_0104 = + {0x1410, 0x0104, pci_subsys_12ae_0001_1410_0104, 0}; +#undef pci_ss_info_1410_0104 +#define pci_ss_info_1410_0104 pci_ss_info_12ae_0001_1410_0104 +static const pciSubsystemInfo pci_ss_info_12ae_0002_10a9_8002 = + {0x10a9, 0x8002, pci_subsys_12ae_0002_10a9_8002, 0}; +#undef pci_ss_info_10a9_8002 +#define pci_ss_info_10a9_8002 pci_ss_info_12ae_0002_10a9_8002 +static const pciSubsystemInfo pci_ss_info_12ae_0002_12ae_0002 = + {0x12ae, 0x0002, pci_subsys_12ae_0002_12ae_0002, 0}; +#undef pci_ss_info_12ae_0002 +#define pci_ss_info_12ae_0002 pci_ss_info_12ae_0002_12ae_0002 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_005c = + {0x12b9, 0x005c, pci_subsys_12b9_1006_12b9_005c, 0}; +#undef pci_ss_info_12b9_005c +#define pci_ss_info_12b9_005c pci_ss_info_12b9_1006_12b9_005c +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_005e = + {0x12b9, 0x005e, pci_subsys_12b9_1006_12b9_005e, 0}; +#undef pci_ss_info_12b9_005e +#define pci_ss_info_12b9_005e pci_ss_info_12b9_1006_12b9_005e +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0062 = + {0x12b9, 0x0062, pci_subsys_12b9_1006_12b9_0062, 0}; +#undef pci_ss_info_12b9_0062 +#define pci_ss_info_12b9_0062 pci_ss_info_12b9_1006_12b9_0062 +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0068 = + {0x12b9, 0x0068, pci_subsys_12b9_1006_12b9_0068, 0}; +#undef pci_ss_info_12b9_0068 +#define pci_ss_info_12b9_0068 pci_ss_info_12b9_1006_12b9_0068 +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_007a = + {0x12b9, 0x007a, pci_subsys_12b9_1006_12b9_007a, 0}; +#undef pci_ss_info_12b9_007a +#define pci_ss_info_12b9_007a pci_ss_info_12b9_1006_12b9_007a +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_007f = + {0x12b9, 0x007f, pci_subsys_12b9_1006_12b9_007f, 0}; +#undef pci_ss_info_12b9_007f +#define pci_ss_info_12b9_007f pci_ss_info_12b9_1006_12b9_007f +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0080 = + {0x12b9, 0x0080, pci_subsys_12b9_1006_12b9_0080, 0}; +#undef pci_ss_info_12b9_0080 +#define pci_ss_info_12b9_0080 pci_ss_info_12b9_1006_12b9_0080 +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0081 = + {0x12b9, 0x0081, pci_subsys_12b9_1006_12b9_0081, 0}; +#undef pci_ss_info_12b9_0081 +#define pci_ss_info_12b9_0081 pci_ss_info_12b9_1006_12b9_0081 +static const pciSubsystemInfo pci_ss_info_12b9_1006_12b9_0091 = + {0x12b9, 0x0091, pci_subsys_12b9_1006_12b9_0091, 0}; +#undef pci_ss_info_12b9_0091 +#define pci_ss_info_12b9_0091 pci_ss_info_12b9_1006_12b9_0091 +static const pciSubsystemInfo pci_ss_info_12b9_1007_12b9_00a3 = + {0x12b9, 0x00a3, pci_subsys_12b9_1007_12b9_00a3, 0}; +#undef pci_ss_info_12b9_00a3 +#define pci_ss_info_12b9_00a3 pci_ss_info_12b9_1007_12b9_00a3 +static const pciSubsystemInfo pci_ss_info_12b9_1007_12b9_00c4 = + {0x12b9, 0x00c4, pci_subsys_12b9_1007_12b9_00c4, 0}; +#undef pci_ss_info_12b9_00c4 +#define pci_ss_info_12b9_00c4 pci_ss_info_12b9_1007_12b9_00c4 +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00a2 = + {0x12b9, 0x00a2, pci_subsys_12b9_1008_12b9_00a2, 0}; +#undef pci_ss_info_12b9_00a2 +#define pci_ss_info_12b9_00a2 pci_ss_info_12b9_1008_12b9_00a2 +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00aa = + {0x12b9, 0x00aa, pci_subsys_12b9_1008_12b9_00aa, 0}; +#undef pci_ss_info_12b9_00aa +#define pci_ss_info_12b9_00aa pci_ss_info_12b9_1008_12b9_00aa +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00ab = + {0x12b9, 0x00ab, pci_subsys_12b9_1008_12b9_00ab, 0}; +#undef pci_ss_info_12b9_00ab +#define pci_ss_info_12b9_00ab pci_ss_info_12b9_1008_12b9_00ab +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00ac = + {0x12b9, 0x00ac, pci_subsys_12b9_1008_12b9_00ac, 0}; +#undef pci_ss_info_12b9_00ac +#define pci_ss_info_12b9_00ac pci_ss_info_12b9_1008_12b9_00ac +static const pciSubsystemInfo pci_ss_info_12b9_1008_12b9_00ad = + {0x12b9, 0x00ad, pci_subsys_12b9_1008_12b9_00ad, 0}; +#undef pci_ss_info_12b9_00ad +#define pci_ss_info_12b9_00ad pci_ss_info_12b9_1008_12b9_00ad +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12be_3042_12be_3042 = + {0x12be, 0x3042, pci_subsys_12be_3042_12be_3042, 0}; +#undef pci_ss_info_12be_3042 +#define pci_ss_info_12be_3042 pci_ss_info_12be_3042_12be_3042 +#endif +static const pciSubsystemInfo pci_ss_info_12d2_0018_1048_0c10 = + {0x1048, 0x0c10, pci_subsys_12d2_0018_1048_0c10, 0}; +#undef pci_ss_info_1048_0c10 +#define pci_ss_info_1048_0c10 pci_ss_info_12d2_0018_1048_0c10 +static const pciSubsystemInfo pci_ss_info_12d2_0018_107b_8030 = + {0x107b, 0x8030, pci_subsys_12d2_0018_107b_8030, 0}; +#undef pci_ss_info_107b_8030 +#define pci_ss_info_107b_8030 pci_ss_info_12d2_0018_107b_8030 +static const pciSubsystemInfo pci_ss_info_12d2_0018_1092_0350 = + {0x1092, 0x0350, pci_subsys_12d2_0018_1092_0350, 0}; +#undef pci_ss_info_1092_0350 +#define pci_ss_info_1092_0350 pci_ss_info_12d2_0018_1092_0350 +static const pciSubsystemInfo pci_ss_info_12d2_0018_1092_1092 = + {0x1092, 0x1092, pci_subsys_12d2_0018_1092_1092, 0}; +#undef pci_ss_info_1092_1092 +#define pci_ss_info_1092_1092 pci_ss_info_12d2_0018_1092_1092 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b1b = + {0x10b4, 0x1b1b, pci_subsys_12d2_0018_10b4_1b1b, 0}; +#undef pci_ss_info_10b4_1b1b +#define pci_ss_info_10b4_1b1b pci_ss_info_12d2_0018_10b4_1b1b +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b1d = + {0x10b4, 0x1b1d, pci_subsys_12d2_0018_10b4_1b1d, 0}; +#undef pci_ss_info_10b4_1b1d +#define pci_ss_info_10b4_1b1d pci_ss_info_12d2_0018_10b4_1b1d +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b1e = + {0x10b4, 0x1b1e, pci_subsys_12d2_0018_10b4_1b1e, 0}; +#undef pci_ss_info_10b4_1b1e +#define pci_ss_info_10b4_1b1e pci_ss_info_12d2_0018_10b4_1b1e +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b20 = + {0x10b4, 0x1b20, pci_subsys_12d2_0018_10b4_1b20, 0}; +#undef pci_ss_info_10b4_1b20 +#define pci_ss_info_10b4_1b20 pci_ss_info_12d2_0018_10b4_1b20 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b21 = + {0x10b4, 0x1b21, pci_subsys_12d2_0018_10b4_1b21, 0}; +#undef pci_ss_info_10b4_1b21 +#define pci_ss_info_10b4_1b21 pci_ss_info_12d2_0018_10b4_1b21 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b22 = + {0x10b4, 0x1b22, pci_subsys_12d2_0018_10b4_1b22, 0}; +#undef pci_ss_info_10b4_1b22 +#define pci_ss_info_10b4_1b22 pci_ss_info_12d2_0018_10b4_1b22 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b23 = + {0x10b4, 0x1b23, pci_subsys_12d2_0018_10b4_1b23, 0}; +#undef pci_ss_info_10b4_1b23 +#define pci_ss_info_10b4_1b23 pci_ss_info_12d2_0018_10b4_1b23 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b27 = + {0x10b4, 0x1b27, pci_subsys_12d2_0018_10b4_1b27, 0}; +#undef pci_ss_info_10b4_1b27 +#define pci_ss_info_10b4_1b27 pci_ss_info_12d2_0018_10b4_1b27 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_1b88 = + {0x10b4, 0x1b88, pci_subsys_12d2_0018_10b4_1b88, 0}; +#undef pci_ss_info_10b4_1b88 +#define pci_ss_info_10b4_1b88 pci_ss_info_12d2_0018_10b4_1b88 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_222a = + {0x10b4, 0x222a, pci_subsys_12d2_0018_10b4_222a, 0}; +#undef pci_ss_info_10b4_222a +#define pci_ss_info_10b4_222a pci_ss_info_12d2_0018_10b4_222a +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_2230 = + {0x10b4, 0x2230, pci_subsys_12d2_0018_10b4_2230, 0}; +#undef pci_ss_info_10b4_2230 +#define pci_ss_info_10b4_2230 pci_ss_info_12d2_0018_10b4_2230 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_2232 = + {0x10b4, 0x2232, pci_subsys_12d2_0018_10b4_2232, 0}; +#undef pci_ss_info_10b4_2232 +#define pci_ss_info_10b4_2232 pci_ss_info_12d2_0018_10b4_2232 +static const pciSubsystemInfo pci_ss_info_12d2_0018_10b4_2235 = + {0x10b4, 0x2235, pci_subsys_12d2_0018_10b4_2235, 0}; +#undef pci_ss_info_10b4_2235 +#define pci_ss_info_10b4_2235 pci_ss_info_12d2_0018_10b4_2235 +static const pciSubsystemInfo pci_ss_info_12d2_0018_2a15_54a3 = + {0x2a15, 0x54a3, pci_subsys_12d2_0018_2a15_54a3, 0}; +#undef pci_ss_info_2a15_54a3 +#define pci_ss_info_2a15_54a3 pci_ss_info_12d2_0018_2a15_54a3 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12d9_1078_12d9_000d = + {0x12d9, 0x000d, pci_subsys_12d9_1078_12d9_000d, 0}; +#undef pci_ss_info_12d9_000d +#define pci_ss_info_12d9_000d pci_ss_info_12d9_1078_12d9_000d +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_104d_8036 = + {0x104d, 0x8036, pci_subsys_12eb_0001_104d_8036, 0}; +#undef pci_ss_info_104d_8036 +#define pci_ss_info_104d_8036 pci_ss_info_12eb_0001_104d_8036 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_1092_2000 = + {0x1092, 0x2000, pci_subsys_12eb_0001_1092_2000, 0}; +#undef pci_ss_info_1092_2000 +#define pci_ss_info_1092_2000 pci_ss_info_12eb_0001_1092_2000 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_1092_2100 = + {0x1092, 0x2100, pci_subsys_12eb_0001_1092_2100, 0}; +#undef pci_ss_info_1092_2100 +#define pci_ss_info_1092_2100 pci_ss_info_12eb_0001_1092_2100 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_1092_2110 = + {0x1092, 0x2110, pci_subsys_12eb_0001_1092_2110, 0}; +#undef pci_ss_info_1092_2110 +#define pci_ss_info_1092_2110 pci_ss_info_12eb_0001_1092_2110 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0001_1092_2200 = + {0x1092, 0x2200, pci_subsys_12eb_0001_1092_2200, 0}; +#undef pci_ss_info_1092_2200 +#define pci_ss_info_1092_2200 pci_ss_info_12eb_0001_1092_2200 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12eb_0001_122d_1002 = + {0x122d, 0x1002, pci_subsys_12eb_0001_122d_1002, 0}; +#undef pci_ss_info_122d_1002 +#define pci_ss_info_122d_1002 pci_ss_info_12eb_0001_122d_1002 +static const pciSubsystemInfo pci_ss_info_12eb_0001_12eb_0001 = + {0x12eb, 0x0001, pci_subsys_12eb_0001_12eb_0001, 0}; +#undef pci_ss_info_12eb_0001 +#define pci_ss_info_12eb_0001 pci_ss_info_12eb_0001_12eb_0001 +static const pciSubsystemInfo pci_ss_info_12eb_0001_5053_3355 = + {0x5053, 0x3355, pci_subsys_12eb_0001_5053_3355, 0}; +#undef pci_ss_info_5053_3355 +#define pci_ss_info_5053_3355 pci_ss_info_12eb_0001_5053_3355 +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_104d_8049 = + {0x104d, 0x8049, pci_subsys_12eb_0002_104d_8049, 0}; +#undef pci_ss_info_104d_8049 +#define pci_ss_info_104d_8049 pci_ss_info_12eb_0002_104d_8049 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_104d_807b = + {0x104d, 0x807b, pci_subsys_12eb_0002_104d_807b, 0}; +#undef pci_ss_info_104d_807b +#define pci_ss_info_104d_807b pci_ss_info_12eb_0002_104d_807b +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3000 = + {0x1092, 0x3000, pci_subsys_12eb_0002_1092_3000, 0}; +#undef pci_ss_info_1092_3000 +#define pci_ss_info_1092_3000 pci_ss_info_12eb_0002_1092_3000 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3001 = + {0x1092, 0x3001, pci_subsys_12eb_0002_1092_3001, 0}; +#undef pci_ss_info_1092_3001 +#define pci_ss_info_1092_3001 pci_ss_info_12eb_0002_1092_3001 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3002 = + {0x1092, 0x3002, pci_subsys_12eb_0002_1092_3002, 0}; +#undef pci_ss_info_1092_3002 +#define pci_ss_info_1092_3002 pci_ss_info_12eb_0002_1092_3002 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3003 = + {0x1092, 0x3003, pci_subsys_12eb_0002_1092_3003, 0}; +#undef pci_ss_info_1092_3003 +#define pci_ss_info_1092_3003 pci_ss_info_12eb_0002_1092_3003 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0002_1092_3004 = + {0x1092, 0x3004, pci_subsys_12eb_0002_1092_3004, 0}; +#undef pci_ss_info_1092_3004 +#define pci_ss_info_1092_3004 pci_ss_info_12eb_0002_1092_3004 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12eb_0002_12eb_0002 = + {0x12eb, 0x0002, pci_subsys_12eb_0002_12eb_0002, 0}; +#undef pci_ss_info_12eb_0002 +#define pci_ss_info_12eb_0002 pci_ss_info_12eb_0002_12eb_0002 +static const pciSubsystemInfo pci_ss_info_12eb_0002_12eb_0088 = + {0x12eb, 0x0088, pci_subsys_12eb_0002_12eb_0088, 0}; +#undef pci_ss_info_12eb_0088 +#define pci_ss_info_12eb_0088 pci_ss_info_12eb_0002_12eb_0088 +static const pciSubsystemInfo pci_ss_info_12eb_0002_144d_3510 = + {0x144d, 0x3510, pci_subsys_12eb_0002_144d_3510, 0}; +#undef pci_ss_info_144d_3510 +#define pci_ss_info_144d_3510 pci_ss_info_12eb_0002_144d_3510 +static const pciSubsystemInfo pci_ss_info_12eb_0002_5053_3356 = + {0x5053, 0x3356, pci_subsys_12eb_0002_5053_3356, 0}; +#undef pci_ss_info_5053_3356 +#define pci_ss_info_5053_3356 pci_ss_info_12eb_0002_5053_3356 +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0003_104d_8049 = + {0x104d, 0x8049, pci_subsys_12eb_0003_104d_8049, 0}; +#undef pci_ss_info_104d_8049 +#define pci_ss_info_104d_8049 pci_ss_info_12eb_0003_104d_8049 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_12eb_0003_104d_8077 = + {0x104d, 0x8077, pci_subsys_12eb_0003_104d_8077, 0}; +#undef pci_ss_info_104d_8077 +#define pci_ss_info_104d_8077 pci_ss_info_12eb_0003_104d_8077 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_12eb_0003_109f_1000 = + {0x109f, 0x1000, pci_subsys_12eb_0003_109f_1000, 0}; +#undef pci_ss_info_109f_1000 +#define pci_ss_info_109f_1000 pci_ss_info_12eb_0003_109f_1000 +static const pciSubsystemInfo pci_ss_info_12eb_0003_12eb_0003 = + {0x12eb, 0x0003, pci_subsys_12eb_0003_12eb_0003, 0}; +#undef pci_ss_info_12eb_0003 +#define pci_ss_info_12eb_0003 pci_ss_info_12eb_0003_12eb_0003 +static const pciSubsystemInfo pci_ss_info_12eb_0003_1462_6780 = + {0x1462, 0x6780, pci_subsys_12eb_0003_1462_6780, 0}; +#undef pci_ss_info_1462_6780 +#define pci_ss_info_1462_6780 pci_ss_info_12eb_0003_1462_6780 +static const pciSubsystemInfo pci_ss_info_12eb_0003_14a4_2073 = + {0x14a4, 0x2073, pci_subsys_12eb_0003_14a4_2073, 0}; +#undef pci_ss_info_14a4_2073 +#define pci_ss_info_14a4_2073 pci_ss_info_12eb_0003_14a4_2073 +static const pciSubsystemInfo pci_ss_info_12eb_0003_14a4_2091 = + {0x14a4, 0x2091, pci_subsys_12eb_0003_14a4_2091, 0}; +#undef pci_ss_info_14a4_2091 +#define pci_ss_info_14a4_2091 pci_ss_info_12eb_0003_14a4_2091 +static const pciSubsystemInfo pci_ss_info_12eb_0003_14a4_2104 = + {0x14a4, 0x2104, pci_subsys_12eb_0003_14a4_2104, 0}; +#undef pci_ss_info_14a4_2104 +#define pci_ss_info_14a4_2104 pci_ss_info_12eb_0003_14a4_2104 +static const pciSubsystemInfo pci_ss_info_12eb_0003_14a4_2106 = + {0x14a4, 0x2106, pci_subsys_12eb_0003_14a4_2106, 0}; +#undef pci_ss_info_14a4_2106 +#define pci_ss_info_14a4_2106 pci_ss_info_12eb_0003_14a4_2106 +static const pciSubsystemInfo pci_ss_info_12eb_8803_12eb_8803 = + {0x12eb, 0x8803, pci_subsys_12eb_8803_12eb_8803, 0}; +#undef pci_ss_info_12eb_8803 +#define pci_ss_info_12eb_8803 pci_ss_info_12eb_8803_12eb_8803 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1308_0001_1308_0001 = + {0x1308, 0x0001, pci_subsys_1308_0001_1308_0001, 0}; +#undef pci_ss_info_1308_0001 +#define pci_ss_info_1308_0001 pci_ss_info_1308_0001_1308_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1317_0985_1734_100c = + {0x1734, 0x100c, pci_subsys_1317_0985_1734_100c, 0}; +#undef pci_ss_info_1734_100c +#define pci_ss_info_1734_100c pci_ss_info_1317_0985_1734_100c +static const pciSubsystemInfo pci_ss_info_1317_8201_10b8_2635 = + {0x10b8, 0x2635, pci_subsys_1317_8201_10b8_2635, 0}; +#undef pci_ss_info_10b8_2635 +#define pci_ss_info_10b8_2635 pci_ss_info_1317_8201_10b8_2635 +static const pciSubsystemInfo pci_ss_info_1317_8201_1317_8201 = + {0x1317, 0x8201, pci_subsys_1317_8201_1317_8201, 0}; +#undef pci_ss_info_1317_8201 +#define pci_ss_info_1317_8201 pci_ss_info_1317_8201_1317_8201 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1319_0801_1319_1319 = + {0x1319, 0x1319, pci_subsys_1319_0801_1319_1319, 0}; +#undef pci_ss_info_1319_1319 +#define pci_ss_info_1319_1319 pci_ss_info_1319_0801_1319_1319 +static const pciSubsystemInfo pci_ss_info_1319_0802_1319_1319 = + {0x1319, 0x1319, pci_subsys_1319_0802_1319_1319, 0}; +#undef pci_ss_info_1319_1319 +#define pci_ss_info_1319_1319 pci_ss_info_1319_0802_1319_1319 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_131f_2030_131f_2030 = + {0x131f, 0x2030, pci_subsys_131f_2030_131f_2030, 0}; +#undef pci_ss_info_131f_2030 +#define pci_ss_info_131f_2030 pci_ss_info_131f_2030_131f_2030 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_134d_7890_134d_0001 = + {0x134d, 0x0001, pci_subsys_134d_7890_134d_0001, 0}; +#undef pci_ss_info_134d_0001 +#define pci_ss_info_134d_0001 pci_ss_info_134d_7890_134d_0001 +static const pciSubsystemInfo pci_ss_info_134d_7891_134d_0001 = + {0x134d, 0x0001, pci_subsys_134d_7891_134d_0001, 0}; +#undef pci_ss_info_134d_0001 +#define pci_ss_info_134d_0001 pci_ss_info_134d_7891_134d_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1371_434e_1371_434e = + {0x1371, 0x434e, pci_subsys_1371_434e_1371_434e, 0}; +#undef pci_ss_info_1371_434e +#define pci_ss_info_1371_434e pci_ss_info_1371_434e_1371_434e +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1394_0001_1394_0001 = + {0x1394, 0x0001, pci_subsys_1394_0001_1394_0001, 0}; +#undef pci_ss_info_1394_0001 +#define pci_ss_info_1394_0001 pci_ss_info_1394_0001_1394_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1397_08b4_1397_b520 = + {0x1397, 0xb520, pci_subsys_1397_08b4_1397_b520, 0}; +#undef pci_ss_info_1397_b520 +#define pci_ss_info_1397_b520 pci_ss_info_1397_08b4_1397_b520 +static const pciSubsystemInfo pci_ss_info_1397_08b4_1397_b540 = + {0x1397, 0xb540, pci_subsys_1397_08b4_1397_b540, 0}; +#undef pci_ss_info_1397_b540 +#define pci_ss_info_1397_b540 pci_ss_info_1397_08b4_1397_b540 +static const pciSubsystemInfo pci_ss_info_1397_2bd0_0675_1704 = + {0x0675, 0x1704, pci_subsys_1397_2bd0_0675_1704, 0}; +#undef pci_ss_info_0675_1704 +#define pci_ss_info_0675_1704 pci_ss_info_1397_2bd0_0675_1704 +static const pciSubsystemInfo pci_ss_info_1397_2bd0_0675_1708 = + {0x0675, 0x1708, pci_subsys_1397_2bd0_0675_1708, 0}; +#undef pci_ss_info_0675_1708 +#define pci_ss_info_0675_1708 pci_ss_info_1397_2bd0_0675_1708 +static const pciSubsystemInfo pci_ss_info_1397_2bd0_1397_2bd0 = + {0x1397, 0x2bd0, pci_subsys_1397_2bd0_1397_2bd0, 0}; +#undef pci_ss_info_1397_2bd0 +#define pci_ss_info_1397_2bd0 pci_ss_info_1397_2bd0_1397_2bd0 +static const pciSubsystemInfo pci_ss_info_1397_2bd0_e4bf_1000 = + {0xe4bf, 0x1000, pci_subsys_1397_2bd0_e4bf_1000, 0}; +#undef pci_ss_info_e4bf_1000 +#define pci_ss_info_e4bf_1000 pci_ss_info_1397_2bd0_e4bf_1000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_13c1_1001_13c1_1001 = + {0x13c1, 0x1001, pci_subsys_13c1_1001_13c1_1001, 0}; +#undef pci_ss_info_13c1_1001 +#define pci_ss_info_13c1_1001 pci_ss_info_13c1_1001_13c1_1001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_13df_0001_13df_0001 = + {0x13df, 0x0001, pci_subsys_13df_0001_13df_0001, 0}; +#undef pci_ss_info_13df_0001 +#define pci_ss_info_13df_0001 pci_ss_info_13df_0001_13df_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_13f6_0100_13f6_ffff = + {0x13f6, 0xffff, pci_subsys_13f6_0100_13f6_ffff, 0}; +#undef pci_ss_info_13f6_ffff +#define pci_ss_info_13f6_ffff pci_ss_info_13f6_0100_13f6_ffff +static const pciSubsystemInfo pci_ss_info_13f6_0101_13f6_0101 = + {0x13f6, 0x0101, pci_subsys_13f6_0101_13f6_0101, 0}; +#undef pci_ss_info_13f6_0101 +#define pci_ss_info_13f6_0101 pci_ss_info_13f6_0101_13f6_0101 +static const pciSubsystemInfo pci_ss_info_13f6_0111_1019_0970 = + {0x1019, 0x0970, pci_subsys_13f6_0111_1019_0970, 0}; +#undef pci_ss_info_1019_0970 +#define pci_ss_info_1019_0970 pci_ss_info_13f6_0111_1019_0970 +static const pciSubsystemInfo pci_ss_info_13f6_0111_1043_8035 = + {0x1043, 0x8035, pci_subsys_13f6_0111_1043_8035, 0}; +#undef pci_ss_info_1043_8035 +#define pci_ss_info_1043_8035 pci_ss_info_13f6_0111_1043_8035 +static const pciSubsystemInfo pci_ss_info_13f6_0111_1043_8077 = + {0x1043, 0x8077, pci_subsys_13f6_0111_1043_8077, 0}; +#undef pci_ss_info_1043_8077 +#define pci_ss_info_1043_8077 pci_ss_info_13f6_0111_1043_8077 +static const pciSubsystemInfo pci_ss_info_13f6_0111_1043_80e2 = + {0x1043, 0x80e2, pci_subsys_13f6_0111_1043_80e2, 0}; +#undef pci_ss_info_1043_80e2 +#define pci_ss_info_1043_80e2 pci_ss_info_13f6_0111_1043_80e2 +static const pciSubsystemInfo pci_ss_info_13f6_0111_13f6_0111 = + {0x13f6, 0x0111, pci_subsys_13f6_0111_13f6_0111, 0}; +#undef pci_ss_info_13f6_0111 +#define pci_ss_info_13f6_0111 pci_ss_info_13f6_0111_13f6_0111 +static const pciSubsystemInfo pci_ss_info_13f6_0111_1681_a000 = + {0x1681, 0xa000, pci_subsys_13f6_0111_1681_a000, 0}; +#undef pci_ss_info_1681_a000 +#define pci_ss_info_1681_a000 pci_ss_info_13f6_0111_1681_a000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_13fe_1600_1601_0002 = + {0x1601, 0x0002, pci_subsys_13fe_1600_1601_0002, 0}; +#undef pci_ss_info_1601_0002 +#define pci_ss_info_1601_0002 pci_ss_info_13fe_1600_1601_0002 +static const pciSubsystemInfo pci_ss_info_13fe_1600_1602_0002 = + {0x1602, 0x0002, pci_subsys_13fe_1600_1602_0002, 0}; +#undef pci_ss_info_1602_0002 +#define pci_ss_info_1602_0002 pci_ss_info_13fe_1600_1602_0002 +static const pciSubsystemInfo pci_ss_info_13fe_1600_1612_0004 = + {0x1612, 0x0004, pci_subsys_13fe_1600_1612_0004, 0}; +#undef pci_ss_info_1612_0004 +#define pci_ss_info_1612_0004 pci_ss_info_13fe_1600_1612_0004 +static const pciSubsystemInfo pci_ss_info_13fe_16ff_1601_0000 = + {0x1601, 0x0000, pci_subsys_13fe_16ff_1601_0000, 0}; +#undef pci_ss_info_1601_0000 +#define pci_ss_info_1601_0000 pci_ss_info_13fe_16ff_1601_0000 +static const pciSubsystemInfo pci_ss_info_13fe_16ff_1602_0000 = + {0x1602, 0x0000, pci_subsys_13fe_16ff_1602_0000, 0}; +#undef pci_ss_info_1602_0000 +#define pci_ss_info_1602_0000 pci_ss_info_13fe_16ff_1602_0000 +static const pciSubsystemInfo pci_ss_info_13fe_16ff_1612_0000 = + {0x1612, 0x0000, pci_subsys_13fe_16ff_1612_0000, 0}; +#undef pci_ss_info_1612_0000 +#define pci_ss_info_1612_0000 pci_ss_info_13fe_16ff_1612_0000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_1712 = + {0x1412, 0x1712, pci_subsys_1412_1712_1412_1712, 0}; +#undef pci_ss_info_1412_1712 +#define pci_ss_info_1412_1712 pci_ss_info_1412_1712_1412_1712 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d630 = + {0x1412, 0xd630, pci_subsys_1412_1712_1412_d630, 0}; +#undef pci_ss_info_1412_d630 +#define pci_ss_info_1412_d630 pci_ss_info_1412_1712_1412_d630 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d631 = + {0x1412, 0xd631, pci_subsys_1412_1712_1412_d631, 0}; +#undef pci_ss_info_1412_d631 +#define pci_ss_info_1412_d631 pci_ss_info_1412_1712_1412_d631 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d632 = + {0x1412, 0xd632, pci_subsys_1412_1712_1412_d632, 0}; +#undef pci_ss_info_1412_d632 +#define pci_ss_info_1412_d632 pci_ss_info_1412_1712_1412_d632 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d633 = + {0x1412, 0xd633, pci_subsys_1412_1712_1412_d633, 0}; +#undef pci_ss_info_1412_d633 +#define pci_ss_info_1412_d633 pci_ss_info_1412_1712_1412_d633 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d634 = + {0x1412, 0xd634, pci_subsys_1412_1712_1412_d634, 0}; +#undef pci_ss_info_1412_d634 +#define pci_ss_info_1412_d634 pci_ss_info_1412_1712_1412_d634 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d635 = + {0x1412, 0xd635, pci_subsys_1412_1712_1412_d635, 0}; +#undef pci_ss_info_1412_d635 +#define pci_ss_info_1412_d635 pci_ss_info_1412_1712_1412_d635 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d637 = + {0x1412, 0xd637, pci_subsys_1412_1712_1412_d637, 0}; +#undef pci_ss_info_1412_d637 +#define pci_ss_info_1412_d637 pci_ss_info_1412_1712_1412_d637 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d638 = + {0x1412, 0xd638, pci_subsys_1412_1712_1412_d638, 0}; +#undef pci_ss_info_1412_d638 +#define pci_ss_info_1412_d638 pci_ss_info_1412_1712_1412_d638 +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d63b = + {0x1412, 0xd63b, pci_subsys_1412_1712_1412_d63b, 0}; +#undef pci_ss_info_1412_d63b +#define pci_ss_info_1412_d63b pci_ss_info_1412_1712_1412_d63b +static const pciSubsystemInfo pci_ss_info_1412_1712_1412_d63c = + {0x1412, 0xd63c, pci_subsys_1412_1712_1412_d63c, 0}; +#undef pci_ss_info_1412_d63c +#define pci_ss_info_1412_d63c pci_ss_info_1412_1712_1412_d63c +static const pciSubsystemInfo pci_ss_info_1412_1712_1416_1712 = + {0x1416, 0x1712, pci_subsys_1412_1712_1416_1712, 0}; +#undef pci_ss_info_1416_1712 +#define pci_ss_info_1416_1712 pci_ss_info_1412_1712_1416_1712 +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_1115 = + {0x153b, 0x1115, pci_subsys_1412_1712_153b_1115, 0}; +#undef pci_ss_info_153b_1115 +#define pci_ss_info_153b_1115 pci_ss_info_1412_1712_153b_1115 +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_1125 = + {0x153b, 0x1125, pci_subsys_1412_1712_153b_1125, 0}; +#undef pci_ss_info_153b_1125 +#define pci_ss_info_153b_1125 pci_ss_info_1412_1712_153b_1125 +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_112b = + {0x153b, 0x112b, pci_subsys_1412_1712_153b_112b, 0}; +#undef pci_ss_info_153b_112b +#define pci_ss_info_153b_112b pci_ss_info_1412_1712_153b_112b +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_112c = + {0x153b, 0x112c, pci_subsys_1412_1712_153b_112c, 0}; +#undef pci_ss_info_153b_112c +#define pci_ss_info_153b_112c pci_ss_info_1412_1712_153b_112c +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_1130 = + {0x153b, 0x1130, pci_subsys_1412_1712_153b_1130, 0}; +#undef pci_ss_info_153b_1130 +#define pci_ss_info_153b_1130 pci_ss_info_1412_1712_153b_1130 +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_1138 = + {0x153b, 0x1138, pci_subsys_1412_1712_153b_1138, 0}; +#undef pci_ss_info_153b_1138 +#define pci_ss_info_153b_1138 pci_ss_info_1412_1712_153b_1138 +static const pciSubsystemInfo pci_ss_info_1412_1712_153b_1151 = + {0x153b, 0x1151, pci_subsys_1412_1712_153b_1151, 0}; +#undef pci_ss_info_153b_1151 +#define pci_ss_info_153b_1151 pci_ss_info_1412_1712_153b_1151 +static const pciSubsystemInfo pci_ss_info_1412_1712_16ce_1040 = + {0x16ce, 0x1040, pci_subsys_1412_1712_16ce_1040, 0}; +#undef pci_ss_info_16ce_1040 +#define pci_ss_info_16ce_1040 pci_ss_info_1412_1712_16ce_1040 +static const pciSubsystemInfo pci_ss_info_1412_1724_1412_1724 = + {0x1412, 0x1724, pci_subsys_1412_1724_1412_1724, 0}; +#undef pci_ss_info_1412_1724 +#define pci_ss_info_1412_1724 pci_ss_info_1412_1724_1412_1724 +static const pciSubsystemInfo pci_ss_info_1412_1724_1412_3630 = + {0x1412, 0x3630, pci_subsys_1412_1724_1412_3630, 0}; +#undef pci_ss_info_1412_3630 +#define pci_ss_info_1412_3630 pci_ss_info_1412_1724_1412_3630 +static const pciSubsystemInfo pci_ss_info_1412_1724_1412_3631 = + {0x1412, 0x3631, pci_subsys_1412_1724_1412_3631, 0}; +#undef pci_ss_info_1412_3631 +#define pci_ss_info_1412_3631 pci_ss_info_1412_1724_1412_3631 +static const pciSubsystemInfo pci_ss_info_1412_1724_153b_1145 = + {0x153b, 0x1145, pci_subsys_1412_1724_153b_1145, 0}; +#undef pci_ss_info_153b_1145 +#define pci_ss_info_153b_1145 pci_ss_info_1412_1724_153b_1145 +static const pciSubsystemInfo pci_ss_info_1412_1724_153b_1147 = + {0x153b, 0x1147, pci_subsys_1412_1724_153b_1147, 0}; +#undef pci_ss_info_153b_1147 +#define pci_ss_info_153b_1147 pci_ss_info_1412_1724_153b_1147 +static const pciSubsystemInfo pci_ss_info_1412_1724_153b_1153 = + {0x153b, 0x1153, pci_subsys_1412_1724_153b_1153, 0}; +#undef pci_ss_info_153b_1153 +#define pci_ss_info_153b_1153 pci_ss_info_1412_1724_153b_1153 +static const pciSubsystemInfo pci_ss_info_1412_1724_270f_f641 = + {0x270f, 0xf641, pci_subsys_1412_1724_270f_f641, 0}; +#undef pci_ss_info_270f_f641 +#define pci_ss_info_270f_f641 pci_ss_info_1412_1724_270f_f641 +static const pciSubsystemInfo pci_ss_info_1412_1724_270f_f645 = + {0x270f, 0xf645, pci_subsys_1412_1724_270f_f645, 0}; +#undef pci_ss_info_270f_f645 +#define pci_ss_info_270f_f645 pci_ss_info_1412_1724_270f_f645 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1415_9501_12c4_0201 = + {0x12c4, 0x0201, pci_subsys_1415_9501_12c4_0201, 0}; +#undef pci_ss_info_12c4_0201 +#define pci_ss_info_12c4_0201 pci_ss_info_1415_9501_12c4_0201 +static const pciSubsystemInfo pci_ss_info_1415_9501_12c4_0202 = + {0x12c4, 0x0202, pci_subsys_1415_9501_12c4_0202, 0}; +#undef pci_ss_info_12c4_0202 +#define pci_ss_info_12c4_0202 pci_ss_info_1415_9501_12c4_0202 +static const pciSubsystemInfo pci_ss_info_1415_9501_12c4_0203 = + {0x12c4, 0x0203, pci_subsys_1415_9501_12c4_0203, 0}; +#undef pci_ss_info_12c4_0203 +#define pci_ss_info_12c4_0203 pci_ss_info_1415_9501_12c4_0203 +static const pciSubsystemInfo pci_ss_info_1415_9501_12c4_0210 = + {0x12c4, 0x0210, pci_subsys_1415_9501_12c4_0210, 0}; +#undef pci_ss_info_12c4_0210 +#define pci_ss_info_12c4_0210 pci_ss_info_1415_9501_12c4_0210 +static const pciSubsystemInfo pci_ss_info_1415_9501_131f_2050 = + {0x131f, 0x2050, pci_subsys_1415_9501_131f_2050, 0}; +#undef pci_ss_info_131f_2050 +#define pci_ss_info_131f_2050 pci_ss_info_1415_9501_131f_2050 +static const pciSubsystemInfo pci_ss_info_1415_9501_131f_2051 = + {0x131f, 0x2051, pci_subsys_1415_9501_131f_2051, 0}; +#undef pci_ss_info_131f_2051 +#define pci_ss_info_131f_2051 pci_ss_info_1415_9501_131f_2051 +static const pciSubsystemInfo pci_ss_info_1415_9501_15ed_2000 = + {0x15ed, 0x2000, pci_subsys_1415_9501_15ed_2000, 0}; +#undef pci_ss_info_15ed_2000 +#define pci_ss_info_15ed_2000 pci_ss_info_1415_9501_15ed_2000 +static const pciSubsystemInfo pci_ss_info_1415_9501_15ed_2001 = + {0x15ed, 0x2001, pci_subsys_1415_9501_15ed_2001, 0}; +#undef pci_ss_info_15ed_2001 +#define pci_ss_info_15ed_2001 pci_ss_info_1415_9501_15ed_2001 +static const pciSubsystemInfo pci_ss_info_1415_9510_12c4_0200 = + {0x12c4, 0x0200, pci_subsys_1415_9510_12c4_0200, 0}; +#undef pci_ss_info_12c4_0200 +#define pci_ss_info_12c4_0200 pci_ss_info_1415_9510_12c4_0200 +static const pciSubsystemInfo pci_ss_info_1415_9511_12c4_0211 = + {0x12c4, 0x0211, pci_subsys_1415_9511_12c4_0211, 0}; +#undef pci_ss_info_12c4_0211 +#define pci_ss_info_12c4_0211 pci_ss_info_1415_9511_12c4_0211 +static const pciSubsystemInfo pci_ss_info_1415_9511_15ed_2000 = + {0x15ed, 0x2000, pci_subsys_1415_9511_15ed_2000, 0}; +#undef pci_ss_info_15ed_2000 +#define pci_ss_info_15ed_2000 pci_ss_info_1415_9511_15ed_2000 +static const pciSubsystemInfo pci_ss_info_1415_9511_15ed_2001 = + {0x15ed, 0x2001, pci_subsys_1415_9511_15ed_2001, 0}; +#undef pci_ss_info_15ed_2001 +#define pci_ss_info_15ed_2001 pci_ss_info_1415_9511_15ed_2001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14c1_8043_103c_1240 = + {0x103c, 0x1240, pci_subsys_14c1_8043_103c_1240, 0}; +#undef pci_ss_info_103c_1240 +#define pci_ss_info_103c_1240 pci_ss_info_14c1_8043_103c_1240 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1600_107b_5048 = + {0x107b, 0x5048, pci_subsys_14e4_1600_107b_5048, 0}; +#undef pci_ss_info_107b_5048 +#define pci_ss_info_107b_5048 pci_ss_info_14e4_1600_107b_5048 +static const pciSubsystemInfo pci_ss_info_14e4_1644_1014_0277 = + {0x1014, 0x0277, pci_subsys_14e4_1644_1014_0277, 0}; +#undef pci_ss_info_1014_0277 +#define pci_ss_info_1014_0277 pci_ss_info_14e4_1644_1014_0277 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1644_1028_00d1 = + {0x1028, 0x00d1, pci_subsys_14e4_1644_1028_00d1, 0}; +#undef pci_ss_info_1028_00d1 +#define pci_ss_info_1028_00d1 pci_ss_info_14e4_1644_1028_00d1 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1644_1028_0106 = + {0x1028, 0x0106, pci_subsys_14e4_1644_1028_0106, 0}; +#undef pci_ss_info_1028_0106 +#define pci_ss_info_1028_0106 pci_ss_info_14e4_1644_1028_0106 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1644_1028_0109 = + {0x1028, 0x0109, pci_subsys_14e4_1644_1028_0109, 0}; +#undef pci_ss_info_1028_0109 +#define pci_ss_info_1028_0109 pci_ss_info_14e4_1644_1028_0109 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1644_1028_010a = + {0x1028, 0x010a, pci_subsys_14e4_1644_1028_010a, 0}; +#undef pci_ss_info_1028_010a +#define pci_ss_info_1028_010a pci_ss_info_14e4_1644_1028_010a +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1000 = + {0x10b7, 0x1000, pci_subsys_14e4_1644_10b7_1000, 0}; +#undef pci_ss_info_10b7_1000 +#define pci_ss_info_10b7_1000 pci_ss_info_14e4_1644_10b7_1000 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1001 = + {0x10b7, 0x1001, pci_subsys_14e4_1644_10b7_1001, 0}; +#undef pci_ss_info_10b7_1001 +#define pci_ss_info_10b7_1001 pci_ss_info_14e4_1644_10b7_1001 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1002 = + {0x10b7, 0x1002, pci_subsys_14e4_1644_10b7_1002, 0}; +#undef pci_ss_info_10b7_1002 +#define pci_ss_info_10b7_1002 pci_ss_info_14e4_1644_10b7_1002 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1003 = + {0x10b7, 0x1003, pci_subsys_14e4_1644_10b7_1003, 0}; +#undef pci_ss_info_10b7_1003 +#define pci_ss_info_10b7_1003 pci_ss_info_14e4_1644_10b7_1003 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1004 = + {0x10b7, 0x1004, pci_subsys_14e4_1644_10b7_1004, 0}; +#undef pci_ss_info_10b7_1004 +#define pci_ss_info_10b7_1004 pci_ss_info_14e4_1644_10b7_1004 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1005 = + {0x10b7, 0x1005, pci_subsys_14e4_1644_10b7_1005, 0}; +#undef pci_ss_info_10b7_1005 +#define pci_ss_info_10b7_1005 pci_ss_info_14e4_1644_10b7_1005 +static const pciSubsystemInfo pci_ss_info_14e4_1644_10b7_1008 = + {0x10b7, 0x1008, pci_subsys_14e4_1644_10b7_1008, 0}; +#undef pci_ss_info_10b7_1008 +#define pci_ss_info_10b7_1008 pci_ss_info_14e4_1644_10b7_1008 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_0002 = + {0x14e4, 0x0002, pci_subsys_14e4_1644_14e4_0002, 0}; +#undef pci_ss_info_14e4_0002 +#define pci_ss_info_14e4_0002 pci_ss_info_14e4_1644_14e4_0002 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_0003 = + {0x14e4, 0x0003, pci_subsys_14e4_1644_14e4_0003, 0}; +#undef pci_ss_info_14e4_0003 +#define pci_ss_info_14e4_0003 pci_ss_info_14e4_1644_14e4_0003 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_0004 = + {0x14e4, 0x0004, pci_subsys_14e4_1644_14e4_0004, 0}; +#undef pci_ss_info_14e4_0004 +#define pci_ss_info_14e4_0004 pci_ss_info_14e4_1644_14e4_0004 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_1028 = + {0x14e4, 0x1028, pci_subsys_14e4_1644_14e4_1028, 0}; +#undef pci_ss_info_14e4_1028 +#define pci_ss_info_14e4_1028 pci_ss_info_14e4_1644_14e4_1028 +static const pciSubsystemInfo pci_ss_info_14e4_1644_14e4_1644 = + {0x14e4, 0x1644, pci_subsys_14e4_1644_14e4_1644, 0}; +#undef pci_ss_info_14e4_1644 +#define pci_ss_info_14e4_1644 pci_ss_info_14e4_1644_14e4_1644 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_007c = + {0x0e11, 0x007c, pci_subsys_14e4_1645_0e11_007c, 0}; +#undef pci_ss_info_0e11_007c +#define pci_ss_info_0e11_007c pci_ss_info_14e4_1645_0e11_007c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_007d = + {0x0e11, 0x007d, pci_subsys_14e4_1645_0e11_007d, 0}; +#undef pci_ss_info_0e11_007d +#define pci_ss_info_0e11_007d pci_ss_info_14e4_1645_0e11_007d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_0085 = + {0x0e11, 0x0085, pci_subsys_14e4_1645_0e11_0085, 0}; +#undef pci_ss_info_0e11_0085 +#define pci_ss_info_0e11_0085 pci_ss_info_14e4_1645_0e11_0085 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_0099 = + {0x0e11, 0x0099, pci_subsys_14e4_1645_0e11_0099, 0}; +#undef pci_ss_info_0e11_0099 +#define pci_ss_info_0e11_0099 pci_ss_info_14e4_1645_0e11_0099 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_009a = + {0x0e11, 0x009a, pci_subsys_14e4_1645_0e11_009a, 0}; +#undef pci_ss_info_0e11_009a +#define pci_ss_info_0e11_009a pci_ss_info_14e4_1645_0e11_009a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_0e11_00c1 = + {0x0e11, 0x00c1, pci_subsys_14e4_1645_0e11_00c1, 0}; +#undef pci_ss_info_0e11_00c1 +#define pci_ss_info_0e11_00c1 pci_ss_info_14e4_1645_0e11_00c1 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_1028_0121 = + {0x1028, 0x0121, pci_subsys_14e4_1645_1028_0121, 0}; +#undef pci_ss_info_1028_0121 +#define pci_ss_info_1028_0121 pci_ss_info_14e4_1645_1028_0121 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_103c_128a = + {0x103c, 0x128a, pci_subsys_14e4_1645_103c_128a, 0}; +#undef pci_ss_info_103c_128a +#define pci_ss_info_103c_128a pci_ss_info_14e4_1645_103c_128a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_103c_128b = + {0x103c, 0x128b, pci_subsys_14e4_1645_103c_128b, 0}; +#undef pci_ss_info_103c_128b +#define pci_ss_info_103c_128b pci_ss_info_14e4_1645_103c_128b +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_103c_12a4 = + {0x103c, 0x12a4, pci_subsys_14e4_1645_103c_12a4, 0}; +#undef pci_ss_info_103c_12a4 +#define pci_ss_info_103c_12a4 pci_ss_info_14e4_1645_103c_12a4 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_103c_12c1 = + {0x103c, 0x12c1, pci_subsys_14e4_1645_103c_12c1, 0}; +#undef pci_ss_info_103c_12c1 +#define pci_ss_info_103c_12c1 pci_ss_info_14e4_1645_103c_12c1 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1645_103c_1300 = + {0x103c, 0x1300, pci_subsys_14e4_1645_103c_1300, 0}; +#undef pci_ss_info_103c_1300 +#define pci_ss_info_103c_1300 pci_ss_info_14e4_1645_103c_1300 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1645_10a9_8010 = + {0x10a9, 0x8010, pci_subsys_14e4_1645_10a9_8010, 0}; +#undef pci_ss_info_10a9_8010 +#define pci_ss_info_10a9_8010 pci_ss_info_14e4_1645_10a9_8010 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10a9_8011 = + {0x10a9, 0x8011, pci_subsys_14e4_1645_10a9_8011, 0}; +#undef pci_ss_info_10a9_8011 +#define pci_ss_info_10a9_8011 pci_ss_info_14e4_1645_10a9_8011 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10a9_8012 = + {0x10a9, 0x8012, pci_subsys_14e4_1645_10a9_8012, 0}; +#undef pci_ss_info_10a9_8012 +#define pci_ss_info_10a9_8012 pci_ss_info_14e4_1645_10a9_8012 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10b7_1004 = + {0x10b7, 0x1004, pci_subsys_14e4_1645_10b7_1004, 0}; +#undef pci_ss_info_10b7_1004 +#define pci_ss_info_10b7_1004 pci_ss_info_14e4_1645_10b7_1004 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10b7_1006 = + {0x10b7, 0x1006, pci_subsys_14e4_1645_10b7_1006, 0}; +#undef pci_ss_info_10b7_1006 +#define pci_ss_info_10b7_1006 pci_ss_info_14e4_1645_10b7_1006 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10b7_1007 = + {0x10b7, 0x1007, pci_subsys_14e4_1645_10b7_1007, 0}; +#undef pci_ss_info_10b7_1007 +#define pci_ss_info_10b7_1007 pci_ss_info_14e4_1645_10b7_1007 +static const pciSubsystemInfo pci_ss_info_14e4_1645_10b7_1008 = + {0x10b7, 0x1008, pci_subsys_14e4_1645_10b7_1008, 0}; +#undef pci_ss_info_10b7_1008 +#define pci_ss_info_10b7_1008 pci_ss_info_14e4_1645_10b7_1008 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0001 = + {0x14e4, 0x0001, pci_subsys_14e4_1645_14e4_0001, 0}; +#undef pci_ss_info_14e4_0001 +#define pci_ss_info_14e4_0001 pci_ss_info_14e4_1645_14e4_0001 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0005 = + {0x14e4, 0x0005, pci_subsys_14e4_1645_14e4_0005, 0}; +#undef pci_ss_info_14e4_0005 +#define pci_ss_info_14e4_0005 pci_ss_info_14e4_1645_14e4_0005 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0006 = + {0x14e4, 0x0006, pci_subsys_14e4_1645_14e4_0006, 0}; +#undef pci_ss_info_14e4_0006 +#define pci_ss_info_14e4_0006 pci_ss_info_14e4_1645_14e4_0006 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0007 = + {0x14e4, 0x0007, pci_subsys_14e4_1645_14e4_0007, 0}; +#undef pci_ss_info_14e4_0007 +#define pci_ss_info_14e4_0007 pci_ss_info_14e4_1645_14e4_0007 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_0008 = + {0x14e4, 0x0008, pci_subsys_14e4_1645_14e4_0008, 0}; +#undef pci_ss_info_14e4_0008 +#define pci_ss_info_14e4_0008 pci_ss_info_14e4_1645_14e4_0008 +static const pciSubsystemInfo pci_ss_info_14e4_1645_14e4_8008 = + {0x14e4, 0x8008, pci_subsys_14e4_1645_14e4_8008, 0}; +#undef pci_ss_info_14e4_8008 +#define pci_ss_info_14e4_8008 pci_ss_info_14e4_1645_14e4_8008 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1646_0e11_00bb = + {0x0e11, 0x00bb, pci_subsys_14e4_1646_0e11_00bb, 0}; +#undef pci_ss_info_0e11_00bb +#define pci_ss_info_0e11_00bb pci_ss_info_14e4_1646_0e11_00bb +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1646_1028_0126 = + {0x1028, 0x0126, pci_subsys_14e4_1646_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_14e4_1646_1028_0126 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1646_14e4_8009 = + {0x14e4, 0x8009, pci_subsys_14e4_1646_14e4_8009, 0}; +#undef pci_ss_info_14e4_8009 +#define pci_ss_info_14e4_8009 pci_ss_info_14e4_1646_14e4_8009 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1647_0e11_0099 = + {0x0e11, 0x0099, pci_subsys_14e4_1647_0e11_0099, 0}; +#undef pci_ss_info_0e11_0099 +#define pci_ss_info_0e11_0099 pci_ss_info_14e4_1647_0e11_0099 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1647_0e11_009a = + {0x0e11, 0x009a, pci_subsys_14e4_1647_0e11_009a, 0}; +#undef pci_ss_info_0e11_009a +#define pci_ss_info_0e11_009a pci_ss_info_14e4_1647_0e11_009a +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1647_10a9_8010 = + {0x10a9, 0x8010, pci_subsys_14e4_1647_10a9_8010, 0}; +#undef pci_ss_info_10a9_8010 +#define pci_ss_info_10a9_8010 pci_ss_info_14e4_1647_10a9_8010 +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_0009 = + {0x14e4, 0x0009, pci_subsys_14e4_1647_14e4_0009, 0}; +#undef pci_ss_info_14e4_0009 +#define pci_ss_info_14e4_0009 pci_ss_info_14e4_1647_14e4_0009 +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_000a = + {0x14e4, 0x000a, pci_subsys_14e4_1647_14e4_000a, 0}; +#undef pci_ss_info_14e4_000a +#define pci_ss_info_14e4_000a pci_ss_info_14e4_1647_14e4_000a +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_000b = + {0x14e4, 0x000b, pci_subsys_14e4_1647_14e4_000b, 0}; +#undef pci_ss_info_14e4_000b +#define pci_ss_info_14e4_000b pci_ss_info_14e4_1647_14e4_000b +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_8009 = + {0x14e4, 0x8009, pci_subsys_14e4_1647_14e4_8009, 0}; +#undef pci_ss_info_14e4_8009 +#define pci_ss_info_14e4_8009 pci_ss_info_14e4_1647_14e4_8009 +static const pciSubsystemInfo pci_ss_info_14e4_1647_14e4_800a = + {0x14e4, 0x800a, pci_subsys_14e4_1647_14e4_800a, 0}; +#undef pci_ss_info_14e4_800a +#define pci_ss_info_14e4_800a pci_ss_info_14e4_1647_14e4_800a +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1648_0e11_00cf = + {0x0e11, 0x00cf, pci_subsys_14e4_1648_0e11_00cf, 0}; +#undef pci_ss_info_0e11_00cf +#define pci_ss_info_0e11_00cf pci_ss_info_14e4_1648_0e11_00cf +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1648_0e11_00d0 = + {0x0e11, 0x00d0, pci_subsys_14e4_1648_0e11_00d0, 0}; +#undef pci_ss_info_0e11_00d0 +#define pci_ss_info_0e11_00d0 pci_ss_info_14e4_1648_0e11_00d0 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1648_0e11_00d1 = + {0x0e11, 0x00d1, pci_subsys_14e4_1648_0e11_00d1, 0}; +#undef pci_ss_info_0e11_00d1 +#define pci_ss_info_0e11_00d1 pci_ss_info_14e4_1648_0e11_00d1 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1648_10a9_8013 = + {0x10a9, 0x8013, pci_subsys_14e4_1648_10a9_8013, 0}; +#undef pci_ss_info_10a9_8013 +#define pci_ss_info_10a9_8013 pci_ss_info_14e4_1648_10a9_8013 +static const pciSubsystemInfo pci_ss_info_14e4_1648_10a9_8018 = + {0x10a9, 0x8018, pci_subsys_14e4_1648_10a9_8018, 0}; +#undef pci_ss_info_10a9_8018 +#define pci_ss_info_10a9_8018 pci_ss_info_14e4_1648_10a9_8018 +static const pciSubsystemInfo pci_ss_info_14e4_1648_10a9_801a = + {0x10a9, 0x801a, pci_subsys_14e4_1648_10a9_801a, 0}; +#undef pci_ss_info_10a9_801a +#define pci_ss_info_10a9_801a pci_ss_info_14e4_1648_10a9_801a +static const pciSubsystemInfo pci_ss_info_14e4_1648_10a9_801b = + {0x10a9, 0x801b, pci_subsys_14e4_1648_10a9_801b, 0}; +#undef pci_ss_info_10a9_801b +#define pci_ss_info_10a9_801b pci_ss_info_14e4_1648_10a9_801b +static const pciSubsystemInfo pci_ss_info_14e4_1648_10b7_2000 = + {0x10b7, 0x2000, pci_subsys_14e4_1648_10b7_2000, 0}; +#undef pci_ss_info_10b7_2000 +#define pci_ss_info_10b7_2000 pci_ss_info_14e4_1648_10b7_2000 +static const pciSubsystemInfo pci_ss_info_14e4_1648_10b7_3000 = + {0x10b7, 0x3000, pci_subsys_14e4_1648_10b7_3000, 0}; +#undef pci_ss_info_10b7_3000 +#define pci_ss_info_10b7_3000 pci_ss_info_14e4_1648_10b7_3000 +static const pciSubsystemInfo pci_ss_info_14e4_1648_1166_1648 = + {0x1166, 0x1648, pci_subsys_14e4_1648_1166_1648, 0}; +#undef pci_ss_info_1166_1648 +#define pci_ss_info_1166_1648 pci_ss_info_14e4_1648_1166_1648 +static const pciSubsystemInfo pci_ss_info_14e4_1648_1734_100b = + {0x1734, 0x100b, pci_subsys_14e4_1648_1734_100b, 0}; +#undef pci_ss_info_1734_100b +#define pci_ss_info_1734_100b pci_ss_info_14e4_1648_1734_100b +#endif +static const pciSubsystemInfo pci_ss_info_14e4_164a_103c_3070 = + {0x103c, 0x3070, pci_subsys_14e4_164a_103c_3070, 0}; +#undef pci_ss_info_103c_3070 +#define pci_ss_info_103c_3070 pci_ss_info_14e4_164a_103c_3070 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_164a_103c_3101 = + {0x103c, 0x3101, pci_subsys_14e4_164a_103c_3101, 0}; +#undef pci_ss_info_103c_3101 +#define pci_ss_info_103c_3101 pci_ss_info_14e4_164a_103c_3101 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_164c_103c_7037 = + {0x103c, 0x7037, pci_subsys_14e4_164c_103c_7037, 0}; +#undef pci_ss_info_103c_7037 +#define pci_ss_info_103c_7037 pci_ss_info_14e4_164c_103c_7037 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_164c_103c_7038 = + {0x103c, 0x7038, pci_subsys_14e4_164c_103c_7038, 0}; +#undef pci_ss_info_103c_7038 +#define pci_ss_info_103c_7038 pci_ss_info_14e4_164c_103c_7038 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1653_0e11_00e3 = + {0x0e11, 0x00e3, pci_subsys_14e4_1653_0e11_00e3, 0}; +#undef pci_ss_info_0e11_00e3 +#define pci_ss_info_0e11_00e3 pci_ss_info_14e4_1653_0e11_00e3 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1654_0e11_00e3 = + {0x0e11, 0x00e3, pci_subsys_14e4_1654_0e11_00e3, 0}; +#undef pci_ss_info_0e11_00e3 +#define pci_ss_info_0e11_00e3 pci_ss_info_14e4_1654_0e11_00e3 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1654_103c_3100 = + {0x103c, 0x3100, pci_subsys_14e4_1654_103c_3100, 0}; +#undef pci_ss_info_103c_3100 +#define pci_ss_info_103c_3100 pci_ss_info_14e4_1654_103c_3100 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1654_103c_3226 = + {0x103c, 0x3226, pci_subsys_14e4_1654_103c_3226, 0}; +#undef pci_ss_info_103c_3226 +#define pci_ss_info_103c_3226 pci_ss_info_14e4_1654_103c_3226 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1659_1014_02c6 = + {0x1014, 0x02c6, pci_subsys_14e4_1659_1014_02c6, 0}; +#undef pci_ss_info_1014_02c6 +#define pci_ss_info_1014_02c6 pci_ss_info_14e4_1659_1014_02c6 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1659_103c_7031 = + {0x103c, 0x7031, pci_subsys_14e4_1659_103c_7031, 0}; +#undef pci_ss_info_103c_7031 +#define pci_ss_info_103c_7031 pci_ss_info_14e4_1659_103c_7031 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1659_103c_7032 = + {0x103c, 0x7032, pci_subsys_14e4_1659_103c_7032, 0}; +#undef pci_ss_info_103c_7032 +#define pci_ss_info_103c_7032 pci_ss_info_14e4_1659_103c_7032 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1659_1734_1061 = + {0x1734, 0x1061, pci_subsys_14e4_1659_1734_1061, 0}; +#undef pci_ss_info_1734_1061 +#define pci_ss_info_1734_1061 pci_ss_info_14e4_1659_1734_1061 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_165d_1028_865d = + {0x1028, 0x865d, pci_subsys_14e4_165d_1028_865d, 0}; +#undef pci_ss_info_1028_865d +#define pci_ss_info_1028_865d pci_ss_info_14e4_165d_1028_865d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_165e_103c_088c = + {0x103c, 0x088c, pci_subsys_14e4_165e_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_14e4_165e_103c_088c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_165e_103c_0890 = + {0x103c, 0x0890, pci_subsys_14e4_165e_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_14e4_165e_103c_0890 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_165e_103c_099c = + {0x103c, 0x099c, pci_subsys_14e4_165e_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_14e4_165e_103c_099c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1668_103c_7039 = + {0x103c, 0x7039, pci_subsys_14e4_1668_103c_7039, 0}; +#undef pci_ss_info_103c_7039 +#define pci_ss_info_103c_7039 pci_ss_info_14e4_1668_103c_7039 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1677_1028_0179 = + {0x1028, 0x0179, pci_subsys_14e4_1677_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_14e4_1677_1028_0179 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1677_1028_0182 = + {0x1028, 0x0182, pci_subsys_14e4_1677_1028_0182, 0}; +#undef pci_ss_info_1028_0182 +#define pci_ss_info_1028_0182 pci_ss_info_14e4_1677_1028_0182 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1677_1028_0187 = + {0x1028, 0x0187, pci_subsys_14e4_1677_1028_0187, 0}; +#undef pci_ss_info_1028_0187 +#define pci_ss_info_1028_0187 pci_ss_info_14e4_1677_1028_0187 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1677_1028_01ad = + {0x1028, 0x01ad, pci_subsys_14e4_1677_1028_01ad, 0}; +#undef pci_ss_info_1028_01ad +#define pci_ss_info_1028_01ad pci_ss_info_14e4_1677_1028_01ad +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1677_103c_3006 = + {0x103c, 0x3006, pci_subsys_14e4_1677_103c_3006, 0}; +#undef pci_ss_info_103c_3006 +#define pci_ss_info_103c_3006 pci_ss_info_14e4_1677_103c_3006 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1677_1734_105d = + {0x1734, 0x105d, pci_subsys_14e4_1677_1734_105d, 0}; +#undef pci_ss_info_1734_105d +#define pci_ss_info_1734_105d pci_ss_info_14e4_1677_1734_105d +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1679_103c_1707 = + {0x103c, 0x1707, pci_subsys_14e4_1679_103c_1707, 0}; +#undef pci_ss_info_103c_1707 +#define pci_ss_info_103c_1707 pci_ss_info_14e4_1679_103c_1707 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1679_103c_170c = + {0x103c, 0x170c, pci_subsys_14e4_1679_103c_170c, 0}; +#undef pci_ss_info_103c_170c +#define pci_ss_info_103c_170c pci_ss_info_14e4_1679_103c_170c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1679_103c_703c = + {0x103c, 0x703c, pci_subsys_14e4_1679_103c_703c, 0}; +#undef pci_ss_info_103c_703c +#define pci_ss_info_103c_703c pci_ss_info_14e4_1679_103c_703c +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_167d_17aa_2081 = + {0x17aa, 0x2081, pci_subsys_14e4_167d_17aa_2081, 0}; +#undef pci_ss_info_17aa_2081 +#define pci_ss_info_17aa_2081 pci_ss_info_14e4_167d_17aa_2081 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_1696_103c_12bc = + {0x103c, 0x12bc, pci_subsys_14e4_1696_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_14e4_1696_103c_12bc +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_1696_14e4_000d = + {0x14e4, 0x000d, pci_subsys_14e4_1696_14e4_000d, 0}; +#undef pci_ss_info_14e4_000d +#define pci_ss_info_14e4_000d pci_ss_info_14e4_1696_14e4_000d +#endif +static const pciSubsystemInfo pci_ss_info_14e4_169c_103c_308b = + {0x103c, 0x308b, pci_subsys_14e4_169c_103c_308b, 0}; +#undef pci_ss_info_103c_308b +#define pci_ss_info_103c_308b pci_ss_info_14e4_169c_103c_308b +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16a6_0e11_00bb = + {0x0e11, 0x00bb, pci_subsys_14e4_16a6_0e11_00bb, 0}; +#undef pci_ss_info_0e11_00bb +#define pci_ss_info_0e11_00bb pci_ss_info_14e4_16a6_0e11_00bb +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16a6_1028_0126 = + {0x1028, 0x0126, pci_subsys_14e4_16a6_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_14e4_16a6_1028_0126 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_16a6_14e4_000c = + {0x14e4, 0x000c, pci_subsys_14e4_16a6_14e4_000c, 0}; +#undef pci_ss_info_14e4_000c +#define pci_ss_info_14e4_000c pci_ss_info_14e4_16a6_14e4_000c +static const pciSubsystemInfo pci_ss_info_14e4_16a6_14e4_8009 = + {0x14e4, 0x8009, pci_subsys_14e4_16a6_14e4_8009, 0}; +#undef pci_ss_info_14e4_8009 +#define pci_ss_info_14e4_8009 pci_ss_info_14e4_16a6_14e4_8009 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16a7_0e11_00ca = + {0x0e11, 0x00ca, pci_subsys_14e4_16a7_0e11_00ca, 0}; +#undef pci_ss_info_0e11_00ca +#define pci_ss_info_0e11_00ca pci_ss_info_14e4_16a7_0e11_00ca +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16a7_0e11_00cb = + {0x0e11, 0x00cb, pci_subsys_14e4_16a7_0e11_00cb, 0}; +#undef pci_ss_info_0e11_00cb +#define pci_ss_info_0e11_00cb pci_ss_info_14e4_16a7_0e11_00cb +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_16a7_14e4_0009 = + {0x14e4, 0x0009, pci_subsys_14e4_16a7_14e4_0009, 0}; +#undef pci_ss_info_14e4_0009 +#define pci_ss_info_14e4_0009 pci_ss_info_14e4_16a7_14e4_0009 +static const pciSubsystemInfo pci_ss_info_14e4_16a7_14e4_000a = + {0x14e4, 0x000a, pci_subsys_14e4_16a7_14e4_000a, 0}; +#undef pci_ss_info_14e4_000a +#define pci_ss_info_14e4_000a pci_ss_info_14e4_16a7_14e4_000a +static const pciSubsystemInfo pci_ss_info_14e4_16a7_14e4_000b = + {0x14e4, 0x000b, pci_subsys_14e4_16a7_14e4_000b, 0}; +#undef pci_ss_info_14e4_000b +#define pci_ss_info_14e4_000b pci_ss_info_14e4_16a7_14e4_000b +static const pciSubsystemInfo pci_ss_info_14e4_16a7_14e4_800a = + {0x14e4, 0x800a, pci_subsys_14e4_16a7_14e4_800a, 0}; +#undef pci_ss_info_14e4_800a +#define pci_ss_info_14e4_800a pci_ss_info_14e4_16a7_14e4_800a +static const pciSubsystemInfo pci_ss_info_14e4_16a8_10a9_8014 = + {0x10a9, 0x8014, pci_subsys_14e4_16a8_10a9_8014, 0}; +#undef pci_ss_info_10a9_8014 +#define pci_ss_info_10a9_8014 pci_ss_info_14e4_16a8_10a9_8014 +static const pciSubsystemInfo pci_ss_info_14e4_16a8_10a9_801c = + {0x10a9, 0x801c, pci_subsys_14e4_16a8_10a9_801c, 0}; +#undef pci_ss_info_10a9_801c +#define pci_ss_info_10a9_801c pci_ss_info_14e4_16a8_10a9_801c +static const pciSubsystemInfo pci_ss_info_14e4_16a8_10b7_2001 = + {0x10b7, 0x2001, pci_subsys_14e4_16a8_10b7_2001, 0}; +#undef pci_ss_info_10b7_2001 +#define pci_ss_info_10b7_2001 pci_ss_info_14e4_16a8_10b7_2001 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16aa_103c_3102 = + {0x103c, 0x3102, pci_subsys_14e4_16aa_103c_3102, 0}; +#undef pci_ss_info_103c_3102 +#define pci_ss_info_103c_3102 pci_ss_info_14e4_16aa_103c_3102 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16ac_103c_1706 = + {0x103c, 0x1706, pci_subsys_14e4_16ac_103c_1706, 0}; +#undef pci_ss_info_103c_1706 +#define pci_ss_info_103c_1706 pci_ss_info_14e4_16ac_103c_1706 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16ac_103c_703b = + {0x103c, 0x703b, pci_subsys_14e4_16ac_103c_703b, 0}; +#undef pci_ss_info_103c_703b +#define pci_ss_info_103c_703b pci_ss_info_14e4_16ac_103c_703b +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16ac_103c_703d = + {0x103c, 0x703d, pci_subsys_14e4_16ac_103c_703d, 0}; +#undef pci_ss_info_103c_703d +#define pci_ss_info_103c_703d pci_ss_info_14e4_16ac_103c_703d +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_16c6_10b7_1100 = + {0x10b7, 0x1100, pci_subsys_14e4_16c6_10b7_1100, 0}; +#undef pci_ss_info_10b7_1100 +#define pci_ss_info_10b7_1100 pci_ss_info_14e4_16c6_10b7_1100 +static const pciSubsystemInfo pci_ss_info_14e4_16c6_14e4_000c = + {0x14e4, 0x000c, pci_subsys_14e4_16c6_14e4_000c, 0}; +#undef pci_ss_info_14e4_000c +#define pci_ss_info_14e4_000c pci_ss_info_14e4_16c6_14e4_000c +static const pciSubsystemInfo pci_ss_info_14e4_16c6_14e4_8009 = + {0x14e4, 0x8009, pci_subsys_14e4_16c6_14e4_8009, 0}; +#undef pci_ss_info_14e4_8009 +#define pci_ss_info_14e4_8009 pci_ss_info_14e4_16c6_14e4_8009 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16c7_0e11_00ca = + {0x0e11, 0x00ca, pci_subsys_14e4_16c7_0e11_00ca, 0}; +#undef pci_ss_info_0e11_00ca +#define pci_ss_info_0e11_00ca pci_ss_info_14e4_16c7_0e11_00ca +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16c7_0e11_00cb = + {0x0e11, 0x00cb, pci_subsys_14e4_16c7_0e11_00cb, 0}; +#undef pci_ss_info_0e11_00cb +#define pci_ss_info_0e11_00cb pci_ss_info_14e4_16c7_0e11_00cb +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16c7_103c_12c3 = + {0x103c, 0x12c3, pci_subsys_14e4_16c7_103c_12c3, 0}; +#undef pci_ss_info_103c_12c3 +#define pci_ss_info_103c_12c3 pci_ss_info_14e4_16c7_103c_12c3 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_16c7_103c_12ca = + {0x103c, 0x12ca, pci_subsys_14e4_16c7_103c_12ca, 0}; +#undef pci_ss_info_103c_12ca +#define pci_ss_info_103c_12ca pci_ss_info_14e4_16c7_103c_12ca +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_16c7_14e4_0009 = + {0x14e4, 0x0009, pci_subsys_14e4_16c7_14e4_0009, 0}; +#undef pci_ss_info_14e4_0009 +#define pci_ss_info_14e4_0009 pci_ss_info_14e4_16c7_14e4_0009 +static const pciSubsystemInfo pci_ss_info_14e4_16c7_14e4_000a = + {0x14e4, 0x000a, pci_subsys_14e4_16c7_14e4_000a, 0}; +#undef pci_ss_info_14e4_000a +#define pci_ss_info_14e4_000a pci_ss_info_14e4_16c7_14e4_000a +#endif +static const pciSubsystemInfo pci_ss_info_14e4_170c_1028_0188 = + {0x1028, 0x0188, pci_subsys_14e4_170c_1028_0188, 0}; +#undef pci_ss_info_1028_0188 +#define pci_ss_info_1028_0188 pci_ss_info_14e4_170c_1028_0188 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_170c_1028_0196 = + {0x1028, 0x0196, pci_subsys_14e4_170c_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_14e4_170c_1028_0196 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_170c_103c_099c = + {0x103c, 0x099c, pci_subsys_14e4_170c_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_14e4_170c_103c_099c +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_170d_1014_0545 = + {0x1014, 0x0545, pci_subsys_14e4_170d_1014_0545, 0}; +#undef pci_ss_info_1014_0545 +#define pci_ss_info_1014_0545 pci_ss_info_14e4_170d_1014_0545 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4301_1028_0407 = + {0x1028, 0x0407, pci_subsys_14e4_4301_1028_0407, 0}; +#undef pci_ss_info_1028_0407 +#define pci_ss_info_1028_0407 pci_ss_info_14e4_4301_1028_0407 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_4301_1043_0120 = + {0x1043, 0x0120, pci_subsys_14e4_4301_1043_0120, 0}; +#undef pci_ss_info_1043_0120 +#define pci_ss_info_1043_0120 pci_ss_info_14e4_4301_1043_0120 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4318_103c_1356 = + {0x103c, 0x1356, pci_subsys_14e4_4318_103c_1356, 0}; +#undef pci_ss_info_103c_1356 +#define pci_ss_info_103c_1356 pci_ss_info_14e4_4318_103c_1356 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_4318_1043_120f = + {0x1043, 0x120f, pci_subsys_14e4_4318_1043_120f, 0}; +#undef pci_ss_info_1043_120f +#define pci_ss_info_1043_120f pci_ss_info_14e4_4318_1043_120f +static const pciSubsystemInfo pci_ss_info_14e4_4318_1468_0311 = + {0x1468, 0x0311, pci_subsys_14e4_4318_1468_0311, 0}; +#undef pci_ss_info_1468_0311 +#define pci_ss_info_1468_0311 pci_ss_info_14e4_4318_1468_0311 +static const pciSubsystemInfo pci_ss_info_14e4_4318_1468_0312 = + {0x1468, 0x0312, pci_subsys_14e4_4318_1468_0312, 0}; +#undef pci_ss_info_1468_0312 +#define pci_ss_info_1468_0312 pci_ss_info_14e4_4318_1468_0312 +static const pciSubsystemInfo pci_ss_info_14e4_4318_14e4_0449 = + {0x14e4, 0x0449, pci_subsys_14e4_4318_14e4_0449, 0}; +#undef pci_ss_info_14e4_0449 +#define pci_ss_info_14e4_0449 pci_ss_info_14e4_4318_14e4_0449 +static const pciSubsystemInfo pci_ss_info_14e4_4318_14e4_4318 = + {0x14e4, 0x4318, pci_subsys_14e4_4318_14e4_4318, 0}; +#undef pci_ss_info_14e4_4318 +#define pci_ss_info_14e4_4318 pci_ss_info_14e4_4318_14e4_4318 +static const pciSubsystemInfo pci_ss_info_14e4_4318_16ec_0119 = + {0x16ec, 0x0119, pci_subsys_14e4_4318_16ec_0119, 0}; +#undef pci_ss_info_16ec_0119 +#define pci_ss_info_16ec_0119 pci_ss_info_14e4_4318_16ec_0119 +static const pciSubsystemInfo pci_ss_info_14e4_4318_1737_0048 = + {0x1737, 0x0048, pci_subsys_14e4_4318_1737_0048, 0}; +#undef pci_ss_info_1737_0048 +#define pci_ss_info_1737_0048 pci_ss_info_14e4_4318_1737_0048 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4320_1028_0001 = + {0x1028, 0x0001, pci_subsys_14e4_4320_1028_0001, 0}; +#undef pci_ss_info_1028_0001 +#define pci_ss_info_1028_0001 pci_ss_info_14e4_4320_1028_0001 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4320_1028_0003 = + {0x1028, 0x0003, pci_subsys_14e4_4320_1028_0003, 0}; +#undef pci_ss_info_1028_0003 +#define pci_ss_info_1028_0003 pci_ss_info_14e4_4320_1028_0003 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4320_103c_12f4 = + {0x103c, 0x12f4, pci_subsys_14e4_4320_103c_12f4, 0}; +#undef pci_ss_info_103c_12f4 +#define pci_ss_info_103c_12f4 pci_ss_info_14e4_4320_103c_12f4 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4320_103c_12fa = + {0x103c, 0x12fa, pci_subsys_14e4_4320_103c_12fa, 0}; +#undef pci_ss_info_103c_12fa +#define pci_ss_info_103c_12fa pci_ss_info_14e4_4320_103c_12fa +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_4320_1043_100f = + {0x1043, 0x100f, pci_subsys_14e4_4320_1043_100f, 0}; +#undef pci_ss_info_1043_100f +#define pci_ss_info_1043_100f pci_ss_info_14e4_4320_1043_100f +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4320_1057_7025 = + {0x1057, 0x7025, pci_subsys_14e4_4320_1057_7025, 0}; +#undef pci_ss_info_1057_7025 +#define pci_ss_info_1057_7025 pci_ss_info_14e4_4320_1057_7025 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_4320_106b_004e = + {0x106b, 0x004e, pci_subsys_14e4_4320_106b_004e, 0}; +#undef pci_ss_info_106b_004e +#define pci_ss_info_106b_004e pci_ss_info_14e4_4320_106b_004e +static const pciSubsystemInfo pci_ss_info_14e4_4320_1154_0330 = + {0x1154, 0x0330, pci_subsys_14e4_4320_1154_0330, 0}; +#undef pci_ss_info_1154_0330 +#define pci_ss_info_1154_0330 pci_ss_info_14e4_4320_1154_0330 +static const pciSubsystemInfo pci_ss_info_14e4_4320_144f_7050 = + {0x144f, 0x7050, pci_subsys_14e4_4320_144f_7050, 0}; +#undef pci_ss_info_144f_7050 +#define pci_ss_info_144f_7050 pci_ss_info_14e4_4320_144f_7050 +static const pciSubsystemInfo pci_ss_info_14e4_4320_14e4_4320 = + {0x14e4, 0x4320, pci_subsys_14e4_4320_14e4_4320, 0}; +#undef pci_ss_info_14e4_4320 +#define pci_ss_info_14e4_4320 pci_ss_info_14e4_4320_14e4_4320 +static const pciSubsystemInfo pci_ss_info_14e4_4320_1737_4320 = + {0x1737, 0x4320, pci_subsys_14e4_4320_1737_4320, 0}; +#undef pci_ss_info_1737_4320 +#define pci_ss_info_1737_4320 pci_ss_info_14e4_4320_1737_4320 +static const pciSubsystemInfo pci_ss_info_14e4_4320_1799_7001 = + {0x1799, 0x7001, pci_subsys_14e4_4320_1799_7001, 0}; +#undef pci_ss_info_1799_7001 +#define pci_ss_info_1799_7001 pci_ss_info_14e4_4320_1799_7001 +static const pciSubsystemInfo pci_ss_info_14e4_4320_1799_7010 = + {0x1799, 0x7010, pci_subsys_14e4_4320_1799_7010, 0}; +#undef pci_ss_info_1799_7010 +#define pci_ss_info_1799_7010 pci_ss_info_14e4_4320_1799_7010 +static const pciSubsystemInfo pci_ss_info_14e4_4320_1799_7011 = + {0x1799, 0x7011, pci_subsys_14e4_4320_1799_7011, 0}; +#undef pci_ss_info_1799_7011 +#define pci_ss_info_1799_7011 pci_ss_info_14e4_4320_1799_7011 +static const pciSubsystemInfo pci_ss_info_14e4_4320_185f_1220 = + {0x185f, 0x1220, pci_subsys_14e4_4320_185f_1220, 0}; +#undef pci_ss_info_185f_1220 +#define pci_ss_info_185f_1220 pci_ss_info_14e4_4320_185f_1220 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4324_1028_0001 = + {0x1028, 0x0001, pci_subsys_14e4_4324_1028_0001, 0}; +#undef pci_ss_info_1028_0001 +#define pci_ss_info_1028_0001 pci_ss_info_14e4_4324_1028_0001 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4324_1028_0003 = + {0x1028, 0x0003, pci_subsys_14e4_4324_1028_0003, 0}; +#undef pci_ss_info_1028_0003 +#define pci_ss_info_1028_0003 pci_ss_info_14e4_4324_1028_0003 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_4325_1414_0003 = + {0x1414, 0x0003, pci_subsys_14e4_4325_1414_0003, 0}; +#undef pci_ss_info_1414_0003 +#define pci_ss_info_1414_0003 pci_ss_info_14e4_4325_1414_0003 +static const pciSubsystemInfo pci_ss_info_14e4_4325_1414_0004 = + {0x1414, 0x0004, pci_subsys_14e4_4325_1414_0004, 0}; +#undef pci_ss_info_1414_0004 +#define pci_ss_info_1414_0004 pci_ss_info_14e4_4325_1414_0004 +#endif +static const pciSubsystemInfo pci_ss_info_14e4_4401_103c_08b0 = + {0x103c, 0x08b0, pci_subsys_14e4_4401_103c_08b0, 0}; +#undef pci_ss_info_103c_08b0 +#define pci_ss_info_103c_08b0 pci_ss_info_14e4_4401_103c_08b0 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14e4_4401_1043_80a8 = + {0x1043, 0x80a8, pci_subsys_14e4_4401_1043_80a8, 0}; +#undef pci_ss_info_1043_80a8 +#define pci_ss_info_1043_80a8 pci_ss_info_14e4_4401_1043_80a8 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1033_1033_8077 = + {0x1033, 0x8077, pci_subsys_14f1_1033_1033_8077, 0}; +#undef pci_ss_info_1033_8077 +#define pci_ss_info_1033_8077 pci_ss_info_14f1_1033_1033_8077 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14f1_1033_122d_4027 = + {0x122d, 0x4027, pci_subsys_14f1_1033_122d_4027, 0}; +#undef pci_ss_info_122d_4027 +#define pci_ss_info_122d_4027 pci_ss_info_14f1_1033_122d_4027 +static const pciSubsystemInfo pci_ss_info_14f1_1033_122d_4030 = + {0x122d, 0x4030, pci_subsys_14f1_1033_122d_4030, 0}; +#undef pci_ss_info_122d_4030 +#define pci_ss_info_122d_4030 pci_ss_info_14f1_1033_122d_4030 +static const pciSubsystemInfo pci_ss_info_14f1_1033_122d_4034 = + {0x122d, 0x4034, pci_subsys_14f1_1033_122d_4034, 0}; +#undef pci_ss_info_122d_4034 +#define pci_ss_info_122d_4034 pci_ss_info_14f1_1033_122d_4034 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_020d = + {0x13e0, 0x020d, pci_subsys_14f1_1033_13e0_020d, 0}; +#undef pci_ss_info_13e0_020d +#define pci_ss_info_13e0_020d pci_ss_info_14f1_1033_13e0_020d +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_020e = + {0x13e0, 0x020e, pci_subsys_14f1_1033_13e0_020e, 0}; +#undef pci_ss_info_13e0_020e +#define pci_ss_info_13e0_020e pci_ss_info_14f1_1033_13e0_020e +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_0261 = + {0x13e0, 0x0261, pci_subsys_14f1_1033_13e0_0261, 0}; +#undef pci_ss_info_13e0_0261 +#define pci_ss_info_13e0_0261 pci_ss_info_14f1_1033_13e0_0261 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_0290 = + {0x13e0, 0x0290, pci_subsys_14f1_1033_13e0_0290, 0}; +#undef pci_ss_info_13e0_0290 +#define pci_ss_info_13e0_0290 pci_ss_info_14f1_1033_13e0_0290 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_02a0 = + {0x13e0, 0x02a0, pci_subsys_14f1_1033_13e0_02a0, 0}; +#undef pci_ss_info_13e0_02a0 +#define pci_ss_info_13e0_02a0 pci_ss_info_14f1_1033_13e0_02a0 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_02b0 = + {0x13e0, 0x02b0, pci_subsys_14f1_1033_13e0_02b0, 0}; +#undef pci_ss_info_13e0_02b0 +#define pci_ss_info_13e0_02b0 pci_ss_info_14f1_1033_13e0_02b0 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_02c0 = + {0x13e0, 0x02c0, pci_subsys_14f1_1033_13e0_02c0, 0}; +#undef pci_ss_info_13e0_02c0 +#define pci_ss_info_13e0_02c0 pci_ss_info_14f1_1033_13e0_02c0 +static const pciSubsystemInfo pci_ss_info_14f1_1033_13e0_02d0 = + {0x13e0, 0x02d0, pci_subsys_14f1_1033_13e0_02d0, 0}; +#undef pci_ss_info_13e0_02d0 +#define pci_ss_info_13e0_02d0 pci_ss_info_14f1_1033_13e0_02d0 +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_1500 = + {0x144f, 0x1500, pci_subsys_14f1_1033_144f_1500, 0}; +#undef pci_ss_info_144f_1500 +#define pci_ss_info_144f_1500 pci_ss_info_14f1_1033_144f_1500 +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_1501 = + {0x144f, 0x1501, pci_subsys_14f1_1033_144f_1501, 0}; +#undef pci_ss_info_144f_1501 +#define pci_ss_info_144f_1501 pci_ss_info_14f1_1033_144f_1501 +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_150a = + {0x144f, 0x150a, pci_subsys_14f1_1033_144f_150a, 0}; +#undef pci_ss_info_144f_150a +#define pci_ss_info_144f_150a pci_ss_info_14f1_1033_144f_150a +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_150b = + {0x144f, 0x150b, pci_subsys_14f1_1033_144f_150b, 0}; +#undef pci_ss_info_144f_150b +#define pci_ss_info_144f_150b pci_ss_info_14f1_1033_144f_150b +static const pciSubsystemInfo pci_ss_info_14f1_1033_144f_1510 = + {0x144f, 0x1510, pci_subsys_14f1_1033_144f_1510, 0}; +#undef pci_ss_info_144f_1510 +#define pci_ss_info_144f_1510 pci_ss_info_14f1_1033_144f_1510 +static const pciSubsystemInfo pci_ss_info_14f1_1035_10cf_1098 = + {0x10cf, 0x1098, pci_subsys_14f1_1035_10cf_1098, 0}; +#undef pci_ss_info_10cf_1098 +#define pci_ss_info_10cf_1098 pci_ss_info_14f1_1035_10cf_1098 +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1036_104d_8067 = + {0x104d, 0x8067, pci_subsys_14f1_1036_104d_8067, 0}; +#undef pci_ss_info_104d_8067 +#define pci_ss_info_104d_8067 pci_ss_info_14f1_1036_104d_8067 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14f1_1036_122d_4029 = + {0x122d, 0x4029, pci_subsys_14f1_1036_122d_4029, 0}; +#undef pci_ss_info_122d_4029 +#define pci_ss_info_122d_4029 pci_ss_info_14f1_1036_122d_4029 +static const pciSubsystemInfo pci_ss_info_14f1_1036_122d_4031 = + {0x122d, 0x4031, pci_subsys_14f1_1036_122d_4031, 0}; +#undef pci_ss_info_122d_4031 +#define pci_ss_info_122d_4031 pci_ss_info_14f1_1036_122d_4031 +static const pciSubsystemInfo pci_ss_info_14f1_1036_13e0_0209 = + {0x13e0, 0x0209, pci_subsys_14f1_1036_13e0_0209, 0}; +#undef pci_ss_info_13e0_0209 +#define pci_ss_info_13e0_0209 pci_ss_info_14f1_1036_13e0_0209 +static const pciSubsystemInfo pci_ss_info_14f1_1036_13e0_020a = + {0x13e0, 0x020a, pci_subsys_14f1_1036_13e0_020a, 0}; +#undef pci_ss_info_13e0_020a +#define pci_ss_info_13e0_020a pci_ss_info_14f1_1036_13e0_020a +static const pciSubsystemInfo pci_ss_info_14f1_1036_13e0_0260 = + {0x13e0, 0x0260, pci_subsys_14f1_1036_13e0_0260, 0}; +#undef pci_ss_info_13e0_0260 +#define pci_ss_info_13e0_0260 pci_ss_info_14f1_1036_13e0_0260 +static const pciSubsystemInfo pci_ss_info_14f1_1036_13e0_0270 = + {0x13e0, 0x0270, pci_subsys_14f1_1036_13e0_0270, 0}; +#undef pci_ss_info_13e0_0270 +#define pci_ss_info_13e0_0270 pci_ss_info_14f1_1036_13e0_0270 +static const pciSubsystemInfo pci_ss_info_14f1_1066_122d_4033 = + {0x122d, 0x4033, pci_subsys_14f1_1066_122d_4033, 0}; +#undef pci_ss_info_122d_4033 +#define pci_ss_info_122d_4033 pci_ss_info_14f1_1066_122d_4033 +static const pciSubsystemInfo pci_ss_info_14f1_1453_13e0_0240 = + {0x13e0, 0x0240, pci_subsys_14f1_1453_13e0_0240, 0}; +#undef pci_ss_info_13e0_0240 +#define pci_ss_info_13e0_0240 pci_ss_info_14f1_1453_13e0_0240 +static const pciSubsystemInfo pci_ss_info_14f1_1453_13e0_0250 = + {0x13e0, 0x0250, pci_subsys_14f1_1453_13e0_0250, 0}; +#undef pci_ss_info_13e0_0250 +#define pci_ss_info_13e0_0250 pci_ss_info_14f1_1453_13e0_0250 +static const pciSubsystemInfo pci_ss_info_14f1_1453_144f_1502 = + {0x144f, 0x1502, pci_subsys_14f1_1453_144f_1502, 0}; +#undef pci_ss_info_144f_1502 +#define pci_ss_info_144f_1502 pci_ss_info_14f1_1453_144f_1502 +static const pciSubsystemInfo pci_ss_info_14f1_1453_144f_1503 = + {0x144f, 0x1503, pci_subsys_14f1_1453_144f_1503, 0}; +#undef pci_ss_info_144f_1503 +#define pci_ss_info_144f_1503 pci_ss_info_14f1_1453_144f_1503 +static const pciSubsystemInfo pci_ss_info_14f1_1456_122d_4035 = + {0x122d, 0x4035, pci_subsys_14f1_1456_122d_4035, 0}; +#undef pci_ss_info_122d_4035 +#define pci_ss_info_122d_4035 pci_ss_info_14f1_1456_122d_4035 +static const pciSubsystemInfo pci_ss_info_14f1_1456_122d_4302 = + {0x122d, 0x4302, pci_subsys_14f1_1456_122d_4302, 0}; +#undef pci_ss_info_122d_4302 +#define pci_ss_info_122d_4302 pci_ss_info_14f1_1456_122d_4302 +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1803_0e11_0023 = + {0x0e11, 0x0023, pci_subsys_14f1_1803_0e11_0023, 0}; +#undef pci_ss_info_0e11_0023 +#define pci_ss_info_0e11_0023 pci_ss_info_14f1_1803_0e11_0023 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1803_0e11_0043 = + {0x0e11, 0x0043, pci_subsys_14f1_1803_0e11_0043, 0}; +#undef pci_ss_info_0e11_0043 +#define pci_ss_info_0e11_0043 pci_ss_info_14f1_1803_0e11_0043 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1815_0e11_0022 = + {0x0e11, 0x0022, pci_subsys_14f1_1815_0e11_0022, 0}; +#undef pci_ss_info_0e11_0022 +#define pci_ss_info_0e11_0022 pci_ss_info_14f1_1815_0e11_0022 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_1815_0e11_0042 = + {0x0e11, 0x0042, pci_subsys_14f1_1815_0e11_0042, 0}; +#undef pci_ss_info_0e11_0042 +#define pci_ss_info_0e11_0042 pci_ss_info_14f1_1815_0e11_0042 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_0e11_b195 = + {0x0e11, 0xb195, pci_subsys_14f1_2013_0e11_b195, 0}; +#undef pci_ss_info_0e11_b195 +#define pci_ss_info_0e11_b195 pci_ss_info_14f1_2013_0e11_b195 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_0e11_b196 = + {0x0e11, 0xb196, pci_subsys_14f1_2013_0e11_b196, 0}; +#undef pci_ss_info_0e11_b196 +#define pci_ss_info_0e11_b196 pci_ss_info_14f1_2013_0e11_b196 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_0e11_b1be = + {0x0e11, 0xb1be, pci_subsys_14f1_2013_0e11_b1be, 0}; +#undef pci_ss_info_0e11_b1be +#define pci_ss_info_0e11_b1be pci_ss_info_14f1_2013_0e11_b1be +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_1025_8013 = + {0x1025, 0x8013, pci_subsys_14f1_2013_1025_8013, 0}; +#undef pci_ss_info_1025_8013 +#define pci_ss_info_1025_8013 pci_ss_info_14f1_2013_1025_8013 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_1033_809d = + {0x1033, 0x809d, pci_subsys_14f1_2013_1033_809d, 0}; +#undef pci_ss_info_1033_809d +#define pci_ss_info_1033_809d pci_ss_info_14f1_2013_1033_809d +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2013_1033_80bc = + {0x1033, 0x80bc, pci_subsys_14f1_2013_1033_80bc, 0}; +#undef pci_ss_info_1033_80bc +#define pci_ss_info_1033_80bc pci_ss_info_14f1_2013_1033_80bc +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14f1_2013_155d_6793 = + {0x155d, 0x6793, pci_subsys_14f1_2013_155d_6793, 0}; +#undef pci_ss_info_155d_6793 +#define pci_ss_info_155d_6793 pci_ss_info_14f1_2013_155d_6793 +static const pciSubsystemInfo pci_ss_info_14f1_2013_155d_8850 = + {0x155d, 0x8850, pci_subsys_14f1_2013_155d_8850, 0}; +#undef pci_ss_info_155d_8850 +#define pci_ss_info_155d_8850 pci_ss_info_14f1_2013_155d_8850 +static const pciSubsystemInfo pci_ss_info_14f1_2045_14f1_2045 = + {0x14f1, 0x2045, pci_subsys_14f1_2045_14f1_2045, 0}; +#undef pci_ss_info_14f1_2045 +#define pci_ss_info_14f1_2045 pci_ss_info_14f1_2045_14f1_2045 +static const pciSubsystemInfo pci_ss_info_14f1_2093_155d_2f07 = + {0x155d, 0x2f07, pci_subsys_14f1_2093_155d_2f07, 0}; +#undef pci_ss_info_155d_2f07 +#define pci_ss_info_155d_2f07 pci_ss_info_14f1_2093_155d_2f07 +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2443_104d_8075 = + {0x104d, 0x8075, pci_subsys_14f1_2443_104d_8075, 0}; +#undef pci_ss_info_104d_8075 +#define pci_ss_info_104d_8075 pci_ss_info_14f1_2443_104d_8075 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2443_104d_8083 = + {0x104d, 0x8083, pci_subsys_14f1_2443_104d_8083, 0}; +#undef pci_ss_info_104d_8083 +#define pci_ss_info_104d_8083 pci_ss_info_14f1_2443_104d_8083 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_2443_104d_8097 = + {0x104d, 0x8097, pci_subsys_14f1_2443_104d_8097, 0}; +#undef pci_ss_info_104d_8097 +#define pci_ss_info_104d_8097 pci_ss_info_14f1_2443_104d_8097 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14f1_2f00_13e0_8d84 = + {0x13e0, 0x8d84, pci_subsys_14f1_2f00_13e0_8d84, 0}; +#undef pci_ss_info_13e0_8d84 +#define pci_ss_info_13e0_8d84 pci_ss_info_14f1_2f00_13e0_8d84 +static const pciSubsystemInfo pci_ss_info_14f1_2f00_13e0_8d85 = + {0x13e0, 0x8d85, pci_subsys_14f1_2f00_13e0_8d85, 0}; +#undef pci_ss_info_13e0_8d85 +#define pci_ss_info_13e0_8d85 pci_ss_info_14f1_2f00_13e0_8d85 +static const pciSubsystemInfo pci_ss_info_14f1_2f00_14f1_2004 = + {0x14f1, 0x2004, pci_subsys_14f1_2f00_14f1_2004, 0}; +#undef pci_ss_info_14f1_2004 +#define pci_ss_info_14f1_2004 pci_ss_info_14f1_2f00_14f1_2004 +static const pciSubsystemInfo pci_ss_info_14f1_8800_0070_2801 = + {0x0070, 0x2801, pci_subsys_14f1_8800_0070_2801, 0}; +#undef pci_ss_info_0070_2801 +#define pci_ss_info_0070_2801 pci_ss_info_14f1_8800_0070_2801 +static const pciSubsystemInfo pci_ss_info_14f1_8800_0070_3401 = + {0x0070, 0x3401, pci_subsys_14f1_8800_0070_3401, 0}; +#undef pci_ss_info_0070_3401 +#define pci_ss_info_0070_3401 pci_ss_info_14f1_8800_0070_3401 +static const pciSubsystemInfo pci_ss_info_14f1_8800_0070_9001 = + {0x0070, 0x9001, pci_subsys_14f1_8800_0070_9001, 0}; +#undef pci_ss_info_0070_9001 +#define pci_ss_info_0070_9001 pci_ss_info_14f1_8800_0070_9001 +static const pciSubsystemInfo pci_ss_info_14f1_8800_0070_9200 = + {0x0070, 0x9200, pci_subsys_14f1_8800_0070_9200, 0}; +#undef pci_ss_info_0070_9200 +#define pci_ss_info_0070_9200 pci_ss_info_14f1_8800_0070_9200 +static const pciSubsystemInfo pci_ss_info_14f1_8800_0070_9202 = + {0x0070, 0x9202, pci_subsys_14f1_8800_0070_9202, 0}; +#undef pci_ss_info_0070_9202 +#define pci_ss_info_0070_9202 pci_ss_info_14f1_8800_0070_9202 +static const pciSubsystemInfo pci_ss_info_14f1_8800_0070_9402 = + {0x0070, 0x9402, pci_subsys_14f1_8800_0070_9402, 0}; +#undef pci_ss_info_0070_9402 +#define pci_ss_info_0070_9402 pci_ss_info_14f1_8800_0070_9402 +static const pciSubsystemInfo pci_ss_info_14f1_8800_0070_9802 = + {0x0070, 0x9802, pci_subsys_14f1_8800_0070_9802, 0}; +#undef pci_ss_info_0070_9802 +#define pci_ss_info_0070_9802 pci_ss_info_14f1_8800_0070_9802 +#endif +static const pciSubsystemInfo pci_ss_info_14f1_8800_1002_00f8 = + {0x1002, 0x00f8, pci_subsys_14f1_8800_1002_00f8, 0}; +#undef pci_ss_info_1002_00f8 +#define pci_ss_info_1002_00f8 pci_ss_info_14f1_8800_1002_00f8 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_14f1_8800_1002_a101 = + {0x1002, 0xa101, pci_subsys_14f1_8800_1002_a101, 0}; +#undef pci_ss_info_1002_a101 +#define pci_ss_info_1002_a101 pci_ss_info_14f1_8800_1002_a101 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_14f1_8800_1043_4823 = + {0x1043, 0x4823, pci_subsys_14f1_8800_1043_4823, 0}; +#undef pci_ss_info_1043_4823 +#define pci_ss_info_1043_4823 pci_ss_info_14f1_8800_1043_4823 +static const pciSubsystemInfo pci_ss_info_14f1_8800_107d_6613 = + {0x107d, 0x6613, pci_subsys_14f1_8800_107d_6613, 0}; +#undef pci_ss_info_107d_6613 +#define pci_ss_info_107d_6613 pci_ss_info_14f1_8800_107d_6613 +static const pciSubsystemInfo pci_ss_info_14f1_8800_107d_6620 = + {0x107d, 0x6620, pci_subsys_14f1_8800_107d_6620, 0}; +#undef pci_ss_info_107d_6620 +#define pci_ss_info_107d_6620 pci_ss_info_14f1_8800_107d_6620 +static const pciSubsystemInfo pci_ss_info_14f1_8800_107d_663c = + {0x107d, 0x663c, pci_subsys_14f1_8800_107d_663c, 0}; +#undef pci_ss_info_107d_663c +#define pci_ss_info_107d_663c pci_ss_info_14f1_8800_107d_663c +static const pciSubsystemInfo pci_ss_info_14f1_8800_107d_665f = + {0x107d, 0x665f, pci_subsys_14f1_8800_107d_665f, 0}; +#undef pci_ss_info_107d_665f +#define pci_ss_info_107d_665f pci_ss_info_14f1_8800_107d_665f +static const pciSubsystemInfo pci_ss_info_14f1_8800_10fc_d003 = + {0x10fc, 0xd003, pci_subsys_14f1_8800_10fc_d003, 0}; +#undef pci_ss_info_10fc_d003 +#define pci_ss_info_10fc_d003 pci_ss_info_14f1_8800_10fc_d003 +static const pciSubsystemInfo pci_ss_info_14f1_8800_10fc_d035 = + {0x10fc, 0xd035, pci_subsys_14f1_8800_10fc_d035, 0}; +#undef pci_ss_info_10fc_d035 +#define pci_ss_info_10fc_d035 pci_ss_info_14f1_8800_10fc_d035 +static const pciSubsystemInfo pci_ss_info_14f1_8800_1421_0334 = + {0x1421, 0x0334, pci_subsys_14f1_8800_1421_0334, 0}; +#undef pci_ss_info_1421_0334 +#define pci_ss_info_1421_0334 pci_ss_info_14f1_8800_1421_0334 +static const pciSubsystemInfo pci_ss_info_14f1_8800_1461_000a = + {0x1461, 0x000a, pci_subsys_14f1_8800_1461_000a, 0}; +#undef pci_ss_info_1461_000a +#define pci_ss_info_1461_000a pci_ss_info_14f1_8800_1461_000a +static const pciSubsystemInfo pci_ss_info_14f1_8800_1461_000b = + {0x1461, 0x000b, pci_subsys_14f1_8800_1461_000b, 0}; +#undef pci_ss_info_1461_000b +#define pci_ss_info_1461_000b pci_ss_info_14f1_8800_1461_000b +static const pciSubsystemInfo pci_ss_info_14f1_8800_1461_8011 = + {0x1461, 0x8011, pci_subsys_14f1_8800_1461_8011, 0}; +#undef pci_ss_info_1461_8011 +#define pci_ss_info_1461_8011 pci_ss_info_14f1_8800_1461_8011 +static const pciSubsystemInfo pci_ss_info_14f1_8800_1462_8606 = + {0x1462, 0x8606, pci_subsys_14f1_8800_1462_8606, 0}; +#undef pci_ss_info_1462_8606 +#define pci_ss_info_1462_8606 pci_ss_info_14f1_8800_1462_8606 +static const pciSubsystemInfo pci_ss_info_14f1_8800_14c7_0107 = + {0x14c7, 0x0107, pci_subsys_14f1_8800_14c7_0107, 0}; +#undef pci_ss_info_14c7_0107 +#define pci_ss_info_14c7_0107 pci_ss_info_14f1_8800_14c7_0107 +static const pciSubsystemInfo pci_ss_info_14f1_8800_14f1_0187 = + {0x14f1, 0x0187, pci_subsys_14f1_8800_14f1_0187, 0}; +#undef pci_ss_info_14f1_0187 +#define pci_ss_info_14f1_0187 pci_ss_info_14f1_8800_14f1_0187 +static const pciSubsystemInfo pci_ss_info_14f1_8800_14f1_0342 = + {0x14f1, 0x0342, pci_subsys_14f1_8800_14f1_0342, 0}; +#undef pci_ss_info_14f1_0342 +#define pci_ss_info_14f1_0342 pci_ss_info_14f1_8800_14f1_0342 +static const pciSubsystemInfo pci_ss_info_14f1_8800_153b_1166 = + {0x153b, 0x1166, pci_subsys_14f1_8800_153b_1166, 0}; +#undef pci_ss_info_153b_1166 +#define pci_ss_info_153b_1166 pci_ss_info_14f1_8800_153b_1166 +static const pciSubsystemInfo pci_ss_info_14f1_8800_1540_2580 = + {0x1540, 0x2580, pci_subsys_14f1_8800_1540_2580, 0}; +#undef pci_ss_info_1540_2580 +#define pci_ss_info_1540_2580 pci_ss_info_14f1_8800_1540_2580 +static const pciSubsystemInfo pci_ss_info_14f1_8800_1554_4811 = + {0x1554, 0x4811, pci_subsys_14f1_8800_1554_4811, 0}; +#undef pci_ss_info_1554_4811 +#define pci_ss_info_1554_4811 pci_ss_info_14f1_8800_1554_4811 +static const pciSubsystemInfo pci_ss_info_14f1_8800_1554_4813 = + {0x1554, 0x4813, pci_subsys_14f1_8800_1554_4813, 0}; +#undef pci_ss_info_1554_4813 +#define pci_ss_info_1554_4813 pci_ss_info_14f1_8800_1554_4813 +static const pciSubsystemInfo pci_ss_info_14f1_8800_17de_08a1 = + {0x17de, 0x08a1, pci_subsys_14f1_8800_17de_08a1, 0}; +#undef pci_ss_info_17de_08a1 +#define pci_ss_info_17de_08a1 pci_ss_info_14f1_8800_17de_08a1 +static const pciSubsystemInfo pci_ss_info_14f1_8800_17de_08a6 = + {0x17de, 0x08a6, pci_subsys_14f1_8800_17de_08a6, 0}; +#undef pci_ss_info_17de_08a6 +#define pci_ss_info_17de_08a6 pci_ss_info_14f1_8800_17de_08a6 +static const pciSubsystemInfo pci_ss_info_14f1_8800_17de_08b2 = + {0x17de, 0x08b2, pci_subsys_14f1_8800_17de_08b2, 0}; +#undef pci_ss_info_17de_08b2 +#define pci_ss_info_17de_08b2 pci_ss_info_14f1_8800_17de_08b2 +static const pciSubsystemInfo pci_ss_info_14f1_8800_17de_a8a6 = + {0x17de, 0xa8a6, pci_subsys_14f1_8800_17de_a8a6, 0}; +#undef pci_ss_info_17de_a8a6 +#define pci_ss_info_17de_a8a6 pci_ss_info_14f1_8800_17de_a8a6 +static const pciSubsystemInfo pci_ss_info_14f1_8800_1822_0025 = + {0x1822, 0x0025, pci_subsys_14f1_8800_1822_0025, 0}; +#undef pci_ss_info_1822_0025 +#define pci_ss_info_1822_0025 pci_ss_info_14f1_8800_1822_0025 +static const pciSubsystemInfo pci_ss_info_14f1_8800_18ac_d500 = + {0x18ac, 0xd500, pci_subsys_14f1_8800_18ac_d500, 0}; +#undef pci_ss_info_18ac_d500 +#define pci_ss_info_18ac_d500 pci_ss_info_14f1_8800_18ac_d500 +static const pciSubsystemInfo pci_ss_info_14f1_8800_18ac_d810 = + {0x18ac, 0xd810, pci_subsys_14f1_8800_18ac_d810, 0}; +#undef pci_ss_info_18ac_d810 +#define pci_ss_info_18ac_d810 pci_ss_info_14f1_8800_18ac_d810 +static const pciSubsystemInfo pci_ss_info_14f1_8800_18ac_d820 = + {0x18ac, 0xd820, pci_subsys_14f1_8800_18ac_d820, 0}; +#undef pci_ss_info_18ac_d820 +#define pci_ss_info_18ac_d820 pci_ss_info_14f1_8800_18ac_d820 +static const pciSubsystemInfo pci_ss_info_14f1_8800_18ac_db00 = + {0x18ac, 0xdb00, pci_subsys_14f1_8800_18ac_db00, 0}; +#undef pci_ss_info_18ac_db00 +#define pci_ss_info_18ac_db00 pci_ss_info_14f1_8800_18ac_db00 +static const pciSubsystemInfo pci_ss_info_14f1_8800_18ac_db11 = + {0x18ac, 0xdb11, pci_subsys_14f1_8800_18ac_db11, 0}; +#undef pci_ss_info_18ac_db11 +#define pci_ss_info_18ac_db11 pci_ss_info_14f1_8800_18ac_db11 +static const pciSubsystemInfo pci_ss_info_14f1_8800_18ac_db50 = + {0x18ac, 0xdb50, pci_subsys_14f1_8800_18ac_db50, 0}; +#undef pci_ss_info_18ac_db50 +#define pci_ss_info_18ac_db50 pci_ss_info_14f1_8800_18ac_db50 +static const pciSubsystemInfo pci_ss_info_14f1_8800_7063_3000 = + {0x7063, 0x3000, pci_subsys_14f1_8800_7063_3000, 0}; +#undef pci_ss_info_7063_3000 +#define pci_ss_info_7063_3000 pci_ss_info_14f1_8800_7063_3000 +static const pciSubsystemInfo pci_ss_info_14f1_8801_0070_2801 = + {0x0070, 0x2801, pci_subsys_14f1_8801_0070_2801, 0}; +#undef pci_ss_info_0070_2801 +#define pci_ss_info_0070_2801 pci_ss_info_14f1_8801_0070_2801 +static const pciSubsystemInfo pci_ss_info_14f1_8802_0070_2801 = + {0x0070, 0x2801, pci_subsys_14f1_8802_0070_2801, 0}; +#undef pci_ss_info_0070_2801 +#define pci_ss_info_0070_2801 pci_ss_info_14f1_8802_0070_2801 +static const pciSubsystemInfo pci_ss_info_14f1_8802_0070_9002 = + {0x0070, 0x9002, pci_subsys_14f1_8802_0070_9002, 0}; +#undef pci_ss_info_0070_9002 +#define pci_ss_info_0070_9002 pci_ss_info_14f1_8802_0070_9002 +static const pciSubsystemInfo pci_ss_info_14f1_8802_1043_4823 = + {0x1043, 0x4823, pci_subsys_14f1_8802_1043_4823, 0}; +#undef pci_ss_info_1043_4823 +#define pci_ss_info_1043_4823 pci_ss_info_14f1_8802_1043_4823 +static const pciSubsystemInfo pci_ss_info_14f1_8802_107d_663c = + {0x107d, 0x663c, pci_subsys_14f1_8802_107d_663c, 0}; +#undef pci_ss_info_107d_663c +#define pci_ss_info_107d_663c pci_ss_info_14f1_8802_107d_663c +static const pciSubsystemInfo pci_ss_info_14f1_8802_14f1_0187 = + {0x14f1, 0x0187, pci_subsys_14f1_8802_14f1_0187, 0}; +#undef pci_ss_info_14f1_0187 +#define pci_ss_info_14f1_0187 pci_ss_info_14f1_8802_14f1_0187 +static const pciSubsystemInfo pci_ss_info_14f1_8802_17de_08a1 = + {0x17de, 0x08a1, pci_subsys_14f1_8802_17de_08a1, 0}; +#undef pci_ss_info_17de_08a1 +#define pci_ss_info_17de_08a1 pci_ss_info_14f1_8802_17de_08a1 +static const pciSubsystemInfo pci_ss_info_14f1_8802_17de_08a6 = + {0x17de, 0x08a6, pci_subsys_14f1_8802_17de_08a6, 0}; +#undef pci_ss_info_17de_08a6 +#define pci_ss_info_17de_08a6 pci_ss_info_14f1_8802_17de_08a6 +static const pciSubsystemInfo pci_ss_info_14f1_8802_18ac_d500 = + {0x18ac, 0xd500, pci_subsys_14f1_8802_18ac_d500, 0}; +#undef pci_ss_info_18ac_d500 +#define pci_ss_info_18ac_d500 pci_ss_info_14f1_8802_18ac_d500 +static const pciSubsystemInfo pci_ss_info_14f1_8802_18ac_d810 = + {0x18ac, 0xd810, pci_subsys_14f1_8802_18ac_d810, 0}; +#undef pci_ss_info_18ac_d810 +#define pci_ss_info_18ac_d810 pci_ss_info_14f1_8802_18ac_d810 +static const pciSubsystemInfo pci_ss_info_14f1_8802_18ac_d820 = + {0x18ac, 0xd820, pci_subsys_14f1_8802_18ac_d820, 0}; +#undef pci_ss_info_18ac_d820 +#define pci_ss_info_18ac_d820 pci_ss_info_14f1_8802_18ac_d820 +static const pciSubsystemInfo pci_ss_info_14f1_8802_18ac_db00 = + {0x18ac, 0xdb00, pci_subsys_14f1_8802_18ac_db00, 0}; +#undef pci_ss_info_18ac_db00 +#define pci_ss_info_18ac_db00 pci_ss_info_14f1_8802_18ac_db00 +static const pciSubsystemInfo pci_ss_info_14f1_8802_18ac_db10 = + {0x18ac, 0xdb10, pci_subsys_14f1_8802_18ac_db10, 0}; +#undef pci_ss_info_18ac_db10 +#define pci_ss_info_18ac_db10 pci_ss_info_14f1_8802_18ac_db10 +static const pciSubsystemInfo pci_ss_info_14f1_8802_7063_3000 = + {0x7063, 0x3000, pci_subsys_14f1_8802_7063_3000, 0}; +#undef pci_ss_info_7063_3000 +#define pci_ss_info_7063_3000 pci_ss_info_14f1_8802_7063_3000 +static const pciSubsystemInfo pci_ss_info_14f1_8804_0070_9002 = + {0x0070, 0x9002, pci_subsys_14f1_8804_0070_9002, 0}; +#undef pci_ss_info_0070_9002 +#define pci_ss_info_0070_9002 pci_ss_info_14f1_8804_0070_9002 +static const pciSubsystemInfo pci_ss_info_14f1_8811_0070_3401 = + {0x0070, 0x3401, pci_subsys_14f1_8811_0070_3401, 0}; +#undef pci_ss_info_0070_3401 +#define pci_ss_info_0070_3401 pci_ss_info_14f1_8811_0070_3401 +static const pciSubsystemInfo pci_ss_info_14f1_8811_1462_8606 = + {0x1462, 0x8606, pci_subsys_14f1_8811_1462_8606, 0}; +#undef pci_ss_info_1462_8606 +#define pci_ss_info_1462_8606 pci_ss_info_14f1_8811_1462_8606 +static const pciSubsystemInfo pci_ss_info_14f1_8811_18ac_d500 = + {0x18ac, 0xd500, pci_subsys_14f1_8811_18ac_d500, 0}; +#undef pci_ss_info_18ac_d500 +#define pci_ss_info_18ac_d500 pci_ss_info_14f1_8811_18ac_d500 +static const pciSubsystemInfo pci_ss_info_14f1_8811_18ac_d810 = + {0x18ac, 0xd810, pci_subsys_14f1_8811_18ac_d810, 0}; +#undef pci_ss_info_18ac_d810 +#define pci_ss_info_18ac_d810 pci_ss_info_14f1_8811_18ac_d810 +static const pciSubsystemInfo pci_ss_info_14f1_8811_18ac_d820 = + {0x18ac, 0xd820, pci_subsys_14f1_8811_18ac_d820, 0}; +#undef pci_ss_info_18ac_d820 +#define pci_ss_info_18ac_d820 pci_ss_info_14f1_8811_18ac_d820 +static const pciSubsystemInfo pci_ss_info_14f1_8811_18ac_db00 = + {0x18ac, 0xdb00, pci_subsys_14f1_8811_18ac_db00, 0}; +#undef pci_ss_info_18ac_db00 +#define pci_ss_info_18ac_db00 pci_ss_info_14f1_8811_18ac_db00 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1516_0803_1320_10bd = + {0x1320, 0x10bd, pci_subsys_1516_0803_1320_10bd, 0}; +#undef pci_ss_info_1320_10bd +#define pci_ss_info_1320_10bd pci_ss_info_1516_0803_1320_10bd +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0200 = + {0x1522, 0x0200, pci_subsys_1522_0100_1522_0200, 0}; +#undef pci_ss_info_1522_0200 +#define pci_ss_info_1522_0200 pci_ss_info_1522_0100_1522_0200 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0300 = + {0x1522, 0x0300, pci_subsys_1522_0100_1522_0300, 0}; +#undef pci_ss_info_1522_0300 +#define pci_ss_info_1522_0300 pci_ss_info_1522_0100_1522_0300 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0400 = + {0x1522, 0x0400, pci_subsys_1522_0100_1522_0400, 0}; +#undef pci_ss_info_1522_0400 +#define pci_ss_info_1522_0400 pci_ss_info_1522_0100_1522_0400 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0500 = + {0x1522, 0x0500, pci_subsys_1522_0100_1522_0500, 0}; +#undef pci_ss_info_1522_0500 +#define pci_ss_info_1522_0500 pci_ss_info_1522_0100_1522_0500 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0600 = + {0x1522, 0x0600, pci_subsys_1522_0100_1522_0600, 0}; +#undef pci_ss_info_1522_0600 +#define pci_ss_info_1522_0600 pci_ss_info_1522_0100_1522_0600 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0700 = + {0x1522, 0x0700, pci_subsys_1522_0100_1522_0700, 0}; +#undef pci_ss_info_1522_0700 +#define pci_ss_info_1522_0700 pci_ss_info_1522_0100_1522_0700 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0800 = + {0x1522, 0x0800, pci_subsys_1522_0100_1522_0800, 0}; +#undef pci_ss_info_1522_0800 +#define pci_ss_info_1522_0800 pci_ss_info_1522_0100_1522_0800 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0c00 = + {0x1522, 0x0c00, pci_subsys_1522_0100_1522_0c00, 0}; +#undef pci_ss_info_1522_0c00 +#define pci_ss_info_1522_0c00 pci_ss_info_1522_0100_1522_0c00 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_0d00 = + {0x1522, 0x0d00, pci_subsys_1522_0100_1522_0d00, 0}; +#undef pci_ss_info_1522_0d00 +#define pci_ss_info_1522_0d00 pci_ss_info_1522_0100_1522_0d00 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_1d00 = + {0x1522, 0x1d00, pci_subsys_1522_0100_1522_1d00, 0}; +#undef pci_ss_info_1522_1d00 +#define pci_ss_info_1522_1d00 pci_ss_info_1522_0100_1522_1d00 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2000 = + {0x1522, 0x2000, pci_subsys_1522_0100_1522_2000, 0}; +#undef pci_ss_info_1522_2000 +#define pci_ss_info_1522_2000 pci_ss_info_1522_0100_1522_2000 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2100 = + {0x1522, 0x2100, pci_subsys_1522_0100_1522_2100, 0}; +#undef pci_ss_info_1522_2100 +#define pci_ss_info_1522_2100 pci_ss_info_1522_0100_1522_2100 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2200 = + {0x1522, 0x2200, pci_subsys_1522_0100_1522_2200, 0}; +#undef pci_ss_info_1522_2200 +#define pci_ss_info_1522_2200 pci_ss_info_1522_0100_1522_2200 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2300 = + {0x1522, 0x2300, pci_subsys_1522_0100_1522_2300, 0}; +#undef pci_ss_info_1522_2300 +#define pci_ss_info_1522_2300 pci_ss_info_1522_0100_1522_2300 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2400 = + {0x1522, 0x2400, pci_subsys_1522_0100_1522_2400, 0}; +#undef pci_ss_info_1522_2400 +#define pci_ss_info_1522_2400 pci_ss_info_1522_0100_1522_2400 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2500 = + {0x1522, 0x2500, pci_subsys_1522_0100_1522_2500, 0}; +#undef pci_ss_info_1522_2500 +#define pci_ss_info_1522_2500 pci_ss_info_1522_0100_1522_2500 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2600 = + {0x1522, 0x2600, pci_subsys_1522_0100_1522_2600, 0}; +#undef pci_ss_info_1522_2600 +#define pci_ss_info_1522_2600 pci_ss_info_1522_0100_1522_2600 +static const pciSubsystemInfo pci_ss_info_1522_0100_1522_2700 = + {0x1522, 0x2700, pci_subsys_1522_0100_1522_2700, 0}; +#undef pci_ss_info_1522_2700 +#define pci_ss_info_1522_2700 pci_ss_info_1522_0100_1522_2700 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1524_0510_103c_006a = + {0x103c, 0x006a, pci_subsys_1524_0510_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_1524_0510_103c_006a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1524_1410_1025_003c = + {0x1025, 0x003c, pci_subsys_1524_1410_1025_003c, 0}; +#undef pci_ss_info_1025_003c +#define pci_ss_info_1025_003c pci_ss_info_1524_1410_1025_003c +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1524_1410_1025_005a = + {0x1025, 0x005a, pci_subsys_1524_1410_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_1524_1410_1025_005a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_1524_1411_103c_006a = + {0x103c, 0x006a, pci_subsys_1524_1411_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_1524_1411_103c_006a +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_167b_2102_187e_3406 = + {0x187e, 0x3406, pci_subsys_167b_2102_187e_3406, 0}; +#undef pci_ss_info_187e_3406 +#define pci_ss_info_187e_3406 pci_ss_info_167b_2102_187e_3406 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_168c_0013_1113_d301 = + {0x1113, 0xd301, pci_subsys_168c_0013_1113_d301, 0}; +#undef pci_ss_info_1113_d301 +#define pci_ss_info_1113_d301 pci_ss_info_168c_0013_1113_d301 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3202 = + {0x1186, 0x3202, pci_subsys_168c_0013_1186_3202, 0}; +#undef pci_ss_info_1186_3202 +#define pci_ss_info_1186_3202 pci_ss_info_168c_0013_1186_3202 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3203 = + {0x1186, 0x3203, pci_subsys_168c_0013_1186_3203, 0}; +#undef pci_ss_info_1186_3203 +#define pci_ss_info_1186_3203 pci_ss_info_168c_0013_1186_3203 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a12 = + {0x1186, 0x3a12, pci_subsys_168c_0013_1186_3a12, 0}; +#undef pci_ss_info_1186_3a12 +#define pci_ss_info_1186_3a12 pci_ss_info_168c_0013_1186_3a12 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a13 = + {0x1186, 0x3a13, pci_subsys_168c_0013_1186_3a13, 0}; +#undef pci_ss_info_1186_3a13 +#define pci_ss_info_1186_3a13 pci_ss_info_168c_0013_1186_3a13 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a14 = + {0x1186, 0x3a14, pci_subsys_168c_0013_1186_3a14, 0}; +#undef pci_ss_info_1186_3a14 +#define pci_ss_info_1186_3a14 pci_ss_info_168c_0013_1186_3a14 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a17 = + {0x1186, 0x3a17, pci_subsys_168c_0013_1186_3a17, 0}; +#undef pci_ss_info_1186_3a17 +#define pci_ss_info_1186_3a17 pci_ss_info_168c_0013_1186_3a17 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a18 = + {0x1186, 0x3a18, pci_subsys_168c_0013_1186_3a18, 0}; +#undef pci_ss_info_1186_3a18 +#define pci_ss_info_1186_3a18 pci_ss_info_168c_0013_1186_3a18 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a63 = + {0x1186, 0x3a63, pci_subsys_168c_0013_1186_3a63, 0}; +#undef pci_ss_info_1186_3a63 +#define pci_ss_info_1186_3a63 pci_ss_info_168c_0013_1186_3a63 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a93 = + {0x1186, 0x3a93, pci_subsys_168c_0013_1186_3a93, 0}; +#undef pci_ss_info_1186_3a93 +#define pci_ss_info_1186_3a93 pci_ss_info_168c_0013_1186_3a93 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3a94 = + {0x1186, 0x3a94, pci_subsys_168c_0013_1186_3a94, 0}; +#undef pci_ss_info_1186_3a94 +#define pci_ss_info_1186_3a94 pci_ss_info_168c_0013_1186_3a94 +static const pciSubsystemInfo pci_ss_info_168c_0013_1186_3ab0 = + {0x1186, 0x3ab0, pci_subsys_168c_0013_1186_3ab0, 0}; +#undef pci_ss_info_1186_3ab0 +#define pci_ss_info_1186_3ab0 pci_ss_info_168c_0013_1186_3ab0 +static const pciSubsystemInfo pci_ss_info_168c_0013_1385_4d00 = + {0x1385, 0x4d00, pci_subsys_168c_0013_1385_4d00, 0}; +#undef pci_ss_info_1385_4d00 +#define pci_ss_info_1385_4d00 pci_ss_info_168c_0013_1385_4d00 +static const pciSubsystemInfo pci_ss_info_168c_0013_1458_e911 = + {0x1458, 0xe911, pci_subsys_168c_0013_1458_e911, 0}; +#undef pci_ss_info_1458_e911 +#define pci_ss_info_1458_e911 pci_ss_info_168c_0013_1458_e911 +static const pciSubsystemInfo pci_ss_info_168c_0013_14b7_0a60 = + {0x14b7, 0x0a60, pci_subsys_168c_0013_14b7_0a60, 0}; +#undef pci_ss_info_14b7_0a60 +#define pci_ss_info_14b7_0a60 pci_ss_info_168c_0013_14b7_0a60 +static const pciSubsystemInfo pci_ss_info_168c_0013_1668_1026 = + {0x1668, 0x1026, pci_subsys_168c_0013_1668_1026, 0}; +#undef pci_ss_info_1668_1026 +#define pci_ss_info_1668_1026 pci_ss_info_168c_0013_1668_1026 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_0013 = + {0x168c, 0x0013, pci_subsys_168c_0013_168c_0013, 0}; +#undef pci_ss_info_168c_0013 +#define pci_ss_info_168c_0013 pci_ss_info_168c_0013_168c_0013 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_1025 = + {0x168c, 0x1025, pci_subsys_168c_0013_168c_1025, 0}; +#undef pci_ss_info_168c_1025 +#define pci_ss_info_168c_1025 pci_ss_info_168c_0013_168c_1025 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_1027 = + {0x168c, 0x1027, pci_subsys_168c_0013_168c_1027, 0}; +#undef pci_ss_info_168c_1027 +#define pci_ss_info_168c_1027 pci_ss_info_168c_0013_168c_1027 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_1042 = + {0x168c, 0x1042, pci_subsys_168c_0013_168c_1042, 0}; +#undef pci_ss_info_168c_1042 +#define pci_ss_info_168c_1042 pci_ss_info_168c_0013_168c_1042 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_2026 = + {0x168c, 0x2026, pci_subsys_168c_0013_168c_2026, 0}; +#undef pci_ss_info_168c_2026 +#define pci_ss_info_168c_2026 pci_ss_info_168c_0013_168c_2026 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_2041 = + {0x168c, 0x2041, pci_subsys_168c_0013_168c_2041, 0}; +#undef pci_ss_info_168c_2041 +#define pci_ss_info_168c_2041 pci_ss_info_168c_0013_168c_2041 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_2042 = + {0x168c, 0x2042, pci_subsys_168c_0013_168c_2042, 0}; +#undef pci_ss_info_168c_2042 +#define pci_ss_info_168c_2042 pci_ss_info_168c_0013_168c_2042 +static const pciSubsystemInfo pci_ss_info_168c_0013_168c_2051 = + {0x168c, 0x2051, pci_subsys_168c_0013_168c_2051, 0}; +#undef pci_ss_info_168c_2051 +#define pci_ss_info_168c_2051 pci_ss_info_168c_0013_168c_2051 +static const pciSubsystemInfo pci_ss_info_168c_0013_16ab_7302 = + {0x16ab, 0x7302, pci_subsys_168c_0013_16ab_7302, 0}; +#undef pci_ss_info_16ab_7302 +#define pci_ss_info_16ab_7302 pci_ss_info_168c_0013_16ab_7302 +static const pciSubsystemInfo pci_ss_info_168c_0013_185f_2012 = + {0x185f, 0x2012, pci_subsys_168c_0013_185f_2012, 0}; +#undef pci_ss_info_185f_2012 +#define pci_ss_info_185f_2012 pci_ss_info_168c_0013_185f_2012 +static const pciSubsystemInfo pci_ss_info_168c_001a_1113_ee20 = + {0x1113, 0xee20, pci_subsys_168c_001a_1113_ee20, 0}; +#undef pci_ss_info_1113_ee20 +#define pci_ss_info_1113_ee20 pci_ss_info_168c_001a_1113_ee20 +static const pciSubsystemInfo pci_ss_info_168c_001a_1113_ee24 = + {0x1113, 0xee24, pci_subsys_168c_001a_1113_ee24, 0}; +#undef pci_ss_info_1113_ee24 +#define pci_ss_info_1113_ee24 pci_ss_info_168c_001a_1113_ee24 +static const pciSubsystemInfo pci_ss_info_168c_001a_1186_3a15 = + {0x1186, 0x3a15, pci_subsys_168c_001a_1186_3a15, 0}; +#undef pci_ss_info_1186_3a15 +#define pci_ss_info_1186_3a15 pci_ss_info_168c_001a_1186_3a15 +static const pciSubsystemInfo pci_ss_info_168c_001a_1186_3a16 = + {0x1186, 0x3a16, pci_subsys_168c_001a_1186_3a16, 0}; +#undef pci_ss_info_1186_3a16 +#define pci_ss_info_1186_3a16 pci_ss_info_168c_001a_1186_3a16 +static const pciSubsystemInfo pci_ss_info_168c_001a_1186_3a23 = + {0x1186, 0x3a23, pci_subsys_168c_001a_1186_3a23, 0}; +#undef pci_ss_info_1186_3a23 +#define pci_ss_info_1186_3a23 pci_ss_info_168c_001a_1186_3a23 +static const pciSubsystemInfo pci_ss_info_168c_001a_1186_3a24 = + {0x1186, 0x3a24, pci_subsys_168c_001a_1186_3a24, 0}; +#undef pci_ss_info_1186_3a24 +#define pci_ss_info_1186_3a24 pci_ss_info_168c_001a_1186_3a24 +static const pciSubsystemInfo pci_ss_info_168c_001a_168c_001a = + {0x168c, 0x001a, pci_subsys_168c_001a_168c_001a, 0}; +#undef pci_ss_info_168c_001a +#define pci_ss_info_168c_001a pci_ss_info_168c_001a_168c_001a +static const pciSubsystemInfo pci_ss_info_168c_001a_168c_1052 = + {0x168c, 0x1052, pci_subsys_168c_001a_168c_1052, 0}; +#undef pci_ss_info_168c_1052 +#define pci_ss_info_168c_1052 pci_ss_info_168c_001a_168c_1052 +static const pciSubsystemInfo pci_ss_info_168c_001b_1186_3a19 = + {0x1186, 0x3a19, pci_subsys_168c_001b_1186_3a19, 0}; +#undef pci_ss_info_1186_3a19 +#define pci_ss_info_1186_3a19 pci_ss_info_168c_001b_1186_3a19 +static const pciSubsystemInfo pci_ss_info_168c_001b_1186_3a22 = + {0x1186, 0x3a22, pci_subsys_168c_001b_1186_3a22, 0}; +#undef pci_ss_info_1186_3a22 +#define pci_ss_info_1186_3a22 pci_ss_info_168c_001b_1186_3a22 +static const pciSubsystemInfo pci_ss_info_168c_001b_168c_2062 = + {0x168c, 0x2062, pci_subsys_168c_001b_168c_2062, 0}; +#undef pci_ss_info_168c_2062 +#define pci_ss_info_168c_2062 pci_ss_info_168c_001b_168c_2062 +static const pciSubsystemInfo pci_ss_info_168c_001b_168c_2063 = + {0x168c, 0x2063, pci_subsys_168c_001b_168c_2063, 0}; +#undef pci_ss_info_168c_2063 +#define pci_ss_info_168c_2063 pci_ss_info_168c_001b_168c_2063 +static const pciSubsystemInfo pci_ss_info_168c_1014_1014_058a = + {0x1014, 0x058a, pci_subsys_168c_1014_1014_058a, 0}; +#undef pci_ss_info_1014_058a +#define pci_ss_info_1014_058a pci_ss_info_168c_1014_1014_058a +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1737_1032_1737_0015 = + {0x1737, 0x0015, pci_subsys_1737_1032_1737_0015, 0}; +#undef pci_ss_info_1737_0015 +#define pci_ss_info_1737_0015 pci_ss_info_1737_1032_1737_0015 +static const pciSubsystemInfo pci_ss_info_1737_1032_1737_0024 = + {0x1737, 0x0024, pci_subsys_1737_1032_1737_0024, 0}; +#undef pci_ss_info_1737_0024 +#define pci_ss_info_1737_0024 pci_ss_info_1737_1032_1737_0024 +static const pciSubsystemInfo pci_ss_info_1737_1064_1737_0016 = + {0x1737, 0x0016, pci_subsys_1737_1064_1737_0016, 0}; +#undef pci_ss_info_1737_0016 +#define pci_ss_info_1737_0016 pci_ss_info_1737_1064_1737_0016 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_173b_03ea_173b_0001 = + {0x173b, 0x0001, pci_subsys_173b_03ea_173b_0001, 0}; +#undef pci_ss_info_173b_0001 +#define pci_ss_info_173b_0001 pci_ss_info_173b_03ea_173b_0001 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_17d5_5831_103c_12d5 = + {0x103c, 0x12d5, pci_subsys_17d5_5831_103c_12d5, 0}; +#undef pci_ss_info_103c_12d5 +#define pci_ss_info_103c_12d5 pci_ss_info_17d5_5831_103c_12d5 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_17d5_5831_10a9_8020 = + {0x10a9, 0x8020, pci_subsys_17d5_5831_10a9_8020, 0}; +#undef pci_ss_info_10a9_8020 +#define pci_ss_info_10a9_8020 pci_ss_info_17d5_5831_10a9_8020 +static const pciSubsystemInfo pci_ss_info_17d5_5831_10a9_8024 = + {0x10a9, 0x8024, pci_subsys_17d5_5831_10a9_8024, 0}; +#undef pci_ss_info_10a9_8024 +#define pci_ss_info_10a9_8024 pci_ss_info_17d5_5831_10a9_8024 +static const pciSubsystemInfo pci_ss_info_17d5_5832_10a9_8021 = + {0x10a9, 0x8021, pci_subsys_17d5_5832_10a9_8021, 0}; +#undef pci_ss_info_10a9_8021 +#define pci_ss_info_10a9_8021 pci_ss_info_17d5_5832_10a9_8021 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_17fe_2220_17fe_2220 = + {0x17fe, 0x2220, pci_subsys_17fe_2220_17fe_2220, 0}; +#undef pci_ss_info_17fe_2220 +#define pci_ss_info_17fe_2220 pci_ss_info_17fe_2220_17fe_2220 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1813_4000_16be_0001 = + {0x16be, 0x0001, pci_subsys_1813_4000_16be_0001, 0}; +#undef pci_ss_info_16be_0001 +#define pci_ss_info_16be_0001 pci_ss_info_1813_4000_16be_0001 +static const pciSubsystemInfo pci_ss_info_1813_4100_16be_0002 = + {0x16be, 0x0002, pci_subsys_1813_4100_16be_0002, 0}; +#undef pci_ss_info_16be_0002 +#define pci_ss_info_16be_0002 pci_ss_info_1813_4100_16be_0002 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_1814_0101_1043_0127 = + {0x1043, 0x0127, pci_subsys_1814_0101_1043_0127, 0}; +#undef pci_ss_info_1043_0127 +#define pci_ss_info_1043_0127 pci_ss_info_1814_0101_1043_0127 +static const pciSubsystemInfo pci_ss_info_1814_0101_1462_6828 = + {0x1462, 0x6828, pci_subsys_1814_0101_1462_6828, 0}; +#undef pci_ss_info_1462_6828 +#define pci_ss_info_1462_6828 pci_ss_info_1814_0101_1462_6828 +static const pciSubsystemInfo pci_ss_info_1814_0201_1043_130f = + {0x1043, 0x130f, pci_subsys_1814_0201_1043_130f, 0}; +#undef pci_ss_info_1043_130f +#define pci_ss_info_1043_130f pci_ss_info_1814_0201_1043_130f +static const pciSubsystemInfo pci_ss_info_1814_0201_1371_001e = + {0x1371, 0x001e, pci_subsys_1814_0201_1371_001e, 0}; +#undef pci_ss_info_1371_001e +#define pci_ss_info_1371_001e pci_ss_info_1814_0201_1371_001e +static const pciSubsystemInfo pci_ss_info_1814_0201_1371_001f = + {0x1371, 0x001f, pci_subsys_1814_0201_1371_001f, 0}; +#undef pci_ss_info_1371_001f +#define pci_ss_info_1371_001f pci_ss_info_1814_0201_1371_001f +static const pciSubsystemInfo pci_ss_info_1814_0201_1371_0020 = + {0x1371, 0x0020, pci_subsys_1814_0201_1371_0020, 0}; +#undef pci_ss_info_1371_0020 +#define pci_ss_info_1371_0020 pci_ss_info_1814_0201_1371_0020 +static const pciSubsystemInfo pci_ss_info_1814_0201_1458_e381 = + {0x1458, 0xe381, pci_subsys_1814_0201_1458_e381, 0}; +#undef pci_ss_info_1458_e381 +#define pci_ss_info_1458_e381 pci_ss_info_1814_0201_1458_e381 +static const pciSubsystemInfo pci_ss_info_1814_0201_1458_e931 = + {0x1458, 0xe931, pci_subsys_1814_0201_1458_e931, 0}; +#undef pci_ss_info_1458_e931 +#define pci_ss_info_1458_e931 pci_ss_info_1814_0201_1458_e931 +static const pciSubsystemInfo pci_ss_info_1814_0201_1462_6835 = + {0x1462, 0x6835, pci_subsys_1814_0201_1462_6835, 0}; +#undef pci_ss_info_1462_6835 +#define pci_ss_info_1462_6835 pci_ss_info_1814_0201_1462_6835 +static const pciSubsystemInfo pci_ss_info_1814_0201_1737_0032 = + {0x1737, 0x0032, pci_subsys_1814_0201_1737_0032, 0}; +#undef pci_ss_info_1737_0032 +#define pci_ss_info_1737_0032 pci_ss_info_1814_0201_1737_0032 +static const pciSubsystemInfo pci_ss_info_1814_0201_1799_700a = + {0x1799, 0x700a, pci_subsys_1814_0201_1799_700a, 0}; +#undef pci_ss_info_1799_700a +#define pci_ss_info_1799_700a pci_ss_info_1814_0201_1799_700a +static const pciSubsystemInfo pci_ss_info_1814_0201_1799_701a = + {0x1799, 0x701a, pci_subsys_1814_0201_1799_701a, 0}; +#undef pci_ss_info_1799_701a +#define pci_ss_info_1799_701a pci_ss_info_1814_0201_1799_701a +static const pciSubsystemInfo pci_ss_info_1814_0201_185f_22a0 = + {0x185f, 0x22a0, pci_subsys_1814_0201_185f_22a0, 0}; +#undef pci_ss_info_185f_22a0 +#define pci_ss_info_185f_22a0 pci_ss_info_1814_0201_185f_22a0 +static const pciSubsystemInfo pci_ss_info_1814_0301_1186_3c08 = + {0x1186, 0x3c08, pci_subsys_1814_0301_1186_3c08, 0}; +#undef pci_ss_info_1186_3c08 +#define pci_ss_info_1186_3c08 pci_ss_info_1814_0301_1186_3c08 +static const pciSubsystemInfo pci_ss_info_1814_0301_1186_3c09 = + {0x1186, 0x3c09, pci_subsys_1814_0301_1186_3c09, 0}; +#undef pci_ss_info_1186_3c09 +#define pci_ss_info_1186_3c09 pci_ss_info_1814_0301_1186_3c09 +static const pciSubsystemInfo pci_ss_info_1814_0301_1737_0055 = + {0x1737, 0x0055, pci_subsys_1814_0301_1737_0055, 0}; +#undef pci_ss_info_1737_0055 +#define pci_ss_info_1737_0055 pci_ss_info_1814_0301_1737_0055 +static const pciSubsystemInfo pci_ss_info_1814_0302_1186_3c08 = + {0x1186, 0x3c08, pci_subsys_1814_0302_1186_3c08, 0}; +#undef pci_ss_info_1186_3c08 +#define pci_ss_info_1186_3c08 pci_ss_info_1814_0302_1186_3c08 +static const pciSubsystemInfo pci_ss_info_1814_0302_1186_3c09 = + {0x1186, 0x3c09, pci_subsys_1814_0302_1186_3c09, 0}; +#undef pci_ss_info_1186_3c09 +#define pci_ss_info_1186_3c09 pci_ss_info_1814_0302_1186_3c09 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_18ec_c006_18ec_d001 = + {0x18ec, 0xd001, pci_subsys_18ec_c006_18ec_d001, 0}; +#undef pci_ss_info_18ec_d001 +#define pci_ss_info_18ec_d001 pci_ss_info_18ec_c006_18ec_d001 +static const pciSubsystemInfo pci_ss_info_18ec_c006_18ec_d002 = + {0x18ec, 0xd002, pci_subsys_18ec_c006_18ec_d002, 0}; +#undef pci_ss_info_18ec_d002 +#define pci_ss_info_18ec_d002 pci_ss_info_18ec_c006_18ec_d002 +static const pciSubsystemInfo pci_ss_info_18ec_c006_18ec_d003 = + {0x18ec, 0xd003, pci_subsys_18ec_c006_18ec_d003, 0}; +#undef pci_ss_info_18ec_d003 +#define pci_ss_info_18ec_d003 pci_ss_info_18ec_c006_18ec_d003 +static const pciSubsystemInfo pci_ss_info_18ec_c006_18ec_d004 = + {0x18ec, 0xd004, pci_subsys_18ec_c006_18ec_d004, 0}; +#undef pci_ss_info_18ec_d004 +#define pci_ss_info_18ec_d004 pci_ss_info_18ec_c006_18ec_d004 +static const pciSubsystemInfo pci_ss_info_18ec_c058_18ec_d001 = + {0x18ec, 0xd001, pci_subsys_18ec_c058_18ec_d001, 0}; +#undef pci_ss_info_18ec_d001 +#define pci_ss_info_18ec_d001 pci_ss_info_18ec_c058_18ec_d001 +static const pciSubsystemInfo pci_ss_info_18ec_c058_18ec_d002 = + {0x18ec, 0xd002, pci_subsys_18ec_c058_18ec_d002, 0}; +#undef pci_ss_info_18ec_d002 +#define pci_ss_info_18ec_d002 pci_ss_info_18ec_c058_18ec_d002 +static const pciSubsystemInfo pci_ss_info_18ec_c058_18ec_d003 = + {0x18ec, 0xd003, pci_subsys_18ec_c058_18ec_d003, 0}; +#undef pci_ss_info_18ec_d003 +#define pci_ss_info_18ec_d003 pci_ss_info_18ec_c058_18ec_d003 +static const pciSubsystemInfo pci_ss_info_18ec_c058_18ec_d004 = + {0x18ec, 0xd004, pci_subsys_18ec_c058_18ec_d004, 0}; +#undef pci_ss_info_18ec_d004 +#define pci_ss_info_18ec_d004 pci_ss_info_18ec_c058_18ec_d004 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_3388_0021_1775_ce90 = + {0x1775, 0xce90, pci_subsys_3388_0021_1775_ce90, 0}; +#undef pci_ss_info_1775_ce90 +#define pci_ss_info_1775_ce90 pci_ss_info_3388_0021_1775_ce90 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_3388_0021_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_3388_0021_4c53_1050 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_3388_0021_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_3388_0021_4c53_1080 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_3388_0021_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_3388_0021_4c53_1090 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_10a0 = + {0x4c53, 0x10a0, pci_subsys_3388_0021_4c53_10a0, 0}; +#undef pci_ss_info_4c53_10a0 +#define pci_ss_info_4c53_10a0 pci_ss_info_3388_0021_4c53_10a0 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_3010 = + {0x4c53, 0x3010, pci_subsys_3388_0021_4c53_3010, 0}; +#undef pci_ss_info_4c53_3010 +#define pci_ss_info_4c53_3010 pci_ss_info_3388_0021_4c53_3010 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_3011 = + {0x4c53, 0x3011, pci_subsys_3388_0021_4c53_3011, 0}; +#undef pci_ss_info_4c53_3011 +#define pci_ss_info_4c53_3011 pci_ss_info_3388_0021_4c53_3011 +static const pciSubsystemInfo pci_ss_info_3388_0021_4c53_4000 = + {0x4c53, 0x4000, pci_subsys_3388_0021_4c53_4000, 0}; +#undef pci_ss_info_4c53_4000 +#define pci_ss_info_4c53_4000 pci_ss_info_3388_0021_4c53_4000 +static const pciSubsystemInfo pci_ss_info_3388_8011_3388_8011 = + {0x3388, 0x8011, pci_subsys_3388_8011_3388_8011, 0}; +#undef pci_ss_info_3388_8011 +#define pci_ss_info_3388_8011 pci_ss_info_3388_8011_3388_8011 +static const pciSubsystemInfo pci_ss_info_3388_8012_3388_8012 = + {0x3388, 0x8012, pci_subsys_3388_8012_3388_8012, 0}; +#undef pci_ss_info_3388_8012 +#define pci_ss_info_3388_8012 pci_ss_info_3388_8012_3388_8012 +static const pciSubsystemInfo pci_ss_info_3388_8013_3388_8013 = + {0x3388, 0x8013, pci_subsys_3388_8013_3388_8013, 0}; +#undef pci_ss_info_3388_8013 +#define pci_ss_info_3388_8013 pci_ss_info_3388_8013_3388_8013 +#endif +static const pciSubsystemInfo pci_ss_info_3d3d_0002_0000_0000 = + {0x0000, 0x0000, pci_subsys_3d3d_0002_0000_0000, 0}; +#undef pci_ss_info_0000_0000 +#define pci_ss_info_0000_0000 pci_ss_info_3d3d_0002_0000_0000 +static const pciSubsystemInfo pci_ss_info_3d3d_0003_0000_0000 = + {0x0000, 0x0000, pci_subsys_3d3d_0003_0000_0000, 0}; +#undef pci_ss_info_0000_0000 +#define pci_ss_info_0000_0000 pci_ss_info_3d3d_0003_0000_0000 +static const pciSubsystemInfo pci_ss_info_3d3d_0006_0000_0000 = + {0x0000, 0x0000, pci_subsys_3d3d_0006_0000_0000, 0}; +#undef pci_ss_info_0000_0000 +#define pci_ss_info_0000_0000 pci_ss_info_3d3d_0006_0000_0000 +static const pciSubsystemInfo pci_ss_info_3d3d_0006_1048_0a42 = + {0x1048, 0x0a42, pci_subsys_3d3d_0006_1048_0a42, 0}; +#undef pci_ss_info_1048_0a42 +#define pci_ss_info_1048_0a42 pci_ss_info_3d3d_0006_1048_0a42 +static const pciSubsystemInfo pci_ss_info_3d3d_0008_1048_0a42 = + {0x1048, 0x0a42, pci_subsys_3d3d_0008_1048_0a42, 0}; +#undef pci_ss_info_1048_0a42 +#define pci_ss_info_1048_0a42 pci_ss_info_3d3d_0008_1048_0a42 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_1040_0011 = + {0x1040, 0x0011, pci_subsys_3d3d_0009_1040_0011, 0}; +#undef pci_ss_info_1040_0011 +#define pci_ss_info_1040_0011 pci_ss_info_3d3d_0009_1040_0011 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_1048_0a42 = + {0x1048, 0x0a42, pci_subsys_3d3d_0009_1048_0a42, 0}; +#undef pci_ss_info_1048_0a42 +#define pci_ss_info_1048_0a42 pci_ss_info_3d3d_0009_1048_0a42 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_13e9_1000 = + {0x13e9, 0x1000, pci_subsys_3d3d_0009_13e9_1000, 0}; +#undef pci_ss_info_13e9_1000 +#define pci_ss_info_13e9_1000 pci_ss_info_3d3d_0009_13e9_1000 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0100 = + {0x3d3d, 0x0100, pci_subsys_3d3d_0009_3d3d_0100, 0}; +#undef pci_ss_info_3d3d_0100 +#define pci_ss_info_3d3d_0100 pci_ss_info_3d3d_0009_3d3d_0100 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0111 = + {0x3d3d, 0x0111, pci_subsys_3d3d_0009_3d3d_0111, 0}; +#undef pci_ss_info_3d3d_0111 +#define pci_ss_info_3d3d_0111 pci_ss_info_3d3d_0009_3d3d_0111 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0114 = + {0x3d3d, 0x0114, pci_subsys_3d3d_0009_3d3d_0114, 0}; +#undef pci_ss_info_3d3d_0114 +#define pci_ss_info_3d3d_0114 pci_ss_info_3d3d_0009_3d3d_0114 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0116 = + {0x3d3d, 0x0116, pci_subsys_3d3d_0009_3d3d_0116, 0}; +#undef pci_ss_info_3d3d_0116 +#define pci_ss_info_3d3d_0116 pci_ss_info_3d3d_0009_3d3d_0116 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0119 = + {0x3d3d, 0x0119, pci_subsys_3d3d_0009_3d3d_0119, 0}; +#undef pci_ss_info_3d3d_0119 +#define pci_ss_info_3d3d_0119 pci_ss_info_3d3d_0009_3d3d_0119 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0120 = + {0x3d3d, 0x0120, pci_subsys_3d3d_0009_3d3d_0120, 0}; +#undef pci_ss_info_3d3d_0120 +#define pci_ss_info_3d3d_0120 pci_ss_info_3d3d_0009_3d3d_0120 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0125 = + {0x3d3d, 0x0125, pci_subsys_3d3d_0009_3d3d_0125, 0}; +#undef pci_ss_info_3d3d_0125 +#define pci_ss_info_3d3d_0125 pci_ss_info_3d3d_0009_3d3d_0125 +static const pciSubsystemInfo pci_ss_info_3d3d_0009_3d3d_0127 = + {0x3d3d, 0x0127, pci_subsys_3d3d_0009_3d3d_0127, 0}; +#undef pci_ss_info_3d3d_0127 +#define pci_ss_info_3d3d_0127 pci_ss_info_3d3d_0009_3d3d_0127 +static const pciSubsystemInfo pci_ss_info_3d3d_000a_3d3d_0121 = + {0x3d3d, 0x0121, pci_subsys_3d3d_000a_3d3d_0121, 0}; +#undef pci_ss_info_3d3d_0121 +#define pci_ss_info_3d3d_0121 pci_ss_info_3d3d_000a_3d3d_0121 +static const pciSubsystemInfo pci_ss_info_3d3d_000c_3d3d_0144 = + {0x3d3d, 0x0144, pci_subsys_3d3d_000c_3d3d_0144, 0}; +#undef pci_ss_info_3d3d_0144 +#define pci_ss_info_3d3d_0144 pci_ss_info_3d3d_000c_3d3d_0144 +static const pciSubsystemInfo pci_ss_info_4005_4000_4005_4000 = + {0x4005, 0x4000, pci_subsys_4005_4000_4005_4000, 0}; +#undef pci_ss_info_4005_4000 +#define pci_ss_info_4005_4000 pci_ss_info_4005_4000_4005_4000 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_0003 = + {0x0070, 0x0003, pci_subsys_4444_0016_0070_0003, 0}; +#undef pci_ss_info_0070_0003 +#define pci_ss_info_0070_0003 pci_ss_info_4444_0016_0070_0003 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_0009 = + {0x0070, 0x0009, pci_subsys_4444_0016_0070_0009, 0}; +#undef pci_ss_info_0070_0009 +#define pci_ss_info_0070_0009 pci_ss_info_4444_0016_0070_0009 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_0801 = + {0x0070, 0x0801, pci_subsys_4444_0016_0070_0801, 0}; +#undef pci_ss_info_0070_0801 +#define pci_ss_info_0070_0801 pci_ss_info_4444_0016_0070_0801 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_0807 = + {0x0070, 0x0807, pci_subsys_4444_0016_0070_0807, 0}; +#undef pci_ss_info_0070_0807 +#define pci_ss_info_0070_0807 pci_ss_info_4444_0016_0070_0807 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_4001 = + {0x0070, 0x4001, pci_subsys_4444_0016_0070_4001, 0}; +#undef pci_ss_info_0070_4001 +#define pci_ss_info_0070_4001 pci_ss_info_4444_0016_0070_4001 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_4009 = + {0x0070, 0x4009, pci_subsys_4444_0016_0070_4009, 0}; +#undef pci_ss_info_0070_4009 +#define pci_ss_info_0070_4009 pci_ss_info_4444_0016_0070_4009 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_4801 = + {0x0070, 0x4801, pci_subsys_4444_0016_0070_4801, 0}; +#undef pci_ss_info_0070_4801 +#define pci_ss_info_0070_4801 pci_ss_info_4444_0016_0070_4801 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_4803 = + {0x0070, 0x4803, pci_subsys_4444_0016_0070_4803, 0}; +#undef pci_ss_info_0070_4803 +#define pci_ss_info_0070_4803 pci_ss_info_4444_0016_0070_4803 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_8003 = + {0x0070, 0x8003, pci_subsys_4444_0016_0070_8003, 0}; +#undef pci_ss_info_0070_8003 +#define pci_ss_info_0070_8003 pci_ss_info_4444_0016_0070_8003 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_8801 = + {0x0070, 0x8801, pci_subsys_4444_0016_0070_8801, 0}; +#undef pci_ss_info_0070_8801 +#define pci_ss_info_0070_8801 pci_ss_info_4444_0016_0070_8801 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_c801 = + {0x0070, 0xc801, pci_subsys_4444_0016_0070_c801, 0}; +#undef pci_ss_info_0070_c801 +#define pci_ss_info_0070_c801 pci_ss_info_4444_0016_0070_c801 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_e807 = + {0x0070, 0xe807, pci_subsys_4444_0016_0070_e807, 0}; +#undef pci_ss_info_0070_e807 +#define pci_ss_info_0070_e807 pci_ss_info_4444_0016_0070_e807 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_e817 = + {0x0070, 0xe817, pci_subsys_4444_0016_0070_e817, 0}; +#undef pci_ss_info_0070_e817 +#define pci_ss_info_0070_e817 pci_ss_info_4444_0016_0070_e817 +static const pciSubsystemInfo pci_ss_info_4444_0016_0070_ff92 = + {0x0070, 0xff92, pci_subsys_4444_0016_0070_ff92, 0}; +#undef pci_ss_info_0070_ff92 +#define pci_ss_info_0070_ff92 pci_ss_info_4444_0016_0070_ff92 +static const pciSubsystemInfo pci_ss_info_4444_0016_0270_0801 = + {0x0270, 0x0801, pci_subsys_4444_0016_0270_0801, 0}; +#undef pci_ss_info_0270_0801 +#define pci_ss_info_0270_0801 pci_ss_info_4444_0016_0270_0801 +static const pciSubsystemInfo pci_ss_info_4444_0016_10fc_d038 = + {0x10fc, 0xd038, pci_subsys_4444_0016_10fc_d038, 0}; +#undef pci_ss_info_10fc_d038 +#define pci_ss_info_10fc_d038 pci_ss_info_4444_0016_10fc_d038 +static const pciSubsystemInfo pci_ss_info_4444_0016_10fc_d039 = + {0x10fc, 0xd039, pci_subsys_4444_0016_10fc_d039, 0}; +#undef pci_ss_info_10fc_d039 +#define pci_ss_info_10fc_d039 pci_ss_info_4444_0016_10fc_d039 +static const pciSubsystemInfo pci_ss_info_4444_0016_12ab_fff3 = + {0x12ab, 0xfff3, pci_subsys_4444_0016_12ab_fff3, 0}; +#undef pci_ss_info_12ab_fff3 +#define pci_ss_info_12ab_fff3 pci_ss_info_4444_0016_12ab_fff3 +static const pciSubsystemInfo pci_ss_info_4444_0016_12ab_ffff = + {0x12ab, 0xffff, pci_subsys_4444_0016_12ab_ffff, 0}; +#undef pci_ss_info_12ab_ffff +#define pci_ss_info_12ab_ffff pci_ss_info_4444_0016_12ab_ffff +static const pciSubsystemInfo pci_ss_info_4444_0016_1461_c019 = + {0x1461, 0xc019, pci_subsys_4444_0016_1461_c019, 0}; +#undef pci_ss_info_1461_c019 +#define pci_ss_info_1461_c019 pci_ss_info_4444_0016_1461_c019 +static const pciSubsystemInfo pci_ss_info_4444_0016_9005_0092 = + {0x9005, 0x0092, pci_subsys_4444_0016_9005_0092, 0}; +#undef pci_ss_info_9005_0092 +#define pci_ss_info_9005_0092 pci_ss_info_4444_0016_9005_0092 +static const pciSubsystemInfo pci_ss_info_4444_0016_9005_0093 = + {0x9005, 0x0093, pci_subsys_4444_0016_9005_0093, 0}; +#undef pci_ss_info_9005_0093 +#define pci_ss_info_9005_0093 pci_ss_info_4444_0016_9005_0093 +static const pciSubsystemInfo pci_ss_info_4444_0803_0070_4000 = + {0x0070, 0x4000, pci_subsys_4444_0803_0070_4000, 0}; +#undef pci_ss_info_0070_4000 +#define pci_ss_info_0070_4000 pci_ss_info_4444_0803_0070_4000 +static const pciSubsystemInfo pci_ss_info_4444_0803_0070_4001 = + {0x0070, 0x4001, pci_subsys_4444_0803_0070_4001, 0}; +#undef pci_ss_info_0070_4001 +#define pci_ss_info_0070_4001 pci_ss_info_4444_0803_0070_4001 +static const pciSubsystemInfo pci_ss_info_4444_0803_0070_4800 = + {0x0070, 0x4800, pci_subsys_4444_0803_0070_4800, 0}; +#undef pci_ss_info_0070_4800 +#define pci_ss_info_0070_4800 pci_ss_info_4444_0803_0070_4800 +static const pciSubsystemInfo pci_ss_info_4444_0803_12ab_0000 = + {0x12ab, 0x0000, pci_subsys_4444_0803_12ab_0000, 0}; +#undef pci_ss_info_12ab_0000 +#define pci_ss_info_12ab_0000 pci_ss_info_4444_0803_12ab_0000 +static const pciSubsystemInfo pci_ss_info_4444_0803_1461_a3ce = + {0x1461, 0xa3ce, pci_subsys_4444_0803_1461_a3ce, 0}; +#undef pci_ss_info_1461_a3ce +#define pci_ss_info_1461_a3ce pci_ss_info_4444_0803_1461_a3ce +static const pciSubsystemInfo pci_ss_info_4444_0803_1461_a3cf = + {0x1461, 0xa3cf, pci_subsys_4444_0803_1461_a3cf, 0}; +#undef pci_ss_info_1461_a3cf +#define pci_ss_info_1461_a3cf pci_ss_info_4444_0803_1461_a3cf +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_4a14_5000_4a14_5000 = + {0x4a14, 0x5000, pci_subsys_4a14_5000_4a14_5000, 0}; +#undef pci_ss_info_4a14_5000 +#define pci_ss_info_4a14_5000 pci_ss_info_4a14_5000_4a14_5000 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_4c53_0000_4c53_3000 = + {0x4c53, 0x3000, pci_subsys_4c53_0000_4c53_3000, 0}; +#undef pci_ss_info_4c53_3000 +#define pci_ss_info_4c53_3000 pci_ss_info_4c53_0000_4c53_3000 +static const pciSubsystemInfo pci_ss_info_4c53_0000_4c53_3001 = + {0x4c53, 0x3001, pci_subsys_4c53_0000_4c53_3001, 0}; +#undef pci_ss_info_4c53_3001 +#define pci_ss_info_4c53_3001 pci_ss_info_4c53_0000_4c53_3001 +static const pciSubsystemInfo pci_ss_info_4c53_0001_4c53_3002 = + {0x4c53, 0x3002, pci_subsys_4c53_0001_4c53_3002, 0}; +#undef pci_ss_info_4c53_3002 +#define pci_ss_info_4c53_3002 pci_ss_info_4c53_0001_4c53_3002 +#endif +static const pciSubsystemInfo pci_ss_info_5333_8900_5333_8900 = + {0x5333, 0x8900, pci_subsys_5333_8900_5333_8900, 0}; +#undef pci_ss_info_5333_8900 +#define pci_ss_info_5333_8900 pci_ss_info_5333_8900_5333_8900 +static const pciSubsystemInfo pci_ss_info_5333_8901_5333_8901 = + {0x5333, 0x8901, pci_subsys_5333_8901_5333_8901, 0}; +#undef pci_ss_info_5333_8901 +#define pci_ss_info_5333_8901 pci_ss_info_5333_8901_5333_8901 +static const pciSubsystemInfo pci_ss_info_5333_8904_1014_00db = + {0x1014, 0x00db, pci_subsys_5333_8904_1014_00db, 0}; +#undef pci_ss_info_1014_00db +#define pci_ss_info_1014_00db pci_ss_info_5333_8904_1014_00db +static const pciSubsystemInfo pci_ss_info_5333_8904_5333_8904 = + {0x5333, 0x8904, pci_subsys_5333_8904_5333_8904, 0}; +#undef pci_ss_info_5333_8904 +#define pci_ss_info_5333_8904 pci_ss_info_5333_8904_5333_8904 +static const pciSubsystemInfo pci_ss_info_5333_8a01_0e11_b032 = + {0x0e11, 0xb032, pci_subsys_5333_8a01_0e11_b032, 0}; +#undef pci_ss_info_0e11_b032 +#define pci_ss_info_0e11_b032 pci_ss_info_5333_8a01_0e11_b032 +static const pciSubsystemInfo pci_ss_info_5333_8a01_10b4_1617 = + {0x10b4, 0x1617, pci_subsys_5333_8a01_10b4_1617, 0}; +#undef pci_ss_info_10b4_1617 +#define pci_ss_info_10b4_1617 pci_ss_info_5333_8a01_10b4_1617 +static const pciSubsystemInfo pci_ss_info_5333_8a01_10b4_1717 = + {0x10b4, 0x1717, pci_subsys_5333_8a01_10b4_1717, 0}; +#undef pci_ss_info_10b4_1717 +#define pci_ss_info_10b4_1717 pci_ss_info_5333_8a01_10b4_1717 +static const pciSubsystemInfo pci_ss_info_5333_8a01_5333_8a01 = + {0x5333, 0x8a01, pci_subsys_5333_8a01_5333_8a01, 0}; +#undef pci_ss_info_5333_8a01 +#define pci_ss_info_5333_8a01 pci_ss_info_5333_8a01_5333_8a01 +static const pciSubsystemInfo pci_ss_info_5333_8a10_1092_8a10 = + {0x1092, 0x8a10, pci_subsys_5333_8a10_1092_8a10, 0}; +#undef pci_ss_info_1092_8a10 +#define pci_ss_info_1092_8a10 pci_ss_info_5333_8a10_1092_8a10 +static const pciSubsystemInfo pci_ss_info_5333_8a13_5333_8a13 = + {0x5333, 0x8a13, pci_subsys_5333_8a13_5333_8a13, 0}; +#undef pci_ss_info_5333_8a13 +#define pci_ss_info_5333_8a13 pci_ss_info_5333_8a13_5333_8a13 +static const pciSubsystemInfo pci_ss_info_5333_8a20_5333_8a20 = + {0x5333, 0x8a20, pci_subsys_5333_8a20_5333_8a20, 0}; +#undef pci_ss_info_5333_8a20 +#define pci_ss_info_5333_8a20 pci_ss_info_5333_8a20_5333_8a20 +static const pciSubsystemInfo pci_ss_info_5333_8a21_5333_8a21 = + {0x5333, 0x8a21, pci_subsys_5333_8a21_5333_8a21, 0}; +#undef pci_ss_info_5333_8a21 +#define pci_ss_info_5333_8a21 pci_ss_info_5333_8a21_5333_8a21 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1033_8068 = + {0x1033, 0x8068, pci_subsys_5333_8a22_1033_8068, 0}; +#undef pci_ss_info_1033_8068 +#define pci_ss_info_1033_8068 pci_ss_info_5333_8a22_1033_8068 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1033_8069 = + {0x1033, 0x8069, pci_subsys_5333_8a22_1033_8069, 0}; +#undef pci_ss_info_1033_8069 +#define pci_ss_info_1033_8069 pci_ss_info_5333_8a22_1033_8069 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1033_8110 = + {0x1033, 0x8110, pci_subsys_5333_8a22_1033_8110, 0}; +#undef pci_ss_info_1033_8110 +#define pci_ss_info_1033_8110 pci_ss_info_5333_8a22_1033_8110 +static const pciSubsystemInfo pci_ss_info_5333_8a22_105d_0018 = + {0x105d, 0x0018, pci_subsys_5333_8a22_105d_0018, 0}; +#undef pci_ss_info_105d_0018 +#define pci_ss_info_105d_0018 pci_ss_info_5333_8a22_105d_0018 +static const pciSubsystemInfo pci_ss_info_5333_8a22_105d_002a = + {0x105d, 0x002a, pci_subsys_5333_8a22_105d_002a, 0}; +#undef pci_ss_info_105d_002a +#define pci_ss_info_105d_002a pci_ss_info_5333_8a22_105d_002a +static const pciSubsystemInfo pci_ss_info_5333_8a22_105d_003a = + {0x105d, 0x003a, pci_subsys_5333_8a22_105d_003a, 0}; +#undef pci_ss_info_105d_003a +#define pci_ss_info_105d_003a pci_ss_info_5333_8a22_105d_003a +static const pciSubsystemInfo pci_ss_info_5333_8a22_105d_092f = + {0x105d, 0x092f, pci_subsys_5333_8a22_105d_092f, 0}; +#undef pci_ss_info_105d_092f +#define pci_ss_info_105d_092f pci_ss_info_5333_8a22_105d_092f +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4207 = + {0x1092, 0x4207, pci_subsys_5333_8a22_1092_4207, 0}; +#undef pci_ss_info_1092_4207 +#define pci_ss_info_1092_4207 pci_ss_info_5333_8a22_1092_4207 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4800 = + {0x1092, 0x4800, pci_subsys_5333_8a22_1092_4800, 0}; +#undef pci_ss_info_1092_4800 +#define pci_ss_info_1092_4800 pci_ss_info_5333_8a22_1092_4800 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4807 = + {0x1092, 0x4807, pci_subsys_5333_8a22_1092_4807, 0}; +#undef pci_ss_info_1092_4807 +#define pci_ss_info_1092_4807 pci_ss_info_5333_8a22_1092_4807 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4808 = + {0x1092, 0x4808, pci_subsys_5333_8a22_1092_4808, 0}; +#undef pci_ss_info_1092_4808 +#define pci_ss_info_1092_4808 pci_ss_info_5333_8a22_1092_4808 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4809 = + {0x1092, 0x4809, pci_subsys_5333_8a22_1092_4809, 0}; +#undef pci_ss_info_1092_4809 +#define pci_ss_info_1092_4809 pci_ss_info_5333_8a22_1092_4809 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_480e = + {0x1092, 0x480e, pci_subsys_5333_8a22_1092_480e, 0}; +#undef pci_ss_info_1092_480e +#define pci_ss_info_1092_480e pci_ss_info_5333_8a22_1092_480e +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4904 = + {0x1092, 0x4904, pci_subsys_5333_8a22_1092_4904, 0}; +#undef pci_ss_info_1092_4904 +#define pci_ss_info_1092_4904 pci_ss_info_5333_8a22_1092_4904 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4905 = + {0x1092, 0x4905, pci_subsys_5333_8a22_1092_4905, 0}; +#undef pci_ss_info_1092_4905 +#define pci_ss_info_1092_4905 pci_ss_info_5333_8a22_1092_4905 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4a09 = + {0x1092, 0x4a09, pci_subsys_5333_8a22_1092_4a09, 0}; +#undef pci_ss_info_1092_4a09 +#define pci_ss_info_1092_4a09 pci_ss_info_5333_8a22_1092_4a09 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4a0b = + {0x1092, 0x4a0b, pci_subsys_5333_8a22_1092_4a0b, 0}; +#undef pci_ss_info_1092_4a0b +#define pci_ss_info_1092_4a0b pci_ss_info_5333_8a22_1092_4a0b +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4a0f = + {0x1092, 0x4a0f, pci_subsys_5333_8a22_1092_4a0f, 0}; +#undef pci_ss_info_1092_4a0f +#define pci_ss_info_1092_4a0f pci_ss_info_5333_8a22_1092_4a0f +static const pciSubsystemInfo pci_ss_info_5333_8a22_1092_4e01 = + {0x1092, 0x4e01, pci_subsys_5333_8a22_1092_4e01, 0}; +#undef pci_ss_info_1092_4e01 +#define pci_ss_info_1092_4e01 pci_ss_info_5333_8a22_1092_4e01 +static const pciSubsystemInfo pci_ss_info_5333_8a22_1102_101d = + {0x1102, 0x101d, pci_subsys_5333_8a22_1102_101d, 0}; +#undef pci_ss_info_1102_101d +#define pci_ss_info_1102_101d pci_ss_info_5333_8a22_1102_101d +static const pciSubsystemInfo pci_ss_info_5333_8a22_1102_101e = + {0x1102, 0x101e, pci_subsys_5333_8a22_1102_101e, 0}; +#undef pci_ss_info_1102_101e +#define pci_ss_info_1102_101e pci_ss_info_5333_8a22_1102_101e +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8100 = + {0x5333, 0x8100, pci_subsys_5333_8a22_5333_8100, 0}; +#undef pci_ss_info_5333_8100 +#define pci_ss_info_5333_8100 pci_ss_info_5333_8a22_5333_8100 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8110 = + {0x5333, 0x8110, pci_subsys_5333_8a22_5333_8110, 0}; +#undef pci_ss_info_5333_8110 +#define pci_ss_info_5333_8110 pci_ss_info_5333_8a22_5333_8110 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8125 = + {0x5333, 0x8125, pci_subsys_5333_8a22_5333_8125, 0}; +#undef pci_ss_info_5333_8125 +#define pci_ss_info_5333_8125 pci_ss_info_5333_8a22_5333_8125 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8143 = + {0x5333, 0x8143, pci_subsys_5333_8a22_5333_8143, 0}; +#undef pci_ss_info_5333_8143 +#define pci_ss_info_5333_8143 pci_ss_info_5333_8a22_5333_8143 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8a22 = + {0x5333, 0x8a22, pci_subsys_5333_8a22_5333_8a22, 0}; +#undef pci_ss_info_5333_8a22 +#define pci_ss_info_5333_8a22 pci_ss_info_5333_8a22_5333_8a22 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_8a2e = + {0x5333, 0x8a2e, pci_subsys_5333_8a22_5333_8a2e, 0}; +#undef pci_ss_info_5333_8a2e +#define pci_ss_info_5333_8a2e pci_ss_info_5333_8a22_5333_8a2e +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_9125 = + {0x5333, 0x9125, pci_subsys_5333_8a22_5333_9125, 0}; +#undef pci_ss_info_5333_9125 +#define pci_ss_info_5333_9125 pci_ss_info_5333_8a22_5333_9125 +static const pciSubsystemInfo pci_ss_info_5333_8a22_5333_9143 = + {0x5333, 0x9143, pci_subsys_5333_8a22_5333_9143, 0}; +#undef pci_ss_info_5333_9143 +#define pci_ss_info_5333_9143 pci_ss_info_5333_8a22_5333_9143 +static const pciSubsystemInfo pci_ss_info_5333_8c01_1179_0001 = + {0x1179, 0x0001, pci_subsys_5333_8c01_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_5333_8c01_1179_0001 +static const pciSubsystemInfo pci_ss_info_5333_8c12_1014_017f = + {0x1014, 0x017f, pci_subsys_5333_8c12_1014_017f, 0}; +#undef pci_ss_info_1014_017f +#define pci_ss_info_1014_017f pci_ss_info_5333_8c12_1014_017f +static const pciSubsystemInfo pci_ss_info_5333_8c12_1179_0001 = + {0x1179, 0x0001, pci_subsys_5333_8c12_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_5333_8c12_1179_0001 +static const pciSubsystemInfo pci_ss_info_5333_8c13_1179_0001 = + {0x1179, 0x0001, pci_subsys_5333_8c13_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_5333_8c13_1179_0001 +static const pciSubsystemInfo pci_ss_info_5333_8c2e_1014_01fc = + {0x1014, 0x01fc, pci_subsys_5333_8c2e_1014_01fc, 0}; +#undef pci_ss_info_1014_01fc +#define pci_ss_info_1014_01fc pci_ss_info_5333_8c2e_1014_01fc +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5932 = + {0x1092, 0x5932, pci_subsys_5333_9102_1092_5932, 0}; +#undef pci_ss_info_1092_5932 +#define pci_ss_info_1092_5932 pci_ss_info_5333_9102_1092_5932 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5934 = + {0x1092, 0x5934, pci_subsys_5333_9102_1092_5934, 0}; +#undef pci_ss_info_1092_5934 +#define pci_ss_info_1092_5934 pci_ss_info_5333_9102_1092_5934 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5952 = + {0x1092, 0x5952, pci_subsys_5333_9102_1092_5952, 0}; +#undef pci_ss_info_1092_5952 +#define pci_ss_info_1092_5952 pci_ss_info_5333_9102_1092_5952 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5954 = + {0x1092, 0x5954, pci_subsys_5333_9102_1092_5954, 0}; +#undef pci_ss_info_1092_5954 +#define pci_ss_info_1092_5954 pci_ss_info_5333_9102_1092_5954 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5a35 = + {0x1092, 0x5a35, pci_subsys_5333_9102_1092_5a35, 0}; +#undef pci_ss_info_1092_5a35 +#define pci_ss_info_1092_5a35 pci_ss_info_5333_9102_1092_5a35 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5a37 = + {0x1092, 0x5a37, pci_subsys_5333_9102_1092_5a37, 0}; +#undef pci_ss_info_1092_5a37 +#define pci_ss_info_1092_5a37 pci_ss_info_5333_9102_1092_5a37 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5a55 = + {0x1092, 0x5a55, pci_subsys_5333_9102_1092_5a55, 0}; +#undef pci_ss_info_1092_5a55 +#define pci_ss_info_1092_5a55 pci_ss_info_5333_9102_1092_5a55 +static const pciSubsystemInfo pci_ss_info_5333_9102_1092_5a57 = + {0x1092, 0x5a57, pci_subsys_5333_9102_1092_5a57, 0}; +#undef pci_ss_info_1092_5a57 +#define pci_ss_info_1092_5a57 pci_ss_info_5333_9102_1092_5a57 +static const pciSubsystemInfo pci_ss_info_8086_0600_8086_01af = + {0x8086, 0x01af, pci_subsys_8086_0600_8086_01af, 0}; +#undef pci_ss_info_8086_01af +#define pci_ss_info_8086_01af pci_ss_info_8086_0600_8086_01af +static const pciSubsystemInfo pci_ss_info_8086_0600_8086_01c1 = + {0x8086, 0x01c1, pci_subsys_8086_0600_8086_01c1, 0}; +#undef pci_ss_info_8086_01c1 +#define pci_ss_info_8086_01c1 pci_ss_info_8086_0600_8086_01c1 +static const pciSubsystemInfo pci_ss_info_8086_0600_8086_01f7 = + {0x8086, 0x01f7, pci_subsys_8086_0600_8086_01f7, 0}; +#undef pci_ss_info_8086_01f7 +#define pci_ss_info_8086_01f7 pci_ss_info_8086_0600_8086_01f7 +static const pciSubsystemInfo pci_ss_info_8086_1000_0e11_b0df = + {0x0e11, 0xb0df, pci_subsys_8086_1000_0e11_b0df, 0}; +#undef pci_ss_info_0e11_b0df +#define pci_ss_info_0e11_b0df pci_ss_info_8086_1000_0e11_b0df +static const pciSubsystemInfo pci_ss_info_8086_1000_0e11_b0e0 = + {0x0e11, 0xb0e0, pci_subsys_8086_1000_0e11_b0e0, 0}; +#undef pci_ss_info_0e11_b0e0 +#define pci_ss_info_0e11_b0e0 pci_ss_info_8086_1000_0e11_b0e0 +static const pciSubsystemInfo pci_ss_info_8086_1000_0e11_b123 = + {0x0e11, 0xb123, pci_subsys_8086_1000_0e11_b123, 0}; +#undef pci_ss_info_0e11_b123 +#define pci_ss_info_0e11_b123 pci_ss_info_8086_1000_0e11_b123 +static const pciSubsystemInfo pci_ss_info_8086_1000_1014_0119 = + {0x1014, 0x0119, pci_subsys_8086_1000_1014_0119, 0}; +#undef pci_ss_info_1014_0119 +#define pci_ss_info_1014_0119 pci_ss_info_8086_1000_1014_0119 +static const pciSubsystemInfo pci_ss_info_8086_1000_8086_1000 = + {0x8086, 0x1000, pci_subsys_8086_1000_8086_1000, 0}; +#undef pci_ss_info_8086_1000 +#define pci_ss_info_8086_1000 pci_ss_info_8086_1000_8086_1000 +static const pciSubsystemInfo pci_ss_info_8086_1001_0e11_004a = + {0x0e11, 0x004a, pci_subsys_8086_1001_0e11_004a, 0}; +#undef pci_ss_info_0e11_004a +#define pci_ss_info_0e11_004a pci_ss_info_8086_1001_0e11_004a +static const pciSubsystemInfo pci_ss_info_8086_1001_1014_01ea = + {0x1014, 0x01ea, pci_subsys_8086_1001_1014_01ea, 0}; +#undef pci_ss_info_1014_01ea +#define pci_ss_info_1014_01ea pci_ss_info_8086_1001_1014_01ea +static const pciSubsystemInfo pci_ss_info_8086_1001_8086_1002 = + {0x8086, 0x1002, pci_subsys_8086_1001_8086_1002, 0}; +#undef pci_ss_info_8086_1002 +#define pci_ss_info_8086_1002 pci_ss_info_8086_1001_8086_1002 +static const pciSubsystemInfo pci_ss_info_8086_1001_8086_1003 = + {0x8086, 0x1003, pci_subsys_8086_1001_8086_1003, 0}; +#undef pci_ss_info_8086_1003 +#define pci_ss_info_8086_1003 pci_ss_info_8086_1001_8086_1003 +static const pciSubsystemInfo pci_ss_info_8086_1002_8086_200e = + {0x8086, 0x200e, pci_subsys_8086_1002_8086_200e, 0}; +#undef pci_ss_info_8086_200e +#define pci_ss_info_8086_200e pci_ss_info_8086_1002_8086_200e +static const pciSubsystemInfo pci_ss_info_8086_1002_8086_2013 = + {0x8086, 0x2013, pci_subsys_8086_1002_8086_2013, 0}; +#undef pci_ss_info_8086_2013 +#define pci_ss_info_8086_2013 pci_ss_info_8086_1002_8086_2013 +static const pciSubsystemInfo pci_ss_info_8086_1002_8086_2017 = + {0x8086, 0x2017, pci_subsys_8086_1002_8086_2017, 0}; +#undef pci_ss_info_8086_2017 +#define pci_ss_info_8086_2017 pci_ss_info_8086_1002_8086_2017 +static const pciSubsystemInfo pci_ss_info_8086_1004_0e11_0049 = + {0x0e11, 0x0049, pci_subsys_8086_1004_0e11_0049, 0}; +#undef pci_ss_info_0e11_0049 +#define pci_ss_info_0e11_0049 pci_ss_info_8086_1004_0e11_0049 +static const pciSubsystemInfo pci_ss_info_8086_1004_0e11_b1a4 = + {0x0e11, 0xb1a4, pci_subsys_8086_1004_0e11_b1a4, 0}; +#undef pci_ss_info_0e11_b1a4 +#define pci_ss_info_0e11_b1a4 pci_ss_info_8086_1004_0e11_b1a4 +static const pciSubsystemInfo pci_ss_info_8086_1004_1014_10f2 = + {0x1014, 0x10f2, pci_subsys_8086_1004_1014_10f2, 0}; +#undef pci_ss_info_1014_10f2 +#define pci_ss_info_1014_10f2 pci_ss_info_8086_1004_1014_10f2 +static const pciSubsystemInfo pci_ss_info_8086_1004_8086_1004 = + {0x8086, 0x1004, pci_subsys_8086_1004_8086_1004, 0}; +#undef pci_ss_info_8086_1004 +#define pci_ss_info_8086_1004 pci_ss_info_8086_1004_8086_1004 +static const pciSubsystemInfo pci_ss_info_8086_1004_8086_2004 = + {0x8086, 0x2004, pci_subsys_8086_1004_8086_2004, 0}; +#undef pci_ss_info_8086_2004 +#define pci_ss_info_8086_2004 pci_ss_info_8086_1004_8086_2004 +static const pciSubsystemInfo pci_ss_info_8086_1008_1014_0269 = + {0x1014, 0x0269, pci_subsys_8086_1008_1014_0269, 0}; +#undef pci_ss_info_1014_0269 +#define pci_ss_info_1014_0269 pci_ss_info_8086_1008_1014_0269 +static const pciSubsystemInfo pci_ss_info_8086_1008_1028_011c = + {0x1028, 0x011c, pci_subsys_8086_1008_1028_011c, 0}; +#undef pci_ss_info_1028_011c +#define pci_ss_info_1028_011c pci_ss_info_8086_1008_1028_011c +static const pciSubsystemInfo pci_ss_info_8086_1008_8086_1107 = + {0x8086, 0x1107, pci_subsys_8086_1008_8086_1107, 0}; +#undef pci_ss_info_8086_1107 +#define pci_ss_info_8086_1107 pci_ss_info_8086_1008_8086_1107 +static const pciSubsystemInfo pci_ss_info_8086_1008_8086_2107 = + {0x8086, 0x2107, pci_subsys_8086_1008_8086_2107, 0}; +#undef pci_ss_info_8086_2107 +#define pci_ss_info_8086_2107 pci_ss_info_8086_1008_8086_2107 +static const pciSubsystemInfo pci_ss_info_8086_1008_8086_2110 = + {0x8086, 0x2110, pci_subsys_8086_1008_8086_2110, 0}; +#undef pci_ss_info_8086_2110 +#define pci_ss_info_8086_2110 pci_ss_info_8086_1008_8086_2110 +static const pciSubsystemInfo pci_ss_info_8086_1008_8086_3108 = + {0x8086, 0x3108, pci_subsys_8086_1008_8086_3108, 0}; +#undef pci_ss_info_8086_3108 +#define pci_ss_info_8086_3108 pci_ss_info_8086_1008_8086_3108 +static const pciSubsystemInfo pci_ss_info_8086_1009_1014_0268 = + {0x1014, 0x0268, pci_subsys_8086_1009_1014_0268, 0}; +#undef pci_ss_info_1014_0268 +#define pci_ss_info_1014_0268 pci_ss_info_8086_1009_1014_0268 +static const pciSubsystemInfo pci_ss_info_8086_1009_8086_1109 = + {0x8086, 0x1109, pci_subsys_8086_1009_8086_1109, 0}; +#undef pci_ss_info_8086_1109 +#define pci_ss_info_8086_1109 pci_ss_info_8086_1009_8086_1109 +static const pciSubsystemInfo pci_ss_info_8086_1009_8086_2109 = + {0x8086, 0x2109, pci_subsys_8086_1009_8086_2109, 0}; +#undef pci_ss_info_8086_2109 +#define pci_ss_info_8086_2109 pci_ss_info_8086_1009_8086_2109 +static const pciSubsystemInfo pci_ss_info_8086_100c_8086_1112 = + {0x8086, 0x1112, pci_subsys_8086_100c_8086_1112, 0}; +#undef pci_ss_info_8086_1112 +#define pci_ss_info_8086_1112 pci_ss_info_8086_100c_8086_1112 +static const pciSubsystemInfo pci_ss_info_8086_100c_8086_2112 = + {0x8086, 0x2112, pci_subsys_8086_100c_8086_2112, 0}; +#undef pci_ss_info_8086_2112 +#define pci_ss_info_8086_2112 pci_ss_info_8086_100c_8086_2112 +static const pciSubsystemInfo pci_ss_info_8086_100d_1028_0123 = + {0x1028, 0x0123, pci_subsys_8086_100d_1028_0123, 0}; +#undef pci_ss_info_1028_0123 +#define pci_ss_info_1028_0123 pci_ss_info_8086_100d_1028_0123 +static const pciSubsystemInfo pci_ss_info_8086_100d_1079_891f = + {0x1079, 0x891f, pci_subsys_8086_100d_1079_891f, 0}; +#undef pci_ss_info_1079_891f +#define pci_ss_info_1079_891f pci_ss_info_8086_100d_1079_891f +static const pciSubsystemInfo pci_ss_info_8086_100d_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_8086_100d_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_8086_100d_4c53_1080 +static const pciSubsystemInfo pci_ss_info_8086_100d_8086_110d = + {0x8086, 0x110d, pci_subsys_8086_100d_8086_110d, 0}; +#undef pci_ss_info_8086_110d +#define pci_ss_info_8086_110d pci_ss_info_8086_100d_8086_110d +static const pciSubsystemInfo pci_ss_info_8086_100e_1014_0265 = + {0x1014, 0x0265, pci_subsys_8086_100e_1014_0265, 0}; +#undef pci_ss_info_1014_0265 +#define pci_ss_info_1014_0265 pci_ss_info_8086_100e_1014_0265 +static const pciSubsystemInfo pci_ss_info_8086_100e_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_100e_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_100e_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_100e_1014_026a = + {0x1014, 0x026a, pci_subsys_8086_100e_1014_026a, 0}; +#undef pci_ss_info_1014_026a +#define pci_ss_info_1014_026a pci_ss_info_8086_100e_1014_026a +static const pciSubsystemInfo pci_ss_info_8086_100e_1028_002e = + {0x1028, 0x002e, pci_subsys_8086_100e_1028_002e, 0}; +#undef pci_ss_info_1028_002e +#define pci_ss_info_1028_002e pci_ss_info_8086_100e_1028_002e +static const pciSubsystemInfo pci_ss_info_8086_100e_1028_0134 = + {0x1028, 0x0134, pci_subsys_8086_100e_1028_0134, 0}; +#undef pci_ss_info_1028_0134 +#define pci_ss_info_1028_0134 pci_ss_info_8086_100e_1028_0134 +static const pciSubsystemInfo pci_ss_info_8086_100e_1028_0151 = + {0x1028, 0x0151, pci_subsys_8086_100e_1028_0151, 0}; +#undef pci_ss_info_1028_0151 +#define pci_ss_info_1028_0151 pci_ss_info_8086_100e_1028_0151 +static const pciSubsystemInfo pci_ss_info_8086_100e_107b_8920 = + {0x107b, 0x8920, pci_subsys_8086_100e_107b_8920, 0}; +#undef pci_ss_info_107b_8920 +#define pci_ss_info_107b_8920 pci_ss_info_8086_100e_107b_8920 +static const pciSubsystemInfo pci_ss_info_8086_100e_8086_001e = + {0x8086, 0x001e, pci_subsys_8086_100e_8086_001e, 0}; +#undef pci_ss_info_8086_001e +#define pci_ss_info_8086_001e pci_ss_info_8086_100e_8086_001e +static const pciSubsystemInfo pci_ss_info_8086_100e_8086_002e = + {0x8086, 0x002e, pci_subsys_8086_100e_8086_002e, 0}; +#undef pci_ss_info_8086_002e +#define pci_ss_info_8086_002e pci_ss_info_8086_100e_8086_002e +static const pciSubsystemInfo pci_ss_info_8086_100e_8086_1376 = + {0x8086, 0x1376, pci_subsys_8086_100e_8086_1376, 0}; +#undef pci_ss_info_8086_1376 +#define pci_ss_info_8086_1376 pci_ss_info_8086_100e_8086_1376 +static const pciSubsystemInfo pci_ss_info_8086_100e_8086_1476 = + {0x8086, 0x1476, pci_subsys_8086_100e_8086_1476, 0}; +#undef pci_ss_info_8086_1476 +#define pci_ss_info_8086_1476 pci_ss_info_8086_100e_8086_1476 +static const pciSubsystemInfo pci_ss_info_8086_100f_1014_0269 = + {0x1014, 0x0269, pci_subsys_8086_100f_1014_0269, 0}; +#undef pci_ss_info_1014_0269 +#define pci_ss_info_1014_0269 pci_ss_info_8086_100f_1014_0269 +static const pciSubsystemInfo pci_ss_info_8086_100f_1014_028e = + {0x1014, 0x028e, pci_subsys_8086_100f_1014_028e, 0}; +#undef pci_ss_info_1014_028e +#define pci_ss_info_1014_028e pci_ss_info_8086_100f_1014_028e +static const pciSubsystemInfo pci_ss_info_8086_100f_8086_1000 = + {0x8086, 0x1000, pci_subsys_8086_100f_8086_1000, 0}; +#undef pci_ss_info_8086_1000 +#define pci_ss_info_8086_1000 pci_ss_info_8086_100f_8086_1000 +static const pciSubsystemInfo pci_ss_info_8086_100f_8086_1001 = + {0x8086, 0x1001, pci_subsys_8086_100f_8086_1001, 0}; +#undef pci_ss_info_8086_1001 +#define pci_ss_info_8086_1001 pci_ss_info_8086_100f_8086_1001 +static const pciSubsystemInfo pci_ss_info_8086_1010_0e11_00db = + {0x0e11, 0x00db, pci_subsys_8086_1010_0e11_00db, 0}; +#undef pci_ss_info_0e11_00db +#define pci_ss_info_0e11_00db pci_ss_info_8086_1010_0e11_00db +static const pciSubsystemInfo pci_ss_info_8086_1010_1014_027c = + {0x1014, 0x027c, pci_subsys_8086_1010_1014_027c, 0}; +#undef pci_ss_info_1014_027c +#define pci_ss_info_1014_027c pci_ss_info_8086_1010_1014_027c +static const pciSubsystemInfo pci_ss_info_8086_1010_18fb_7872 = + {0x18fb, 0x7872, pci_subsys_8086_1010_18fb_7872, 0}; +#undef pci_ss_info_18fb_7872 +#define pci_ss_info_18fb_7872 pci_ss_info_8086_1010_18fb_7872 +static const pciSubsystemInfo pci_ss_info_8086_1010_1fc1_0026 = + {0x1fc1, 0x0026, pci_subsys_8086_1010_1fc1_0026, 0}; +#undef pci_ss_info_1fc1_0026 +#define pci_ss_info_1fc1_0026 pci_ss_info_8086_1010_1fc1_0026 +static const pciSubsystemInfo pci_ss_info_8086_1010_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_8086_1010_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_8086_1010_4c53_1080 +static const pciSubsystemInfo pci_ss_info_8086_1010_4c53_10a0 = + {0x4c53, 0x10a0, pci_subsys_8086_1010_4c53_10a0, 0}; +#undef pci_ss_info_4c53_10a0 +#define pci_ss_info_4c53_10a0 pci_ss_info_8086_1010_4c53_10a0 +static const pciSubsystemInfo pci_ss_info_8086_1010_8086_1011 = + {0x8086, 0x1011, pci_subsys_8086_1010_8086_1011, 0}; +#undef pci_ss_info_8086_1011 +#define pci_ss_info_8086_1011 pci_ss_info_8086_1010_8086_1011 +static const pciSubsystemInfo pci_ss_info_8086_1010_8086_1012 = + {0x8086, 0x1012, pci_subsys_8086_1010_8086_1012, 0}; +#undef pci_ss_info_8086_1012 +#define pci_ss_info_8086_1012 pci_ss_info_8086_1010_8086_1012 +static const pciSubsystemInfo pci_ss_info_8086_1010_8086_101a = + {0x8086, 0x101a, pci_subsys_8086_1010_8086_101a, 0}; +#undef pci_ss_info_8086_101a +#define pci_ss_info_8086_101a pci_ss_info_8086_1010_8086_101a +static const pciSubsystemInfo pci_ss_info_8086_1010_8086_3424 = + {0x8086, 0x3424, pci_subsys_8086_1010_8086_3424, 0}; +#undef pci_ss_info_8086_3424 +#define pci_ss_info_8086_3424 pci_ss_info_8086_1010_8086_3424 +static const pciSubsystemInfo pci_ss_info_8086_1011_1014_0268 = + {0x1014, 0x0268, pci_subsys_8086_1011_1014_0268, 0}; +#undef pci_ss_info_1014_0268 +#define pci_ss_info_1014_0268 pci_ss_info_8086_1011_1014_0268 +static const pciSubsystemInfo pci_ss_info_8086_1011_8086_1002 = + {0x8086, 0x1002, pci_subsys_8086_1011_8086_1002, 0}; +#undef pci_ss_info_8086_1002 +#define pci_ss_info_8086_1002 pci_ss_info_8086_1011_8086_1002 +static const pciSubsystemInfo pci_ss_info_8086_1011_8086_1003 = + {0x8086, 0x1003, pci_subsys_8086_1011_8086_1003, 0}; +#undef pci_ss_info_8086_1003 +#define pci_ss_info_8086_1003 pci_ss_info_8086_1011_8086_1003 +static const pciSubsystemInfo pci_ss_info_8086_1012_0e11_00dc = + {0x0e11, 0x00dc, pci_subsys_8086_1012_0e11_00dc, 0}; +#undef pci_ss_info_0e11_00dc +#define pci_ss_info_0e11_00dc pci_ss_info_8086_1012_0e11_00dc +static const pciSubsystemInfo pci_ss_info_8086_1012_8086_1012 = + {0x8086, 0x1012, pci_subsys_8086_1012_8086_1012, 0}; +#undef pci_ss_info_8086_1012 +#define pci_ss_info_8086_1012 pci_ss_info_8086_1012_8086_1012 +static const pciSubsystemInfo pci_ss_info_8086_1013_8086_0013 = + {0x8086, 0x0013, pci_subsys_8086_1013_8086_0013, 0}; +#undef pci_ss_info_8086_0013 +#define pci_ss_info_8086_0013 pci_ss_info_8086_1013_8086_0013 +static const pciSubsystemInfo pci_ss_info_8086_1013_8086_1013 = + {0x8086, 0x1013, pci_subsys_8086_1013_8086_1013, 0}; +#undef pci_ss_info_8086_1013 +#define pci_ss_info_8086_1013 pci_ss_info_8086_1013_8086_1013 +static const pciSubsystemInfo pci_ss_info_8086_1013_8086_1113 = + {0x8086, 0x1113, pci_subsys_8086_1013_8086_1113, 0}; +#undef pci_ss_info_8086_1113 +#define pci_ss_info_8086_1113 pci_ss_info_8086_1013_8086_1113 +static const pciSubsystemInfo pci_ss_info_8086_1014_8086_0014 = + {0x8086, 0x0014, pci_subsys_8086_1014_8086_0014, 0}; +#undef pci_ss_info_8086_0014 +#define pci_ss_info_8086_0014 pci_ss_info_8086_1014_8086_0014 +static const pciSubsystemInfo pci_ss_info_8086_1014_8086_1014 = + {0x8086, 0x1014, pci_subsys_8086_1014_8086_1014, 0}; +#undef pci_ss_info_8086_1014 +#define pci_ss_info_8086_1014 pci_ss_info_8086_1014_8086_1014 +static const pciSubsystemInfo pci_ss_info_8086_1015_8086_1015 = + {0x8086, 0x1015, pci_subsys_8086_1015_8086_1015, 0}; +#undef pci_ss_info_8086_1015 +#define pci_ss_info_8086_1015 pci_ss_info_8086_1015_8086_1015 +static const pciSubsystemInfo pci_ss_info_8086_1016_1014_052c = + {0x1014, 0x052c, pci_subsys_8086_1016_1014_052c, 0}; +#undef pci_ss_info_1014_052c +#define pci_ss_info_1014_052c pci_ss_info_8086_1016_1014_052c +static const pciSubsystemInfo pci_ss_info_8086_1016_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_1016_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_1016_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_1016_8086_1016 = + {0x8086, 0x1016, pci_subsys_8086_1016_8086_1016, 0}; +#undef pci_ss_info_8086_1016 +#define pci_ss_info_8086_1016 pci_ss_info_8086_1016_8086_1016 +static const pciSubsystemInfo pci_ss_info_8086_1017_8086_1017 = + {0x8086, 0x1017, pci_subsys_8086_1017_8086_1017, 0}; +#undef pci_ss_info_8086_1017 +#define pci_ss_info_8086_1017 pci_ss_info_8086_1017_8086_1017 +static const pciSubsystemInfo pci_ss_info_8086_1018_8086_1018 = + {0x8086, 0x1018, pci_subsys_8086_1018_8086_1018, 0}; +#undef pci_ss_info_8086_1018 +#define pci_ss_info_8086_1018 pci_ss_info_8086_1018_8086_1018 +static const pciSubsystemInfo pci_ss_info_8086_1019_1458_1019 = + {0x1458, 0x1019, pci_subsys_8086_1019_1458_1019, 0}; +#undef pci_ss_info_1458_1019 +#define pci_ss_info_1458_1019 pci_ss_info_8086_1019_1458_1019 +static const pciSubsystemInfo pci_ss_info_8086_1019_1458_e000 = + {0x1458, 0xe000, pci_subsys_8086_1019_1458_e000, 0}; +#undef pci_ss_info_1458_e000 +#define pci_ss_info_1458_e000 pci_ss_info_8086_1019_1458_e000 +static const pciSubsystemInfo pci_ss_info_8086_1019_8086_1019 = + {0x8086, 0x1019, pci_subsys_8086_1019_8086_1019, 0}; +#undef pci_ss_info_8086_1019 +#define pci_ss_info_8086_1019 pci_ss_info_8086_1019_8086_1019 +static const pciSubsystemInfo pci_ss_info_8086_1019_8086_301f = + {0x8086, 0x301f, pci_subsys_8086_1019_8086_301f, 0}; +#undef pci_ss_info_8086_301f +#define pci_ss_info_8086_301f pci_ss_info_8086_1019_8086_301f +static const pciSubsystemInfo pci_ss_info_8086_1019_8086_302c = + {0x8086, 0x302c, pci_subsys_8086_1019_8086_302c, 0}; +#undef pci_ss_info_8086_302c +#define pci_ss_info_8086_302c pci_ss_info_8086_1019_8086_302c +static const pciSubsystemInfo pci_ss_info_8086_1019_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_1019_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_1019_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_101a_8086_101a = + {0x8086, 0x101a, pci_subsys_8086_101a_8086_101a, 0}; +#undef pci_ss_info_8086_101a +#define pci_ss_info_8086_101a pci_ss_info_8086_101a_8086_101a +static const pciSubsystemInfo pci_ss_info_8086_101d_8086_1000 = + {0x8086, 0x1000, pci_subsys_8086_101d_8086_1000, 0}; +#undef pci_ss_info_8086_1000 +#define pci_ss_info_8086_1000 pci_ss_info_8086_101d_8086_1000 +static const pciSubsystemInfo pci_ss_info_8086_101e_1014_0549 = + {0x1014, 0x0549, pci_subsys_8086_101e_1014_0549, 0}; +#undef pci_ss_info_1014_0549 +#define pci_ss_info_1014_0549 pci_ss_info_8086_101e_1014_0549 +static const pciSubsystemInfo pci_ss_info_8086_101e_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_101e_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_101e_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_101e_8086_101e = + {0x8086, 0x101e, pci_subsys_8086_101e_8086_101e, 0}; +#undef pci_ss_info_8086_101e +#define pci_ss_info_8086_101e pci_ss_info_8086_101e_8086_101e +static const pciSubsystemInfo pci_ss_info_8086_1026_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_1026_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_1026_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_1026_8086_1000 = + {0x8086, 0x1000, pci_subsys_8086_1026_8086_1000, 0}; +#undef pci_ss_info_8086_1000 +#define pci_ss_info_8086_1000 pci_ss_info_8086_1026_8086_1000 +static const pciSubsystemInfo pci_ss_info_8086_1026_8086_1001 = + {0x8086, 0x1001, pci_subsys_8086_1026_8086_1001, 0}; +#undef pci_ss_info_8086_1001 +#define pci_ss_info_8086_1001 pci_ss_info_8086_1026_8086_1001 +static const pciSubsystemInfo pci_ss_info_8086_1026_8086_1002 = + {0x8086, 0x1002, pci_subsys_8086_1026_8086_1002, 0}; +#undef pci_ss_info_8086_1002 +#define pci_ss_info_8086_1002 pci_ss_info_8086_1026_8086_1002 +static const pciSubsystemInfo pci_ss_info_8086_1026_8086_1003 = + {0x8086, 0x1003, pci_subsys_8086_1026_8086_1003, 0}; +#undef pci_ss_info_8086_1003 +#define pci_ss_info_8086_1003 pci_ss_info_8086_1026_8086_1003 +static const pciSubsystemInfo pci_ss_info_8086_1026_8086_1026 = + {0x8086, 0x1026, pci_subsys_8086_1026_8086_1026, 0}; +#undef pci_ss_info_8086_1026 +#define pci_ss_info_8086_1026 pci_ss_info_8086_1026_8086_1026 +static const pciSubsystemInfo pci_ss_info_8086_1027_103c_3103 = + {0x103c, 0x3103, pci_subsys_8086_1027_103c_3103, 0}; +#undef pci_ss_info_103c_3103 +#define pci_ss_info_103c_3103 pci_ss_info_8086_1027_103c_3103 +static const pciSubsystemInfo pci_ss_info_8086_1027_8086_1001 = + {0x8086, 0x1001, pci_subsys_8086_1027_8086_1001, 0}; +#undef pci_ss_info_8086_1001 +#define pci_ss_info_8086_1001 pci_ss_info_8086_1027_8086_1001 +static const pciSubsystemInfo pci_ss_info_8086_1027_8086_1002 = + {0x8086, 0x1002, pci_subsys_8086_1027_8086_1002, 0}; +#undef pci_ss_info_8086_1002 +#define pci_ss_info_8086_1002 pci_ss_info_8086_1027_8086_1002 +static const pciSubsystemInfo pci_ss_info_8086_1027_8086_1003 = + {0x8086, 0x1003, pci_subsys_8086_1027_8086_1003, 0}; +#undef pci_ss_info_8086_1003 +#define pci_ss_info_8086_1003 pci_ss_info_8086_1027_8086_1003 +static const pciSubsystemInfo pci_ss_info_8086_1027_8086_1027 = + {0x8086, 0x1027, pci_subsys_8086_1027_8086_1027, 0}; +#undef pci_ss_info_8086_1027 +#define pci_ss_info_8086_1027 pci_ss_info_8086_1027_8086_1027 +static const pciSubsystemInfo pci_ss_info_8086_1028_8086_1028 = + {0x8086, 0x1028, pci_subsys_8086_1028_8086_1028, 0}; +#undef pci_ss_info_8086_1028 +#define pci_ss_info_8086_1028 pci_ss_info_8086_1028_8086_1028 +static const pciSubsystemInfo pci_ss_info_8086_1031_1014_0209 = + {0x1014, 0x0209, pci_subsys_8086_1031_1014_0209, 0}; +#undef pci_ss_info_1014_0209 +#define pci_ss_info_1014_0209 pci_ss_info_8086_1031_1014_0209 +static const pciSubsystemInfo pci_ss_info_8086_1031_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_1031_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_1031_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_1031_104d_813c = + {0x104d, 0x813c, pci_subsys_8086_1031_104d_813c, 0}; +#undef pci_ss_info_104d_813c +#define pci_ss_info_104d_813c pci_ss_info_8086_1031_104d_813c +static const pciSubsystemInfo pci_ss_info_8086_1031_107b_5350 = + {0x107b, 0x5350, pci_subsys_8086_1031_107b_5350, 0}; +#undef pci_ss_info_107b_5350 +#define pci_ss_info_107b_5350 pci_ss_info_8086_1031_107b_5350 +static const pciSubsystemInfo pci_ss_info_8086_1031_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_1031_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_1031_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_1031_144d_c000 = + {0x144d, 0xc000, pci_subsys_8086_1031_144d_c000, 0}; +#undef pci_ss_info_144d_c000 +#define pci_ss_info_144d_c000 pci_ss_info_8086_1031_144d_c000 +static const pciSubsystemInfo pci_ss_info_8086_1031_144d_c001 = + {0x144d, 0xc001, pci_subsys_8086_1031_144d_c001, 0}; +#undef pci_ss_info_144d_c001 +#define pci_ss_info_144d_c001 pci_ss_info_8086_1031_144d_c001 +static const pciSubsystemInfo pci_ss_info_8086_1031_144d_c003 = + {0x144d, 0xc003, pci_subsys_8086_1031_144d_c003, 0}; +#undef pci_ss_info_144d_c003 +#define pci_ss_info_144d_c003 pci_ss_info_8086_1031_144d_c003 +static const pciSubsystemInfo pci_ss_info_8086_1031_144d_c006 = + {0x144d, 0xc006, pci_subsys_8086_1031_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_8086_1031_144d_c006 +static const pciSubsystemInfo pci_ss_info_8086_1038_0e11_0098 = + {0x0e11, 0x0098, pci_subsys_8086_1038_0e11_0098, 0}; +#undef pci_ss_info_0e11_0098 +#define pci_ss_info_0e11_0098 pci_ss_info_8086_1038_0e11_0098 +static const pciSubsystemInfo pci_ss_info_8086_1039_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_1039_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_1039_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_103d_1014_0522 = + {0x1014, 0x0522, pci_subsys_8086_103d_1014_0522, 0}; +#undef pci_ss_info_1014_0522 +#define pci_ss_info_1014_0522 pci_ss_info_8086_103d_1014_0522 +static const pciSubsystemInfo pci_ss_info_8086_1040_16be_1040 = + {0x16be, 0x1040, pci_subsys_8086_1040_16be_1040, 0}; +#undef pci_ss_info_16be_1040 +#define pci_ss_info_16be_1040 pci_ss_info_8086_1040_16be_1040 +static const pciSubsystemInfo pci_ss_info_8086_1043_103c_08b0 = + {0x103c, 0x08b0, pci_subsys_8086_1043_103c_08b0, 0}; +#undef pci_ss_info_103c_08b0 +#define pci_ss_info_103c_08b0 pci_ss_info_8086_1043_103c_08b0 +static const pciSubsystemInfo pci_ss_info_8086_1043_8086_2527 = + {0x8086, 0x2527, pci_subsys_8086_1043_8086_2527, 0}; +#undef pci_ss_info_8086_2527 +#define pci_ss_info_8086_2527 pci_ss_info_8086_1043_8086_2527 +static const pciSubsystemInfo pci_ss_info_8086_1048_8086_a01f = + {0x8086, 0xa01f, pci_subsys_8086_1048_8086_a01f, 0}; +#undef pci_ss_info_8086_a01f +#define pci_ss_info_8086_a01f pci_ss_info_8086_1048_8086_a01f +static const pciSubsystemInfo pci_ss_info_8086_1048_8086_a11f = + {0x8086, 0xa11f, pci_subsys_8086_1048_8086_a11f, 0}; +#undef pci_ss_info_8086_a11f +#define pci_ss_info_8086_a11f pci_ss_info_8086_1048_8086_a11f +static const pciSubsystemInfo pci_ss_info_8086_1050_1462_728c = + {0x1462, 0x728c, pci_subsys_8086_1050_1462_728c, 0}; +#undef pci_ss_info_1462_728c +#define pci_ss_info_1462_728c pci_ss_info_8086_1050_1462_728c +static const pciSubsystemInfo pci_ss_info_8086_1050_1462_758c = + {0x1462, 0x758c, pci_subsys_8086_1050_1462_758c, 0}; +#undef pci_ss_info_1462_758c +#define pci_ss_info_1462_758c pci_ss_info_8086_1050_1462_758c +static const pciSubsystemInfo pci_ss_info_8086_1050_8086_3020 = + {0x8086, 0x3020, pci_subsys_8086_1050_8086_3020, 0}; +#undef pci_ss_info_8086_3020 +#define pci_ss_info_8086_3020 pci_ss_info_8086_1050_8086_3020 +static const pciSubsystemInfo pci_ss_info_8086_1050_8086_302f = + {0x8086, 0x302f, pci_subsys_8086_1050_8086_302f, 0}; +#undef pci_ss_info_8086_302f +#define pci_ss_info_8086_302f pci_ss_info_8086_1050_8086_302f +static const pciSubsystemInfo pci_ss_info_8086_1050_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_1050_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_1050_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_105e_103c_7044 = + {0x103c, 0x7044, pci_subsys_8086_105e_103c_7044, 0}; +#undef pci_ss_info_103c_7044 +#define pci_ss_info_103c_7044 pci_ss_info_8086_105e_103c_7044 +static const pciSubsystemInfo pci_ss_info_8086_105e_1775_6003 = + {0x1775, 0x6003, pci_subsys_8086_105e_1775_6003, 0}; +#undef pci_ss_info_1775_6003 +#define pci_ss_info_1775_6003 pci_ss_info_8086_105e_1775_6003 +static const pciSubsystemInfo pci_ss_info_8086_105e_8086_005e = + {0x8086, 0x005e, pci_subsys_8086_105e_8086_005e, 0}; +#undef pci_ss_info_8086_005e +#define pci_ss_info_8086_005e pci_ss_info_8086_105e_8086_005e +static const pciSubsystemInfo pci_ss_info_8086_105e_8086_105e = + {0x8086, 0x105e, pci_subsys_8086_105e_8086_105e, 0}; +#undef pci_ss_info_8086_105e +#define pci_ss_info_8086_105e pci_ss_info_8086_105e_8086_105e +static const pciSubsystemInfo pci_ss_info_8086_105e_8086_115e = + {0x8086, 0x115e, pci_subsys_8086_105e_8086_115e, 0}; +#undef pci_ss_info_8086_115e +#define pci_ss_info_8086_115e pci_ss_info_8086_105e_8086_115e +static const pciSubsystemInfo pci_ss_info_8086_105e_8086_116e = + {0x8086, 0x116e, pci_subsys_8086_105e_8086_116e, 0}; +#undef pci_ss_info_8086_116e +#define pci_ss_info_8086_116e pci_ss_info_8086_105e_8086_116e +static const pciSubsystemInfo pci_ss_info_8086_105e_8086_125e = + {0x8086, 0x125e, pci_subsys_8086_105e_8086_125e, 0}; +#undef pci_ss_info_8086_125e +#define pci_ss_info_8086_125e pci_ss_info_8086_105e_8086_125e +static const pciSubsystemInfo pci_ss_info_8086_105e_8086_135e = + {0x8086, 0x135e, pci_subsys_8086_105e_8086_135e, 0}; +#undef pci_ss_info_8086_135e +#define pci_ss_info_8086_135e pci_ss_info_8086_105e_8086_135e +static const pciSubsystemInfo pci_ss_info_8086_105f_8086_115f = + {0x8086, 0x115f, pci_subsys_8086_105f_8086_115f, 0}; +#undef pci_ss_info_8086_115f +#define pci_ss_info_8086_115f pci_ss_info_8086_105f_8086_115f +static const pciSubsystemInfo pci_ss_info_8086_105f_8086_116f = + {0x8086, 0x116f, pci_subsys_8086_105f_8086_116f, 0}; +#undef pci_ss_info_8086_116f +#define pci_ss_info_8086_116f pci_ss_info_8086_105f_8086_116f +static const pciSubsystemInfo pci_ss_info_8086_105f_8086_125f = + {0x8086, 0x125f, pci_subsys_8086_105f_8086_125f, 0}; +#undef pci_ss_info_8086_125f +#define pci_ss_info_8086_125f pci_ss_info_8086_105f_8086_125f +static const pciSubsystemInfo pci_ss_info_8086_105f_8086_135f = + {0x8086, 0x135f, pci_subsys_8086_105f_8086_135f, 0}; +#undef pci_ss_info_8086_135f +#define pci_ss_info_8086_135f pci_ss_info_8086_105f_8086_135f +static const pciSubsystemInfo pci_ss_info_8086_1060_8086_0060 = + {0x8086, 0x0060, pci_subsys_8086_1060_8086_0060, 0}; +#undef pci_ss_info_8086_0060 +#define pci_ss_info_8086_0060 pci_ss_info_8086_1060_8086_0060 +static const pciSubsystemInfo pci_ss_info_8086_1060_8086_1060 = + {0x8086, 0x1060, pci_subsys_8086_1060_8086_1060, 0}; +#undef pci_ss_info_8086_1060 +#define pci_ss_info_8086_1060 pci_ss_info_8086_1060_8086_1060 +static const pciSubsystemInfo pci_ss_info_8086_1064_1043_80f8 = + {0x1043, 0x80f8, pci_subsys_8086_1064_1043_80f8, 0}; +#undef pci_ss_info_1043_80f8 +#define pci_ss_info_1043_80f8 pci_ss_info_8086_1064_1043_80f8 +static const pciSubsystemInfo pci_ss_info_8086_1075_1028_0165 = + {0x1028, 0x0165, pci_subsys_8086_1075_1028_0165, 0}; +#undef pci_ss_info_1028_0165 +#define pci_ss_info_1028_0165 pci_ss_info_8086_1075_1028_0165 +static const pciSubsystemInfo pci_ss_info_8086_1075_8086_0075 = + {0x8086, 0x0075, pci_subsys_8086_1075_8086_0075, 0}; +#undef pci_ss_info_8086_0075 +#define pci_ss_info_8086_0075 pci_ss_info_8086_1075_8086_0075 +static const pciSubsystemInfo pci_ss_info_8086_1075_8086_1075 = + {0x8086, 0x1075, pci_subsys_8086_1075_8086_1075, 0}; +#undef pci_ss_info_8086_1075 +#define pci_ss_info_8086_1075 pci_ss_info_8086_1075_8086_1075 +static const pciSubsystemInfo pci_ss_info_8086_1076_1028_0165 = + {0x1028, 0x0165, pci_subsys_8086_1076_1028_0165, 0}; +#undef pci_ss_info_1028_0165 +#define pci_ss_info_1028_0165 pci_ss_info_8086_1076_1028_0165 +static const pciSubsystemInfo pci_ss_info_8086_1076_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_1076_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_1076_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_1076_8086_0076 = + {0x8086, 0x0076, pci_subsys_8086_1076_8086_0076, 0}; +#undef pci_ss_info_8086_0076 +#define pci_ss_info_8086_0076 pci_ss_info_8086_1076_8086_0076 +static const pciSubsystemInfo pci_ss_info_8086_1076_8086_1076 = + {0x8086, 0x1076, pci_subsys_8086_1076_8086_1076, 0}; +#undef pci_ss_info_8086_1076 +#define pci_ss_info_8086_1076 pci_ss_info_8086_1076_8086_1076 +static const pciSubsystemInfo pci_ss_info_8086_1076_8086_1176 = + {0x8086, 0x1176, pci_subsys_8086_1076_8086_1176, 0}; +#undef pci_ss_info_8086_1176 +#define pci_ss_info_8086_1176 pci_ss_info_8086_1076_8086_1176 +static const pciSubsystemInfo pci_ss_info_8086_1076_8086_1276 = + {0x8086, 0x1276, pci_subsys_8086_1076_8086_1276, 0}; +#undef pci_ss_info_8086_1276 +#define pci_ss_info_8086_1276 pci_ss_info_8086_1076_8086_1276 +static const pciSubsystemInfo pci_ss_info_8086_1077_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_1077_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_1077_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_1077_8086_0077 = + {0x8086, 0x0077, pci_subsys_8086_1077_8086_0077, 0}; +#undef pci_ss_info_8086_0077 +#define pci_ss_info_8086_0077 pci_ss_info_8086_1077_8086_0077 +static const pciSubsystemInfo pci_ss_info_8086_1077_8086_1077 = + {0x8086, 0x1077, pci_subsys_8086_1077_8086_1077, 0}; +#undef pci_ss_info_8086_1077 +#define pci_ss_info_8086_1077 pci_ss_info_8086_1077_8086_1077 +static const pciSubsystemInfo pci_ss_info_8086_1078_8086_1078 = + {0x8086, 0x1078, pci_subsys_8086_1078_8086_1078, 0}; +#undef pci_ss_info_8086_1078 +#define pci_ss_info_8086_1078 pci_ss_info_8086_1078_8086_1078 +static const pciSubsystemInfo pci_ss_info_8086_1079_103c_12a6 = + {0x103c, 0x12a6, pci_subsys_8086_1079_103c_12a6, 0}; +#undef pci_ss_info_103c_12a6 +#define pci_ss_info_103c_12a6 pci_ss_info_8086_1079_103c_12a6 +static const pciSubsystemInfo pci_ss_info_8086_1079_103c_12cf = + {0x103c, 0x12cf, pci_subsys_8086_1079_103c_12cf, 0}; +#undef pci_ss_info_103c_12cf +#define pci_ss_info_103c_12cf pci_ss_info_8086_1079_103c_12cf +static const pciSubsystemInfo pci_ss_info_8086_1079_1775_10d0 = + {0x1775, 0x10d0, pci_subsys_8086_1079_1775_10d0, 0}; +#undef pci_ss_info_1775_10d0 +#define pci_ss_info_1775_10d0 pci_ss_info_8086_1079_1775_10d0 +static const pciSubsystemInfo pci_ss_info_8086_1079_1775_ce90 = + {0x1775, 0xce90, pci_subsys_8086_1079_1775_ce90, 0}; +#undef pci_ss_info_1775_ce90 +#define pci_ss_info_1775_ce90 pci_ss_info_8086_1079_1775_ce90 +static const pciSubsystemInfo pci_ss_info_8086_1079_1fc1_0027 = + {0x1fc1, 0x0027, pci_subsys_8086_1079_1fc1_0027, 0}; +#undef pci_ss_info_1fc1_0027 +#define pci_ss_info_1fc1_0027 pci_ss_info_8086_1079_1fc1_0027 +static const pciSubsystemInfo pci_ss_info_8086_1079_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_1079_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_1079_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_1079_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_1079_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_1079_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_1079_8086_0079 = + {0x8086, 0x0079, pci_subsys_8086_1079_8086_0079, 0}; +#undef pci_ss_info_8086_0079 +#define pci_ss_info_8086_0079 pci_ss_info_8086_1079_8086_0079 +static const pciSubsystemInfo pci_ss_info_8086_1079_8086_1079 = + {0x8086, 0x1079, pci_subsys_8086_1079_8086_1079, 0}; +#undef pci_ss_info_8086_1079 +#define pci_ss_info_8086_1079 pci_ss_info_8086_1079_8086_1079 +static const pciSubsystemInfo pci_ss_info_8086_1079_8086_1179 = + {0x8086, 0x1179, pci_subsys_8086_1079_8086_1179, 0}; +#undef pci_ss_info_8086_1179 +#define pci_ss_info_8086_1179 pci_ss_info_8086_1079_8086_1179 +static const pciSubsystemInfo pci_ss_info_8086_1079_8086_117a = + {0x8086, 0x117a, pci_subsys_8086_1079_8086_117a, 0}; +#undef pci_ss_info_8086_117a +#define pci_ss_info_8086_117a pci_ss_info_8086_1079_8086_117a +static const pciSubsystemInfo pci_ss_info_8086_107a_103c_12a8 = + {0x103c, 0x12a8, pci_subsys_8086_107a_103c_12a8, 0}; +#undef pci_ss_info_103c_12a8 +#define pci_ss_info_103c_12a8 pci_ss_info_8086_107a_103c_12a8 +static const pciSubsystemInfo pci_ss_info_8086_107a_8086_107a = + {0x8086, 0x107a, pci_subsys_8086_107a_8086_107a, 0}; +#undef pci_ss_info_8086_107a +#define pci_ss_info_8086_107a pci_ss_info_8086_107a_8086_107a +static const pciSubsystemInfo pci_ss_info_8086_107a_8086_127a = + {0x8086, 0x127a, pci_subsys_8086_107a_8086_127a, 0}; +#undef pci_ss_info_8086_127a +#define pci_ss_info_8086_127a pci_ss_info_8086_107a_8086_127a +static const pciSubsystemInfo pci_ss_info_8086_107b_8086_007b = + {0x8086, 0x007b, pci_subsys_8086_107b_8086_007b, 0}; +#undef pci_ss_info_8086_007b +#define pci_ss_info_8086_007b pci_ss_info_8086_107b_8086_007b +static const pciSubsystemInfo pci_ss_info_8086_107b_8086_107b = + {0x8086, 0x107b, pci_subsys_8086_107b_8086_107b, 0}; +#undef pci_ss_info_8086_107b +#define pci_ss_info_8086_107b pci_ss_info_8086_107b_8086_107b +static const pciSubsystemInfo pci_ss_info_8086_107c_8086_1376 = + {0x8086, 0x1376, pci_subsys_8086_107c_8086_1376, 0}; +#undef pci_ss_info_8086_1376 +#define pci_ss_info_8086_1376 pci_ss_info_8086_107c_8086_1376 +static const pciSubsystemInfo pci_ss_info_8086_107c_8086_1476 = + {0x8086, 0x1476, pci_subsys_8086_107c_8086_1476, 0}; +#undef pci_ss_info_8086_1476 +#define pci_ss_info_8086_1476 pci_ss_info_8086_107c_8086_1476 +static const pciSubsystemInfo pci_ss_info_8086_107d_8086_1082 = + {0x8086, 0x1082, pci_subsys_8086_107d_8086_1082, 0}; +#undef pci_ss_info_8086_1082 +#define pci_ss_info_8086_1082 pci_ss_info_8086_107d_8086_1082 +static const pciSubsystemInfo pci_ss_info_8086_107d_8086_1092 = + {0x8086, 0x1092, pci_subsys_8086_107d_8086_1092, 0}; +#undef pci_ss_info_8086_1092 +#define pci_ss_info_8086_1092 pci_ss_info_8086_107d_8086_1092 +static const pciSubsystemInfo pci_ss_info_8086_107e_8086_1084 = + {0x8086, 0x1084, pci_subsys_8086_107e_8086_1084, 0}; +#undef pci_ss_info_8086_1084 +#define pci_ss_info_8086_1084 pci_ss_info_8086_107e_8086_1084 +static const pciSubsystemInfo pci_ss_info_8086_107e_8086_1094 = + {0x8086, 0x1094, pci_subsys_8086_107e_8086_1094, 0}; +#undef pci_ss_info_8086_1094 +#define pci_ss_info_8086_1094 pci_ss_info_8086_107e_8086_1094 +static const pciSubsystemInfo pci_ss_info_8086_108a_8086_108a = + {0x8086, 0x108a, pci_subsys_8086_108a_8086_108a, 0}; +#undef pci_ss_info_8086_108a +#define pci_ss_info_8086_108a pci_ss_info_8086_108a_8086_108a +static const pciSubsystemInfo pci_ss_info_8086_108a_8086_118a = + {0x8086, 0x118a, pci_subsys_8086_108a_8086_118a, 0}; +#undef pci_ss_info_8086_118a +#define pci_ss_info_8086_118a pci_ss_info_8086_108a_8086_118a +static const pciSubsystemInfo pci_ss_info_8086_1099_8086_1099 = + {0x8086, 0x1099, pci_subsys_8086_1099_8086_1099, 0}; +#undef pci_ss_info_8086_1099 +#define pci_ss_info_8086_1099 pci_ss_info_8086_1099_8086_1099 +static const pciSubsystemInfo pci_ss_info_8086_109a_17aa_2001 = + {0x17aa, 0x2001, pci_subsys_8086_109a_17aa_2001, 0}; +#undef pci_ss_info_17aa_2001 +#define pci_ss_info_17aa_2001 pci_ss_info_8086_109a_17aa_2001 +static const pciSubsystemInfo pci_ss_info_8086_109a_17aa_207e = + {0x17aa, 0x207e, pci_subsys_8086_109a_17aa_207e, 0}; +#undef pci_ss_info_17aa_207e +#define pci_ss_info_17aa_207e pci_ss_info_8086_109a_17aa_207e +static const pciSubsystemInfo pci_ss_info_8086_109a_8086_109a = + {0x8086, 0x109a, pci_subsys_8086_109a_8086_109a, 0}; +#undef pci_ss_info_8086_109a +#define pci_ss_info_8086_109a pci_ss_info_8086_109a_8086_109a +static const pciSubsystemInfo pci_ss_info_8086_10b5_103c_3109 = + {0x103c, 0x3109, pci_subsys_8086_10b5_103c_3109, 0}; +#undef pci_ss_info_103c_3109 +#define pci_ss_info_103c_3109 pci_ss_info_8086_10b5_103c_3109 +static const pciSubsystemInfo pci_ss_info_8086_10b5_8086_1099 = + {0x8086, 0x1099, pci_subsys_8086_10b5_8086_1099, 0}; +#undef pci_ss_info_8086_1099 +#define pci_ss_info_8086_1099 pci_ss_info_8086_10b5_8086_1099 +static const pciSubsystemInfo pci_ss_info_8086_10b5_8086_1199 = + {0x8086, 0x1199, pci_subsys_8086_10b5_8086_1199, 0}; +#undef pci_ss_info_8086_1199 +#define pci_ss_info_8086_1199 pci_ss_info_8086_10b5_8086_1199 +static const pciSubsystemInfo pci_ss_info_8086_10b9_8086_1083 = + {0x8086, 0x1083, pci_subsys_8086_10b9_8086_1083, 0}; +#undef pci_ss_info_8086_1083 +#define pci_ss_info_8086_1083 pci_ss_info_8086_10b9_8086_1083 +static const pciSubsystemInfo pci_ss_info_8086_10b9_8086_1093 = + {0x8086, 0x1093, pci_subsys_8086_10b9_8086_1093, 0}; +#undef pci_ss_info_8086_1093 +#define pci_ss_info_8086_1093 pci_ss_info_8086_10b9_8086_1093 +static const pciSubsystemInfo pci_ss_info_8086_1130_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_1130_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_1130_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_1130_1043_8027 = + {0x1043, 0x8027, pci_subsys_8086_1130_1043_8027, 0}; +#undef pci_ss_info_1043_8027 +#define pci_ss_info_1043_8027 pci_ss_info_8086_1130_1043_8027 +static const pciSubsystemInfo pci_ss_info_8086_1130_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_1130_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_1130_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_1130_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_1130_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_1130_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_1130_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_1130_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_1130_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_1132_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_1132_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_1132_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_1132_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_1132_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_1132_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_1132_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_1132_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_1132_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_1132_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_1132_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_1132_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_1132_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_1132_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_1132_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_1161_8086_1161 = + {0x8086, 0x1161, pci_subsys_8086_1161_8086_1161, 0}; +#undef pci_ss_info_8086_1161 +#define pci_ss_info_8086_1161 pci_ss_info_8086_1161_8086_1161 +static const pciSubsystemInfo pci_ss_info_8086_1200_172a_0000 = + {0x172a, 0x0000, pci_subsys_8086_1200_172a_0000, 0}; +#undef pci_ss_info_172a_0000 +#define pci_ss_info_172a_0000 pci_ss_info_8086_1200_172a_0000 +static const pciSubsystemInfo pci_ss_info_8086_1209_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_8086_1209_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_8086_1209_4c53_1050 +static const pciSubsystemInfo pci_ss_info_8086_1209_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_8086_1209_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_8086_1209_4c53_1051 +static const pciSubsystemInfo pci_ss_info_8086_1209_4c53_1070 = + {0x4c53, 0x1070, pci_subsys_8086_1209_4c53_1070, 0}; +#undef pci_ss_info_4c53_1070 +#define pci_ss_info_4c53_1070 pci_ss_info_8086_1209_4c53_1070 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3001 = + {0x0e11, 0x3001, pci_subsys_8086_1229_0e11_3001, 0}; +#undef pci_ss_info_0e11_3001 +#define pci_ss_info_0e11_3001 pci_ss_info_8086_1229_0e11_3001 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3002 = + {0x0e11, 0x3002, pci_subsys_8086_1229_0e11_3002, 0}; +#undef pci_ss_info_0e11_3002 +#define pci_ss_info_0e11_3002 pci_ss_info_8086_1229_0e11_3002 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3003 = + {0x0e11, 0x3003, pci_subsys_8086_1229_0e11_3003, 0}; +#undef pci_ss_info_0e11_3003 +#define pci_ss_info_0e11_3003 pci_ss_info_8086_1229_0e11_3003 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3004 = + {0x0e11, 0x3004, pci_subsys_8086_1229_0e11_3004, 0}; +#undef pci_ss_info_0e11_3004 +#define pci_ss_info_0e11_3004 pci_ss_info_8086_1229_0e11_3004 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3005 = + {0x0e11, 0x3005, pci_subsys_8086_1229_0e11_3005, 0}; +#undef pci_ss_info_0e11_3005 +#define pci_ss_info_0e11_3005 pci_ss_info_8086_1229_0e11_3005 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3006 = + {0x0e11, 0x3006, pci_subsys_8086_1229_0e11_3006, 0}; +#undef pci_ss_info_0e11_3006 +#define pci_ss_info_0e11_3006 pci_ss_info_8086_1229_0e11_3006 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_3007 = + {0x0e11, 0x3007, pci_subsys_8086_1229_0e11_3007, 0}; +#undef pci_ss_info_0e11_3007 +#define pci_ss_info_0e11_3007 pci_ss_info_8086_1229_0e11_3007 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b01e = + {0x0e11, 0xb01e, pci_subsys_8086_1229_0e11_b01e, 0}; +#undef pci_ss_info_0e11_b01e +#define pci_ss_info_0e11_b01e pci_ss_info_8086_1229_0e11_b01e +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b01f = + {0x0e11, 0xb01f, pci_subsys_8086_1229_0e11_b01f, 0}; +#undef pci_ss_info_0e11_b01f +#define pci_ss_info_0e11_b01f pci_ss_info_8086_1229_0e11_b01f +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b02f = + {0x0e11, 0xb02f, pci_subsys_8086_1229_0e11_b02f, 0}; +#undef pci_ss_info_0e11_b02f +#define pci_ss_info_0e11_b02f pci_ss_info_8086_1229_0e11_b02f +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b04a = + {0x0e11, 0xb04a, pci_subsys_8086_1229_0e11_b04a, 0}; +#undef pci_ss_info_0e11_b04a +#define pci_ss_info_0e11_b04a pci_ss_info_8086_1229_0e11_b04a +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0c6 = + {0x0e11, 0xb0c6, pci_subsys_8086_1229_0e11_b0c6, 0}; +#undef pci_ss_info_0e11_b0c6 +#define pci_ss_info_0e11_b0c6 pci_ss_info_8086_1229_0e11_b0c6 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0c7 = + {0x0e11, 0xb0c7, pci_subsys_8086_1229_0e11_b0c7, 0}; +#undef pci_ss_info_0e11_b0c7 +#define pci_ss_info_0e11_b0c7 pci_ss_info_8086_1229_0e11_b0c7 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0d7 = + {0x0e11, 0xb0d7, pci_subsys_8086_1229_0e11_b0d7, 0}; +#undef pci_ss_info_0e11_b0d7 +#define pci_ss_info_0e11_b0d7 pci_ss_info_8086_1229_0e11_b0d7 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0dd = + {0x0e11, 0xb0dd, pci_subsys_8086_1229_0e11_b0dd, 0}; +#undef pci_ss_info_0e11_b0dd +#define pci_ss_info_0e11_b0dd pci_ss_info_8086_1229_0e11_b0dd +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0de = + {0x0e11, 0xb0de, pci_subsys_8086_1229_0e11_b0de, 0}; +#undef pci_ss_info_0e11_b0de +#define pci_ss_info_0e11_b0de pci_ss_info_8086_1229_0e11_b0de +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b0e1 = + {0x0e11, 0xb0e1, pci_subsys_8086_1229_0e11_b0e1, 0}; +#undef pci_ss_info_0e11_b0e1 +#define pci_ss_info_0e11_b0e1 pci_ss_info_8086_1229_0e11_b0e1 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b134 = + {0x0e11, 0xb134, pci_subsys_8086_1229_0e11_b134, 0}; +#undef pci_ss_info_0e11_b134 +#define pci_ss_info_0e11_b134 pci_ss_info_8086_1229_0e11_b134 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b13c = + {0x0e11, 0xb13c, pci_subsys_8086_1229_0e11_b13c, 0}; +#undef pci_ss_info_0e11_b13c +#define pci_ss_info_0e11_b13c pci_ss_info_8086_1229_0e11_b13c +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b144 = + {0x0e11, 0xb144, pci_subsys_8086_1229_0e11_b144, 0}; +#undef pci_ss_info_0e11_b144 +#define pci_ss_info_0e11_b144 pci_ss_info_8086_1229_0e11_b144 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b163 = + {0x0e11, 0xb163, pci_subsys_8086_1229_0e11_b163, 0}; +#undef pci_ss_info_0e11_b163 +#define pci_ss_info_0e11_b163 pci_ss_info_8086_1229_0e11_b163 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b164 = + {0x0e11, 0xb164, pci_subsys_8086_1229_0e11_b164, 0}; +#undef pci_ss_info_0e11_b164 +#define pci_ss_info_0e11_b164 pci_ss_info_8086_1229_0e11_b164 +static const pciSubsystemInfo pci_ss_info_8086_1229_0e11_b1a4 = + {0x0e11, 0xb1a4, pci_subsys_8086_1229_0e11_b1a4, 0}; +#undef pci_ss_info_0e11_b1a4 +#define pci_ss_info_0e11_b1a4 pci_ss_info_8086_1229_0e11_b1a4 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_005c = + {0x1014, 0x005c, pci_subsys_8086_1229_1014_005c, 0}; +#undef pci_ss_info_1014_005c +#define pci_ss_info_1014_005c pci_ss_info_8086_1229_1014_005c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_01bc = + {0x1014, 0x01bc, pci_subsys_8086_1229_1014_01bc, 0}; +#undef pci_ss_info_1014_01bc +#define pci_ss_info_1014_01bc pci_ss_info_8086_1229_1014_01bc +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_01f1 = + {0x1014, 0x01f1, pci_subsys_8086_1229_1014_01f1, 0}; +#undef pci_ss_info_1014_01f1 +#define pci_ss_info_1014_01f1 pci_ss_info_8086_1229_1014_01f1 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_01f2 = + {0x1014, 0x01f2, pci_subsys_8086_1229_1014_01f2, 0}; +#undef pci_ss_info_1014_01f2 +#define pci_ss_info_1014_01f2 pci_ss_info_8086_1229_1014_01f2 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_0207 = + {0x1014, 0x0207, pci_subsys_8086_1229_1014_0207, 0}; +#undef pci_ss_info_1014_0207 +#define pci_ss_info_1014_0207 pci_ss_info_8086_1229_1014_0207 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_0232 = + {0x1014, 0x0232, pci_subsys_8086_1229_1014_0232, 0}; +#undef pci_ss_info_1014_0232 +#define pci_ss_info_1014_0232 pci_ss_info_8086_1229_1014_0232 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_023a = + {0x1014, 0x023a, pci_subsys_8086_1229_1014_023a, 0}; +#undef pci_ss_info_1014_023a +#define pci_ss_info_1014_023a pci_ss_info_8086_1229_1014_023a +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_105c = + {0x1014, 0x105c, pci_subsys_8086_1229_1014_105c, 0}; +#undef pci_ss_info_1014_105c +#define pci_ss_info_1014_105c pci_ss_info_8086_1229_1014_105c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_2205 = + {0x1014, 0x2205, pci_subsys_8086_1229_1014_2205, 0}; +#undef pci_ss_info_1014_2205 +#define pci_ss_info_1014_2205 pci_ss_info_8086_1229_1014_2205 +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_305c = + {0x1014, 0x305c, pci_subsys_8086_1229_1014_305c, 0}; +#undef pci_ss_info_1014_305c +#define pci_ss_info_1014_305c pci_ss_info_8086_1229_1014_305c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_405c = + {0x1014, 0x405c, pci_subsys_8086_1229_1014_405c, 0}; +#undef pci_ss_info_1014_405c +#define pci_ss_info_1014_405c pci_ss_info_8086_1229_1014_405c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_505c = + {0x1014, 0x505c, pci_subsys_8086_1229_1014_505c, 0}; +#undef pci_ss_info_1014_505c +#define pci_ss_info_1014_505c pci_ss_info_8086_1229_1014_505c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_605c = + {0x1014, 0x605c, pci_subsys_8086_1229_1014_605c, 0}; +#undef pci_ss_info_1014_605c +#define pci_ss_info_1014_605c pci_ss_info_8086_1229_1014_605c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_705c = + {0x1014, 0x705c, pci_subsys_8086_1229_1014_705c, 0}; +#undef pci_ss_info_1014_705c +#define pci_ss_info_1014_705c pci_ss_info_8086_1229_1014_705c +static const pciSubsystemInfo pci_ss_info_8086_1229_1014_805c = + {0x1014, 0x805c, pci_subsys_8086_1229_1014_805c, 0}; +#undef pci_ss_info_1014_805c +#define pci_ss_info_1014_805c pci_ss_info_8086_1229_1014_805c +static const pciSubsystemInfo pci_ss_info_8086_1229_1028_009b = + {0x1028, 0x009b, pci_subsys_8086_1229_1028_009b, 0}; +#undef pci_ss_info_1028_009b +#define pci_ss_info_1028_009b pci_ss_info_8086_1229_1028_009b +static const pciSubsystemInfo pci_ss_info_8086_1229_1028_00ce = + {0x1028, 0x00ce, pci_subsys_8086_1229_1028_00ce, 0}; +#undef pci_ss_info_1028_00ce +#define pci_ss_info_1028_00ce pci_ss_info_8086_1229_1028_00ce +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8000 = + {0x1033, 0x8000, pci_subsys_8086_1229_1033_8000, 0}; +#undef pci_ss_info_1033_8000 +#define pci_ss_info_1033_8000 pci_ss_info_8086_1229_1033_8000 +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8016 = + {0x1033, 0x8016, pci_subsys_8086_1229_1033_8016, 0}; +#undef pci_ss_info_1033_8016 +#define pci_ss_info_1033_8016 pci_ss_info_8086_1229_1033_8016 +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_801f = + {0x1033, 0x801f, pci_subsys_8086_1229_1033_801f, 0}; +#undef pci_ss_info_1033_801f +#define pci_ss_info_1033_801f pci_ss_info_8086_1229_1033_801f +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8026 = + {0x1033, 0x8026, pci_subsys_8086_1229_1033_8026, 0}; +#undef pci_ss_info_1033_8026 +#define pci_ss_info_1033_8026 pci_ss_info_8086_1229_1033_8026 +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8063 = + {0x1033, 0x8063, pci_subsys_8086_1229_1033_8063, 0}; +#undef pci_ss_info_1033_8063 +#define pci_ss_info_1033_8063 pci_ss_info_8086_1229_1033_8063 +static const pciSubsystemInfo pci_ss_info_8086_1229_1033_8064 = + {0x1033, 0x8064, pci_subsys_8086_1229_1033_8064, 0}; +#undef pci_ss_info_1033_8064 +#define pci_ss_info_1033_8064 pci_ss_info_8086_1229_1033_8064 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10c0 = + {0x103c, 0x10c0, pci_subsys_8086_1229_103c_10c0, 0}; +#undef pci_ss_info_103c_10c0 +#define pci_ss_info_103c_10c0 pci_ss_info_8086_1229_103c_10c0 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10c3 = + {0x103c, 0x10c3, pci_subsys_8086_1229_103c_10c3, 0}; +#undef pci_ss_info_103c_10c3 +#define pci_ss_info_103c_10c3 pci_ss_info_8086_1229_103c_10c3 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10ca = + {0x103c, 0x10ca, pci_subsys_8086_1229_103c_10ca, 0}; +#undef pci_ss_info_103c_10ca +#define pci_ss_info_103c_10ca pci_ss_info_8086_1229_103c_10ca +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10cb = + {0x103c, 0x10cb, pci_subsys_8086_1229_103c_10cb, 0}; +#undef pci_ss_info_103c_10cb +#define pci_ss_info_103c_10cb pci_ss_info_8086_1229_103c_10cb +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10e3 = + {0x103c, 0x10e3, pci_subsys_8086_1229_103c_10e3, 0}; +#undef pci_ss_info_103c_10e3 +#define pci_ss_info_103c_10e3 pci_ss_info_8086_1229_103c_10e3 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_10e4 = + {0x103c, 0x10e4, pci_subsys_8086_1229_103c_10e4, 0}; +#undef pci_ss_info_103c_10e4 +#define pci_ss_info_103c_10e4 pci_ss_info_8086_1229_103c_10e4 +static const pciSubsystemInfo pci_ss_info_8086_1229_103c_1200 = + {0x103c, 0x1200, pci_subsys_8086_1229_103c_1200, 0}; +#undef pci_ss_info_103c_1200 +#define pci_ss_info_103c_1200 pci_ss_info_8086_1229_103c_1200 +static const pciSubsystemInfo pci_ss_info_8086_1229_108e_10cf = + {0x108e, 0x10cf, pci_subsys_8086_1229_108e_10cf, 0}; +#undef pci_ss_info_108e_10cf +#define pci_ss_info_108e_10cf pci_ss_info_8086_1229_108e_10cf +static const pciSubsystemInfo pci_ss_info_8086_1229_10c3_1100 = + {0x10c3, 0x1100, pci_subsys_8086_1229_10c3_1100, 0}; +#undef pci_ss_info_10c3_1100 +#define pci_ss_info_10c3_1100 pci_ss_info_8086_1229_10c3_1100 +static const pciSubsystemInfo pci_ss_info_8086_1229_10cf_1115 = + {0x10cf, 0x1115, pci_subsys_8086_1229_10cf_1115, 0}; +#undef pci_ss_info_10cf_1115 +#define pci_ss_info_10cf_1115 pci_ss_info_8086_1229_10cf_1115 +static const pciSubsystemInfo pci_ss_info_8086_1229_10cf_1143 = + {0x10cf, 0x1143, pci_subsys_8086_1229_10cf_1143, 0}; +#undef pci_ss_info_10cf_1143 +#define pci_ss_info_10cf_1143 pci_ss_info_8086_1229_10cf_1143 +static const pciSubsystemInfo pci_ss_info_8086_1229_110a_008b = + {0x110a, 0x008b, pci_subsys_8086_1229_110a_008b, 0}; +#undef pci_ss_info_110a_008b +#define pci_ss_info_110a_008b pci_ss_info_8086_1229_110a_008b +static const pciSubsystemInfo pci_ss_info_8086_1229_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_1229_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_1229_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_1229_1179_0002 = + {0x1179, 0x0002, pci_subsys_8086_1229_1179_0002, 0}; +#undef pci_ss_info_1179_0002 +#define pci_ss_info_1179_0002 pci_ss_info_8086_1229_1179_0002 +static const pciSubsystemInfo pci_ss_info_8086_1229_1179_0003 = + {0x1179, 0x0003, pci_subsys_8086_1229_1179_0003, 0}; +#undef pci_ss_info_1179_0003 +#define pci_ss_info_1179_0003 pci_ss_info_8086_1229_1179_0003 +static const pciSubsystemInfo pci_ss_info_8086_1229_1259_2560 = + {0x1259, 0x2560, pci_subsys_8086_1229_1259_2560, 0}; +#undef pci_ss_info_1259_2560 +#define pci_ss_info_1259_2560 pci_ss_info_8086_1229_1259_2560 +static const pciSubsystemInfo pci_ss_info_8086_1229_1259_2561 = + {0x1259, 0x2561, pci_subsys_8086_1229_1259_2561, 0}; +#undef pci_ss_info_1259_2561 +#define pci_ss_info_1259_2561 pci_ss_info_8086_1229_1259_2561 +static const pciSubsystemInfo pci_ss_info_8086_1229_1266_0001 = + {0x1266, 0x0001, pci_subsys_8086_1229_1266_0001, 0}; +#undef pci_ss_info_1266_0001 +#define pci_ss_info_1266_0001 pci_ss_info_8086_1229_1266_0001 +static const pciSubsystemInfo pci_ss_info_8086_1229_13e9_1000 = + {0x13e9, 0x1000, pci_subsys_8086_1229_13e9_1000, 0}; +#undef pci_ss_info_13e9_1000 +#define pci_ss_info_13e9_1000 pci_ss_info_8086_1229_13e9_1000 +static const pciSubsystemInfo pci_ss_info_8086_1229_144d_2501 = + {0x144d, 0x2501, pci_subsys_8086_1229_144d_2501, 0}; +#undef pci_ss_info_144d_2501 +#define pci_ss_info_144d_2501 pci_ss_info_8086_1229_144d_2501 +static const pciSubsystemInfo pci_ss_info_8086_1229_144d_2502 = + {0x144d, 0x2502, pci_subsys_8086_1229_144d_2502, 0}; +#undef pci_ss_info_144d_2502 +#define pci_ss_info_144d_2502 pci_ss_info_8086_1229_144d_2502 +static const pciSubsystemInfo pci_ss_info_8086_1229_1668_1100 = + {0x1668, 0x1100, pci_subsys_8086_1229_1668_1100, 0}; +#undef pci_ss_info_1668_1100 +#define pci_ss_info_1668_1100 pci_ss_info_8086_1229_1668_1100 +static const pciSubsystemInfo pci_ss_info_8086_1229_1775_ce90 = + {0x1775, 0xce90, pci_subsys_8086_1229_1775_ce90, 0}; +#undef pci_ss_info_1775_ce90 +#define pci_ss_info_1775_ce90 pci_ss_info_8086_1229_1775_ce90 +static const pciSubsystemInfo pci_ss_info_8086_1229_4c53_1080 = + {0x4c53, 0x1080, pci_subsys_8086_1229_4c53_1080, 0}; +#undef pci_ss_info_4c53_1080 +#define pci_ss_info_4c53_1080 pci_ss_info_8086_1229_4c53_1080 +static const pciSubsystemInfo pci_ss_info_8086_1229_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_1229_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_1229_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0001 = + {0x8086, 0x0001, pci_subsys_8086_1229_8086_0001, 0}; +#undef pci_ss_info_8086_0001 +#define pci_ss_info_8086_0001 pci_ss_info_8086_1229_8086_0001 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0002 = + {0x8086, 0x0002, pci_subsys_8086_1229_8086_0002, 0}; +#undef pci_ss_info_8086_0002 +#define pci_ss_info_8086_0002 pci_ss_info_8086_1229_8086_0002 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0003 = + {0x8086, 0x0003, pci_subsys_8086_1229_8086_0003, 0}; +#undef pci_ss_info_8086_0003 +#define pci_ss_info_8086_0003 pci_ss_info_8086_1229_8086_0003 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0004 = + {0x8086, 0x0004, pci_subsys_8086_1229_8086_0004, 0}; +#undef pci_ss_info_8086_0004 +#define pci_ss_info_8086_0004 pci_ss_info_8086_1229_8086_0004 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0005 = + {0x8086, 0x0005, pci_subsys_8086_1229_8086_0005, 0}; +#undef pci_ss_info_8086_0005 +#define pci_ss_info_8086_0005 pci_ss_info_8086_1229_8086_0005 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0006 = + {0x8086, 0x0006, pci_subsys_8086_1229_8086_0006, 0}; +#undef pci_ss_info_8086_0006 +#define pci_ss_info_8086_0006 pci_ss_info_8086_1229_8086_0006 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0007 = + {0x8086, 0x0007, pci_subsys_8086_1229_8086_0007, 0}; +#undef pci_ss_info_8086_0007 +#define pci_ss_info_8086_0007 pci_ss_info_8086_1229_8086_0007 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0008 = + {0x8086, 0x0008, pci_subsys_8086_1229_8086_0008, 0}; +#undef pci_ss_info_8086_0008 +#define pci_ss_info_8086_0008 pci_ss_info_8086_1229_8086_0008 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000a = + {0x8086, 0x000a, pci_subsys_8086_1229_8086_000a, 0}; +#undef pci_ss_info_8086_000a +#define pci_ss_info_8086_000a pci_ss_info_8086_1229_8086_000a +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000b = + {0x8086, 0x000b, pci_subsys_8086_1229_8086_000b, 0}; +#undef pci_ss_info_8086_000b +#define pci_ss_info_8086_000b pci_ss_info_8086_1229_8086_000b +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000c = + {0x8086, 0x000c, pci_subsys_8086_1229_8086_000c, 0}; +#undef pci_ss_info_8086_000c +#define pci_ss_info_8086_000c pci_ss_info_8086_1229_8086_000c +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000d = + {0x8086, 0x000d, pci_subsys_8086_1229_8086_000d, 0}; +#undef pci_ss_info_8086_000d +#define pci_ss_info_8086_000d pci_ss_info_8086_1229_8086_000d +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000e = + {0x8086, 0x000e, pci_subsys_8086_1229_8086_000e, 0}; +#undef pci_ss_info_8086_000e +#define pci_ss_info_8086_000e pci_ss_info_8086_1229_8086_000e +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_000f = + {0x8086, 0x000f, pci_subsys_8086_1229_8086_000f, 0}; +#undef pci_ss_info_8086_000f +#define pci_ss_info_8086_000f pci_ss_info_8086_1229_8086_000f +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0010 = + {0x8086, 0x0010, pci_subsys_8086_1229_8086_0010, 0}; +#undef pci_ss_info_8086_0010 +#define pci_ss_info_8086_0010 pci_ss_info_8086_1229_8086_0010 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0011 = + {0x8086, 0x0011, pci_subsys_8086_1229_8086_0011, 0}; +#undef pci_ss_info_8086_0011 +#define pci_ss_info_8086_0011 pci_ss_info_8086_1229_8086_0011 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0012 = + {0x8086, 0x0012, pci_subsys_8086_1229_8086_0012, 0}; +#undef pci_ss_info_8086_0012 +#define pci_ss_info_8086_0012 pci_ss_info_8086_1229_8086_0012 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0013 = + {0x8086, 0x0013, pci_subsys_8086_1229_8086_0013, 0}; +#undef pci_ss_info_8086_0013 +#define pci_ss_info_8086_0013 pci_ss_info_8086_1229_8086_0013 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0030 = + {0x8086, 0x0030, pci_subsys_8086_1229_8086_0030, 0}; +#undef pci_ss_info_8086_0030 +#define pci_ss_info_8086_0030 pci_ss_info_8086_1229_8086_0030 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0031 = + {0x8086, 0x0031, pci_subsys_8086_1229_8086_0031, 0}; +#undef pci_ss_info_8086_0031 +#define pci_ss_info_8086_0031 pci_ss_info_8086_1229_8086_0031 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0040 = + {0x8086, 0x0040, pci_subsys_8086_1229_8086_0040, 0}; +#undef pci_ss_info_8086_0040 +#define pci_ss_info_8086_0040 pci_ss_info_8086_1229_8086_0040 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0041 = + {0x8086, 0x0041, pci_subsys_8086_1229_8086_0041, 0}; +#undef pci_ss_info_8086_0041 +#define pci_ss_info_8086_0041 pci_ss_info_8086_1229_8086_0041 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0042 = + {0x8086, 0x0042, pci_subsys_8086_1229_8086_0042, 0}; +#undef pci_ss_info_8086_0042 +#define pci_ss_info_8086_0042 pci_ss_info_8086_1229_8086_0042 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_0050 = + {0x8086, 0x0050, pci_subsys_8086_1229_8086_0050, 0}; +#undef pci_ss_info_8086_0050 +#define pci_ss_info_8086_0050 pci_ss_info_8086_1229_8086_0050 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1009 = + {0x8086, 0x1009, pci_subsys_8086_1229_8086_1009, 0}; +#undef pci_ss_info_8086_1009 +#define pci_ss_info_8086_1009 pci_ss_info_8086_1229_8086_1009 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_100c = + {0x8086, 0x100c, pci_subsys_8086_1229_8086_100c, 0}; +#undef pci_ss_info_8086_100c +#define pci_ss_info_8086_100c pci_ss_info_8086_1229_8086_100c +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1012 = + {0x8086, 0x1012, pci_subsys_8086_1229_8086_1012, 0}; +#undef pci_ss_info_8086_1012 +#define pci_ss_info_8086_1012 pci_ss_info_8086_1229_8086_1012 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1013 = + {0x8086, 0x1013, pci_subsys_8086_1229_8086_1013, 0}; +#undef pci_ss_info_8086_1013 +#define pci_ss_info_8086_1013 pci_ss_info_8086_1229_8086_1013 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1015 = + {0x8086, 0x1015, pci_subsys_8086_1229_8086_1015, 0}; +#undef pci_ss_info_8086_1015 +#define pci_ss_info_8086_1015 pci_ss_info_8086_1229_8086_1015 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1017 = + {0x8086, 0x1017, pci_subsys_8086_1229_8086_1017, 0}; +#undef pci_ss_info_8086_1017 +#define pci_ss_info_8086_1017 pci_ss_info_8086_1229_8086_1017 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1030 = + {0x8086, 0x1030, pci_subsys_8086_1229_8086_1030, 0}; +#undef pci_ss_info_8086_1030 +#define pci_ss_info_8086_1030 pci_ss_info_8086_1229_8086_1030 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1040 = + {0x8086, 0x1040, pci_subsys_8086_1229_8086_1040, 0}; +#undef pci_ss_info_8086_1040 +#define pci_ss_info_8086_1040 pci_ss_info_8086_1229_8086_1040 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1041 = + {0x8086, 0x1041, pci_subsys_8086_1229_8086_1041, 0}; +#undef pci_ss_info_8086_1041 +#define pci_ss_info_8086_1041 pci_ss_info_8086_1229_8086_1041 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1042 = + {0x8086, 0x1042, pci_subsys_8086_1229_8086_1042, 0}; +#undef pci_ss_info_8086_1042 +#define pci_ss_info_8086_1042 pci_ss_info_8086_1229_8086_1042 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1050 = + {0x8086, 0x1050, pci_subsys_8086_1229_8086_1050, 0}; +#undef pci_ss_info_8086_1050 +#define pci_ss_info_8086_1050 pci_ss_info_8086_1229_8086_1050 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1051 = + {0x8086, 0x1051, pci_subsys_8086_1229_8086_1051, 0}; +#undef pci_ss_info_8086_1051 +#define pci_ss_info_8086_1051 pci_ss_info_8086_1229_8086_1051 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_1052 = + {0x8086, 0x1052, pci_subsys_8086_1229_8086_1052, 0}; +#undef pci_ss_info_8086_1052 +#define pci_ss_info_8086_1052 pci_ss_info_8086_1229_8086_1052 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_10f0 = + {0x8086, 0x10f0, pci_subsys_8086_1229_8086_10f0, 0}; +#undef pci_ss_info_8086_10f0 +#define pci_ss_info_8086_10f0 pci_ss_info_8086_1229_8086_10f0 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2009 = + {0x8086, 0x2009, pci_subsys_8086_1229_8086_2009, 0}; +#undef pci_ss_info_8086_2009 +#define pci_ss_info_8086_2009 pci_ss_info_8086_1229_8086_2009 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_200d = + {0x8086, 0x200d, pci_subsys_8086_1229_8086_200d, 0}; +#undef pci_ss_info_8086_200d +#define pci_ss_info_8086_200d pci_ss_info_8086_1229_8086_200d +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_200e = + {0x8086, 0x200e, pci_subsys_8086_1229_8086_200e, 0}; +#undef pci_ss_info_8086_200e +#define pci_ss_info_8086_200e pci_ss_info_8086_1229_8086_200e +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_200f = + {0x8086, 0x200f, pci_subsys_8086_1229_8086_200f, 0}; +#undef pci_ss_info_8086_200f +#define pci_ss_info_8086_200f pci_ss_info_8086_1229_8086_200f +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2010 = + {0x8086, 0x2010, pci_subsys_8086_1229_8086_2010, 0}; +#undef pci_ss_info_8086_2010 +#define pci_ss_info_8086_2010 pci_ss_info_8086_1229_8086_2010 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2013 = + {0x8086, 0x2013, pci_subsys_8086_1229_8086_2013, 0}; +#undef pci_ss_info_8086_2013 +#define pci_ss_info_8086_2013 pci_ss_info_8086_1229_8086_2013 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2016 = + {0x8086, 0x2016, pci_subsys_8086_1229_8086_2016, 0}; +#undef pci_ss_info_8086_2016 +#define pci_ss_info_8086_2016 pci_ss_info_8086_1229_8086_2016 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2017 = + {0x8086, 0x2017, pci_subsys_8086_1229_8086_2017, 0}; +#undef pci_ss_info_8086_2017 +#define pci_ss_info_8086_2017 pci_ss_info_8086_1229_8086_2017 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2018 = + {0x8086, 0x2018, pci_subsys_8086_1229_8086_2018, 0}; +#undef pci_ss_info_8086_2018 +#define pci_ss_info_8086_2018 pci_ss_info_8086_1229_8086_2018 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2019 = + {0x8086, 0x2019, pci_subsys_8086_1229_8086_2019, 0}; +#undef pci_ss_info_8086_2019 +#define pci_ss_info_8086_2019 pci_ss_info_8086_1229_8086_2019 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2101 = + {0x8086, 0x2101, pci_subsys_8086_1229_8086_2101, 0}; +#undef pci_ss_info_8086_2101 +#define pci_ss_info_8086_2101 pci_ss_info_8086_1229_8086_2101 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2102 = + {0x8086, 0x2102, pci_subsys_8086_1229_8086_2102, 0}; +#undef pci_ss_info_8086_2102 +#define pci_ss_info_8086_2102 pci_ss_info_8086_1229_8086_2102 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2103 = + {0x8086, 0x2103, pci_subsys_8086_1229_8086_2103, 0}; +#undef pci_ss_info_8086_2103 +#define pci_ss_info_8086_2103 pci_ss_info_8086_1229_8086_2103 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2104 = + {0x8086, 0x2104, pci_subsys_8086_1229_8086_2104, 0}; +#undef pci_ss_info_8086_2104 +#define pci_ss_info_8086_2104 pci_ss_info_8086_1229_8086_2104 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2105 = + {0x8086, 0x2105, pci_subsys_8086_1229_8086_2105, 0}; +#undef pci_ss_info_8086_2105 +#define pci_ss_info_8086_2105 pci_ss_info_8086_1229_8086_2105 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2106 = + {0x8086, 0x2106, pci_subsys_8086_1229_8086_2106, 0}; +#undef pci_ss_info_8086_2106 +#define pci_ss_info_8086_2106 pci_ss_info_8086_1229_8086_2106 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2107 = + {0x8086, 0x2107, pci_subsys_8086_1229_8086_2107, 0}; +#undef pci_ss_info_8086_2107 +#define pci_ss_info_8086_2107 pci_ss_info_8086_1229_8086_2107 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2108 = + {0x8086, 0x2108, pci_subsys_8086_1229_8086_2108, 0}; +#undef pci_ss_info_8086_2108 +#define pci_ss_info_8086_2108 pci_ss_info_8086_1229_8086_2108 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2200 = + {0x8086, 0x2200, pci_subsys_8086_1229_8086_2200, 0}; +#undef pci_ss_info_8086_2200 +#define pci_ss_info_8086_2200 pci_ss_info_8086_1229_8086_2200 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2201 = + {0x8086, 0x2201, pci_subsys_8086_1229_8086_2201, 0}; +#undef pci_ss_info_8086_2201 +#define pci_ss_info_8086_2201 pci_ss_info_8086_1229_8086_2201 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2202 = + {0x8086, 0x2202, pci_subsys_8086_1229_8086_2202, 0}; +#undef pci_ss_info_8086_2202 +#define pci_ss_info_8086_2202 pci_ss_info_8086_1229_8086_2202 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2203 = + {0x8086, 0x2203, pci_subsys_8086_1229_8086_2203, 0}; +#undef pci_ss_info_8086_2203 +#define pci_ss_info_8086_2203 pci_ss_info_8086_1229_8086_2203 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2204 = + {0x8086, 0x2204, pci_subsys_8086_1229_8086_2204, 0}; +#undef pci_ss_info_8086_2204 +#define pci_ss_info_8086_2204 pci_ss_info_8086_1229_8086_2204 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2205 = + {0x8086, 0x2205, pci_subsys_8086_1229_8086_2205, 0}; +#undef pci_ss_info_8086_2205 +#define pci_ss_info_8086_2205 pci_ss_info_8086_1229_8086_2205 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2206 = + {0x8086, 0x2206, pci_subsys_8086_1229_8086_2206, 0}; +#undef pci_ss_info_8086_2206 +#define pci_ss_info_8086_2206 pci_ss_info_8086_1229_8086_2206 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2207 = + {0x8086, 0x2207, pci_subsys_8086_1229_8086_2207, 0}; +#undef pci_ss_info_8086_2207 +#define pci_ss_info_8086_2207 pci_ss_info_8086_1229_8086_2207 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2208 = + {0x8086, 0x2208, pci_subsys_8086_1229_8086_2208, 0}; +#undef pci_ss_info_8086_2208 +#define pci_ss_info_8086_2208 pci_ss_info_8086_1229_8086_2208 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2402 = + {0x8086, 0x2402, pci_subsys_8086_1229_8086_2402, 0}; +#undef pci_ss_info_8086_2402 +#define pci_ss_info_8086_2402 pci_ss_info_8086_1229_8086_2402 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2407 = + {0x8086, 0x2407, pci_subsys_8086_1229_8086_2407, 0}; +#undef pci_ss_info_8086_2407 +#define pci_ss_info_8086_2407 pci_ss_info_8086_1229_8086_2407 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2408 = + {0x8086, 0x2408, pci_subsys_8086_1229_8086_2408, 0}; +#undef pci_ss_info_8086_2408 +#define pci_ss_info_8086_2408 pci_ss_info_8086_1229_8086_2408 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2409 = + {0x8086, 0x2409, pci_subsys_8086_1229_8086_2409, 0}; +#undef pci_ss_info_8086_2409 +#define pci_ss_info_8086_2409 pci_ss_info_8086_1229_8086_2409 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_240f = + {0x8086, 0x240f, pci_subsys_8086_1229_8086_240f, 0}; +#undef pci_ss_info_8086_240f +#define pci_ss_info_8086_240f pci_ss_info_8086_1229_8086_240f +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2410 = + {0x8086, 0x2410, pci_subsys_8086_1229_8086_2410, 0}; +#undef pci_ss_info_8086_2410 +#define pci_ss_info_8086_2410 pci_ss_info_8086_1229_8086_2410 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2411 = + {0x8086, 0x2411, pci_subsys_8086_1229_8086_2411, 0}; +#undef pci_ss_info_8086_2411 +#define pci_ss_info_8086_2411 pci_ss_info_8086_1229_8086_2411 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2412 = + {0x8086, 0x2412, pci_subsys_8086_1229_8086_2412, 0}; +#undef pci_ss_info_8086_2412 +#define pci_ss_info_8086_2412 pci_ss_info_8086_1229_8086_2412 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_2413 = + {0x8086, 0x2413, pci_subsys_8086_1229_8086_2413, 0}; +#undef pci_ss_info_8086_2413 +#define pci_ss_info_8086_2413 pci_ss_info_8086_1229_8086_2413 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3000 = + {0x8086, 0x3000, pci_subsys_8086_1229_8086_3000, 0}; +#undef pci_ss_info_8086_3000 +#define pci_ss_info_8086_3000 pci_ss_info_8086_1229_8086_3000 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3001 = + {0x8086, 0x3001, pci_subsys_8086_1229_8086_3001, 0}; +#undef pci_ss_info_8086_3001 +#define pci_ss_info_8086_3001 pci_ss_info_8086_1229_8086_3001 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3002 = + {0x8086, 0x3002, pci_subsys_8086_1229_8086_3002, 0}; +#undef pci_ss_info_8086_3002 +#define pci_ss_info_8086_3002 pci_ss_info_8086_1229_8086_3002 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3006 = + {0x8086, 0x3006, pci_subsys_8086_1229_8086_3006, 0}; +#undef pci_ss_info_8086_3006 +#define pci_ss_info_8086_3006 pci_ss_info_8086_1229_8086_3006 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3007 = + {0x8086, 0x3007, pci_subsys_8086_1229_8086_3007, 0}; +#undef pci_ss_info_8086_3007 +#define pci_ss_info_8086_3007 pci_ss_info_8086_1229_8086_3007 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3008 = + {0x8086, 0x3008, pci_subsys_8086_1229_8086_3008, 0}; +#undef pci_ss_info_8086_3008 +#define pci_ss_info_8086_3008 pci_ss_info_8086_1229_8086_3008 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3010 = + {0x8086, 0x3010, pci_subsys_8086_1229_8086_3010, 0}; +#undef pci_ss_info_8086_3010 +#define pci_ss_info_8086_3010 pci_ss_info_8086_1229_8086_3010 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3011 = + {0x8086, 0x3011, pci_subsys_8086_1229_8086_3011, 0}; +#undef pci_ss_info_8086_3011 +#define pci_ss_info_8086_3011 pci_ss_info_8086_1229_8086_3011 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3012 = + {0x8086, 0x3012, pci_subsys_8086_1229_8086_3012, 0}; +#undef pci_ss_info_8086_3012 +#define pci_ss_info_8086_3012 pci_ss_info_8086_1229_8086_3012 +static const pciSubsystemInfo pci_ss_info_8086_1229_8086_3411 = + {0x8086, 0x3411, pci_subsys_8086_1229_8086_3411, 0}; +#undef pci_ss_info_8086_3411 +#define pci_ss_info_8086_3411 pci_ss_info_8086_1229_8086_3411 +static const pciSubsystemInfo pci_ss_info_8086_1361_8086_1361 = + {0x8086, 0x1361, pci_subsys_8086_1361_8086_1361, 0}; +#undef pci_ss_info_8086_1361 +#define pci_ss_info_8086_1361 pci_ss_info_8086_1361_8086_1361 +static const pciSubsystemInfo pci_ss_info_8086_1361_8086_8000 = + {0x8086, 0x8000, pci_subsys_8086_1361_8086_8000, 0}; +#undef pci_ss_info_8086_8000 +#define pci_ss_info_8086_8000 pci_ss_info_8086_1361_8086_8000 +static const pciSubsystemInfo pci_ss_info_8086_1461_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_1461_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_1461_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_1461_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_1461_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_1461_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0431 = + {0x101e, 0x0431, pci_subsys_8086_1960_101e_0431, 0}; +#undef pci_ss_info_101e_0431 +#define pci_ss_info_101e_0431 pci_ss_info_8086_1960_101e_0431 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0438 = + {0x101e, 0x0438, pci_subsys_8086_1960_101e_0438, 0}; +#undef pci_ss_info_101e_0438 +#define pci_ss_info_101e_0438 pci_ss_info_8086_1960_101e_0438 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0466 = + {0x101e, 0x0466, pci_subsys_8086_1960_101e_0466, 0}; +#undef pci_ss_info_101e_0466 +#define pci_ss_info_101e_0466 pci_ss_info_8086_1960_101e_0466 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0467 = + {0x101e, 0x0467, pci_subsys_8086_1960_101e_0467, 0}; +#undef pci_ss_info_101e_0467 +#define pci_ss_info_101e_0467 pci_ss_info_8086_1960_101e_0467 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0490 = + {0x101e, 0x0490, pci_subsys_8086_1960_101e_0490, 0}; +#undef pci_ss_info_101e_0490 +#define pci_ss_info_101e_0490 pci_ss_info_8086_1960_101e_0490 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_0762 = + {0x101e, 0x0762, pci_subsys_8086_1960_101e_0762, 0}; +#undef pci_ss_info_101e_0762 +#define pci_ss_info_101e_0762 pci_ss_info_8086_1960_101e_0762 +static const pciSubsystemInfo pci_ss_info_8086_1960_101e_09a0 = + {0x101e, 0x09a0, pci_subsys_8086_1960_101e_09a0, 0}; +#undef pci_ss_info_101e_09a0 +#define pci_ss_info_101e_09a0 pci_ss_info_8086_1960_101e_09a0 +static const pciSubsystemInfo pci_ss_info_8086_1960_1028_0467 = + {0x1028, 0x0467, pci_subsys_8086_1960_1028_0467, 0}; +#undef pci_ss_info_1028_0467 +#define pci_ss_info_1028_0467 pci_ss_info_8086_1960_1028_0467 +static const pciSubsystemInfo pci_ss_info_8086_1960_1028_1111 = + {0x1028, 0x1111, pci_subsys_8086_1960_1028_1111, 0}; +#undef pci_ss_info_1028_1111 +#define pci_ss_info_1028_1111 pci_ss_info_8086_1960_1028_1111 +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_03a2 = + {0x103c, 0x03a2, pci_subsys_8086_1960_103c_03a2, 0}; +#undef pci_ss_info_103c_03a2 +#define pci_ss_info_103c_03a2 pci_ss_info_8086_1960_103c_03a2 +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_10c6 = + {0x103c, 0x10c6, pci_subsys_8086_1960_103c_10c6, 0}; +#undef pci_ss_info_103c_10c6 +#define pci_ss_info_103c_10c6 pci_ss_info_8086_1960_103c_10c6 +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_10c7 = + {0x103c, 0x10c7, pci_subsys_8086_1960_103c_10c7, 0}; +#undef pci_ss_info_103c_10c7 +#define pci_ss_info_103c_10c7 pci_ss_info_8086_1960_103c_10c7 +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_10cc = + {0x103c, 0x10cc, pci_subsys_8086_1960_103c_10cc, 0}; +#undef pci_ss_info_103c_10cc +#define pci_ss_info_103c_10cc pci_ss_info_8086_1960_103c_10cc +static const pciSubsystemInfo pci_ss_info_8086_1960_103c_10cd = + {0x103c, 0x10cd, pci_subsys_8086_1960_103c_10cd, 0}; +#undef pci_ss_info_103c_10cd +#define pci_ss_info_103c_10cd pci_ss_info_8086_1960_103c_10cd +static const pciSubsystemInfo pci_ss_info_8086_1960_105a_0000 = + {0x105a, 0x0000, pci_subsys_8086_1960_105a_0000, 0}; +#undef pci_ss_info_105a_0000 +#define pci_ss_info_105a_0000 pci_ss_info_8086_1960_105a_0000 +static const pciSubsystemInfo pci_ss_info_8086_1960_105a_2168 = + {0x105a, 0x2168, pci_subsys_8086_1960_105a_2168, 0}; +#undef pci_ss_info_105a_2168 +#define pci_ss_info_105a_2168 pci_ss_info_8086_1960_105a_2168 +static const pciSubsystemInfo pci_ss_info_8086_1960_105a_5168 = + {0x105a, 0x5168, pci_subsys_8086_1960_105a_5168, 0}; +#undef pci_ss_info_105a_5168 +#define pci_ss_info_105a_5168 pci_ss_info_8086_1960_105a_5168 +static const pciSubsystemInfo pci_ss_info_8086_1960_1111_1111 = + {0x1111, 0x1111, pci_subsys_8086_1960_1111_1111, 0}; +#undef pci_ss_info_1111_1111 +#define pci_ss_info_1111_1111 pci_ss_info_8086_1960_1111_1111 +static const pciSubsystemInfo pci_ss_info_8086_1960_1111_1112 = + {0x1111, 0x1112, pci_subsys_8086_1960_1111_1112, 0}; +#undef pci_ss_info_1111_1112 +#define pci_ss_info_1111_1112 pci_ss_info_8086_1960_1111_1112 +static const pciSubsystemInfo pci_ss_info_8086_1960_113c_03a2 = + {0x113c, 0x03a2, pci_subsys_8086_1960_113c_03a2, 0}; +#undef pci_ss_info_113c_03a2 +#define pci_ss_info_113c_03a2 pci_ss_info_8086_1960_113c_03a2 +static const pciSubsystemInfo pci_ss_info_8086_1960_e4bf_1010 = + {0xe4bf, 0x1010, pci_subsys_8086_1960_e4bf_1010, 0}; +#undef pci_ss_info_e4bf_1010 +#define pci_ss_info_e4bf_1010 pci_ss_info_8086_1960_e4bf_1010 +static const pciSubsystemInfo pci_ss_info_8086_1960_e4bf_1020 = + {0xe4bf, 0x1020, pci_subsys_8086_1960_e4bf_1020, 0}; +#undef pci_ss_info_e4bf_1020 +#define pci_ss_info_e4bf_1020 pci_ss_info_8086_1960_e4bf_1020 +static const pciSubsystemInfo pci_ss_info_8086_1960_e4bf_1040 = + {0xe4bf, 0x1040, pci_subsys_8086_1960_e4bf_1040, 0}; +#undef pci_ss_info_e4bf_1040 +#define pci_ss_info_e4bf_1040 pci_ss_info_8086_1960_e4bf_1040 +static const pciSubsystemInfo pci_ss_info_8086_1960_e4bf_3100 = + {0xe4bf, 0x3100, pci_subsys_8086_1960_e4bf_3100, 0}; +#undef pci_ss_info_e4bf_3100 +#define pci_ss_info_e4bf_3100 pci_ss_info_8086_1960_e4bf_3100 +static const pciSubsystemInfo pci_ss_info_8086_1962_105a_0000 = + {0x105a, 0x0000, pci_subsys_8086_1962_105a_0000, 0}; +#undef pci_ss_info_105a_0000 +#define pci_ss_info_105a_0000 pci_ss_info_8086_1962_105a_0000 +static const pciSubsystemInfo pci_ss_info_8086_1a30_1028_010e = + {0x1028, 0x010e, pci_subsys_8086_1a30_1028_010e, 0}; +#undef pci_ss_info_1028_010e +#define pci_ss_info_1028_010e pci_ss_info_8086_1a30_1028_010e +static const pciSubsystemInfo pci_ss_info_8086_2415_1028_0095 = + {0x1028, 0x0095, pci_subsys_8086_2415_1028_0095, 0}; +#undef pci_ss_info_1028_0095 +#define pci_ss_info_1028_0095 pci_ss_info_8086_2415_1028_0095 +static const pciSubsystemInfo pci_ss_info_8086_2415_110a_0051 = + {0x110a, 0x0051, pci_subsys_8086_2415_110a_0051, 0}; +#undef pci_ss_info_110a_0051 +#define pci_ss_info_110a_0051 pci_ss_info_8086_2415_110a_0051 +static const pciSubsystemInfo pci_ss_info_8086_2415_11d4_0040 = + {0x11d4, 0x0040, pci_subsys_8086_2415_11d4_0040, 0}; +#undef pci_ss_info_11d4_0040 +#define pci_ss_info_11d4_0040 pci_ss_info_8086_2415_11d4_0040 +static const pciSubsystemInfo pci_ss_info_8086_2415_11d4_0048 = + {0x11d4, 0x0048, pci_subsys_8086_2415_11d4_0048, 0}; +#undef pci_ss_info_11d4_0048 +#define pci_ss_info_11d4_0048 pci_ss_info_8086_2415_11d4_0048 +static const pciSubsystemInfo pci_ss_info_8086_2415_11d4_5340 = + {0x11d4, 0x5340, pci_subsys_8086_2415_11d4_5340, 0}; +#undef pci_ss_info_11d4_5340 +#define pci_ss_info_11d4_5340 pci_ss_info_8086_2415_11d4_5340 +static const pciSubsystemInfo pci_ss_info_8086_2415_1734_1025 = + {0x1734, 0x1025, pci_subsys_8086_2415_1734_1025, 0}; +#undef pci_ss_info_1734_1025 +#define pci_ss_info_1734_1025 pci_ss_info_8086_2415_1734_1025 +static const pciSubsystemInfo pci_ss_info_8086_2425_11d4_0040 = + {0x11d4, 0x0040, pci_subsys_8086_2425_11d4_0040, 0}; +#undef pci_ss_info_11d4_0040 +#define pci_ss_info_11d4_0040 pci_ss_info_8086_2425_11d4_0040 +static const pciSubsystemInfo pci_ss_info_8086_2425_11d4_0048 = + {0x11d4, 0x0048, pci_subsys_8086_2425_11d4_0048, 0}; +#undef pci_ss_info_11d4_0048 +#define pci_ss_info_11d4_0048 pci_ss_info_8086_2425_11d4_0048 +static const pciSubsystemInfo pci_ss_info_8086_2442_1014_01c6 = + {0x1014, 0x01c6, pci_subsys_8086_2442_1014_01c6, 0}; +#undef pci_ss_info_1014_01c6 +#define pci_ss_info_1014_01c6 pci_ss_info_8086_2442_1014_01c6 +static const pciSubsystemInfo pci_ss_info_8086_2442_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2442_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2442_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2442_1028_00c7 = + {0x1028, 0x00c7, pci_subsys_8086_2442_1028_00c7, 0}; +#undef pci_ss_info_1028_00c7 +#define pci_ss_info_1028_00c7 pci_ss_info_8086_2442_1028_00c7 +static const pciSubsystemInfo pci_ss_info_8086_2442_1028_010e = + {0x1028, 0x010e, pci_subsys_8086_2442_1028_010e, 0}; +#undef pci_ss_info_1028_010e +#define pci_ss_info_1028_010e pci_ss_info_8086_2442_1028_010e +static const pciSubsystemInfo pci_ss_info_8086_2442_1043_8027 = + {0x1043, 0x8027, pci_subsys_8086_2442_1043_8027, 0}; +#undef pci_ss_info_1043_8027 +#define pci_ss_info_1043_8027 pci_ss_info_8086_2442_1043_8027 +static const pciSubsystemInfo pci_ss_info_8086_2442_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2442_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2442_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2442_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2442_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2442_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2442_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_2442_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_2442_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_2442_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_2442_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_2442_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_2443_1014_01c6 = + {0x1014, 0x01c6, pci_subsys_8086_2443_1014_01c6, 0}; +#undef pci_ss_info_1014_01c6 +#define pci_ss_info_1014_01c6 pci_ss_info_8086_2443_1014_01c6 +static const pciSubsystemInfo pci_ss_info_8086_2443_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2443_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2443_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2443_1028_00c7 = + {0x1028, 0x00c7, pci_subsys_8086_2443_1028_00c7, 0}; +#undef pci_ss_info_1028_00c7 +#define pci_ss_info_1028_00c7 pci_ss_info_8086_2443_1028_00c7 +static const pciSubsystemInfo pci_ss_info_8086_2443_1028_010e = + {0x1028, 0x010e, pci_subsys_8086_2443_1028_010e, 0}; +#undef pci_ss_info_1028_010e +#define pci_ss_info_1028_010e pci_ss_info_8086_2443_1028_010e +static const pciSubsystemInfo pci_ss_info_8086_2443_1043_8027 = + {0x1043, 0x8027, pci_subsys_8086_2443_1043_8027, 0}; +#undef pci_ss_info_1043_8027 +#define pci_ss_info_1043_8027 pci_ss_info_8086_2443_1043_8027 +static const pciSubsystemInfo pci_ss_info_8086_2443_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2443_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2443_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2443_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2443_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2443_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2443_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_2443_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_2443_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_2443_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_2443_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_2443_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_2444_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2444_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2444_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2444_1028_00c7 = + {0x1028, 0x00c7, pci_subsys_8086_2444_1028_00c7, 0}; +#undef pci_ss_info_1028_00c7 +#define pci_ss_info_1028_00c7 pci_ss_info_8086_2444_1028_00c7 +static const pciSubsystemInfo pci_ss_info_8086_2444_1028_010e = + {0x1028, 0x010e, pci_subsys_8086_2444_1028_010e, 0}; +#undef pci_ss_info_1028_010e +#define pci_ss_info_1028_010e pci_ss_info_8086_2444_1028_010e +static const pciSubsystemInfo pci_ss_info_8086_2444_1043_8027 = + {0x1043, 0x8027, pci_subsys_8086_2444_1043_8027, 0}; +#undef pci_ss_info_1043_8027 +#define pci_ss_info_1043_8027 pci_ss_info_8086_2444_1043_8027 +static const pciSubsystemInfo pci_ss_info_8086_2444_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2444_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2444_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2444_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2444_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2444_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2444_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_2444_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_2444_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_2445_0e11_0088 = + {0x0e11, 0x0088, pci_subsys_8086_2445_0e11_0088, 0}; +#undef pci_ss_info_0e11_0088 +#define pci_ss_info_0e11_0088 pci_ss_info_8086_2445_0e11_0088 +static const pciSubsystemInfo pci_ss_info_8086_2445_1014_01c6 = + {0x1014, 0x01c6, pci_subsys_8086_2445_1014_01c6, 0}; +#undef pci_ss_info_1014_01c6 +#define pci_ss_info_1014_01c6 pci_ss_info_8086_2445_1014_01c6 +static const pciSubsystemInfo pci_ss_info_8086_2445_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2445_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2445_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2445_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2445_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2445_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2445_1462_3370 = + {0x1462, 0x3370, pci_subsys_8086_2445_1462_3370, 0}; +#undef pci_ss_info_1462_3370 +#define pci_ss_info_1462_3370 pci_ss_info_8086_2445_1462_3370 +static const pciSubsystemInfo pci_ss_info_8086_2445_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2445_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2445_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2445_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_2445_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_2445_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_2446_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_2446_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_2446_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_2446_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_2446_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_2446_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_2448_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2448_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2448_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2448_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_2448_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_2448_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_2449_0e11_0012 = + {0x0e11, 0x0012, pci_subsys_8086_2449_0e11_0012, 0}; +#undef pci_ss_info_0e11_0012 +#define pci_ss_info_0e11_0012 pci_ss_info_8086_2449_0e11_0012 +static const pciSubsystemInfo pci_ss_info_8086_2449_0e11_0091 = + {0x0e11, 0x0091, pci_subsys_8086_2449_0e11_0091, 0}; +#undef pci_ss_info_0e11_0091 +#define pci_ss_info_0e11_0091 pci_ss_info_8086_2449_0e11_0091 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_01ce = + {0x1014, 0x01ce, pci_subsys_8086_2449_1014_01ce, 0}; +#undef pci_ss_info_1014_01ce +#define pci_ss_info_1014_01ce pci_ss_info_8086_2449_1014_01ce +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_01dc = + {0x1014, 0x01dc, pci_subsys_8086_2449_1014_01dc, 0}; +#undef pci_ss_info_1014_01dc +#define pci_ss_info_1014_01dc pci_ss_info_8086_2449_1014_01dc +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_01eb = + {0x1014, 0x01eb, pci_subsys_8086_2449_1014_01eb, 0}; +#undef pci_ss_info_1014_01eb +#define pci_ss_info_1014_01eb pci_ss_info_8086_2449_1014_01eb +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_01ec = + {0x1014, 0x01ec, pci_subsys_8086_2449_1014_01ec, 0}; +#undef pci_ss_info_1014_01ec +#define pci_ss_info_1014_01ec pci_ss_info_8086_2449_1014_01ec +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0202 = + {0x1014, 0x0202, pci_subsys_8086_2449_1014_0202, 0}; +#undef pci_ss_info_1014_0202 +#define pci_ss_info_1014_0202 pci_ss_info_8086_2449_1014_0202 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0205 = + {0x1014, 0x0205, pci_subsys_8086_2449_1014_0205, 0}; +#undef pci_ss_info_1014_0205 +#define pci_ss_info_1014_0205 pci_ss_info_8086_2449_1014_0205 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0217 = + {0x1014, 0x0217, pci_subsys_8086_2449_1014_0217, 0}; +#undef pci_ss_info_1014_0217 +#define pci_ss_info_1014_0217 pci_ss_info_8086_2449_1014_0217 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0234 = + {0x1014, 0x0234, pci_subsys_8086_2449_1014_0234, 0}; +#undef pci_ss_info_1014_0234 +#define pci_ss_info_1014_0234 pci_ss_info_8086_2449_1014_0234 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_023d = + {0x1014, 0x023d, pci_subsys_8086_2449_1014_023d, 0}; +#undef pci_ss_info_1014_023d +#define pci_ss_info_1014_023d pci_ss_info_8086_2449_1014_023d +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0244 = + {0x1014, 0x0244, pci_subsys_8086_2449_1014_0244, 0}; +#undef pci_ss_info_1014_0244 +#define pci_ss_info_1014_0244 pci_ss_info_8086_2449_1014_0244 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0245 = + {0x1014, 0x0245, pci_subsys_8086_2449_1014_0245, 0}; +#undef pci_ss_info_1014_0245 +#define pci_ss_info_1014_0245 pci_ss_info_8086_2449_1014_0245 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0265 = + {0x1014, 0x0265, pci_subsys_8086_2449_1014_0265, 0}; +#undef pci_ss_info_1014_0265 +#define pci_ss_info_1014_0265 pci_ss_info_8086_2449_1014_0265 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_2449_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_2449_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_2449_1014_026a = + {0x1014, 0x026a, pci_subsys_8086_2449_1014_026a, 0}; +#undef pci_ss_info_1014_026a +#define pci_ss_info_1014_026a pci_ss_info_8086_2449_1014_026a +static const pciSubsystemInfo pci_ss_info_8086_2449_109f_315d = + {0x109f, 0x315d, pci_subsys_8086_2449_109f_315d, 0}; +#undef pci_ss_info_109f_315d +#define pci_ss_info_109f_315d pci_ss_info_8086_2449_109f_315d +static const pciSubsystemInfo pci_ss_info_8086_2449_109f_3181 = + {0x109f, 0x3181, pci_subsys_8086_2449_109f_3181, 0}; +#undef pci_ss_info_109f_3181 +#define pci_ss_info_109f_3181 pci_ss_info_8086_2449_109f_3181 +static const pciSubsystemInfo pci_ss_info_8086_2449_1179_ff01 = + {0x1179, 0xff01, pci_subsys_8086_2449_1179_ff01, 0}; +#undef pci_ss_info_1179_ff01 +#define pci_ss_info_1179_ff01 pci_ss_info_8086_2449_1179_ff01 +static const pciSubsystemInfo pci_ss_info_8086_2449_1186_7801 = + {0x1186, 0x7801, pci_subsys_8086_2449_1186_7801, 0}; +#undef pci_ss_info_1186_7801 +#define pci_ss_info_1186_7801 pci_ss_info_8086_2449_1186_7801 +static const pciSubsystemInfo pci_ss_info_8086_2449_144d_2602 = + {0x144d, 0x2602, pci_subsys_8086_2449_144d_2602, 0}; +#undef pci_ss_info_144d_2602 +#define pci_ss_info_144d_2602 pci_ss_info_8086_2449_144d_2602 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3010 = + {0x8086, 0x3010, pci_subsys_8086_2449_8086_3010, 0}; +#undef pci_ss_info_8086_3010 +#define pci_ss_info_8086_3010 pci_ss_info_8086_2449_8086_3010 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3011 = + {0x8086, 0x3011, pci_subsys_8086_2449_8086_3011, 0}; +#undef pci_ss_info_8086_3011 +#define pci_ss_info_8086_3011 pci_ss_info_8086_2449_8086_3011 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3012 = + {0x8086, 0x3012, pci_subsys_8086_2449_8086_3012, 0}; +#undef pci_ss_info_8086_3012 +#define pci_ss_info_8086_3012 pci_ss_info_8086_2449_8086_3012 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3013 = + {0x8086, 0x3013, pci_subsys_8086_2449_8086_3013, 0}; +#undef pci_ss_info_8086_3013 +#define pci_ss_info_8086_3013 pci_ss_info_8086_2449_8086_3013 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3014 = + {0x8086, 0x3014, pci_subsys_8086_2449_8086_3014, 0}; +#undef pci_ss_info_8086_3014 +#define pci_ss_info_8086_3014 pci_ss_info_8086_2449_8086_3014 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3015 = + {0x8086, 0x3015, pci_subsys_8086_2449_8086_3015, 0}; +#undef pci_ss_info_8086_3015 +#define pci_ss_info_8086_3015 pci_ss_info_8086_2449_8086_3015 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3016 = + {0x8086, 0x3016, pci_subsys_8086_2449_8086_3016, 0}; +#undef pci_ss_info_8086_3016 +#define pci_ss_info_8086_3016 pci_ss_info_8086_2449_8086_3016 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3017 = + {0x8086, 0x3017, pci_subsys_8086_2449_8086_3017, 0}; +#undef pci_ss_info_8086_3017 +#define pci_ss_info_8086_3017 pci_ss_info_8086_2449_8086_3017 +static const pciSubsystemInfo pci_ss_info_8086_2449_8086_3018 = + {0x8086, 0x3018, pci_subsys_8086_2449_8086_3018, 0}; +#undef pci_ss_info_8086_3018 +#define pci_ss_info_8086_3018 pci_ss_info_8086_2449_8086_3018 +static const pciSubsystemInfo pci_ss_info_8086_244a_1025_1016 = + {0x1025, 0x1016, pci_subsys_8086_244a_1025_1016, 0}; +#undef pci_ss_info_1025_1016 +#define pci_ss_info_1025_1016 pci_ss_info_8086_244a_1025_1016 +static const pciSubsystemInfo pci_ss_info_8086_244a_104d_80df = + {0x104d, 0x80df, pci_subsys_8086_244a_104d_80df, 0}; +#undef pci_ss_info_104d_80df +#define pci_ss_info_104d_80df pci_ss_info_8086_244a_104d_80df +static const pciSubsystemInfo pci_ss_info_8086_244b_1014_01c6 = + {0x1014, 0x01c6, pci_subsys_8086_244b_1014_01c6, 0}; +#undef pci_ss_info_1014_01c6 +#define pci_ss_info_1014_01c6 pci_ss_info_8086_244b_1014_01c6 +static const pciSubsystemInfo pci_ss_info_8086_244b_1028_00c7 = + {0x1028, 0x00c7, pci_subsys_8086_244b_1028_00c7, 0}; +#undef pci_ss_info_1028_00c7 +#define pci_ss_info_1028_00c7 pci_ss_info_8086_244b_1028_00c7 +static const pciSubsystemInfo pci_ss_info_8086_244b_1028_010e = + {0x1028, 0x010e, pci_subsys_8086_244b_1028_010e, 0}; +#undef pci_ss_info_1028_010e +#define pci_ss_info_1028_010e pci_ss_info_8086_244b_1028_010e +static const pciSubsystemInfo pci_ss_info_8086_244b_1043_8027 = + {0x1043, 0x8027, pci_subsys_8086_244b_1043_8027, 0}; +#undef pci_ss_info_1043_8027 +#define pci_ss_info_1043_8027 pci_ss_info_8086_244b_1043_8027 +static const pciSubsystemInfo pci_ss_info_8086_244b_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_244b_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_244b_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_244b_8086_4532 = + {0x8086, 0x4532, pci_subsys_8086_244b_8086_4532, 0}; +#undef pci_ss_info_8086_4532 +#define pci_ss_info_8086_4532 pci_ss_info_8086_244b_8086_4532 +static const pciSubsystemInfo pci_ss_info_8086_244b_8086_4557 = + {0x8086, 0x4557, pci_subsys_8086_244b_8086_4557, 0}; +#undef pci_ss_info_8086_4557 +#define pci_ss_info_8086_4557 pci_ss_info_8086_244b_8086_4557 +static const pciSubsystemInfo pci_ss_info_8086_244e_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_244e_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_244e_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_2482_0e11_0030 = + {0x0e11, 0x0030, pci_subsys_8086_2482_0e11_0030, 0}; +#undef pci_ss_info_0e11_0030 +#define pci_ss_info_0e11_0030 pci_ss_info_8086_2482_0e11_0030 +static const pciSubsystemInfo pci_ss_info_8086_2482_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_2482_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_2482_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_2482_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2482_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2482_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2482_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2482_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2482_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2482_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_2482_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_2482_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_2482_8086_3424 = + {0x8086, 0x3424, pci_subsys_8086_2482_8086_3424, 0}; +#undef pci_ss_info_8086_3424 +#define pci_ss_info_8086_3424 pci_ss_info_8086_2482_8086_3424 +static const pciSubsystemInfo pci_ss_info_8086_2482_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_2482_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_2482_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_2483_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_2483_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_2483_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_2483_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2483_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2483_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2483_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2483_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2483_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2483_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_2483_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_2483_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_2484_0e11_0030 = + {0x0e11, 0x0030, pci_subsys_8086_2484_0e11_0030, 0}; +#undef pci_ss_info_0e11_0030 +#define pci_ss_info_0e11_0030 pci_ss_info_8086_2484_0e11_0030 +static const pciSubsystemInfo pci_ss_info_8086_2484_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_2484_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_2484_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_2484_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2484_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2484_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2484_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2484_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2484_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2484_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_2484_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_2484_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_2485_1013_5959 = + {0x1013, 0x5959, pci_subsys_8086_2485_1013_5959, 0}; +#undef pci_ss_info_1013_5959 +#define pci_ss_info_1013_5959 pci_ss_info_8086_2485_1013_5959 +static const pciSubsystemInfo pci_ss_info_8086_2485_1014_0222 = + {0x1014, 0x0222, pci_subsys_8086_2485_1014_0222, 0}; +#undef pci_ss_info_1014_0222 +#define pci_ss_info_1014_0222 pci_ss_info_8086_2485_1014_0222 +static const pciSubsystemInfo pci_ss_info_8086_2485_1014_0508 = + {0x1014, 0x0508, pci_subsys_8086_2485_1014_0508, 0}; +#undef pci_ss_info_1014_0508 +#define pci_ss_info_1014_0508 pci_ss_info_8086_2485_1014_0508 +static const pciSubsystemInfo pci_ss_info_8086_2485_1014_051c = + {0x1014, 0x051c, pci_subsys_8086_2485_1014_051c, 0}; +#undef pci_ss_info_1014_051c +#define pci_ss_info_1014_051c pci_ss_info_8086_2485_1014_051c +static const pciSubsystemInfo pci_ss_info_8086_2485_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2485_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2485_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2485_144d_c006 = + {0x144d, 0xc006, pci_subsys_8086_2485_144d_c006, 0}; +#undef pci_ss_info_144d_c006 +#define pci_ss_info_144d_c006 pci_ss_info_8086_2485_144d_c006 +static const pciSubsystemInfo pci_ss_info_8086_2486_1014_0223 = + {0x1014, 0x0223, pci_subsys_8086_2486_1014_0223, 0}; +#undef pci_ss_info_1014_0223 +#define pci_ss_info_1014_0223 pci_ss_info_8086_2486_1014_0223 +static const pciSubsystemInfo pci_ss_info_8086_2486_1014_0503 = + {0x1014, 0x0503, pci_subsys_8086_2486_1014_0503, 0}; +#undef pci_ss_info_1014_0503 +#define pci_ss_info_1014_0503 pci_ss_info_8086_2486_1014_0503 +static const pciSubsystemInfo pci_ss_info_8086_2486_1014_051a = + {0x1014, 0x051a, pci_subsys_8086_2486_1014_051a, 0}; +#undef pci_ss_info_1014_051a +#define pci_ss_info_1014_051a pci_ss_info_8086_2486_1014_051a +static const pciSubsystemInfo pci_ss_info_8086_2486_101f_1025 = + {0x101f, 0x1025, pci_subsys_8086_2486_101f_1025, 0}; +#undef pci_ss_info_101f_1025 +#define pci_ss_info_101f_1025 pci_ss_info_8086_2486_101f_1025 +static const pciSubsystemInfo pci_ss_info_8086_2486_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2486_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2486_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2486_134d_4c21 = + {0x134d, 0x4c21, pci_subsys_8086_2486_134d_4c21, 0}; +#undef pci_ss_info_134d_4c21 +#define pci_ss_info_134d_4c21 pci_ss_info_8086_2486_134d_4c21 +static const pciSubsystemInfo pci_ss_info_8086_2486_144d_2115 = + {0x144d, 0x2115, pci_subsys_8086_2486_144d_2115, 0}; +#undef pci_ss_info_144d_2115 +#define pci_ss_info_144d_2115 pci_ss_info_8086_2486_144d_2115 +static const pciSubsystemInfo pci_ss_info_8086_2486_14f1_5421 = + {0x14f1, 0x5421, pci_subsys_8086_2486_14f1_5421, 0}; +#undef pci_ss_info_14f1_5421 +#define pci_ss_info_14f1_5421 pci_ss_info_8086_2486_14f1_5421 +static const pciSubsystemInfo pci_ss_info_8086_2487_0e11_0030 = + {0x0e11, 0x0030, pci_subsys_8086_2487_0e11_0030, 0}; +#undef pci_ss_info_0e11_0030 +#define pci_ss_info_0e11_0030 pci_ss_info_8086_2487_0e11_0030 +static const pciSubsystemInfo pci_ss_info_8086_2487_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_2487_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_2487_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_2487_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_2487_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_2487_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_2487_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2487_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2487_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2487_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_2487_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_2487_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_248a_0e11_0030 = + {0x0e11, 0x0030, pci_subsys_8086_248a_0e11_0030, 0}; +#undef pci_ss_info_0e11_0030 +#define pci_ss_info_0e11_0030 pci_ss_info_8086_248a_0e11_0030 +static const pciSubsystemInfo pci_ss_info_8086_248a_1014_0220 = + {0x1014, 0x0220, pci_subsys_8086_248a_1014_0220, 0}; +#undef pci_ss_info_1014_0220 +#define pci_ss_info_1014_0220 pci_ss_info_8086_248a_1014_0220 +static const pciSubsystemInfo pci_ss_info_8086_248a_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_248a_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_248a_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_248a_8086_1958 = + {0x8086, 0x1958, pci_subsys_8086_248a_8086_1958, 0}; +#undef pci_ss_info_8086_1958 +#define pci_ss_info_8086_1958 pci_ss_info_8086_248a_8086_1958 +static const pciSubsystemInfo pci_ss_info_8086_248a_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_248a_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_248a_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_248b_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_248b_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_248b_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_24c0_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c0_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c0_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c0_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c0_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c0_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c2_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c2_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1014_052d = + {0x1014, 0x052d, pci_subsys_8086_24c2_1014_052d, 0}; +#undef pci_ss_info_1014_052d +#define pci_ss_info_1014_052d pci_ss_info_8086_24c2_1014_052d +static const pciSubsystemInfo pci_ss_info_8086_24c2_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c2_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c2_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c2_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24c2_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24c2_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24c2_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24c2_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24c2_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24c2_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24c2_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c2_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c2_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c2_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c2_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c2_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c2_103c_08b0 = + {0x103c, 0x08b0, pci_subsys_8086_24c2_103c_08b0, 0}; +#undef pci_ss_info_103c_08b0 +#define pci_ss_info_103c_08b0 pci_ss_info_8086_24c2_103c_08b0 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c2_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c2_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c2_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c2_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1509_2990 = + {0x1509, 0x2990, pci_subsys_8086_24c2_1509_2990, 0}; +#undef pci_ss_info_1509_2990 +#define pci_ss_info_1509_2990 pci_ss_info_8086_24c2_1509_2990 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1734_1004 = + {0x1734, 0x1004, pci_subsys_8086_24c2_1734_1004, 0}; +#undef pci_ss_info_1734_1004 +#define pci_ss_info_1734_1004 pci_ss_info_8086_24c2_1734_1004 +static const pciSubsystemInfo pci_ss_info_8086_24c2_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24c2_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24c2_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24c2_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24c2_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24c2_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24c2_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_24c2_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_24c2_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c3_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c3_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1014_052d = + {0x1014, 0x052d, pci_subsys_8086_24c3_1014_052d, 0}; +#undef pci_ss_info_1014_052d +#define pci_ss_info_1014_052d pci_ss_info_8086_24c3_1014_052d +static const pciSubsystemInfo pci_ss_info_8086_24c3_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c3_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c3_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c3_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24c3_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24c3_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24c3_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c3_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c3_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c3_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c3_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c3_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c3_103c_08b0 = + {0x103c, 0x08b0, pci_subsys_8086_24c3_103c_08b0, 0}; +#undef pci_ss_info_103c_08b0 +#define pci_ss_info_103c_08b0 pci_ss_info_8086_24c3_103c_08b0 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c3_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c3_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1458_24c2 = + {0x1458, 0x24c2, pci_subsys_8086_24c3_1458_24c2, 0}; +#undef pci_ss_info_1458_24c2 +#define pci_ss_info_1458_24c2 pci_ss_info_8086_24c3_1458_24c2 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c3_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c3_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1734_1004 = + {0x1734, 0x1004, pci_subsys_8086_24c3_1734_1004, 0}; +#undef pci_ss_info_1734_1004 +#define pci_ss_info_1734_1004 pci_ss_info_8086_24c3_1734_1004 +static const pciSubsystemInfo pci_ss_info_8086_24c3_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24c3_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24c3_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24c3_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24c3_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24c3_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c4_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c4_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1014_052d = + {0x1014, 0x052d, pci_subsys_8086_24c4_1014_052d, 0}; +#undef pci_ss_info_1014_052d +#define pci_ss_info_1014_052d pci_ss_info_8086_24c4_1014_052d +static const pciSubsystemInfo pci_ss_info_8086_24c4_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c4_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c4_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c4_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24c4_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24c4_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24c4_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24c4_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24c4_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24c4_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24c4_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c4_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c4_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c4_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c4_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c4_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c4_103c_08b0 = + {0x103c, 0x08b0, pci_subsys_8086_24c4_103c_08b0, 0}; +#undef pci_ss_info_103c_08b0 +#define pci_ss_info_103c_08b0 pci_ss_info_8086_24c4_103c_08b0 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c4_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c4_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c4_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c4_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1509_2990 = + {0x1509, 0x2990, pci_subsys_8086_24c4_1509_2990, 0}; +#undef pci_ss_info_1509_2990 +#define pci_ss_info_1509_2990 pci_ss_info_8086_24c4_1509_2990 +static const pciSubsystemInfo pci_ss_info_8086_24c4_1734_1004 = + {0x1734, 0x1004, pci_subsys_8086_24c4_1734_1004, 0}; +#undef pci_ss_info_1734_1004 +#define pci_ss_info_1734_1004 pci_ss_info_8086_24c4_1734_1004 +static const pciSubsystemInfo pci_ss_info_8086_24c4_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24c4_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24c4_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24c4_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_24c4_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_24c4_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_24c5_0e11_00b8 = + {0x0e11, 0x00b8, pci_subsys_8086_24c5_0e11_00b8, 0}; +#undef pci_ss_info_0e11_00b8 +#define pci_ss_info_0e11_00b8 pci_ss_info_8086_24c5_0e11_00b8 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c5_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c5_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1014_055f = + {0x1014, 0x055f, pci_subsys_8086_24c5_1014_055f, 0}; +#undef pci_ss_info_1014_055f +#define pci_ss_info_1014_055f pci_ss_info_8086_24c5_1014_055f +static const pciSubsystemInfo pci_ss_info_8086_24c5_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c5_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c5_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c5_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_24c5_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_24c5_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24c5_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24c5_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24c5_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24c5_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24c5_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c5_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c5_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c5_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c5_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c5_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c5_103c_08b0 = + {0x103c, 0x08b0, pci_subsys_8086_24c5_103c_08b0, 0}; +#undef pci_ss_info_103c_08b0 +#define pci_ss_info_103c_08b0 pci_ss_info_8086_24c5_103c_08b0 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c5_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c5_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1458_a002 = + {0x1458, 0xa002, pci_subsys_8086_24c5_1458_a002, 0}; +#undef pci_ss_info_1458_a002 +#define pci_ss_info_1458_a002 pci_ss_info_8086_24c5_1458_a002 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c5_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c5_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1734_1005 = + {0x1734, 0x1005, pci_subsys_8086_24c5_1734_1005, 0}; +#undef pci_ss_info_1734_1005 +#define pci_ss_info_1734_1005 pci_ss_info_8086_24c5_1734_1005 +static const pciSubsystemInfo pci_ss_info_8086_24c5_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24c5_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24c5_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24c6_1014_0559 = + {0x1014, 0x0559, pci_subsys_8086_24c6_1014_0559, 0}; +#undef pci_ss_info_1014_0559 +#define pci_ss_info_1014_0559 pci_ss_info_8086_24c6_1014_0559 +static const pciSubsystemInfo pci_ss_info_8086_24c6_1025_003c = + {0x1025, 0x003c, pci_subsys_8086_24c6_1025_003c, 0}; +#undef pci_ss_info_1025_003c +#define pci_ss_info_1025_003c pci_ss_info_8086_24c6_1025_003c +static const pciSubsystemInfo pci_ss_info_8086_24c6_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c6_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c6_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c6_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24c6_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24c6_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24c6_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c6_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c6_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c6_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c6_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c6_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c6_103c_08b0 = + {0x103c, 0x08b0, pci_subsys_8086_24c6_103c_08b0, 0}; +#undef pci_ss_info_103c_08b0 +#define pci_ss_info_103c_08b0 pci_ss_info_8086_24c6_103c_08b0 +static const pciSubsystemInfo pci_ss_info_8086_24c6_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c6_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c6_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24c7_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24c7_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1014_052d = + {0x1014, 0x052d, pci_subsys_8086_24c7_1014_052d, 0}; +#undef pci_ss_info_1014_052d +#define pci_ss_info_1014_052d pci_ss_info_8086_24c7_1014_052d +static const pciSubsystemInfo pci_ss_info_8086_24c7_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24c7_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24c7_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24c7_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24c7_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24c7_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24c7_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24c7_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24c7_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24c7_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24c7_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24c7_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24c7_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24c7_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24c7_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24c7_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24c7_103c_08b0 = + {0x103c, 0x08b0, pci_subsys_8086_24c7_103c_08b0, 0}; +#undef pci_ss_info_103c_08b0 +#define pci_ss_info_103c_08b0 pci_ss_info_8086_24c7_103c_08b0 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24c7_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24c7_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24c7_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24c7_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1509_2990 = + {0x1509, 0x2990, pci_subsys_8086_24c7_1509_2990, 0}; +#undef pci_ss_info_1509_2990 +#define pci_ss_info_1509_2990 pci_ss_info_8086_24c7_1509_2990 +static const pciSubsystemInfo pci_ss_info_8086_24c7_1734_1004 = + {0x1734, 0x1004, pci_subsys_8086_24c7_1734_1004, 0}; +#undef pci_ss_info_1734_1004 +#define pci_ss_info_1734_1004 pci_ss_info_8086_24c7_1734_1004 +static const pciSubsystemInfo pci_ss_info_8086_24c7_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24c7_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24c7_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24c7_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_24c7_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_24c7_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_24ca_1014_052d = + {0x1014, 0x052d, pci_subsys_8086_24ca_1014_052d, 0}; +#undef pci_ss_info_1014_052d +#define pci_ss_info_1014_052d pci_ss_info_8086_24ca_1014_052d +static const pciSubsystemInfo pci_ss_info_8086_24ca_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24ca_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24ca_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24ca_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24ca_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24ca_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24ca_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24ca_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24ca_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24ca_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24ca_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24ca_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24ca_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24ca_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24ca_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24ca_103c_08b0 = + {0x103c, 0x08b0, pci_subsys_8086_24ca_103c_08b0, 0}; +#undef pci_ss_info_103c_08b0 +#define pci_ss_info_103c_08b0 pci_ss_info_8086_24ca_103c_08b0 +static const pciSubsystemInfo pci_ss_info_8086_24ca_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24ca_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24ca_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24ca_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24ca_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24ca_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24ca_8086_4541 = + {0x8086, 0x4541, pci_subsys_8086_24ca_8086_4541, 0}; +#undef pci_ss_info_8086_4541 +#define pci_ss_info_8086_4541 pci_ss_info_8086_24ca_8086_4541 +static const pciSubsystemInfo pci_ss_info_8086_24cb_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24cb_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24cb_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24cb_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24cb_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24cb_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24cb_1458_24c2 = + {0x1458, 0x24c2, pci_subsys_8086_24cb_1458_24c2, 0}; +#undef pci_ss_info_1458_24c2 +#define pci_ss_info_1458_24c2 pci_ss_info_8086_24cb_1458_24c2 +static const pciSubsystemInfo pci_ss_info_8086_24cb_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_24cb_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_24cb_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_24cb_1734_1004 = + {0x1734, 0x1004, pci_subsys_8086_24cb_1734_1004, 0}; +#undef pci_ss_info_1734_1004 +#define pci_ss_info_1734_1004 pci_ss_info_8086_24cb_1734_1004 +static const pciSubsystemInfo pci_ss_info_8086_24cb_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24cb_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24cb_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24cc_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24cc_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24cc_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_24cd_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_24cd_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1014_052e = + {0x1014, 0x052e, pci_subsys_8086_24cd_1014_052e, 0}; +#undef pci_ss_info_1014_052e +#define pci_ss_info_1014_052e pci_ss_info_8086_24cd_1014_052e +static const pciSubsystemInfo pci_ss_info_8086_24cd_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_24cd_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_24cd_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_24cd_1028_011d = + {0x1028, 0x011d, pci_subsys_8086_24cd_1028_011d, 0}; +#undef pci_ss_info_1028_011d +#define pci_ss_info_1028_011d pci_ss_info_8086_24cd_1028_011d +static const pciSubsystemInfo pci_ss_info_8086_24cd_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_24cd_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_24cd_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_24cd_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_24cd_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_24cd_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_24cd_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_24cd_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_24cd_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_24cd_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_24cd_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_24cd_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_24cd_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_24cd_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_24cd_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_24cd_103c_08b0 = + {0x103c, 0x08b0, pci_subsys_8086_24cd_103c_08b0, 0}; +#undef pci_ss_info_103c_08b0 +#define pci_ss_info_103c_08b0 pci_ss_info_8086_24cd_103c_08b0 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1071_8160 = + {0x1071, 0x8160, pci_subsys_8086_24cd_1071_8160, 0}; +#undef pci_ss_info_1071_8160 +#define pci_ss_info_1071_8160 pci_ss_info_8086_24cd_1071_8160 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1179_ff00 = + {0x1179, 0xff00, pci_subsys_8086_24cd_1179_ff00, 0}; +#undef pci_ss_info_1179_ff00 +#define pci_ss_info_1179_ff00 pci_ss_info_8086_24cd_1179_ff00 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1462_3981 = + {0x1462, 0x3981, pci_subsys_8086_24cd_1462_3981, 0}; +#undef pci_ss_info_1462_3981 +#define pci_ss_info_1462_3981 pci_ss_info_8086_24cd_1462_3981 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1509_1968 = + {0x1509, 0x1968, pci_subsys_8086_24cd_1509_1968, 0}; +#undef pci_ss_info_1509_1968 +#define pci_ss_info_1509_1968 pci_ss_info_8086_24cd_1509_1968 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1734_1004 = + {0x1734, 0x1004, pci_subsys_8086_24cd_1734_1004, 0}; +#undef pci_ss_info_1734_1004 +#define pci_ss_info_1734_1004 pci_ss_info_8086_24cd_1734_1004 +static const pciSubsystemInfo pci_ss_info_8086_24cd_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_24cd_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_24cd_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_24cd_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_24cd_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_24cd_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_24d1_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d1_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d1_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d1_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_24d1_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_24d1_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_24d1_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24d1_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24d1_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24d1_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24d1_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24d1_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24d1_1458_24d1 = + {0x1458, 0x24d1, pci_subsys_8086_24d1_1458_24d1, 0}; +#undef pci_ss_info_1458_24d1 +#define pci_ss_info_1458_24d1 pci_ss_info_8086_24d1_1458_24d1 +static const pciSubsystemInfo pci_ss_info_8086_24d1_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d1_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d1_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d1_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24d1_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24d1_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24d1_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24d1_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24d1_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24d1_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24d1_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24d1_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24d1_8086_4c43 = + {0x8086, 0x4c43, pci_subsys_8086_24d1_8086_4c43, 0}; +#undef pci_ss_info_8086_4c43 +#define pci_ss_info_8086_4c43 pci_ss_info_8086_24d1_8086_4c43 +static const pciSubsystemInfo pci_ss_info_8086_24d1_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24d1_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24d1_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24d2_1014_02ed = + {0x1014, 0x02ed, pci_subsys_8086_24d2_1014_02ed, 0}; +#undef pci_ss_info_1014_02ed +#define pci_ss_info_1014_02ed pci_ss_info_8086_24d2_1014_02ed +static const pciSubsystemInfo pci_ss_info_8086_24d2_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d2_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d2_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d2_1028_0183 = + {0x1028, 0x0183, pci_subsys_8086_24d2_1028_0183, 0}; +#undef pci_ss_info_1028_0183 +#define pci_ss_info_1028_0183 pci_ss_info_8086_24d2_1028_0183 +static const pciSubsystemInfo pci_ss_info_8086_24d2_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_24d2_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_24d2_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_24d2_103c_006a = + {0x103c, 0x006a, pci_subsys_8086_24d2_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_8086_24d2_103c_006a +static const pciSubsystemInfo pci_ss_info_8086_24d2_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24d2_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24d2_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24d2_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24d2_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24d2_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24d2_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24d2_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24d2_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24d2_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d2_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d2_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d2_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24d2_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24d2_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24d2_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24d2_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24d2_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24d2_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24d2_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24d2_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24d2_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24d2_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24d2_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24d2_8086_4c43 = + {0x8086, 0x4c43, pci_subsys_8086_24d2_8086_4c43, 0}; +#undef pci_ss_info_8086_4c43 +#define pci_ss_info_8086_4c43 pci_ss_info_8086_24d2_8086_4c43 +static const pciSubsystemInfo pci_ss_info_8086_24d2_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24d2_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24d2_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24d3_1014_02ed = + {0x1014, 0x02ed, pci_subsys_8086_24d3_1014_02ed, 0}; +#undef pci_ss_info_1014_02ed +#define pci_ss_info_1014_02ed pci_ss_info_8086_24d3_1014_02ed +static const pciSubsystemInfo pci_ss_info_8086_24d3_1028_0156 = + {0x1028, 0x0156, pci_subsys_8086_24d3_1028_0156, 0}; +#undef pci_ss_info_1028_0156 +#define pci_ss_info_1028_0156 pci_ss_info_8086_24d3_1028_0156 +static const pciSubsystemInfo pci_ss_info_8086_24d3_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d3_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d3_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d3_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24d3_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24d3_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24d3_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24d3_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24d3_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24d3_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d3_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d3_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d3_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24d3_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24d3_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24d3_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24d3_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24d3_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24d3_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24d3_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24d3_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24d3_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24d3_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24d3_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24d3_8086_4c43 = + {0x8086, 0x4c43, pci_subsys_8086_24d3_8086_4c43, 0}; +#undef pci_ss_info_8086_4c43 +#define pci_ss_info_8086_4c43 pci_ss_info_8086_24d3_8086_4c43 +static const pciSubsystemInfo pci_ss_info_8086_24d3_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24d3_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24d3_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24d4_1014_02ed = + {0x1014, 0x02ed, pci_subsys_8086_24d4_1014_02ed, 0}; +#undef pci_ss_info_1014_02ed +#define pci_ss_info_1014_02ed pci_ss_info_8086_24d4_1014_02ed +static const pciSubsystemInfo pci_ss_info_8086_24d4_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d4_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d4_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d4_1028_0183 = + {0x1028, 0x0183, pci_subsys_8086_24d4_1028_0183, 0}; +#undef pci_ss_info_1028_0183 +#define pci_ss_info_1028_0183 pci_ss_info_8086_24d4_1028_0183 +static const pciSubsystemInfo pci_ss_info_8086_24d4_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_24d4_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_24d4_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_24d4_103c_006a = + {0x103c, 0x006a, pci_subsys_8086_24d4_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_8086_24d4_103c_006a +static const pciSubsystemInfo pci_ss_info_8086_24d4_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24d4_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24d4_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24d4_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24d4_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24d4_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24d4_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24d4_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24d4_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24d4_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d4_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d4_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d4_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24d4_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24d4_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24d4_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24d4_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24d4_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24d4_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24d4_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24d4_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24d4_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24d4_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24d4_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24d4_8086_4c43 = + {0x8086, 0x4c43, pci_subsys_8086_24d4_8086_4c43, 0}; +#undef pci_ss_info_8086_4c43 +#define pci_ss_info_8086_4c43 pci_ss_info_8086_24d4_8086_4c43 +static const pciSubsystemInfo pci_ss_info_8086_24d4_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24d4_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24d4_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24d5_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d5_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d5_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d5_103c_006a = + {0x103c, 0x006a, pci_subsys_8086_24d5_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_8086_24d5_103c_006a +static const pciSubsystemInfo pci_ss_info_8086_24d5_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24d5_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24d5_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24d5_1043_80f3 = + {0x1043, 0x80f3, pci_subsys_8086_24d5_1043_80f3, 0}; +#undef pci_ss_info_1043_80f3 +#define pci_ss_info_1043_80f3 pci_ss_info_8086_24d5_1043_80f3 +static const pciSubsystemInfo pci_ss_info_8086_24d5_1043_810f = + {0x1043, 0x810f, pci_subsys_8086_24d5_1043_810f, 0}; +#undef pci_ss_info_1043_810f +#define pci_ss_info_1043_810f pci_ss_info_8086_24d5_1043_810f +static const pciSubsystemInfo pci_ss_info_8086_24d5_1458_a002 = + {0x1458, 0xa002, pci_subsys_8086_24d5_1458_a002, 0}; +#undef pci_ss_info_1458_a002 +#define pci_ss_info_1458_a002 pci_ss_info_8086_24d5_1458_a002 +static const pciSubsystemInfo pci_ss_info_8086_24d5_1462_0080 = + {0x1462, 0x0080, pci_subsys_8086_24d5_1462_0080, 0}; +#undef pci_ss_info_1462_0080 +#define pci_ss_info_1462_0080 pci_ss_info_8086_24d5_1462_0080 +static const pciSubsystemInfo pci_ss_info_8086_24d5_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d5_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d5_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d5_8086_a000 = + {0x8086, 0xa000, pci_subsys_8086_24d5_8086_a000, 0}; +#undef pci_ss_info_8086_a000 +#define pci_ss_info_8086_a000 pci_ss_info_8086_24d5_8086_a000 +static const pciSubsystemInfo pci_ss_info_8086_24d5_8086_e000 = + {0x8086, 0xe000, pci_subsys_8086_24d5_8086_e000, 0}; +#undef pci_ss_info_8086_e000 +#define pci_ss_info_8086_e000 pci_ss_info_8086_24d5_8086_e000 +static const pciSubsystemInfo pci_ss_info_8086_24d5_8086_e001 = + {0x8086, 0xe001, pci_subsys_8086_24d5_8086_e001, 0}; +#undef pci_ss_info_8086_e001 +#define pci_ss_info_8086_e001 pci_ss_info_8086_24d5_8086_e001 +static const pciSubsystemInfo pci_ss_info_8086_24d5_8086_e002 = + {0x8086, 0xe002, pci_subsys_8086_24d5_8086_e002, 0}; +#undef pci_ss_info_8086_e002 +#define pci_ss_info_8086_e002 pci_ss_info_8086_24d5_8086_e002 +static const pciSubsystemInfo pci_ss_info_8086_24d6_103c_006a = + {0x103c, 0x006a, pci_subsys_8086_24d6_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_8086_24d6_103c_006a +static const pciSubsystemInfo pci_ss_info_8086_24d7_1014_02ed = + {0x1014, 0x02ed, pci_subsys_8086_24d7_1014_02ed, 0}; +#undef pci_ss_info_1014_02ed +#define pci_ss_info_1014_02ed pci_ss_info_8086_24d7_1014_02ed +static const pciSubsystemInfo pci_ss_info_8086_24d7_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24d7_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24d7_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24d7_1028_0183 = + {0x1028, 0x0183, pci_subsys_8086_24d7_1028_0183, 0}; +#undef pci_ss_info_1028_0183 +#define pci_ss_info_1028_0183 pci_ss_info_8086_24d7_1028_0183 +static const pciSubsystemInfo pci_ss_info_8086_24d7_103c_006a = + {0x103c, 0x006a, pci_subsys_8086_24d7_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_8086_24d7_103c_006a +static const pciSubsystemInfo pci_ss_info_8086_24d7_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24d7_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24d7_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24d7_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24d7_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24d7_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24d7_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24d7_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24d7_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24d7_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24d7_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24d7_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24d7_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24d7_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24d7_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24d7_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24d7_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24d7_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24d7_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24d7_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24d7_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24d7_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24d7_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24d7_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24d7_8086_4c43 = + {0x8086, 0x4c43, pci_subsys_8086_24d7_8086_4c43, 0}; +#undef pci_ss_info_8086_4c43 +#define pci_ss_info_8086_4c43 pci_ss_info_8086_24d7_8086_4c43 +static const pciSubsystemInfo pci_ss_info_8086_24d7_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24d7_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24d7_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24db_1014_02ed = + {0x1014, 0x02ed, pci_subsys_8086_24db_1014_02ed, 0}; +#undef pci_ss_info_1014_02ed +#define pci_ss_info_1014_02ed pci_ss_info_8086_24db_1014_02ed +static const pciSubsystemInfo pci_ss_info_8086_24db_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24db_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24db_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24db_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_24db_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_24db_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_24db_103c_006a = + {0x103c, 0x006a, pci_subsys_8086_24db_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_8086_24db_103c_006a +static const pciSubsystemInfo pci_ss_info_8086_24db_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24db_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24db_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24db_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24db_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24db_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24db_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24db_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24db_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24db_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24db_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24db_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24db_1462_7580 = + {0x1462, 0x7580, pci_subsys_8086_24db_1462_7580, 0}; +#undef pci_ss_info_1462_7580 +#define pci_ss_info_1462_7580 pci_ss_info_8086_24db_1462_7580 +static const pciSubsystemInfo pci_ss_info_8086_24db_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24db_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24db_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24db_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24db_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24db_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24db_8086_24db = + {0x8086, 0x24db, pci_subsys_8086_24db_8086_24db, 0}; +#undef pci_ss_info_8086_24db +#define pci_ss_info_8086_24db pci_ss_info_8086_24db_8086_24db +static const pciSubsystemInfo pci_ss_info_8086_24db_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24db_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24db_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24db_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24db_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24db_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24db_8086_4c43 = + {0x8086, 0x4c43, pci_subsys_8086_24db_8086_4c43, 0}; +#undef pci_ss_info_8086_4c43 +#define pci_ss_info_8086_4c43 pci_ss_info_8086_24db_8086_4c43 +static const pciSubsystemInfo pci_ss_info_8086_24db_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24db_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24db_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24dd_1014_02ed = + {0x1014, 0x02ed, pci_subsys_8086_24dd_1014_02ed, 0}; +#undef pci_ss_info_1014_02ed +#define pci_ss_info_1014_02ed pci_ss_info_8086_24dd_1014_02ed +static const pciSubsystemInfo pci_ss_info_8086_24dd_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24dd_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24dd_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24dd_1028_0183 = + {0x1028, 0x0183, pci_subsys_8086_24dd_1028_0183, 0}; +#undef pci_ss_info_1028_0183 +#define pci_ss_info_1028_0183 pci_ss_info_8086_24dd_1028_0183 +static const pciSubsystemInfo pci_ss_info_8086_24dd_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_24dd_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_24dd_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_24dd_103c_006a = + {0x103c, 0x006a, pci_subsys_8086_24dd_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_8086_24dd_103c_006a +static const pciSubsystemInfo pci_ss_info_8086_24dd_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_24dd_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_24dd_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_24dd_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24dd_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24dd_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24dd_1458_5006 = + {0x1458, 0x5006, pci_subsys_8086_24dd_1458_5006, 0}; +#undef pci_ss_info_1458_5006 +#define pci_ss_info_1458_5006 pci_ss_info_8086_24dd_1458_5006 +static const pciSubsystemInfo pci_ss_info_8086_24dd_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24dd_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24dd_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24dd_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24dd_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24dd_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24dd_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24dd_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24dd_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24dd_8086_4c43 = + {0x8086, 0x4c43, pci_subsys_8086_24dd_8086_4c43, 0}; +#undef pci_ss_info_8086_4c43 +#define pci_ss_info_8086_4c43 pci_ss_info_8086_24dd_8086_4c43 +static const pciSubsystemInfo pci_ss_info_8086_24dd_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24dd_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24dd_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_24de_1014_02ed = + {0x1014, 0x02ed, pci_subsys_8086_24de_1014_02ed, 0}; +#undef pci_ss_info_1014_02ed +#define pci_ss_info_1014_02ed pci_ss_info_8086_24de_1014_02ed +static const pciSubsystemInfo pci_ss_info_8086_24de_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_24de_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_24de_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_24de_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_24de_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_24de_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_24de_1458_24d2 = + {0x1458, 0x24d2, pci_subsys_8086_24de_1458_24d2, 0}; +#undef pci_ss_info_1458_24d2 +#define pci_ss_info_1458_24d2 pci_ss_info_8086_24de_1458_24d2 +static const pciSubsystemInfo pci_ss_info_8086_24de_1462_7280 = + {0x1462, 0x7280, pci_subsys_8086_24de_1462_7280, 0}; +#undef pci_ss_info_1462_7280 +#define pci_ss_info_1462_7280 pci_ss_info_8086_24de_1462_7280 +static const pciSubsystemInfo pci_ss_info_8086_24de_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_24de_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_24de_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_24de_1734_101c = + {0x1734, 0x101c, pci_subsys_8086_24de_1734_101c, 0}; +#undef pci_ss_info_1734_101c +#define pci_ss_info_1734_101c pci_ss_info_8086_24de_1734_101c +static const pciSubsystemInfo pci_ss_info_8086_24de_8086_3427 = + {0x8086, 0x3427, pci_subsys_8086_24de_8086_3427, 0}; +#undef pci_ss_info_8086_3427 +#define pci_ss_info_8086_3427 pci_ss_info_8086_24de_8086_3427 +static const pciSubsystemInfo pci_ss_info_8086_24de_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_24de_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_24de_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_24de_8086_4c43 = + {0x8086, 0x4c43, pci_subsys_8086_24de_8086_4c43, 0}; +#undef pci_ss_info_8086_4c43 +#define pci_ss_info_8086_4c43 pci_ss_info_8086_24de_8086_4c43 +static const pciSubsystemInfo pci_ss_info_8086_24de_8086_524c = + {0x8086, 0x524c, pci_subsys_8086_24de_8086_524c, 0}; +#undef pci_ss_info_8086_524c +#define pci_ss_info_8086_524c pci_ss_info_8086_24de_8086_524c +static const pciSubsystemInfo pci_ss_info_8086_2500_1028_0095 = + {0x1028, 0x0095, pci_subsys_8086_2500_1028_0095, 0}; +#undef pci_ss_info_1028_0095 +#define pci_ss_info_1028_0095 pci_ss_info_8086_2500_1028_0095 +static const pciSubsystemInfo pci_ss_info_8086_2500_1043_801c = + {0x1043, 0x801c, pci_subsys_8086_2500_1043_801c, 0}; +#undef pci_ss_info_1043_801c +#define pci_ss_info_1043_801c pci_ss_info_8086_2500_1043_801c +static const pciSubsystemInfo pci_ss_info_8086_2501_1043_801c = + {0x1043, 0x801c, pci_subsys_8086_2501_1043_801c, 0}; +#undef pci_ss_info_1043_801c +#define pci_ss_info_1043_801c pci_ss_info_8086_2501_1043_801c +static const pciSubsystemInfo pci_ss_info_8086_2530_1028_00c7 = + {0x1028, 0x00c7, pci_subsys_8086_2530_1028_00c7, 0}; +#undef pci_ss_info_1028_00c7 +#define pci_ss_info_1028_00c7 pci_ss_info_8086_2530_1028_00c7 +static const pciSubsystemInfo pci_ss_info_8086_2530_147b_0507 = + {0x147b, 0x0507, pci_subsys_8086_2530_147b_0507, 0}; +#undef pci_ss_info_147b_0507 +#define pci_ss_info_147b_0507 pci_ss_info_8086_2530_147b_0507 +static const pciSubsystemInfo pci_ss_info_8086_2540_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2540_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2540_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2541_15d9_3480 = + {0x15d9, 0x3480, pci_subsys_8086_2541_15d9_3480, 0}; +#undef pci_ss_info_15d9_3480 +#define pci_ss_info_15d9_3480 pci_ss_info_8086_2541_15d9_3480 +static const pciSubsystemInfo pci_ss_info_8086_2541_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_2541_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_2541_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_2541_8086_3424 = + {0x8086, 0x3424, pci_subsys_8086_2541_8086_3424, 0}; +#undef pci_ss_info_8086_3424 +#define pci_ss_info_8086_3424 pci_ss_info_8086_2541_8086_3424 +static const pciSubsystemInfo pci_ss_info_8086_2544_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_2544_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_2544_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_254c_4c53_1090 = + {0x4c53, 0x1090, pci_subsys_8086_254c_4c53_1090, 0}; +#undef pci_ss_info_4c53_1090 +#define pci_ss_info_4c53_1090 pci_ss_info_8086_254c_4c53_1090 +static const pciSubsystemInfo pci_ss_info_8086_254c_8086_3424 = + {0x8086, 0x3424, pci_subsys_8086_254c_8086_3424, 0}; +#undef pci_ss_info_8086_3424 +#define pci_ss_info_8086_3424 pci_ss_info_8086_254c_8086_3424 +static const pciSubsystemInfo pci_ss_info_8086_2560_1028_0126 = + {0x1028, 0x0126, pci_subsys_8086_2560_1028_0126, 0}; +#undef pci_ss_info_1028_0126 +#define pci_ss_info_1028_0126 pci_ss_info_8086_2560_1028_0126 +static const pciSubsystemInfo pci_ss_info_8086_2560_1458_2560 = + {0x1458, 0x2560, pci_subsys_8086_2560_1458_2560, 0}; +#undef pci_ss_info_1458_2560 +#define pci_ss_info_1458_2560 pci_ss_info_8086_2560_1458_2560 +static const pciSubsystemInfo pci_ss_info_8086_2560_1462_5800 = + {0x1462, 0x5800, pci_subsys_8086_2560_1462_5800, 0}; +#undef pci_ss_info_1462_5800 +#define pci_ss_info_1462_5800 pci_ss_info_8086_2560_1462_5800 +static const pciSubsystemInfo pci_ss_info_8086_2562_0e11_00b9 = + {0x0e11, 0x00b9, pci_subsys_8086_2562_0e11_00b9, 0}; +#undef pci_ss_info_0e11_00b9 +#define pci_ss_info_0e11_00b9 pci_ss_info_8086_2562_0e11_00b9 +static const pciSubsystemInfo pci_ss_info_8086_2562_1014_0267 = + {0x1014, 0x0267, pci_subsys_8086_2562_1014_0267, 0}; +#undef pci_ss_info_1014_0267 +#define pci_ss_info_1014_0267 pci_ss_info_8086_2562_1014_0267 +static const pciSubsystemInfo pci_ss_info_8086_2562_1734_1004 = + {0x1734, 0x1004, pci_subsys_8086_2562_1734_1004, 0}; +#undef pci_ss_info_1734_1004 +#define pci_ss_info_1734_1004 pci_ss_info_8086_2562_1734_1004 +static const pciSubsystemInfo pci_ss_info_8086_2570_103c_006a = + {0x103c, 0x006a, pci_subsys_8086_2570_103c_006a, 0}; +#undef pci_ss_info_103c_006a +#define pci_ss_info_103c_006a pci_ss_info_8086_2570_103c_006a +static const pciSubsystemInfo pci_ss_info_8086_2570_1043_80f2 = + {0x1043, 0x80f2, pci_subsys_8086_2570_1043_80f2, 0}; +#undef pci_ss_info_1043_80f2 +#define pci_ss_info_1043_80f2 pci_ss_info_8086_2570_1043_80f2 +static const pciSubsystemInfo pci_ss_info_8086_2570_1458_2570 = + {0x1458, 0x2570, pci_subsys_8086_2570_1458_2570, 0}; +#undef pci_ss_info_1458_2570 +#define pci_ss_info_1458_2570 pci_ss_info_8086_2570_1458_2570 +static const pciSubsystemInfo pci_ss_info_8086_2572_1028_019d = + {0x1028, 0x019d, pci_subsys_8086_2572_1028_019d, 0}; +#undef pci_ss_info_1028_019d +#define pci_ss_info_1028_019d pci_ss_info_8086_2572_1028_019d +static const pciSubsystemInfo pci_ss_info_8086_2572_103c_12bc = + {0x103c, 0x12bc, pci_subsys_8086_2572_103c_12bc, 0}; +#undef pci_ss_info_103c_12bc +#define pci_ss_info_103c_12bc pci_ss_info_8086_2572_103c_12bc +static const pciSubsystemInfo pci_ss_info_8086_2572_1043_80a5 = + {0x1043, 0x80a5, pci_subsys_8086_2572_1043_80a5, 0}; +#undef pci_ss_info_1043_80a5 +#define pci_ss_info_1043_80a5 pci_ss_info_8086_2572_1043_80a5 +static const pciSubsystemInfo pci_ss_info_8086_2572_8086_4246 = + {0x8086, 0x4246, pci_subsys_8086_2572_8086_4246, 0}; +#undef pci_ss_info_8086_4246 +#define pci_ss_info_8086_4246 pci_ss_info_8086_2572_8086_4246 +static const pciSubsystemInfo pci_ss_info_8086_2572_8086_4c43 = + {0x8086, 0x4c43, pci_subsys_8086_2572_8086_4c43, 0}; +#undef pci_ss_info_8086_4c43 +#define pci_ss_info_8086_4c43 pci_ss_info_8086_2572_8086_4c43 +static const pciSubsystemInfo pci_ss_info_8086_2578_1458_2578 = + {0x1458, 0x2578, pci_subsys_8086_2578_1458_2578, 0}; +#undef pci_ss_info_1458_2578 +#define pci_ss_info_1458_2578 pci_ss_info_8086_2578_1458_2578 +static const pciSubsystemInfo pci_ss_info_8086_2578_1462_7580 = + {0x1462, 0x7580, pci_subsys_8086_2578_1462_7580, 0}; +#undef pci_ss_info_1462_7580 +#define pci_ss_info_1462_7580 pci_ss_info_8086_2578_1462_7580 +static const pciSubsystemInfo pci_ss_info_8086_2578_15d9_4580 = + {0x15d9, 0x4580, pci_subsys_8086_2578_15d9_4580, 0}; +#undef pci_ss_info_15d9_4580 +#define pci_ss_info_15d9_4580 pci_ss_info_8086_2578_15d9_4580 +static const pciSubsystemInfo pci_ss_info_8086_2580_1458_2580 = + {0x1458, 0x2580, pci_subsys_8086_2580_1458_2580, 0}; +#undef pci_ss_info_1458_2580 +#define pci_ss_info_1458_2580 pci_ss_info_8086_2580_1458_2580 +static const pciSubsystemInfo pci_ss_info_8086_2580_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_2580_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_2580_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_2580_1734_105b = + {0x1734, 0x105b, pci_subsys_8086_2580_1734_105b, 0}; +#undef pci_ss_info_1734_105b +#define pci_ss_info_1734_105b pci_ss_info_8086_2580_1734_105b +static const pciSubsystemInfo pci_ss_info_8086_2582_1028_1079 = + {0x1028, 0x1079, pci_subsys_8086_2582_1028_1079, 0}; +#undef pci_ss_info_1028_1079 +#define pci_ss_info_1028_1079 pci_ss_info_8086_2582_1028_1079 +static const pciSubsystemInfo pci_ss_info_8086_2582_103c_3006 = + {0x103c, 0x3006, pci_subsys_8086_2582_103c_3006, 0}; +#undef pci_ss_info_103c_3006 +#define pci_ss_info_103c_3006 pci_ss_info_8086_2582_103c_3006 +static const pciSubsystemInfo pci_ss_info_8086_2582_1043_2582 = + {0x1043, 0x2582, pci_subsys_8086_2582_1043_2582, 0}; +#undef pci_ss_info_1043_2582 +#define pci_ss_info_1043_2582 pci_ss_info_8086_2582_1043_2582 +static const pciSubsystemInfo pci_ss_info_8086_2582_1458_2582 = + {0x1458, 0x2582, pci_subsys_8086_2582_1458_2582, 0}; +#undef pci_ss_info_1458_2582 +#define pci_ss_info_1458_2582 pci_ss_info_8086_2582_1458_2582 +static const pciSubsystemInfo pci_ss_info_8086_2582_1734_105b = + {0x1734, 0x105b, pci_subsys_8086_2582_1734_105b, 0}; +#undef pci_ss_info_1734_105b +#define pci_ss_info_1734_105b pci_ss_info_8086_2582_1734_105b +static const pciSubsystemInfo pci_ss_info_8086_2590_1028_0182 = + {0x1028, 0x0182, pci_subsys_8086_2590_1028_0182, 0}; +#undef pci_ss_info_1028_0182 +#define pci_ss_info_1028_0182 pci_ss_info_8086_2590_1028_0182 +static const pciSubsystemInfo pci_ss_info_8086_2590_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2590_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2590_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2590_a304_81b7 = + {0xa304, 0x81b7, pci_subsys_8086_2590_a304_81b7, 0}; +#undef pci_ss_info_a304_81b7 +#define pci_ss_info_a304_81b7 pci_ss_info_8086_2590_a304_81b7 +static const pciSubsystemInfo pci_ss_info_8086_2592_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2592_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2592_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2592_103c_308a = + {0x103c, 0x308a, pci_subsys_8086_2592_103c_308a, 0}; +#undef pci_ss_info_103c_308a +#define pci_ss_info_103c_308a pci_ss_info_8086_2592_103c_308a +static const pciSubsystemInfo pci_ss_info_8086_2592_1043_1881 = + {0x1043, 0x1881, pci_subsys_8086_2592_1043_1881, 0}; +#undef pci_ss_info_1043_1881 +#define pci_ss_info_1043_1881 pci_ss_info_8086_2592_1043_1881 +static const pciSubsystemInfo pci_ss_info_8086_25a2_1775_10d0 = + {0x1775, 0x10d0, pci_subsys_8086_25a2_1775_10d0, 0}; +#undef pci_ss_info_1775_10d0 +#define pci_ss_info_1775_10d0 pci_ss_info_8086_25a2_1775_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25a2_1775_ce90 = + {0x1775, 0xce90, pci_subsys_8086_25a2_1775_ce90, 0}; +#undef pci_ss_info_1775_ce90 +#define pci_ss_info_1775_ce90 pci_ss_info_8086_25a2_1775_ce90 +static const pciSubsystemInfo pci_ss_info_8086_25a2_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25a2_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25a2_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25a2_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25a2_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25a2_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25a3_1775_ce90 = + {0x1775, 0xce90, pci_subsys_8086_25a3_1775_ce90, 0}; +#undef pci_ss_info_1775_ce90 +#define pci_ss_info_1775_ce90 pci_ss_info_8086_25a3_1775_ce90 +static const pciSubsystemInfo pci_ss_info_8086_25a3_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25a3_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25a3_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25a3_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25a3_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25a3_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25a3_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25a3_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25a3_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25a4_1775_10d0 = + {0x1775, 0x10d0, pci_subsys_8086_25a4_1775_10d0, 0}; +#undef pci_ss_info_1775_10d0 +#define pci_ss_info_1775_10d0 pci_ss_info_8086_25a4_1775_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25a4_1775_ce90 = + {0x1775, 0xce90, pci_subsys_8086_25a4_1775_ce90, 0}; +#undef pci_ss_info_1775_ce90 +#define pci_ss_info_1775_ce90 pci_ss_info_8086_25a4_1775_ce90 +static const pciSubsystemInfo pci_ss_info_8086_25a4_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25a4_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25a4_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25a4_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25a4_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25a4_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25a4_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25a4_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25a4_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25a6_1775_ce90 = + {0x1775, 0xce90, pci_subsys_8086_25a6_1775_ce90, 0}; +#undef pci_ss_info_1775_ce90 +#define pci_ss_info_1775_ce90 pci_ss_info_8086_25a6_1775_ce90 +static const pciSubsystemInfo pci_ss_info_8086_25a6_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25a6_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25a6_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25a9_1775_10d0 = + {0x1775, 0x10d0, pci_subsys_8086_25a9_1775_10d0, 0}; +#undef pci_ss_info_1775_10d0 +#define pci_ss_info_1775_10d0 pci_ss_info_8086_25a9_1775_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25a9_1775_ce90 = + {0x1775, 0xce90, pci_subsys_8086_25a9_1775_ce90, 0}; +#undef pci_ss_info_1775_ce90 +#define pci_ss_info_1775_ce90 pci_ss_info_8086_25a9_1775_ce90 +static const pciSubsystemInfo pci_ss_info_8086_25a9_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25a9_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25a9_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25a9_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25a9_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25a9_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25a9_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25a9_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25a9_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25aa_1775_ce90 = + {0x1775, 0xce90, pci_subsys_8086_25aa_1775_ce90, 0}; +#undef pci_ss_info_1775_ce90 +#define pci_ss_info_1775_ce90 pci_ss_info_8086_25aa_1775_ce90 +static const pciSubsystemInfo pci_ss_info_8086_25aa_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25aa_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25aa_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25aa_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25aa_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25aa_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25ab_1775_10d0 = + {0x1775, 0x10d0, pci_subsys_8086_25ab_1775_10d0, 0}; +#undef pci_ss_info_1775_10d0 +#define pci_ss_info_1775_10d0 pci_ss_info_8086_25ab_1775_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25ab_1775_ce90 = + {0x1775, 0xce90, pci_subsys_8086_25ab_1775_ce90, 0}; +#undef pci_ss_info_1775_ce90 +#define pci_ss_info_1775_ce90 pci_ss_info_8086_25ab_1775_ce90 +static const pciSubsystemInfo pci_ss_info_8086_25ab_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25ab_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25ab_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25ab_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25ab_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25ab_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25ab_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25ab_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25ab_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25ac_1775_10d0 = + {0x1775, 0x10d0, pci_subsys_8086_25ac_1775_10d0, 0}; +#undef pci_ss_info_1775_10d0 +#define pci_ss_info_1775_10d0 pci_ss_info_8086_25ac_1775_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25ac_1775_ce90 = + {0x1775, 0xce90, pci_subsys_8086_25ac_1775_ce90, 0}; +#undef pci_ss_info_1775_ce90 +#define pci_ss_info_1775_ce90 pci_ss_info_8086_25ac_1775_ce90 +static const pciSubsystemInfo pci_ss_info_8086_25ac_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25ac_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25ac_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25ac_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25ac_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25ac_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25ac_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25ac_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25ac_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25ad_1775_10d0 = + {0x1775, 0x10d0, pci_subsys_8086_25ad_1775_10d0, 0}; +#undef pci_ss_info_1775_10d0 +#define pci_ss_info_1775_10d0 pci_ss_info_8086_25ad_1775_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25ad_1775_ce90 = + {0x1775, 0xce90, pci_subsys_8086_25ad_1775_ce90, 0}; +#undef pci_ss_info_1775_ce90 +#define pci_ss_info_1775_ce90 pci_ss_info_8086_25ad_1775_ce90 +static const pciSubsystemInfo pci_ss_info_8086_25ad_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_25ad_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_25ad_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_25ad_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25ad_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25ad_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25ad_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25ad_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25ad_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_25b0_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_25b0_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_25b0_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_25b0_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_25b0_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_25b0_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_2640_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_2640_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_2640_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_2640_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_2640_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_2640_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_2641_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2641_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2641_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2651_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_2651_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_2651_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_2651_1043_2601 = + {0x1043, 0x2601, pci_subsys_8086_2651_1043_2601, 0}; +#undef pci_ss_info_1043_2601 +#define pci_ss_info_1043_2601 pci_ss_info_8086_2651_1043_2601 +static const pciSubsystemInfo pci_ss_info_8086_2651_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_2651_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_2651_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_2651_8086_4147 = + {0x8086, 0x4147, pci_subsys_8086_2651_8086_4147, 0}; +#undef pci_ss_info_8086_4147 +#define pci_ss_info_8086_4147 pci_ss_info_8086_2651_8086_4147 +static const pciSubsystemInfo pci_ss_info_8086_2652_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_2652_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_2652_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_2658_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_2658_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_2658_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_2658_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2658_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2658_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2658_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_2658_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_2658_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_2658_1458_2558 = + {0x1458, 0x2558, pci_subsys_8086_2658_1458_2558, 0}; +#undef pci_ss_info_1458_2558 +#define pci_ss_info_1458_2558 pci_ss_info_8086_2658_1458_2558 +static const pciSubsystemInfo pci_ss_info_8086_2658_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_2658_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_2658_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_2658_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_2658_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_2658_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_2659_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_2659_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_2659_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_2659_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2659_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2659_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2659_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_2659_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_2659_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_2659_1458_2659 = + {0x1458, 0x2659, pci_subsys_8086_2659_1458_2659, 0}; +#undef pci_ss_info_1458_2659 +#define pci_ss_info_1458_2659 pci_ss_info_8086_2659_1458_2659 +static const pciSubsystemInfo pci_ss_info_8086_2659_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_2659_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_2659_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_2659_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_2659_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_2659_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_265a_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_265a_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_265a_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_265a_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_265a_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_265a_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_265a_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_265a_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_265a_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_265a_1458_265a = + {0x1458, 0x265a, pci_subsys_8086_265a_1458_265a, 0}; +#undef pci_ss_info_1458_265a +#define pci_ss_info_1458_265a pci_ss_info_8086_265a_1458_265a +static const pciSubsystemInfo pci_ss_info_8086_265a_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_265a_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_265a_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_265a_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_265a_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_265a_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_265b_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_265b_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_265b_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_265b_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_265b_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_265b_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_265b_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_265b_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_265b_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_265b_1458_265a = + {0x1458, 0x265a, pci_subsys_8086_265b_1458_265a, 0}; +#undef pci_ss_info_1458_265a +#define pci_ss_info_1458_265a pci_ss_info_8086_265b_1458_265a +static const pciSubsystemInfo pci_ss_info_8086_265b_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_265b_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_265b_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_265b_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_265b_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_265b_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_265c_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_265c_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_265c_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_265c_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_265c_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_265c_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_265c_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_265c_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_265c_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_265c_1458_5006 = + {0x1458, 0x5006, pci_subsys_8086_265c_1458_5006, 0}; +#undef pci_ss_info_1458_5006 +#define pci_ss_info_1458_5006 pci_ss_info_8086_265c_1458_5006 +static const pciSubsystemInfo pci_ss_info_8086_265c_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_265c_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_265c_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_265c_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_265c_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_265c_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_265c_8086_265c = + {0x8086, 0x265c, pci_subsys_8086_265c_8086_265c, 0}; +#undef pci_ss_info_8086_265c +#define pci_ss_info_8086_265c pci_ss_info_8086_265c_8086_265c +static const pciSubsystemInfo pci_ss_info_8086_2660_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2660_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2660_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2668_103c_2a09 = + {0x103c, 0x2a09, pci_subsys_8086_2668_103c_2a09, 0}; +#undef pci_ss_info_103c_2a09 +#define pci_ss_info_103c_2a09 pci_ss_info_8086_2668_103c_2a09 +static const pciSubsystemInfo pci_ss_info_8086_2668_1043_814e = + {0x1043, 0x814e, pci_subsys_8086_2668_1043_814e, 0}; +#undef pci_ss_info_1043_814e +#define pci_ss_info_1043_814e pci_ss_info_8086_2668_1043_814e +static const pciSubsystemInfo pci_ss_info_8086_266a_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_266a_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_266a_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_266a_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_266a_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_266a_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_266a_1458_266a = + {0x1458, 0x266a, pci_subsys_8086_266a_1458_266a, 0}; +#undef pci_ss_info_1458_266a +#define pci_ss_info_1458_266a pci_ss_info_8086_266a_1458_266a +static const pciSubsystemInfo pci_ss_info_8086_266a_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_266a_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_266a_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_266a_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_266a_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_266a_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_266d_1025_006a = + {0x1025, 0x006a, pci_subsys_8086_266d_1025_006a, 0}; +#undef pci_ss_info_1025_006a +#define pci_ss_info_1025_006a pci_ss_info_8086_266d_1025_006a +static const pciSubsystemInfo pci_ss_info_8086_266d_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_266d_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_266d_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_266e_1025_006a = + {0x1025, 0x006a, pci_subsys_8086_266e_1025_006a, 0}; +#undef pci_ss_info_1025_006a +#define pci_ss_info_1025_006a pci_ss_info_8086_266e_1025_006a +static const pciSubsystemInfo pci_ss_info_8086_266e_1028_0179 = + {0x1028, 0x0179, pci_subsys_8086_266e_1028_0179, 0}; +#undef pci_ss_info_1028_0179 +#define pci_ss_info_1028_0179 pci_ss_info_8086_266e_1028_0179 +static const pciSubsystemInfo pci_ss_info_8086_266e_1028_0182 = + {0x1028, 0x0182, pci_subsys_8086_266e_1028_0182, 0}; +#undef pci_ss_info_1028_0182 +#define pci_ss_info_1028_0182 pci_ss_info_8086_266e_1028_0182 +static const pciSubsystemInfo pci_ss_info_8086_266e_1028_0188 = + {0x1028, 0x0188, pci_subsys_8086_266e_1028_0188, 0}; +#undef pci_ss_info_1028_0188 +#define pci_ss_info_1028_0188 pci_ss_info_8086_266e_1028_0188 +static const pciSubsystemInfo pci_ss_info_8086_266e_103c_0944 = + {0x103c, 0x0944, pci_subsys_8086_266e_103c_0944, 0}; +#undef pci_ss_info_103c_0944 +#define pci_ss_info_103c_0944 pci_ss_info_8086_266e_103c_0944 +static const pciSubsystemInfo pci_ss_info_8086_266e_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_266e_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_266e_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_266e_103c_3006 = + {0x103c, 0x3006, pci_subsys_8086_266e_103c_3006, 0}; +#undef pci_ss_info_103c_3006 +#define pci_ss_info_103c_3006 pci_ss_info_8086_266e_103c_3006 +static const pciSubsystemInfo pci_ss_info_8086_266e_1458_a002 = + {0x1458, 0xa002, pci_subsys_8086_266e_1458_a002, 0}; +#undef pci_ss_info_1458_a002 +#define pci_ss_info_1458_a002 pci_ss_info_8086_266e_1458_a002 +static const pciSubsystemInfo pci_ss_info_8086_266e_152d_0745 = + {0x152d, 0x0745, pci_subsys_8086_266e_152d_0745, 0}; +#undef pci_ss_info_152d_0745 +#define pci_ss_info_152d_0745 pci_ss_info_8086_266e_152d_0745 +static const pciSubsystemInfo pci_ss_info_8086_266e_1734_105a = + {0x1734, 0x105a, pci_subsys_8086_266e_1734_105a, 0}; +#undef pci_ss_info_1734_105a +#define pci_ss_info_1734_105a pci_ss_info_8086_266e_1734_105a +static const pciSubsystemInfo pci_ss_info_8086_266f_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_266f_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_266f_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_266f_1043_80a6 = + {0x1043, 0x80a6, pci_subsys_8086_266f_1043_80a6, 0}; +#undef pci_ss_info_1043_80a6 +#define pci_ss_info_1043_80a6 pci_ss_info_8086_266f_1043_80a6 +static const pciSubsystemInfo pci_ss_info_8086_266f_1458_266f = + {0x1458, 0x266f, pci_subsys_8086_266f_1458_266f, 0}; +#undef pci_ss_info_1458_266f +#define pci_ss_info_1458_266f pci_ss_info_8086_266f_1458_266f +static const pciSubsystemInfo pci_ss_info_8086_266f_1462_7028 = + {0x1462, 0x7028, pci_subsys_8086_266f_1462_7028, 0}; +#undef pci_ss_info_1462_7028 +#define pci_ss_info_1462_7028 pci_ss_info_8086_266f_1462_7028 +static const pciSubsystemInfo pci_ss_info_8086_266f_1734_105c = + {0x1734, 0x105c, pci_subsys_8086_266f_1734_105c, 0}; +#undef pci_ss_info_1734_105c +#define pci_ss_info_1734_105c pci_ss_info_8086_266f_1734_105c +static const pciSubsystemInfo pci_ss_info_8086_2770_107b_5048 = + {0x107b, 0x5048, pci_subsys_8086_2770_107b_5048, 0}; +#undef pci_ss_info_107b_5048 +#define pci_ss_info_107b_5048 pci_ss_info_8086_2770_107b_5048 +static const pciSubsystemInfo pci_ss_info_8086_2770_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_2770_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_2770_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_2772_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_2772_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_2772_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_2782_1043_2582 = + {0x1043, 0x2582, pci_subsys_8086_2782_1043_2582, 0}; +#undef pci_ss_info_1043_2582 +#define pci_ss_info_1043_2582 pci_ss_info_8086_2782_1043_2582 +static const pciSubsystemInfo pci_ss_info_8086_2782_1734_105b = + {0x1734, 0x105b, pci_subsys_8086_2782_1734_105b, 0}; +#undef pci_ss_info_1734_105b +#define pci_ss_info_1734_105b pci_ss_info_8086_2782_1734_105b +static const pciSubsystemInfo pci_ss_info_8086_2792_103c_099c = + {0x103c, 0x099c, pci_subsys_8086_2792_103c_099c, 0}; +#undef pci_ss_info_103c_099c +#define pci_ss_info_103c_099c pci_ss_info_8086_2792_103c_099c +static const pciSubsystemInfo pci_ss_info_8086_2792_1043_1881 = + {0x1043, 0x1881, pci_subsys_8086_2792_1043_1881, 0}; +#undef pci_ss_info_1043_1881 +#define pci_ss_info_1043_1881 pci_ss_info_8086_2792_1043_1881 +static const pciSubsystemInfo pci_ss_info_8086_27a0_17aa_2017 = + {0x17aa, 0x2017, pci_subsys_8086_27a0_17aa_2017, 0}; +#undef pci_ss_info_17aa_2017 +#define pci_ss_info_17aa_2017 pci_ss_info_8086_27a0_17aa_2017 +static const pciSubsystemInfo pci_ss_info_8086_27a2_17aa_201a = + {0x17aa, 0x201a, pci_subsys_8086_27a2_17aa_201a, 0}; +#undef pci_ss_info_17aa_201a +#define pci_ss_info_17aa_201a pci_ss_info_8086_27a2_17aa_201a +static const pciSubsystemInfo pci_ss_info_8086_27a6_17aa_201a = + {0x17aa, 0x201a, pci_subsys_8086_27a6_17aa_201a, 0}; +#undef pci_ss_info_17aa_201a +#define pci_ss_info_17aa_201a pci_ss_info_8086_27a6_17aa_201a +static const pciSubsystemInfo pci_ss_info_8086_27b8_107b_5048 = + {0x107b, 0x5048, pci_subsys_8086_27b8_107b_5048, 0}; +#undef pci_ss_info_107b_5048 +#define pci_ss_info_107b_5048 pci_ss_info_8086_27b8_107b_5048 +static const pciSubsystemInfo pci_ss_info_8086_27b8_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27b8_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27b8_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27b9_17aa_2009 = + {0x17aa, 0x2009, pci_subsys_8086_27b9_17aa_2009, 0}; +#undef pci_ss_info_17aa_2009 +#define pci_ss_info_17aa_2009 pci_ss_info_8086_27b9_17aa_2009 +static const pciSubsystemInfo pci_ss_info_8086_27c0_107b_5048 = + {0x107b, 0x5048, pci_subsys_8086_27c0_107b_5048, 0}; +#undef pci_ss_info_107b_5048 +#define pci_ss_info_107b_5048 pci_ss_info_8086_27c0_107b_5048 +static const pciSubsystemInfo pci_ss_info_8086_27c0_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27c0_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27c0_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27c5_17aa_200d = + {0x17aa, 0x200d, pci_subsys_8086_27c5_17aa_200d, 0}; +#undef pci_ss_info_17aa_200d +#define pci_ss_info_17aa_200d pci_ss_info_8086_27c5_17aa_200d +static const pciSubsystemInfo pci_ss_info_8086_27c8_107b_5048 = + {0x107b, 0x5048, pci_subsys_8086_27c8_107b_5048, 0}; +#undef pci_ss_info_107b_5048 +#define pci_ss_info_107b_5048 pci_ss_info_8086_27c8_107b_5048 +static const pciSubsystemInfo pci_ss_info_8086_27c8_17aa_200a = + {0x17aa, 0x200a, pci_subsys_8086_27c8_17aa_200a, 0}; +#undef pci_ss_info_17aa_200a +#define pci_ss_info_17aa_200a pci_ss_info_8086_27c8_17aa_200a +static const pciSubsystemInfo pci_ss_info_8086_27c8_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27c8_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27c8_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27c9_107b_5048 = + {0x107b, 0x5048, pci_subsys_8086_27c9_107b_5048, 0}; +#undef pci_ss_info_107b_5048 +#define pci_ss_info_107b_5048 pci_ss_info_8086_27c9_107b_5048 +static const pciSubsystemInfo pci_ss_info_8086_27c9_17aa_200a = + {0x17aa, 0x200a, pci_subsys_8086_27c9_17aa_200a, 0}; +#undef pci_ss_info_17aa_200a +#define pci_ss_info_17aa_200a pci_ss_info_8086_27c9_17aa_200a +static const pciSubsystemInfo pci_ss_info_8086_27c9_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27c9_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27c9_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27ca_107b_5048 = + {0x107b, 0x5048, pci_subsys_8086_27ca_107b_5048, 0}; +#undef pci_ss_info_107b_5048 +#define pci_ss_info_107b_5048 pci_ss_info_8086_27ca_107b_5048 +static const pciSubsystemInfo pci_ss_info_8086_27ca_17aa_200a = + {0x17aa, 0x200a, pci_subsys_8086_27ca_17aa_200a, 0}; +#undef pci_ss_info_17aa_200a +#define pci_ss_info_17aa_200a pci_ss_info_8086_27ca_17aa_200a +static const pciSubsystemInfo pci_ss_info_8086_27ca_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27ca_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27ca_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27cb_107b_5048 = + {0x107b, 0x5048, pci_subsys_8086_27cb_107b_5048, 0}; +#undef pci_ss_info_107b_5048 +#define pci_ss_info_107b_5048 pci_ss_info_8086_27cb_107b_5048 +static const pciSubsystemInfo pci_ss_info_8086_27cb_17aa_200a = + {0x17aa, 0x200a, pci_subsys_8086_27cb_17aa_200a, 0}; +#undef pci_ss_info_17aa_200a +#define pci_ss_info_17aa_200a pci_ss_info_8086_27cb_17aa_200a +static const pciSubsystemInfo pci_ss_info_8086_27cb_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27cb_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27cb_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27cc_17aa_200b = + {0x17aa, 0x200b, pci_subsys_8086_27cc_17aa_200b, 0}; +#undef pci_ss_info_17aa_200b +#define pci_ss_info_17aa_200b pci_ss_info_8086_27cc_17aa_200b +static const pciSubsystemInfo pci_ss_info_8086_27cc_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27cc_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27cc_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27d8_107b_5048 = + {0x107b, 0x5048, pci_subsys_8086_27d8_107b_5048, 0}; +#undef pci_ss_info_107b_5048 +#define pci_ss_info_107b_5048 pci_ss_info_8086_27d8_107b_5048 +static const pciSubsystemInfo pci_ss_info_8086_27d8_152d_0753 = + {0x152d, 0x0753, pci_subsys_8086_27d8_152d_0753, 0}; +#undef pci_ss_info_152d_0753 +#define pci_ss_info_152d_0753 pci_ss_info_8086_27d8_152d_0753 +static const pciSubsystemInfo pci_ss_info_8086_27d8_17aa_2010 = + {0x17aa, 0x2010, pci_subsys_8086_27d8_17aa_2010, 0}; +#undef pci_ss_info_17aa_2010 +#define pci_ss_info_17aa_2010 pci_ss_info_8086_27d8_17aa_2010 +static const pciSubsystemInfo pci_ss_info_8086_27da_17aa_200f = + {0x17aa, 0x200f, pci_subsys_8086_27da_17aa_200f, 0}; +#undef pci_ss_info_17aa_200f +#define pci_ss_info_17aa_200f pci_ss_info_8086_27da_17aa_200f +static const pciSubsystemInfo pci_ss_info_8086_27da_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27da_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27da_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_27dc_8086_308d = + {0x8086, 0x308d, pci_subsys_8086_27dc_8086_308d, 0}; +#undef pci_ss_info_8086_308d +#define pci_ss_info_8086_308d pci_ss_info_8086_27dc_8086_308d +static const pciSubsystemInfo pci_ss_info_8086_27df_107b_5048 = + {0x107b, 0x5048, pci_subsys_8086_27df_107b_5048, 0}; +#undef pci_ss_info_107b_5048 +#define pci_ss_info_107b_5048 pci_ss_info_8086_27df_107b_5048 +static const pciSubsystemInfo pci_ss_info_8086_27df_17aa_200c = + {0x17aa, 0x200c, pci_subsys_8086_27df_17aa_200c, 0}; +#undef pci_ss_info_17aa_200c +#define pci_ss_info_17aa_200c pci_ss_info_8086_27df_17aa_200c +static const pciSubsystemInfo pci_ss_info_8086_27df_8086_544e = + {0x8086, 0x544e, pci_subsys_8086_27df_8086_544e, 0}; +#undef pci_ss_info_8086_544e +#define pci_ss_info_8086_544e pci_ss_info_8086_27df_8086_544e +static const pciSubsystemInfo pci_ss_info_8086_3340_1025_005a = + {0x1025, 0x005a, pci_subsys_8086_3340_1025_005a, 0}; +#undef pci_ss_info_1025_005a +#define pci_ss_info_1025_005a pci_ss_info_8086_3340_1025_005a +static const pciSubsystemInfo pci_ss_info_8086_3340_103c_088c = + {0x103c, 0x088c, pci_subsys_8086_3340_103c_088c, 0}; +#undef pci_ss_info_103c_088c +#define pci_ss_info_103c_088c pci_ss_info_8086_3340_103c_088c +static const pciSubsystemInfo pci_ss_info_8086_3340_103c_0890 = + {0x103c, 0x0890, pci_subsys_8086_3340_103c_0890, 0}; +#undef pci_ss_info_103c_0890 +#define pci_ss_info_103c_0890 pci_ss_info_8086_3340_103c_0890 +static const pciSubsystemInfo pci_ss_info_8086_3340_103c_08b0 = + {0x103c, 0x08b0, pci_subsys_8086_3340_103c_08b0, 0}; +#undef pci_ss_info_103c_08b0 +#define pci_ss_info_103c_08b0 pci_ss_info_8086_3340_103c_08b0 +static const pciSubsystemInfo pci_ss_info_8086_3575_0e11_0030 = + {0x0e11, 0x0030, pci_subsys_8086_3575_0e11_0030, 0}; +#undef pci_ss_info_0e11_0030 +#define pci_ss_info_0e11_0030 pci_ss_info_8086_3575_0e11_0030 +static const pciSubsystemInfo pci_ss_info_8086_3575_1014_021d = + {0x1014, 0x021d, pci_subsys_8086_3575_1014_021d, 0}; +#undef pci_ss_info_1014_021d +#define pci_ss_info_1014_021d pci_ss_info_8086_3575_1014_021d +static const pciSubsystemInfo pci_ss_info_8086_3575_104d_80e7 = + {0x104d, 0x80e7, pci_subsys_8086_3575_104d_80e7, 0}; +#undef pci_ss_info_104d_80e7 +#define pci_ss_info_104d_80e7 pci_ss_info_8086_3575_104d_80e7 +static const pciSubsystemInfo pci_ss_info_8086_3577_1014_0513 = + {0x1014, 0x0513, pci_subsys_8086_3577_1014_0513, 0}; +#undef pci_ss_info_1014_0513 +#define pci_ss_info_1014_0513 pci_ss_info_8086_3577_1014_0513 +static const pciSubsystemInfo pci_ss_info_8086_3580_1014_055c = + {0x1014, 0x055c, pci_subsys_8086_3580_1014_055c, 0}; +#undef pci_ss_info_1014_055c +#define pci_ss_info_1014_055c pci_ss_info_8086_3580_1014_055c +static const pciSubsystemInfo pci_ss_info_8086_3580_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_3580_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_3580_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_3580_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_3580_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_3580_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_3580_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_3580_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_3580_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_3580_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_3580_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_3580_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_3580_1775_10d0 = + {0x1775, 0x10d0, pci_subsys_8086_3580_1775_10d0, 0}; +#undef pci_ss_info_1775_10d0 +#define pci_ss_info_1775_10d0 pci_ss_info_8086_3580_1775_10d0 +static const pciSubsystemInfo pci_ss_info_8086_3580_1775_ce90 = + {0x1775, 0xce90, pci_subsys_8086_3580_1775_ce90, 0}; +#undef pci_ss_info_1775_ce90 +#define pci_ss_info_1775_ce90 pci_ss_info_8086_3580_1775_ce90 +static const pciSubsystemInfo pci_ss_info_8086_3580_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_3580_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_3580_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_3580_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_3580_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_3580_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_3581_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_3581_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_3581_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_3582_1014_0562 = + {0x1014, 0x0562, pci_subsys_8086_3582_1014_0562, 0}; +#undef pci_ss_info_1014_0562 +#define pci_ss_info_1014_0562 pci_ss_info_8086_3582_1014_0562 +static const pciSubsystemInfo pci_ss_info_8086_3582_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_3582_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_3582_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_3582_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_3582_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_3582_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_3582_1775_10d0 = + {0x1775, 0x10d0, pci_subsys_8086_3582_1775_10d0, 0}; +#undef pci_ss_info_1775_10d0 +#define pci_ss_info_1775_10d0 pci_ss_info_8086_3582_1775_10d0 +static const pciSubsystemInfo pci_ss_info_8086_3582_1775_ce90 = + {0x1775, 0xce90, pci_subsys_8086_3582_1775_ce90, 0}; +#undef pci_ss_info_1775_ce90 +#define pci_ss_info_1775_ce90 pci_ss_info_8086_3582_1775_ce90 +static const pciSubsystemInfo pci_ss_info_8086_3582_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_3582_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_3582_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_3582_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_3582_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_3582_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_3584_1014_055d = + {0x1014, 0x055d, pci_subsys_8086_3584_1014_055d, 0}; +#undef pci_ss_info_1014_055d +#define pci_ss_info_1014_055d pci_ss_info_8086_3584_1014_055d +static const pciSubsystemInfo pci_ss_info_8086_3584_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_3584_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_3584_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_3584_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_3584_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_3584_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_3584_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_3584_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_3584_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_3584_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_3584_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_3584_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_3584_1775_10d0 = + {0x1775, 0x10d0, pci_subsys_8086_3584_1775_10d0, 0}; +#undef pci_ss_info_1775_10d0 +#define pci_ss_info_1775_10d0 pci_ss_info_8086_3584_1775_10d0 +static const pciSubsystemInfo pci_ss_info_8086_3584_1775_ce90 = + {0x1775, 0xce90, pci_subsys_8086_3584_1775_ce90, 0}; +#undef pci_ss_info_1775_ce90 +#define pci_ss_info_1775_ce90 pci_ss_info_8086_3584_1775_ce90 +static const pciSubsystemInfo pci_ss_info_8086_3584_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_3584_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_3584_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_3584_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_3584_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_3584_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_3585_1014_055e = + {0x1014, 0x055e, pci_subsys_8086_3585_1014_055e, 0}; +#undef pci_ss_info_1014_055e +#define pci_ss_info_1014_055e pci_ss_info_8086_3585_1014_055e +static const pciSubsystemInfo pci_ss_info_8086_3585_1028_0139 = + {0x1028, 0x0139, pci_subsys_8086_3585_1028_0139, 0}; +#undef pci_ss_info_1028_0139 +#define pci_ss_info_1028_0139 pci_ss_info_8086_3585_1028_0139 +static const pciSubsystemInfo pci_ss_info_8086_3585_1028_0163 = + {0x1028, 0x0163, pci_subsys_8086_3585_1028_0163, 0}; +#undef pci_ss_info_1028_0163 +#define pci_ss_info_1028_0163 pci_ss_info_8086_3585_1028_0163 +static const pciSubsystemInfo pci_ss_info_8086_3585_1028_0196 = + {0x1028, 0x0196, pci_subsys_8086_3585_1028_0196, 0}; +#undef pci_ss_info_1028_0196 +#define pci_ss_info_1028_0196 pci_ss_info_8086_3585_1028_0196 +static const pciSubsystemInfo pci_ss_info_8086_3585_1734_1055 = + {0x1734, 0x1055, pci_subsys_8086_3585_1734_1055, 0}; +#undef pci_ss_info_1734_1055 +#define pci_ss_info_1734_1055 pci_ss_info_8086_3585_1734_1055 +static const pciSubsystemInfo pci_ss_info_8086_3585_1775_10d0 = + {0x1775, 0x10d0, pci_subsys_8086_3585_1775_10d0, 0}; +#undef pci_ss_info_1775_10d0 +#define pci_ss_info_1775_10d0 pci_ss_info_8086_3585_1775_10d0 +static const pciSubsystemInfo pci_ss_info_8086_3585_1775_ce90 = + {0x1775, 0xce90, pci_subsys_8086_3585_1775_ce90, 0}; +#undef pci_ss_info_1775_ce90 +#define pci_ss_info_1775_ce90 pci_ss_info_8086_3585_1775_ce90 +static const pciSubsystemInfo pci_ss_info_8086_3585_4c53_10b0 = + {0x4c53, 0x10b0, pci_subsys_8086_3585_4c53_10b0, 0}; +#undef pci_ss_info_4c53_10b0 +#define pci_ss_info_4c53_10b0 pci_ss_info_8086_3585_4c53_10b0 +static const pciSubsystemInfo pci_ss_info_8086_3585_4c53_10e0 = + {0x4c53, 0x10e0, pci_subsys_8086_3585_4c53_10e0, 0}; +#undef pci_ss_info_4c53_10e0 +#define pci_ss_info_4c53_10e0 pci_ss_info_8086_3585_4c53_10e0 +static const pciSubsystemInfo pci_ss_info_8086_3590_1028_019a = + {0x1028, 0x019a, pci_subsys_8086_3590_1028_019a, 0}; +#undef pci_ss_info_1028_019a +#define pci_ss_info_1028_019a pci_ss_info_8086_3590_1028_019a +static const pciSubsystemInfo pci_ss_info_8086_3590_1734_103e = + {0x1734, 0x103e, pci_subsys_8086_3590_1734_103e, 0}; +#undef pci_ss_info_1734_103e +#define pci_ss_info_1734_103e pci_ss_info_8086_3590_1734_103e +static const pciSubsystemInfo pci_ss_info_8086_3590_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_3590_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_3590_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_3591_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_3591_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_3591_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_3591_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_3591_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_3591_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_3594_4c53_10d0 = + {0x4c53, 0x10d0, pci_subsys_8086_3594_4c53_10d0, 0}; +#undef pci_ss_info_4c53_10d0 +#define pci_ss_info_4c53_10d0 pci_ss_info_8086_3594_4c53_10d0 +static const pciSubsystemInfo pci_ss_info_8086_359e_1028_0169 = + {0x1028, 0x0169, pci_subsys_8086_359e_1028_0169, 0}; +#undef pci_ss_info_1028_0169 +#define pci_ss_info_1028_0169 pci_ss_info_8086_359e_1028_0169 +static const pciSubsystemInfo pci_ss_info_8086_4222_8086_1005 = + {0x8086, 0x1005, pci_subsys_8086_4222_8086_1005, 0}; +#undef pci_ss_info_8086_1005 +#define pci_ss_info_8086_1005 pci_ss_info_8086_4222_8086_1005 +static const pciSubsystemInfo pci_ss_info_8086_4222_8086_1034 = + {0x8086, 0x1034, pci_subsys_8086_4222_8086_1034, 0}; +#undef pci_ss_info_8086_1034 +#define pci_ss_info_8086_1034 pci_ss_info_8086_4222_8086_1034 +static const pciSubsystemInfo pci_ss_info_8086_4222_8086_1044 = + {0x8086, 0x1044, pci_subsys_8086_4222_8086_1044, 0}; +#undef pci_ss_info_8086_1044 +#define pci_ss_info_8086_1044 pci_ss_info_8086_4222_8086_1044 +static const pciSubsystemInfo pci_ss_info_8086_4223_1351_103c = + {0x1351, 0x103c, pci_subsys_8086_4223_1351_103c, 0}; +#undef pci_ss_info_1351_103c +#define pci_ss_info_1351_103c pci_ss_info_8086_4223_1351_103c +static const pciSubsystemInfo pci_ss_info_8086_4227_8086_1011 = + {0x8086, 0x1011, pci_subsys_8086_4227_8086_1011, 0}; +#undef pci_ss_info_8086_1011 +#define pci_ss_info_8086_1011 pci_ss_info_8086_4227_8086_1011 +static const pciSubsystemInfo pci_ss_info_8086_4227_8086_1014 = + {0x8086, 0x1014, pci_subsys_8086_4227_8086_1014, 0}; +#undef pci_ss_info_8086_1014 +#define pci_ss_info_8086_1014 pci_ss_info_8086_4227_8086_1014 +static const pciSubsystemInfo pci_ss_info_8086_5201_8086_0001 = + {0x8086, 0x0001, pci_subsys_8086_5201_8086_0001, 0}; +#undef pci_ss_info_8086_0001 +#define pci_ss_info_8086_0001 pci_ss_info_8086_5201_8086_0001 +static const pciSubsystemInfo pci_ss_info_8086_7110_15ad_1976 = + {0x15ad, 0x1976, pci_subsys_8086_7110_15ad_1976, 0}; +#undef pci_ss_info_15ad_1976 +#define pci_ss_info_15ad_1976 pci_ss_info_8086_7110_15ad_1976 +static const pciSubsystemInfo pci_ss_info_8086_7111_15ad_1976 = + {0x15ad, 0x1976, pci_subsys_8086_7111_15ad_1976, 0}; +#undef pci_ss_info_15ad_1976 +#define pci_ss_info_15ad_1976 pci_ss_info_8086_7111_15ad_1976 +static const pciSubsystemInfo pci_ss_info_8086_7112_15ad_1976 = + {0x15ad, 0x1976, pci_subsys_8086_7112_15ad_1976, 0}; +#undef pci_ss_info_15ad_1976 +#define pci_ss_info_15ad_1976 pci_ss_info_8086_7112_15ad_1976 +static const pciSubsystemInfo pci_ss_info_8086_7113_15ad_1976 = + {0x15ad, 0x1976, pci_subsys_8086_7113_15ad_1976, 0}; +#undef pci_ss_info_15ad_1976 +#define pci_ss_info_15ad_1976 pci_ss_info_8086_7113_15ad_1976 +static const pciSubsystemInfo pci_ss_info_8086_7120_4c53_1040 = + {0x4c53, 0x1040, pci_subsys_8086_7120_4c53_1040, 0}; +#undef pci_ss_info_4c53_1040 +#define pci_ss_info_4c53_1040 pci_ss_info_8086_7120_4c53_1040 +static const pciSubsystemInfo pci_ss_info_8086_7120_4c53_1060 = + {0x4c53, 0x1060, pci_subsys_8086_7120_4c53_1060, 0}; +#undef pci_ss_info_4c53_1060 +#define pci_ss_info_4c53_1060 pci_ss_info_8086_7120_4c53_1060 +static const pciSubsystemInfo pci_ss_info_8086_7121_4c53_1040 = + {0x4c53, 0x1040, pci_subsys_8086_7121_4c53_1040, 0}; +#undef pci_ss_info_4c53_1040 +#define pci_ss_info_4c53_1040 pci_ss_info_8086_7121_4c53_1040 +static const pciSubsystemInfo pci_ss_info_8086_7121_4c53_1060 = + {0x4c53, 0x1060, pci_subsys_8086_7121_4c53_1060, 0}; +#undef pci_ss_info_4c53_1060 +#define pci_ss_info_4c53_1060 pci_ss_info_8086_7121_4c53_1060 +static const pciSubsystemInfo pci_ss_info_8086_7121_8086_4341 = + {0x8086, 0x4341, pci_subsys_8086_7121_8086_4341, 0}; +#undef pci_ss_info_8086_4341 +#define pci_ss_info_8086_4341 pci_ss_info_8086_7121_8086_4341 +static const pciSubsystemInfo pci_ss_info_8086_7190_0e11_0500 = + {0x0e11, 0x0500, pci_subsys_8086_7190_0e11_0500, 0}; +#undef pci_ss_info_0e11_0500 +#define pci_ss_info_0e11_0500 pci_ss_info_8086_7190_0e11_0500 +static const pciSubsystemInfo pci_ss_info_8086_7190_0e11_b110 = + {0x0e11, 0xb110, pci_subsys_8086_7190_0e11_b110, 0}; +#undef pci_ss_info_0e11_b110 +#define pci_ss_info_0e11_b110 pci_ss_info_8086_7190_0e11_b110 +static const pciSubsystemInfo pci_ss_info_8086_7190_1028_008e = + {0x1028, 0x008e, pci_subsys_8086_7190_1028_008e, 0}; +#undef pci_ss_info_1028_008e +#define pci_ss_info_1028_008e pci_ss_info_8086_7190_1028_008e +static const pciSubsystemInfo pci_ss_info_8086_7190_1179_0001 = + {0x1179, 0x0001, pci_subsys_8086_7190_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_8086_7190_1179_0001 +static const pciSubsystemInfo pci_ss_info_8086_7190_15ad_1976 = + {0x15ad, 0x1976, pci_subsys_8086_7190_15ad_1976, 0}; +#undef pci_ss_info_15ad_1976 +#define pci_ss_info_15ad_1976 pci_ss_info_8086_7190_15ad_1976 +static const pciSubsystemInfo pci_ss_info_8086_7190_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_8086_7190_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_8086_7190_4c53_1050 +static const pciSubsystemInfo pci_ss_info_8086_7190_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_8086_7190_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_8086_7190_4c53_1051 +static const pciSubsystemInfo pci_ss_info_8086_7191_1028_008e = + {0x1028, 0x008e, pci_subsys_8086_7191_1028_008e, 0}; +#undef pci_ss_info_1028_008e +#define pci_ss_info_1028_008e pci_ss_info_8086_7191_1028_008e +static const pciSubsystemInfo pci_ss_info_8086_7192_0e11_0460 = + {0x0e11, 0x0460, pci_subsys_8086_7192_0e11_0460, 0}; +#undef pci_ss_info_0e11_0460 +#define pci_ss_info_0e11_0460 pci_ss_info_8086_7192_0e11_0460 +static const pciSubsystemInfo pci_ss_info_8086_7192_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_8086_7192_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_8086_7192_4c53_1000 +static const pciSubsystemInfo pci_ss_info_8086_7194_1033_0000 = + {0x1033, 0x0000, pci_subsys_8086_7194_1033_0000, 0}; +#undef pci_ss_info_1033_0000 +#define pci_ss_info_1033_0000 pci_ss_info_8086_7194_1033_0000 +static const pciSubsystemInfo pci_ss_info_8086_7194_4c53_10a0 = + {0x4c53, 0x10a0, pci_subsys_8086_7194_4c53_10a0, 0}; +#undef pci_ss_info_4c53_10a0 +#define pci_ss_info_4c53_10a0 pci_ss_info_8086_7194_4c53_10a0 +static const pciSubsystemInfo pci_ss_info_8086_7195_1033_80cc = + {0x1033, 0x80cc, pci_subsys_8086_7195_1033_80cc, 0}; +#undef pci_ss_info_1033_80cc +#define pci_ss_info_1033_80cc pci_ss_info_8086_7195_1033_80cc +static const pciSubsystemInfo pci_ss_info_8086_7195_10cf_1099 = + {0x10cf, 0x1099, pci_subsys_8086_7195_10cf_1099, 0}; +#undef pci_ss_info_10cf_1099 +#define pci_ss_info_10cf_1099 pci_ss_info_8086_7195_10cf_1099 +static const pciSubsystemInfo pci_ss_info_8086_7195_11d4_0040 = + {0x11d4, 0x0040, pci_subsys_8086_7195_11d4_0040, 0}; +#undef pci_ss_info_11d4_0040 +#define pci_ss_info_11d4_0040 pci_ss_info_8086_7195_11d4_0040 +static const pciSubsystemInfo pci_ss_info_8086_7195_11d4_0048 = + {0x11d4, 0x0048, pci_subsys_8086_7195_11d4_0048, 0}; +#undef pci_ss_info_11d4_0048 +#define pci_ss_info_11d4_0048 pci_ss_info_8086_7195_11d4_0048 +static const pciSubsystemInfo pci_ss_info_8086_71a0_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_8086_71a0_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_8086_71a0_4c53_1050 +static const pciSubsystemInfo pci_ss_info_8086_71a0_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_8086_71a0_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_8086_71a0_4c53_1051 +static const pciSubsystemInfo pci_ss_info_8086_71a2_4c53_1000 = + {0x4c53, 0x1000, pci_subsys_8086_71a2_4c53_1000, 0}; +#undef pci_ss_info_4c53_1000 +#define pci_ss_info_4c53_1000 pci_ss_info_8086_71a2_4c53_1000 +static const pciSubsystemInfo pci_ss_info_8086_7800_003d_0008 = + {0x003d, 0x0008, pci_subsys_8086_7800_003d_0008, 0}; +#undef pci_ss_info_003d_0008 +#define pci_ss_info_003d_0008 pci_ss_info_8086_7800_003d_0008 +static const pciSubsystemInfo pci_ss_info_8086_7800_003d_000b = + {0x003d, 0x000b, pci_subsys_8086_7800_003d_000b, 0}; +#undef pci_ss_info_003d_000b +#define pci_ss_info_003d_000b pci_ss_info_8086_7800_003d_000b +static const pciSubsystemInfo pci_ss_info_8086_7800_1092_0100 = + {0x1092, 0x0100, pci_subsys_8086_7800_1092_0100, 0}; +#undef pci_ss_info_1092_0100 +#define pci_ss_info_1092_0100 pci_ss_info_8086_7800_1092_0100 +static const pciSubsystemInfo pci_ss_info_8086_7800_10b4_201a = + {0x10b4, 0x201a, pci_subsys_8086_7800_10b4_201a, 0}; +#undef pci_ss_info_10b4_201a +#define pci_ss_info_10b4_201a pci_ss_info_8086_7800_10b4_201a +static const pciSubsystemInfo pci_ss_info_8086_7800_10b4_202f = + {0x10b4, 0x202f, pci_subsys_8086_7800_10b4_202f, 0}; +#undef pci_ss_info_10b4_202f +#define pci_ss_info_10b4_202f pci_ss_info_8086_7800_10b4_202f +static const pciSubsystemInfo pci_ss_info_8086_7800_8086_0000 = + {0x8086, 0x0000, pci_subsys_8086_7800_8086_0000, 0}; +#undef pci_ss_info_8086_0000 +#define pci_ss_info_8086_0000 pci_ss_info_8086_7800_8086_0000 +static const pciSubsystemInfo pci_ss_info_8086_7800_8086_0100 = + {0x8086, 0x0100, pci_subsys_8086_7800_8086_0100, 0}; +#undef pci_ss_info_8086_0100 +#define pci_ss_info_8086_0100 pci_ss_info_8086_7800_8086_0100 +static const pciSubsystemInfo pci_ss_info_8086_8500_1993_0ded = + {0x1993, 0x0ded, pci_subsys_8086_8500_1993_0ded, 0}; +#undef pci_ss_info_1993_0ded +#define pci_ss_info_1993_0ded pci_ss_info_8086_8500_1993_0ded +static const pciSubsystemInfo pci_ss_info_8086_8500_1993_0dee = + {0x1993, 0x0dee, pci_subsys_8086_8500_1993_0dee, 0}; +#undef pci_ss_info_1993_0dee +#define pci_ss_info_1993_0dee pci_ss_info_8086_8500_1993_0dee +static const pciSubsystemInfo pci_ss_info_8086_8500_1993_0def = + {0x1993, 0x0def, pci_subsys_8086_8500_1993_0def, 0}; +#undef pci_ss_info_1993_0def +#define pci_ss_info_1993_0def pci_ss_info_8086_8500_1993_0def +static const pciSubsystemInfo pci_ss_info_8086_b555_12c7_5005 = + {0x12c7, 0x5005, pci_subsys_8086_b555_12c7_5005, 0}; +#undef pci_ss_info_12c7_5005 +#define pci_ss_info_12c7_5005 pci_ss_info_8086_b555_12c7_5005 +static const pciSubsystemInfo pci_ss_info_8086_b555_12c7_5006 = + {0x12c7, 0x5006, pci_subsys_8086_b555_12c7_5006, 0}; +#undef pci_ss_info_12c7_5006 +#define pci_ss_info_12c7_5006 pci_ss_info_8086_b555_12c7_5006 +static const pciSubsystemInfo pci_ss_info_8086_b555_12d9_000a = + {0x12d9, 0x000a, pci_subsys_8086_b555_12d9_000a, 0}; +#undef pci_ss_info_12d9_000a +#define pci_ss_info_12d9_000a pci_ss_info_8086_b555_12d9_000a +static const pciSubsystemInfo pci_ss_info_8086_b555_4c53_1050 = + {0x4c53, 0x1050, pci_subsys_8086_b555_4c53_1050, 0}; +#undef pci_ss_info_4c53_1050 +#define pci_ss_info_4c53_1050 pci_ss_info_8086_b555_4c53_1050 +static const pciSubsystemInfo pci_ss_info_8086_b555_4c53_1051 = + {0x4c53, 0x1051, pci_subsys_8086_b555_4c53_1051, 0}; +#undef pci_ss_info_4c53_1051 +#define pci_ss_info_4c53_1051 pci_ss_info_8086_b555_4c53_1051 +static const pciSubsystemInfo pci_ss_info_8086_b555_e4bf_1000 = + {0xe4bf, 0x1000, pci_subsys_8086_b555_e4bf_1000, 0}; +#undef pci_ss_info_e4bf_1000 +#define pci_ss_info_e4bf_1000 pci_ss_info_8086_b555_e4bf_1000 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9004_5078_9004_7850 = + {0x9004, 0x7850, pci_subsys_9004_5078_9004_7850, 0}; +#undef pci_ss_info_9004_7850 +#define pci_ss_info_9004_7850 pci_ss_info_9004_5078_9004_7850 +static const pciSubsystemInfo pci_ss_info_9004_5647_9004_7710 = + {0x9004, 0x7710, pci_subsys_9004_5647_9004_7710, 0}; +#undef pci_ss_info_9004_7710 +#define pci_ss_info_9004_7710 pci_ss_info_9004_5647_9004_7710 +static const pciSubsystemInfo pci_ss_info_9004_5647_9004_7711 = + {0x9004, 0x7711, pci_subsys_9004_5647_9004_7711, 0}; +#undef pci_ss_info_9004_7711 +#define pci_ss_info_9004_7711 pci_ss_info_9004_5647_9004_7711 +static const pciSubsystemInfo pci_ss_info_9004_6075_9004_7560 = + {0x9004, 0x7560, pci_subsys_9004_6075_9004_7560, 0}; +#undef pci_ss_info_9004_7560 +#define pci_ss_info_9004_7560 pci_ss_info_9004_6075_9004_7560 +static const pciSubsystemInfo pci_ss_info_9004_6178_9004_7861 = + {0x9004, 0x7861, pci_subsys_9004_6178_9004_7861, 0}; +#undef pci_ss_info_9004_7861 +#define pci_ss_info_9004_7861 pci_ss_info_9004_6178_9004_7861 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0008 = + {0x9004, 0x0008, pci_subsys_9004_6915_9004_0008, 0}; +#undef pci_ss_info_9004_0008 +#define pci_ss_info_9004_0008 pci_ss_info_9004_6915_9004_0008 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0009 = + {0x9004, 0x0009, pci_subsys_9004_6915_9004_0009, 0}; +#undef pci_ss_info_9004_0009 +#define pci_ss_info_9004_0009 pci_ss_info_9004_6915_9004_0009 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0010 = + {0x9004, 0x0010, pci_subsys_9004_6915_9004_0010, 0}; +#undef pci_ss_info_9004_0010 +#define pci_ss_info_9004_0010 pci_ss_info_9004_6915_9004_0010 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0018 = + {0x9004, 0x0018, pci_subsys_9004_6915_9004_0018, 0}; +#undef pci_ss_info_9004_0018 +#define pci_ss_info_9004_0018 pci_ss_info_9004_6915_9004_0018 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0019 = + {0x9004, 0x0019, pci_subsys_9004_6915_9004_0019, 0}; +#undef pci_ss_info_9004_0019 +#define pci_ss_info_9004_0019 pci_ss_info_9004_6915_9004_0019 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0020 = + {0x9004, 0x0020, pci_subsys_9004_6915_9004_0020, 0}; +#undef pci_ss_info_9004_0020 +#define pci_ss_info_9004_0020 pci_ss_info_9004_6915_9004_0020 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_0028 = + {0x9004, 0x0028, pci_subsys_9004_6915_9004_0028, 0}; +#undef pci_ss_info_9004_0028 +#define pci_ss_info_9004_0028 pci_ss_info_9004_6915_9004_0028 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8008 = + {0x9004, 0x8008, pci_subsys_9004_6915_9004_8008, 0}; +#undef pci_ss_info_9004_8008 +#define pci_ss_info_9004_8008 pci_ss_info_9004_6915_9004_8008 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8009 = + {0x9004, 0x8009, pci_subsys_9004_6915_9004_8009, 0}; +#undef pci_ss_info_9004_8009 +#define pci_ss_info_9004_8009 pci_ss_info_9004_6915_9004_8009 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8010 = + {0x9004, 0x8010, pci_subsys_9004_6915_9004_8010, 0}; +#undef pci_ss_info_9004_8010 +#define pci_ss_info_9004_8010 pci_ss_info_9004_6915_9004_8010 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8018 = + {0x9004, 0x8018, pci_subsys_9004_6915_9004_8018, 0}; +#undef pci_ss_info_9004_8018 +#define pci_ss_info_9004_8018 pci_ss_info_9004_6915_9004_8018 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8019 = + {0x9004, 0x8019, pci_subsys_9004_6915_9004_8019, 0}; +#undef pci_ss_info_9004_8019 +#define pci_ss_info_9004_8019 pci_ss_info_9004_6915_9004_8019 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8020 = + {0x9004, 0x8020, pci_subsys_9004_6915_9004_8020, 0}; +#undef pci_ss_info_9004_8020 +#define pci_ss_info_9004_8020 pci_ss_info_9004_6915_9004_8020 +static const pciSubsystemInfo pci_ss_info_9004_6915_9004_8028 = + {0x9004, 0x8028, pci_subsys_9004_6915_9004_8028, 0}; +#undef pci_ss_info_9004_8028 +#define pci_ss_info_9004_8028 pci_ss_info_9004_6915_9004_8028 +static const pciSubsystemInfo pci_ss_info_9004_7815_9004_7815 = + {0x9004, 0x7815, pci_subsys_9004_7815_9004_7815, 0}; +#undef pci_ss_info_9004_7815 +#define pci_ss_info_9004_7815 pci_ss_info_9004_7815_9004_7815 +static const pciSubsystemInfo pci_ss_info_9004_7815_9004_7840 = + {0x9004, 0x7840, pci_subsys_9004_7815_9004_7840, 0}; +#undef pci_ss_info_9004_7840 +#define pci_ss_info_9004_7840 pci_ss_info_9004_7815_9004_7840 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7890 = + {0x9004, 0x7890, pci_subsys_9004_7895_9004_7890, 0}; +#undef pci_ss_info_9004_7890 +#define pci_ss_info_9004_7890 pci_ss_info_9004_7895_9004_7890 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7891 = + {0x9004, 0x7891, pci_subsys_9004_7895_9004_7891, 0}; +#undef pci_ss_info_9004_7891 +#define pci_ss_info_9004_7891 pci_ss_info_9004_7895_9004_7891 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7892 = + {0x9004, 0x7892, pci_subsys_9004_7895_9004_7892, 0}; +#undef pci_ss_info_9004_7892 +#define pci_ss_info_9004_7892 pci_ss_info_9004_7895_9004_7892 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7894 = + {0x9004, 0x7894, pci_subsys_9004_7895_9004_7894, 0}; +#undef pci_ss_info_9004_7894 +#define pci_ss_info_9004_7894 pci_ss_info_9004_7895_9004_7894 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7895 = + {0x9004, 0x7895, pci_subsys_9004_7895_9004_7895, 0}; +#undef pci_ss_info_9004_7895 +#define pci_ss_info_9004_7895 pci_ss_info_9004_7895_9004_7895 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7896 = + {0x9004, 0x7896, pci_subsys_9004_7895_9004_7896, 0}; +#undef pci_ss_info_9004_7896 +#define pci_ss_info_9004_7896 pci_ss_info_9004_7895_9004_7896 +static const pciSubsystemInfo pci_ss_info_9004_7895_9004_7897 = + {0x9004, 0x7897, pci_subsys_9004_7895_9004_7897, 0}; +#undef pci_ss_info_9004_7897 +#define pci_ss_info_9004_7897 pci_ss_info_9004_7895_9004_7897 +static const pciSubsystemInfo pci_ss_info_9004_8078_9004_7880 = + {0x9004, 0x7880, pci_subsys_9004_8078_9004_7880, 0}; +#undef pci_ss_info_9004_7880 +#define pci_ss_info_9004_7880 pci_ss_info_9004_8078_9004_7880 +static const pciSubsystemInfo pci_ss_info_9004_8178_9004_7881 = + {0x9004, 0x7881, pci_subsys_9004_8178_9004_7881, 0}; +#undef pci_ss_info_9004_7881 +#define pci_ss_info_9004_7881 pci_ss_info_9004_8178_9004_7881 +static const pciSubsystemInfo pci_ss_info_9004_8778_9004_7887 = + {0x9004, 0x7887, pci_subsys_9004_8778_9004_7887, 0}; +#undef pci_ss_info_9004_7887 +#define pci_ss_info_9004_7887 pci_ss_info_9004_8778_9004_7887 +static const pciSubsystemInfo pci_ss_info_9004_8878_9004_7888 = + {0x9004, 0x7888, pci_subsys_9004_8878_9004_7888, 0}; +#undef pci_ss_info_9004_7888 +#define pci_ss_info_9004_7888 pci_ss_info_9004_8878_9004_7888 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9005_0010_9005_2180 = + {0x9005, 0x2180, pci_subsys_9005_0010_9005_2180, 0}; +#undef pci_ss_info_9005_2180 +#define pci_ss_info_9005_2180 pci_ss_info_9005_0010_9005_2180 +static const pciSubsystemInfo pci_ss_info_9005_0010_9005_8100 = + {0x9005, 0x8100, pci_subsys_9005_0010_9005_8100, 0}; +#undef pci_ss_info_9005_8100 +#define pci_ss_info_9005_8100 pci_ss_info_9005_0010_9005_8100 +static const pciSubsystemInfo pci_ss_info_9005_0010_9005_a100 = + {0x9005, 0xa100, pci_subsys_9005_0010_9005_a100, 0}; +#undef pci_ss_info_9005_a100 +#define pci_ss_info_9005_a100 pci_ss_info_9005_0010_9005_a100 +static const pciSubsystemInfo pci_ss_info_9005_0010_9005_a180 = + {0x9005, 0xa180, pci_subsys_9005_0010_9005_a180, 0}; +#undef pci_ss_info_9005_a180 +#define pci_ss_info_9005_a180 pci_ss_info_9005_0010_9005_a180 +static const pciSubsystemInfo pci_ss_info_9005_0010_9005_e100 = + {0x9005, 0xe100, pci_subsys_9005_0010_9005_e100, 0}; +#undef pci_ss_info_9005_e100 +#define pci_ss_info_9005_e100 pci_ss_info_9005_0010_9005_e100 +static const pciSubsystemInfo pci_ss_info_9005_0013_9005_0003 = + {0x9005, 0x0003, pci_subsys_9005_0013_9005_0003, 0}; +#undef pci_ss_info_9005_0003 +#define pci_ss_info_9005_0003 pci_ss_info_9005_0013_9005_0003 +static const pciSubsystemInfo pci_ss_info_9005_0013_9005_000f = + {0x9005, 0x000f, pci_subsys_9005_0013_9005_000f, 0}; +#undef pci_ss_info_9005_000f +#define pci_ss_info_9005_000f pci_ss_info_9005_0013_9005_000f +static const pciSubsystemInfo pci_ss_info_9005_001f_9005_000f = + {0x9005, 0x000f, pci_subsys_9005_001f_9005_000f, 0}; +#undef pci_ss_info_9005_000f +#define pci_ss_info_9005_000f pci_ss_info_9005_001f_9005_000f +static const pciSubsystemInfo pci_ss_info_9005_001f_9005_a180 = + {0x9005, 0xa180, pci_subsys_9005_001f_9005_a180, 0}; +#undef pci_ss_info_9005_a180 +#define pci_ss_info_9005_a180 pci_ss_info_9005_001f_9005_a180 +static const pciSubsystemInfo pci_ss_info_9005_0050_9005_f500 = + {0x9005, 0xf500, pci_subsys_9005_0050_9005_f500, 0}; +#undef pci_ss_info_9005_f500 +#define pci_ss_info_9005_f500 pci_ss_info_9005_0050_9005_f500 +static const pciSubsystemInfo pci_ss_info_9005_0050_9005_ffff = + {0x9005, 0xffff, pci_subsys_9005_0050_9005_ffff, 0}; +#undef pci_ss_info_9005_ffff +#define pci_ss_info_9005_ffff pci_ss_info_9005_0050_9005_ffff +static const pciSubsystemInfo pci_ss_info_9005_0051_9005_b500 = + {0x9005, 0xb500, pci_subsys_9005_0051_9005_b500, 0}; +#undef pci_ss_info_9005_b500 +#define pci_ss_info_9005_b500 pci_ss_info_9005_0051_9005_b500 +static const pciSubsystemInfo pci_ss_info_9005_0053_9005_ffff = + {0x9005, 0xffff, pci_subsys_9005_0053_9005_ffff, 0}; +#undef pci_ss_info_9005_ffff +#define pci_ss_info_9005_ffff pci_ss_info_9005_0053_9005_ffff +#endif +static const pciSubsystemInfo pci_ss_info_9005_0080_0e11_e2a0 = + {0x0e11, 0xe2a0, pci_subsys_9005_0080_0e11_e2a0, 0}; +#undef pci_ss_info_0e11_e2a0 +#define pci_ss_info_0e11_e2a0 pci_ss_info_9005_0080_0e11_e2a0 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9005_0080_9005_6220 = + {0x9005, 0x6220, pci_subsys_9005_0080_9005_6220, 0}; +#undef pci_ss_info_9005_6220 +#define pci_ss_info_9005_6220 pci_ss_info_9005_0080_9005_6220 +static const pciSubsystemInfo pci_ss_info_9005_0080_9005_62a0 = + {0x9005, 0x62a0, pci_subsys_9005_0080_9005_62a0, 0}; +#undef pci_ss_info_9005_62a0 +#define pci_ss_info_9005_62a0 pci_ss_info_9005_0080_9005_62a0 +static const pciSubsystemInfo pci_ss_info_9005_0080_9005_e220 = + {0x9005, 0xe220, pci_subsys_9005_0080_9005_e220, 0}; +#undef pci_ss_info_9005_e220 +#define pci_ss_info_9005_e220 pci_ss_info_9005_0080_9005_e220 +static const pciSubsystemInfo pci_ss_info_9005_0080_9005_e2a0 = + {0x9005, 0xe2a0, pci_subsys_9005_0080_9005_e2a0, 0}; +#undef pci_ss_info_9005_e2a0 +#define pci_ss_info_9005_e2a0 pci_ss_info_9005_0080_9005_e2a0 +static const pciSubsystemInfo pci_ss_info_9005_0081_9005_62a1 = + {0x9005, 0x62a1, pci_subsys_9005_0081_9005_62a1, 0}; +#undef pci_ss_info_9005_62a1 +#define pci_ss_info_9005_62a1 pci_ss_info_9005_0081_9005_62a1 +static const pciSubsystemInfo pci_ss_info_9005_008f_1179_0001 = + {0x1179, 0x0001, pci_subsys_9005_008f_1179_0001, 0}; +#undef pci_ss_info_1179_0001 +#define pci_ss_info_1179_0001 pci_ss_info_9005_008f_1179_0001 +static const pciSubsystemInfo pci_ss_info_9005_008f_15d9_9005 = + {0x15d9, 0x9005, pci_subsys_9005_008f_15d9_9005, 0}; +#undef pci_ss_info_15d9_9005 +#define pci_ss_info_15d9_9005 pci_ss_info_9005_008f_15d9_9005 +#endif +static const pciSubsystemInfo pci_ss_info_9005_00c0_0e11_f620 = + {0x0e11, 0xf620, pci_subsys_9005_00c0_0e11_f620, 0}; +#undef pci_ss_info_0e11_f620 +#define pci_ss_info_0e11_f620 pci_ss_info_9005_00c0_0e11_f620 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9005_00c0_9005_f620 = + {0x9005, 0xf620, pci_subsys_9005_00c0_9005_f620, 0}; +#undef pci_ss_info_9005_f620 +#define pci_ss_info_9005_f620 pci_ss_info_9005_00c0_9005_f620 +#endif +static const pciSubsystemInfo pci_ss_info_9005_00c5_1028_00c5 = + {0x1028, 0x00c5, pci_subsys_9005_00c5_1028_00c5, 0}; +#undef pci_ss_info_1028_00c5 +#define pci_ss_info_1028_00c5 pci_ss_info_9005_00c5_1028_00c5 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_9005_00cf_1028_00ce = + {0x1028, 0x00ce, pci_subsys_9005_00cf_1028_00ce, 0}; +#undef pci_ss_info_1028_00ce +#define pci_ss_info_1028_00ce pci_ss_info_9005_00cf_1028_00ce +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_9005_00cf_1028_00d1 = + {0x1028, 0x00d1, pci_subsys_9005_00cf_1028_00d1, 0}; +#undef pci_ss_info_1028_00d1 +#define pci_ss_info_1028_00d1 pci_ss_info_9005_00cf_1028_00d1 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_9005_00cf_1028_00d9 = + {0x1028, 0x00d9, pci_subsys_9005_00cf_1028_00d9, 0}; +#undef pci_ss_info_1028_00d9 +#define pci_ss_info_1028_00d9 pci_ss_info_9005_00cf_1028_00d9 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9005_00cf_10f1_2462 = + {0x10f1, 0x2462, pci_subsys_9005_00cf_10f1_2462, 0}; +#undef pci_ss_info_10f1_2462 +#define pci_ss_info_10f1_2462 pci_ss_info_9005_00cf_10f1_2462 +static const pciSubsystemInfo pci_ss_info_9005_00cf_15d9_9005 = + {0x15d9, 0x9005, pci_subsys_9005_00cf_15d9_9005, 0}; +#undef pci_ss_info_15d9_9005 +#define pci_ss_info_15d9_9005 pci_ss_info_9005_00cf_15d9_9005 +#endif +static const pciSubsystemInfo pci_ss_info_9005_00cf_8086_3411 = + {0x8086, 0x3411, pci_subsys_9005_00cf_8086_3411, 0}; +#undef pci_ss_info_8086_3411 +#define pci_ss_info_8086_3411 pci_ss_info_9005_00cf_8086_3411 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9005_0250_1014_0279 = + {0x1014, 0x0279, pci_subsys_9005_0250_1014_0279, 0}; +#undef pci_ss_info_1014_0279 +#define pci_ss_info_1014_0279 pci_ss_info_9005_0250_1014_0279 +static const pciSubsystemInfo pci_ss_info_9005_0250_1014_028c = + {0x1014, 0x028c, pci_subsys_9005_0250_1014_028c, 0}; +#undef pci_ss_info_1014_028c +#define pci_ss_info_1014_028c pci_ss_info_9005_0250_1014_028c +static const pciSubsystemInfo pci_ss_info_9005_0283_9005_0283 = + {0x9005, 0x0283, pci_subsys_9005_0283_9005_0283, 0}; +#undef pci_ss_info_9005_0283 +#define pci_ss_info_9005_0283 pci_ss_info_9005_0283_9005_0283 +static const pciSubsystemInfo pci_ss_info_9005_0284_9005_0284 = + {0x9005, 0x0284, pci_subsys_9005_0284_9005_0284, 0}; +#undef pci_ss_info_9005_0284 +#define pci_ss_info_9005_0284 pci_ss_info_9005_0284_9005_0284 +#endif +static const pciSubsystemInfo pci_ss_info_9005_0285_0e11_0295 = + {0x0e11, 0x0295, pci_subsys_9005_0285_0e11_0295, 0}; +#undef pci_ss_info_0e11_0295 +#define pci_ss_info_0e11_0295 pci_ss_info_9005_0285_0e11_0295 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9005_0285_1014_02f2 = + {0x1014, 0x02f2, pci_subsys_9005_0285_1014_02f2, 0}; +#undef pci_ss_info_1014_02f2 +#define pci_ss_info_1014_02f2 pci_ss_info_9005_0285_1014_02f2 +#endif +static const pciSubsystemInfo pci_ss_info_9005_0285_1028_0287 = + {0x1028, 0x0287, pci_subsys_9005_0285_1028_0287, 0}; +#undef pci_ss_info_1028_0287 +#define pci_ss_info_1028_0287 pci_ss_info_9005_0285_1028_0287 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_9005_0285_1028_0291 = + {0x1028, 0x0291, pci_subsys_9005_0285_1028_0291, 0}; +#undef pci_ss_info_1028_0291 +#define pci_ss_info_1028_0291 pci_ss_info_9005_0285_1028_0291 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +static const pciSubsystemInfo pci_ss_info_9005_0285_103c_3227 = + {0x103c, 0x3227, pci_subsys_9005_0285_103c_3227, 0}; +#undef pci_ss_info_103c_3227 +#define pci_ss_info_103c_3227 pci_ss_info_9005_0285_103c_3227 +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9005_0285_17aa_0286 = + {0x17aa, 0x0286, pci_subsys_9005_0285_17aa_0286, 0}; +#undef pci_ss_info_17aa_0286 +#define pci_ss_info_17aa_0286 pci_ss_info_9005_0285_17aa_0286 +static const pciSubsystemInfo pci_ss_info_9005_0285_17aa_0287 = + {0x17aa, 0x0287, pci_subsys_9005_0285_17aa_0287, 0}; +#undef pci_ss_info_17aa_0287 +#define pci_ss_info_17aa_0287 pci_ss_info_9005_0285_17aa_0287 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0285 = + {0x9005, 0x0285, pci_subsys_9005_0285_9005_0285, 0}; +#undef pci_ss_info_9005_0285 +#define pci_ss_info_9005_0285 pci_ss_info_9005_0285_9005_0285 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0286 = + {0x9005, 0x0286, pci_subsys_9005_0285_9005_0286, 0}; +#undef pci_ss_info_9005_0286 +#define pci_ss_info_9005_0286 pci_ss_info_9005_0285_9005_0286 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0287 = + {0x9005, 0x0287, pci_subsys_9005_0285_9005_0287, 0}; +#undef pci_ss_info_9005_0287 +#define pci_ss_info_9005_0287 pci_ss_info_9005_0285_9005_0287 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0288 = + {0x9005, 0x0288, pci_subsys_9005_0285_9005_0288, 0}; +#undef pci_ss_info_9005_0288 +#define pci_ss_info_9005_0288 pci_ss_info_9005_0285_9005_0288 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0289 = + {0x9005, 0x0289, pci_subsys_9005_0285_9005_0289, 0}; +#undef pci_ss_info_9005_0289 +#define pci_ss_info_9005_0289 pci_ss_info_9005_0285_9005_0289 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_028a = + {0x9005, 0x028a, pci_subsys_9005_0285_9005_028a, 0}; +#undef pci_ss_info_9005_028a +#define pci_ss_info_9005_028a pci_ss_info_9005_0285_9005_028a +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_028b = + {0x9005, 0x028b, pci_subsys_9005_0285_9005_028b, 0}; +#undef pci_ss_info_9005_028b +#define pci_ss_info_9005_028b pci_ss_info_9005_0285_9005_028b +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_028e = + {0x9005, 0x028e, pci_subsys_9005_0285_9005_028e, 0}; +#undef pci_ss_info_9005_028e +#define pci_ss_info_9005_028e pci_ss_info_9005_0285_9005_028e +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_028f = + {0x9005, 0x028f, pci_subsys_9005_0285_9005_028f, 0}; +#undef pci_ss_info_9005_028f +#define pci_ss_info_9005_028f pci_ss_info_9005_0285_9005_028f +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0290 = + {0x9005, 0x0290, pci_subsys_9005_0285_9005_0290, 0}; +#undef pci_ss_info_9005_0290 +#define pci_ss_info_9005_0290 pci_ss_info_9005_0285_9005_0290 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0292 = + {0x9005, 0x0292, pci_subsys_9005_0285_9005_0292, 0}; +#undef pci_ss_info_9005_0292 +#define pci_ss_info_9005_0292 pci_ss_info_9005_0285_9005_0292 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0293 = + {0x9005, 0x0293, pci_subsys_9005_0285_9005_0293, 0}; +#undef pci_ss_info_9005_0293 +#define pci_ss_info_9005_0293 pci_ss_info_9005_0285_9005_0293 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0294 = + {0x9005, 0x0294, pci_subsys_9005_0285_9005_0294, 0}; +#undef pci_ss_info_9005_0294 +#define pci_ss_info_9005_0294 pci_ss_info_9005_0285_9005_0294 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0296 = + {0x9005, 0x0296, pci_subsys_9005_0285_9005_0296, 0}; +#undef pci_ss_info_9005_0296 +#define pci_ss_info_9005_0296 pci_ss_info_9005_0285_9005_0296 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0297 = + {0x9005, 0x0297, pci_subsys_9005_0285_9005_0297, 0}; +#undef pci_ss_info_9005_0297 +#define pci_ss_info_9005_0297 pci_ss_info_9005_0285_9005_0297 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0298 = + {0x9005, 0x0298, pci_subsys_9005_0285_9005_0298, 0}; +#undef pci_ss_info_9005_0298 +#define pci_ss_info_9005_0298 pci_ss_info_9005_0285_9005_0298 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_0299 = + {0x9005, 0x0299, pci_subsys_9005_0285_9005_0299, 0}; +#undef pci_ss_info_9005_0299 +#define pci_ss_info_9005_0299 pci_ss_info_9005_0285_9005_0299 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_029a = + {0x9005, 0x029a, pci_subsys_9005_0285_9005_029a, 0}; +#undef pci_ss_info_9005_029a +#define pci_ss_info_9005_029a pci_ss_info_9005_0285_9005_029a +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_02b5 = + {0x9005, 0x02b5, pci_subsys_9005_0285_9005_02b5, 0}; +#undef pci_ss_info_9005_02b5 +#define pci_ss_info_9005_02b5 pci_ss_info_9005_0285_9005_02b5 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_02b6 = + {0x9005, 0x02b6, pci_subsys_9005_0285_9005_02b6, 0}; +#undef pci_ss_info_9005_02b6 +#define pci_ss_info_9005_02b6 pci_ss_info_9005_0285_9005_02b6 +static const pciSubsystemInfo pci_ss_info_9005_0285_9005_02b7 = + {0x9005, 0x02b7, pci_subsys_9005_0285_9005_02b7, 0}; +#undef pci_ss_info_9005_02b7 +#define pci_ss_info_9005_02b7 pci_ss_info_9005_0285_9005_02b7 +static const pciSubsystemInfo pci_ss_info_9005_0286_1014_034d = + {0x1014, 0x034d, pci_subsys_9005_0286_1014_034d, 0}; +#undef pci_ss_info_1014_034d +#define pci_ss_info_1014_034d pci_ss_info_9005_0286_1014_034d +static const pciSubsystemInfo pci_ss_info_9005_0286_1014_9540 = + {0x1014, 0x9540, pci_subsys_9005_0286_1014_9540, 0}; +#undef pci_ss_info_1014_9540 +#define pci_ss_info_1014_9540 pci_ss_info_9005_0286_1014_9540 +static const pciSubsystemInfo pci_ss_info_9005_0286_1014_9580 = + {0x1014, 0x9580, pci_subsys_9005_0286_1014_9580, 0}; +#undef pci_ss_info_1014_9580 +#define pci_ss_info_1014_9580 pci_ss_info_9005_0286_1014_9580 +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_028c = + {0x9005, 0x028c, pci_subsys_9005_0286_9005_028c, 0}; +#undef pci_ss_info_9005_028c +#define pci_ss_info_9005_028c pci_ss_info_9005_0286_9005_028c +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_028d = + {0x9005, 0x028d, pci_subsys_9005_0286_9005_028d, 0}; +#undef pci_ss_info_9005_028d +#define pci_ss_info_9005_028d pci_ss_info_9005_0286_9005_028d +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_029b = + {0x9005, 0x029b, pci_subsys_9005_0286_9005_029b, 0}; +#undef pci_ss_info_9005_029b +#define pci_ss_info_9005_029b pci_ss_info_9005_0286_9005_029b +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_029c = + {0x9005, 0x029c, pci_subsys_9005_0286_9005_029c, 0}; +#undef pci_ss_info_9005_029c +#define pci_ss_info_9005_029c pci_ss_info_9005_0286_9005_029c +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_029d = + {0x9005, 0x029d, pci_subsys_9005_0286_9005_029d, 0}; +#undef pci_ss_info_9005_029d +#define pci_ss_info_9005_029d pci_ss_info_9005_0286_9005_029d +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_029e = + {0x9005, 0x029e, pci_subsys_9005_0286_9005_029e, 0}; +#undef pci_ss_info_9005_029e +#define pci_ss_info_9005_029e pci_ss_info_9005_0286_9005_029e +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_029f = + {0x9005, 0x029f, pci_subsys_9005_0286_9005_029f, 0}; +#undef pci_ss_info_9005_029f +#define pci_ss_info_9005_029f pci_ss_info_9005_0286_9005_029f +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_02a0 = + {0x9005, 0x02a0, pci_subsys_9005_0286_9005_02a0, 0}; +#undef pci_ss_info_9005_02a0 +#define pci_ss_info_9005_02a0 pci_ss_info_9005_0286_9005_02a0 +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_02a1 = + {0x9005, 0x02a1, pci_subsys_9005_0286_9005_02a1, 0}; +#undef pci_ss_info_9005_02a1 +#define pci_ss_info_9005_02a1 pci_ss_info_9005_0286_9005_02a1 +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_02a2 = + {0x9005, 0x02a2, pci_subsys_9005_0286_9005_02a2, 0}; +#undef pci_ss_info_9005_02a2 +#define pci_ss_info_9005_02a2 pci_ss_info_9005_0286_9005_02a2 +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_02a3 = + {0x9005, 0x02a3, pci_subsys_9005_0286_9005_02a3, 0}; +#undef pci_ss_info_9005_02a3 +#define pci_ss_info_9005_02a3 pci_ss_info_9005_0286_9005_02a3 +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_02a4 = + {0x9005, 0x02a4, pci_subsys_9005_0286_9005_02a4, 0}; +#undef pci_ss_info_9005_02a4 +#define pci_ss_info_9005_02a4 pci_ss_info_9005_0286_9005_02a4 +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_02a5 = + {0x9005, 0x02a5, pci_subsys_9005_0286_9005_02a5, 0}; +#undef pci_ss_info_9005_02a5 +#define pci_ss_info_9005_02a5 pci_ss_info_9005_0286_9005_02a5 +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_02a6 = + {0x9005, 0x02a6, pci_subsys_9005_0286_9005_02a6, 0}; +#undef pci_ss_info_9005_02a6 +#define pci_ss_info_9005_02a6 pci_ss_info_9005_0286_9005_02a6 +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_02a7 = + {0x9005, 0x02a7, pci_subsys_9005_0286_9005_02a7, 0}; +#undef pci_ss_info_9005_02a7 +#define pci_ss_info_9005_02a7 pci_ss_info_9005_0286_9005_02a7 +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_02a8 = + {0x9005, 0x02a8, pci_subsys_9005_0286_9005_02a8, 0}; +#undef pci_ss_info_9005_02a8 +#define pci_ss_info_9005_02a8 pci_ss_info_9005_0286_9005_02a8 +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_02a9 = + {0x9005, 0x02a9, pci_subsys_9005_0286_9005_02a9, 0}; +#undef pci_ss_info_9005_02a9 +#define pci_ss_info_9005_02a9 pci_ss_info_9005_0286_9005_02a9 +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_02aa = + {0x9005, 0x02aa, pci_subsys_9005_0286_9005_02aa, 0}; +#undef pci_ss_info_9005_02aa +#define pci_ss_info_9005_02aa pci_ss_info_9005_0286_9005_02aa +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_02ac = + {0x9005, 0x02ac, pci_subsys_9005_0286_9005_02ac, 0}; +#undef pci_ss_info_9005_02ac +#define pci_ss_info_9005_02ac pci_ss_info_9005_0286_9005_02ac +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_02b3 = + {0x9005, 0x02b3, pci_subsys_9005_0286_9005_02b3, 0}; +#undef pci_ss_info_9005_02b3 +#define pci_ss_info_9005_02b3 pci_ss_info_9005_0286_9005_02b3 +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_02b4 = + {0x9005, 0x02b4, pci_subsys_9005_0286_9005_02b4, 0}; +#undef pci_ss_info_9005_02b4 +#define pci_ss_info_9005_02b4 pci_ss_info_9005_0286_9005_02b4 +static const pciSubsystemInfo pci_ss_info_9005_0286_9005_0800 = + {0x9005, 0x0800, pci_subsys_9005_0286_9005_0800, 0}; +#undef pci_ss_info_9005_0800 +#define pci_ss_info_9005_0800 pci_ss_info_9005_0286_9005_0800 +static const pciSubsystemInfo pci_ss_info_9005_0410_9005_0410 = + {0x9005, 0x0410, pci_subsys_9005_0410_9005_0410, 0}; +#undef pci_ss_info_9005_0410 +#define pci_ss_info_9005_0410 pci_ss_info_9005_0410_9005_0410 +static const pciSubsystemInfo pci_ss_info_9005_0410_9005_0411 = + {0x9005, 0x0411, pci_subsys_9005_0410_9005_0411, 0}; +#undef pci_ss_info_9005_0411 +#define pci_ss_info_9005_0411 pci_ss_info_9005_0410_9005_0411 +static const pciSubsystemInfo pci_ss_info_9005_0412_9005_0412 = + {0x9005, 0x0412, pci_subsys_9005_0412_9005_0412, 0}; +#undef pci_ss_info_9005_0412 +#define pci_ss_info_9005_0412 pci_ss_info_9005_0412_9005_0412 +static const pciSubsystemInfo pci_ss_info_9005_0412_9005_0413 = + {0x9005, 0x0413, pci_subsys_9005_0412_9005_0413, 0}; +#undef pci_ss_info_9005_0413 +#define pci_ss_info_9005_0413 pci_ss_info_9005_0412_9005_0413 +static const pciSubsystemInfo pci_ss_info_9005_041f_9005_041f = + {0x9005, 0x041f, pci_subsys_9005_041f_9005_041f, 0}; +#undef pci_ss_info_9005_041f +#define pci_ss_info_9005_041f pci_ss_info_9005_041f_9005_041f +static const pciSubsystemInfo pci_ss_info_9005_0430_9005_0430 = + {0x9005, 0x0430, pci_subsys_9005_0430_9005_0430, 0}; +#undef pci_ss_info_9005_0430 +#define pci_ss_info_9005_0430 pci_ss_info_9005_0430_9005_0430 +static const pciSubsystemInfo pci_ss_info_9005_0432_9005_0432 = + {0x9005, 0x0432, pci_subsys_9005_0432_9005_0432, 0}; +#undef pci_ss_info_9005_0432 +#define pci_ss_info_9005_0432 pci_ss_info_9005_0432_9005_0432 +static const pciSubsystemInfo pci_ss_info_9005_0500_1014_02c1 = + {0x1014, 0x02c1, pci_subsys_9005_0500_1014_02c1, 0}; +#undef pci_ss_info_1014_02c1 +#define pci_ss_info_1014_02c1 pci_ss_info_9005_0500_1014_02c1 +static const pciSubsystemInfo pci_ss_info_9005_0500_1014_02c2 = + {0x1014, 0x02c2, pci_subsys_9005_0500_1014_02c2, 0}; +#undef pci_ss_info_1014_02c2 +#define pci_ss_info_1014_02c2 pci_ss_info_9005_0500_1014_02c2 +static const pciSubsystemInfo pci_ss_info_9005_0503_1014_02bf = + {0x1014, 0x02bf, pci_subsys_9005_0503_1014_02bf, 0}; +#undef pci_ss_info_1014_02bf +#define pci_ss_info_1014_02bf pci_ss_info_9005_0503_1014_02bf +static const pciSubsystemInfo pci_ss_info_9005_0503_1014_02d5 = + {0x1014, 0x02d5, pci_subsys_9005_0503_1014_02d5, 0}; +#undef pci_ss_info_1014_02d5 +#define pci_ss_info_1014_02d5 pci_ss_info_9005_0503_1014_02d5 +#endif +static const pciSubsystemInfo pci_ss_info_9005_8011_0e11_00ac = + {0x0e11, 0x00ac, pci_subsys_9005_8011_0e11_00ac, 0}; +#undef pci_ss_info_0e11_00ac +#define pci_ss_info_0e11_00ac pci_ss_info_9005_8011_0e11_00ac +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9005_8011_9005_0041 = + {0x9005, 0x0041, pci_subsys_9005_8011_9005_0041, 0}; +#undef pci_ss_info_9005_0041 +#define pci_ss_info_9005_0041 pci_ss_info_9005_8011_9005_0041 +static const pciSubsystemInfo pci_ss_info_9005_801f_1734_1011 = + {0x1734, 0x1011, pci_subsys_9005_801f_1734_1011, 0}; +#undef pci_ss_info_1734_1011 +#define pci_ss_info_1734_1011 pci_ss_info_9005_801f_1734_1011 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_9710_9815_1000_0020 = + {0x1000, 0x0020, pci_subsys_9710_9815_1000_0020, 0}; +#undef pci_ss_info_1000_0020 +#define pci_ss_info_1000_0020 pci_ss_info_9710_9815_1000_0020 +static const pciSubsystemInfo pci_ss_info_9710_9835_1000_0002 = + {0x1000, 0x0002, pci_subsys_9710_9835_1000_0002, 0}; +#undef pci_ss_info_1000_0002 +#define pci_ss_info_1000_0002 pci_ss_info_9710_9835_1000_0002 +static const pciSubsystemInfo pci_ss_info_9710_9835_1000_0012 = + {0x1000, 0x0012, pci_subsys_9710_9835_1000_0012, 0}; +#undef pci_ss_info_1000_0012 +#define pci_ss_info_1000_0012 pci_ss_info_9710_9835_1000_0012 +static const pciSubsystemInfo pci_ss_info_9710_9845_1000_0004 = + {0x1000, 0x0004, pci_subsys_9710_9845_1000_0004, 0}; +#undef pci_ss_info_1000_0004 +#define pci_ss_info_1000_0004 pci_ss_info_9710_9845_1000_0004 +static const pciSubsystemInfo pci_ss_info_9710_9845_1000_0006 = + {0x1000, 0x0006, pci_subsys_9710_9845_1000_0006, 0}; +#undef pci_ss_info_1000_0006 +#define pci_ss_info_1000_0006 pci_ss_info_9710_9845_1000_0006 +static const pciSubsystemInfo pci_ss_info_9710_9855_1000_0014 = + {0x1000, 0x0014, pci_subsys_9710_9855_1000_0014, 0}; +#undef pci_ss_info_1000_0014 +#define pci_ss_info_1000_0014 pci_ss_info_9710_9855_1000_0014 +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo pci_ss_info_e159_0001_0059_0001 = + {0x0059, 0x0001, pci_subsys_e159_0001_0059_0001, 0}; +#undef pci_ss_info_0059_0001 +#define pci_ss_info_0059_0001 pci_ss_info_e159_0001_0059_0001 +static const pciSubsystemInfo pci_ss_info_e159_0001_0059_0003 = + {0x0059, 0x0003, pci_subsys_e159_0001_0059_0003, 0}; +#undef pci_ss_info_0059_0003 +#define pci_ss_info_0059_0003 pci_ss_info_e159_0001_0059_0003 +static const pciSubsystemInfo pci_ss_info_e159_0001_00a7_0001 = + {0x00a7, 0x0001, pci_subsys_e159_0001_00a7_0001, 0}; +#undef pci_ss_info_00a7_0001 +#define pci_ss_info_00a7_0001 pci_ss_info_e159_0001_00a7_0001 +#endif +static const pciSubsystemInfo pci_ss_info_e159_0001_8086_0003 = + {0x8086, 0x0003, pci_subsys_e159_0001_8086_0003, 0}; +#undef pci_ss_info_8086_0003 +#define pci_ss_info_8086_0003 pci_ss_info_e159_0001_8086_0003 +#ifdef VENDOR_INCLUDE_NONVIDEO +#endif +#define pci_ss_list_0095_0680 NULL +#define pci_ss_list_018a_0106 NULL +#define pci_ss_list_021b_8139 NULL +#define pci_ss_list_0291_8212 NULL +#define pci_ss_list_02ac_1012 NULL +#define pci_ss_list_0357_000a NULL +#define pci_ss_list_0432_0001 NULL +#define pci_ss_list_045e_006e NULL +#define pci_ss_list_045e_00c2 NULL +#define pci_ss_list_04cf_8818 NULL +#define pci_ss_list_050d_001a NULL +#define pci_ss_list_050d_0109 NULL +#define pci_ss_list_050d_7050 NULL +#define pci_ss_list_05a9_8519 NULL +#define pci_ss_list_05e3_0701 NULL +#define pci_ss_list_066f_3410 NULL +#define pci_ss_list_066f_3500 NULL +#define pci_ss_list_0675_1700 NULL +#define pci_ss_list_0675_1702 NULL +#define pci_ss_list_0675_1703 NULL +#define pci_ss_list_0675_1704 NULL +#define pci_ss_list_067b_2303 NULL +#define pci_ss_list_067b_3507 NULL +#define pci_ss_list_09c1_0704 NULL +#define pci_ss_list_0b0b_0105 NULL +#define pci_ss_list_0b0b_0205 NULL +#define pci_ss_list_0b0b_0305 NULL +#define pci_ss_list_0b0b_0405 NULL +#define pci_ss_list_0b0b_0505 NULL +#define pci_ss_list_0b0b_0506 NULL +#define pci_ss_list_0b0b_0605 NULL +#define pci_ss_list_0b0b_0705 NULL +#define pci_ss_list_0b49_064f NULL +#define pci_ss_list_0ccd_0038 NULL +#define pci_ss_list_0e11_0001 NULL +#define pci_ss_list_0e11_0002 NULL +static const pciSubsystemInfo *pci_ss_list_0e11_0046[] = { + &pci_ss_info_0e11_0046_0e11_409a, + &pci_ss_info_0e11_0046_0e11_409b, + &pci_ss_info_0e11_0046_0e11_409c, + &pci_ss_info_0e11_0046_0e11_409d, + NULL +}; +#define pci_ss_list_0e11_0049 NULL +#define pci_ss_list_0e11_004a NULL +#define pci_ss_list_0e11_005a NULL +#define pci_ss_list_0e11_007c NULL +#define pci_ss_list_0e11_007d NULL +#define pci_ss_list_0e11_0085 NULL +#define pci_ss_list_0e11_00b1 NULL +#define pci_ss_list_0e11_00bb NULL +#define pci_ss_list_0e11_00ca NULL +#define pci_ss_list_0e11_00cb NULL +#define pci_ss_list_0e11_00cf NULL +#define pci_ss_list_0e11_00d0 NULL +#define pci_ss_list_0e11_00d1 NULL +#define pci_ss_list_0e11_00e3 NULL +#define pci_ss_list_0e11_0508 NULL +#define pci_ss_list_0e11_1000 NULL +#define pci_ss_list_0e11_2000 NULL +#define pci_ss_list_0e11_3032 NULL +#define pci_ss_list_0e11_3033 NULL +#define pci_ss_list_0e11_3034 NULL +#define pci_ss_list_0e11_4000 NULL +#define pci_ss_list_0e11_4030 NULL +#define pci_ss_list_0e11_4031 NULL +#define pci_ss_list_0e11_4032 NULL +#define pci_ss_list_0e11_4033 NULL +#define pci_ss_list_0e11_4034 NULL +#define pci_ss_list_0e11_4040 NULL +#define pci_ss_list_0e11_4048 NULL +#define pci_ss_list_0e11_4050 NULL +#define pci_ss_list_0e11_4051 NULL +#define pci_ss_list_0e11_4058 NULL +#define pci_ss_list_0e11_4070 NULL +#define pci_ss_list_0e11_4080 NULL +#define pci_ss_list_0e11_4082 NULL +#define pci_ss_list_0e11_4083 NULL +#define pci_ss_list_0e11_4091 NULL +#define pci_ss_list_0e11_409a NULL +#define pci_ss_list_0e11_409b NULL +#define pci_ss_list_0e11_409c NULL +#define pci_ss_list_0e11_409d NULL +#define pci_ss_list_0e11_6010 NULL +#define pci_ss_list_0e11_7020 NULL +#define pci_ss_list_0e11_a0ec NULL +#define pci_ss_list_0e11_a0f0 NULL +#define pci_ss_list_0e11_a0f3 NULL +static const pciSubsystemInfo *pci_ss_list_0e11_a0f7[] = { + &pci_ss_info_0e11_a0f7_8086_002a, + &pci_ss_info_0e11_a0f7_8086_002b, + NULL +}; +#define pci_ss_list_0e11_a0f8 NULL +#define pci_ss_list_0e11_a0fc NULL +static const pciSubsystemInfo *pci_ss_list_0e11_ae10[] = { + &pci_ss_info_0e11_ae10_0e11_4030, + &pci_ss_info_0e11_ae10_0e11_4031, + &pci_ss_info_0e11_ae10_0e11_4032, + &pci_ss_info_0e11_ae10_0e11_4033, + NULL +}; +#define pci_ss_list_0e11_ae29 NULL +#define pci_ss_list_0e11_ae2a NULL +#define pci_ss_list_0e11_ae2b NULL +#define pci_ss_list_0e11_ae31 NULL +#define pci_ss_list_0e11_ae32 NULL +#define pci_ss_list_0e11_ae33 NULL +#define pci_ss_list_0e11_ae34 NULL +#define pci_ss_list_0e11_ae35 NULL +#define pci_ss_list_0e11_ae40 NULL +#define pci_ss_list_0e11_ae43 NULL +#define pci_ss_list_0e11_ae69 NULL +#define pci_ss_list_0e11_ae6c NULL +#define pci_ss_list_0e11_ae6d NULL +#define pci_ss_list_0e11_b011 NULL +#define pci_ss_list_0e11_b012 NULL +#define pci_ss_list_0e11_b01e NULL +#define pci_ss_list_0e11_b01f NULL +#define pci_ss_list_0e11_b02f NULL +#define pci_ss_list_0e11_b030 NULL +#define pci_ss_list_0e11_b04a NULL +#define pci_ss_list_0e11_b060 NULL +#define pci_ss_list_0e11_b0c6 NULL +#define pci_ss_list_0e11_b0c7 NULL +#define pci_ss_list_0e11_b0d7 NULL +#define pci_ss_list_0e11_b0dd NULL +#define pci_ss_list_0e11_b0de NULL +#define pci_ss_list_0e11_b0df NULL +#define pci_ss_list_0e11_b0e0 NULL +#define pci_ss_list_0e11_b0e1 NULL +#define pci_ss_list_0e11_b123 NULL +#define pci_ss_list_0e11_b134 NULL +#define pci_ss_list_0e11_b13c NULL +#define pci_ss_list_0e11_b144 NULL +#define pci_ss_list_0e11_b163 NULL +#define pci_ss_list_0e11_b164 NULL +static const pciSubsystemInfo *pci_ss_list_0e11_b178[] = { + &pci_ss_info_0e11_b178_0e11_4080, + &pci_ss_info_0e11_b178_0e11_4082, + &pci_ss_info_0e11_b178_0e11_4083, + NULL +}; +#define pci_ss_list_0e11_b1a4 NULL +#define pci_ss_list_0e11_b200 NULL +#define pci_ss_list_0e11_b203 NULL +#define pci_ss_list_0e11_b204 NULL +#define pci_ss_list_0e11_f130 NULL +#define pci_ss_list_0e11_f150 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1000_0001[] = { + &pci_ss_info_1000_0001_1000_1000, + NULL +}; +#define pci_ss_list_1000_0002 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0003[] = { + &pci_ss_info_1000_0003_1000_1000, + NULL +}; +#define pci_ss_list_1000_0004 NULL +#define pci_ss_list_1000_0005 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0006[] = { + &pci_ss_info_1000_0006_1000_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_000a[] = { + &pci_ss_info_1000_000a_0e11_b143, + &pci_ss_info_1000_000a_1000_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_000b[] = { + &pci_ss_info_1000_000b_0e11_6004, + &pci_ss_info_1000_000b_1000_1000, + &pci_ss_info_1000_000b_1000_1010, + &pci_ss_info_1000_000b_1000_1020, + &pci_ss_info_1000_000b_13e9_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_000c[] = { + &pci_ss_info_1000_000c_1000_1010, + &pci_ss_info_1000_000c_1000_1020, + &pci_ss_info_1000_000c_1de1_3906, + &pci_ss_info_1000_000c_1de1_3907, + NULL +}; +#define pci_ss_list_1000_000d NULL +static const pciSubsystemInfo *pci_ss_list_1000_000f[] = { + &pci_ss_info_1000_000f_0e11_7004, + &pci_ss_info_1000_000f_1000_1000, + &pci_ss_info_1000_000f_1000_1010, + &pci_ss_info_1000_000f_1000_1020, + &pci_ss_info_1000_000f_1092_8760, + &pci_ss_info_1000_000f_1775_10d0, + &pci_ss_info_1000_000f_1775_10d1, + &pci_ss_info_1000_000f_1de1_3904, + &pci_ss_info_1000_000f_4c53_1000, + &pci_ss_info_1000_000f_4c53_1050, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0010[] = { + &pci_ss_info_1000_0010_0e11_4040, + &pci_ss_info_1000_0010_0e11_4048, + &pci_ss_info_1000_0010_1000_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0012[] = { + &pci_ss_info_1000_0012_1000_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0013[] = { + &pci_ss_info_1000_0013_1000_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0020[] = { + &pci_ss_info_1000_0020_1000_1000, + &pci_ss_info_1000_0020_107b_1040, + &pci_ss_info_1000_0020_1de1_1020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0021[] = { + &pci_ss_info_1000_0021_1000_1000, + &pci_ss_info_1000_0021_1000_1010, + &pci_ss_info_1000_0021_103c_1330, + &pci_ss_info_1000_0021_103c_1340, + &pci_ss_info_1000_0021_124b_1070, + &pci_ss_info_1000_0021_4c53_1080, + &pci_ss_info_1000_0021_4c53_1300, + &pci_ss_info_1000_0021_4c53_1310, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0030[] = { + &pci_ss_info_1000_0030_0e11_00da, + &pci_ss_info_1000_0030_1028_0123, + &pci_ss_info_1000_0030_1028_014a, + &pci_ss_info_1000_0030_1028_016c, + &pci_ss_info_1000_0030_1028_0183, + &pci_ss_info_1000_0030_1028_1010, + &pci_ss_info_1000_0030_103c_12c5, + &pci_ss_info_1000_0030_124b_1170, + &pci_ss_info_1000_0030_1734_1052, + NULL +}; +#define pci_ss_list_1000_0031 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0032[] = { + &pci_ss_info_1000_0032_1000_1000, + NULL +}; +#define pci_ss_list_1000_0033 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0040[] = { + &pci_ss_info_1000_0040_1000_0033, + &pci_ss_info_1000_0040_1000_0066, + NULL +}; +#define pci_ss_list_1000_0041 NULL +#define pci_ss_list_1000_0050 NULL +#define pci_ss_list_1000_0054 NULL +#define pci_ss_list_1000_0056 NULL +#define pci_ss_list_1000_0058 NULL +#define pci_ss_list_1000_005a NULL +#define pci_ss_list_1000_005c NULL +#define pci_ss_list_1000_005e NULL +static const pciSubsystemInfo *pci_ss_list_1000_0060[] = { + &pci_ss_info_1000_0060_1028_1f0a, + &pci_ss_info_1000_0060_1028_1f0b, + &pci_ss_info_1000_0060_1028_1f0c, + &pci_ss_info_1000_0060_1028_1f0d, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0062[] = { + &pci_ss_info_1000_0062_1000_0062, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_008f[] = { + &pci_ss_info_1000_008f_1092_8000, + &pci_ss_info_1000_008f_1092_8760, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0407[] = { + &pci_ss_info_1000_0407_1000_0530, + &pci_ss_info_1000_0407_1000_0531, + &pci_ss_info_1000_0407_1000_0532, + &pci_ss_info_1000_0407_1028_0531, + &pci_ss_info_1000_0407_1028_0533, + &pci_ss_info_1000_0407_8086_0530, + &pci_ss_info_1000_0407_8086_0532, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0408[] = { + &pci_ss_info_1000_0408_1000_0001, + &pci_ss_info_1000_0408_1000_0002, + &pci_ss_info_1000_0408_1025_004d, + &pci_ss_info_1000_0408_1028_0001, + &pci_ss_info_1000_0408_1028_0002, + &pci_ss_info_1000_0408_1734_1065, + &pci_ss_info_1000_0408_8086_0002, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0409[] = { + &pci_ss_info_1000_0409_1000_3004, + &pci_ss_info_1000_0409_1000_3008, + &pci_ss_info_1000_0409_8086_3008, + &pci_ss_info_1000_0409_8086_3431, + &pci_ss_info_1000_0409_8086_3499, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0411[] = { + &pci_ss_info_1000_0411_1000_1001, + &pci_ss_info_1000_0411_1000_1002, + &pci_ss_info_1000_0411_1000_1003, + &pci_ss_info_1000_0411_1000_1004, + &pci_ss_info_1000_0411_1000_100c, + &pci_ss_info_1000_0411_1000_100d, + &pci_ss_info_1000_0411_1000_2004, + &pci_ss_info_1000_0411_1000_2005, + &pci_ss_info_1000_0411_1033_8287, + &pci_ss_info_1000_0411_1054_3016, + &pci_ss_info_1000_0411_1734_1081, + &pci_ss_info_1000_0411_1734_10a3, + &pci_ss_info_1000_0411_8086_1001, + &pci_ss_info_1000_0411_8086_1003, + &pci_ss_info_1000_0411_8086_3500, + &pci_ss_info_1000_0411_8086_3501, + &pci_ss_info_1000_0411_8086_3504, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1000_0413[] = { + &pci_ss_info_1000_0413_1000_1005, + NULL +}; +#define pci_ss_list_1000_0621 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0622[] = { + &pci_ss_info_1000_0622_1000_1020, + NULL +}; +#define pci_ss_list_1000_0623 NULL +#define pci_ss_list_1000_0624 NULL +#define pci_ss_list_1000_0625 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0626[] = { + &pci_ss_info_1000_0626_1000_1010, + NULL +}; +#define pci_ss_list_1000_0627 NULL +#define pci_ss_list_1000_0628 NULL +#define pci_ss_list_1000_0629 NULL +#define pci_ss_list_1000_0640 NULL +#define pci_ss_list_1000_0642 NULL +#define pci_ss_list_1000_0646 NULL +#define pci_ss_list_1000_0701 NULL +static const pciSubsystemInfo *pci_ss_list_1000_0702[] = { + &pci_ss_info_1000_0702_1318_0000, + NULL +}; +#define pci_ss_list_1000_0804 NULL +#define pci_ss_list_1000_0805 NULL +#define pci_ss_list_1000_0806 NULL +#define pci_ss_list_1000_0807 NULL +#define pci_ss_list_1000_0901 NULL +#define pci_ss_list_1000_1000 NULL +static const pciSubsystemInfo *pci_ss_list_1000_1960[] = { + &pci_ss_info_1000_1960_1000_0518, + &pci_ss_info_1000_1960_1000_0520, + &pci_ss_info_1000_1960_1000_0522, + &pci_ss_info_1000_1960_1000_0523, + &pci_ss_info_1000_1960_1000_4523, + &pci_ss_info_1000_1960_1000_a520, + &pci_ss_info_1000_1960_1028_0518, + &pci_ss_info_1000_1960_1028_0520, + &pci_ss_info_1000_1960_1028_0531, + &pci_ss_info_1000_1960_1028_0533, + &pci_ss_info_1000_1960_8086_0520, + &pci_ss_info_1000_1960_8086_0523, + NULL +}; +#endif +#define pci_ss_list_1001_0010 NULL +#define pci_ss_list_1001_0011 NULL +#define pci_ss_list_1001_0012 NULL +#define pci_ss_list_1001_0013 NULL +#define pci_ss_list_1001_0014 NULL +#define pci_ss_list_1001_0015 NULL +#define pci_ss_list_1001_0016 NULL +#define pci_ss_list_1001_0017 NULL +#define pci_ss_list_1001_9100 NULL +#define pci_ss_list_1002_3150 NULL +#define pci_ss_list_1002_3152 NULL +#define pci_ss_list_1002_3154 NULL +#define pci_ss_list_1002_3e50 NULL +#define pci_ss_list_1002_3e54 NULL +#define pci_ss_list_1002_3e70 NULL +#define pci_ss_list_1002_4136 NULL +#define pci_ss_list_1002_4137 NULL +#define pci_ss_list_1002_4144 NULL +#define pci_ss_list_1002_4145 NULL +#define pci_ss_list_1002_4146 NULL +#define pci_ss_list_1002_4147 NULL +#define pci_ss_list_1002_4148 NULL +#define pci_ss_list_1002_4149 NULL +#define pci_ss_list_1002_414a NULL +#define pci_ss_list_1002_414b NULL +static const pciSubsystemInfo *pci_ss_list_1002_4150[] = { + &pci_ss_info_1002_4150_1002_0002, + &pci_ss_info_1002_4150_1002_0003, + &pci_ss_info_1002_4150_1002_4722, + &pci_ss_info_1002_4150_1458_4024, + &pci_ss_info_1002_4150_148c_2064, + &pci_ss_info_1002_4150_148c_2066, + &pci_ss_info_1002_4150_174b_7c19, + &pci_ss_info_1002_4150_174b_7c29, + &pci_ss_info_1002_4150_17ee_2002, + &pci_ss_info_1002_4150_18bc_0101, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4151[] = { + &pci_ss_info_1002_4151_1043_c004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4152[] = { + &pci_ss_info_1002_4152_1002_0002, + &pci_ss_info_1002_4152_1002_4772, + &pci_ss_info_1002_4152_1043_c002, + &pci_ss_info_1002_4152_1043_c01a, + &pci_ss_info_1002_4152_174b_7c29, + &pci_ss_info_1002_4152_1787_4002, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4153[] = { + &pci_ss_info_1002_4153_1043_010c, + &pci_ss_info_1002_4153_1462_932c, + NULL +}; +#define pci_ss_list_1002_4154 NULL +#define pci_ss_list_1002_4155 NULL +#define pci_ss_list_1002_4156 NULL +#define pci_ss_list_1002_4157 NULL +#define pci_ss_list_1002_4158 NULL +#define pci_ss_list_1002_4164 NULL +#define pci_ss_list_1002_4165 NULL +#define pci_ss_list_1002_4166 NULL +#define pci_ss_list_1002_4168 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4170[] = { + &pci_ss_info_1002_4170_1002_0003, + &pci_ss_info_1002_4170_1002_4723, + &pci_ss_info_1002_4170_1458_4025, + &pci_ss_info_1002_4170_148c_2067, + &pci_ss_info_1002_4170_174b_7c28, + &pci_ss_info_1002_4170_17ee_2003, + &pci_ss_info_1002_4170_18bc_0100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4171[] = { + &pci_ss_info_1002_4171_1043_c005, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4172[] = { + &pci_ss_info_1002_4172_1002_0003, + &pci_ss_info_1002_4172_1002_4773, + &pci_ss_info_1002_4172_1043_c003, + &pci_ss_info_1002_4172_1043_c01b, + &pci_ss_info_1002_4172_174b_7c28, + &pci_ss_info_1002_4172_1787_4003, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4173[] = { + &pci_ss_info_1002_4173_1043_010d, + NULL +}; +#define pci_ss_list_1002_4237 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4242[] = { + &pci_ss_info_1002_4242_1002_02aa, + NULL +}; +#define pci_ss_list_1002_4243 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4336[] = { + &pci_ss_info_1002_4336_1002_4336, + &pci_ss_info_1002_4336_103c_0024, + &pci_ss_info_1002_4336_161f_2029, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4337[] = { + &pci_ss_info_1002_4337_1014_053a, + &pci_ss_info_1002_4337_103c_0850, + NULL +}; +#define pci_ss_list_1002_4341 NULL +#define pci_ss_list_1002_4345 NULL +#define pci_ss_list_1002_4347 NULL +#define pci_ss_list_1002_4348 NULL +#define pci_ss_list_1002_4349 NULL +#define pci_ss_list_1002_434d NULL +#define pci_ss_list_1002_4353 NULL +#define pci_ss_list_1002_4354 NULL +#define pci_ss_list_1002_4358 NULL +#define pci_ss_list_1002_4363 NULL +#define pci_ss_list_1002_436e NULL +static const pciSubsystemInfo *pci_ss_list_1002_4370[] = { + &pci_ss_info_1002_4370_1025_0079, + &pci_ss_info_1002_4370_103c_308b, + &pci_ss_info_1002_4370_107b_0300, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4371[] = { + &pci_ss_info_1002_4371_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4372[] = { + &pci_ss_info_1002_4372_1025_0080, + &pci_ss_info_1002_4372_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4373[] = { + &pci_ss_info_1002_4373_1025_0080, + &pci_ss_info_1002_4373_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4374[] = { + &pci_ss_info_1002_4374_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4375[] = { + &pci_ss_info_1002_4375_1025_0080, + &pci_ss_info_1002_4375_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4376[] = { + &pci_ss_info_1002_4376_1025_0080, + &pci_ss_info_1002_4376_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4377[] = { + &pci_ss_info_1002_4377_1025_0080, + &pci_ss_info_1002_4377_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4378[] = { + &pci_ss_info_1002_4378_1025_0080, + &pci_ss_info_1002_4378_103c_308b, + NULL +}; +#define pci_ss_list_1002_4379 NULL +#define pci_ss_list_1002_437a NULL +#define pci_ss_list_1002_437b NULL +#define pci_ss_list_1002_4380 NULL +#define pci_ss_list_1002_4381 NULL +#define pci_ss_list_1002_4382 NULL +#define pci_ss_list_1002_4383 NULL +#define pci_ss_list_1002_4384 NULL +#define pci_ss_list_1002_4385 NULL +#define pci_ss_list_1002_4386 NULL +#define pci_ss_list_1002_4387 NULL +#define pci_ss_list_1002_4388 NULL +#define pci_ss_list_1002_4389 NULL +#define pci_ss_list_1002_438a NULL +#define pci_ss_list_1002_438b NULL +#define pci_ss_list_1002_438c NULL +#define pci_ss_list_1002_438d NULL +#define pci_ss_list_1002_438e NULL +#define pci_ss_list_1002_4437 NULL +#define pci_ss_list_1002_4554 NULL +#define pci_ss_list_1002_4654 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4742[] = { + &pci_ss_info_1002_4742_1002_0040, + &pci_ss_info_1002_4742_1002_0044, + &pci_ss_info_1002_4742_1002_0061, + &pci_ss_info_1002_4742_1002_0062, + &pci_ss_info_1002_4742_1002_0063, + &pci_ss_info_1002_4742_1002_0080, + &pci_ss_info_1002_4742_1002_0084, + &pci_ss_info_1002_4742_1002_4742, + &pci_ss_info_1002_4742_1002_8001, + &pci_ss_info_1002_4742_1028_0082, + &pci_ss_info_1002_4742_1028_4082, + &pci_ss_info_1002_4742_1028_8082, + &pci_ss_info_1002_4742_1028_c082, + &pci_ss_info_1002_4742_8086_4152, + &pci_ss_info_1002_4742_8086_464a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4744[] = { + &pci_ss_info_1002_4744_1002_4744, + NULL +}; +#define pci_ss_list_1002_4747 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4749[] = { + &pci_ss_info_1002_4749_1002_0061, + &pci_ss_info_1002_4749_1002_0062, + NULL +}; +#define pci_ss_list_1002_474c NULL +static const pciSubsystemInfo *pci_ss_list_1002_474d[] = { + &pci_ss_info_1002_474d_1002_0004, + &pci_ss_info_1002_474d_1002_0008, + &pci_ss_info_1002_474d_1002_0080, + &pci_ss_info_1002_474d_1002_0084, + &pci_ss_info_1002_474d_1002_474d, + &pci_ss_info_1002_474d_1033_806a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_474e[] = { + &pci_ss_info_1002_474e_1002_474e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_474f[] = { + &pci_ss_info_1002_474f_1002_0008, + &pci_ss_info_1002_474f_1002_474f, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4750[] = { + &pci_ss_info_1002_4750_1002_0040, + &pci_ss_info_1002_4750_1002_0044, + &pci_ss_info_1002_4750_1002_0080, + &pci_ss_info_1002_4750_1002_0084, + &pci_ss_info_1002_4750_1002_4750, + NULL +}; +#define pci_ss_list_1002_4751 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4752[] = { + &pci_ss_info_1002_4752_0e11_001e, + &pci_ss_info_1002_4752_1002_0008, + &pci_ss_info_1002_4752_1002_4752, + &pci_ss_info_1002_4752_1002_8008, + &pci_ss_info_1002_4752_1028_00ce, + &pci_ss_info_1002_4752_1028_00d1, + &pci_ss_info_1002_4752_1028_00d9, + &pci_ss_info_1002_4752_1028_0134, + &pci_ss_info_1002_4752_103c_10e1, + &pci_ss_info_1002_4752_107b_6400, + &pci_ss_info_1002_4752_1734_007a, + &pci_ss_info_1002_4752_8086_3411, + &pci_ss_info_1002_4752_8086_3427, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4753[] = { + &pci_ss_info_1002_4753_1002_4753, + NULL +}; +#define pci_ss_list_1002_4754 NULL +#define pci_ss_list_1002_4755 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4756[] = { + &pci_ss_info_1002_4756_1002_4756, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4757[] = { + &pci_ss_info_1002_4757_1002_4757, + &pci_ss_info_1002_4757_1028_0089, + &pci_ss_info_1002_4757_1028_008e, + &pci_ss_info_1002_4757_1028_4082, + &pci_ss_info_1002_4757_1028_8082, + &pci_ss_info_1002_4757_1028_c082, + NULL +}; +#define pci_ss_list_1002_4758 NULL +#define pci_ss_list_1002_4759 NULL +static const pciSubsystemInfo *pci_ss_list_1002_475a[] = { + &pci_ss_info_1002_475a_1002_0084, + &pci_ss_info_1002_475a_1002_0087, + &pci_ss_info_1002_475a_1002_475a, + NULL +}; +#define pci_ss_list_1002_4964 NULL +#define pci_ss_list_1002_4965 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4966[] = { + &pci_ss_info_1002_4966_10f1_0002, + &pci_ss_info_1002_4966_148c_2039, + &pci_ss_info_1002_4966_1509_9a00, + &pci_ss_info_1002_4966_1681_0040, + &pci_ss_info_1002_4966_174b_7176, + &pci_ss_info_1002_4966_174b_7192, + &pci_ss_info_1002_4966_17af_2005, + &pci_ss_info_1002_4966_17af_2006, + NULL +}; +#define pci_ss_list_1002_4967 NULL +#define pci_ss_list_1002_496e NULL +#define pci_ss_list_1002_4a48 NULL +#define pci_ss_list_1002_4a49 NULL +#define pci_ss_list_1002_4a4a NULL +#define pci_ss_list_1002_4a4b NULL +#define pci_ss_list_1002_4a4c NULL +#define pci_ss_list_1002_4a4d NULL +#define pci_ss_list_1002_4a4e NULL +#define pci_ss_list_1002_4a50 NULL +#define pci_ss_list_1002_4a54 NULL +#define pci_ss_list_1002_4a69 NULL +#define pci_ss_list_1002_4a6a NULL +#define pci_ss_list_1002_4a6b NULL +#define pci_ss_list_1002_4a70 NULL +#define pci_ss_list_1002_4a74 NULL +#define pci_ss_list_1002_4b49 NULL +#define pci_ss_list_1002_4b4b NULL +#define pci_ss_list_1002_4b4c NULL +#define pci_ss_list_1002_4b69 NULL +#define pci_ss_list_1002_4b6b NULL +#define pci_ss_list_1002_4b6c NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c42[] = { + &pci_ss_info_1002_4c42_0e11_b0e7, + &pci_ss_info_1002_4c42_0e11_b0e8, + &pci_ss_info_1002_4c42_0e11_b10e, + &pci_ss_info_1002_4c42_1002_0040, + &pci_ss_info_1002_4c42_1002_0044, + &pci_ss_info_1002_4c42_1002_4c42, + &pci_ss_info_1002_4c42_1002_8001, + &pci_ss_info_1002_4c42_1028_0085, + NULL +}; +#define pci_ss_list_1002_4c44 NULL +#define pci_ss_list_1002_4c45 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c46[] = { + &pci_ss_info_1002_4c46_1028_00b1, + NULL +}; +#define pci_ss_list_1002_4c47 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c49[] = { + &pci_ss_info_1002_4c49_1002_0004, + &pci_ss_info_1002_4c49_1002_0040, + &pci_ss_info_1002_4c49_1002_0044, + &pci_ss_info_1002_4c49_1002_4c49, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4c4d[] = { + &pci_ss_info_1002_4c4d_0e11_b111, + &pci_ss_info_1002_4c4d_0e11_b160, + &pci_ss_info_1002_4c4d_1002_0084, + &pci_ss_info_1002_4c4d_1014_0154, + &pci_ss_info_1002_4c4d_1028_00aa, + &pci_ss_info_1002_4c4d_1028_00bb, + &pci_ss_info_1002_4c4d_10e1_10cf, + &pci_ss_info_1002_4c4d_1179_ff00, + &pci_ss_info_1002_4c4d_13bd_1019, + NULL +}; +#define pci_ss_list_1002_4c4e NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c50[] = { + &pci_ss_info_1002_4c50_1002_4c50, + NULL +}; +#define pci_ss_list_1002_4c51 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c52[] = { + &pci_ss_info_1002_4c52_1033_8112, + NULL +}; +#define pci_ss_list_1002_4c53 NULL +#define pci_ss_list_1002_4c54 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c57[] = { + &pci_ss_info_1002_4c57_1014_0517, + &pci_ss_info_1002_4c57_1028_00e6, + &pci_ss_info_1002_4c57_1028_012a, + &pci_ss_info_1002_4c57_144d_c006, + NULL +}; +#define pci_ss_list_1002_4c58 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4c59[] = { + &pci_ss_info_1002_4c59_0e11_b111, + &pci_ss_info_1002_4c59_1014_0235, + &pci_ss_info_1002_4c59_1014_0239, + &pci_ss_info_1002_4c59_104d_80e7, + &pci_ss_info_1002_4c59_104d_8140, + &pci_ss_info_1002_4c59_1509_1930, + NULL +}; +#define pci_ss_list_1002_4c5a NULL +#define pci_ss_list_1002_4c64 NULL +#define pci_ss_list_1002_4c65 NULL +#define pci_ss_list_1002_4c66 NULL +#define pci_ss_list_1002_4c67 NULL +#define pci_ss_list_1002_4c6e NULL +#define pci_ss_list_1002_4d46 NULL +#define pci_ss_list_1002_4d4c NULL +static const pciSubsystemInfo *pci_ss_list_1002_4e44[] = { + &pci_ss_info_1002_4e44_1002_515e, + &pci_ss_info_1002_4e44_1002_5965, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_4e45[] = { + &pci_ss_info_1002_4e45_1002_0002, + &pci_ss_info_1002_4e45_1681_0002, + NULL +}; +#define pci_ss_list_1002_4e46 NULL +#define pci_ss_list_1002_4e47 NULL +#define pci_ss_list_1002_4e48 NULL +#define pci_ss_list_1002_4e49 NULL +#define pci_ss_list_1002_4e4a NULL +#define pci_ss_list_1002_4e4b NULL +static const pciSubsystemInfo *pci_ss_list_1002_4e50[] = { + &pci_ss_info_1002_4e50_1025_005a, + &pci_ss_info_1002_4e50_103c_088c, + &pci_ss_info_1002_4e50_103c_0890, + &pci_ss_info_1002_4e50_1462_0311, + &pci_ss_info_1002_4e50_1734_1055, + NULL +}; +#define pci_ss_list_1002_4e51 NULL +#define pci_ss_list_1002_4e52 NULL +#define pci_ss_list_1002_4e53 NULL +#define pci_ss_list_1002_4e54 NULL +#define pci_ss_list_1002_4e56 NULL +#define pci_ss_list_1002_4e64 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4e65[] = { + &pci_ss_info_1002_4e65_1002_0003, + &pci_ss_info_1002_4e65_1681_0003, + NULL +}; +#define pci_ss_list_1002_4e66 NULL +#define pci_ss_list_1002_4e67 NULL +#define pci_ss_list_1002_4e68 NULL +#define pci_ss_list_1002_4e69 NULL +static const pciSubsystemInfo *pci_ss_list_1002_4e6a[] = { + &pci_ss_info_1002_4e6a_1002_4e71, + NULL +}; +#define pci_ss_list_1002_4e71 NULL +#define pci_ss_list_1002_4f72 NULL +#define pci_ss_list_1002_4f73 NULL +#define pci_ss_list_1002_5041 NULL +#define pci_ss_list_1002_5042 NULL +#define pci_ss_list_1002_5043 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5044[] = { + &pci_ss_info_1002_5044_1002_0028, + &pci_ss_info_1002_5044_1002_0029, + NULL +}; +#define pci_ss_list_1002_5045 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5046[] = { + &pci_ss_info_1002_5046_1002_0004, + &pci_ss_info_1002_5046_1002_0008, + &pci_ss_info_1002_5046_1002_0014, + &pci_ss_info_1002_5046_1002_0018, + &pci_ss_info_1002_5046_1002_0028, + &pci_ss_info_1002_5046_1002_002a, + &pci_ss_info_1002_5046_1002_0048, + &pci_ss_info_1002_5046_1002_2000, + &pci_ss_info_1002_5046_1002_2001, + NULL +}; +#define pci_ss_list_1002_5047 NULL +#define pci_ss_list_1002_5048 NULL +#define pci_ss_list_1002_5049 NULL +#define pci_ss_list_1002_504a NULL +#define pci_ss_list_1002_504b NULL +#define pci_ss_list_1002_504c NULL +#define pci_ss_list_1002_504d NULL +#define pci_ss_list_1002_504e NULL +#define pci_ss_list_1002_504f NULL +static const pciSubsystemInfo *pci_ss_list_1002_5050[] = { + &pci_ss_info_1002_5050_1002_0008, + NULL +}; +#define pci_ss_list_1002_5051 NULL +#define pci_ss_list_1002_5052 NULL +#define pci_ss_list_1002_5053 NULL +#define pci_ss_list_1002_5054 NULL +#define pci_ss_list_1002_5055 NULL +#define pci_ss_list_1002_5056 NULL +#define pci_ss_list_1002_5057 NULL +#define pci_ss_list_1002_5058 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5144[] = { + &pci_ss_info_1002_5144_1002_0008, + &pci_ss_info_1002_5144_1002_0009, + &pci_ss_info_1002_5144_1002_000a, + &pci_ss_info_1002_5144_1002_001a, + &pci_ss_info_1002_5144_1002_0029, + &pci_ss_info_1002_5144_1002_0038, + &pci_ss_info_1002_5144_1002_0039, + &pci_ss_info_1002_5144_1002_008a, + &pci_ss_info_1002_5144_1002_00ba, + &pci_ss_info_1002_5144_1002_0139, + &pci_ss_info_1002_5144_1002_028a, + &pci_ss_info_1002_5144_1002_02aa, + &pci_ss_info_1002_5144_1002_053a, + NULL +}; +#define pci_ss_list_1002_5145 NULL +#define pci_ss_list_1002_5146 NULL +#define pci_ss_list_1002_5147 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5148[] = { + &pci_ss_info_1002_5148_1002_010a, + &pci_ss_info_1002_5148_1002_0152, + &pci_ss_info_1002_5148_1002_0162, + &pci_ss_info_1002_5148_1002_0172, + NULL +}; +#define pci_ss_list_1002_5149 NULL +#define pci_ss_list_1002_514a NULL +#define pci_ss_list_1002_514b NULL +static const pciSubsystemInfo *pci_ss_list_1002_514c[] = { + &pci_ss_info_1002_514c_1002_003a, + &pci_ss_info_1002_514c_1002_013a, + &pci_ss_info_1002_514c_148c_2026, + &pci_ss_info_1002_514c_1681_0010, + &pci_ss_info_1002_514c_174b_7149, + NULL +}; +#define pci_ss_list_1002_514d NULL +#define pci_ss_list_1002_514e NULL +#define pci_ss_list_1002_514f NULL +#define pci_ss_list_1002_5154 NULL +#define pci_ss_list_1002_5155 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5157[] = { + &pci_ss_info_1002_5157_1002_013a, + &pci_ss_info_1002_5157_1002_103a, + &pci_ss_info_1002_5157_1458_4000, + &pci_ss_info_1002_5157_148c_2024, + &pci_ss_info_1002_5157_148c_2025, + &pci_ss_info_1002_5157_148c_2036, + &pci_ss_info_1002_5157_174b_7146, + &pci_ss_info_1002_5157_174b_7147, + &pci_ss_info_1002_5157_174b_7161, + &pci_ss_info_1002_5157_17af_0202, + NULL +}; +#define pci_ss_list_1002_5158 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5159[] = { + &pci_ss_info_1002_5159_1002_000a, + &pci_ss_info_1002_5159_1002_000b, + &pci_ss_info_1002_5159_1002_0038, + &pci_ss_info_1002_5159_1002_003a, + &pci_ss_info_1002_5159_1002_00ba, + &pci_ss_info_1002_5159_1002_013a, + &pci_ss_info_1002_5159_1002_0908, + &pci_ss_info_1002_5159_1014_029a, + &pci_ss_info_1002_5159_1014_02c8, + &pci_ss_info_1002_5159_1028_019a, + &pci_ss_info_1002_5159_103c_1292, + &pci_ss_info_1002_5159_1458_4002, + &pci_ss_info_1002_5159_148c_2003, + &pci_ss_info_1002_5159_148c_2023, + &pci_ss_info_1002_5159_174b_7112, + &pci_ss_info_1002_5159_174b_7c28, + &pci_ss_info_1002_5159_1787_0202, + &pci_ss_info_1002_5159_17ee_1001, + NULL +}; +#define pci_ss_list_1002_515a NULL +#define pci_ss_list_1002_515e NULL +#define pci_ss_list_1002_515f NULL +#define pci_ss_list_1002_5168 NULL +#define pci_ss_list_1002_5169 NULL +#define pci_ss_list_1002_516a NULL +#define pci_ss_list_1002_516b NULL +#define pci_ss_list_1002_516c NULL +static const pciSubsystemInfo *pci_ss_list_1002_5245[] = { + &pci_ss_info_1002_5245_1002_0008, + &pci_ss_info_1002_5245_1002_0028, + &pci_ss_info_1002_5245_1002_0029, + &pci_ss_info_1002_5245_1002_0068, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_5246[] = { + &pci_ss_info_1002_5246_1002_0004, + &pci_ss_info_1002_5246_1002_0008, + &pci_ss_info_1002_5246_1002_0028, + &pci_ss_info_1002_5246_1002_0044, + &pci_ss_info_1002_5246_1002_0068, + &pci_ss_info_1002_5246_1002_0448, + NULL +}; +#define pci_ss_list_1002_5247 NULL +#define pci_ss_list_1002_524b NULL +static const pciSubsystemInfo *pci_ss_list_1002_524c[] = { + &pci_ss_info_1002_524c_1002_0008, + &pci_ss_info_1002_524c_1002_0088, + NULL +}; +#define pci_ss_list_1002_5345 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5346[] = { + &pci_ss_info_1002_5346_1002_0048, + NULL +}; +#define pci_ss_list_1002_5347 NULL +#define pci_ss_list_1002_5348 NULL +#define pci_ss_list_1002_534b NULL +#define pci_ss_list_1002_534c NULL +static const pciSubsystemInfo *pci_ss_list_1002_534d[] = { + &pci_ss_info_1002_534d_1002_0008, + &pci_ss_info_1002_534d_1002_0018, + NULL +}; +#define pci_ss_list_1002_534e NULL +static const pciSubsystemInfo *pci_ss_list_1002_5354[] = { + &pci_ss_info_1002_5354_1002_5654, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_5446[] = { + &pci_ss_info_1002_5446_1002_0004, + &pci_ss_info_1002_5446_1002_0008, + &pci_ss_info_1002_5446_1002_0018, + &pci_ss_info_1002_5446_1002_0028, + &pci_ss_info_1002_5446_1002_0029, + &pci_ss_info_1002_5446_1002_002a, + &pci_ss_info_1002_5446_1002_002b, + &pci_ss_info_1002_5446_1002_0048, + NULL +}; +#define pci_ss_list_1002_544c NULL +static const pciSubsystemInfo *pci_ss_list_1002_5452[] = { + &pci_ss_info_1002_5452_1002_001c, + &pci_ss_info_1002_5452_103c_1279, + NULL +}; +#define pci_ss_list_1002_5453 NULL +#define pci_ss_list_1002_5454 NULL +#define pci_ss_list_1002_5455 NULL +#define pci_ss_list_1002_5460 NULL +#define pci_ss_list_1002_5462 NULL +#define pci_ss_list_1002_5464 NULL +#define pci_ss_list_1002_5548 NULL +#define pci_ss_list_1002_5549 NULL +#define pci_ss_list_1002_554a NULL +#define pci_ss_list_1002_554b NULL +#define pci_ss_list_1002_554d NULL +#define pci_ss_list_1002_554f NULL +#define pci_ss_list_1002_5550 NULL +#define pci_ss_list_1002_5551 NULL +#define pci_ss_list_1002_5552 NULL +#define pci_ss_list_1002_5554 NULL +#define pci_ss_list_1002_5569 NULL +#define pci_ss_list_1002_556b NULL +#define pci_ss_list_1002_556d NULL +#define pci_ss_list_1002_556f NULL +#define pci_ss_list_1002_5571 NULL +#define pci_ss_list_1002_564a NULL +#define pci_ss_list_1002_564b NULL +#define pci_ss_list_1002_564f NULL +#define pci_ss_list_1002_5652 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5653[] = { + &pci_ss_info_1002_5653_1025_0080, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_5654[] = { + &pci_ss_info_1002_5654_1002_5654, + NULL +}; +#define pci_ss_list_1002_5655 NULL +#define pci_ss_list_1002_5656 NULL +#define pci_ss_list_1002_5830 NULL +#define pci_ss_list_1002_5831 NULL +#define pci_ss_list_1002_5832 NULL +#define pci_ss_list_1002_5833 NULL +#define pci_ss_list_1002_5834 NULL +#define pci_ss_list_1002_5835 NULL +#define pci_ss_list_1002_5838 NULL +#define pci_ss_list_1002_5940 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5941[] = { + &pci_ss_info_1002_5941_1458_4019, + &pci_ss_info_1002_5941_174b_7c12, + &pci_ss_info_1002_5941_17af_200d, + &pci_ss_info_1002_5941_18bc_0050, + NULL +}; +#define pci_ss_list_1002_5944 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5950[] = { + &pci_ss_info_1002_5950_1025_0080, + &pci_ss_info_1002_5950_103c_308b, + NULL +}; +#define pci_ss_list_1002_5951 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5954[] = { + &pci_ss_info_1002_5954_1002_5954, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_5955[] = { + &pci_ss_info_1002_5955_1002_5955, + &pci_ss_info_1002_5955_103c_308b, + NULL +}; +#define pci_ss_list_1002_5960 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5961[] = { + &pci_ss_info_1002_5961_1002_2f72, + &pci_ss_info_1002_5961_1019_4c30, + &pci_ss_info_1002_5961_12ab_5961, + &pci_ss_info_1002_5961_1458_4018, + &pci_ss_info_1002_5961_174b_7c13, + &pci_ss_info_1002_5961_17af_200c, + &pci_ss_info_1002_5961_18bc_0050, + &pci_ss_info_1002_5961_18bc_0051, + &pci_ss_info_1002_5961_18bc_0053, + NULL +}; +#define pci_ss_list_1002_5962 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5964[] = { + &pci_ss_info_1002_5964_1043_c006, + &pci_ss_info_1002_5964_1458_4018, + &pci_ss_info_1002_5964_1458_4032, + &pci_ss_info_1002_5964_147b_6191, + &pci_ss_info_1002_5964_148c_2073, + &pci_ss_info_1002_5964_174b_7c13, + &pci_ss_info_1002_5964_1787_5964, + &pci_ss_info_1002_5964_17af_2012, + &pci_ss_info_1002_5964_18bc_0170, + &pci_ss_info_1002_5964_18bc_0173, + NULL +}; +#define pci_ss_list_1002_5969 NULL +#define pci_ss_list_1002_5974 NULL +#define pci_ss_list_1002_5975 NULL +#define pci_ss_list_1002_5a33 NULL +#define pci_ss_list_1002_5a34 NULL +#define pci_ss_list_1002_5a36 NULL +#define pci_ss_list_1002_5a38 NULL +#define pci_ss_list_1002_5a39 NULL +#define pci_ss_list_1002_5a3f NULL +#define pci_ss_list_1002_5a41 NULL +#define pci_ss_list_1002_5a42 NULL +#define pci_ss_list_1002_5a61 NULL +#define pci_ss_list_1002_5a62 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5b60[] = { + &pci_ss_info_1002_5b60_1043_002a, + &pci_ss_info_1002_5b60_1043_032e, + &pci_ss_info_1002_5b60_1462_0400, + &pci_ss_info_1002_5b60_1462_0402, + &pci_ss_info_1002_5b60_196d_1086, + NULL +}; +#define pci_ss_list_1002_5b62 NULL +#define pci_ss_list_1002_5b63 NULL +#define pci_ss_list_1002_5b64 NULL +#define pci_ss_list_1002_5b65 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5b70[] = { + &pci_ss_info_1002_5b70_1462_0403, + &pci_ss_info_1002_5b70_196d_1087, + NULL +}; +#define pci_ss_list_1002_5b72 NULL +#define pci_ss_list_1002_5b73 NULL +#define pci_ss_list_1002_5b74 NULL +#define pci_ss_list_1002_5c61 NULL +static const pciSubsystemInfo *pci_ss_list_1002_5c63[] = { + &pci_ss_info_1002_5c63_1002_5c63, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_5d44[] = { + &pci_ss_info_1002_5d44_1458_4019, + &pci_ss_info_1002_5d44_1458_4032, + &pci_ss_info_1002_5d44_174b_7c12, + &pci_ss_info_1002_5d44_1787_5965, + &pci_ss_info_1002_5d44_17af_2013, + &pci_ss_info_1002_5d44_18bc_0171, + &pci_ss_info_1002_5d44_18bc_0172, + NULL +}; +#define pci_ss_list_1002_5d48 NULL +#define pci_ss_list_1002_5d49 NULL +#define pci_ss_list_1002_5d4a NULL +#define pci_ss_list_1002_5d4d NULL +#define pci_ss_list_1002_5d4f NULL +static const pciSubsystemInfo *pci_ss_list_1002_5d52[] = { + &pci_ss_info_1002_5d52_1002_0b12, + &pci_ss_info_1002_5d52_1002_0b13, + NULL +}; +#define pci_ss_list_1002_5d57 NULL +#define pci_ss_list_1002_5d6d NULL +#define pci_ss_list_1002_5d6f NULL +#define pci_ss_list_1002_5d72 NULL +#define pci_ss_list_1002_5d77 NULL +#define pci_ss_list_1002_5e48 NULL +#define pci_ss_list_1002_5e49 NULL +#define pci_ss_list_1002_5e4a NULL +#define pci_ss_list_1002_5e4b NULL +#define pci_ss_list_1002_5e4c NULL +static const pciSubsystemInfo *pci_ss_list_1002_5e4d[] = { + &pci_ss_info_1002_5e4d_148c_2116, + NULL +}; +#define pci_ss_list_1002_5e4f NULL +#define pci_ss_list_1002_5e6b NULL +static const pciSubsystemInfo *pci_ss_list_1002_5e6d[] = { + &pci_ss_info_1002_5e6d_148c_2117, + NULL +}; +#define pci_ss_list_1002_5f57 NULL +#define pci_ss_list_1002_700f NULL +#define pci_ss_list_1002_7010 NULL +#define pci_ss_list_1002_7100 NULL +#define pci_ss_list_1002_7102 NULL +#define pci_ss_list_1002_7103 NULL +#define pci_ss_list_1002_7104 NULL +#define pci_ss_list_1002_7105 NULL +#define pci_ss_list_1002_7106 NULL +#define pci_ss_list_1002_7108 NULL +static const pciSubsystemInfo *pci_ss_list_1002_7109[] = { + &pci_ss_info_1002_7109_1002_0322, + &pci_ss_info_1002_7109_1002_0d02, + NULL +}; +#define pci_ss_list_1002_710a NULL +#define pci_ss_list_1002_710b NULL +#define pci_ss_list_1002_710c NULL +#define pci_ss_list_1002_7120 NULL +#define pci_ss_list_1002_7124 NULL +static const pciSubsystemInfo *pci_ss_list_1002_7129[] = { + &pci_ss_info_1002_7129_1002_0323, + &pci_ss_info_1002_7129_1002_0d03, + NULL +}; +#define pci_ss_list_1002_7140 NULL +static const pciSubsystemInfo *pci_ss_list_1002_7142[] = { + &pci_ss_info_1002_7142_1002_0322, + NULL +}; +#define pci_ss_list_1002_7145 NULL +static const pciSubsystemInfo *pci_ss_list_1002_7146[] = { + &pci_ss_info_1002_7146_1002_0322, + NULL +}; +#define pci_ss_list_1002_7149 NULL +#define pci_ss_list_1002_714a NULL +#define pci_ss_list_1002_714b NULL +#define pci_ss_list_1002_714c NULL +#define pci_ss_list_1002_714d NULL +#define pci_ss_list_1002_714e NULL +#define pci_ss_list_1002_7152 NULL +#define pci_ss_list_1002_715e NULL +static const pciSubsystemInfo *pci_ss_list_1002_7162[] = { + &pci_ss_info_1002_7162_1002_0323, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1002_7166[] = { + &pci_ss_info_1002_7166_1002_0323, + NULL +}; +#define pci_ss_list_1002_7172 NULL +#define pci_ss_list_1002_7180 NULL +#define pci_ss_list_1002_7181 NULL +#define pci_ss_list_1002_71a0 NULL +#define pci_ss_list_1002_71a1 NULL +#define pci_ss_list_1002_71c0 NULL +#define pci_ss_list_1002_71c2 NULL +static const pciSubsystemInfo *pci_ss_list_1002_71c4[] = { + &pci_ss_info_1002_71c4_17aa_2007, + NULL +}; +#define pci_ss_list_1002_71c5 NULL +#define pci_ss_list_1002_71c6 NULL +#define pci_ss_list_1002_71ce NULL +#define pci_ss_list_1002_71d5 NULL +#define pci_ss_list_1002_71d6 NULL +#define pci_ss_list_1002_71de NULL +#define pci_ss_list_1002_71e0 NULL +#define pci_ss_list_1002_71e2 NULL +#define pci_ss_list_1002_7240 NULL +#define pci_ss_list_1002_7241 NULL +#define pci_ss_list_1002_7242 NULL +#define pci_ss_list_1002_7243 NULL +#define pci_ss_list_1002_7244 NULL +#define pci_ss_list_1002_7245 NULL +#define pci_ss_list_1002_7246 NULL +#define pci_ss_list_1002_7247 NULL +#define pci_ss_list_1002_7248 NULL +#define pci_ss_list_1002_7249 NULL +#define pci_ss_list_1002_724a NULL +#define pci_ss_list_1002_724b NULL +#define pci_ss_list_1002_724c NULL +#define pci_ss_list_1002_724d NULL +#define pci_ss_list_1002_724e NULL +#define pci_ss_list_1002_7269 NULL +#define pci_ss_list_1002_726e NULL +#define pci_ss_list_1002_7833 NULL +#define pci_ss_list_1002_7834 NULL +#define pci_ss_list_1002_7835 NULL +#define pci_ss_list_1002_7838 NULL +#define pci_ss_list_1002_7c37 NULL +#define pci_ss_list_1002_cab0 NULL +#define pci_ss_list_1002_cab2 NULL +#define pci_ss_list_1002_cab3 NULL +#define pci_ss_list_1002_cbb2 NULL +#define pci_ss_list_1003_0201 NULL +#define pci_ss_list_1004_0005 NULL +#define pci_ss_list_1004_0006 NULL +#define pci_ss_list_1004_0007 NULL +#define pci_ss_list_1004_0008 NULL +#define pci_ss_list_1004_0009 NULL +#define pci_ss_list_1004_000c NULL +#define pci_ss_list_1004_000d NULL +#define pci_ss_list_1004_0101 NULL +#define pci_ss_list_1004_0102 NULL +#define pci_ss_list_1004_0103 NULL +#define pci_ss_list_1004_0104 NULL +#define pci_ss_list_1004_0105 NULL +#define pci_ss_list_1004_0200 NULL +#define pci_ss_list_1004_0280 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1004_0304[] = { + &pci_ss_info_1004_0304_1004_0304, + &pci_ss_info_1004_0304_122d_1206, + &pci_ss_info_1004_0304_1483_5020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1004_0305[] = { + &pci_ss_info_1004_0305_1004_0305, + &pci_ss_info_1004_0305_122d_1207, + &pci_ss_info_1004_0305_1483_5021, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1004_0306[] = { + &pci_ss_info_1004_0306_1004_0306, + &pci_ss_info_1004_0306_122d_1208, + &pci_ss_info_1004_0306_1483_5022, + NULL +}; +#define pci_ss_list_1004_0307 NULL +#define pci_ss_list_1004_0308 NULL +#define pci_ss_list_1004_0702 NULL +#define pci_ss_list_1004_0703 NULL +#endif +#define pci_ss_list_1005_2064 NULL +#define pci_ss_list_1005_2128 NULL +#define pci_ss_list_1005_2301 NULL +#define pci_ss_list_1005_2302 NULL +#define pci_ss_list_1005_2364 NULL +#define pci_ss_list_1005_2464 NULL +#define pci_ss_list_1005_2501 NULL +#define pci_ss_list_100b_0001 NULL +#define pci_ss_list_100b_0002 NULL +#define pci_ss_list_100b_000e NULL +#define pci_ss_list_100b_000f NULL +#define pci_ss_list_100b_0011 NULL +#define pci_ss_list_100b_0012 NULL +static const pciSubsystemInfo *pci_ss_list_100b_0020[] = { + &pci_ss_info_100b_0020_103c_0024, + &pci_ss_info_100b_0020_12d9_000c, + &pci_ss_info_100b_0020_1385_f311, + NULL +}; +#define pci_ss_list_100b_0021 NULL +#define pci_ss_list_100b_0022 NULL +#define pci_ss_list_100b_0028 NULL +#define pci_ss_list_100b_002a NULL +#define pci_ss_list_100b_002b NULL +#define pci_ss_list_100b_002d NULL +#define pci_ss_list_100b_002e NULL +#define pci_ss_list_100b_002f NULL +#define pci_ss_list_100b_0030 NULL +#define pci_ss_list_100b_0035 NULL +#define pci_ss_list_100b_0500 NULL +#define pci_ss_list_100b_0501 NULL +#define pci_ss_list_100b_0502 NULL +#define pci_ss_list_100b_0503 NULL +#define pci_ss_list_100b_0504 NULL +#define pci_ss_list_100b_0505 NULL +#define pci_ss_list_100b_0510 NULL +#define pci_ss_list_100b_0511 NULL +#define pci_ss_list_100b_0515 NULL +#define pci_ss_list_100b_d001 NULL +#define pci_ss_list_100c_3202 NULL +#define pci_ss_list_100c_3205 NULL +#define pci_ss_list_100c_3206 NULL +#define pci_ss_list_100c_3207 NULL +#define pci_ss_list_100c_3208 NULL +#define pci_ss_list_100c_4702 NULL +#define pci_ss_list_100e_9000 NULL +#define pci_ss_list_100e_9001 NULL +#define pci_ss_list_100e_9002 NULL +#define pci_ss_list_100e_9100 NULL +#define pci_ss_list_1011_0001 NULL +#define pci_ss_list_1011_0002 NULL +#define pci_ss_list_1011_0004 NULL +#define pci_ss_list_1011_0007 NULL +#define pci_ss_list_1011_0008 NULL +static const pciSubsystemInfo *pci_ss_list_1011_0009[] = { + &pci_ss_info_1011_0009_1025_0310, + &pci_ss_info_1011_0009_10b8_2001, + &pci_ss_info_1011_0009_10b8_2002, + &pci_ss_info_1011_0009_10b8_2003, + &pci_ss_info_1011_0009_1109_2400, + &pci_ss_info_1011_0009_1112_2300, + &pci_ss_info_1011_0009_1112_2320, + &pci_ss_info_1011_0009_1112_2340, + &pci_ss_info_1011_0009_1113_1207, + &pci_ss_info_1011_0009_1186_1100, + &pci_ss_info_1011_0009_1186_1112, + &pci_ss_info_1011_0009_1186_1140, + &pci_ss_info_1011_0009_1186_1142, + &pci_ss_info_1011_0009_11f6_0503, + &pci_ss_info_1011_0009_1282_9100, + &pci_ss_info_1011_0009_1385_1100, + &pci_ss_info_1011_0009_2646_0001, + NULL +}; +#define pci_ss_list_1011_000a NULL +#define pci_ss_list_1011_000d NULL +static const pciSubsystemInfo *pci_ss_list_1011_000f[] = { + &pci_ss_info_1011_000f_1011_def1, + &pci_ss_info_1011_000f_103c_def1, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1011_0014[] = { + &pci_ss_info_1011_0014_1186_0100, + NULL +}; +#define pci_ss_list_1011_0016 NULL +#define pci_ss_list_1011_0017 NULL +static const pciSubsystemInfo *pci_ss_list_1011_0019[] = { + &pci_ss_info_1011_0019_1011_500a, + &pci_ss_info_1011_0019_1011_500b, + &pci_ss_info_1011_0019_1014_0001, + &pci_ss_info_1011_0019_1025_0315, + &pci_ss_info_1011_0019_1033_800c, + &pci_ss_info_1011_0019_1033_800d, + &pci_ss_info_1011_0019_103c_125a, + &pci_ss_info_1011_0019_108d_0016, + &pci_ss_info_1011_0019_108d_0017, + &pci_ss_info_1011_0019_10b8_2005, + &pci_ss_info_1011_0019_10b8_8034, + &pci_ss_info_1011_0019_10ef_8169, + &pci_ss_info_1011_0019_1109_2a00, + &pci_ss_info_1011_0019_1109_2b00, + &pci_ss_info_1011_0019_1109_3000, + &pci_ss_info_1011_0019_1113_1207, + &pci_ss_info_1011_0019_1113_2220, + &pci_ss_info_1011_0019_115d_0002, + &pci_ss_info_1011_0019_1179_0203, + &pci_ss_info_1011_0019_1179_0204, + &pci_ss_info_1011_0019_1186_1100, + &pci_ss_info_1011_0019_1186_1101, + &pci_ss_info_1011_0019_1186_1102, + &pci_ss_info_1011_0019_1186_1112, + &pci_ss_info_1011_0019_1259_2800, + &pci_ss_info_1011_0019_1266_0004, + &pci_ss_info_1011_0019_12af_0019, + &pci_ss_info_1011_0019_1374_0001, + &pci_ss_info_1011_0019_1374_0002, + &pci_ss_info_1011_0019_1374_0007, + &pci_ss_info_1011_0019_1374_0008, + &pci_ss_info_1011_0019_1385_2100, + &pci_ss_info_1011_0019_1395_0001, + &pci_ss_info_1011_0019_13d1_ab01, + &pci_ss_info_1011_0019_1498_000a, + &pci_ss_info_1011_0019_1498_000b, + &pci_ss_info_1011_0019_1498_000c, + &pci_ss_info_1011_0019_14cb_0100, + &pci_ss_info_1011_0019_8086_0001, + NULL +}; +#define pci_ss_list_1011_001a NULL +#define pci_ss_list_1011_0021 NULL +#define pci_ss_list_1011_0022 NULL +#define pci_ss_list_1011_0023 NULL +#define pci_ss_list_1011_0024 NULL +#define pci_ss_list_1011_0025 NULL +#define pci_ss_list_1011_0026 NULL +static const pciSubsystemInfo *pci_ss_list_1011_0034[] = { + &pci_ss_info_1011_0034_1374_0003, + NULL +}; +#define pci_ss_list_1011_0045 NULL +static const pciSubsystemInfo *pci_ss_list_1011_0046[] = { + &pci_ss_info_1011_0046_0e11_4050, + &pci_ss_info_1011_0046_0e11_4051, + &pci_ss_info_1011_0046_0e11_4058, + &pci_ss_info_1011_0046_103c_10c2, + &pci_ss_info_1011_0046_12d9_000a, + &pci_ss_info_1011_0046_4c53_1050, + &pci_ss_info_1011_0046_4c53_1051, + &pci_ss_info_1011_0046_9005_0364, + &pci_ss_info_1011_0046_9005_0365, + &pci_ss_info_1011_0046_9005_1364, + &pci_ss_info_1011_0046_9005_1365, + &pci_ss_info_1011_0046_e4bf_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1011_1065[] = { + &pci_ss_info_1011_1065_1069_0020, + NULL +}; +#define pci_ss_list_1013_0038 NULL +#define pci_ss_list_1013_0040 NULL +#define pci_ss_list_1013_004c NULL +#define pci_ss_list_1013_00a0 NULL +#define pci_ss_list_1013_00a2 NULL +#define pci_ss_list_1013_00a4 NULL +#define pci_ss_list_1013_00a8 NULL +#define pci_ss_list_1013_00ac NULL +#define pci_ss_list_1013_00b0 NULL +#define pci_ss_list_1013_00b8 NULL +static const pciSubsystemInfo *pci_ss_list_1013_00bc[] = { + &pci_ss_info_1013_00bc_1013_00bc, + NULL +}; +#define pci_ss_list_1013_00d0 NULL +#define pci_ss_list_1013_00d2 NULL +#define pci_ss_list_1013_00d4 NULL +#define pci_ss_list_1013_00d5 NULL +static const pciSubsystemInfo *pci_ss_list_1013_00d6[] = { + &pci_ss_info_1013_00d6_13ce_8031, + &pci_ss_info_1013_00d6_13cf_8031, + NULL +}; +#define pci_ss_list_1013_00e8 NULL +#define pci_ss_list_1013_1100 NULL +#define pci_ss_list_1013_1110 NULL +#define pci_ss_list_1013_1112 NULL +#define pci_ss_list_1013_1113 NULL +#define pci_ss_list_1013_1200 NULL +#define pci_ss_list_1013_1202 NULL +#define pci_ss_list_1013_1204 NULL +#define pci_ss_list_1013_4000 NULL +#define pci_ss_list_1013_4400 NULL +static const pciSubsystemInfo *pci_ss_list_1013_6001[] = { + &pci_ss_info_1013_6001_1014_1010, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1013_6003[] = { + &pci_ss_info_1013_6003_1013_4280, + &pci_ss_info_1013_6003_1014_0153, + &pci_ss_info_1013_6003_153b_112e, + &pci_ss_info_1013_6003_153b_1136, + &pci_ss_info_1013_6003_1681_0050, + &pci_ss_info_1013_6003_1681_a011, + &pci_ss_info_1013_6003_5053_3357, + NULL +}; +#define pci_ss_list_1013_6004 NULL +static const pciSubsystemInfo *pci_ss_list_1013_6005[] = { + &pci_ss_info_1013_6005_1013_4281, + &pci_ss_info_1013_6005_10cf_10a8, + &pci_ss_info_1013_6005_10cf_10a9, + &pci_ss_info_1013_6005_10cf_10aa, + &pci_ss_info_1013_6005_10cf_10ab, + &pci_ss_info_1013_6005_10cf_10ac, + &pci_ss_info_1013_6005_10cf_10ad, + &pci_ss_info_1013_6005_10cf_10b4, + &pci_ss_info_1013_6005_1179_0001, + &pci_ss_info_1013_6005_14c0_000c, + NULL +}; +#define pci_ss_list_1014_0002 NULL +#define pci_ss_list_1014_0005 NULL +#define pci_ss_list_1014_0007 NULL +#define pci_ss_list_1014_000a NULL +#define pci_ss_list_1014_0017 NULL +#define pci_ss_list_1014_0018 NULL +#define pci_ss_list_1014_001b NULL +#define pci_ss_list_1014_001c NULL +#define pci_ss_list_1014_001d NULL +#define pci_ss_list_1014_0020 NULL +#define pci_ss_list_1014_0022 NULL +#define pci_ss_list_1014_002d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1014_002e[] = { + &pci_ss_info_1014_002e_1014_002e, + &pci_ss_info_1014_002e_1014_022e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1014_0031[] = { + &pci_ss_info_1014_0031_1014_0031, + NULL +}; +#define pci_ss_list_1014_0036 NULL +#define pci_ss_list_1014_0037 NULL +#define pci_ss_list_1014_003a NULL +#define pci_ss_list_1014_003c NULL +static const pciSubsystemInfo *pci_ss_list_1014_003e[] = { + &pci_ss_info_1014_003e_1014_003e, + &pci_ss_info_1014_003e_1014_00cd, + &pci_ss_info_1014_003e_1014_00ce, + &pci_ss_info_1014_003e_1014_00cf, + &pci_ss_info_1014_003e_1014_00e4, + &pci_ss_info_1014_003e_1014_00e5, + &pci_ss_info_1014_003e_1014_016d, + NULL +}; +#define pci_ss_list_1014_0045 NULL +#define pci_ss_list_1014_0046 NULL +#define pci_ss_list_1014_0047 NULL +#define pci_ss_list_1014_0048 NULL +#define pci_ss_list_1014_0049 NULL +#define pci_ss_list_1014_004e NULL +#define pci_ss_list_1014_004f NULL +#define pci_ss_list_1014_0050 NULL +#define pci_ss_list_1014_0053 NULL +#define pci_ss_list_1014_0054 NULL +#define pci_ss_list_1014_0057 NULL +#define pci_ss_list_1014_0058 NULL +#define pci_ss_list_1014_005c NULL +#define pci_ss_list_1014_005e NULL +#define pci_ss_list_1014_007c NULL +#define pci_ss_list_1014_007d NULL +#define pci_ss_list_1014_008b NULL +#define pci_ss_list_1014_008e NULL +static const pciSubsystemInfo *pci_ss_list_1014_0090[] = { + &pci_ss_info_1014_0090_1014_008e, + NULL +}; +#define pci_ss_list_1014_0091 NULL +#define pci_ss_list_1014_0095 NULL +static const pciSubsystemInfo *pci_ss_list_1014_0096[] = { + &pci_ss_info_1014_0096_1014_0097, + &pci_ss_info_1014_0096_1014_0098, + &pci_ss_info_1014_0096_1014_0099, + NULL +}; +#define pci_ss_list_1014_009f NULL +#define pci_ss_list_1014_00a5 NULL +#define pci_ss_list_1014_00a6 NULL +static const pciSubsystemInfo *pci_ss_list_1014_00b7[] = { + &pci_ss_info_1014_00b7_1092_00b8, + NULL +}; +#define pci_ss_list_1014_00b8 NULL +#define pci_ss_list_1014_00be NULL +#define pci_ss_list_1014_00dc NULL +#define pci_ss_list_1014_00fc NULL +#define pci_ss_list_1014_0104 NULL +#define pci_ss_list_1014_0105 NULL +#define pci_ss_list_1014_010f NULL +static const pciSubsystemInfo *pci_ss_list_1014_0142[] = { + &pci_ss_info_1014_0142_1014_0143, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1014_0144[] = { + &pci_ss_info_1014_0144_1014_0145, + NULL +}; +#define pci_ss_list_1014_0156 NULL +#define pci_ss_list_1014_015e NULL +#define pci_ss_list_1014_0160 NULL +#define pci_ss_list_1014_016e NULL +#define pci_ss_list_1014_0170 NULL +#define pci_ss_list_1014_017d NULL +static const pciSubsystemInfo *pci_ss_list_1014_0180[] = { + &pci_ss_info_1014_0180_1014_0241, + &pci_ss_info_1014_0180_1014_0264, + NULL +}; +#define pci_ss_list_1014_0188 NULL +#define pci_ss_list_1014_01a7 NULL +static const pciSubsystemInfo *pci_ss_list_1014_01bd[] = { + &pci_ss_info_1014_01bd_1014_01be, + &pci_ss_info_1014_01bd_1014_01bf, + &pci_ss_info_1014_01bd_1014_0208, + &pci_ss_info_1014_01bd_1014_020e, + &pci_ss_info_1014_01bd_1014_022e, + &pci_ss_info_1014_01bd_1014_0258, + &pci_ss_info_1014_01bd_1014_0259, + NULL +}; +#define pci_ss_list_1014_01c1 NULL +#define pci_ss_list_1014_01e6 NULL +#define pci_ss_list_1014_01ff NULL +static const pciSubsystemInfo *pci_ss_list_1014_0219[] = { + &pci_ss_info_1014_0219_1014_021a, + &pci_ss_info_1014_0219_1014_0251, + &pci_ss_info_1014_0219_1014_0252, + NULL +}; +#define pci_ss_list_1014_021b NULL +#define pci_ss_list_1014_021c NULL +#define pci_ss_list_1014_0233 NULL +#define pci_ss_list_1014_0266 NULL +#define pci_ss_list_1014_0268 NULL +#define pci_ss_list_1014_0269 NULL +static const pciSubsystemInfo *pci_ss_list_1014_028c[] = { + &pci_ss_info_1014_028c_1014_028d, + &pci_ss_info_1014_028c_1014_02be, + &pci_ss_info_1014_028c_1014_02c0, + &pci_ss_info_1014_028c_1014_030d, + NULL +}; +#define pci_ss_list_1014_02a1 NULL +static const pciSubsystemInfo *pci_ss_list_1014_02bd[] = { + &pci_ss_info_1014_02bd_1014_02c1, + &pci_ss_info_1014_02bd_1014_02c2, + NULL +}; +#define pci_ss_list_1014_0302 NULL +#define pci_ss_list_1014_0308 NULL +#define pci_ss_list_1014_0314 NULL +#define pci_ss_list_1014_3022 NULL +#define pci_ss_list_1014_4022 NULL +#define pci_ss_list_1014_ffff NULL +#endif +#define pci_ss_list_1017_5343 NULL +#define pci_ss_list_101a_0005 NULL +#define pci_ss_list_101c_0193 NULL +#define pci_ss_list_101c_0196 NULL +#define pci_ss_list_101c_0197 NULL +#define pci_ss_list_101c_0296 NULL +#define pci_ss_list_101c_3193 NULL +#define pci_ss_list_101c_3197 NULL +#define pci_ss_list_101c_3296 NULL +#define pci_ss_list_101c_4296 NULL +#define pci_ss_list_101c_9710 NULL +#define pci_ss_list_101c_9712 NULL +#define pci_ss_list_101c_c24a NULL +#define pci_ss_list_101e_0009 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_101e_1960[] = { + &pci_ss_info_101e_1960_101e_0471, + &pci_ss_info_101e_1960_101e_0475, + &pci_ss_info_101e_1960_101e_0477, + &pci_ss_info_101e_1960_101e_0493, + &pci_ss_info_101e_1960_101e_0494, + &pci_ss_info_101e_1960_101e_0503, + &pci_ss_info_101e_1960_101e_0511, + &pci_ss_info_101e_1960_101e_0522, + &pci_ss_info_101e_1960_1028_0471, + &pci_ss_info_101e_1960_1028_0475, + &pci_ss_info_101e_1960_1028_0493, + &pci_ss_info_101e_1960_1028_0511, + &pci_ss_info_101e_1960_103c_60e7, + NULL +}; +#define pci_ss_list_101e_9010 NULL +#define pci_ss_list_101e_9030 NULL +#define pci_ss_list_101e_9031 NULL +#define pci_ss_list_101e_9032 NULL +#define pci_ss_list_101e_9033 NULL +#define pci_ss_list_101e_9040 NULL +#define pci_ss_list_101e_9060 NULL +static const pciSubsystemInfo *pci_ss_list_101e_9063[] = { + &pci_ss_info_101e_9063_101e_0767, + NULL +}; +#endif +#define pci_ss_list_1022_1100 NULL +#define pci_ss_list_1022_1101 NULL +#define pci_ss_list_1022_1102 NULL +#define pci_ss_list_1022_1103 NULL +static const pciSubsystemInfo *pci_ss_list_1022_2000[] = { + &pci_ss_info_1022_2000_1014_2000, + &pci_ss_info_1022_2000_1022_2000, + &pci_ss_info_1022_2000_103c_104c, + &pci_ss_info_1022_2000_103c_1064, + &pci_ss_info_1022_2000_103c_1065, + &pci_ss_info_1022_2000_103c_106c, + &pci_ss_info_1022_2000_103c_106e, + &pci_ss_info_1022_2000_103c_10ea, + &pci_ss_info_1022_2000_1113_1220, + &pci_ss_info_1022_2000_1259_2450, + &pci_ss_info_1022_2000_1259_2454, + &pci_ss_info_1022_2000_1259_2700, + &pci_ss_info_1022_2000_1259_2701, + &pci_ss_info_1022_2000_1259_2702, + &pci_ss_info_1022_2000_1259_2703, + &pci_ss_info_1022_2000_1259_2704, + &pci_ss_info_1022_2000_4c53_1000, + &pci_ss_info_1022_2000_4c53_1010, + &pci_ss_info_1022_2000_4c53_1020, + &pci_ss_info_1022_2000_4c53_1030, + &pci_ss_info_1022_2000_4c53_1040, + &pci_ss_info_1022_2000_4c53_1060, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1022_2001[] = { + &pci_ss_info_1022_2001_1092_0a78, + &pci_ss_info_1022_2001_1668_0299, + NULL +}; +#define pci_ss_list_1022_2003 NULL +#define pci_ss_list_1022_2020 NULL +#define pci_ss_list_1022_2040 NULL +#define pci_ss_list_1022_2081 NULL +#define pci_ss_list_1022_2082 NULL +#define pci_ss_list_1022_208f NULL +#define pci_ss_list_1022_2090 NULL +#define pci_ss_list_1022_2091 NULL +#define pci_ss_list_1022_2093 NULL +#define pci_ss_list_1022_2094 NULL +#define pci_ss_list_1022_2095 NULL +#define pci_ss_list_1022_2096 NULL +#define pci_ss_list_1022_2097 NULL +#define pci_ss_list_1022_209a NULL +#define pci_ss_list_1022_3000 NULL +#define pci_ss_list_1022_7006 NULL +#define pci_ss_list_1022_7007 NULL +#define pci_ss_list_1022_700a NULL +#define pci_ss_list_1022_700b NULL +#define pci_ss_list_1022_700c NULL +#define pci_ss_list_1022_700d NULL +#define pci_ss_list_1022_700e NULL +#define pci_ss_list_1022_700f NULL +#define pci_ss_list_1022_7400 NULL +#define pci_ss_list_1022_7401 NULL +#define pci_ss_list_1022_7403 NULL +#define pci_ss_list_1022_7404 NULL +#define pci_ss_list_1022_7408 NULL +#define pci_ss_list_1022_7409 NULL +#define pci_ss_list_1022_740b NULL +#define pci_ss_list_1022_740c NULL +#define pci_ss_list_1022_7410 NULL +#define pci_ss_list_1022_7411 NULL +#define pci_ss_list_1022_7413 NULL +#define pci_ss_list_1022_7414 NULL +static const pciSubsystemInfo *pci_ss_list_1022_7440[] = { + &pci_ss_info_1022_7440_1043_8044, + NULL +}; +#define pci_ss_list_1022_7441 NULL +static const pciSubsystemInfo *pci_ss_list_1022_7443[] = { + &pci_ss_info_1022_7443_1043_8044, + NULL +}; +#define pci_ss_list_1022_7445 NULL +#define pci_ss_list_1022_7446 NULL +#define pci_ss_list_1022_7448 NULL +#define pci_ss_list_1022_7449 NULL +#define pci_ss_list_1022_7450 NULL +#define pci_ss_list_1022_7451 NULL +#define pci_ss_list_1022_7454 NULL +#define pci_ss_list_1022_7455 NULL +#define pci_ss_list_1022_7458 NULL +#define pci_ss_list_1022_7459 NULL +static const pciSubsystemInfo *pci_ss_list_1022_7460[] = { + &pci_ss_info_1022_7460_161f_3017, + NULL +}; +#define pci_ss_list_1022_7461 NULL +#define pci_ss_list_1022_7462 NULL +static const pciSubsystemInfo *pci_ss_list_1022_7464[] = { + &pci_ss_info_1022_7464_161f_3017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1022_7468[] = { + &pci_ss_info_1022_7468_161f_3017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1022_7469[] = { + &pci_ss_info_1022_7469_1022_2b80, + &pci_ss_info_1022_7469_161f_3017, + NULL +}; +#define pci_ss_list_1022_746a NULL +static const pciSubsystemInfo *pci_ss_list_1022_746b[] = { + &pci_ss_info_1022_746b_161f_3017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1022_746d[] = { + &pci_ss_info_1022_746d_161f_3017, + NULL +}; +#define pci_ss_list_1022_746e NULL +#define pci_ss_list_1022_756b NULL +#define pci_ss_list_1023_0194 NULL +#define pci_ss_list_1023_2000 NULL +static const pciSubsystemInfo *pci_ss_list_1023_2001[] = { + &pci_ss_info_1023_2001_122d_1400, + NULL +}; +#define pci_ss_list_1023_2100 NULL +#define pci_ss_list_1023_2200 NULL +static const pciSubsystemInfo *pci_ss_list_1023_8400[] = { + &pci_ss_info_1023_8400_1023_8400, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1023_8420[] = { + &pci_ss_info_1023_8420_0e11_b15a, + NULL +}; +#define pci_ss_list_1023_8500 NULL +static const pciSubsystemInfo *pci_ss_list_1023_8520[] = { + &pci_ss_info_1023_8520_0e11_b16e, + &pci_ss_info_1023_8520_1023_8520, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1023_8620[] = { + &pci_ss_info_1023_8620_1014_0502, + &pci_ss_info_1023_8620_1014_1025, + NULL +}; +#define pci_ss_list_1023_8820 NULL +#define pci_ss_list_1023_9320 NULL +#define pci_ss_list_1023_9350 NULL +#define pci_ss_list_1023_9360 NULL +#define pci_ss_list_1023_9382 NULL +#define pci_ss_list_1023_9383 NULL +#define pci_ss_list_1023_9385 NULL +#define pci_ss_list_1023_9386 NULL +#define pci_ss_list_1023_9388 NULL +#define pci_ss_list_1023_9397 NULL +#define pci_ss_list_1023_939a NULL +#define pci_ss_list_1023_9420 NULL +#define pci_ss_list_1023_9430 NULL +#define pci_ss_list_1023_9440 NULL +#define pci_ss_list_1023_9460 NULL +#define pci_ss_list_1023_9470 NULL +#define pci_ss_list_1023_9520 NULL +static const pciSubsystemInfo *pci_ss_list_1023_9525[] = { + &pci_ss_info_1023_9525_10cf_1094, + NULL +}; +#define pci_ss_list_1023_9540 NULL +#define pci_ss_list_1023_9660 NULL +#define pci_ss_list_1023_9680 NULL +#define pci_ss_list_1023_9682 NULL +#define pci_ss_list_1023_9683 NULL +#define pci_ss_list_1023_9685 NULL +static const pciSubsystemInfo *pci_ss_list_1023_9750[] = { + &pci_ss_info_1023_9750_1014_9750, + &pci_ss_info_1023_9750_1023_9750, + NULL +}; +#define pci_ss_list_1023_9753 NULL +#define pci_ss_list_1023_9754 NULL +#define pci_ss_list_1023_9759 NULL +#define pci_ss_list_1023_9783 NULL +#define pci_ss_list_1023_9785 NULL +#define pci_ss_list_1023_9850 NULL +static const pciSubsystemInfo *pci_ss_list_1023_9880[] = { + &pci_ss_info_1023_9880_1023_9880, + NULL +}; +#define pci_ss_list_1023_9910 NULL +#define pci_ss_list_1023_9930 NULL +#define pci_ss_list_1025_0090 NULL +#define pci_ss_list_1025_1435 NULL +#define pci_ss_list_1025_1445 NULL +#define pci_ss_list_1025_1449 NULL +#define pci_ss_list_1025_1451 NULL +#define pci_ss_list_1025_1461 NULL +#define pci_ss_list_1025_1489 NULL +#define pci_ss_list_1025_1511 NULL +#define pci_ss_list_1025_1512 NULL +#define pci_ss_list_1025_1513 NULL +static const pciSubsystemInfo *pci_ss_list_1025_1521[] = { + &pci_ss_info_1025_1521_10b9_1521, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1025_1523[] = { + &pci_ss_info_1025_1523_10b9_1523, + NULL +}; +#define pci_ss_list_1025_1531 NULL +static const pciSubsystemInfo *pci_ss_list_1025_1533[] = { + &pci_ss_info_1025_1533_10b9_1533, + NULL +}; +#define pci_ss_list_1025_1535 NULL +static const pciSubsystemInfo *pci_ss_list_1025_1541[] = { + &pci_ss_info_1025_1541_10b9_1541, + NULL +}; +#define pci_ss_list_1025_1542 NULL +#define pci_ss_list_1025_1543 NULL +#define pci_ss_list_1025_1561 NULL +#define pci_ss_list_1025_1621 NULL +#define pci_ss_list_1025_1631 NULL +#define pci_ss_list_1025_1641 NULL +#define pci_ss_list_1025_1647 NULL +#define pci_ss_list_1025_1671 NULL +#define pci_ss_list_1025_1672 NULL +#define pci_ss_list_1025_3141 NULL +#define pci_ss_list_1025_3143 NULL +#define pci_ss_list_1025_3145 NULL +#define pci_ss_list_1025_3147 NULL +#define pci_ss_list_1025_3149 NULL +#define pci_ss_list_1025_3151 NULL +#define pci_ss_list_1025_3307 NULL +#define pci_ss_list_1025_3309 NULL +#define pci_ss_list_1025_3321 NULL +#define pci_ss_list_1025_5212 NULL +#define pci_ss_list_1025_5215 NULL +#define pci_ss_list_1025_5217 NULL +#define pci_ss_list_1025_5219 NULL +#define pci_ss_list_1025_5225 NULL +#define pci_ss_list_1025_5229 NULL +#define pci_ss_list_1025_5235 NULL +#define pci_ss_list_1025_5237 NULL +#define pci_ss_list_1025_5240 NULL +#define pci_ss_list_1025_5241 NULL +#define pci_ss_list_1025_5242 NULL +#define pci_ss_list_1025_5243 NULL +#define pci_ss_list_1025_5244 NULL +#define pci_ss_list_1025_5247 NULL +#define pci_ss_list_1025_5251 NULL +#define pci_ss_list_1025_5427 NULL +#define pci_ss_list_1025_5451 NULL +#define pci_ss_list_1025_5453 NULL +static const pciSubsystemInfo *pci_ss_list_1025_7101[] = { + &pci_ss_info_1025_7101_10b9_7101, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1028_0001[] = { + &pci_ss_info_1028_0001_1028_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1028_0002[] = { + &pci_ss_info_1028_0002_1028_0002, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1028_0003[] = { + &pci_ss_info_1028_0003_1028_0003, + NULL +}; +#define pci_ss_list_1028_0006 NULL +#define pci_ss_list_1028_0007 NULL +#define pci_ss_list_1028_0008 NULL +#define pci_ss_list_1028_0009 NULL +#define pci_ss_list_1028_000a NULL +#define pci_ss_list_1028_000c NULL +#define pci_ss_list_1028_000d NULL +#define pci_ss_list_1028_000e NULL +#define pci_ss_list_1028_000f NULL +#define pci_ss_list_1028_0010 NULL +#define pci_ss_list_1028_0011 NULL +#define pci_ss_list_1028_0012 NULL +static const pciSubsystemInfo *pci_ss_list_1028_0013[] = { + &pci_ss_info_1028_0013_1028_016c, + &pci_ss_info_1028_0013_1028_016d, + &pci_ss_info_1028_0013_1028_016e, + &pci_ss_info_1028_0013_1028_016f, + &pci_ss_info_1028_0013_1028_0170, + NULL +}; +#define pci_ss_list_1028_0014 NULL +#define pci_ss_list_1028_0015 NULL +#define pci_ss_list_102a_0000 NULL +#define pci_ss_list_102a_0010 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_102a_001f[] = { + &pci_ss_info_102a_001f_9005_000f, + &pci_ss_info_102a_001f_9005_0106, + &pci_ss_info_102a_001f_9005_a180, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102a_00c5[] = { + &pci_ss_info_102a_00c5_1028_00c5, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102a_00cf[] = { + &pci_ss_info_102a_00cf_1028_0106, + &pci_ss_info_102a_00cf_1028_0121, + NULL +}; +#endif +#define pci_ss_list_102b_0010 NULL +#define pci_ss_list_102b_0100 NULL +#define pci_ss_list_102b_0518 NULL +#define pci_ss_list_102b_0519 NULL +static const pciSubsystemInfo *pci_ss_list_102b_051a[] = { + &pci_ss_info_102b_051a_102b_0100, + &pci_ss_info_102b_051a_102b_1100, + &pci_ss_info_102b_051a_102b_1200, + &pci_ss_info_102b_051a_1100_102b, + &pci_ss_info_102b_051a_110a_0018, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_051b[] = { + &pci_ss_info_102b_051b_102b_051b, + &pci_ss_info_102b_051b_102b_1100, + &pci_ss_info_102b_051b_102b_1200, + NULL +}; +#define pci_ss_list_102b_051e NULL +#define pci_ss_list_102b_051f NULL +static const pciSubsystemInfo *pci_ss_list_102b_0520[] = { + &pci_ss_info_102b_0520_102b_dbc2, + &pci_ss_info_102b_0520_102b_dbc8, + &pci_ss_info_102b_0520_102b_dbe2, + &pci_ss_info_102b_0520_102b_dbe8, + &pci_ss_info_102b_0520_102b_ff03, + &pci_ss_info_102b_0520_102b_ff04, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_0521[] = { + &pci_ss_info_102b_0521_1014_ff03, + &pci_ss_info_102b_0521_102b_48e9, + &pci_ss_info_102b_0521_102b_48f8, + &pci_ss_info_102b_0521_102b_4a60, + &pci_ss_info_102b_0521_102b_4a64, + &pci_ss_info_102b_0521_102b_c93c, + &pci_ss_info_102b_0521_102b_c9b0, + &pci_ss_info_102b_0521_102b_c9bc, + &pci_ss_info_102b_0521_102b_ca60, + &pci_ss_info_102b_0521_102b_ca6c, + &pci_ss_info_102b_0521_102b_dbbc, + &pci_ss_info_102b_0521_102b_dbc2, + &pci_ss_info_102b_0521_102b_dbc3, + &pci_ss_info_102b_0521_102b_dbc8, + &pci_ss_info_102b_0521_102b_dbd2, + &pci_ss_info_102b_0521_102b_dbd3, + &pci_ss_info_102b_0521_102b_dbd4, + &pci_ss_info_102b_0521_102b_dbd5, + &pci_ss_info_102b_0521_102b_dbd8, + &pci_ss_info_102b_0521_102b_dbd9, + &pci_ss_info_102b_0521_102b_dbe2, + &pci_ss_info_102b_0521_102b_dbe3, + &pci_ss_info_102b_0521_102b_dbe8, + &pci_ss_info_102b_0521_102b_dbf2, + &pci_ss_info_102b_0521_102b_dbf3, + &pci_ss_info_102b_0521_102b_dbf4, + &pci_ss_info_102b_0521_102b_dbf5, + &pci_ss_info_102b_0521_102b_dbf8, + &pci_ss_info_102b_0521_102b_dbf9, + &pci_ss_info_102b_0521_102b_f806, + &pci_ss_info_102b_0521_102b_ff00, + &pci_ss_info_102b_0521_102b_ff02, + &pci_ss_info_102b_0521_102b_ff03, + &pci_ss_info_102b_0521_102b_ff04, + &pci_ss_info_102b_0521_110a_0032, + NULL +}; +#define pci_ss_list_102b_0522 NULL +static const pciSubsystemInfo *pci_ss_list_102b_0525[] = { + &pci_ss_info_102b_0525_0e11_b16f, + &pci_ss_info_102b_0525_102b_0328, + &pci_ss_info_102b_0525_102b_0338, + &pci_ss_info_102b_0525_102b_0378, + &pci_ss_info_102b_0525_102b_0541, + &pci_ss_info_102b_0525_102b_0542, + &pci_ss_info_102b_0525_102b_0543, + &pci_ss_info_102b_0525_102b_0641, + &pci_ss_info_102b_0525_102b_0642, + &pci_ss_info_102b_0525_102b_0643, + &pci_ss_info_102b_0525_102b_07c0, + &pci_ss_info_102b_0525_102b_07c1, + &pci_ss_info_102b_0525_102b_0d41, + &pci_ss_info_102b_0525_102b_0d42, + &pci_ss_info_102b_0525_102b_0d43, + &pci_ss_info_102b_0525_102b_0e00, + &pci_ss_info_102b_0525_102b_0e01, + &pci_ss_info_102b_0525_102b_0e02, + &pci_ss_info_102b_0525_102b_0e03, + &pci_ss_info_102b_0525_102b_0f80, + &pci_ss_info_102b_0525_102b_0f81, + &pci_ss_info_102b_0525_102b_0f82, + &pci_ss_info_102b_0525_102b_0f83, + &pci_ss_info_102b_0525_102b_19d8, + &pci_ss_info_102b_0525_102b_19f8, + &pci_ss_info_102b_0525_102b_2159, + &pci_ss_info_102b_0525_102b_2179, + &pci_ss_info_102b_0525_102b_217d, + &pci_ss_info_102b_0525_102b_23c0, + &pci_ss_info_102b_0525_102b_23c1, + &pci_ss_info_102b_0525_102b_23c2, + &pci_ss_info_102b_0525_102b_23c3, + &pci_ss_info_102b_0525_102b_2f58, + &pci_ss_info_102b_0525_102b_2f78, + &pci_ss_info_102b_0525_102b_3693, + &pci_ss_info_102b_0525_102b_5dd0, + &pci_ss_info_102b_0525_102b_5f50, + &pci_ss_info_102b_0525_102b_5f51, + &pci_ss_info_102b_0525_102b_5f52, + &pci_ss_info_102b_0525_102b_9010, + &pci_ss_info_102b_0525_1458_0400, + &pci_ss_info_102b_0525_1705_0001, + &pci_ss_info_102b_0525_1705_0002, + &pci_ss_info_102b_0525_1705_0003, + &pci_ss_info_102b_0525_1705_0004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_0527[] = { + &pci_ss_info_102b_0527_102b_0840, + &pci_ss_info_102b_0527_102b_0850, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_0528[] = { + &pci_ss_info_102b_0528_102b_1020, + &pci_ss_info_102b_0528_102b_1030, + &pci_ss_info_102b_0528_102b_14e1, + &pci_ss_info_102b_0528_102b_2021, + NULL +}; +#define pci_ss_list_102b_0d10 NULL +static const pciSubsystemInfo *pci_ss_list_102b_1000[] = { + &pci_ss_info_102b_1000_102b_ff01, + &pci_ss_info_102b_1000_102b_ff05, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_1001[] = { + &pci_ss_info_102b_1001_102b_1001, + &pci_ss_info_102b_1001_102b_ff00, + &pci_ss_info_102b_1001_102b_ff01, + &pci_ss_info_102b_1001_102b_ff03, + &pci_ss_info_102b_1001_102b_ff04, + &pci_ss_info_102b_1001_102b_ff05, + &pci_ss_info_102b_1001_110a_001e, + NULL +}; +#define pci_ss_list_102b_2007 NULL +static const pciSubsystemInfo *pci_ss_list_102b_2527[] = { + &pci_ss_info_102b_2527_102b_0f83, + &pci_ss_info_102b_2527_102b_0f84, + &pci_ss_info_102b_2527_102b_1e41, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_2537[] = { + &pci_ss_info_102b_2537_102b_1820, + &pci_ss_info_102b_2537_102b_1830, + &pci_ss_info_102b_2537_102b_1c10, + &pci_ss_info_102b_2537_102b_2811, + &pci_ss_info_102b_2537_102b_2c11, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102b_2538[] = { + &pci_ss_info_102b_2538_102b_08c7, + &pci_ss_info_102b_2538_102b_0907, + &pci_ss_info_102b_2538_102b_1047, + &pci_ss_info_102b_2538_102b_1087, + &pci_ss_info_102b_2538_102b_2538, + &pci_ss_info_102b_2538_102b_3007, + NULL +}; +#define pci_ss_list_102b_4536 NULL +#define pci_ss_list_102b_4cdc NULL +#define pci_ss_list_102b_4fc5 NULL +#define pci_ss_list_102b_5e10 NULL +#define pci_ss_list_102b_6573 NULL +#define pci_ss_list_102c_00b8 NULL +static const pciSubsystemInfo *pci_ss_list_102c_00c0[] = { + &pci_ss_info_102c_00c0_102c_00c0, + &pci_ss_info_102c_00c0_4c53_1000, + &pci_ss_info_102c_00c0_4c53_1010, + &pci_ss_info_102c_00c0_4c53_1020, + &pci_ss_info_102c_00c0_4c53_1030, + &pci_ss_info_102c_00c0_4c53_1050, + &pci_ss_info_102c_00c0_4c53_1051, + NULL +}; +#define pci_ss_list_102c_00d0 NULL +#define pci_ss_list_102c_00d8 NULL +#define pci_ss_list_102c_00dc NULL +#define pci_ss_list_102c_00e0 NULL +#define pci_ss_list_102c_00e4 NULL +static const pciSubsystemInfo *pci_ss_list_102c_00e5[] = { + &pci_ss_info_102c_00e5_0e11_b049, + &pci_ss_info_102c_00e5_1179_0001, + NULL +}; +#define pci_ss_list_102c_00f0 NULL +#define pci_ss_list_102c_00f4 NULL +#define pci_ss_list_102c_00f5 NULL +static const pciSubsystemInfo *pci_ss_list_102c_0c30[] = { + &pci_ss_info_102c_0c30_4c53_1000, + &pci_ss_info_102c_0c30_4c53_1050, + &pci_ss_info_102c_0c30_4c53_1051, + &pci_ss_info_102c_0c30_4c53_1080, + NULL +}; +#define pci_ss_list_102d_50dc NULL +#define pci_ss_list_102f_0009 NULL +#define pci_ss_list_102f_000a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_102f_0020[] = { + &pci_ss_info_102f_0020_102f_00f8, + NULL +}; +#define pci_ss_list_102f_0030 NULL +#define pci_ss_list_102f_0031 NULL +#define pci_ss_list_102f_0105 NULL +#define pci_ss_list_102f_0106 NULL +#define pci_ss_list_102f_0107 NULL +#define pci_ss_list_102f_0108 NULL +#define pci_ss_list_102f_0180 NULL +#define pci_ss_list_102f_0181 NULL +#define pci_ss_list_102f_0182 NULL +#endif +#define pci_ss_list_1031_5601 NULL +#define pci_ss_list_1031_5607 NULL +#define pci_ss_list_1031_5631 NULL +#define pci_ss_list_1031_6057 NULL +#define pci_ss_list_1033_0000 NULL +#define pci_ss_list_1033_0001 NULL +#define pci_ss_list_1033_0002 NULL +#define pci_ss_list_1033_0003 NULL +#define pci_ss_list_1033_0004 NULL +#define pci_ss_list_1033_0005 NULL +#define pci_ss_list_1033_0006 NULL +#define pci_ss_list_1033_0007 NULL +#define pci_ss_list_1033_0008 NULL +#define pci_ss_list_1033_0009 NULL +#define pci_ss_list_1033_0016 NULL +#define pci_ss_list_1033_001a NULL +#define pci_ss_list_1033_0021 NULL +#define pci_ss_list_1033_0029 NULL +#define pci_ss_list_1033_002a NULL +#define pci_ss_list_1033_002c NULL +#define pci_ss_list_1033_002d NULL +static const pciSubsystemInfo *pci_ss_list_1033_0035[] = { + &pci_ss_info_1033_0035_1033_0035, + &pci_ss_info_1033_0035_1179_0001, + &pci_ss_info_1033_0035_12ee_7000, + &pci_ss_info_1033_0035_14c2_0105, + &pci_ss_info_1033_0035_1799_0001, + &pci_ss_info_1033_0035_1931_000a, + &pci_ss_info_1033_0035_1931_000b, + &pci_ss_info_1033_0035_807d_0035, + NULL +}; +#define pci_ss_list_1033_003b NULL +#define pci_ss_list_1033_003e NULL +#define pci_ss_list_1033_0046 NULL +#define pci_ss_list_1033_005a NULL +#define pci_ss_list_1033_0063 NULL +static const pciSubsystemInfo *pci_ss_list_1033_0067[] = { + &pci_ss_info_1033_0067_1010_0020, + &pci_ss_info_1033_0067_1010_0080, + &pci_ss_info_1033_0067_1010_0088, + &pci_ss_info_1033_0067_1010_0090, + &pci_ss_info_1033_0067_1010_0098, + &pci_ss_info_1033_0067_1010_00a0, + &pci_ss_info_1033_0067_1010_00a8, + &pci_ss_info_1033_0067_1010_0120, + NULL +}; +#define pci_ss_list_1033_0072 NULL +static const pciSubsystemInfo *pci_ss_list_1033_0074[] = { + &pci_ss_info_1033_0074_1033_8014, + NULL +}; +#define pci_ss_list_1033_009b NULL +#define pci_ss_list_1033_00a5 NULL +#define pci_ss_list_1033_00a6 NULL +static const pciSubsystemInfo *pci_ss_list_1033_00cd[] = { + &pci_ss_info_1033_00cd_12ee_8011, + NULL +}; +#define pci_ss_list_1033_00ce NULL +#define pci_ss_list_1033_00df NULL +static const pciSubsystemInfo *pci_ss_list_1033_00e0[] = { + &pci_ss_info_1033_00e0_12ee_7001, + &pci_ss_info_1033_00e0_14c2_0205, + &pci_ss_info_1033_00e0_1799_0002, + &pci_ss_info_1033_00e0_807d_1043, + NULL +}; +#define pci_ss_list_1033_00e7 NULL +#define pci_ss_list_1033_00f2 NULL +#define pci_ss_list_1033_00f3 NULL +#define pci_ss_list_1033_010c NULL +#define pci_ss_list_1033_0125 NULL +#define pci_ss_list_1033_013a NULL +#define pci_ss_list_1036_0000 NULL +#define pci_ss_list_1039_0001 NULL +#define pci_ss_list_1039_0002 NULL +#define pci_ss_list_1039_0003 NULL +#define pci_ss_list_1039_0004 NULL +#define pci_ss_list_1039_0006 NULL +#define pci_ss_list_1039_0008 NULL +#define pci_ss_list_1039_0009 NULL +#define pci_ss_list_1039_000a NULL +#define pci_ss_list_1039_0016 NULL +#define pci_ss_list_1039_0018 NULL +#define pci_ss_list_1039_0180 NULL +#define pci_ss_list_1039_0181 NULL +#define pci_ss_list_1039_0182 NULL +#define pci_ss_list_1039_0186 NULL +#define pci_ss_list_1039_0190 NULL +#define pci_ss_list_1039_0191 NULL +static const pciSubsystemInfo *pci_ss_list_1039_0200[] = { + &pci_ss_info_1039_0200_1039_0000, + NULL +}; +#define pci_ss_list_1039_0204 NULL +#define pci_ss_list_1039_0205 NULL +static const pciSubsystemInfo *pci_ss_list_1039_0300[] = { + &pci_ss_info_1039_0300_107d_2720, + NULL +}; +#define pci_ss_list_1039_0310 NULL +#define pci_ss_list_1039_0315 NULL +#define pci_ss_list_1039_0325 NULL +#define pci_ss_list_1039_0330 NULL +#define pci_ss_list_1039_0406 NULL +#define pci_ss_list_1039_0496 NULL +#define pci_ss_list_1039_0530 NULL +#define pci_ss_list_1039_0540 NULL +#define pci_ss_list_1039_0550 NULL +#define pci_ss_list_1039_0597 NULL +#define pci_ss_list_1039_0601 NULL +#define pci_ss_list_1039_0620 NULL +#define pci_ss_list_1039_0630 NULL +#define pci_ss_list_1039_0633 NULL +#define pci_ss_list_1039_0635 NULL +#define pci_ss_list_1039_0645 NULL +#define pci_ss_list_1039_0646 NULL +#define pci_ss_list_1039_0648 NULL +#define pci_ss_list_1039_0650 NULL +#define pci_ss_list_1039_0651 NULL +#define pci_ss_list_1039_0655 NULL +#define pci_ss_list_1039_0660 NULL +#define pci_ss_list_1039_0661 NULL +#define pci_ss_list_1039_0662 NULL +#define pci_ss_list_1039_0730 NULL +#define pci_ss_list_1039_0733 NULL +#define pci_ss_list_1039_0735 NULL +#define pci_ss_list_1039_0740 NULL +#define pci_ss_list_1039_0741 NULL +#define pci_ss_list_1039_0745 NULL +#define pci_ss_list_1039_0746 NULL +#define pci_ss_list_1039_0755 NULL +#define pci_ss_list_1039_0760 NULL +#define pci_ss_list_1039_0761 NULL +static const pciSubsystemInfo *pci_ss_list_1039_0900[] = { + &pci_ss_info_1039_0900_1019_0a14, + &pci_ss_info_1039_0900_1039_0900, + &pci_ss_info_1039_0900_1043_8035, + NULL +}; +#define pci_ss_list_1039_0961 NULL +#define pci_ss_list_1039_0962 NULL +#define pci_ss_list_1039_0963 NULL +#define pci_ss_list_1039_0964 NULL +#define pci_ss_list_1039_0965 NULL +#define pci_ss_list_1039_0966 NULL +#define pci_ss_list_1039_0968 NULL +#define pci_ss_list_1039_1180 NULL +#define pci_ss_list_1039_1182 NULL +#define pci_ss_list_1039_1183 NULL +#define pci_ss_list_1039_1184 NULL +#define pci_ss_list_1039_1185 NULL +#define pci_ss_list_1039_3602 NULL +#define pci_ss_list_1039_5107 NULL +#define pci_ss_list_1039_5300 NULL +#define pci_ss_list_1039_5315 NULL +#define pci_ss_list_1039_5401 NULL +#define pci_ss_list_1039_5511 NULL +static const pciSubsystemInfo *pci_ss_list_1039_5513[] = { + &pci_ss_info_1039_5513_1019_0970, + &pci_ss_info_1039_5513_1039_5513, + &pci_ss_info_1039_5513_1043_8035, + NULL +}; +#define pci_ss_list_1039_5517 NULL +#define pci_ss_list_1039_5571 NULL +#define pci_ss_list_1039_5581 NULL +#define pci_ss_list_1039_5582 NULL +#define pci_ss_list_1039_5591 NULL +#define pci_ss_list_1039_5596 NULL +#define pci_ss_list_1039_5597 NULL +#define pci_ss_list_1039_5600 NULL +#define pci_ss_list_1039_6204 NULL +#define pci_ss_list_1039_6205 NULL +#define pci_ss_list_1039_6236 NULL +static const pciSubsystemInfo *pci_ss_list_1039_6300[] = { + &pci_ss_info_1039_6300_1019_0970, + &pci_ss_info_1039_6300_1043_8035, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1039_6306[] = { + &pci_ss_info_1039_6306_1039_6306, + NULL +}; +#define pci_ss_list_1039_6325 NULL +static const pciSubsystemInfo *pci_ss_list_1039_6326[] = { + &pci_ss_info_1039_6326_1039_6326, + &pci_ss_info_1039_6326_1092_0a50, + &pci_ss_info_1039_6326_1092_0a70, + &pci_ss_info_1039_6326_1092_4910, + &pci_ss_info_1039_6326_1092_4920, + &pci_ss_info_1039_6326_1569_6326, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1039_6330[] = { + &pci_ss_info_1039_6330_1039_6330, + NULL +}; +#define pci_ss_list_1039_6350 NULL +#define pci_ss_list_1039_6351 NULL +static const pciSubsystemInfo *pci_ss_list_1039_7001[] = { + &pci_ss_info_1039_7001_1019_0a14, + &pci_ss_info_1039_7001_1039_7000, + &pci_ss_info_1039_7001_1462_5470, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1039_7002[] = { + &pci_ss_info_1039_7002_1509_7002, + NULL +}; +#define pci_ss_list_1039_7007 NULL +static const pciSubsystemInfo *pci_ss_list_1039_7012[] = { + &pci_ss_info_1039_7012_15bd_1001, + NULL +}; +#define pci_ss_list_1039_7013 NULL +static const pciSubsystemInfo *pci_ss_list_1039_7016[] = { + &pci_ss_info_1039_7016_1039_7016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1039_7018[] = { + &pci_ss_info_1039_7018_1014_01b6, + &pci_ss_info_1039_7018_1014_01b7, + &pci_ss_info_1039_7018_1019_7018, + &pci_ss_info_1039_7018_1025_000e, + &pci_ss_info_1039_7018_1025_0018, + &pci_ss_info_1039_7018_1039_7018, + &pci_ss_info_1039_7018_1043_800b, + &pci_ss_info_1039_7018_1054_7018, + &pci_ss_info_1039_7018_107d_5330, + &pci_ss_info_1039_7018_107d_5350, + &pci_ss_info_1039_7018_1170_3209, + &pci_ss_info_1039_7018_1462_400a, + &pci_ss_info_1039_7018_14a4_2089, + &pci_ss_info_1039_7018_14cd_2194, + &pci_ss_info_1039_7018_14ff_1100, + &pci_ss_info_1039_7018_152d_8808, + &pci_ss_info_1039_7018_1558_1103, + &pci_ss_info_1039_7018_1558_2200, + &pci_ss_info_1039_7018_1563_7018, + &pci_ss_info_1039_7018_15c5_0111, + &pci_ss_info_1039_7018_270f_a171, + &pci_ss_info_1039_7018_a0a0_0022, + NULL +}; +#define pci_ss_list_1039_7019 NULL +#define pci_ss_list_1039_7502 NULL +#define pci_ss_list_103c_002a NULL +#define pci_ss_list_103c_1005 NULL +#define pci_ss_list_103c_1008 NULL +#define pci_ss_list_103c_1028 NULL +static const pciSubsystemInfo *pci_ss_list_103c_1029[] = { + &pci_ss_info_103c_1029_107e_000f, + &pci_ss_info_103c_1029_9004_9210, + &pci_ss_info_103c_1029_9004_9211, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_103c_102a[] = { + &pci_ss_info_103c_102a_107e_000e, + &pci_ss_info_103c_102a_9004_9110, + &pci_ss_info_103c_102a_9004_9111, + NULL +}; +#define pci_ss_list_103c_1030 NULL +static const pciSubsystemInfo *pci_ss_list_103c_1031[] = { + &pci_ss_info_103c_1031_103c_1040, + &pci_ss_info_103c_1031_103c_1041, + &pci_ss_info_103c_1031_103c_1042, + NULL +}; +#define pci_ss_list_103c_1040 NULL +#define pci_ss_list_103c_1041 NULL +#define pci_ss_list_103c_1042 NULL +static const pciSubsystemInfo *pci_ss_list_103c_1048[] = { + &pci_ss_info_103c_1048_103c_1049, + &pci_ss_info_103c_1048_103c_104a, + &pci_ss_info_103c_1048_103c_104b, + &pci_ss_info_103c_1048_103c_1223, + &pci_ss_info_103c_1048_103c_1226, + &pci_ss_info_103c_1048_103c_1227, + &pci_ss_info_103c_1048_103c_1282, + &pci_ss_info_103c_1048_103c_1301, + NULL +}; +#define pci_ss_list_103c_1054 NULL +#define pci_ss_list_103c_1064 NULL +#define pci_ss_list_103c_108b NULL +#define pci_ss_list_103c_10c1 NULL +#define pci_ss_list_103c_10ed NULL +#define pci_ss_list_103c_10f0 NULL +#define pci_ss_list_103c_10f1 NULL +#define pci_ss_list_103c_1200 NULL +#define pci_ss_list_103c_1219 NULL +#define pci_ss_list_103c_121a NULL +#define pci_ss_list_103c_121b NULL +#define pci_ss_list_103c_121c NULL +#define pci_ss_list_103c_1229 NULL +#define pci_ss_list_103c_122a NULL +#define pci_ss_list_103c_122e NULL +#define pci_ss_list_103c_127b NULL +#define pci_ss_list_103c_127c NULL +#define pci_ss_list_103c_1290 NULL +#define pci_ss_list_103c_1291 NULL +#define pci_ss_list_103c_12b4 NULL +#define pci_ss_list_103c_12eb NULL +#define pci_ss_list_103c_12ec NULL +#define pci_ss_list_103c_12ee NULL +#define pci_ss_list_103c_12f8 NULL +#define pci_ss_list_103c_12fa NULL +#define pci_ss_list_103c_2910 NULL +#define pci_ss_list_103c_2925 NULL +#define pci_ss_list_103c_3080 NULL +#define pci_ss_list_103c_3085 NULL +static const pciSubsystemInfo *pci_ss_list_103c_3220[] = { + &pci_ss_info_103c_3220_103c_3225, + NULL +}; +#define pci_ss_list_103c_3230 NULL +#define pci_ss_list_103c_4030 NULL +#define pci_ss_list_103c_4031 NULL +#define pci_ss_list_103c_4037 NULL +#define pci_ss_list_103c_403b NULL +#define pci_ss_list_103c_60e8 NULL +#define pci_ss_list_1042_1000 NULL +#define pci_ss_list_1042_1001 NULL +#define pci_ss_list_1042_3000 NULL +#define pci_ss_list_1042_3010 NULL +#define pci_ss_list_1042_3020 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1043_0675[] = { + &pci_ss_info_1043_0675_0675_1704, + &pci_ss_info_1043_0675_0675_1707, + &pci_ss_info_1043_0675_10cf_105e, + NULL +}; +#define pci_ss_list_1043_0c11 NULL +#define pci_ss_list_1043_4015 NULL +#define pci_ss_list_1043_4021 NULL +#define pci_ss_list_1043_4057 NULL +#define pci_ss_list_1043_8043 NULL +#define pci_ss_list_1043_8047 NULL +#define pci_ss_list_1043_807b NULL +#define pci_ss_list_1043_8095 NULL +#define pci_ss_list_1043_80ac NULL +#define pci_ss_list_1043_80bb NULL +#define pci_ss_list_1043_80c5 NULL +#define pci_ss_list_1043_80df NULL +#define pci_ss_list_1043_815a NULL +#define pci_ss_list_1043_8187 NULL +#define pci_ss_list_1043_8188 NULL +#endif +#define pci_ss_list_1044_1012 NULL +#define pci_ss_list_1044_a400 NULL +#define pci_ss_list_1044_a500 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1044_a501[] = { + &pci_ss_info_1044_a501_1044_c001, + &pci_ss_info_1044_a501_1044_c002, + &pci_ss_info_1044_a501_1044_c003, + &pci_ss_info_1044_a501_1044_c004, + &pci_ss_info_1044_a501_1044_c005, + &pci_ss_info_1044_a501_1044_c00a, + &pci_ss_info_1044_a501_1044_c00b, + &pci_ss_info_1044_a501_1044_c00c, + &pci_ss_info_1044_a501_1044_c00d, + &pci_ss_info_1044_a501_1044_c00e, + &pci_ss_info_1044_a501_1044_c00f, + &pci_ss_info_1044_a501_1044_c014, + &pci_ss_info_1044_a501_1044_c015, + &pci_ss_info_1044_a501_1044_c016, + &pci_ss_info_1044_a501_1044_c01e, + &pci_ss_info_1044_a501_1044_c01f, + &pci_ss_info_1044_a501_1044_c020, + &pci_ss_info_1044_a501_1044_c021, + &pci_ss_info_1044_a501_1044_c028, + &pci_ss_info_1044_a501_1044_c029, + &pci_ss_info_1044_a501_1044_c02a, + &pci_ss_info_1044_a501_1044_c03c, + &pci_ss_info_1044_a501_1044_c03d, + &pci_ss_info_1044_a501_1044_c03e, + &pci_ss_info_1044_a501_1044_c046, + &pci_ss_info_1044_a501_1044_c047, + &pci_ss_info_1044_a501_1044_c048, + &pci_ss_info_1044_a501_1044_c050, + &pci_ss_info_1044_a501_1044_c051, + &pci_ss_info_1044_a501_1044_c052, + &pci_ss_info_1044_a501_1044_c05a, + &pci_ss_info_1044_a501_1044_c05b, + &pci_ss_info_1044_a501_1044_c064, + &pci_ss_info_1044_a501_1044_c065, + &pci_ss_info_1044_a501_1044_c066, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1044_a511[] = { + &pci_ss_info_1044_a511_1044_c032, + &pci_ss_info_1044_a511_1044_c035, + NULL +}; +#endif +#define pci_ss_list_1045_a0f8 NULL +#define pci_ss_list_1045_c101 NULL +#define pci_ss_list_1045_c178 NULL +#define pci_ss_list_1045_c556 NULL +#define pci_ss_list_1045_c557 NULL +#define pci_ss_list_1045_c558 NULL +#define pci_ss_list_1045_c567 NULL +#define pci_ss_list_1045_c568 NULL +#define pci_ss_list_1045_c569 NULL +#define pci_ss_list_1045_c621 NULL +#define pci_ss_list_1045_c700 NULL +#define pci_ss_list_1045_c701 NULL +#define pci_ss_list_1045_c814 NULL +#define pci_ss_list_1045_c822 NULL +#define pci_ss_list_1045_c824 NULL +#define pci_ss_list_1045_c825 NULL +#define pci_ss_list_1045_c832 NULL +#define pci_ss_list_1045_c861 NULL +#define pci_ss_list_1045_c895 NULL +#define pci_ss_list_1045_c935 NULL +#define pci_ss_list_1045_d568 NULL +#define pci_ss_list_1045_d721 NULL +#define pci_ss_list_1048_0c60 NULL +#define pci_ss_list_1048_0d22 NULL +#define pci_ss_list_1048_1000 NULL +#define pci_ss_list_1048_3000 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1048_8901[] = { + &pci_ss_info_1048_8901_1048_0935, + NULL +}; +#endif +#define pci_ss_list_104a_0008 NULL +#define pci_ss_list_104a_0009 NULL +#define pci_ss_list_104a_0010 NULL +#define pci_ss_list_104a_0209 NULL +#define pci_ss_list_104a_020a NULL +#define pci_ss_list_104a_0210 NULL +#define pci_ss_list_104a_021a NULL +#define pci_ss_list_104a_021b NULL +static const pciSubsystemInfo *pci_ss_list_104a_0500[] = { + &pci_ss_info_104a_0500_104a_0500, + NULL +}; +#define pci_ss_list_104a_0564 NULL +#define pci_ss_list_104a_0981 NULL +#define pci_ss_list_104a_1746 NULL +#define pci_ss_list_104a_2774 NULL +#define pci_ss_list_104a_3520 NULL +#define pci_ss_list_104a_55cc NULL +#define pci_ss_list_104b_0140 NULL +#define pci_ss_list_104b_1040 NULL +#define pci_ss_list_104b_8130 NULL +#define pci_ss_list_104c_0500 NULL +#define pci_ss_list_104c_0508 NULL +#define pci_ss_list_104c_1000 NULL +#define pci_ss_list_104c_104c NULL +#define pci_ss_list_104c_3d04 NULL +static const pciSubsystemInfo *pci_ss_list_104c_3d07[] = { + &pci_ss_info_104c_3d07_1011_4d10, + &pci_ss_info_104c_3d07_1040_000f, + &pci_ss_info_104c_3d07_1040_0011, + &pci_ss_info_104c_3d07_1048_0a31, + &pci_ss_info_104c_3d07_1048_0a32, + &pci_ss_info_104c_3d07_1048_0a34, + &pci_ss_info_104c_3d07_1048_0a35, + &pci_ss_info_104c_3d07_1048_0a36, + &pci_ss_info_104c_3d07_1048_0a43, + &pci_ss_info_104c_3d07_1048_0a44, + &pci_ss_info_104c_3d07_107d_2633, + &pci_ss_info_104c_3d07_1092_0127, + &pci_ss_info_104c_3d07_1092_0136, + &pci_ss_info_104c_3d07_1092_0141, + &pci_ss_info_104c_3d07_1092_0146, + &pci_ss_info_104c_3d07_1092_0148, + &pci_ss_info_104c_3d07_1092_0149, + &pci_ss_info_104c_3d07_1092_0152, + &pci_ss_info_104c_3d07_1092_0154, + &pci_ss_info_104c_3d07_1092_0155, + &pci_ss_info_104c_3d07_1092_0156, + &pci_ss_info_104c_3d07_1092_0157, + &pci_ss_info_104c_3d07_1097_3d01, + &pci_ss_info_104c_3d07_1102_100f, + &pci_ss_info_104c_3d07_3d3d_0100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8000[] = { + &pci_ss_info_104c_8000_e4bf_1010, + &pci_ss_info_104c_8000_e4bf_1020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8009[] = { + &pci_ss_info_104c_8009_104d_8032, + NULL +}; +#define pci_ss_list_104c_8017 NULL +static const pciSubsystemInfo *pci_ss_list_104c_8019[] = { + &pci_ss_info_104c_8019_11bd_000a, + &pci_ss_info_104c_8019_11bd_000e, + &pci_ss_info_104c_8019_e4bf_1010, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8020[] = { + &pci_ss_info_104c_8020_11bd_000f, + &pci_ss_info_104c_8020_11bd_001c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8021[] = { + &pci_ss_info_104c_8021_104d_80df, + &pci_ss_info_104c_8021_104d_80e7, + NULL +}; +#define pci_ss_list_104c_8022 NULL +static const pciSubsystemInfo *pci_ss_list_104c_8023[] = { + &pci_ss_info_104c_8023_103c_088c, + &pci_ss_info_104c_8023_1043_808b, + NULL +}; +#define pci_ss_list_104c_8024 NULL +static const pciSubsystemInfo *pci_ss_list_104c_8025[] = { + &pci_ss_info_104c_8025_1458_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8026[] = { + &pci_ss_info_104c_8026_1025_003c, + &pci_ss_info_104c_8026_103c_006a, + &pci_ss_info_104c_8026_1043_808d, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8027[] = { + &pci_ss_info_104c_8027_1028_00e6, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8029[] = { + &pci_ss_info_104c_8029_1028_0163, + &pci_ss_info_104c_8029_1028_0196, + &pci_ss_info_104c_8029_1071_8160, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_802b[] = { + &pci_ss_info_104c_802b_1028_0139, + &pci_ss_info_104c_802b_1028_014e, + NULL +}; +#define pci_ss_list_104c_802e NULL +static const pciSubsystemInfo *pci_ss_list_104c_8031[] = { + &pci_ss_info_104c_8031_1025_0080, + &pci_ss_info_104c_8031_103c_099c, + &pci_ss_info_104c_8031_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8032[] = { + &pci_ss_info_104c_8032_1025_0080, + &pci_ss_info_104c_8032_103c_099c, + &pci_ss_info_104c_8032_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8033[] = { + &pci_ss_info_104c_8033_1025_0080, + &pci_ss_info_104c_8033_103c_099c, + &pci_ss_info_104c_8033_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8034[] = { + &pci_ss_info_104c_8034_1025_0080, + &pci_ss_info_104c_8034_103c_099c, + &pci_ss_info_104c_8034_103c_308b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_8035[] = { + &pci_ss_info_104c_8035_103c_099c, + NULL +}; +#define pci_ss_list_104c_8036 NULL +#define pci_ss_list_104c_8038 NULL +static const pciSubsystemInfo *pci_ss_list_104c_8039[] = { + &pci_ss_info_104c_8039_103c_309f, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_803a[] = { + &pci_ss_info_104c_803a_103c_309f, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_803b[] = { + &pci_ss_info_104c_803b_103c_309f, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_803c[] = { + &pci_ss_info_104c_803c_103c_309f, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_803d[] = { + &pci_ss_info_104c_803d_103c_309f, + NULL +}; +#define pci_ss_list_104c_8201 NULL +static const pciSubsystemInfo *pci_ss_list_104c_8204[] = { + &pci_ss_info_104c_8204_1028_0139, + &pci_ss_info_104c_8204_1028_014e, + NULL +}; +#define pci_ss_list_104c_8231 NULL +#define pci_ss_list_104c_8235 NULL +static const pciSubsystemInfo *pci_ss_list_104c_8400[] = { + &pci_ss_info_104c_8400_1186_3b00, + &pci_ss_info_104c_8400_1186_3b01, + &pci_ss_info_104c_8400_16ab_8501, + NULL +}; +#define pci_ss_list_104c_8401 NULL +#define pci_ss_list_104c_9000 NULL +#define pci_ss_list_104c_9065 NULL +static const pciSubsystemInfo *pci_ss_list_104c_9066[] = { + &pci_ss_info_104c_9066_104c_9066, + &pci_ss_info_104c_9066_1186_3b04, + &pci_ss_info_104c_9066_1186_3b05, + &pci_ss_info_104c_9066_13d1_aba0, + &pci_ss_info_104c_9066_1737_0033, + NULL +}; +#define pci_ss_list_104c_a001 NULL +#define pci_ss_list_104c_a100 NULL +#define pci_ss_list_104c_a102 NULL +static const pciSubsystemInfo *pci_ss_list_104c_a106[] = { + &pci_ss_info_104c_a106_175c_5000, + &pci_ss_info_104c_a106_175c_6400, + &pci_ss_info_104c_a106_175c_8700, + NULL +}; +#define pci_ss_list_104c_ac10 NULL +#define pci_ss_list_104c_ac11 NULL +#define pci_ss_list_104c_ac12 NULL +#define pci_ss_list_104c_ac13 NULL +#define pci_ss_list_104c_ac15 NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac16[] = { + &pci_ss_info_104c_ac16_1014_0092, + NULL +}; +#define pci_ss_list_104c_ac17 NULL +#define pci_ss_list_104c_ac18 NULL +#define pci_ss_list_104c_ac19 NULL +#define pci_ss_list_104c_ac1a NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac1b[] = { + &pci_ss_info_104c_ac1b_0e11_b113, + &pci_ss_info_104c_ac1b_1014_0130, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_ac1c[] = { + &pci_ss_info_104c_ac1c_0e11_b121, + &pci_ss_info_104c_ac1c_1028_0088, + NULL +}; +#define pci_ss_list_104c_ac1d NULL +#define pci_ss_list_104c_ac1e NULL +#define pci_ss_list_104c_ac1f NULL +#define pci_ss_list_104c_ac20 NULL +#define pci_ss_list_104c_ac21 NULL +#define pci_ss_list_104c_ac22 NULL +#define pci_ss_list_104c_ac23 NULL +#define pci_ss_list_104c_ac28 NULL +#define pci_ss_list_104c_ac30 NULL +#define pci_ss_list_104c_ac40 NULL +#define pci_ss_list_104c_ac41 NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac42[] = { + &pci_ss_info_104c_ac42_1028_00e6, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_ac44[] = { + &pci_ss_info_104c_ac44_1028_0163, + &pci_ss_info_104c_ac44_1028_0196, + &pci_ss_info_104c_ac44_1071_8160, + NULL +}; +#define pci_ss_list_104c_ac46 NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac47[] = { + &pci_ss_info_104c_ac47_1028_0139, + &pci_ss_info_104c_ac47_1028_013f, + &pci_ss_info_104c_ac47_1028_014e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_ac4a[] = { + &pci_ss_info_104c_ac4a_1028_0139, + &pci_ss_info_104c_ac4a_1028_014e, + NULL +}; +#define pci_ss_list_104c_ac50 NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac51[] = { + &pci_ss_info_104c_ac51_0e11_004e, + &pci_ss_info_104c_ac51_1014_0148, + &pci_ss_info_104c_ac51_1014_023b, + &pci_ss_info_104c_ac51_1028_00b1, + &pci_ss_info_104c_ac51_1028_012a, + &pci_ss_info_104c_ac51_1033_80cd, + &pci_ss_info_104c_ac51_1095_10cf, + &pci_ss_info_104c_ac51_10cf_1095, + &pci_ss_info_104c_ac51_e4bf_1000, + NULL +}; +#define pci_ss_list_104c_ac52 NULL +#define pci_ss_list_104c_ac53 NULL +static const pciSubsystemInfo *pci_ss_list_104c_ac54[] = { + &pci_ss_info_104c_ac54_103c_08b0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_ac55[] = { + &pci_ss_info_104c_ac55_1014_0512, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_ac56[] = { + &pci_ss_info_104c_ac56_1014_0512, + &pci_ss_info_104c_ac56_1014_0528, + &pci_ss_info_104c_ac56_17aa_2012, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104c_ac60[] = { + &pci_ss_info_104c_ac60_175c_5100, + &pci_ss_info_104c_ac60_175c_6100, + &pci_ss_info_104c_ac60_175c_6200, + &pci_ss_info_104c_ac60_175c_8800, + NULL +}; +#define pci_ss_list_104c_ac8d NULL +#define pci_ss_list_104c_ac8e NULL +#define pci_ss_list_104c_ac8f NULL +#define pci_ss_list_104c_fe00 NULL +#define pci_ss_list_104c_fe03 NULL +#define pci_ss_list_104d_8004 NULL +#define pci_ss_list_104d_8009 NULL +#define pci_ss_list_104d_8039 NULL +#define pci_ss_list_104d_8056 NULL +#define pci_ss_list_104d_808a NULL +#define pci_ss_list_104e_0017 NULL +#define pci_ss_list_104e_0107 NULL +#define pci_ss_list_104e_0109 NULL +#define pci_ss_list_104e_0111 NULL +#define pci_ss_list_104e_0217 NULL +#define pci_ss_list_104e_0317 NULL +#define pci_ss_list_1050_0000 NULL +#define pci_ss_list_1050_0001 NULL +#define pci_ss_list_1050_0033 NULL +#define pci_ss_list_1050_0105 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1050_0840[] = { + &pci_ss_info_1050_0840_1050_0001, + &pci_ss_info_1050_0840_1050_0840, + NULL +}; +#define pci_ss_list_1050_0940 NULL +#define pci_ss_list_1050_5a5a NULL +static const pciSubsystemInfo *pci_ss_list_1050_6692[] = { + &pci_ss_info_1050_6692_1043_1702, + &pci_ss_info_1050_6692_1043_1703, + &pci_ss_info_1050_6692_1043_1707, + &pci_ss_info_1050_6692_144f_1702, + &pci_ss_info_1050_6692_144f_1703, + &pci_ss_info_1050_6692_144f_1707, + NULL +}; +#define pci_ss_list_1050_9921 NULL +#define pci_ss_list_1050_9922 NULL +#define pci_ss_list_1050_9970 NULL +#endif +#define pci_ss_list_1055_9130 NULL +#define pci_ss_list_1055_9460 NULL +#define pci_ss_list_1055_9462 NULL +#define pci_ss_list_1055_9463 NULL +#define pci_ss_list_1057_0001 NULL +#define pci_ss_list_1057_0002 NULL +#define pci_ss_list_1057_0003 NULL +#define pci_ss_list_1057_0004 NULL +#define pci_ss_list_1057_0006 NULL +#define pci_ss_list_1057_0008 NULL +#define pci_ss_list_1057_0009 NULL +#define pci_ss_list_1057_0012 NULL +#define pci_ss_list_1057_0100 NULL +#define pci_ss_list_1057_0431 NULL +static const pciSubsystemInfo *pci_ss_list_1057_1801[] = { + &pci_ss_info_1057_1801_14fb_0101, + &pci_ss_info_1057_1801_14fb_0102, + &pci_ss_info_1057_1801_14fb_0202, + &pci_ss_info_1057_1801_14fb_0611, + &pci_ss_info_1057_1801_14fb_0612, + &pci_ss_info_1057_1801_14fb_0613, + &pci_ss_info_1057_1801_14fb_0614, + &pci_ss_info_1057_1801_14fb_0621, + &pci_ss_info_1057_1801_14fb_0622, + &pci_ss_info_1057_1801_14fb_0810, + &pci_ss_info_1057_1801_175c_4200, + &pci_ss_info_1057_1801_175c_4300, + &pci_ss_info_1057_1801_175c_4400, + &pci_ss_info_1057_1801_ecc0_0010, + &pci_ss_info_1057_1801_ecc0_0020, + &pci_ss_info_1057_1801_ecc0_0030, + &pci_ss_info_1057_1801_ecc0_0031, + &pci_ss_info_1057_1801_ecc0_0040, + &pci_ss_info_1057_1801_ecc0_0041, + &pci_ss_info_1057_1801_ecc0_0050, + &pci_ss_info_1057_1801_ecc0_0051, + &pci_ss_info_1057_1801_ecc0_0070, + &pci_ss_info_1057_1801_ecc0_0071, + &pci_ss_info_1057_1801_ecc0_0072, + NULL +}; +#define pci_ss_list_1057_18c0 NULL +#define pci_ss_list_1057_18c1 NULL +#define pci_ss_list_1057_3055 NULL +static const pciSubsystemInfo *pci_ss_list_1057_3410[] = { + &pci_ss_info_1057_3410_ecc0_0050, + &pci_ss_info_1057_3410_ecc0_0051, + &pci_ss_info_1057_3410_ecc0_0060, + &pci_ss_info_1057_3410_ecc0_0070, + &pci_ss_info_1057_3410_ecc0_0071, + &pci_ss_info_1057_3410_ecc0_0072, + &pci_ss_info_1057_3410_ecc0_0080, + &pci_ss_info_1057_3410_ecc0_0081, + &pci_ss_info_1057_3410_ecc0_0090, + &pci_ss_info_1057_3410_ecc0_00a0, + &pci_ss_info_1057_3410_ecc0_00b0, + &pci_ss_info_1057_3410_ecc0_0100, + NULL +}; +#define pci_ss_list_1057_4801 NULL +#define pci_ss_list_1057_4802 NULL +#define pci_ss_list_1057_4803 NULL +#define pci_ss_list_1057_4806 NULL +#define pci_ss_list_1057_4d68 NULL +static const pciSubsystemInfo *pci_ss_list_1057_5600[] = { + &pci_ss_info_1057_5600_1057_0300, + &pci_ss_info_1057_5600_1057_0301, + &pci_ss_info_1057_5600_1057_0302, + &pci_ss_info_1057_5600_1057_5600, + &pci_ss_info_1057_5600_13d2_0300, + &pci_ss_info_1057_5600_13d2_0301, + &pci_ss_info_1057_5600_13d2_0302, + &pci_ss_info_1057_5600_1436_0300, + &pci_ss_info_1057_5600_1436_0301, + &pci_ss_info_1057_5600_1436_0302, + &pci_ss_info_1057_5600_144f_100c, + &pci_ss_info_1057_5600_1494_0300, + &pci_ss_info_1057_5600_1494_0301, + &pci_ss_info_1057_5600_14c8_0300, + &pci_ss_info_1057_5600_14c8_0302, + &pci_ss_info_1057_5600_1668_0300, + &pci_ss_info_1057_5600_1668_0302, + NULL +}; +#define pci_ss_list_1057_5608 NULL +#define pci_ss_list_1057_5803 NULL +#define pci_ss_list_1057_5806 NULL +#define pci_ss_list_1057_5808 NULL +#define pci_ss_list_1057_5809 NULL +#define pci_ss_list_1057_6400 NULL +#define pci_ss_list_1057_6405 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_105a_0d30[] = { + &pci_ss_info_105a_0d30_105a_4d33, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_0d38[] = { + &pci_ss_info_105a_0d38_105a_4d39, + NULL +}; +#define pci_ss_list_105a_1275 NULL +#define pci_ss_list_105a_3318 NULL +static const pciSubsystemInfo *pci_ss_list_105a_3319[] = { + &pci_ss_info_105a_3319_8086_3427, + NULL +}; +#define pci_ss_list_105a_3371 NULL +static const pciSubsystemInfo *pci_ss_list_105a_3373[] = { + &pci_ss_info_105a_3373_1043_80f5, + &pci_ss_info_105a_3373_1462_702e, + NULL +}; +#define pci_ss_list_105a_3375 NULL +static const pciSubsystemInfo *pci_ss_list_105a_3376[] = { + &pci_ss_info_105a_3376_1043_809e, + NULL +}; +#define pci_ss_list_105a_3515 NULL +#define pci_ss_list_105a_3519 NULL +#define pci_ss_list_105a_3570 NULL +#define pci_ss_list_105a_3571 NULL +#define pci_ss_list_105a_3574 NULL +#define pci_ss_list_105a_3577 NULL +#define pci_ss_list_105a_3d17 NULL +#define pci_ss_list_105a_3d18 NULL +#define pci_ss_list_105a_3d73 NULL +#define pci_ss_list_105a_3d75 NULL +#define pci_ss_list_105a_4302 NULL +static const pciSubsystemInfo *pci_ss_list_105a_4d30[] = { + &pci_ss_info_105a_4d30_105a_4d33, + &pci_ss_info_105a_4d30_105a_4d39, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_4d33[] = { + &pci_ss_info_105a_4d33_105a_4d33, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_4d38[] = { + &pci_ss_info_105a_4d38_105a_4d30, + &pci_ss_info_105a_4d38_105a_4d33, + &pci_ss_info_105a_4d38_105a_4d39, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_4d68[] = { + &pci_ss_info_105a_4d68_105a_4d68, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_4d69[] = { + &pci_ss_info_105a_4d69_105a_4d68, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_5275[] = { + &pci_ss_info_105a_5275_1043_807e, + &pci_ss_info_105a_5275_105a_0275, + &pci_ss_info_105a_5275_105a_1275, + &pci_ss_info_105a_5275_1458_b001, + NULL +}; +#define pci_ss_list_105a_5300 NULL +static const pciSubsystemInfo *pci_ss_list_105a_6268[] = { + &pci_ss_info_105a_6268_105a_4d68, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105a_6269[] = { + &pci_ss_info_105a_6269_105a_6269, + NULL +}; +#define pci_ss_list_105a_6621 NULL +#define pci_ss_list_105a_6622 NULL +#define pci_ss_list_105a_6624 NULL +#define pci_ss_list_105a_6626 NULL +#define pci_ss_list_105a_6629 NULL +#define pci_ss_list_105a_7275 NULL +#define pci_ss_list_105a_8002 NULL +#define pci_ss_list_105a_8350 NULL +#define pci_ss_list_105a_c350 NULL +#endif +#define pci_ss_list_105d_2309 NULL +static const pciSubsystemInfo *pci_ss_list_105d_2339[] = { + &pci_ss_info_105d_2339_105d_0000, + &pci_ss_info_105d_2339_105d_0001, + &pci_ss_info_105d_2339_105d_0002, + &pci_ss_info_105d_2339_105d_0003, + &pci_ss_info_105d_2339_105d_0004, + &pci_ss_info_105d_2339_105d_0005, + &pci_ss_info_105d_2339_105d_0006, + &pci_ss_info_105d_2339_105d_0007, + &pci_ss_info_105d_2339_105d_0008, + &pci_ss_info_105d_2339_105d_0009, + &pci_ss_info_105d_2339_105d_000a, + &pci_ss_info_105d_2339_105d_000b, + &pci_ss_info_105d_2339_11a4_000a, + &pci_ss_info_105d_2339_13cc_0000, + &pci_ss_info_105d_2339_13cc_0004, + &pci_ss_info_105d_2339_13cc_0005, + &pci_ss_info_105d_2339_13cc_0006, + &pci_ss_info_105d_2339_13cc_0008, + &pci_ss_info_105d_2339_13cc_0009, + &pci_ss_info_105d_2339_13cc_000a, + &pci_ss_info_105d_2339_13cc_000c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105d_493d[] = { + &pci_ss_info_105d_493d_11a4_000a, + &pci_ss_info_105d_493d_11a4_000b, + &pci_ss_info_105d_493d_13cc_0002, + &pci_ss_info_105d_493d_13cc_0003, + &pci_ss_info_105d_493d_13cc_0007, + &pci_ss_info_105d_493d_13cc_0008, + &pci_ss_info_105d_493d_13cc_0009, + &pci_ss_info_105d_493d_13cc_000a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_105d_5348[] = { + &pci_ss_info_105d_5348_105d_0037, + &pci_ss_info_105d_5348_11a4_0028, + &pci_ss_info_105d_5348_11a4_0038, + NULL +}; +#define pci_ss_list_1060_0001 NULL +#define pci_ss_list_1060_0002 NULL +#define pci_ss_list_1060_0101 NULL +#define pci_ss_list_1060_0881 NULL +#define pci_ss_list_1060_0886 NULL +#define pci_ss_list_1060_0891 NULL +#define pci_ss_list_1060_1001 NULL +#define pci_ss_list_1060_673a NULL +#define pci_ss_list_1060_673b NULL +#define pci_ss_list_1060_8710 NULL +#define pci_ss_list_1060_886a NULL +#define pci_ss_list_1060_8881 NULL +#define pci_ss_list_1060_8886 NULL +#define pci_ss_list_1060_888a NULL +#define pci_ss_list_1060_8891 NULL +#define pci_ss_list_1060_9017 NULL +#define pci_ss_list_1060_9018 NULL +#define pci_ss_list_1060_9026 NULL +#define pci_ss_list_1060_e881 NULL +#define pci_ss_list_1060_e886 NULL +#define pci_ss_list_1060_e88a NULL +#define pci_ss_list_1060_e891 NULL +#define pci_ss_list_1061_0001 NULL +#define pci_ss_list_1061_0002 NULL +#define pci_ss_list_1066_0000 NULL +#define pci_ss_list_1066_0001 NULL +#define pci_ss_list_1066_0002 NULL +#define pci_ss_list_1066_0003 NULL +#define pci_ss_list_1066_0004 NULL +#define pci_ss_list_1066_0005 NULL +#define pci_ss_list_1066_8002 NULL +#define pci_ss_list_1067_0301 NULL +#define pci_ss_list_1067_0304 NULL +#define pci_ss_list_1067_0308 NULL +#define pci_ss_list_1067_1002 NULL +#define pci_ss_list_1069_0001 NULL +#define pci_ss_list_1069_0002 NULL +#define pci_ss_list_1069_0010 NULL +#define pci_ss_list_1069_0020 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1069_0050[] = { + &pci_ss_info_1069_0050_1069_0050, + &pci_ss_info_1069_0050_1069_0052, + &pci_ss_info_1069_0050_1069_0054, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1069_b166[] = { + &pci_ss_info_1069_b166_1014_0242, + &pci_ss_info_1069_b166_1014_0266, + &pci_ss_info_1069_b166_1014_0278, + &pci_ss_info_1069_b166_1014_02d3, + &pci_ss_info_1069_b166_1014_02d4, + &pci_ss_info_1069_b166_1069_0200, + &pci_ss_info_1069_b166_1069_0202, + &pci_ss_info_1069_b166_1069_0204, + &pci_ss_info_1069_b166_1069_0206, + NULL +}; +#define pci_ss_list_1069_ba55 NULL +static const pciSubsystemInfo *pci_ss_list_1069_ba56[] = { + &pci_ss_info_1069_ba56_1069_0030, + &pci_ss_info_1069_ba56_1069_0040, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1069_ba57[] = { + &pci_ss_info_1069_ba57_1069_0072, + NULL +}; +#endif +#define pci_ss_list_106b_0001 NULL +#define pci_ss_list_106b_0002 NULL +#define pci_ss_list_106b_0003 NULL +#define pci_ss_list_106b_0004 NULL +#define pci_ss_list_106b_0007 NULL +#define pci_ss_list_106b_000c NULL +#define pci_ss_list_106b_000e NULL +#define pci_ss_list_106b_0010 NULL +#define pci_ss_list_106b_0017 NULL +#define pci_ss_list_106b_0018 NULL +#define pci_ss_list_106b_0019 NULL +#define pci_ss_list_106b_001e NULL +#define pci_ss_list_106b_001f NULL +#define pci_ss_list_106b_0020 NULL +#define pci_ss_list_106b_0021 NULL +#define pci_ss_list_106b_0022 NULL +#define pci_ss_list_106b_0024 NULL +#define pci_ss_list_106b_0025 NULL +#define pci_ss_list_106b_0026 NULL +#define pci_ss_list_106b_0027 NULL +#define pci_ss_list_106b_0028 NULL +#define pci_ss_list_106b_0029 NULL +#define pci_ss_list_106b_002d NULL +#define pci_ss_list_106b_002e NULL +#define pci_ss_list_106b_002f NULL +#define pci_ss_list_106b_0030 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_106b_0031[] = { + &pci_ss_info_106b_0031_106b_5811, + NULL +}; +#define pci_ss_list_106b_0032 NULL +#define pci_ss_list_106b_0033 NULL +#define pci_ss_list_106b_0034 NULL +#define pci_ss_list_106b_0035 NULL +#define pci_ss_list_106b_0036 NULL +#define pci_ss_list_106b_003b NULL +#define pci_ss_list_106b_003e NULL +#define pci_ss_list_106b_003f NULL +#define pci_ss_list_106b_0040 NULL +#define pci_ss_list_106b_0041 NULL +#define pci_ss_list_106b_0042 NULL +#define pci_ss_list_106b_0043 NULL +#define pci_ss_list_106b_0045 NULL +#define pci_ss_list_106b_0046 NULL +#define pci_ss_list_106b_0047 NULL +#define pci_ss_list_106b_0048 NULL +#define pci_ss_list_106b_0049 NULL +#define pci_ss_list_106b_004b NULL +#define pci_ss_list_106b_004c NULL +#define pci_ss_list_106b_004f NULL +#define pci_ss_list_106b_0050 NULL +#define pci_ss_list_106b_0051 NULL +#define pci_ss_list_106b_0052 NULL +#define pci_ss_list_106b_0053 NULL +#define pci_ss_list_106b_0054 NULL +#define pci_ss_list_106b_0055 NULL +#define pci_ss_list_106b_0058 NULL +#define pci_ss_list_106b_0059 NULL +#define pci_ss_list_106b_0066 NULL +#define pci_ss_list_106b_0067 NULL +#define pci_ss_list_106b_0068 NULL +#define pci_ss_list_106b_0069 NULL +#define pci_ss_list_106b_006a NULL +#define pci_ss_list_106b_006b NULL +#define pci_ss_list_106b_1645 NULL +#endif +#define pci_ss_list_106c_8801 NULL +#define pci_ss_list_106c_8802 NULL +#define pci_ss_list_106c_8803 NULL +#define pci_ss_list_106c_8804 NULL +#define pci_ss_list_106c_8805 NULL +#define pci_ss_list_1071_8160 NULL +#define pci_ss_list_1073_0001 NULL +#define pci_ss_list_1073_0002 NULL +#define pci_ss_list_1073_0003 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1073_0004[] = { + &pci_ss_info_1073_0004_1073_0004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_0005[] = { + &pci_ss_info_1073_0005_1073_0005, + NULL +}; +#define pci_ss_list_1073_0006 NULL +static const pciSubsystemInfo *pci_ss_list_1073_0008[] = { + &pci_ss_info_1073_0008_1073_0008, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_000a[] = { + &pci_ss_info_1073_000a_1073_0004, + &pci_ss_info_1073_000a_1073_000a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_000c[] = { + &pci_ss_info_1073_000c_107a_000c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_000d[] = { + &pci_ss_info_1073_000d_1073_000d, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_0010[] = { + &pci_ss_info_1073_0010_1073_0006, + &pci_ss_info_1073_0010_1073_0010, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1073_0012[] = { + &pci_ss_info_1073_0012_1073_0012, + NULL +}; +#define pci_ss_list_1073_0020 NULL +static const pciSubsystemInfo *pci_ss_list_1073_2000[] = { + &pci_ss_info_1073_2000_1073_2000, + NULL +}; +#endif +#define pci_ss_list_1074_4e78 NULL +#define pci_ss_list_1077_1016 NULL +#define pci_ss_list_1077_1020 NULL +#define pci_ss_list_1077_1022 NULL +#define pci_ss_list_1077_1080 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1077_1216[] = { + &pci_ss_info_1077_1216_101e_8471, + &pci_ss_info_1077_1216_101e_8493, + NULL +}; +#define pci_ss_list_1077_1240 NULL +#define pci_ss_list_1077_1280 NULL +#define pci_ss_list_1077_2020 NULL +static const pciSubsystemInfo *pci_ss_list_1077_2100[] = { + &pci_ss_info_1077_2100_1077_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1077_2200[] = { + &pci_ss_info_1077_2200_1077_0002, + NULL +}; +#define pci_ss_list_1077_2300 NULL +static const pciSubsystemInfo *pci_ss_list_1077_2312[] = { + &pci_ss_info_1077_2312_103c_0131, + &pci_ss_info_1077_2312_103c_12ba, + NULL +}; +#define pci_ss_list_1077_2322 NULL +static const pciSubsystemInfo *pci_ss_list_1077_2422[] = { + &pci_ss_info_1077_2422_103c_12d7, + &pci_ss_info_1077_2422_103c_12dd, + NULL +}; +#define pci_ss_list_1077_2432 NULL +#define pci_ss_list_1077_3010 NULL +#define pci_ss_list_1077_3022 NULL +#define pci_ss_list_1077_4010 NULL +#define pci_ss_list_1077_4022 NULL +#define pci_ss_list_1077_6312 NULL +#define pci_ss_list_1077_6322 NULL +#endif +#define pci_ss_list_1078_0000 NULL +#define pci_ss_list_1078_0001 NULL +#define pci_ss_list_1078_0002 NULL +#define pci_ss_list_1078_0100 NULL +#define pci_ss_list_1078_0101 NULL +#define pci_ss_list_1078_0102 NULL +#define pci_ss_list_1078_0103 NULL +#define pci_ss_list_1078_0104 NULL +#define pci_ss_list_1078_0400 NULL +#define pci_ss_list_1078_0401 NULL +#define pci_ss_list_1078_0402 NULL +#define pci_ss_list_1078_0403 NULL +#define pci_ss_list_107d_0000 NULL +#define pci_ss_list_107d_204d NULL +#define pci_ss_list_107d_2134 NULL +#define pci_ss_list_107d_2971 NULL +#define pci_ss_list_107e_0001 NULL +#define pci_ss_list_107e_0002 NULL +#define pci_ss_list_107e_0004 NULL +#define pci_ss_list_107e_0005 NULL +#define pci_ss_list_107e_0008 NULL +#define pci_ss_list_107e_9003 NULL +#define pci_ss_list_107e_9007 NULL +#define pci_ss_list_107e_9008 NULL +#define pci_ss_list_107e_900c NULL +#define pci_ss_list_107e_900e NULL +#define pci_ss_list_107e_9011 NULL +#define pci_ss_list_107e_9013 NULL +#define pci_ss_list_107e_9023 NULL +#define pci_ss_list_107e_9027 NULL +#define pci_ss_list_107e_9031 NULL +#define pci_ss_list_107e_9033 NULL +#define pci_ss_list_107f_0802 NULL +#define pci_ss_list_1080_0600 NULL +#define pci_ss_list_1080_c691 NULL +#define pci_ss_list_1080_c693 NULL +#define pci_ss_list_1081_0d47 NULL +#define pci_ss_list_1083_0001 NULL +#define pci_ss_list_108a_0001 NULL +#define pci_ss_list_108a_0010 NULL +#define pci_ss_list_108a_0040 NULL +#define pci_ss_list_108a_3000 NULL +#define pci_ss_list_108d_0001 NULL +#define pci_ss_list_108d_0002 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_108d_0004[] = { + &pci_ss_info_108d_0004_108d_0004, + NULL +}; +#define pci_ss_list_108d_0005 NULL +#define pci_ss_list_108d_0006 NULL +static const pciSubsystemInfo *pci_ss_list_108d_0007[] = { + &pci_ss_info_108d_0007_108d_0007, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_108d_0008[] = { + &pci_ss_info_108d_0008_108d_0008, + NULL +}; +#define pci_ss_list_108d_0011 NULL +#define pci_ss_list_108d_0012 NULL +#define pci_ss_list_108d_0013 NULL +#define pci_ss_list_108d_0014 NULL +static const pciSubsystemInfo *pci_ss_list_108d_0019[] = { + &pci_ss_info_108d_0019_108d_0016, + &pci_ss_info_108d_0019_108d_0017, + NULL +}; +#define pci_ss_list_108d_0021 NULL +#define pci_ss_list_108d_0022 NULL +#endif +#define pci_ss_list_108e_0001 NULL +#define pci_ss_list_108e_1000 NULL +#define pci_ss_list_108e_1001 NULL +#define pci_ss_list_108e_1100 NULL +#define pci_ss_list_108e_1101 NULL +#define pci_ss_list_108e_1102 NULL +#define pci_ss_list_108e_1103 NULL +#define pci_ss_list_108e_1648 NULL +#define pci_ss_list_108e_2bad NULL +#define pci_ss_list_108e_5000 NULL +#define pci_ss_list_108e_5043 NULL +#define pci_ss_list_108e_8000 NULL +#define pci_ss_list_108e_8001 NULL +#define pci_ss_list_108e_8002 NULL +#define pci_ss_list_108e_a000 NULL +#define pci_ss_list_108e_a001 NULL +#define pci_ss_list_108e_a801 NULL +#define pci_ss_list_108e_abba NULL +#define pci_ss_list_1091_0020 NULL +#define pci_ss_list_1091_0021 NULL +#define pci_ss_list_1091_0040 NULL +#define pci_ss_list_1091_0041 NULL +#define pci_ss_list_1091_0060 NULL +#define pci_ss_list_1091_00e4 NULL +#define pci_ss_list_1091_0720 NULL +#define pci_ss_list_1091_07a0 NULL +#define pci_ss_list_1091_1091 NULL +#define pci_ss_list_1092_00a0 NULL +#define pci_ss_list_1092_00a8 NULL +#define pci_ss_list_1092_0550 NULL +#define pci_ss_list_1092_08d4 NULL +#define pci_ss_list_1092_094c NULL +#define pci_ss_list_1092_1092 NULL +#define pci_ss_list_1092_6120 NULL +#define pci_ss_list_1092_8810 NULL +#define pci_ss_list_1092_8811 NULL +#define pci_ss_list_1092_8880 NULL +#define pci_ss_list_1092_8881 NULL +#define pci_ss_list_1092_88b0 NULL +#define pci_ss_list_1092_88b1 NULL +#define pci_ss_list_1092_88c0 NULL +#define pci_ss_list_1092_88c1 NULL +#define pci_ss_list_1092_88d0 NULL +#define pci_ss_list_1092_88d1 NULL +#define pci_ss_list_1092_88f0 NULL +#define pci_ss_list_1092_88f1 NULL +#define pci_ss_list_1092_9999 NULL +#define pci_ss_list_1093_0160 NULL +#define pci_ss_list_1093_0162 NULL +#define pci_ss_list_1093_1150 NULL +#define pci_ss_list_1093_1170 NULL +#define pci_ss_list_1093_1180 NULL +#define pci_ss_list_1093_1190 NULL +#define pci_ss_list_1093_1310 NULL +#define pci_ss_list_1093_1330 NULL +#define pci_ss_list_1093_1350 NULL +#define pci_ss_list_1093_14e0 NULL +#define pci_ss_list_1093_14f0 NULL +#define pci_ss_list_1093_17d0 NULL +#define pci_ss_list_1093_1870 NULL +#define pci_ss_list_1093_1880 NULL +#define pci_ss_list_1093_18b0 NULL +#define pci_ss_list_1093_2410 NULL +#define pci_ss_list_1093_2890 NULL +#define pci_ss_list_1093_2a60 NULL +#define pci_ss_list_1093_2a70 NULL +#define pci_ss_list_1093_2a80 NULL +#define pci_ss_list_1093_2c80 NULL +#define pci_ss_list_1093_2ca0 NULL +#define pci_ss_list_1093_70a9 NULL +#define pci_ss_list_1093_70b8 NULL +#define pci_ss_list_1093_b001 NULL +#define pci_ss_list_1093_b011 NULL +#define pci_ss_list_1093_b021 NULL +#define pci_ss_list_1093_b031 NULL +#define pci_ss_list_1093_b041 NULL +#define pci_ss_list_1093_b051 NULL +#define pci_ss_list_1093_b061 NULL +#define pci_ss_list_1093_b071 NULL +#define pci_ss_list_1093_b081 NULL +#define pci_ss_list_1093_b091 NULL +#define pci_ss_list_1093_c801 NULL +#define pci_ss_list_1093_c831 NULL +#define pci_ss_list_1095_0240 NULL +#define pci_ss_list_1095_0640 NULL +#define pci_ss_list_1095_0643 NULL +#define pci_ss_list_1095_0646 NULL +#define pci_ss_list_1095_0647 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1095_0648[] = { + &pci_ss_info_1095_0648_1043_8025, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1095_0649[] = { + &pci_ss_info_1095_0649_0e11_005d, + &pci_ss_info_1095_0649_0e11_007e, + &pci_ss_info_1095_0649_101e_0649, + NULL +}; +#define pci_ss_list_1095_0650 NULL +static const pciSubsystemInfo *pci_ss_list_1095_0670[] = { + &pci_ss_info_1095_0670_1095_0670, + NULL +}; +#define pci_ss_list_1095_0673 NULL +static const pciSubsystemInfo *pci_ss_list_1095_0680[] = { + &pci_ss_info_1095_0680_1095_3680, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1095_3112[] = { + &pci_ss_info_1095_3112_1095_3112, + &pci_ss_info_1095_3112_1095_6112, + &pci_ss_info_1095_3112_9005_0250, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1095_3114[] = { + &pci_ss_info_1095_3114_1095_3114, + &pci_ss_info_1095_3114_1095_6114, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1095_3124[] = { + &pci_ss_info_1095_3124_1095_3124, + NULL +}; +#define pci_ss_list_1095_3132 NULL +static const pciSubsystemInfo *pci_ss_list_1095_3512[] = { + &pci_ss_info_1095_3512_1095_3512, + &pci_ss_info_1095_3512_1095_6512, + NULL +}; +#endif +#define pci_ss_list_1098_0001 NULL +#define pci_ss_list_1098_0002 NULL +#define pci_ss_list_109e_032e NULL +#define pci_ss_list_109e_0350 NULL +#define pci_ss_list_109e_0351 NULL +static const pciSubsystemInfo *pci_ss_list_109e_0369[] = { + &pci_ss_info_109e_0369_1002_0001, + &pci_ss_info_109e_0369_1002_0003, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_036c[] = { + &pci_ss_info_109e_036c_13e9_0070, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_036e[] = { + &pci_ss_info_109e_036e_0070_13eb, + &pci_ss_info_109e_036e_0070_ff01, + &pci_ss_info_109e_036e_0071_0101, + &pci_ss_info_109e_036e_107d_6606, + &pci_ss_info_109e_036e_11bd_0012, + &pci_ss_info_109e_036e_11bd_001c, + &pci_ss_info_109e_036e_127a_0001, + &pci_ss_info_109e_036e_127a_0002, + &pci_ss_info_109e_036e_127a_0003, + &pci_ss_info_109e_036e_127a_0048, + &pci_ss_info_109e_036e_144f_3000, + &pci_ss_info_109e_036e_1461_0002, + &pci_ss_info_109e_036e_1461_0003, + &pci_ss_info_109e_036e_1461_0004, + &pci_ss_info_109e_036e_1461_0761, + &pci_ss_info_109e_036e_1461_0771, + &pci_ss_info_109e_036e_14f1_0001, + &pci_ss_info_109e_036e_14f1_0002, + &pci_ss_info_109e_036e_14f1_0003, + &pci_ss_info_109e_036e_14f1_0048, + &pci_ss_info_109e_036e_1822_0001, + &pci_ss_info_109e_036e_1851_1850, + &pci_ss_info_109e_036e_1851_1851, + &pci_ss_info_109e_036e_1852_1852, + &pci_ss_info_109e_036e_18ac_d500, + &pci_ss_info_109e_036e_270f_fc00, + &pci_ss_info_109e_036e_bd11_1200, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_036f[] = { + &pci_ss_info_109e_036f_127a_0044, + &pci_ss_info_109e_036f_127a_0122, + &pci_ss_info_109e_036f_127a_0144, + &pci_ss_info_109e_036f_127a_0222, + &pci_ss_info_109e_036f_127a_0244, + &pci_ss_info_109e_036f_127a_0322, + &pci_ss_info_109e_036f_127a_0422, + &pci_ss_info_109e_036f_127a_1122, + &pci_ss_info_109e_036f_127a_1222, + &pci_ss_info_109e_036f_127a_1322, + &pci_ss_info_109e_036f_127a_1522, + &pci_ss_info_109e_036f_127a_1622, + &pci_ss_info_109e_036f_127a_1722, + &pci_ss_info_109e_036f_14f1_0044, + &pci_ss_info_109e_036f_14f1_0122, + &pci_ss_info_109e_036f_14f1_0144, + &pci_ss_info_109e_036f_14f1_0222, + &pci_ss_info_109e_036f_14f1_0244, + &pci_ss_info_109e_036f_14f1_0322, + &pci_ss_info_109e_036f_14f1_0422, + &pci_ss_info_109e_036f_14f1_1122, + &pci_ss_info_109e_036f_14f1_1222, + &pci_ss_info_109e_036f_14f1_1322, + &pci_ss_info_109e_036f_14f1_1522, + &pci_ss_info_109e_036f_14f1_1622, + &pci_ss_info_109e_036f_14f1_1722, + &pci_ss_info_109e_036f_1851_1850, + &pci_ss_info_109e_036f_1851_1851, + &pci_ss_info_109e_036f_1852_1852, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_0370[] = { + &pci_ss_info_109e_0370_1851_1850, + &pci_ss_info_109e_0370_1851_1851, + &pci_ss_info_109e_0370_1852_1852, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_0878[] = { + &pci_ss_info_109e_0878_0070_13eb, + &pci_ss_info_109e_0878_0070_ff01, + &pci_ss_info_109e_0878_0071_0101, + &pci_ss_info_109e_0878_1002_0001, + &pci_ss_info_109e_0878_1002_0003, + &pci_ss_info_109e_0878_11bd_0012, + &pci_ss_info_109e_0878_11bd_001c, + &pci_ss_info_109e_0878_127a_0001, + &pci_ss_info_109e_0878_127a_0002, + &pci_ss_info_109e_0878_127a_0003, + &pci_ss_info_109e_0878_127a_0048, + &pci_ss_info_109e_0878_13e9_0070, + &pci_ss_info_109e_0878_144f_3000, + &pci_ss_info_109e_0878_1461_0002, + &pci_ss_info_109e_0878_1461_0004, + &pci_ss_info_109e_0878_1461_0761, + &pci_ss_info_109e_0878_1461_0771, + &pci_ss_info_109e_0878_14f1_0001, + &pci_ss_info_109e_0878_14f1_0002, + &pci_ss_info_109e_0878_14f1_0003, + &pci_ss_info_109e_0878_14f1_0048, + &pci_ss_info_109e_0878_1822_0001, + &pci_ss_info_109e_0878_18ac_d500, + &pci_ss_info_109e_0878_270f_fc00, + &pci_ss_info_109e_0878_bd11_1200, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_109e_0879[] = { + &pci_ss_info_109e_0879_127a_0044, + &pci_ss_info_109e_0879_127a_0122, + &pci_ss_info_109e_0879_127a_0144, + &pci_ss_info_109e_0879_127a_0222, + &pci_ss_info_109e_0879_127a_0244, + &pci_ss_info_109e_0879_127a_0322, + &pci_ss_info_109e_0879_127a_0422, + &pci_ss_info_109e_0879_127a_1122, + &pci_ss_info_109e_0879_127a_1222, + &pci_ss_info_109e_0879_127a_1322, + &pci_ss_info_109e_0879_127a_1522, + &pci_ss_info_109e_0879_127a_1622, + &pci_ss_info_109e_0879_127a_1722, + &pci_ss_info_109e_0879_14f1_0044, + &pci_ss_info_109e_0879_14f1_0122, + &pci_ss_info_109e_0879_14f1_0144, + &pci_ss_info_109e_0879_14f1_0222, + &pci_ss_info_109e_0879_14f1_0244, + &pci_ss_info_109e_0879_14f1_0322, + &pci_ss_info_109e_0879_14f1_0422, + &pci_ss_info_109e_0879_14f1_1122, + &pci_ss_info_109e_0879_14f1_1222, + &pci_ss_info_109e_0879_14f1_1322, + &pci_ss_info_109e_0879_14f1_1522, + &pci_ss_info_109e_0879_14f1_1622, + &pci_ss_info_109e_0879_14f1_1722, + NULL +}; +#define pci_ss_list_109e_0880 NULL +#define pci_ss_list_109e_2115 NULL +#define pci_ss_list_109e_2125 NULL +#define pci_ss_list_109e_2164 NULL +#define pci_ss_list_109e_2165 NULL +#define pci_ss_list_109e_8230 NULL +#define pci_ss_list_109e_8472 NULL +#define pci_ss_list_109e_8474 NULL +#define pci_ss_list_10a5_3052 NULL +#define pci_ss_list_10a5_5449 NULL +#define pci_ss_list_10a8_0000 NULL +#define pci_ss_list_10a9_0001 NULL +#define pci_ss_list_10a9_0002 NULL +#define pci_ss_list_10a9_0003 NULL +#define pci_ss_list_10a9_0004 NULL +#define pci_ss_list_10a9_0005 NULL +#define pci_ss_list_10a9_0006 NULL +#define pci_ss_list_10a9_0007 NULL +#define pci_ss_list_10a9_0008 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10a9_0009[] = { + &pci_ss_info_10a9_0009_10a9_8002, + NULL +}; +#define pci_ss_list_10a9_0010 NULL +#define pci_ss_list_10a9_0011 NULL +#define pci_ss_list_10a9_0012 NULL +#define pci_ss_list_10a9_1001 NULL +#define pci_ss_list_10a9_1002 NULL +#define pci_ss_list_10a9_1003 NULL +#define pci_ss_list_10a9_1004 NULL +#define pci_ss_list_10a9_1005 NULL +#define pci_ss_list_10a9_1006 NULL +#define pci_ss_list_10a9_1007 NULL +#define pci_ss_list_10a9_1008 NULL +#define pci_ss_list_10a9_100a NULL +#define pci_ss_list_10a9_2001 NULL +#define pci_ss_list_10a9_2002 NULL +#define pci_ss_list_10a9_4001 NULL +#define pci_ss_list_10a9_4002 NULL +#define pci_ss_list_10a9_8001 NULL +#define pci_ss_list_10a9_8002 NULL +#endif +#define pci_ss_list_10aa_0000 NULL +#define pci_ss_list_10ad_0001 NULL +#define pci_ss_list_10ad_0003 NULL +#define pci_ss_list_10ad_0005 NULL +#define pci_ss_list_10ad_0103 NULL +#define pci_ss_list_10ad_0105 NULL +#define pci_ss_list_10ad_0565 NULL +#define pci_ss_list_10b3_3106 NULL +#define pci_ss_list_10b3_b106 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b4_1b1d[] = { + &pci_ss_info_10b4_1b1d_10b4_237e, + NULL +}; +#endif +#define pci_ss_list_10b5_0001 NULL +#define pci_ss_list_10b5_1042 NULL +#define pci_ss_list_10b5_1076 NULL +#define pci_ss_list_10b5_1077 NULL +#define pci_ss_list_10b5_1078 NULL +#define pci_ss_list_10b5_1103 NULL +#define pci_ss_list_10b5_1146 NULL +#define pci_ss_list_10b5_1147 NULL +#define pci_ss_list_10b5_2540 NULL +#define pci_ss_list_10b5_2724 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b5_6540[] = { + &pci_ss_info_10b5_6540_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b5_6541[] = { + &pci_ss_info_10b5_6541_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b5_6542[] = { + &pci_ss_info_10b5_6542_4c53_10e0, + NULL +}; +#define pci_ss_list_10b5_8111 NULL +#define pci_ss_list_10b5_8114 NULL +#define pci_ss_list_10b5_8516 NULL +#define pci_ss_list_10b5_8532 NULL +static const pciSubsystemInfo *pci_ss_list_10b5_9030[] = { + &pci_ss_info_10b5_9030_10b5_2862, + &pci_ss_info_10b5_9030_10b5_2906, + &pci_ss_info_10b5_9030_10b5_2940, + &pci_ss_info_10b5_9030_10b5_2977, + &pci_ss_info_10b5_9030_10b5_2978, + &pci_ss_info_10b5_9030_10b5_3025, + &pci_ss_info_10b5_9030_10b5_3068, + &pci_ss_info_10b5_9030_1397_3136, + &pci_ss_info_10b5_9030_1397_3137, + &pci_ss_info_10b5_9030_1518_0200, + &pci_ss_info_10b5_9030_15ed_1002, + &pci_ss_info_10b5_9030_15ed_1003, + NULL +}; +#define pci_ss_list_10b5_9036 NULL +static const pciSubsystemInfo *pci_ss_list_10b5_9050[] = { + &pci_ss_info_10b5_9050_10b5_1067, + &pci_ss_info_10b5_9050_10b5_1172, + &pci_ss_info_10b5_9050_10b5_2036, + &pci_ss_info_10b5_9050_10b5_2221, + &pci_ss_info_10b5_9050_10b5_2273, + &pci_ss_info_10b5_9050_10b5_2431, + &pci_ss_info_10b5_9050_10b5_2905, + &pci_ss_info_10b5_9050_10b5_9050, + &pci_ss_info_10b5_9050_1498_0362, + &pci_ss_info_10b5_9050_1522_0001, + &pci_ss_info_10b5_9050_1522_0002, + &pci_ss_info_10b5_9050_1522_0003, + &pci_ss_info_10b5_9050_1522_0004, + &pci_ss_info_10b5_9050_1522_0010, + &pci_ss_info_10b5_9050_1522_0020, + &pci_ss_info_10b5_9050_15ed_1000, + &pci_ss_info_10b5_9050_15ed_1001, + &pci_ss_info_10b5_9050_15ed_1002, + &pci_ss_info_10b5_9050_15ed_1003, + &pci_ss_info_10b5_9050_5654_2036, + &pci_ss_info_10b5_9050_5654_3132, + &pci_ss_info_10b5_9050_5654_5634, + &pci_ss_info_10b5_9050_d531_c002, + &pci_ss_info_10b5_9050_d84d_4006, + &pci_ss_info_10b5_9050_d84d_4008, + &pci_ss_info_10b5_9050_d84d_4014, + &pci_ss_info_10b5_9050_d84d_4018, + &pci_ss_info_10b5_9050_d84d_4025, + &pci_ss_info_10b5_9050_d84d_4027, + &pci_ss_info_10b5_9050_d84d_4028, + &pci_ss_info_10b5_9050_d84d_4036, + &pci_ss_info_10b5_9050_d84d_4037, + &pci_ss_info_10b5_9050_d84d_4038, + &pci_ss_info_10b5_9050_d84d_4052, + &pci_ss_info_10b5_9050_d84d_4053, + &pci_ss_info_10b5_9050_d84d_4055, + &pci_ss_info_10b5_9050_d84d_4058, + &pci_ss_info_10b5_9050_d84d_4065, + &pci_ss_info_10b5_9050_d84d_4068, + &pci_ss_info_10b5_9050_d84d_4078, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b5_9054[] = { + &pci_ss_info_10b5_9054_10b5_2455, + &pci_ss_info_10b5_9054_10b5_2696, + &pci_ss_info_10b5_9054_10b5_2717, + &pci_ss_info_10b5_9054_10b5_2844, + &pci_ss_info_10b5_9054_12c7_4001, + &pci_ss_info_10b5_9054_12d9_0002, + &pci_ss_info_10b5_9054_16df_0011, + &pci_ss_info_10b5_9054_16df_0012, + &pci_ss_info_10b5_9054_16df_0013, + &pci_ss_info_10b5_9054_16df_0014, + &pci_ss_info_10b5_9054_16df_0015, + &pci_ss_info_10b5_9054_16df_0016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b5_9056[] = { + &pci_ss_info_10b5_9056_10b5_2979, + NULL +}; +#define pci_ss_list_10b5_9060 NULL +static const pciSubsystemInfo *pci_ss_list_10b5_906d[] = { + &pci_ss_info_10b5_906d_125c_0640, + NULL +}; +#define pci_ss_list_10b5_906e NULL +static const pciSubsystemInfo *pci_ss_list_10b5_9080[] = { + &pci_ss_info_10b5_9080_103c_10eb, + &pci_ss_info_10b5_9080_103c_10ec, + &pci_ss_info_10b5_9080_10b5_1123, + &pci_ss_info_10b5_9080_10b5_9080, + &pci_ss_info_10b5_9080_129d_0002, + &pci_ss_info_10b5_9080_12d9_0002, + &pci_ss_info_10b5_9080_12df_4422, + &pci_ss_info_10b5_9080_1517_000b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b5_9656[] = { + &pci_ss_info_10b5_9656_1517_000f, + &pci_ss_info_10b5_9656_1885_0700, + &pci_ss_info_10b5_9656_1885_0701, + NULL +}; +#define pci_ss_list_10b5_bb04 NULL +#define pci_ss_list_10b5_c001 NULL +#endif +#define pci_ss_list_10b6_0001 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b6_0002[] = { + &pci_ss_info_10b6_0002_10b6_0002, + &pci_ss_info_10b6_0002_10b6_0006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_0003[] = { + &pci_ss_info_10b6_0003_0e11_b0fd, + &pci_ss_info_10b6_0003_10b6_0003, + &pci_ss_info_10b6_0003_10b6_0007, + NULL +}; +#define pci_ss_list_10b6_0004 NULL +static const pciSubsystemInfo *pci_ss_list_10b6_0006[] = { + &pci_ss_info_10b6_0006_10b6_0006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_0007[] = { + &pci_ss_info_10b6_0007_10b6_0007, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_0009[] = { + &pci_ss_info_10b6_0009_10b6_0009, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_000a[] = { + &pci_ss_info_10b6_000a_10b6_000a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_000b[] = { + &pci_ss_info_10b6_000b_10b6_0008, + &pci_ss_info_10b6_000b_10b6_000b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b6_000c[] = { + &pci_ss_info_10b6_000c_10b6_000c, + NULL +}; +#define pci_ss_list_10b6_1000 NULL +#define pci_ss_list_10b6_1001 NULL +#endif +#define pci_ss_list_10b7_0001 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b7_0013[] = { + &pci_ss_info_10b7_0013_10b7_2031, + NULL +}; +#define pci_ss_list_10b7_0910 NULL +#define pci_ss_list_10b7_1006 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_1007[] = { + &pci_ss_info_10b7_1007_10b7_615c, + NULL +}; +#define pci_ss_list_10b7_1201 NULL +#define pci_ss_list_10b7_1202 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_1700[] = { + &pci_ss_info_10b7_1700_1043_80eb, + &pci_ss_info_10b7_1700_10b7_0010, + &pci_ss_info_10b7_1700_10b7_0020, + &pci_ss_info_10b7_1700_147b_1407, + NULL +}; +#define pci_ss_list_10b7_3390 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_3590[] = { + &pci_ss_info_10b7_3590_10b7_3590, + NULL +}; +#define pci_ss_list_10b7_4500 NULL +#define pci_ss_list_10b7_5055 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_5057[] = { + &pci_ss_info_10b7_5057_10b7_5a57, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_5157[] = { + &pci_ss_info_10b7_5157_10b7_5b57, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_5257[] = { + &pci_ss_info_10b7_5257_10b7_5c57, + NULL +}; +#define pci_ss_list_10b7_5900 NULL +#define pci_ss_list_10b7_5920 NULL +#define pci_ss_list_10b7_5950 NULL +#define pci_ss_list_10b7_5951 NULL +#define pci_ss_list_10b7_5952 NULL +#define pci_ss_list_10b7_5970 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_5b57[] = { + &pci_ss_info_10b7_5b57_10b7_5b57, + NULL +}; +#define pci_ss_list_10b7_6000 NULL +#define pci_ss_list_10b7_6001 NULL +#define pci_ss_list_10b7_6055 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_6056[] = { + &pci_ss_info_10b7_6056_10b7_6556, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_6560[] = { + &pci_ss_info_10b7_6560_10b7_656a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_6561[] = { + &pci_ss_info_10b7_6561_10b7_656b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_6562[] = { + &pci_ss_info_10b7_6562_10b7_656b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_6563[] = { + &pci_ss_info_10b7_6563_10b7_656b, + NULL +}; +#define pci_ss_list_10b7_6564 NULL +#define pci_ss_list_10b7_7646 NULL +#define pci_ss_list_10b7_7770 NULL +#define pci_ss_list_10b7_7940 NULL +#define pci_ss_list_10b7_7980 NULL +#define pci_ss_list_10b7_7990 NULL +#define pci_ss_list_10b7_80eb NULL +#define pci_ss_list_10b7_8811 NULL +#define pci_ss_list_10b7_9000 NULL +#define pci_ss_list_10b7_9001 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9004[] = { + &pci_ss_info_10b7_9004_10b7_9004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_9005[] = { + &pci_ss_info_10b7_9005_10b7_9005, + NULL +}; +#define pci_ss_list_10b7_9006 NULL +#define pci_ss_list_10b7_900a NULL +#define pci_ss_list_10b7_9050 NULL +#define pci_ss_list_10b7_9051 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9054[] = { + &pci_ss_info_10b7_9054_10b7_9054, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_9055[] = { + &pci_ss_info_10b7_9055_1028_0080, + &pci_ss_info_10b7_9055_1028_0081, + &pci_ss_info_10b7_9055_1028_0082, + &pci_ss_info_10b7_9055_1028_0083, + &pci_ss_info_10b7_9055_1028_0084, + &pci_ss_info_10b7_9055_1028_0085, + &pci_ss_info_10b7_9055_1028_0086, + &pci_ss_info_10b7_9055_1028_0087, + &pci_ss_info_10b7_9055_1028_0088, + &pci_ss_info_10b7_9055_1028_0089, + &pci_ss_info_10b7_9055_1028_0090, + &pci_ss_info_10b7_9055_1028_0091, + &pci_ss_info_10b7_9055_1028_0092, + &pci_ss_info_10b7_9055_1028_0093, + &pci_ss_info_10b7_9055_1028_0094, + &pci_ss_info_10b7_9055_1028_0095, + &pci_ss_info_10b7_9055_1028_0096, + &pci_ss_info_10b7_9055_1028_0097, + &pci_ss_info_10b7_9055_1028_0098, + &pci_ss_info_10b7_9055_1028_0099, + &pci_ss_info_10b7_9055_10b7_9055, + NULL +}; +#define pci_ss_list_10b7_9056 NULL +#define pci_ss_list_10b7_9058 NULL +#define pci_ss_list_10b7_905a NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9200[] = { + &pci_ss_info_10b7_9200_1028_0095, + &pci_ss_info_10b7_9200_1028_0097, + &pci_ss_info_10b7_9200_1028_00fe, + &pci_ss_info_10b7_9200_1028_012a, + &pci_ss_info_10b7_9200_10b7_1000, + &pci_ss_info_10b7_9200_10b7_7000, + &pci_ss_info_10b7_9200_10f1_2466, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_9201[] = { + &pci_ss_info_10b7_9201_1043_80ab, + NULL +}; +#define pci_ss_list_10b7_9202 NULL +#define pci_ss_list_10b7_9210 NULL +#define pci_ss_list_10b7_9300 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9800[] = { + &pci_ss_info_10b7_9800_10b7_9800, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_9805[] = { + &pci_ss_info_10b7_9805_10b7_1201, + &pci_ss_info_10b7_9805_10b7_1202, + &pci_ss_info_10b7_9805_10b7_9805, + &pci_ss_info_10b7_9805_10f1_2462, + NULL +}; +#define pci_ss_list_10b7_9900 NULL +#define pci_ss_list_10b7_9902 NULL +#define pci_ss_list_10b7_9903 NULL +static const pciSubsystemInfo *pci_ss_list_10b7_9904[] = { + &pci_ss_info_10b7_9904_10b7_1000, + &pci_ss_info_10b7_9904_10b7_2000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b7_9905[] = { + &pci_ss_info_10b7_9905_10b7_1101, + &pci_ss_info_10b7_9905_10b7_1102, + &pci_ss_info_10b7_9905_10b7_2101, + &pci_ss_info_10b7_9905_10b7_2102, + NULL +}; +#define pci_ss_list_10b7_9908 NULL +#define pci_ss_list_10b7_9909 NULL +#define pci_ss_list_10b7_990a NULL +#define pci_ss_list_10b7_990b NULL +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b8_0005[] = { + &pci_ss_info_10b8_0005_1055_e000, + &pci_ss_info_10b8_0005_1055_e002, + &pci_ss_info_10b8_0005_10b8_a011, + &pci_ss_info_10b8_0005_10b8_a014, + &pci_ss_info_10b8_0005_10b8_a015, + &pci_ss_info_10b8_0005_10b8_a016, + &pci_ss_info_10b8_0005_10b8_a017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b8_0006[] = { + &pci_ss_info_10b8_0006_1055_e100, + &pci_ss_info_10b8_0006_1055_e102, + &pci_ss_info_10b8_0006_1055_e300, + &pci_ss_info_10b8_0006_1055_e302, + &pci_ss_info_10b8_0006_10b8_a012, + &pci_ss_info_10b8_0006_13a2_8002, + &pci_ss_info_10b8_0006_13a2_8006, + NULL +}; +#define pci_ss_list_10b8_1000 NULL +#define pci_ss_list_10b8_1001 NULL +#define pci_ss_list_10b8_2802 NULL +#define pci_ss_list_10b8_a011 NULL +#define pci_ss_list_10b8_b106 NULL +#endif +#define pci_ss_list_10b9_0101 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b9_0111[] = { + &pci_ss_info_10b9_0111_10b9_0111, + NULL +}; +#define pci_ss_list_10b9_0780 NULL +#define pci_ss_list_10b9_0782 NULL +#define pci_ss_list_10b9_1435 NULL +#define pci_ss_list_10b9_1445 NULL +#define pci_ss_list_10b9_1449 NULL +#define pci_ss_list_10b9_1451 NULL +#define pci_ss_list_10b9_1461 NULL +#define pci_ss_list_10b9_1489 NULL +#define pci_ss_list_10b9_1511 NULL +#define pci_ss_list_10b9_1512 NULL +#define pci_ss_list_10b9_1513 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_1521[] = { + &pci_ss_info_10b9_1521_10b9_1521, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b9_1523[] = { + &pci_ss_info_10b9_1523_10b9_1523, + NULL +}; +#define pci_ss_list_10b9_1531 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_1533[] = { + &pci_ss_info_10b9_1533_1014_053b, + &pci_ss_info_10b9_1533_10b9_1533, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10b9_1541[] = { + &pci_ss_info_10b9_1541_10b9_1541, + NULL +}; +#define pci_ss_list_10b9_1543 NULL +#define pci_ss_list_10b9_1563 NULL +#define pci_ss_list_10b9_1573 NULL +#define pci_ss_list_10b9_1621 NULL +#define pci_ss_list_10b9_1631 NULL +#define pci_ss_list_10b9_1632 NULL +#define pci_ss_list_10b9_1641 NULL +#define pci_ss_list_10b9_1644 NULL +#define pci_ss_list_10b9_1646 NULL +#define pci_ss_list_10b9_1647 NULL +#define pci_ss_list_10b9_1651 NULL +#define pci_ss_list_10b9_1671 NULL +#define pci_ss_list_10b9_1672 NULL +#define pci_ss_list_10b9_1681 NULL +#define pci_ss_list_10b9_1687 NULL +#define pci_ss_list_10b9_1689 NULL +#define pci_ss_list_10b9_1695 NULL +#define pci_ss_list_10b9_1697 NULL +#define pci_ss_list_10b9_3141 NULL +#define pci_ss_list_10b9_3143 NULL +#define pci_ss_list_10b9_3145 NULL +#define pci_ss_list_10b9_3147 NULL +#define pci_ss_list_10b9_3149 NULL +#define pci_ss_list_10b9_3151 NULL +#define pci_ss_list_10b9_3307 NULL +#define pci_ss_list_10b9_3309 NULL +#define pci_ss_list_10b9_3323 NULL +#define pci_ss_list_10b9_5212 NULL +#define pci_ss_list_10b9_5215 NULL +#define pci_ss_list_10b9_5217 NULL +#define pci_ss_list_10b9_5219 NULL +#define pci_ss_list_10b9_5225 NULL +#define pci_ss_list_10b9_5228 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_5229[] = { + &pci_ss_info_10b9_5229_1014_050f, + &pci_ss_info_10b9_5229_1014_053d, + &pci_ss_info_10b9_5229_103c_0024, + &pci_ss_info_10b9_5229_1043_8053, + &pci_ss_info_10b9_5229_1849_5229, + NULL +}; +#define pci_ss_list_10b9_5235 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_5237[] = { + &pci_ss_info_10b9_5237_1014_0540, + &pci_ss_info_10b9_5237_103c_0024, + &pci_ss_info_10b9_5237_104d_810f, + NULL +}; +#define pci_ss_list_10b9_5239 NULL +#define pci_ss_list_10b9_5243 NULL +#define pci_ss_list_10b9_5246 NULL +#define pci_ss_list_10b9_5247 NULL +#define pci_ss_list_10b9_5249 NULL +#define pci_ss_list_10b9_524b NULL +#define pci_ss_list_10b9_524c NULL +#define pci_ss_list_10b9_524d NULL +#define pci_ss_list_10b9_524e NULL +#define pci_ss_list_10b9_5251 NULL +#define pci_ss_list_10b9_5253 NULL +#define pci_ss_list_10b9_5261 NULL +#define pci_ss_list_10b9_5263 NULL +#define pci_ss_list_10b9_5281 NULL +#define pci_ss_list_10b9_5287 NULL +#define pci_ss_list_10b9_5288 NULL +#define pci_ss_list_10b9_5289 NULL +#define pci_ss_list_10b9_5450 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_5451[] = { + &pci_ss_info_10b9_5451_1014_0506, + &pci_ss_info_10b9_5451_1014_053e, + &pci_ss_info_10b9_5451_103c_0024, + &pci_ss_info_10b9_5451_10b9_5451, + NULL +}; +#define pci_ss_list_10b9_5453 NULL +#define pci_ss_list_10b9_5455 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_5457[] = { + &pci_ss_info_10b9_5457_1014_0535, + &pci_ss_info_10b9_5457_103c_0024, + NULL +}; +#define pci_ss_list_10b9_5459 NULL +#define pci_ss_list_10b9_545a NULL +#define pci_ss_list_10b9_5461 NULL +#define pci_ss_list_10b9_5471 NULL +#define pci_ss_list_10b9_5473 NULL +static const pciSubsystemInfo *pci_ss_list_10b9_7101[] = { + &pci_ss_info_10b9_7101_1014_0510, + &pci_ss_info_10b9_7101_1014_053c, + &pci_ss_info_10b9_7101_103c_0024, + NULL +}; +#endif +#define pci_ss_list_10ba_0301 NULL +#define pci_ss_list_10ba_0304 NULL +#define pci_ss_list_10ba_0308 NULL +#define pci_ss_list_10ba_1002 NULL +#define pci_ss_list_10bd_0e34 NULL +#define pci_ss_list_10c3_1100 NULL +#define pci_ss_list_10c8_0001 NULL +#define pci_ss_list_10c8_0002 NULL +#define pci_ss_list_10c8_0003 NULL +static const pciSubsystemInfo *pci_ss_list_10c8_0004[] = { + &pci_ss_info_10c8_0004_1014_00ba, + &pci_ss_info_10c8_0004_1025_1007, + &pci_ss_info_10c8_0004_1028_0074, + &pci_ss_info_10c8_0004_1028_0075, + &pci_ss_info_10c8_0004_1028_007d, + &pci_ss_info_10c8_0004_1028_007e, + &pci_ss_info_10c8_0004_1033_802f, + &pci_ss_info_10c8_0004_104d_801b, + &pci_ss_info_10c8_0004_104d_802f, + &pci_ss_info_10c8_0004_104d_830b, + &pci_ss_info_10c8_0004_10ba_0e00, + &pci_ss_info_10c8_0004_10c8_0004, + &pci_ss_info_10c8_0004_10cf_1029, + &pci_ss_info_10c8_0004_10f7_8308, + &pci_ss_info_10c8_0004_10f7_8309, + &pci_ss_info_10c8_0004_10f7_830b, + &pci_ss_info_10c8_0004_10f7_830d, + &pci_ss_info_10c8_0004_10f7_8312, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10c8_0005[] = { + &pci_ss_info_10c8_0005_1014_00dd, + &pci_ss_info_10c8_0005_1028_0088, + NULL +}; +#define pci_ss_list_10c8_0006 NULL +static const pciSubsystemInfo *pci_ss_list_10c8_0016[] = { + &pci_ss_info_10c8_0016_10c8_0016, + NULL +}; +#define pci_ss_list_10c8_0025 NULL +#define pci_ss_list_10c8_0083 NULL +static const pciSubsystemInfo *pci_ss_list_10c8_8005[] = { + &pci_ss_info_10c8_8005_0e11_b0d1, + &pci_ss_info_10c8_8005_0e11_b126, + &pci_ss_info_10c8_8005_1014_00dd, + &pci_ss_info_10c8_8005_1025_1003, + &pci_ss_info_10c8_8005_1028_0088, + &pci_ss_info_10c8_8005_1028_008f, + &pci_ss_info_10c8_8005_103c_0007, + &pci_ss_info_10c8_8005_103c_0008, + &pci_ss_info_10c8_8005_103c_000d, + &pci_ss_info_10c8_8005_10c8_8005, + &pci_ss_info_10c8_8005_110a_8005, + &pci_ss_info_10c8_8005_14c0_0004, + NULL +}; +#define pci_ss_list_10c8_8006 NULL +#define pci_ss_list_10c8_8016 NULL +#define pci_ss_list_10cc_0660 NULL +#define pci_ss_list_10cc_0661 NULL +#define pci_ss_list_10cd_1100 NULL +#define pci_ss_list_10cd_1200 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10cd_1300[] = { + &pci_ss_info_10cd_1300_10cd_1310, + &pci_ss_info_10cd_1300_1195_1320, + NULL +}; +#define pci_ss_list_10cd_2300 NULL +#define pci_ss_list_10cd_2500 NULL +#endif +#define pci_ss_list_10cf_2001 NULL +#define pci_ss_list_10d9_0431 NULL +#define pci_ss_list_10d9_0512 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10d9_0531[] = { + &pci_ss_info_10d9_0531_1186_1200, + NULL +}; +#define pci_ss_list_10d9_8625 NULL +#define pci_ss_list_10d9_8626 NULL +#define pci_ss_list_10d9_8888 NULL +#endif +#define pci_ss_list_10da_0508 NULL +#define pci_ss_list_10da_3390 NULL +#define pci_ss_list_10dc_0001 NULL +#define pci_ss_list_10dc_0002 NULL +#define pci_ss_list_10dc_0021 NULL +#define pci_ss_list_10dc_0022 NULL +#define pci_ss_list_10dc_10dc NULL +#define pci_ss_list_10dd_0100 NULL +#define pci_ss_list_10de_0008 NULL +#define pci_ss_list_10de_0009 NULL +#define pci_ss_list_10de_0010 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0020[] = { + &pci_ss_info_10de_0020_1043_0200, + &pci_ss_info_10de_0020_1048_0c18, + &pci_ss_info_10de_0020_1048_0c19, + &pci_ss_info_10de_0020_1048_0c1b, + &pci_ss_info_10de_0020_1048_0c1c, + &pci_ss_info_10de_0020_1092_0550, + &pci_ss_info_10de_0020_1092_0552, + &pci_ss_info_10de_0020_1092_4804, + &pci_ss_info_10de_0020_1092_4808, + &pci_ss_info_10de_0020_1092_4810, + &pci_ss_info_10de_0020_1092_4812, + &pci_ss_info_10de_0020_1092_4815, + &pci_ss_info_10de_0020_1092_4820, + &pci_ss_info_10de_0020_1092_4822, + &pci_ss_info_10de_0020_1092_4904, + &pci_ss_info_10de_0020_1092_4914, + &pci_ss_info_10de_0020_1092_8225, + &pci_ss_info_10de_0020_10b4_273d, + &pci_ss_info_10de_0020_10b4_273e, + &pci_ss_info_10de_0020_10b4_2740, + &pci_ss_info_10de_0020_10de_0020, + &pci_ss_info_10de_0020_1102_1015, + &pci_ss_info_10de_0020_1102_1016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0028[] = { + &pci_ss_info_10de_0028_1043_0200, + &pci_ss_info_10de_0028_1043_0201, + &pci_ss_info_10de_0028_1043_0205, + &pci_ss_info_10de_0028_1043_4000, + &pci_ss_info_10de_0028_1048_0c21, + &pci_ss_info_10de_0028_1048_0c28, + &pci_ss_info_10de_0028_1048_0c29, + &pci_ss_info_10de_0028_1048_0c2a, + &pci_ss_info_10de_0028_1048_0c2b, + &pci_ss_info_10de_0028_1048_0c31, + &pci_ss_info_10de_0028_1048_0c32, + &pci_ss_info_10de_0028_1048_0c33, + &pci_ss_info_10de_0028_1048_0c34, + &pci_ss_info_10de_0028_107d_2134, + &pci_ss_info_10de_0028_1092_4804, + &pci_ss_info_10de_0028_1092_4a00, + &pci_ss_info_10de_0028_1092_4a02, + &pci_ss_info_10de_0028_1092_5a00, + &pci_ss_info_10de_0028_1092_6a02, + &pci_ss_info_10de_0028_1092_7a02, + &pci_ss_info_10de_0028_10de_0005, + &pci_ss_info_10de_0028_10de_000f, + &pci_ss_info_10de_0028_1102_1020, + &pci_ss_info_10de_0028_1102_1026, + &pci_ss_info_10de_0028_14af_5810, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0029[] = { + &pci_ss_info_10de_0029_1043_0200, + &pci_ss_info_10de_0029_1043_0201, + &pci_ss_info_10de_0029_1043_0205, + &pci_ss_info_10de_0029_1048_0c2e, + &pci_ss_info_10de_0029_1048_0c2f, + &pci_ss_info_10de_0029_1048_0c30, + &pci_ss_info_10de_0029_1102_1021, + &pci_ss_info_10de_0029_1102_1029, + &pci_ss_info_10de_0029_1102_102f, + &pci_ss_info_10de_0029_14af_5820, + NULL +}; +#define pci_ss_list_10de_002a NULL +#define pci_ss_list_10de_002b NULL +static const pciSubsystemInfo *pci_ss_list_10de_002c[] = { + &pci_ss_info_10de_002c_1043_0200, + &pci_ss_info_10de_002c_1043_0201, + &pci_ss_info_10de_002c_1048_0c20, + &pci_ss_info_10de_002c_1048_0c21, + &pci_ss_info_10de_002c_1092_6820, + &pci_ss_info_10de_002c_1102_1031, + &pci_ss_info_10de_002c_1102_1034, + &pci_ss_info_10de_002c_14af_5008, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_002d[] = { + &pci_ss_info_10de_002d_1043_0200, + &pci_ss_info_10de_002d_1043_0201, + &pci_ss_info_10de_002d_1048_0c3a, + &pci_ss_info_10de_002d_1048_0c3b, + &pci_ss_info_10de_002d_10de_001e, + &pci_ss_info_10de_002d_1102_1023, + &pci_ss_info_10de_002d_1102_1024, + &pci_ss_info_10de_002d_1102_102c, + &pci_ss_info_10de_002d_1462_8808, + &pci_ss_info_10de_002d_1554_1041, + &pci_ss_info_10de_002d_1569_002d, + NULL +}; +#define pci_ss_list_10de_002e NULL +#define pci_ss_list_10de_002f NULL +#define pci_ss_list_10de_0034 NULL +#define pci_ss_list_10de_0035 NULL +#define pci_ss_list_10de_0036 NULL +#define pci_ss_list_10de_0037 NULL +#define pci_ss_list_10de_0038 NULL +#define pci_ss_list_10de_003a NULL +#define pci_ss_list_10de_003b NULL +#define pci_ss_list_10de_003c NULL +#define pci_ss_list_10de_003d NULL +#define pci_ss_list_10de_003e NULL +#define pci_ss_list_10de_0040 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0041[] = { + &pci_ss_info_10de_0041_1043_817b, + NULL +}; +#define pci_ss_list_10de_0042 NULL +#define pci_ss_list_10de_0043 NULL +#define pci_ss_list_10de_0044 NULL +#define pci_ss_list_10de_0045 NULL +#define pci_ss_list_10de_0046 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0047[] = { + &pci_ss_info_10de_0047_1682_2109, + NULL +}; +#define pci_ss_list_10de_0048 NULL +#define pci_ss_list_10de_0049 NULL +#define pci_ss_list_10de_004d NULL +#define pci_ss_list_10de_004e NULL +static const pciSubsystemInfo *pci_ss_list_10de_0050[] = { + &pci_ss_info_10de_0050_1043_815a, + &pci_ss_info_10de_0050_1458_0c11, + &pci_ss_info_10de_0050_1462_7100, + &pci_ss_info_10de_0050_147b_1c1a, + NULL +}; +#define pci_ss_list_10de_0051 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0052[] = { + &pci_ss_info_10de_0052_1043_815a, + &pci_ss_info_10de_0052_1458_0c11, + &pci_ss_info_10de_0052_1462_7100, + &pci_ss_info_10de_0052_147b_1c1a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0053[] = { + &pci_ss_info_10de_0053_1043_815a, + &pci_ss_info_10de_0053_1458_5002, + &pci_ss_info_10de_0053_1462_7100, + &pci_ss_info_10de_0053_147b_1c1a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0054[] = { + &pci_ss_info_10de_0054_1458_b003, + &pci_ss_info_10de_0054_1462_7100, + &pci_ss_info_10de_0054_147b_1c1a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0055[] = { + &pci_ss_info_10de_0055_1043_815a, + &pci_ss_info_10de_0055_1458_b003, + &pci_ss_info_10de_0055_147b_1c1a, + NULL +}; +#define pci_ss_list_10de_0056 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0057[] = { + &pci_ss_info_10de_0057_1043_8141, + &pci_ss_info_10de_0057_1458_e000, + &pci_ss_info_10de_0057_1462_7100, + &pci_ss_info_10de_0057_147b_1c1a, + NULL +}; +#define pci_ss_list_10de_0058 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0059[] = { + &pci_ss_info_10de_0059_1043_812a, + &pci_ss_info_10de_0059_147b_1c1a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_005a[] = { + &pci_ss_info_10de_005a_1043_815a, + &pci_ss_info_10de_005a_1458_5004, + &pci_ss_info_10de_005a_1462_7100, + &pci_ss_info_10de_005a_147b_1c1a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_005b[] = { + &pci_ss_info_10de_005b_1043_815a, + &pci_ss_info_10de_005b_1458_5004, + &pci_ss_info_10de_005b_1462_7100, + &pci_ss_info_10de_005b_147b_1c1a, + NULL +}; +#define pci_ss_list_10de_005c NULL +#define pci_ss_list_10de_005d NULL +static const pciSubsystemInfo *pci_ss_list_10de_005e[] = { + &pci_ss_info_10de_005e_10f1_2891, + &pci_ss_info_10de_005e_1458_5000, + &pci_ss_info_10de_005e_1462_7100, + &pci_ss_info_10de_005e_147b_1c1a, + NULL +}; +#define pci_ss_list_10de_005f NULL +static const pciSubsystemInfo *pci_ss_list_10de_0060[] = { + &pci_ss_info_10de_0060_1043_80ad, + &pci_ss_info_10de_0060_a0a0_03ba, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0064[] = { + &pci_ss_info_10de_0064_a0a0_03bb, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0065[] = { + &pci_ss_info_10de_0065_a0a0_03b2, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0066[] = { + &pci_ss_info_10de_0066_1043_80a7, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0067[] = { + &pci_ss_info_10de_0067_1043_0c11, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0068[] = { + &pci_ss_info_10de_0068_1043_0c11, + &pci_ss_info_10de_0068_a0a0_03b4, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_006a[] = { + &pci_ss_info_10de_006a_1043_8095, + &pci_ss_info_10de_006a_a0a0_0304, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_006b[] = { + &pci_ss_info_10de_006b_10de_006b, + NULL +}; +#define pci_ss_list_10de_006c NULL +#define pci_ss_list_10de_006d NULL +static const pciSubsystemInfo *pci_ss_list_10de_006e[] = { + &pci_ss_info_10de_006e_a0a0_0306, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0080[] = { + &pci_ss_info_10de_0080_147b_1c09, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0084[] = { + &pci_ss_info_10de_0084_147b_1c09, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0085[] = { + &pci_ss_info_10de_0085_147b_1c09, + NULL +}; +#define pci_ss_list_10de_0086 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0087[] = { + &pci_ss_info_10de_0087_147b_1c09, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0088[] = { + &pci_ss_info_10de_0088_147b_1c09, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_008a[] = { + &pci_ss_info_10de_008a_147b_1c09, + NULL +}; +#define pci_ss_list_10de_008b NULL +#define pci_ss_list_10de_008c NULL +#define pci_ss_list_10de_008e NULL +#define pci_ss_list_10de_0090 NULL +#define pci_ss_list_10de_0091 NULL +#define pci_ss_list_10de_0092 NULL +#define pci_ss_list_10de_0093 NULL +#define pci_ss_list_10de_0098 NULL +#define pci_ss_list_10de_0099 NULL +#define pci_ss_list_10de_009d NULL +static const pciSubsystemInfo *pci_ss_list_10de_00a0[] = { + &pci_ss_info_10de_00a0_14af_5810, + NULL +}; +#define pci_ss_list_10de_00c0 NULL +#define pci_ss_list_10de_00c1 NULL +#define pci_ss_list_10de_00c2 NULL +#define pci_ss_list_10de_00c3 NULL +#define pci_ss_list_10de_00c8 NULL +#define pci_ss_list_10de_00c9 NULL +#define pci_ss_list_10de_00cc NULL +static const pciSubsystemInfo *pci_ss_list_10de_00cd[] = { + &pci_ss_info_10de_00cd_10de_029b, + NULL +}; +#define pci_ss_list_10de_00ce NULL +#define pci_ss_list_10de_00d0 NULL +#define pci_ss_list_10de_00d1 NULL +#define pci_ss_list_10de_00d2 NULL +#define pci_ss_list_10de_00d3 NULL +#define pci_ss_list_10de_00d4 NULL +#define pci_ss_list_10de_00d5 NULL +#define pci_ss_list_10de_00d6 NULL +#define pci_ss_list_10de_00d7 NULL +#define pci_ss_list_10de_00d8 NULL +#define pci_ss_list_10de_00d9 NULL +#define pci_ss_list_10de_00da NULL +#define pci_ss_list_10de_00dd NULL +static const pciSubsystemInfo *pci_ss_list_10de_00df[] = { + &pci_ss_info_10de_00df_105b_0c43, + &pci_ss_info_10de_00df_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00e0[] = { + &pci_ss_info_10de_00e0_10de_0c11, + &pci_ss_info_10de_00e0_1462_7030, + &pci_ss_info_10de_00e0_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00e1[] = { + &pci_ss_info_10de_00e1_1462_7030, + &pci_ss_info_10de_00e1_147b_1c0b, + NULL +}; +#define pci_ss_list_10de_00e2 NULL +static const pciSubsystemInfo *pci_ss_list_10de_00e3[] = { + &pci_ss_info_10de_00e3_105b_0c43, + &pci_ss_info_10de_00e3_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00e4[] = { + &pci_ss_info_10de_00e4_105b_0c43, + &pci_ss_info_10de_00e4_1462_7030, + &pci_ss_info_10de_00e4_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00e5[] = { + &pci_ss_info_10de_00e5_105b_0c43, + &pci_ss_info_10de_00e5_1462_7030, + &pci_ss_info_10de_00e5_147b_1c0b, + NULL +}; +#define pci_ss_list_10de_00e6 NULL +static const pciSubsystemInfo *pci_ss_list_10de_00e7[] = { + &pci_ss_info_10de_00e7_105b_0c43, + &pci_ss_info_10de_00e7_1462_7030, + &pci_ss_info_10de_00e7_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00e8[] = { + &pci_ss_info_10de_00e8_105b_0c43, + &pci_ss_info_10de_00e8_1462_7030, + &pci_ss_info_10de_00e8_147b_1c0b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00ea[] = { + &pci_ss_info_10de_00ea_105b_0c43, + &pci_ss_info_10de_00ea_147b_1c0b, + NULL +}; +#define pci_ss_list_10de_00ed NULL +#define pci_ss_list_10de_00ee NULL +#define pci_ss_list_10de_00f0 NULL +static const pciSubsystemInfo *pci_ss_list_10de_00f1[] = { + &pci_ss_info_10de_00f1_1043_81a6, + &pci_ss_info_10de_00f1_1682_2119, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_00f2[] = { + &pci_ss_info_10de_00f2_1682_211c, + NULL +}; +#define pci_ss_list_10de_00f3 NULL +#define pci_ss_list_10de_00f4 NULL +#define pci_ss_list_10de_00f5 NULL +static const pciSubsystemInfo *pci_ss_list_10de_00f6[] = { + &pci_ss_info_10de_00f6_1682_217e, + NULL +}; +#define pci_ss_list_10de_00f8 NULL +static const pciSubsystemInfo *pci_ss_list_10de_00f9[] = { + &pci_ss_info_10de_00f9_1682_2120, + NULL +}; +#define pci_ss_list_10de_00fa NULL +#define pci_ss_list_10de_00fb NULL +#define pci_ss_list_10de_00fc NULL +#define pci_ss_list_10de_00fd NULL +#define pci_ss_list_10de_00fe NULL +#define pci_ss_list_10de_00ff NULL +static const pciSubsystemInfo *pci_ss_list_10de_0100[] = { + &pci_ss_info_10de_0100_1043_0200, + &pci_ss_info_10de_0100_1043_0201, + &pci_ss_info_10de_0100_1043_4008, + &pci_ss_info_10de_0100_1043_4009, + &pci_ss_info_10de_0100_1048_0c41, + &pci_ss_info_10de_0100_1048_0c43, + &pci_ss_info_10de_0100_1048_0c48, + &pci_ss_info_10de_0100_1102_102d, + &pci_ss_info_10de_0100_14af_5022, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0101[] = { + &pci_ss_info_10de_0101_1043_0202, + &pci_ss_info_10de_0101_1043_400a, + &pci_ss_info_10de_0101_1043_400b, + &pci_ss_info_10de_0101_1048_0c42, + &pci_ss_info_10de_0101_107d_2822, + &pci_ss_info_10de_0101_1102_102e, + &pci_ss_info_10de_0101_14af_5021, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0103[] = { + &pci_ss_info_10de_0103_1048_0c40, + &pci_ss_info_10de_0103_1048_0c44, + &pci_ss_info_10de_0103_1048_0c45, + &pci_ss_info_10de_0103_1048_0c4a, + &pci_ss_info_10de_0103_1048_0c4b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0110[] = { + &pci_ss_info_10de_0110_1043_4015, + &pci_ss_info_10de_0110_1043_4031, + &pci_ss_info_10de_0110_1048_0c60, + &pci_ss_info_10de_0110_1048_0c61, + &pci_ss_info_10de_0110_1048_0c63, + &pci_ss_info_10de_0110_1048_0c64, + &pci_ss_info_10de_0110_1048_0c65, + &pci_ss_info_10de_0110_1048_0c66, + &pci_ss_info_10de_0110_10de_0091, + &pci_ss_info_10de_0110_10de_00a1, + &pci_ss_info_10de_0110_1462_8817, + &pci_ss_info_10de_0110_14af_7102, + &pci_ss_info_10de_0110_14af_7103, + NULL +}; +#define pci_ss_list_10de_0111 NULL +#define pci_ss_list_10de_0112 NULL +#define pci_ss_list_10de_0113 NULL +#define pci_ss_list_10de_0140 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0141[] = { + &pci_ss_info_10de_0141_1458_3124, + NULL +}; +#define pci_ss_list_10de_0142 NULL +#define pci_ss_list_10de_0144 NULL +#define pci_ss_list_10de_0145 NULL +#define pci_ss_list_10de_0146 NULL +#define pci_ss_list_10de_0147 NULL +#define pci_ss_list_10de_0148 NULL +#define pci_ss_list_10de_0149 NULL +#define pci_ss_list_10de_014a NULL +#define pci_ss_list_10de_014c NULL +#define pci_ss_list_10de_014d NULL +#define pci_ss_list_10de_014e NULL +#define pci_ss_list_10de_014f NULL +static const pciSubsystemInfo *pci_ss_list_10de_0150[] = { + &pci_ss_info_10de_0150_1043_4016, + &pci_ss_info_10de_0150_1048_0c50, + &pci_ss_info_10de_0150_1048_0c52, + &pci_ss_info_10de_0150_107d_2840, + &pci_ss_info_10de_0150_107d_2842, + &pci_ss_info_10de_0150_10de_002e, + &pci_ss_info_10de_0150_1462_8831, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0151[] = { + &pci_ss_info_10de_0151_1043_405f, + &pci_ss_info_10de_0151_1462_5506, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0152[] = { + &pci_ss_info_10de_0152_1048_0c56, + NULL +}; +#define pci_ss_list_10de_0153 NULL +#define pci_ss_list_10de_0160 NULL +#define pci_ss_list_10de_0161 NULL +#define pci_ss_list_10de_0162 NULL +#define pci_ss_list_10de_0163 NULL +#define pci_ss_list_10de_0164 NULL +#define pci_ss_list_10de_0165 NULL +#define pci_ss_list_10de_0166 NULL +#define pci_ss_list_10de_0167 NULL +#define pci_ss_list_10de_0168 NULL +#define pci_ss_list_10de_0169 NULL +#define pci_ss_list_10de_0170 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0171[] = { + &pci_ss_info_10de_0171_10b0_0002, + &pci_ss_info_10de_0171_10de_0008, + &pci_ss_info_10de_0171_1462_8661, + &pci_ss_info_10de_0171_1462_8730, + &pci_ss_info_10de_0171_1462_8852, + &pci_ss_info_10de_0171_147b_8f00, + NULL +}; +#define pci_ss_list_10de_0172 NULL +#define pci_ss_list_10de_0173 NULL +#define pci_ss_list_10de_0174 NULL +#define pci_ss_list_10de_0175 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0176[] = { + &pci_ss_info_10de_0176_103c_08b0, + &pci_ss_info_10de_0176_4c53_1090, + NULL +}; +#define pci_ss_list_10de_0177 NULL +#define pci_ss_list_10de_0178 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0179[] = { + &pci_ss_info_10de_0179_10de_0179, + NULL +}; +#define pci_ss_list_10de_017a NULL +#define pci_ss_list_10de_017b NULL +#define pci_ss_list_10de_017c NULL +#define pci_ss_list_10de_017d NULL +static const pciSubsystemInfo *pci_ss_list_10de_0181[] = { + &pci_ss_info_10de_0181_1043_8063, + &pci_ss_info_10de_0181_1043_806f, + &pci_ss_info_10de_0181_1462_8880, + &pci_ss_info_10de_0181_1462_8900, + &pci_ss_info_10de_0181_1462_9350, + &pci_ss_info_10de_0181_147b_8f0d, + NULL +}; +#define pci_ss_list_10de_0182 NULL +#define pci_ss_list_10de_0183 NULL +#define pci_ss_list_10de_0185 NULL +#define pci_ss_list_10de_0186 NULL +#define pci_ss_list_10de_0187 NULL +#define pci_ss_list_10de_0188 NULL +#define pci_ss_list_10de_018a NULL +#define pci_ss_list_10de_018b NULL +#define pci_ss_list_10de_018c NULL +#define pci_ss_list_10de_018d NULL +#define pci_ss_list_10de_01a0 NULL +#define pci_ss_list_10de_01a4 NULL +#define pci_ss_list_10de_01ab NULL +#define pci_ss_list_10de_01ac NULL +#define pci_ss_list_10de_01ad NULL +#define pci_ss_list_10de_01b0 NULL +#define pci_ss_list_10de_01b1 NULL +#define pci_ss_list_10de_01b2 NULL +#define pci_ss_list_10de_01b4 NULL +#define pci_ss_list_10de_01b7 NULL +#define pci_ss_list_10de_01b8 NULL +#define pci_ss_list_10de_01bc NULL +#define pci_ss_list_10de_01c1 NULL +#define pci_ss_list_10de_01c2 NULL +#define pci_ss_list_10de_01c3 NULL +static const pciSubsystemInfo *pci_ss_list_10de_01d1[] = { + &pci_ss_info_10de_01d1_1462_0345, + NULL +}; +#define pci_ss_list_10de_01d6 NULL +#define pci_ss_list_10de_01d7 NULL +#define pci_ss_list_10de_01d8 NULL +#define pci_ss_list_10de_01da NULL +static const pciSubsystemInfo *pci_ss_list_10de_01de[] = { + &pci_ss_info_10de_01de_10de_01dc, + NULL +}; +#define pci_ss_list_10de_01df NULL +static const pciSubsystemInfo *pci_ss_list_10de_01e0[] = { + &pci_ss_info_10de_01e0_147b_1c09, + NULL +}; +#define pci_ss_list_10de_01e8 NULL +static const pciSubsystemInfo *pci_ss_list_10de_01ea[] = { + &pci_ss_info_10de_01ea_a0a0_03b9, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_01eb[] = { + &pci_ss_info_10de_01eb_a0a0_03b9, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_01ec[] = { + &pci_ss_info_10de_01ec_a0a0_03b9, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_01ed[] = { + &pci_ss_info_10de_01ed_a0a0_03b9, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_01ee[] = { + &pci_ss_info_10de_01ee_a0a0_03b9, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_01ef[] = { + &pci_ss_info_10de_01ef_a0a0_03b9, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_01f0[] = { + &pci_ss_info_10de_01f0_a0a0_03b5, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0200[] = { + &pci_ss_info_10de_0200_1043_402f, + &pci_ss_info_10de_0200_1048_0c70, + NULL +}; +#define pci_ss_list_10de_0201 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0202[] = { + &pci_ss_info_10de_0202_1043_405b, + &pci_ss_info_10de_0202_1545_002f, + NULL +}; +#define pci_ss_list_10de_0203 NULL +#define pci_ss_list_10de_0211 NULL +#define pci_ss_list_10de_0212 NULL +#define pci_ss_list_10de_0215 NULL +#define pci_ss_list_10de_0218 NULL +#define pci_ss_list_10de_0221 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0240[] = { + &pci_ss_info_10de_0240_1462_7207, + NULL +}; +#define pci_ss_list_10de_0241 NULL +#define pci_ss_list_10de_0242 NULL +#define pci_ss_list_10de_0243 NULL +#define pci_ss_list_10de_0244 NULL +#define pci_ss_list_10de_0245 NULL +#define pci_ss_list_10de_0246 NULL +#define pci_ss_list_10de_0247 NULL +#define pci_ss_list_10de_0248 NULL +#define pci_ss_list_10de_0249 NULL +#define pci_ss_list_10de_024a NULL +#define pci_ss_list_10de_024b NULL +#define pci_ss_list_10de_024c NULL +#define pci_ss_list_10de_024d NULL +#define pci_ss_list_10de_024e NULL +#define pci_ss_list_10de_024f NULL +#define pci_ss_list_10de_0250 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0251[] = { + &pci_ss_info_10de_0251_1043_8023, + NULL +}; +#define pci_ss_list_10de_0252 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0253[] = { + &pci_ss_info_10de_0253_107d_2896, + &pci_ss_info_10de_0253_147b_8f09, + NULL +}; +#define pci_ss_list_10de_0258 NULL +#define pci_ss_list_10de_0259 NULL +#define pci_ss_list_10de_025b NULL +static const pciSubsystemInfo *pci_ss_list_10de_0260[] = { + &pci_ss_info_10de_0260_1462_7207, + NULL +}; +#define pci_ss_list_10de_0261 NULL +#define pci_ss_list_10de_0262 NULL +#define pci_ss_list_10de_0263 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0264[] = { + &pci_ss_info_10de_0264_1462_7207, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0265[] = { + &pci_ss_info_10de_0265_1462_7207, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0266[] = { + &pci_ss_info_10de_0266_1462_7207, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_0267[] = { + &pci_ss_info_10de_0267_1462_7207, + NULL +}; +#define pci_ss_list_10de_0268 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0269[] = { + &pci_ss_info_10de_0269_1462_7207, + NULL +}; +#define pci_ss_list_10de_026a NULL +#define pci_ss_list_10de_026b NULL +static const pciSubsystemInfo *pci_ss_list_10de_026c[] = { + &pci_ss_info_10de_026c_1462_7207, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_026d[] = { + &pci_ss_info_10de_026d_1462_7207, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_026e[] = { + &pci_ss_info_10de_026e_1462_7207, + NULL +}; +#define pci_ss_list_10de_026f NULL +static const pciSubsystemInfo *pci_ss_list_10de_0270[] = { + &pci_ss_info_10de_0270_1462_7207, + NULL +}; +#define pci_ss_list_10de_0271 NULL +#define pci_ss_list_10de_0272 NULL +static const pciSubsystemInfo *pci_ss_list_10de_027e[] = { + &pci_ss_info_10de_027e_1462_7207, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_027f[] = { + &pci_ss_info_10de_027f_1462_7207, + NULL +}; +#define pci_ss_list_10de_0280 NULL +#define pci_ss_list_10de_0281 NULL +#define pci_ss_list_10de_0282 NULL +#define pci_ss_list_10de_0286 NULL +#define pci_ss_list_10de_0288 NULL +#define pci_ss_list_10de_0289 NULL +#define pci_ss_list_10de_028c NULL +#define pci_ss_list_10de_0290 NULL +#define pci_ss_list_10de_0291 NULL +#define pci_ss_list_10de_0292 NULL +#define pci_ss_list_10de_0298 NULL +#define pci_ss_list_10de_0299 NULL +#define pci_ss_list_10de_029a NULL +#define pci_ss_list_10de_029b NULL +#define pci_ss_list_10de_029c NULL +#define pci_ss_list_10de_029d NULL +#define pci_ss_list_10de_029e NULL +#define pci_ss_list_10de_029f NULL +#define pci_ss_list_10de_02a0 NULL +#define pci_ss_list_10de_02e1 NULL +static const pciSubsystemInfo *pci_ss_list_10de_02f0[] = { + &pci_ss_info_10de_02f0_1462_7207, + NULL +}; +#define pci_ss_list_10de_02f1 NULL +#define pci_ss_list_10de_02f2 NULL +#define pci_ss_list_10de_02f3 NULL +#define pci_ss_list_10de_02f4 NULL +#define pci_ss_list_10de_02f5 NULL +#define pci_ss_list_10de_02f6 NULL +#define pci_ss_list_10de_02f7 NULL +static const pciSubsystemInfo *pci_ss_list_10de_02f8[] = { + &pci_ss_info_10de_02f8_1462_7207, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_02f9[] = { + &pci_ss_info_10de_02f9_1462_7207, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_02fa[] = { + &pci_ss_info_10de_02fa_1462_7207, + NULL +}; +#define pci_ss_list_10de_02fb NULL +#define pci_ss_list_10de_02fc NULL +#define pci_ss_list_10de_02fd NULL +static const pciSubsystemInfo *pci_ss_list_10de_02fe[] = { + &pci_ss_info_10de_02fe_1462_7207, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10de_02ff[] = { + &pci_ss_info_10de_02ff_1462_7207, + NULL +}; +#define pci_ss_list_10de_0300 NULL +#define pci_ss_list_10de_0301 NULL +#define pci_ss_list_10de_0302 NULL +#define pci_ss_list_10de_0308 NULL +#define pci_ss_list_10de_0309 NULL +#define pci_ss_list_10de_0311 NULL +#define pci_ss_list_10de_0312 NULL +#define pci_ss_list_10de_0313 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0314[] = { + &pci_ss_info_10de_0314_1043_814a, + NULL +}; +#define pci_ss_list_10de_0316 NULL +#define pci_ss_list_10de_0317 NULL +#define pci_ss_list_10de_031a NULL +#define pci_ss_list_10de_031b NULL +#define pci_ss_list_10de_031c NULL +#define pci_ss_list_10de_031d NULL +#define pci_ss_list_10de_031e NULL +#define pci_ss_list_10de_031f NULL +#define pci_ss_list_10de_0320 NULL +#define pci_ss_list_10de_0321 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0322[] = { + &pci_ss_info_10de_0322_1462_9171, + &pci_ss_info_10de_0322_1462_9360, + NULL +}; +#define pci_ss_list_10de_0323 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0324[] = { + &pci_ss_info_10de_0324_1028_0196, + &pci_ss_info_10de_0324_1071_8160, + NULL +}; +#define pci_ss_list_10de_0325 NULL +#define pci_ss_list_10de_0326 NULL +#define pci_ss_list_10de_0327 NULL +#define pci_ss_list_10de_0328 NULL +#define pci_ss_list_10de_0329 NULL +#define pci_ss_list_10de_032a NULL +#define pci_ss_list_10de_032b NULL +#define pci_ss_list_10de_032c NULL +#define pci_ss_list_10de_032d NULL +#define pci_ss_list_10de_032f NULL +#define pci_ss_list_10de_0330 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0331[] = { + &pci_ss_info_10de_0331_1043_8145, + NULL +}; +#define pci_ss_list_10de_0332 NULL +#define pci_ss_list_10de_0333 NULL +#define pci_ss_list_10de_0334 NULL +#define pci_ss_list_10de_0338 NULL +#define pci_ss_list_10de_033f NULL +#define pci_ss_list_10de_0341 NULL +#define pci_ss_list_10de_0342 NULL +#define pci_ss_list_10de_0343 NULL +#define pci_ss_list_10de_0344 NULL +#define pci_ss_list_10de_0345 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0347[] = { + &pci_ss_info_10de_0347_103c_006a, + NULL +}; +#define pci_ss_list_10de_0348 NULL +#define pci_ss_list_10de_0349 NULL +#define pci_ss_list_10de_034b NULL +#define pci_ss_list_10de_034c NULL +#define pci_ss_list_10de_034e NULL +#define pci_ss_list_10de_034f NULL +#define pci_ss_list_10de_0360 NULL +#define pci_ss_list_10de_0361 NULL +#define pci_ss_list_10de_0362 NULL +#define pci_ss_list_10de_0363 NULL +#define pci_ss_list_10de_0364 NULL +#define pci_ss_list_10de_0365 NULL +#define pci_ss_list_10de_0366 NULL +#define pci_ss_list_10de_0367 NULL +#define pci_ss_list_10de_0368 NULL +#define pci_ss_list_10de_0369 NULL +#define pci_ss_list_10de_036a NULL +#define pci_ss_list_10de_036b NULL +#define pci_ss_list_10de_036c NULL +#define pci_ss_list_10de_036d NULL +#define pci_ss_list_10de_036e NULL +#define pci_ss_list_10de_0370 NULL +#define pci_ss_list_10de_0371 NULL +#define pci_ss_list_10de_0372 NULL +#define pci_ss_list_10de_0373 NULL +#define pci_ss_list_10de_0374 NULL +#define pci_ss_list_10de_0375 NULL +#define pci_ss_list_10de_0376 NULL +#define pci_ss_list_10de_0377 NULL +#define pci_ss_list_10de_0378 NULL +#define pci_ss_list_10de_037a NULL +#define pci_ss_list_10de_037e NULL +#define pci_ss_list_10de_037f NULL +#define pci_ss_list_10de_0391 NULL +static const pciSubsystemInfo *pci_ss_list_10de_0392[] = { + &pci_ss_info_10de_0392_1462_0622, + NULL +}; +#define pci_ss_list_10de_0393 NULL +#define pci_ss_list_10de_0398 NULL +#define pci_ss_list_10de_039e NULL +#define pci_ss_list_10de_03a0 NULL +#define pci_ss_list_10de_03a1 NULL +#define pci_ss_list_10de_03a2 NULL +#define pci_ss_list_10de_03a3 NULL +#define pci_ss_list_10de_03a4 NULL +#define pci_ss_list_10de_03a5 NULL +#define pci_ss_list_10de_03a6 NULL +#define pci_ss_list_10de_03a7 NULL +#define pci_ss_list_10de_03a8 NULL +#define pci_ss_list_10de_03a9 NULL +#define pci_ss_list_10de_03aa NULL +#define pci_ss_list_10de_03ab NULL +#define pci_ss_list_10de_03ac NULL +#define pci_ss_list_10de_03ad NULL +#define pci_ss_list_10de_03ae NULL +#define pci_ss_list_10de_03af NULL +#define pci_ss_list_10de_03b0 NULL +#define pci_ss_list_10de_03b1 NULL +#define pci_ss_list_10de_03b2 NULL +#define pci_ss_list_10de_03b3 NULL +#define pci_ss_list_10de_03b4 NULL +#define pci_ss_list_10de_03b5 NULL +#define pci_ss_list_10de_03b6 NULL +#define pci_ss_list_10de_03b7 NULL +#define pci_ss_list_10de_03b8 NULL +#define pci_ss_list_10de_03b9 NULL +#define pci_ss_list_10de_03ba NULL +#define pci_ss_list_10de_03bb NULL +#define pci_ss_list_10de_03d0 NULL +#define pci_ss_list_10de_03d1 NULL +#define pci_ss_list_10de_03d2 NULL +#define pci_ss_list_10de_03d5 NULL +#define pci_ss_list_10de_03e0 NULL +#define pci_ss_list_10de_03e1 NULL +#define pci_ss_list_10de_03e2 NULL +#define pci_ss_list_10de_03e3 NULL +#define pci_ss_list_10de_03e4 NULL +#define pci_ss_list_10de_03e5 NULL +#define pci_ss_list_10de_03e6 NULL +#define pci_ss_list_10de_03e7 NULL +#define pci_ss_list_10de_03e8 NULL +#define pci_ss_list_10de_03e9 NULL +#define pci_ss_list_10de_03ea NULL +#define pci_ss_list_10de_03eb NULL +#define pci_ss_list_10de_03ec NULL +#define pci_ss_list_10de_03ee NULL +#define pci_ss_list_10de_03ef NULL +#define pci_ss_list_10de_03f0 NULL +#define pci_ss_list_10de_03f1 NULL +#define pci_ss_list_10de_03f2 NULL +#define pci_ss_list_10de_03f3 NULL +#define pci_ss_list_10de_03f4 NULL +#define pci_ss_list_10de_03f5 NULL +#define pci_ss_list_10de_03f6 NULL +#define pci_ss_list_10de_03f7 NULL +#define pci_ss_list_10de_0440 NULL +#define pci_ss_list_10de_0441 NULL +#define pci_ss_list_10de_0442 NULL +#define pci_ss_list_10de_0443 NULL +#define pci_ss_list_10de_0444 NULL +#define pci_ss_list_10de_0445 NULL +#define pci_ss_list_10de_0446 NULL +#define pci_ss_list_10de_0447 NULL +#define pci_ss_list_10de_0448 NULL +#define pci_ss_list_10de_0449 NULL +#define pci_ss_list_10de_044a NULL +#define pci_ss_list_10de_044b NULL +#define pci_ss_list_10de_044c NULL +#define pci_ss_list_10de_044d NULL +#define pci_ss_list_10de_044e NULL +#define pci_ss_list_10de_044f NULL +#define pci_ss_list_10de_0450 NULL +#define pci_ss_list_10de_0451 NULL +#define pci_ss_list_10de_0452 NULL +#define pci_ss_list_10de_0453 NULL +#define pci_ss_list_10de_0454 NULL +#define pci_ss_list_10de_0455 NULL +#define pci_ss_list_10de_0456 NULL +#define pci_ss_list_10de_0457 NULL +#define pci_ss_list_10de_0458 NULL +#define pci_ss_list_10de_0459 NULL +#define pci_ss_list_10de_045a NULL +#define pci_ss_list_10de_045c NULL +#define pci_ss_list_10de_045d NULL +#define pci_ss_list_10de_045e NULL +#define pci_ss_list_10de_045f NULL +#define pci_ss_list_10df_1ae5 NULL +#define pci_ss_list_10df_f085 NULL +#define pci_ss_list_10df_f095 NULL +#define pci_ss_list_10df_f098 NULL +#define pci_ss_list_10df_f0a1 NULL +#define pci_ss_list_10df_f0a5 NULL +#define pci_ss_list_10df_f0b5 NULL +#define pci_ss_list_10df_f0d1 NULL +#define pci_ss_list_10df_f0d5 NULL +#define pci_ss_list_10df_f0e1 NULL +#define pci_ss_list_10df_f0e5 NULL +#define pci_ss_list_10df_f0f5 NULL +#define pci_ss_list_10df_f700 NULL +#define pci_ss_list_10df_f701 NULL +#define pci_ss_list_10df_f800 NULL +#define pci_ss_list_10df_f801 NULL +#define pci_ss_list_10df_f900 NULL +#define pci_ss_list_10df_f901 NULL +#define pci_ss_list_10df_f980 NULL +#define pci_ss_list_10df_f981 NULL +#define pci_ss_list_10df_f982 NULL +#define pci_ss_list_10df_fa00 NULL +#define pci_ss_list_10df_fb00 NULL +#define pci_ss_list_10df_fc00 NULL +#define pci_ss_list_10df_fc10 NULL +#define pci_ss_list_10df_fc20 NULL +#define pci_ss_list_10df_fd00 NULL +#define pci_ss_list_10df_fe00 NULL +#define pci_ss_list_10df_ff00 NULL +#define pci_ss_list_10e0_5026 NULL +#define pci_ss_list_10e0_5027 NULL +#define pci_ss_list_10e0_5028 NULL +#define pci_ss_list_10e0_8849 NULL +#define pci_ss_list_10e0_8853 NULL +#define pci_ss_list_10e0_9128 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10e1_0391[] = { + &pci_ss_info_10e1_0391_10e1_0391, + NULL +}; +#define pci_ss_list_10e1_690c NULL +#define pci_ss_list_10e1_dc29 NULL +#endif +#define pci_ss_list_10e3_0000 NULL +#define pci_ss_list_10e3_0108 NULL +#define pci_ss_list_10e3_0148 NULL +#define pci_ss_list_10e3_0860 NULL +#define pci_ss_list_10e3_0862 NULL +#define pci_ss_list_10e3_8260 NULL +#define pci_ss_list_10e3_8261 NULL +#define pci_ss_list_10e3_a108 NULL +#define pci_ss_list_10e4_8029 NULL +#define pci_ss_list_10e8_1072 NULL +#define pci_ss_list_10e8_2011 NULL +#define pci_ss_list_10e8_4750 NULL +#define pci_ss_list_10e8_5920 NULL +#define pci_ss_list_10e8_8043 NULL +#define pci_ss_list_10e8_8062 NULL +#define pci_ss_list_10e8_807d NULL +#define pci_ss_list_10e8_8088 NULL +#define pci_ss_list_10e8_8089 NULL +#define pci_ss_list_10e8_809c NULL +#define pci_ss_list_10e8_80d7 NULL +#define pci_ss_list_10e8_80d9 NULL +#define pci_ss_list_10e8_80da NULL +#define pci_ss_list_10e8_811a NULL +#define pci_ss_list_10e8_814c NULL +#define pci_ss_list_10e8_8170 NULL +#define pci_ss_list_10e8_81e6 NULL +#define pci_ss_list_10e8_8291 NULL +#define pci_ss_list_10e8_82c4 NULL +#define pci_ss_list_10e8_82c5 NULL +#define pci_ss_list_10e8_82c6 NULL +#define pci_ss_list_10e8_82c7 NULL +#define pci_ss_list_10e8_82ca NULL +#define pci_ss_list_10e8_82db NULL +#define pci_ss_list_10e8_82e2 NULL +#define pci_ss_list_10e8_8851 NULL +#define pci_ss_list_10ea_1680 NULL +#define pci_ss_list_10ea_1682 NULL +#define pci_ss_list_10ea_1683 NULL +#define pci_ss_list_10ea_2000 NULL +#define pci_ss_list_10ea_2010 NULL +#define pci_ss_list_10ea_5000 NULL +#define pci_ss_list_10ea_5050 NULL +#define pci_ss_list_10ea_5202 NULL +#define pci_ss_list_10ea_5252 NULL +#define pci_ss_list_10eb_0101 NULL +#define pci_ss_list_10eb_8111 NULL +#define pci_ss_list_10ec_0139 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10ec_0883[] = { + &pci_ss_info_10ec_0883_1025_1605, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10ec_8029[] = { + &pci_ss_info_10ec_8029_10b8_2011, + &pci_ss_info_10ec_8029_10ec_8029, + &pci_ss_info_10ec_8029_1113_1208, + &pci_ss_info_10ec_8029_1186_0300, + &pci_ss_info_10ec_8029_1259_2400, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10ec_8129[] = { + &pci_ss_info_10ec_8129_10ec_8129, + NULL +}; +#define pci_ss_list_10ec_8136 NULL +static const pciSubsystemInfo *pci_ss_list_10ec_8138[] = { + &pci_ss_info_10ec_8138_10ec_8138, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_10ec_8139[] = { + &pci_ss_info_10ec_8139_0357_000a, + &pci_ss_info_10ec_8139_1025_005a, + &pci_ss_info_10ec_8139_1025_8920, + &pci_ss_info_10ec_8139_1025_8921, + &pci_ss_info_10ec_8139_103c_006a, + &pci_ss_info_10ec_8139_1043_8109, + &pci_ss_info_10ec_8139_1071_8160, + &pci_ss_info_10ec_8139_10bd_0320, + &pci_ss_info_10ec_8139_10ec_8139, + &pci_ss_info_10ec_8139_1113_ec01, + &pci_ss_info_10ec_8139_1186_1300, + &pci_ss_info_10ec_8139_1186_1320, + &pci_ss_info_10ec_8139_1186_8139, + &pci_ss_info_10ec_8139_11f6_8139, + &pci_ss_info_10ec_8139_1259_2500, + &pci_ss_info_10ec_8139_1259_2503, + &pci_ss_info_10ec_8139_1429_d010, + &pci_ss_info_10ec_8139_1432_9130, + &pci_ss_info_10ec_8139_1436_8139, + &pci_ss_info_10ec_8139_1458_e000, + &pci_ss_info_10ec_8139_1462_788c, + &pci_ss_info_10ec_8139_146c_1439, + &pci_ss_info_10ec_8139_1489_6001, + &pci_ss_info_10ec_8139_1489_6002, + &pci_ss_info_10ec_8139_149c_139a, + &pci_ss_info_10ec_8139_149c_8139, + &pci_ss_info_10ec_8139_14cb_0200, + &pci_ss_info_10ec_8139_1695_9001, + &pci_ss_info_10ec_8139_1799_5000, + &pci_ss_info_10ec_8139_1904_8139, + &pci_ss_info_10ec_8139_2646_0001, + &pci_ss_info_10ec_8139_8e2e_7000, + &pci_ss_info_10ec_8139_8e2e_7100, + &pci_ss_info_10ec_8139_a0a0_0007, + NULL +}; +#define pci_ss_list_10ec_8167 NULL +#define pci_ss_list_10ec_8168 NULL +static const pciSubsystemInfo *pci_ss_list_10ec_8169[] = { + &pci_ss_info_10ec_8169_1025_0079, + &pci_ss_info_10ec_8169_1259_c107, + &pci_ss_info_10ec_8169_1371_434e, + &pci_ss_info_10ec_8169_1458_e000, + &pci_ss_info_10ec_8169_1462_702c, + NULL +}; +#define pci_ss_list_10ec_8180 NULL +#define pci_ss_list_10ec_8185 NULL +#define pci_ss_list_10ec_8197 NULL +#endif +#define pci_ss_list_10ed_7310 NULL +#define pci_ss_list_10ee_0205 NULL +#define pci_ss_list_10ee_0210 NULL +#define pci_ss_list_10ee_0314 NULL +#define pci_ss_list_10ee_0405 NULL +#define pci_ss_list_10ee_0410 NULL +#define pci_ss_list_10ee_3fc0 NULL +#define pci_ss_list_10ee_3fc1 NULL +#define pci_ss_list_10ee_3fc2 NULL +#define pci_ss_list_10ee_3fc3 NULL +#define pci_ss_list_10ee_3fc4 NULL +#define pci_ss_list_10ee_3fc5 NULL +#define pci_ss_list_10ee_3fc6 NULL +#define pci_ss_list_10ee_8381 NULL +#define pci_ss_list_10ee_d154 NULL +#define pci_ss_list_10ef_8154 NULL +#define pci_ss_list_10f1_2865 NULL +#define pci_ss_list_10f5_a001 NULL +#define pci_ss_list_10fa_000c NULL +#define pci_ss_list_10fb_186f NULL +#define pci_ss_list_10fc_0003 NULL +#define pci_ss_list_10fc_0005 NULL +#define pci_ss_list_1101_1060 NULL +#define pci_ss_list_1101_1622 NULL +#define pci_ss_list_1101_9100 NULL +#define pci_ss_list_1101_9400 NULL +#define pci_ss_list_1101_9401 NULL +#define pci_ss_list_1101_9500 NULL +#define pci_ss_list_1101_9502 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1102_0002[] = { + &pci_ss_info_1102_0002_1102_0020, + &pci_ss_info_1102_0002_1102_0021, + &pci_ss_info_1102_0002_1102_002f, + &pci_ss_info_1102_0002_1102_100a, + &pci_ss_info_1102_0002_1102_4001, + &pci_ss_info_1102_0002_1102_8022, + &pci_ss_info_1102_0002_1102_8023, + &pci_ss_info_1102_0002_1102_8024, + &pci_ss_info_1102_0002_1102_8025, + &pci_ss_info_1102_0002_1102_8026, + &pci_ss_info_1102_0002_1102_8027, + &pci_ss_info_1102_0002_1102_8028, + &pci_ss_info_1102_0002_1102_8031, + &pci_ss_info_1102_0002_1102_8040, + &pci_ss_info_1102_0002_1102_8051, + &pci_ss_info_1102_0002_1102_8061, + &pci_ss_info_1102_0002_1102_8064, + &pci_ss_info_1102_0002_1102_8065, + &pci_ss_info_1102_0002_1102_8067, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1102_0004[] = { + &pci_ss_info_1102_0004_1102_0051, + &pci_ss_info_1102_0004_1102_0053, + &pci_ss_info_1102_0004_1102_0058, + &pci_ss_info_1102_0004_1102_1007, + &pci_ss_info_1102_0004_1102_2002, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1102_0005[] = { + &pci_ss_info_1102_0005_1102_0021, + &pci_ss_info_1102_0005_1102_1003, + NULL +}; +#define pci_ss_list_1102_0006 NULL +static const pciSubsystemInfo *pci_ss_list_1102_0007[] = { + &pci_ss_info_1102_0007_1102_0007, + &pci_ss_info_1102_0007_1102_1001, + &pci_ss_info_1102_0007_1102_1002, + &pci_ss_info_1102_0007_1102_1006, + &pci_ss_info_1102_0007_1462_1009, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1102_0008[] = { + &pci_ss_info_1102_0008_1102_0008, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1102_4001[] = { + &pci_ss_info_1102_4001_1102_0010, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1102_7002[] = { + &pci_ss_info_1102_7002_1102_0020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1102_7003[] = { + &pci_ss_info_1102_7003_1102_0040, + NULL +}; +#define pci_ss_list_1102_7004 NULL +static const pciSubsystemInfo *pci_ss_list_1102_7005[] = { + &pci_ss_info_1102_7005_1102_1001, + &pci_ss_info_1102_7005_1102_1002, + NULL +}; +#define pci_ss_list_1102_8064 NULL +static const pciSubsystemInfo *pci_ss_list_1102_8938[] = { + &pci_ss_info_1102_8938_1033_80e5, + &pci_ss_info_1102_8938_1071_7150, + &pci_ss_info_1102_8938_110a_5938, + &pci_ss_info_1102_8938_13bd_100c, + &pci_ss_info_1102_8938_13bd_100d, + &pci_ss_info_1102_8938_13bd_100e, + &pci_ss_info_1102_8938_13bd_f6f1, + &pci_ss_info_1102_8938_14ff_0e70, + &pci_ss_info_1102_8938_14ff_c401, + &pci_ss_info_1102_8938_156d_b400, + &pci_ss_info_1102_8938_156d_b550, + &pci_ss_info_1102_8938_156d_b560, + &pci_ss_info_1102_8938_156d_b700, + &pci_ss_info_1102_8938_156d_b795, + &pci_ss_info_1102_8938_156d_b797, + NULL +}; +#endif +#define pci_ss_list_1103_0003 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1103_0004[] = { + &pci_ss_info_1103_0004_1103_0001, + &pci_ss_info_1103_0004_1103_0004, + &pci_ss_info_1103_0004_1103_0005, + NULL +}; +#define pci_ss_list_1103_0005 NULL +#define pci_ss_list_1103_0006 NULL +#define pci_ss_list_1103_0007 NULL +#define pci_ss_list_1103_0008 NULL +#define pci_ss_list_1103_0009 NULL +#endif +#define pci_ss_list_1105_1105 NULL +#define pci_ss_list_1105_8300 NULL +#define pci_ss_list_1105_8400 NULL +#define pci_ss_list_1105_8401 NULL +#define pci_ss_list_1105_8470 NULL +#define pci_ss_list_1105_8471 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1105_8475[] = { + &pci_ss_info_1105_8475_1105_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1105_8476[] = { + &pci_ss_info_1105_8476_127d_0000, + NULL +}; +#define pci_ss_list_1105_8485 NULL +#define pci_ss_list_1105_8486 NULL +#endif +#define pci_ss_list_1106_0102 NULL +#define pci_ss_list_1106_0130 NULL +#define pci_ss_list_1106_0204 NULL +#define pci_ss_list_1106_0208 NULL +#define pci_ss_list_1106_0238 NULL +#define pci_ss_list_1106_0258 NULL +#define pci_ss_list_1106_0259 NULL +#define pci_ss_list_1106_0269 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1106_0282[] = { + &pci_ss_info_1106_0282_1043_80a3, + NULL +}; +#define pci_ss_list_1106_0290 NULL +#define pci_ss_list_1106_0293 NULL +#define pci_ss_list_1106_0296 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0305[] = { + &pci_ss_info_1106_0305_1019_0987, + &pci_ss_info_1106_0305_1043_8033, + &pci_ss_info_1106_0305_1043_803e, + &pci_ss_info_1106_0305_1043_8042, + &pci_ss_info_1106_0305_147b_a401, + NULL +}; +#define pci_ss_list_1106_0308 NULL +#define pci_ss_list_1106_0314 NULL +#define pci_ss_list_1106_0324 NULL +#define pci_ss_list_1106_0327 NULL +#define pci_ss_list_1106_0336 NULL +#define pci_ss_list_1106_0340 NULL +#define pci_ss_list_1106_0351 NULL +#define pci_ss_list_1106_0364 NULL +#define pci_ss_list_1106_0391 NULL +#define pci_ss_list_1106_0501 NULL +#define pci_ss_list_1106_0505 NULL +#define pci_ss_list_1106_0561 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0571[] = { + &pci_ss_info_1106_0571_1019_0985, + &pci_ss_info_1106_0571_1019_0a81, + &pci_ss_info_1106_0571_1043_8052, + &pci_ss_info_1106_0571_1043_808c, + &pci_ss_info_1106_0571_1043_80a1, + &pci_ss_info_1106_0571_1043_80ed, + &pci_ss_info_1106_0571_1106_0571, + &pci_ss_info_1106_0571_1179_0001, + &pci_ss_info_1106_0571_1297_f641, + &pci_ss_info_1106_0571_1458_5002, + &pci_ss_info_1106_0571_1462_7020, + &pci_ss_info_1106_0571_147b_1407, + &pci_ss_info_1106_0571_1849_0571, + NULL +}; +#define pci_ss_list_1106_0576 NULL +#define pci_ss_list_1106_0585 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0586[] = { + &pci_ss_info_1106_0586_1106_0000, + NULL +}; +#define pci_ss_list_1106_0591 NULL +#define pci_ss_list_1106_0595 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0596[] = { + &pci_ss_info_1106_0596_1106_0000, + &pci_ss_info_1106_0596_1458_0596, + NULL +}; +#define pci_ss_list_1106_0597 NULL +#define pci_ss_list_1106_0598 NULL +#define pci_ss_list_1106_0601 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0605[] = { + &pci_ss_info_1106_0605_1043_802c, + NULL +}; +#define pci_ss_list_1106_0680 NULL +static const pciSubsystemInfo *pci_ss_list_1106_0686[] = { + &pci_ss_info_1106_0686_1019_0985, + &pci_ss_info_1106_0686_1043_802c, + &pci_ss_info_1106_0686_1043_8033, + &pci_ss_info_1106_0686_1043_803e, + &pci_ss_info_1106_0686_1043_8040, + &pci_ss_info_1106_0686_1043_8042, + &pci_ss_info_1106_0686_1106_0000, + &pci_ss_info_1106_0686_1106_0686, + &pci_ss_info_1106_0686_1179_0001, + &pci_ss_info_1106_0686_147b_a702, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_0691[] = { + &pci_ss_info_1106_0691_1019_0985, + &pci_ss_info_1106_0691_1179_0001, + &pci_ss_info_1106_0691_1458_0691, + NULL +}; +#define pci_ss_list_1106_0693 NULL +#define pci_ss_list_1106_0698 NULL +#define pci_ss_list_1106_0926 NULL +#define pci_ss_list_1106_1000 NULL +#define pci_ss_list_1106_1106 NULL +#define pci_ss_list_1106_1204 NULL +#define pci_ss_list_1106_1208 NULL +#define pci_ss_list_1106_1238 NULL +#define pci_ss_list_1106_1258 NULL +#define pci_ss_list_1106_1259 NULL +#define pci_ss_list_1106_1269 NULL +#define pci_ss_list_1106_1282 NULL +#define pci_ss_list_1106_1290 NULL +#define pci_ss_list_1106_1293 NULL +#define pci_ss_list_1106_1296 NULL +#define pci_ss_list_1106_1308 NULL +#define pci_ss_list_1106_1314 NULL +#define pci_ss_list_1106_1324 NULL +#define pci_ss_list_1106_1327 NULL +#define pci_ss_list_1106_1336 NULL +#define pci_ss_list_1106_1340 NULL +#define pci_ss_list_1106_1351 NULL +#define pci_ss_list_1106_1364 NULL +#define pci_ss_list_1106_1571 NULL +#define pci_ss_list_1106_1595 NULL +#define pci_ss_list_1106_2204 NULL +#define pci_ss_list_1106_2208 NULL +#define pci_ss_list_1106_2238 NULL +#define pci_ss_list_1106_2258 NULL +#define pci_ss_list_1106_2259 NULL +#define pci_ss_list_1106_2269 NULL +#define pci_ss_list_1106_2282 NULL +#define pci_ss_list_1106_2290 NULL +#define pci_ss_list_1106_2293 NULL +#define pci_ss_list_1106_2296 NULL +#define pci_ss_list_1106_2308 NULL +#define pci_ss_list_1106_2314 NULL +#define pci_ss_list_1106_2324 NULL +#define pci_ss_list_1106_2327 NULL +#define pci_ss_list_1106_2336 NULL +#define pci_ss_list_1106_2340 NULL +#define pci_ss_list_1106_2351 NULL +#define pci_ss_list_1106_2364 NULL +#define pci_ss_list_1106_287a NULL +#define pci_ss_list_1106_287b NULL +#define pci_ss_list_1106_287c NULL +#define pci_ss_list_1106_287d NULL +#define pci_ss_list_1106_287e NULL +#define pci_ss_list_1106_3022 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3038[] = { + &pci_ss_info_1106_3038_0925_1234, + &pci_ss_info_1106_3038_1019_0985, + &pci_ss_info_1106_3038_1019_0a81, + &pci_ss_info_1106_3038_1043_8080, + &pci_ss_info_1106_3038_1043_808c, + &pci_ss_info_1106_3038_1043_80a1, + &pci_ss_info_1106_3038_1043_80ed, + &pci_ss_info_1106_3038_1179_0001, + &pci_ss_info_1106_3038_1458_5004, + &pci_ss_info_1106_3038_1462_7020, + &pci_ss_info_1106_3038_147b_1407, + &pci_ss_info_1106_3038_182d_201d, + &pci_ss_info_1106_3038_1849_3038, + NULL +}; +#define pci_ss_list_1106_3040 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3043[] = { + &pci_ss_info_1106_3043_10bd_0000, + &pci_ss_info_1106_3043_1106_0100, + &pci_ss_info_1106_3043_1186_1400, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3044[] = { + &pci_ss_info_1106_3044_1025_005a, + &pci_ss_info_1106_3044_1043_808a, + &pci_ss_info_1106_3044_1458_1000, + &pci_ss_info_1106_3044_1462_207d, + &pci_ss_info_1106_3044_1462_702d, + &pci_ss_info_1106_3044_1462_971d, + NULL +}; +#define pci_ss_list_1106_3050 NULL +#define pci_ss_list_1106_3051 NULL +#define pci_ss_list_1106_3053 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3057[] = { + &pci_ss_info_1106_3057_1019_0985, + &pci_ss_info_1106_3057_1019_0987, + &pci_ss_info_1106_3057_1043_8033, + &pci_ss_info_1106_3057_1043_803e, + &pci_ss_info_1106_3057_1043_8040, + &pci_ss_info_1106_3057_1043_8042, + &pci_ss_info_1106_3057_1179_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3058[] = { + &pci_ss_info_1106_3058_0e11_0097, + &pci_ss_info_1106_3058_0e11_b194, + &pci_ss_info_1106_3058_1019_0985, + &pci_ss_info_1106_3058_1019_0987, + &pci_ss_info_1106_3058_1043_1106, + &pci_ss_info_1106_3058_1106_4511, + &pci_ss_info_1106_3058_1458_7600, + &pci_ss_info_1106_3058_1462_3091, + &pci_ss_info_1106_3058_1462_3300, + &pci_ss_info_1106_3058_15dd_7609, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3059[] = { + &pci_ss_info_1106_3059_1019_0a81, + &pci_ss_info_1106_3059_1043_8095, + &pci_ss_info_1106_3059_1043_80a1, + &pci_ss_info_1106_3059_1043_80b0, + &pci_ss_info_1106_3059_1043_812a, + &pci_ss_info_1106_3059_1106_3059, + &pci_ss_info_1106_3059_1106_4161, + &pci_ss_info_1106_3059_1106_4170, + &pci_ss_info_1106_3059_1106_4552, + &pci_ss_info_1106_3059_1297_c160, + &pci_ss_info_1106_3059_1458_a002, + &pci_ss_info_1106_3059_1462_0080, + &pci_ss_info_1106_3059_1462_3800, + &pci_ss_info_1106_3059_147b_1407, + &pci_ss_info_1106_3059_1849_9761, + &pci_ss_info_1106_3059_4005_4710, + &pci_ss_info_1106_3059_a0a0_01b6, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3065[] = { + &pci_ss_info_1106_3065_1043_80a1, + &pci_ss_info_1106_3065_1106_0102, + &pci_ss_info_1106_3065_1186_1400, + &pci_ss_info_1106_3065_1186_1401, + &pci_ss_info_1106_3065_13b9_1421, + &pci_ss_info_1106_3065_147b_1c09, + &pci_ss_info_1106_3065_1695_3005, + &pci_ss_info_1106_3065_1695_300c, + &pci_ss_info_1106_3065_1849_3065, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3068[] = { + &pci_ss_info_1106_3068_1462_309e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3074[] = { + &pci_ss_info_1106_3074_1043_8052, + NULL +}; +#define pci_ss_list_1106_3091 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3099[] = { + &pci_ss_info_1106_3099_1043_8064, + &pci_ss_info_1106_3099_1043_807f, + &pci_ss_info_1106_3099_1849_3099, + NULL +}; +#define pci_ss_list_1106_3101 NULL +#define pci_ss_list_1106_3102 NULL +#define pci_ss_list_1106_3103 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3104[] = { + &pci_ss_info_1106_3104_1019_0a81, + &pci_ss_info_1106_3104_1043_808c, + &pci_ss_info_1106_3104_1043_80a1, + &pci_ss_info_1106_3104_1043_80ed, + &pci_ss_info_1106_3104_1297_f641, + &pci_ss_info_1106_3104_1458_5004, + &pci_ss_info_1106_3104_1462_7020, + &pci_ss_info_1106_3104_147b_1407, + &pci_ss_info_1106_3104_182d_201d, + &pci_ss_info_1106_3104_1849_3104, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3106[] = { + &pci_ss_info_1106_3106_1186_1403, + NULL +}; +#define pci_ss_list_1106_3108 NULL +#define pci_ss_list_1106_3109 NULL +#define pci_ss_list_1106_3112 NULL +#define pci_ss_list_1106_3113 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3116[] = { + &pci_ss_info_1106_3116_1297_f641, + NULL +}; +#define pci_ss_list_1106_3118 NULL +#define pci_ss_list_1106_3119 NULL +#define pci_ss_list_1106_3122 NULL +#define pci_ss_list_1106_3123 NULL +#define pci_ss_list_1106_3128 NULL +#define pci_ss_list_1106_3133 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3147[] = { + &pci_ss_info_1106_3147_1043_808c, + NULL +}; +#define pci_ss_list_1106_3148 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3149[] = { + &pci_ss_info_1106_3149_1043_80ed, + &pci_ss_info_1106_3149_1458_b003, + &pci_ss_info_1106_3149_1462_7020, + &pci_ss_info_1106_3149_147b_1407, + &pci_ss_info_1106_3149_147b_1408, + &pci_ss_info_1106_3149_1849_3149, + NULL +}; +#define pci_ss_list_1106_3156 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3164[] = { + &pci_ss_info_1106_3164_1043_80f4, + &pci_ss_info_1106_3164_1462_7028, + NULL +}; +#define pci_ss_list_1106_3168 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3177[] = { + &pci_ss_info_1106_3177_1019_0a81, + &pci_ss_info_1106_3177_1043_808c, + &pci_ss_info_1106_3177_1043_80a1, + &pci_ss_info_1106_3177_1297_f641, + &pci_ss_info_1106_3177_1458_5001, + &pci_ss_info_1106_3177_1849_3177, + NULL +}; +#define pci_ss_list_1106_3178 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3188[] = { + &pci_ss_info_1106_3188_1043_80a3, + &pci_ss_info_1106_3188_147b_1407, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1106_3189[] = { + &pci_ss_info_1106_3189_1043_807f, + &pci_ss_info_1106_3189_1458_5000, + &pci_ss_info_1106_3189_1849_3189, + NULL +}; +#define pci_ss_list_1106_3204 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3205[] = { + &pci_ss_info_1106_3205_1458_5000, + NULL +}; +#define pci_ss_list_1106_3208 NULL +#define pci_ss_list_1106_3213 NULL +#define pci_ss_list_1106_3218 NULL +static const pciSubsystemInfo *pci_ss_list_1106_3227[] = { + &pci_ss_info_1106_3227_1043_80ed, + &pci_ss_info_1106_3227_1106_3227, + &pci_ss_info_1106_3227_1458_5001, + &pci_ss_info_1106_3227_147b_1407, + &pci_ss_info_1106_3227_1849_3227, + NULL +}; +#define pci_ss_list_1106_3238 NULL +#define pci_ss_list_1106_3249 NULL +#define pci_ss_list_1106_324a NULL +#define pci_ss_list_1106_324b NULL +#define pci_ss_list_1106_324e NULL +#define pci_ss_list_1106_3258 NULL +#define pci_ss_list_1106_3259 NULL +#define pci_ss_list_1106_3269 NULL +#define pci_ss_list_1106_3282 NULL +#define pci_ss_list_1106_3287 NULL +#define pci_ss_list_1106_3288 NULL +#define pci_ss_list_1106_3290 NULL +#define pci_ss_list_1106_3296 NULL +#define pci_ss_list_1106_3324 NULL +#define pci_ss_list_1106_3327 NULL +#define pci_ss_list_1106_3336 NULL +#define pci_ss_list_1106_3337 NULL +#define pci_ss_list_1106_3340 NULL +#define pci_ss_list_1106_3344 NULL +#define pci_ss_list_1106_3349 NULL +#define pci_ss_list_1106_3351 NULL +#define pci_ss_list_1106_3364 NULL +#define pci_ss_list_1106_337a NULL +#define pci_ss_list_1106_337b NULL +#define pci_ss_list_1106_4149 NULL +#define pci_ss_list_1106_4204 NULL +#define pci_ss_list_1106_4208 NULL +#define pci_ss_list_1106_4238 NULL +#define pci_ss_list_1106_4258 NULL +#define pci_ss_list_1106_4259 NULL +#define pci_ss_list_1106_4269 NULL +#define pci_ss_list_1106_4282 NULL +#define pci_ss_list_1106_4290 NULL +#define pci_ss_list_1106_4293 NULL +#define pci_ss_list_1106_4296 NULL +#define pci_ss_list_1106_4308 NULL +#define pci_ss_list_1106_4314 NULL +#define pci_ss_list_1106_4324 NULL +#define pci_ss_list_1106_4327 NULL +#define pci_ss_list_1106_4336 NULL +#define pci_ss_list_1106_4340 NULL +#define pci_ss_list_1106_4351 NULL +#define pci_ss_list_1106_4364 NULL +#define pci_ss_list_1106_5030 NULL +#define pci_ss_list_1106_5208 NULL +#define pci_ss_list_1106_5238 NULL +#define pci_ss_list_1106_5290 NULL +#define pci_ss_list_1106_5308 NULL +#define pci_ss_list_1106_5327 NULL +#define pci_ss_list_1106_5336 NULL +#define pci_ss_list_1106_5340 NULL +#define pci_ss_list_1106_5351 NULL +#define pci_ss_list_1106_5364 NULL +#define pci_ss_list_1106_6100 NULL +#define pci_ss_list_1106_6327 NULL +#define pci_ss_list_1106_7204 NULL +static const pciSubsystemInfo *pci_ss_list_1106_7205[] = { + &pci_ss_info_1106_7205_1458_d000, + NULL +}; +#define pci_ss_list_1106_7208 NULL +#define pci_ss_list_1106_7238 NULL +#define pci_ss_list_1106_7258 NULL +#define pci_ss_list_1106_7259 NULL +#define pci_ss_list_1106_7269 NULL +#define pci_ss_list_1106_7282 NULL +#define pci_ss_list_1106_7290 NULL +#define pci_ss_list_1106_7293 NULL +#define pci_ss_list_1106_7296 NULL +#define pci_ss_list_1106_7308 NULL +#define pci_ss_list_1106_7314 NULL +#define pci_ss_list_1106_7324 NULL +#define pci_ss_list_1106_7327 NULL +#define pci_ss_list_1106_7336 NULL +#define pci_ss_list_1106_7340 NULL +#define pci_ss_list_1106_7351 NULL +#define pci_ss_list_1106_7364 NULL +#define pci_ss_list_1106_8231 NULL +#define pci_ss_list_1106_8235 NULL +#define pci_ss_list_1106_8305 NULL +#define pci_ss_list_1106_8324 NULL +#define pci_ss_list_1106_8391 NULL +#define pci_ss_list_1106_8501 NULL +#define pci_ss_list_1106_8596 NULL +#define pci_ss_list_1106_8597 NULL +static const pciSubsystemInfo *pci_ss_list_1106_8598[] = { + &pci_ss_info_1106_8598_1019_0985, + NULL +}; +#define pci_ss_list_1106_8601 NULL +#define pci_ss_list_1106_8605 NULL +#define pci_ss_list_1106_8691 NULL +#define pci_ss_list_1106_8693 NULL +#define pci_ss_list_1106_a208 NULL +#define pci_ss_list_1106_a238 NULL +#define pci_ss_list_1106_a327 NULL +#define pci_ss_list_1106_a364 NULL +#define pci_ss_list_1106_b091 NULL +#define pci_ss_list_1106_b099 NULL +#define pci_ss_list_1106_b101 NULL +#define pci_ss_list_1106_b102 NULL +#define pci_ss_list_1106_b103 NULL +#define pci_ss_list_1106_b112 NULL +#define pci_ss_list_1106_b113 NULL +#define pci_ss_list_1106_b115 NULL +#define pci_ss_list_1106_b168 NULL +static const pciSubsystemInfo *pci_ss_list_1106_b188[] = { + &pci_ss_info_1106_b188_147b_1407, + NULL +}; +#define pci_ss_list_1106_b198 NULL +#define pci_ss_list_1106_b213 NULL +#define pci_ss_list_1106_b999 NULL +#define pci_ss_list_1106_c208 NULL +#define pci_ss_list_1106_c238 NULL +#define pci_ss_list_1106_c327 NULL +#define pci_ss_list_1106_c340 NULL +#define pci_ss_list_1106_c364 NULL +#define pci_ss_list_1106_d104 NULL +#define pci_ss_list_1106_d208 NULL +#define pci_ss_list_1106_d213 NULL +#define pci_ss_list_1106_d238 NULL +#define pci_ss_list_1106_d340 NULL +#define pci_ss_list_1106_e208 NULL +#define pci_ss_list_1106_e238 NULL +#define pci_ss_list_1106_e340 NULL +#define pci_ss_list_1106_f208 NULL +#define pci_ss_list_1106_f238 NULL +#define pci_ss_list_1106_f340 NULL +#endif +#define pci_ss_list_1107_0576 NULL +#define pci_ss_list_1108_0100 NULL +#define pci_ss_list_1108_0101 NULL +#define pci_ss_list_1108_0105 NULL +#define pci_ss_list_1108_0108 NULL +#define pci_ss_list_1108_0138 NULL +#define pci_ss_list_1108_0139 NULL +#define pci_ss_list_1108_013c NULL +#define pci_ss_list_1108_013d NULL +#define pci_ss_list_1109_1400 NULL +#define pci_ss_list_110a_0002 NULL +#define pci_ss_list_110a_0005 NULL +#define pci_ss_list_110a_0006 NULL +#define pci_ss_list_110a_0015 NULL +#define pci_ss_list_110a_001d NULL +#define pci_ss_list_110a_007b NULL +#define pci_ss_list_110a_007c NULL +#define pci_ss_list_110a_007d NULL +#define pci_ss_list_110a_2101 NULL +#define pci_ss_list_110a_2102 NULL +#define pci_ss_list_110a_2104 NULL +#define pci_ss_list_110a_3142 NULL +#define pci_ss_list_110a_4021 NULL +#define pci_ss_list_110a_4029 NULL +#define pci_ss_list_110a_4942 NULL +#define pci_ss_list_110a_6120 NULL +#define pci_ss_list_110b_0001 NULL +#define pci_ss_list_110b_0004 NULL +#define pci_ss_list_1110_6037 NULL +#define pci_ss_list_1110_6073 NULL +#define pci_ss_list_1112_2200 NULL +#define pci_ss_list_1112_2300 NULL +#define pci_ss_list_1112_2340 NULL +#define pci_ss_list_1112_2400 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1113_1211[] = { + &pci_ss_info_1113_1211_103c_1207, + &pci_ss_info_1113_1211_1113_1211, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1113_1216[] = { + &pci_ss_info_1113_1216_1113_2242, + &pci_ss_info_1113_1216_111a_1020, + NULL +}; +#define pci_ss_list_1113_1217 NULL +#define pci_ss_list_1113_5105 NULL +static const pciSubsystemInfo *pci_ss_list_1113_9211[] = { + &pci_ss_info_1113_9211_1113_9211, + NULL +}; +#define pci_ss_list_1113_9511 NULL +#define pci_ss_list_1113_d301 NULL +#define pci_ss_list_1113_ec02 NULL +#endif +#define pci_ss_list_1114_0506 NULL +#define pci_ss_list_1116_0022 NULL +#define pci_ss_list_1116_0023 NULL +#define pci_ss_list_1116_0024 NULL +#define pci_ss_list_1116_0025 NULL +#define pci_ss_list_1116_0026 NULL +#define pci_ss_list_1116_0027 NULL +#define pci_ss_list_1116_0028 NULL +#define pci_ss_list_1117_9500 NULL +#define pci_ss_list_1117_9501 NULL +#define pci_ss_list_1119_0000 NULL +#define pci_ss_list_1119_0001 NULL +#define pci_ss_list_1119_0002 NULL +#define pci_ss_list_1119_0003 NULL +#define pci_ss_list_1119_0004 NULL +#define pci_ss_list_1119_0005 NULL +#define pci_ss_list_1119_0006 NULL +#define pci_ss_list_1119_0007 NULL +#define pci_ss_list_1119_0008 NULL +#define pci_ss_list_1119_0009 NULL +#define pci_ss_list_1119_000a NULL +#define pci_ss_list_1119_000b NULL +#define pci_ss_list_1119_000c NULL +#define pci_ss_list_1119_000d NULL +#define pci_ss_list_1119_0010 NULL +#define pci_ss_list_1119_0011 NULL +#define pci_ss_list_1119_0012 NULL +#define pci_ss_list_1119_0013 NULL +#define pci_ss_list_1119_0100 NULL +#define pci_ss_list_1119_0101 NULL +#define pci_ss_list_1119_0102 NULL +#define pci_ss_list_1119_0103 NULL +#define pci_ss_list_1119_0104 NULL +#define pci_ss_list_1119_0105 NULL +#define pci_ss_list_1119_0110 NULL +#define pci_ss_list_1119_0111 NULL +#define pci_ss_list_1119_0112 NULL +#define pci_ss_list_1119_0113 NULL +#define pci_ss_list_1119_0114 NULL +#define pci_ss_list_1119_0115 NULL +#define pci_ss_list_1119_0118 NULL +#define pci_ss_list_1119_0119 NULL +#define pci_ss_list_1119_011a NULL +#define pci_ss_list_1119_011b NULL +#define pci_ss_list_1119_0120 NULL +#define pci_ss_list_1119_0121 NULL +#define pci_ss_list_1119_0122 NULL +#define pci_ss_list_1119_0123 NULL +#define pci_ss_list_1119_0124 NULL +#define pci_ss_list_1119_0125 NULL +#define pci_ss_list_1119_0136 NULL +#define pci_ss_list_1119_0137 NULL +#define pci_ss_list_1119_0138 NULL +#define pci_ss_list_1119_0139 NULL +#define pci_ss_list_1119_013a NULL +#define pci_ss_list_1119_013b NULL +#define pci_ss_list_1119_013c NULL +#define pci_ss_list_1119_013d NULL +#define pci_ss_list_1119_013e NULL +#define pci_ss_list_1119_013f NULL +#define pci_ss_list_1119_0166 NULL +#define pci_ss_list_1119_0167 NULL +#define pci_ss_list_1119_0168 NULL +#define pci_ss_list_1119_0169 NULL +#define pci_ss_list_1119_016a NULL +#define pci_ss_list_1119_016b NULL +#define pci_ss_list_1119_016c NULL +#define pci_ss_list_1119_016d NULL +#define pci_ss_list_1119_016e NULL +#define pci_ss_list_1119_016f NULL +#define pci_ss_list_1119_01d6 NULL +#define pci_ss_list_1119_01d7 NULL +#define pci_ss_list_1119_01f6 NULL +#define pci_ss_list_1119_01f7 NULL +#define pci_ss_list_1119_01fc NULL +#define pci_ss_list_1119_01fd NULL +#define pci_ss_list_1119_01fe NULL +#define pci_ss_list_1119_01ff NULL +#define pci_ss_list_1119_0210 NULL +#define pci_ss_list_1119_0211 NULL +#define pci_ss_list_1119_0260 NULL +#define pci_ss_list_1119_0261 NULL +#define pci_ss_list_1119_02ff NULL +#define pci_ss_list_1119_0300 NULL +#define pci_ss_list_111a_0000 NULL +#define pci_ss_list_111a_0002 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_111a_0003[] = { + &pci_ss_info_111a_0003_111a_0000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_111a_0005[] = { + &pci_ss_info_111a_0005_111a_0001, + &pci_ss_info_111a_0005_111a_0009, + &pci_ss_info_111a_0005_111a_0101, + &pci_ss_info_111a_0005_111a_0109, + &pci_ss_info_111a_0005_111a_0809, + &pci_ss_info_111a_0005_111a_0909, + &pci_ss_info_111a_0005_111a_0a09, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_111a_0007[] = { + &pci_ss_info_111a_0007_111a_1001, + NULL +}; +#define pci_ss_list_111a_1203 NULL +#endif +#define pci_ss_list_111c_0001 NULL +#define pci_ss_list_111d_0001 NULL +#define pci_ss_list_111d_0003 NULL +#define pci_ss_list_111d_0004 NULL +#define pci_ss_list_111d_0005 NULL +#define pci_ss_list_111f_4a47 NULL +#define pci_ss_list_111f_5243 NULL +#define pci_ss_list_1124_2581 NULL +#define pci_ss_list_1127_0200 NULL +#define pci_ss_list_1127_0210 NULL +#define pci_ss_list_1127_0250 NULL +#define pci_ss_list_1127_0300 NULL +#define pci_ss_list_1127_0310 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1127_0400[] = { + &pci_ss_info_1127_0400_1127_0400, + NULL +}; +#endif +#define pci_ss_list_112f_0000 NULL +#define pci_ss_list_112f_0001 NULL +#define pci_ss_list_112f_0008 NULL +#define pci_ss_list_1131_1561 NULL +#define pci_ss_list_1131_1562 NULL +#define pci_ss_list_1131_3400 NULL +#define pci_ss_list_1131_5400 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1131_5402[] = { + &pci_ss_info_1131_5402_1244_0f00, + NULL +}; +#define pci_ss_list_1131_5405 NULL +#define pci_ss_list_1131_5406 NULL +static const pciSubsystemInfo *pci_ss_list_1131_7130[] = { + &pci_ss_info_1131_7130_102b_48d0, + &pci_ss_info_1131_7130_1048_226b, + &pci_ss_info_1131_7130_1131_2001, + &pci_ss_info_1131_7130_1131_2005, + &pci_ss_info_1131_7130_1461_050c, + &pci_ss_info_1131_7130_1461_10ff, + &pci_ss_info_1131_7130_1461_2108, + &pci_ss_info_1131_7130_1461_2115, + &pci_ss_info_1131_7130_153b_1152, + &pci_ss_info_1131_7130_185b_c100, + &pci_ss_info_1131_7130_185b_c901, + &pci_ss_info_1131_7130_5168_0138, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1131_7133[] = { + &pci_ss_info_1131_7133_0000_4091, + &pci_ss_info_1131_7133_1019_4cb5, + &pci_ss_info_1131_7133_1043_0210, + &pci_ss_info_1131_7133_1043_4843, + &pci_ss_info_1131_7133_1043_4845, + &pci_ss_info_1131_7133_1043_4862, + &pci_ss_info_1131_7133_1131_2001, + &pci_ss_info_1131_7133_1131_2018, + &pci_ss_info_1131_7133_1131_4ee9, + &pci_ss_info_1131_7133_11bd_002b, + &pci_ss_info_1131_7133_11bd_002e, + &pci_ss_info_1131_7133_12ab_0800, + &pci_ss_info_1131_7133_1421_0335, + &pci_ss_info_1131_7133_1421_1370, + &pci_ss_info_1131_7133_1435_7330, + &pci_ss_info_1131_7133_1435_7350, + &pci_ss_info_1131_7133_1461_1044, + &pci_ss_info_1131_7133_1461_f31f, + &pci_ss_info_1131_7133_1462_6231, + &pci_ss_info_1131_7133_1489_0214, + &pci_ss_info_1131_7133_14c0_1212, + &pci_ss_info_1131_7133_153b_1160, + &pci_ss_info_1131_7133_153b_1162, + &pci_ss_info_1131_7133_185b_c100, + &pci_ss_info_1131_7133_5168_0306, + &pci_ss_info_1131_7133_5168_0319, + &pci_ss_info_1131_7133_5168_0502, + &pci_ss_info_1131_7133_5168_0520, + &pci_ss_info_1131_7133_5168_1502, + &pci_ss_info_1131_7133_5168_2502, + &pci_ss_info_1131_7133_5168_2520, + &pci_ss_info_1131_7133_5168_3502, + &pci_ss_info_1131_7133_5168_3520, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1131_7134[] = { + &pci_ss_info_1131_7134_1019_4cb4, + &pci_ss_info_1131_7134_1043_0210, + &pci_ss_info_1131_7134_1043_4840, + &pci_ss_info_1131_7134_1043_4842, + &pci_ss_info_1131_7134_1131_2004, + &pci_ss_info_1131_7134_1131_4e85, + &pci_ss_info_1131_7134_1131_6752, + &pci_ss_info_1131_7134_11bd_002b, + &pci_ss_info_1131_7134_11bd_002d, + &pci_ss_info_1131_7134_1461_2c00, + &pci_ss_info_1131_7134_1461_9715, + &pci_ss_info_1131_7134_1461_a70a, + &pci_ss_info_1131_7134_1461_a70b, + &pci_ss_info_1131_7134_1461_d6ee, + &pci_ss_info_1131_7134_1471_b7e9, + &pci_ss_info_1131_7134_153b_1142, + &pci_ss_info_1131_7134_153b_1143, + &pci_ss_info_1131_7134_153b_1158, + &pci_ss_info_1131_7134_1540_9524, + &pci_ss_info_1131_7134_16be_0003, + &pci_ss_info_1131_7134_185b_c200, + &pci_ss_info_1131_7134_185b_c900, + &pci_ss_info_1131_7134_1894_a006, + &pci_ss_info_1131_7134_1894_fe01, + NULL +}; +#define pci_ss_list_1131_7145 NULL +static const pciSubsystemInfo *pci_ss_list_1131_7146[] = { + &pci_ss_info_1131_7146_110a_0000, + &pci_ss_info_1131_7146_110a_ffff, + &pci_ss_info_1131_7146_1131_4f56, + &pci_ss_info_1131_7146_1131_4f60, + &pci_ss_info_1131_7146_1131_4f61, + &pci_ss_info_1131_7146_1131_5f61, + &pci_ss_info_1131_7146_114b_2003, + &pci_ss_info_1131_7146_11bd_0006, + &pci_ss_info_1131_7146_11bd_000a, + &pci_ss_info_1131_7146_11bd_000f, + &pci_ss_info_1131_7146_13c2_0000, + &pci_ss_info_1131_7146_13c2_0001, + &pci_ss_info_1131_7146_13c2_0002, + &pci_ss_info_1131_7146_13c2_0003, + &pci_ss_info_1131_7146_13c2_0004, + &pci_ss_info_1131_7146_13c2_0006, + &pci_ss_info_1131_7146_13c2_0008, + &pci_ss_info_1131_7146_13c2_000a, + &pci_ss_info_1131_7146_13c2_1003, + &pci_ss_info_1131_7146_13c2_1004, + &pci_ss_info_1131_7146_13c2_1005, + &pci_ss_info_1131_7146_13c2_100c, + &pci_ss_info_1131_7146_13c2_100f, + &pci_ss_info_1131_7146_13c2_1011, + &pci_ss_info_1131_7146_13c2_1013, + &pci_ss_info_1131_7146_13c2_1016, + &pci_ss_info_1131_7146_13c2_1102, + &pci_ss_info_1131_7146_153b_1156, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1131_9730[] = { + &pci_ss_info_1131_9730_1131_0000, + NULL +}; +#endif +#define pci_ss_list_1133_7901 NULL +#define pci_ss_list_1133_7902 NULL +#define pci_ss_list_1133_7911 NULL +#define pci_ss_list_1133_7912 NULL +#define pci_ss_list_1133_7941 NULL +#define pci_ss_list_1133_7942 NULL +#define pci_ss_list_1133_7943 NULL +#define pci_ss_list_1133_7944 NULL +#define pci_ss_list_1133_b921 NULL +#define pci_ss_list_1133_b922 NULL +#define pci_ss_list_1133_b923 NULL +#define pci_ss_list_1133_e001 NULL +#define pci_ss_list_1133_e002 NULL +#define pci_ss_list_1133_e003 NULL +#define pci_ss_list_1133_e004 NULL +#define pci_ss_list_1133_e005 NULL +#define pci_ss_list_1133_e006 NULL +#define pci_ss_list_1133_e007 NULL +#define pci_ss_list_1133_e008 NULL +#define pci_ss_list_1133_e009 NULL +#define pci_ss_list_1133_e00a NULL +#define pci_ss_list_1133_e00b NULL +#define pci_ss_list_1133_e00c NULL +#define pci_ss_list_1133_e00d NULL +#define pci_ss_list_1133_e00e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1133_e010[] = { + &pci_ss_info_1133_e010_110a_0021, + NULL +}; +#define pci_ss_list_1133_e011 NULL +#define pci_ss_list_1133_e012 NULL +static const pciSubsystemInfo *pci_ss_list_1133_e013[] = { + &pci_ss_info_1133_e013_1133_1300, + &pci_ss_info_1133_e013_1133_e013, + NULL +}; +#define pci_ss_list_1133_e014 NULL +static const pciSubsystemInfo *pci_ss_list_1133_e015[] = { + &pci_ss_info_1133_e015_1133_e015, + NULL +}; +#define pci_ss_list_1133_e016 NULL +static const pciSubsystemInfo *pci_ss_list_1133_e017[] = { + &pci_ss_info_1133_e017_1133_e017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1133_e018[] = { + &pci_ss_info_1133_e018_1133_1800, + &pci_ss_info_1133_e018_1133_e018, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1133_e019[] = { + &pci_ss_info_1133_e019_1133_e019, + NULL +}; +#define pci_ss_list_1133_e01a NULL +static const pciSubsystemInfo *pci_ss_list_1133_e01b[] = { + &pci_ss_info_1133_e01b_1133_e01b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1133_e01c[] = { + &pci_ss_info_1133_e01c_1133_1c01, + &pci_ss_info_1133_e01c_1133_1c02, + &pci_ss_info_1133_e01c_1133_1c03, + &pci_ss_info_1133_e01c_1133_1c04, + &pci_ss_info_1133_e01c_1133_1c05, + &pci_ss_info_1133_e01c_1133_1c06, + &pci_ss_info_1133_e01c_1133_1c07, + &pci_ss_info_1133_e01c_1133_1c08, + &pci_ss_info_1133_e01c_1133_1c09, + &pci_ss_info_1133_e01c_1133_1c0a, + &pci_ss_info_1133_e01c_1133_1c0b, + &pci_ss_info_1133_e01c_1133_1c0c, + NULL +}; +#define pci_ss_list_1133_e01e NULL +#define pci_ss_list_1133_e020 NULL +#define pci_ss_list_1133_e022 NULL +static const pciSubsystemInfo *pci_ss_list_1133_e024[] = { + &pci_ss_info_1133_e024_1133_2400, + &pci_ss_info_1133_e024_1133_e024, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1133_e028[] = { + &pci_ss_info_1133_e028_1133_2800, + &pci_ss_info_1133_e028_1133_e028, + NULL +}; +#define pci_ss_list_1133_e02a NULL +#define pci_ss_list_1133_e02c NULL +#endif +#define pci_ss_list_1134_0001 NULL +#define pci_ss_list_1134_0002 NULL +#define pci_ss_list_1135_0001 NULL +#define pci_ss_list_1138_8905 NULL +#define pci_ss_list_1139_0001 NULL +#define pci_ss_list_113c_0000 NULL +#define pci_ss_list_113c_0001 NULL +#define pci_ss_list_113c_0911 NULL +#define pci_ss_list_113c_0912 NULL +#define pci_ss_list_113c_0913 NULL +#define pci_ss_list_113c_0914 NULL +#define pci_ss_list_113f_0808 NULL +#define pci_ss_list_113f_1010 NULL +#define pci_ss_list_113f_80c0 NULL +#define pci_ss_list_113f_80c4 NULL +#define pci_ss_list_113f_80c8 NULL +#define pci_ss_list_113f_8888 NULL +#define pci_ss_list_113f_9090 NULL +#define pci_ss_list_1142_3210 NULL +#define pci_ss_list_1142_6422 NULL +#define pci_ss_list_1142_6424 NULL +#define pci_ss_list_1142_6425 NULL +#define pci_ss_list_1142_643d NULL +#define pci_ss_list_1144_0001 NULL +#define pci_ss_list_1145_8007 NULL +#define pci_ss_list_1145_f007 NULL +#define pci_ss_list_1145_f010 NULL +#define pci_ss_list_1145_f012 NULL +#define pci_ss_list_1145_f013 NULL +#define pci_ss_list_1145_f015 NULL +#define pci_ss_list_1145_f020 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1148_4000[] = { + &pci_ss_info_1148_4000_0e11_b03b, + &pci_ss_info_1148_4000_0e11_b03c, + &pci_ss_info_1148_4000_0e11_b03d, + &pci_ss_info_1148_4000_0e11_b03e, + &pci_ss_info_1148_4000_0e11_b03f, + &pci_ss_info_1148_4000_1148_5521, + &pci_ss_info_1148_4000_1148_5522, + &pci_ss_info_1148_4000_1148_5541, + &pci_ss_info_1148_4000_1148_5543, + &pci_ss_info_1148_4000_1148_5544, + &pci_ss_info_1148_4000_1148_5821, + &pci_ss_info_1148_4000_1148_5822, + &pci_ss_info_1148_4000_1148_5841, + &pci_ss_info_1148_4000_1148_5843, + &pci_ss_info_1148_4000_1148_5844, + NULL +}; +#define pci_ss_list_1148_4200 NULL +static const pciSubsystemInfo *pci_ss_list_1148_4300[] = { + &pci_ss_info_1148_4300_1148_9821, + &pci_ss_info_1148_4300_1148_9822, + &pci_ss_info_1148_4300_1148_9841, + &pci_ss_info_1148_4300_1148_9842, + &pci_ss_info_1148_4300_1148_9843, + &pci_ss_info_1148_4300_1148_9844, + &pci_ss_info_1148_4300_1148_9861, + &pci_ss_info_1148_4300_1148_9862, + &pci_ss_info_1148_4300_1148_9871, + &pci_ss_info_1148_4300_1148_9872, + &pci_ss_info_1148_4300_1259_2970, + &pci_ss_info_1148_4300_1259_2971, + &pci_ss_info_1148_4300_1259_2972, + &pci_ss_info_1148_4300_1259_2973, + &pci_ss_info_1148_4300_1259_2974, + &pci_ss_info_1148_4300_1259_2975, + &pci_ss_info_1148_4300_1259_2976, + &pci_ss_info_1148_4300_1259_2977, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1148_4320[] = { + &pci_ss_info_1148_4320_1148_0121, + &pci_ss_info_1148_4320_1148_0221, + &pci_ss_info_1148_4320_1148_0321, + &pci_ss_info_1148_4320_1148_0421, + &pci_ss_info_1148_4320_1148_0621, + &pci_ss_info_1148_4320_1148_0721, + &pci_ss_info_1148_4320_1148_0821, + &pci_ss_info_1148_4320_1148_0921, + &pci_ss_info_1148_4320_1148_1121, + &pci_ss_info_1148_4320_1148_1221, + &pci_ss_info_1148_4320_1148_3221, + &pci_ss_info_1148_4320_1148_5021, + &pci_ss_info_1148_4320_1148_5041, + &pci_ss_info_1148_4320_1148_5043, + &pci_ss_info_1148_4320_1148_5051, + &pci_ss_info_1148_4320_1148_5061, + &pci_ss_info_1148_4320_1148_5071, + &pci_ss_info_1148_4320_1148_9521, + NULL +}; +#define pci_ss_list_1148_4400 NULL +#define pci_ss_list_1148_4500 NULL +#define pci_ss_list_1148_9000 NULL +#define pci_ss_list_1148_9843 NULL +static const pciSubsystemInfo *pci_ss_list_1148_9e00[] = { + &pci_ss_info_1148_9e00_1148_2100, + &pci_ss_info_1148_9e00_1148_21d0, + &pci_ss_info_1148_9e00_1148_2200, + &pci_ss_info_1148_9e00_1148_8100, + &pci_ss_info_1148_9e00_1148_8200, + &pci_ss_info_1148_9e00_1148_9100, + &pci_ss_info_1148_9e00_1148_9200, + NULL +}; +#endif +#define pci_ss_list_114a_5579 NULL +#define pci_ss_list_114a_5587 NULL +#define pci_ss_list_114a_6504 NULL +#define pci_ss_list_114a_7587 NULL +#define pci_ss_list_114f_0002 NULL +#define pci_ss_list_114f_0003 NULL +#define pci_ss_list_114f_0004 NULL +#define pci_ss_list_114f_0005 NULL +#define pci_ss_list_114f_0006 NULL +#define pci_ss_list_114f_0009 NULL +#define pci_ss_list_114f_000a NULL +#define pci_ss_list_114f_000c NULL +#define pci_ss_list_114f_000d NULL +#define pci_ss_list_114f_0011 NULL +#define pci_ss_list_114f_0012 NULL +#define pci_ss_list_114f_0014 NULL +#define pci_ss_list_114f_0015 NULL +#define pci_ss_list_114f_0016 NULL +#define pci_ss_list_114f_0017 NULL +#define pci_ss_list_114f_001a NULL +#define pci_ss_list_114f_001b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_114f_001d[] = { + &pci_ss_info_114f_001d_114f_0050, + &pci_ss_info_114f_001d_114f_0051, + &pci_ss_info_114f_001d_114f_0052, + &pci_ss_info_114f_001d_114f_0053, + NULL +}; +#define pci_ss_list_114f_0023 NULL +static const pciSubsystemInfo *pci_ss_list_114f_0024[] = { + &pci_ss_info_114f_0024_114f_0030, + &pci_ss_info_114f_0024_114f_0031, + NULL +}; +#define pci_ss_list_114f_0026 NULL +#define pci_ss_list_114f_0027 NULL +#define pci_ss_list_114f_0028 NULL +#define pci_ss_list_114f_0029 NULL +#define pci_ss_list_114f_0034 NULL +#define pci_ss_list_114f_0035 NULL +#define pci_ss_list_114f_0040 NULL +#define pci_ss_list_114f_0042 NULL +#define pci_ss_list_114f_0043 NULL +#define pci_ss_list_114f_0044 NULL +#define pci_ss_list_114f_0045 NULL +#define pci_ss_list_114f_004e NULL +#define pci_ss_list_114f_0070 NULL +#define pci_ss_list_114f_0071 NULL +#define pci_ss_list_114f_0072 NULL +#define pci_ss_list_114f_0073 NULL +#define pci_ss_list_114f_00b0 NULL +#define pci_ss_list_114f_00b1 NULL +#define pci_ss_list_114f_00c8 NULL +#define pci_ss_list_114f_00c9 NULL +#define pci_ss_list_114f_00ca NULL +#define pci_ss_list_114f_00cb NULL +#define pci_ss_list_114f_00d0 NULL +#define pci_ss_list_114f_00d1 NULL +#define pci_ss_list_114f_6001 NULL +#endif +#define pci_ss_list_1158_3011 NULL +#define pci_ss_list_1158_9050 NULL +#define pci_ss_list_1158_9051 NULL +#define pci_ss_list_1159_0001 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_115d_0003[] = { + &pci_ss_info_115d_0003_1014_0181, + &pci_ss_info_115d_0003_1014_1181, + &pci_ss_info_115d_0003_1014_8181, + &pci_ss_info_115d_0003_1014_9181, + &pci_ss_info_115d_0003_115d_0181, + &pci_ss_info_115d_0003_115d_0182, + &pci_ss_info_115d_0003_115d_1181, + &pci_ss_info_115d_0003_1179_0181, + &pci_ss_info_115d_0003_8086_8181, + &pci_ss_info_115d_0003_8086_9181, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_115d_0005[] = { + &pci_ss_info_115d_0005_1014_0182, + &pci_ss_info_115d_0005_1014_1182, + &pci_ss_info_115d_0005_115d_0182, + &pci_ss_info_115d_0005_115d_1182, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_115d_0007[] = { + &pci_ss_info_115d_0007_1014_0182, + &pci_ss_info_115d_0007_1014_1182, + &pci_ss_info_115d_0007_115d_0182, + &pci_ss_info_115d_0007_115d_1182, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_115d_000b[] = { + &pci_ss_info_115d_000b_1014_0183, + &pci_ss_info_115d_000b_115d_0183, + NULL +}; +#define pci_ss_list_115d_000c NULL +static const pciSubsystemInfo *pci_ss_list_115d_000f[] = { + &pci_ss_info_115d_000f_1014_0183, + &pci_ss_info_115d_000f_115d_0183, + NULL +}; +#define pci_ss_list_115d_00d4 NULL +static const pciSubsystemInfo *pci_ss_list_115d_0101[] = { + &pci_ss_info_115d_0101_115d_1081, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_115d_0103[] = { + &pci_ss_info_115d_0103_1014_9181, + &pci_ss_info_115d_0103_1115_1181, + &pci_ss_info_115d_0103_115d_1181, + &pci_ss_info_115d_0103_8086_9181, + NULL +}; +#endif +#define pci_ss_list_1163_0001 NULL +static const pciSubsystemInfo *pci_ss_list_1163_2000[] = { + &pci_ss_info_1163_2000_1092_2000, + NULL +}; +#define pci_ss_list_1165_0001 NULL +#define pci_ss_list_1166_0000 NULL +#define pci_ss_list_1166_0005 NULL +#define pci_ss_list_1166_0006 NULL +#define pci_ss_list_1166_0007 NULL +#define pci_ss_list_1166_0008 NULL +#define pci_ss_list_1166_0009 NULL +#define pci_ss_list_1166_0010 NULL +#define pci_ss_list_1166_0011 NULL +#define pci_ss_list_1166_0012 NULL +#define pci_ss_list_1166_0013 NULL +#define pci_ss_list_1166_0014 NULL +#define pci_ss_list_1166_0015 NULL +#define pci_ss_list_1166_0016 NULL +#define pci_ss_list_1166_0017 NULL +#define pci_ss_list_1166_0036 NULL +#define pci_ss_list_1166_0101 NULL +#define pci_ss_list_1166_0103 NULL +#define pci_ss_list_1166_0104 NULL +#define pci_ss_list_1166_0110 NULL +#define pci_ss_list_1166_0130 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1166_0132[] = { + &pci_ss_info_1166_0132_1166_0132, + NULL +}; +#define pci_ss_list_1166_0140 NULL +#define pci_ss_list_1166_0141 NULL +#define pci_ss_list_1166_0142 NULL +#define pci_ss_list_1166_0200 NULL +static const pciSubsystemInfo *pci_ss_list_1166_0201[] = { + &pci_ss_info_1166_0201_4c53_1080, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1166_0203[] = { + &pci_ss_info_1166_0203_1734_1012, + NULL +}; +#define pci_ss_list_1166_0205 NULL +#define pci_ss_list_1166_0211 NULL +static const pciSubsystemInfo *pci_ss_list_1166_0212[] = { + &pci_ss_info_1166_0212_4c53_1080, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1166_0213[] = { + &pci_ss_info_1166_0213_1028_4134, + &pci_ss_info_1166_0213_1028_c134, + &pci_ss_info_1166_0213_1734_1012, + NULL +}; +#define pci_ss_list_1166_0214 NULL +static const pciSubsystemInfo *pci_ss_list_1166_0217[] = { + &pci_ss_info_1166_0217_1028_4134, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1166_0220[] = { + &pci_ss_info_1166_0220_4c53_1080, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1166_0221[] = { + &pci_ss_info_1166_0221_1734_1012, + NULL +}; +#define pci_ss_list_1166_0223 NULL +#define pci_ss_list_1166_0225 NULL +static const pciSubsystemInfo *pci_ss_list_1166_0227[] = { + &pci_ss_info_1166_0227_1734_1012, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1166_0230[] = { + &pci_ss_info_1166_0230_4c53_1080, + NULL +}; +#define pci_ss_list_1166_0234 NULL +#define pci_ss_list_1166_0240 NULL +#define pci_ss_list_1166_0241 NULL +#define pci_ss_list_1166_0242 NULL +#define pci_ss_list_1166_024a NULL +#define pci_ss_list_1166_024b NULL +#endif +#define pci_ss_list_116a_6100 NULL +#define pci_ss_list_116a_6800 NULL +#define pci_ss_list_116a_7100 NULL +#define pci_ss_list_116a_7800 NULL +#define pci_ss_list_1178_afa1 NULL +#define pci_ss_list_1179_0102 NULL +#define pci_ss_list_1179_0103 NULL +#define pci_ss_list_1179_0404 NULL +#define pci_ss_list_1179_0406 NULL +#define pci_ss_list_1179_0407 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1179_0601[] = { + &pci_ss_info_1179_0601_1179_0001, + NULL +}; +#define pci_ss_list_1179_0603 NULL +static const pciSubsystemInfo *pci_ss_list_1179_060a[] = { + &pci_ss_info_1179_060a_1179_0001, + NULL +}; +#define pci_ss_list_1179_060f NULL +#define pci_ss_list_1179_0617 NULL +#define pci_ss_list_1179_0618 NULL +#define pci_ss_list_1179_0701 NULL +#define pci_ss_list_1179_0804 NULL +#define pci_ss_list_1179_0805 NULL +static const pciSubsystemInfo *pci_ss_list_1179_0d01[] = { + &pci_ss_info_1179_0d01_1179_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_117c_0030[] = { + &pci_ss_info_117c_0030_117c_8013, + &pci_ss_info_117c_0030_117c_8014, + NULL +}; +#endif +#define pci_ss_list_1180_0465 NULL +#define pci_ss_list_1180_0466 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1180_0475[] = { + &pci_ss_info_1180_0475_144d_c006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1180_0476[] = { + &pci_ss_info_1180_0476_1014_0185, + &pci_ss_info_1180_0476_1028_0188, + &pci_ss_info_1180_0476_1043_1967, + &pci_ss_info_1180_0476_1043_1987, + &pci_ss_info_1180_0476_104d_80df, + &pci_ss_info_1180_0476_104d_80e7, + &pci_ss_info_1180_0476_144d_c00c, + &pci_ss_info_1180_0476_14ef_0220, + &pci_ss_info_1180_0476_17aa_201c, + NULL +}; +#define pci_ss_list_1180_0477 NULL +static const pciSubsystemInfo *pci_ss_list_1180_0478[] = { + &pci_ss_info_1180_0478_1014_0184, + NULL +}; +#define pci_ss_list_1180_0511 NULL +static const pciSubsystemInfo *pci_ss_list_1180_0522[] = { + &pci_ss_info_1180_0522_1014_01cf, + &pci_ss_info_1180_0522_1043_1967, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1180_0551[] = { + &pci_ss_info_1180_0551_144d_c006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1180_0552[] = { + &pci_ss_info_1180_0552_1014_0511, + &pci_ss_info_1180_0552_1028_0188, + &pci_ss_info_1180_0552_144d_c00c, + &pci_ss_info_1180_0552_17aa_201e, + NULL +}; +#define pci_ss_list_1180_0554 NULL +#define pci_ss_list_1180_0575 NULL +#define pci_ss_list_1180_0576 NULL +static const pciSubsystemInfo *pci_ss_list_1180_0592[] = { + &pci_ss_info_1180_0592_1043_1967, + &pci_ss_info_1180_0592_144d_c018, + NULL +}; +#define pci_ss_list_1180_0811 NULL +static const pciSubsystemInfo *pci_ss_list_1180_0822[] = { + &pci_ss_info_1180_0822_1014_0556, + &pci_ss_info_1180_0822_1014_0598, + &pci_ss_info_1180_0822_1028_0188, + &pci_ss_info_1180_0822_1028_01a2, + &pci_ss_info_1180_0822_1043_1967, + &pci_ss_info_1180_0822_144d_c018, + &pci_ss_info_1180_0822_17aa_201d, + NULL +}; +#define pci_ss_list_1180_0841 NULL +static const pciSubsystemInfo *pci_ss_list_1180_0852[] = { + &pci_ss_info_1180_0852_1043_1967, + NULL +}; +#endif +#define pci_ss_list_1186_0100 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1186_1002[] = { + &pci_ss_info_1186_1002_1186_1002, + &pci_ss_info_1186_1002_1186_1012, + NULL +}; +#define pci_ss_list_1186_1025 NULL +#define pci_ss_list_1186_1026 NULL +#define pci_ss_list_1186_1043 NULL +static const pciSubsystemInfo *pci_ss_list_1186_1300[] = { + &pci_ss_info_1186_1300_1186_1300, + &pci_ss_info_1186_1300_1186_1301, + &pci_ss_info_1186_1300_1186_1303, + NULL +}; +#define pci_ss_list_1186_1340 NULL +#define pci_ss_list_1186_1405 NULL +#define pci_ss_list_1186_1541 NULL +#define pci_ss_list_1186_1561 NULL +#define pci_ss_list_1186_2027 NULL +#define pci_ss_list_1186_3203 NULL +#define pci_ss_list_1186_3300 NULL +#define pci_ss_list_1186_3a03 NULL +#define pci_ss_list_1186_3a04 NULL +#define pci_ss_list_1186_3a05 NULL +#define pci_ss_list_1186_3a07 NULL +#define pci_ss_list_1186_3a08 NULL +#define pci_ss_list_1186_3a10 NULL +#define pci_ss_list_1186_3a11 NULL +#define pci_ss_list_1186_3a12 NULL +#define pci_ss_list_1186_3a13 NULL +#define pci_ss_list_1186_3a14 NULL +#define pci_ss_list_1186_3a63 NULL +#define pci_ss_list_1186_4000 NULL +#define pci_ss_list_1186_4300 NULL +#define pci_ss_list_1186_4800 NULL +#define pci_ss_list_1186_4b01 NULL +static const pciSubsystemInfo *pci_ss_list_1186_4c00[] = { + &pci_ss_info_1186_4c00_1186_4c00, + NULL +}; +#define pci_ss_list_1186_8400 NULL +#endif +#define pci_ss_list_118c_0014 NULL +#define pci_ss_list_118c_1117 NULL +#define pci_ss_list_118d_0001 NULL +#define pci_ss_list_118d_0012 NULL +#define pci_ss_list_118d_0014 NULL +#define pci_ss_list_118d_0024 NULL +#define pci_ss_list_118d_0044 NULL +#define pci_ss_list_118d_0112 NULL +#define pci_ss_list_118d_0114 NULL +#define pci_ss_list_118d_0124 NULL +#define pci_ss_list_118d_0144 NULL +#define pci_ss_list_118d_0212 NULL +#define pci_ss_list_118d_0214 NULL +#define pci_ss_list_118d_0224 NULL +#define pci_ss_list_118d_0244 NULL +#define pci_ss_list_118d_0312 NULL +#define pci_ss_list_118d_0314 NULL +#define pci_ss_list_118d_0324 NULL +#define pci_ss_list_118d_0344 NULL +#define pci_ss_list_1190_c731 NULL +#define pci_ss_list_1191_0003 NULL +#define pci_ss_list_1191_0004 NULL +#define pci_ss_list_1191_0005 NULL +#define pci_ss_list_1191_0006 NULL +#define pci_ss_list_1191_0007 NULL +#define pci_ss_list_1191_0008 NULL +#define pci_ss_list_1191_0009 NULL +#define pci_ss_list_1191_8002 NULL +#define pci_ss_list_1191_8010 NULL +#define pci_ss_list_1191_8020 NULL +#define pci_ss_list_1191_8030 NULL +#define pci_ss_list_1191_8040 NULL +#define pci_ss_list_1191_8050 NULL +#define pci_ss_list_1191_8060 NULL +#define pci_ss_list_1191_8080 NULL +#define pci_ss_list_1191_8081 NULL +#define pci_ss_list_1191_808a NULL +#define pci_ss_list_1193_0001 NULL +#define pci_ss_list_1193_0002 NULL +#define pci_ss_list_1197_010c NULL +#define pci_ss_list_119b_1221 NULL +#define pci_ss_list_119e_0001 NULL +#define pci_ss_list_119e_0003 NULL +#define pci_ss_list_11a9_4240 NULL +#define pci_ss_list_11ab_0146 NULL +#define pci_ss_list_11ab_138f NULL +#define pci_ss_list_11ab_1fa6 NULL +#define pci_ss_list_11ab_1fa7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11ab_1faa[] = { + &pci_ss_info_11ab_1faa_1385_4e00, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11ab_4320[] = { + &pci_ss_info_11ab_4320_1019_0f38, + &pci_ss_info_11ab_4320_1019_8001, + &pci_ss_info_11ab_4320_1043_173c, + &pci_ss_info_11ab_4320_1043_811a, + &pci_ss_info_11ab_4320_105b_0c19, + &pci_ss_info_11ab_4320_10b8_b452, + &pci_ss_info_11ab_4320_11ab_0121, + &pci_ss_info_11ab_4320_11ab_0321, + &pci_ss_info_11ab_4320_11ab_1021, + &pci_ss_info_11ab_4320_11ab_4320, + &pci_ss_info_11ab_4320_11ab_5021, + &pci_ss_info_11ab_4320_11ab_9521, + &pci_ss_info_11ab_4320_1458_e000, + &pci_ss_info_11ab_4320_147b_1406, + &pci_ss_info_11ab_4320_15d4_0047, + &pci_ss_info_11ab_4320_1695_9025, + &pci_ss_info_11ab_4320_17f2_1c03, + &pci_ss_info_11ab_4320_270f_2803, + NULL +}; +#define pci_ss_list_11ab_4340 NULL +#define pci_ss_list_11ab_4341 NULL +#define pci_ss_list_11ab_4342 NULL +#define pci_ss_list_11ab_4343 NULL +#define pci_ss_list_11ab_4344 NULL +#define pci_ss_list_11ab_4345 NULL +#define pci_ss_list_11ab_4346 NULL +#define pci_ss_list_11ab_4347 NULL +static const pciSubsystemInfo *pci_ss_list_11ab_4350[] = { + &pci_ss_info_11ab_4350_1179_0001, + &pci_ss_info_11ab_4350_11ab_3521, + &pci_ss_info_11ab_4350_1854_000d, + &pci_ss_info_11ab_4350_1854_000e, + &pci_ss_info_11ab_4350_1854_000f, + &pci_ss_info_11ab_4350_1854_0011, + &pci_ss_info_11ab_4350_1854_0012, + &pci_ss_info_11ab_4350_1854_0016, + &pci_ss_info_11ab_4350_1854_0017, + &pci_ss_info_11ab_4350_1854_0018, + &pci_ss_info_11ab_4350_1854_0019, + &pci_ss_info_11ab_4350_1854_001c, + &pci_ss_info_11ab_4350_1854_001e, + &pci_ss_info_11ab_4350_1854_0020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11ab_4351[] = { + &pci_ss_info_11ab_4351_107b_4009, + &pci_ss_info_11ab_4351_10f7_8338, + &pci_ss_info_11ab_4351_1179_0001, + &pci_ss_info_11ab_4351_1179_ff00, + &pci_ss_info_11ab_4351_1179_ff10, + &pci_ss_info_11ab_4351_11ab_3621, + &pci_ss_info_11ab_4351_13d1_ac12, + &pci_ss_info_11ab_4351_161f_203d, + &pci_ss_info_11ab_4351_1854_000d, + &pci_ss_info_11ab_4351_1854_000e, + &pci_ss_info_11ab_4351_1854_000f, + &pci_ss_info_11ab_4351_1854_0011, + &pci_ss_info_11ab_4351_1854_0012, + &pci_ss_info_11ab_4351_1854_0016, + &pci_ss_info_11ab_4351_1854_0017, + &pci_ss_info_11ab_4351_1854_0018, + &pci_ss_info_11ab_4351_1854_0019, + &pci_ss_info_11ab_4351_1854_001c, + &pci_ss_info_11ab_4351_1854_001e, + &pci_ss_info_11ab_4351_1854_0020, + NULL +}; +#define pci_ss_list_11ab_4352 NULL +static const pciSubsystemInfo *pci_ss_list_11ab_4360[] = { + &pci_ss_info_11ab_4360_1043_8134, + &pci_ss_info_11ab_4360_107b_4009, + &pci_ss_info_11ab_4360_11ab_5221, + &pci_ss_info_11ab_4360_1458_e000, + &pci_ss_info_11ab_4360_1462_052c, + &pci_ss_info_11ab_4360_1849_8052, + &pci_ss_info_11ab_4360_a0a0_0509, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11ab_4361[] = { + &pci_ss_info_11ab_4361_107b_3015, + &pci_ss_info_11ab_4361_11ab_5021, + &pci_ss_info_11ab_4361_8086_3063, + &pci_ss_info_11ab_4361_8086_3439, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11ab_4362[] = { + &pci_ss_info_11ab_4362_103c_2a0d, + &pci_ss_info_11ab_4362_1043_8142, + &pci_ss_info_11ab_4362_109f_3197, + &pci_ss_info_11ab_4362_10f7_8338, + &pci_ss_info_11ab_4362_10fd_a430, + &pci_ss_info_11ab_4362_1179_0001, + &pci_ss_info_11ab_4362_1179_ff00, + &pci_ss_info_11ab_4362_1179_ff10, + &pci_ss_info_11ab_4362_11ab_5321, + &pci_ss_info_11ab_4362_1297_c240, + &pci_ss_info_11ab_4362_1297_c241, + &pci_ss_info_11ab_4362_1297_c242, + &pci_ss_info_11ab_4362_1297_c243, + &pci_ss_info_11ab_4362_1297_c244, + &pci_ss_info_11ab_4362_13d1_ac11, + &pci_ss_info_11ab_4362_1458_e000, + &pci_ss_info_11ab_4362_1462_058c, + &pci_ss_info_11ab_4362_14c0_0012, + &pci_ss_info_11ab_4362_1558_04a0, + &pci_ss_info_11ab_4362_15bd_1003, + &pci_ss_info_11ab_4362_161f_203c, + &pci_ss_info_11ab_4362_161f_203d, + &pci_ss_info_11ab_4362_1695_9029, + &pci_ss_info_11ab_4362_17f2_2c08, + &pci_ss_info_11ab_4362_17ff_0585, + &pci_ss_info_11ab_4362_1849_8053, + &pci_ss_info_11ab_4362_1854_000b, + &pci_ss_info_11ab_4362_1854_000c, + &pci_ss_info_11ab_4362_1854_0010, + &pci_ss_info_11ab_4362_1854_0013, + &pci_ss_info_11ab_4362_1854_0014, + &pci_ss_info_11ab_4362_1854_0015, + &pci_ss_info_11ab_4362_1854_001a, + &pci_ss_info_11ab_4362_1854_001b, + &pci_ss_info_11ab_4362_1854_001d, + &pci_ss_info_11ab_4362_1854_001f, + &pci_ss_info_11ab_4362_1854_0021, + &pci_ss_info_11ab_4362_1854_0022, + &pci_ss_info_11ab_4362_270f_2801, + &pci_ss_info_11ab_4362_a0a0_0506, + NULL +}; +#define pci_ss_list_11ab_4363 NULL +#define pci_ss_list_11ab_4611 NULL +#define pci_ss_list_11ab_4620 NULL +#define pci_ss_list_11ab_4801 NULL +#define pci_ss_list_11ab_5005 NULL +#define pci_ss_list_11ab_5040 NULL +#define pci_ss_list_11ab_5041 NULL +#define pci_ss_list_11ab_5080 NULL +#define pci_ss_list_11ab_5081 NULL +#define pci_ss_list_11ab_6041 NULL +#define pci_ss_list_11ab_6081 NULL +#define pci_ss_list_11ab_6460 NULL +#define pci_ss_list_11ab_6480 NULL +#define pci_ss_list_11ab_6485 NULL +#define pci_ss_list_11ab_f003 NULL +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11ad_0002[] = { + &pci_ss_info_11ad_0002_11ad_0002, + &pci_ss_info_11ad_0002_11ad_0003, + &pci_ss_info_11ad_0002_11ad_f003, + &pci_ss_info_11ad_0002_11ad_ffff, + &pci_ss_info_11ad_0002_1385_f004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11ad_c115[] = { + &pci_ss_info_11ad_c115_11ad_c001, + NULL +}; +#endif +#define pci_ss_list_11af_0001 NULL +#define pci_ss_list_11af_ee40 NULL +#define pci_ss_list_11b0_0002 NULL +#define pci_ss_list_11b0_0292 NULL +#define pci_ss_list_11b0_0960 NULL +#define pci_ss_list_11b0_c960 NULL +#define pci_ss_list_11b8_0001 NULL +#define pci_ss_list_11b9_c0ed NULL +#define pci_ss_list_11bc_0001 NULL +#define pci_ss_list_11bd_002e NULL +#define pci_ss_list_11bd_bede NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11c1_0440[] = { + &pci_ss_info_11c1_0440_1033_8015, + &pci_ss_info_11c1_0440_1033_8047, + &pci_ss_info_11c1_0440_1033_804f, + &pci_ss_info_11c1_0440_10cf_102c, + &pci_ss_info_11c1_0440_10cf_104a, + &pci_ss_info_11c1_0440_10cf_105f, + &pci_ss_info_11c1_0440_1179_0001, + &pci_ss_info_11c1_0440_11c1_0440, + &pci_ss_info_11c1_0440_122d_4101, + &pci_ss_info_11c1_0440_122d_4102, + &pci_ss_info_11c1_0440_13e0_0040, + &pci_ss_info_11c1_0440_13e0_0440, + &pci_ss_info_11c1_0440_13e0_0441, + &pci_ss_info_11c1_0440_13e0_0450, + &pci_ss_info_11c1_0440_13e0_f100, + &pci_ss_info_11c1_0440_13e0_f101, + &pci_ss_info_11c1_0440_144d_2101, + &pci_ss_info_11c1_0440_149f_0440, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11c1_0441[] = { + &pci_ss_info_11c1_0441_1033_804d, + &pci_ss_info_11c1_0441_1033_8065, + &pci_ss_info_11c1_0441_1092_0440, + &pci_ss_info_11c1_0441_1179_0001, + &pci_ss_info_11c1_0441_11c1_0440, + &pci_ss_info_11c1_0441_11c1_0441, + &pci_ss_info_11c1_0441_122d_4100, + &pci_ss_info_11c1_0441_13e0_0040, + &pci_ss_info_11c1_0441_13e0_0100, + &pci_ss_info_11c1_0441_13e0_0410, + &pci_ss_info_11c1_0441_13e0_0420, + &pci_ss_info_11c1_0441_13e0_0440, + &pci_ss_info_11c1_0441_13e0_0443, + &pci_ss_info_11c1_0441_13e0_f102, + &pci_ss_info_11c1_0441_1416_9804, + &pci_ss_info_11c1_0441_141d_0440, + &pci_ss_info_11c1_0441_144f_0441, + &pci_ss_info_11c1_0441_144f_0449, + &pci_ss_info_11c1_0441_144f_110d, + &pci_ss_info_11c1_0441_1468_0441, + &pci_ss_info_11c1_0441_1668_0440, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11c1_0442[] = { + &pci_ss_info_11c1_0442_11c1_0440, + &pci_ss_info_11c1_0442_11c1_0442, + &pci_ss_info_11c1_0442_13e0_0412, + &pci_ss_info_11c1_0442_13e0_0442, + &pci_ss_info_11c1_0442_13fc_2471, + &pci_ss_info_11c1_0442_144d_2104, + &pci_ss_info_11c1_0442_144f_1104, + &pci_ss_info_11c1_0442_149f_0440, + &pci_ss_info_11c1_0442_1668_0440, + NULL +}; +#define pci_ss_list_11c1_0443 NULL +#define pci_ss_list_11c1_0444 NULL +static const pciSubsystemInfo *pci_ss_list_11c1_0445[] = { + &pci_ss_info_11c1_0445_8086_2203, + &pci_ss_info_11c1_0445_8086_2204, + NULL +}; +#define pci_ss_list_11c1_0446 NULL +#define pci_ss_list_11c1_0447 NULL +static const pciSubsystemInfo *pci_ss_list_11c1_0448[] = { + &pci_ss_info_11c1_0448_1014_0131, + &pci_ss_info_11c1_0448_1033_8066, + &pci_ss_info_11c1_0448_13e0_0030, + &pci_ss_info_11c1_0448_13e0_0040, + &pci_ss_info_11c1_0448_1668_2400, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11c1_0449[] = { + &pci_ss_info_11c1_0449_0e11_b14d, + &pci_ss_info_11c1_0449_13e0_0020, + &pci_ss_info_11c1_0449_13e0_0041, + &pci_ss_info_11c1_0449_1436_0440, + &pci_ss_info_11c1_0449_144f_0449, + &pci_ss_info_11c1_0449_1468_0410, + &pci_ss_info_11c1_0449_1468_0440, + &pci_ss_info_11c1_0449_1468_0449, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11c1_044a[] = { + &pci_ss_info_11c1_044a_10cf_1072, + &pci_ss_info_11c1_044a_13e0_0012, + &pci_ss_info_11c1_044a_13e0_0042, + &pci_ss_info_11c1_044a_144f_1005, + NULL +}; +#define pci_ss_list_11c1_044b NULL +#define pci_ss_list_11c1_044c NULL +#define pci_ss_list_11c1_044d NULL +#define pci_ss_list_11c1_044e NULL +#define pci_ss_list_11c1_044f NULL +static const pciSubsystemInfo *pci_ss_list_11c1_0450[] = { + &pci_ss_info_11c1_0450_1033_80a8, + &pci_ss_info_11c1_0450_144f_4005, + &pci_ss_info_11c1_0450_1468_0450, + &pci_ss_info_11c1_0450_4005_144f, + NULL +}; +#define pci_ss_list_11c1_0451 NULL +#define pci_ss_list_11c1_0452 NULL +#define pci_ss_list_11c1_0453 NULL +#define pci_ss_list_11c1_0454 NULL +#define pci_ss_list_11c1_0455 NULL +#define pci_ss_list_11c1_0456 NULL +#define pci_ss_list_11c1_0457 NULL +#define pci_ss_list_11c1_0458 NULL +#define pci_ss_list_11c1_0459 NULL +#define pci_ss_list_11c1_045a NULL +#define pci_ss_list_11c1_045c NULL +#define pci_ss_list_11c1_0461 NULL +#define pci_ss_list_11c1_0462 NULL +#define pci_ss_list_11c1_0480 NULL +#define pci_ss_list_11c1_048c NULL +#define pci_ss_list_11c1_048f NULL +#define pci_ss_list_11c1_5801 NULL +#define pci_ss_list_11c1_5802 NULL +#define pci_ss_list_11c1_5803 NULL +static const pciSubsystemInfo *pci_ss_list_11c1_5811[] = { + &pci_ss_info_11c1_5811_8086_524c, + &pci_ss_info_11c1_5811_dead_0800, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11c1_8110[] = { + &pci_ss_info_11c1_8110_12d9_000c, + NULL +}; +#define pci_ss_list_11c1_ab10 NULL +static const pciSubsystemInfo *pci_ss_list_11c1_ab11[] = { + &pci_ss_info_11c1_ab11_11c1_ab12, + &pci_ss_info_11c1_ab11_11c1_ab13, + &pci_ss_info_11c1_ab11_11c1_ab15, + &pci_ss_info_11c1_ab11_11c1_ab16, + NULL +}; +#define pci_ss_list_11c1_ab20 NULL +#define pci_ss_list_11c1_ab21 NULL +static const pciSubsystemInfo *pci_ss_list_11c1_ab30[] = { + &pci_ss_info_11c1_ab30_14cd_2012, + NULL +}; +#define pci_ss_list_11c1_ed00 NULL +#define pci_ss_list_11c1_ed01 NULL +#endif +#define pci_ss_list_11c8_0658 NULL +#define pci_ss_list_11c8_d665 NULL +#define pci_ss_list_11c8_d667 NULL +#define pci_ss_list_11c9_0010 NULL +#define pci_ss_list_11c9_0011 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11cb_2000[] = { + &pci_ss_info_11cb_2000_11cb_0200, + &pci_ss_info_11cb_2000_11cb_b008, + NULL +}; +#define pci_ss_list_11cb_4000 NULL +#define pci_ss_list_11cb_8000 NULL +#endif +#define pci_ss_list_11d1_01f7 NULL +#define pci_ss_list_11d4_1535 NULL +#define pci_ss_list_11d4_1805 NULL +#define pci_ss_list_11d4_1889 NULL +#define pci_ss_list_11d4_1986 NULL +#define pci_ss_list_11d4_5340 NULL +#define pci_ss_list_11d5_0115 NULL +#define pci_ss_list_11d5_0117 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11de_6057[] = { + &pci_ss_info_11de_6057_1031_7efe, + &pci_ss_info_11de_6057_1031_fc00, + &pci_ss_info_11de_6057_12f8_8a02, + &pci_ss_info_11de_6057_13ca_4231, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11de_6120[] = { + &pci_ss_info_11de_6120_1328_f001, + &pci_ss_info_11de_6120_13c2_0000, + &pci_ss_info_11de_6120_1de1_9fff, + NULL +}; +#endif +#define pci_ss_list_11e3_0001 NULL +#define pci_ss_list_11e3_5030 NULL +#define pci_ss_list_11f0_4231 NULL +#define pci_ss_list_11f0_4232 NULL +#define pci_ss_list_11f0_4233 NULL +#define pci_ss_list_11f0_4234 NULL +#define pci_ss_list_11f0_4235 NULL +#define pci_ss_list_11f0_4236 NULL +#define pci_ss_list_11f0_4731 NULL +#define pci_ss_list_11f4_2915 NULL +#define pci_ss_list_11f6_0112 NULL +#define pci_ss_list_11f6_0113 NULL +#define pci_ss_list_11f6_1401 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11f6_2011[] = { + &pci_ss_info_11f6_2011_11f6_2011, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_11f6_2201[] = { + &pci_ss_info_11f6_2201_11f6_2011, + NULL +}; +#define pci_ss_list_11f6_9881 NULL +#endif +#define pci_ss_list_11f8_7375 NULL +#define pci_ss_list_11fe_0001 NULL +#define pci_ss_list_11fe_0002 NULL +#define pci_ss_list_11fe_0003 NULL +#define pci_ss_list_11fe_0004 NULL +#define pci_ss_list_11fe_0005 NULL +#define pci_ss_list_11fe_0006 NULL +#define pci_ss_list_11fe_0007 NULL +#define pci_ss_list_11fe_0008 NULL +#define pci_ss_list_11fe_0009 NULL +#define pci_ss_list_11fe_000a NULL +#define pci_ss_list_11fe_000b NULL +#define pci_ss_list_11fe_000c NULL +#define pci_ss_list_11fe_000d NULL +#define pci_ss_list_11fe_000e NULL +#define pci_ss_list_11fe_000f NULL +#define pci_ss_list_11fe_0801 NULL +#define pci_ss_list_11fe_0802 NULL +#define pci_ss_list_11fe_0803 NULL +#define pci_ss_list_11fe_0805 NULL +#define pci_ss_list_11fe_080c NULL +#define pci_ss_list_11fe_080d NULL +#define pci_ss_list_11fe_0812 NULL +#define pci_ss_list_11fe_0903 NULL +#define pci_ss_list_11fe_8015 NULL +#define pci_ss_list_11ff_0003 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1202_4300[] = { + &pci_ss_info_1202_4300_1202_9841, + &pci_ss_info_1202_4300_1202_9842, + &pci_ss_info_1202_4300_1202_9843, + &pci_ss_info_1202_4300_1202_9844, + NULL +}; +#endif +#define pci_ss_list_1208_4853 NULL +#define pci_ss_list_120e_0100 NULL +#define pci_ss_list_120e_0101 NULL +#define pci_ss_list_120e_0102 NULL +#define pci_ss_list_120e_0103 NULL +#define pci_ss_list_120e_0104 NULL +#define pci_ss_list_120e_0105 NULL +#define pci_ss_list_120e_0200 NULL +#define pci_ss_list_120e_0201 NULL +#define pci_ss_list_120e_0300 NULL +#define pci_ss_list_120e_0301 NULL +#define pci_ss_list_120e_0310 NULL +#define pci_ss_list_120e_0311 NULL +#define pci_ss_list_120e_0320 NULL +#define pci_ss_list_120e_0321 NULL +#define pci_ss_list_120e_0400 NULL +#define pci_ss_list_120f_0001 NULL +#define pci_ss_list_1217_00f7 NULL +#define pci_ss_list_1217_6729 NULL +#define pci_ss_list_1217_673a NULL +#define pci_ss_list_1217_6832 NULL +#define pci_ss_list_1217_6836 NULL +#define pci_ss_list_1217_6872 NULL +#define pci_ss_list_1217_6925 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1217_6933[] = { + &pci_ss_info_1217_6933_1025_1016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1217_6972[] = { + &pci_ss_info_1217_6972_1014_020c, + &pci_ss_info_1217_6972_1179_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1217_7110[] = { + &pci_ss_info_1217_7110_103c_088c, + &pci_ss_info_1217_7110_103c_0890, + &pci_ss_info_1217_7110_1734_106c, + NULL +}; +#define pci_ss_list_1217_7112 NULL +#define pci_ss_list_1217_7113 NULL +#define pci_ss_list_1217_7114 NULL +#define pci_ss_list_1217_7120 NULL +#define pci_ss_list_1217_7130 NULL +#define pci_ss_list_1217_7134 NULL +#define pci_ss_list_1217_7135 NULL +#define pci_ss_list_1217_71e2 NULL +#define pci_ss_list_1217_7212 NULL +#define pci_ss_list_1217_7213 NULL +static const pciSubsystemInfo *pci_ss_list_1217_7223[] = { + &pci_ss_info_1217_7223_103c_088c, + &pci_ss_info_1217_7223_103c_0890, + NULL +}; +#define pci_ss_list_1217_7233 NULL +#endif +#define pci_ss_list_121a_0001 NULL +#define pci_ss_list_121a_0002 NULL +static const pciSubsystemInfo *pci_ss_list_121a_0003[] = { + &pci_ss_info_121a_0003_1092_0003, + &pci_ss_info_121a_0003_1092_4000, + &pci_ss_info_121a_0003_1092_4002, + &pci_ss_info_121a_0003_1092_4801, + &pci_ss_info_121a_0003_1092_4803, + &pci_ss_info_121a_0003_1092_8030, + &pci_ss_info_121a_0003_1092_8035, + &pci_ss_info_121a_0003_10b0_0001, + &pci_ss_info_121a_0003_1102_1018, + &pci_ss_info_121a_0003_121a_0001, + &pci_ss_info_121a_0003_121a_0003, + &pci_ss_info_121a_0003_121a_0004, + &pci_ss_info_121a_0003_139c_0016, + &pci_ss_info_121a_0003_139c_0017, + &pci_ss_info_121a_0003_14af_0002, + NULL +}; +#define pci_ss_list_121a_0004 NULL +static const pciSubsystemInfo *pci_ss_list_121a_0005[] = { + &pci_ss_info_121a_0005_121a_0004, + &pci_ss_info_121a_0005_121a_0030, + &pci_ss_info_121a_0005_121a_0031, + &pci_ss_info_121a_0005_121a_0034, + &pci_ss_info_121a_0005_121a_0036, + &pci_ss_info_121a_0005_121a_0037, + &pci_ss_info_121a_0005_121a_0038, + &pci_ss_info_121a_0005_121a_003a, + &pci_ss_info_121a_0005_121a_0044, + &pci_ss_info_121a_0005_121a_004b, + &pci_ss_info_121a_0005_121a_004c, + &pci_ss_info_121a_0005_121a_004d, + &pci_ss_info_121a_0005_121a_004e, + &pci_ss_info_121a_0005_121a_0051, + &pci_ss_info_121a_0005_121a_0052, + &pci_ss_info_121a_0005_121a_0057, + &pci_ss_info_121a_0005_121a_0060, + &pci_ss_info_121a_0005_121a_0061, + &pci_ss_info_121a_0005_121a_0062, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_121a_0009[] = { + &pci_ss_info_121a_0009_121a_0003, + &pci_ss_info_121a_0009_121a_0009, + NULL +}; +#define pci_ss_list_121a_0057 NULL +#define pci_ss_list_121e_0201 NULL +#define pci_ss_list_1220_1220 NULL +#define pci_ss_list_1223_0003 NULL +#define pci_ss_list_1223_0004 NULL +#define pci_ss_list_1223_0005 NULL +#define pci_ss_list_1223_0008 NULL +#define pci_ss_list_1223_0009 NULL +#define pci_ss_list_1223_000a NULL +#define pci_ss_list_1223_000b NULL +#define pci_ss_list_1223_000c NULL +#define pci_ss_list_1223_000d NULL +#define pci_ss_list_1223_000e NULL +#define pci_ss_list_1227_0006 NULL +#define pci_ss_list_1227_0023 NULL +#define pci_ss_list_122d_1206 NULL +#define pci_ss_list_122d_1400 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_122d_50dc[] = { + &pci_ss_info_122d_50dc_122d_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_122d_80da[] = { + &pci_ss_info_122d_80da_122d_0001, + NULL +}; +#endif +#define pci_ss_list_1236_0000 NULL +#define pci_ss_list_1236_6401 NULL +#define pci_ss_list_123d_0000 NULL +#define pci_ss_list_123d_0002 NULL +#define pci_ss_list_123d_0003 NULL +#define pci_ss_list_123f_00e4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_123f_8120[] = { + &pci_ss_info_123f_8120_11bd_0006, + &pci_ss_info_123f_8120_11bd_000a, + &pci_ss_info_123f_8120_11bd_000f, + &pci_ss_info_123f_8120_1809_0016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_123f_8888[] = { + &pci_ss_info_123f_8888_1002_0001, + &pci_ss_info_123f_8888_1002_0002, + &pci_ss_info_123f_8888_1328_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1242_1560[] = { + &pci_ss_info_1242_1560_1242_6562, + &pci_ss_info_1242_1560_1242_656a, + NULL +}; +#define pci_ss_list_1242_4643 NULL +#define pci_ss_list_1242_6562 NULL +#define pci_ss_list_1242_656a NULL +#endif +#define pci_ss_list_1244_0700 NULL +#define pci_ss_list_1244_0800 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1244_0a00[] = { + &pci_ss_info_1244_0a00_1244_0a00, + NULL +}; +#define pci_ss_list_1244_0e00 NULL +#define pci_ss_list_1244_1100 NULL +#define pci_ss_list_1244_1200 NULL +#define pci_ss_list_1244_2700 NULL +#define pci_ss_list_1244_2900 NULL +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_124b_0040[] = { + &pci_ss_info_124b_0040_124b_9080, + NULL +}; +#endif +#define pci_ss_list_124d_0000 NULL +#define pci_ss_list_124d_0002 NULL +#define pci_ss_list_124d_0003 NULL +#define pci_ss_list_124d_0004 NULL +#define pci_ss_list_124f_0041 NULL +#define pci_ss_list_1255_1110 NULL +#define pci_ss_list_1255_1210 NULL +#define pci_ss_list_1255_2110 NULL +#define pci_ss_list_1255_2120 NULL +#define pci_ss_list_1255_2130 NULL +#define pci_ss_list_1256_4201 NULL +#define pci_ss_list_1256_4401 NULL +#define pci_ss_list_1256_5201 NULL +#define pci_ss_list_1259_2560 NULL +#define pci_ss_list_1259_a117 NULL +#define pci_ss_list_1259_a11e NULL +#define pci_ss_list_1259_a120 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_125b_1400[] = { + &pci_ss_info_125b_1400_1186_1100, + NULL +}; +#endif +#define pci_ss_list_125c_0101 NULL +#define pci_ss_list_125c_0640 NULL +#define pci_ss_list_125d_0000 NULL +#define pci_ss_list_125d_1948 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_125d_1968[] = { + &pci_ss_info_125d_1968_1028_0085, + &pci_ss_info_125d_1968_1033_8051, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1969[] = { + &pci_ss_info_125d_1969_1014_0166, + &pci_ss_info_125d_1969_125d_8888, + &pci_ss_info_125d_1969_153b_111b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1978[] = { + &pci_ss_info_125d_1978_0e11_b112, + &pci_ss_info_125d_1978_1033_803c, + &pci_ss_info_125d_1978_1033_8058, + &pci_ss_info_125d_1978_1092_4000, + &pci_ss_info_125d_1978_1179_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1988[] = { + &pci_ss_info_125d_1988_0e11_0098, + &pci_ss_info_125d_1988_1092_4100, + &pci_ss_info_125d_1988_125d_1988, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1989[] = { + &pci_ss_info_125d_1989_125d_1989, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_125d_1998[] = { + &pci_ss_info_125d_1998_1028_00b1, + &pci_ss_info_125d_1998_1028_00e6, + NULL +}; +#define pci_ss_list_125d_1999 NULL +#define pci_ss_list_125d_199a NULL +#define pci_ss_list_125d_199b NULL +#define pci_ss_list_125d_2808 NULL +#define pci_ss_list_125d_2838 NULL +static const pciSubsystemInfo *pci_ss_list_125d_2898[] = { + &pci_ss_info_125d_2898_125d_0424, + &pci_ss_info_125d_2898_125d_0425, + &pci_ss_info_125d_2898_125d_0426, + &pci_ss_info_125d_2898_125d_0427, + &pci_ss_info_125d_2898_125d_0428, + &pci_ss_info_125d_2898_125d_0429, + &pci_ss_info_125d_2898_147a_c001, + &pci_ss_info_125d_2898_14fe_0428, + &pci_ss_info_125d_2898_14fe_0429, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1260_3872[] = { + &pci_ss_info_1260_3872_1468_0202, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1260_3873[] = { + &pci_ss_info_1260_3873_1186_3501, + &pci_ss_info_1260_3873_1186_3700, + &pci_ss_info_1260_3873_1385_4105, + &pci_ss_info_1260_3873_1668_0414, + &pci_ss_info_1260_3873_16a5_1601, + &pci_ss_info_1260_3873_1737_3874, + &pci_ss_info_1260_3873_8086_2513, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1260_3886[] = { + &pci_ss_info_1260_3886_17cf_0037, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1260_3890[] = { + &pci_ss_info_1260_3890_10b8_2802, + &pci_ss_info_1260_3890_10b8_2835, + &pci_ss_info_1260_3890_10b8_a835, + &pci_ss_info_1260_3890_1113_4203, + &pci_ss_info_1260_3890_1113_ee03, + &pci_ss_info_1260_3890_1113_ee08, + &pci_ss_info_1260_3890_1186_3202, + &pci_ss_info_1260_3890_1259_c104, + &pci_ss_info_1260_3890_1260_0000, + &pci_ss_info_1260_3890_1385_4800, + &pci_ss_info_1260_3890_16a5_1605, + &pci_ss_info_1260_3890_17cf_0014, + &pci_ss_info_1260_3890_17cf_0020, + NULL +}; +#define pci_ss_list_1260_8130 NULL +#define pci_ss_list_1260_8131 NULL +static const pciSubsystemInfo *pci_ss_list_1260_ffff[] = { + &pci_ss_info_1260_ffff_1260_0000, + NULL +}; +#endif +#define pci_ss_list_1266_0001 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1266_1910[] = { + &pci_ss_info_1266_1910_1266_1910, + NULL +}; +#endif +#define pci_ss_list_1267_5352 NULL +#define pci_ss_list_1267_5a4b NULL +#define pci_ss_list_126c_1211 NULL +#define pci_ss_list_126c_126c NULL +#define pci_ss_list_126f_0501 NULL +#define pci_ss_list_126f_0510 NULL +#define pci_ss_list_126f_0710 NULL +#define pci_ss_list_126f_0712 NULL +#define pci_ss_list_126f_0720 NULL +#define pci_ss_list_126f_0730 NULL +#define pci_ss_list_126f_0810 NULL +#define pci_ss_list_126f_0811 NULL +#define pci_ss_list_126f_0820 NULL +#define pci_ss_list_126f_0910 NULL +#define pci_ss_list_1273_0002 NULL +#define pci_ss_list_1274_1171 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1274_1371[] = { + &pci_ss_info_1274_1371_0e11_0024, + &pci_ss_info_1274_1371_0e11_b1a7, + &pci_ss_info_1274_1371_1033_80ac, + &pci_ss_info_1274_1371_1042_1854, + &pci_ss_info_1274_1371_107b_8054, + &pci_ss_info_1274_1371_1274_1371, + &pci_ss_info_1274_1371_1274_8001, + &pci_ss_info_1274_1371_1462_6470, + &pci_ss_info_1274_1371_1462_6560, + &pci_ss_info_1274_1371_1462_6630, + &pci_ss_info_1274_1371_1462_6631, + &pci_ss_info_1274_1371_1462_6632, + &pci_ss_info_1274_1371_1462_6633, + &pci_ss_info_1274_1371_1462_6820, + &pci_ss_info_1274_1371_1462_6822, + &pci_ss_info_1274_1371_1462_6830, + &pci_ss_info_1274_1371_1462_6880, + &pci_ss_info_1274_1371_1462_6900, + &pci_ss_info_1274_1371_1462_6910, + &pci_ss_info_1274_1371_1462_6930, + &pci_ss_info_1274_1371_1462_6990, + &pci_ss_info_1274_1371_1462_6991, + &pci_ss_info_1274_1371_14a4_2077, + &pci_ss_info_1274_1371_14a4_2105, + &pci_ss_info_1274_1371_14a4_2107, + &pci_ss_info_1274_1371_14a4_2172, + &pci_ss_info_1274_1371_1509_9902, + &pci_ss_info_1274_1371_1509_9903, + &pci_ss_info_1274_1371_1509_9904, + &pci_ss_info_1274_1371_1509_9905, + &pci_ss_info_1274_1371_152d_8801, + &pci_ss_info_1274_1371_152d_8802, + &pci_ss_info_1274_1371_152d_8803, + &pci_ss_info_1274_1371_152d_8804, + &pci_ss_info_1274_1371_152d_8805, + &pci_ss_info_1274_1371_270f_2001, + &pci_ss_info_1274_1371_270f_2200, + &pci_ss_info_1274_1371_270f_3000, + &pci_ss_info_1274_1371_270f_3100, + &pci_ss_info_1274_1371_270f_3102, + &pci_ss_info_1274_1371_270f_7060, + &pci_ss_info_1274_1371_8086_4249, + &pci_ss_info_1274_1371_8086_424c, + &pci_ss_info_1274_1371_8086_425a, + &pci_ss_info_1274_1371_8086_4341, + &pci_ss_info_1274_1371_8086_4343, + &pci_ss_info_1274_1371_8086_4541, + &pci_ss_info_1274_1371_8086_4649, + &pci_ss_info_1274_1371_8086_464a, + &pci_ss_info_1274_1371_8086_4d4f, + &pci_ss_info_1274_1371_8086_4f43, + &pci_ss_info_1274_1371_8086_5243, + &pci_ss_info_1274_1371_8086_5352, + &pci_ss_info_1274_1371_8086_5643, + &pci_ss_info_1274_1371_8086_5753, + NULL +}; +#define pci_ss_list_1274_5000 NULL +static const pciSubsystemInfo *pci_ss_list_1274_5880[] = { + &pci_ss_info_1274_5880_1274_2000, + &pci_ss_info_1274_5880_1274_2003, + &pci_ss_info_1274_5880_1274_5880, + &pci_ss_info_1274_5880_1274_8001, + &pci_ss_info_1274_5880_1458_a000, + &pci_ss_info_1274_5880_1462_6880, + &pci_ss_info_1274_5880_270f_2001, + &pci_ss_info_1274_5880_270f_2200, + &pci_ss_info_1274_5880_270f_7040, + NULL +}; +#endif +#define pci_ss_list_1278_0701 NULL +#define pci_ss_list_1278_0710 NULL +#define pci_ss_list_1279_0060 NULL +#define pci_ss_list_1279_0061 NULL +#define pci_ss_list_1279_0295 NULL +#define pci_ss_list_1279_0395 NULL +#define pci_ss_list_1279_0396 NULL +#define pci_ss_list_1279_0397 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_127a_1002[] = { + &pci_ss_info_127a_1002_1092_094c, + &pci_ss_info_127a_1002_122d_4002, + &pci_ss_info_127a_1002_122d_4005, + &pci_ss_info_127a_1002_122d_4007, + &pci_ss_info_127a_1002_122d_4012, + &pci_ss_info_127a_1002_122d_4017, + &pci_ss_info_127a_1002_122d_4018, + &pci_ss_info_127a_1002_127a_1002, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1003[] = { + &pci_ss_info_127a_1003_0e11_b0bc, + &pci_ss_info_127a_1003_0e11_b114, + &pci_ss_info_127a_1003_1033_802b, + &pci_ss_info_127a_1003_13df_1003, + &pci_ss_info_127a_1003_13e0_0117, + &pci_ss_info_127a_1003_13e0_0147, + &pci_ss_info_127a_1003_13e0_0197, + &pci_ss_info_127a_1003_13e0_01c7, + &pci_ss_info_127a_1003_13e0_01f7, + &pci_ss_info_127a_1003_1436_1003, + &pci_ss_info_127a_1003_1436_1103, + &pci_ss_info_127a_1003_1436_1602, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1004[] = { + &pci_ss_info_127a_1004_1048_1500, + &pci_ss_info_127a_1004_10cf_1059, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1005[] = { + &pci_ss_info_127a_1005_1005_127a, + &pci_ss_info_127a_1005_1033_8029, + &pci_ss_info_127a_1005_1033_8054, + &pci_ss_info_127a_1005_10cf_103c, + &pci_ss_info_127a_1005_10cf_1055, + &pci_ss_info_127a_1005_10cf_1056, + &pci_ss_info_127a_1005_122d_4003, + &pci_ss_info_127a_1005_122d_4006, + &pci_ss_info_127a_1005_122d_4008, + &pci_ss_info_127a_1005_122d_4009, + &pci_ss_info_127a_1005_122d_4010, + &pci_ss_info_127a_1005_122d_4011, + &pci_ss_info_127a_1005_122d_4013, + &pci_ss_info_127a_1005_122d_4015, + &pci_ss_info_127a_1005_122d_4016, + &pci_ss_info_127a_1005_122d_4019, + &pci_ss_info_127a_1005_13df_1005, + &pci_ss_info_127a_1005_13e0_0187, + &pci_ss_info_127a_1005_13e0_01a7, + &pci_ss_info_127a_1005_13e0_01b7, + &pci_ss_info_127a_1005_13e0_01d7, + &pci_ss_info_127a_1005_1436_1005, + &pci_ss_info_127a_1005_1436_1105, + &pci_ss_info_127a_1005_1437_1105, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1022[] = { + &pci_ss_info_127a_1022_1436_1303, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_1023[] = { + &pci_ss_info_127a_1023_122d_4020, + &pci_ss_info_127a_1023_122d_4023, + &pci_ss_info_127a_1023_13e0_0247, + &pci_ss_info_127a_1023_13e0_0297, + &pci_ss_info_127a_1023_13e0_02c7, + &pci_ss_info_127a_1023_1436_1203, + &pci_ss_info_127a_1023_1436_1303, + NULL +}; +#define pci_ss_list_127a_1024 NULL +static const pciSubsystemInfo *pci_ss_list_127a_1025[] = { + &pci_ss_info_127a_1025_10cf_106a, + &pci_ss_info_127a_1025_122d_4021, + &pci_ss_info_127a_1025_122d_4022, + &pci_ss_info_127a_1025_122d_4024, + &pci_ss_info_127a_1025_122d_4025, + NULL +}; +#define pci_ss_list_127a_1026 NULL +#define pci_ss_list_127a_1032 NULL +#define pci_ss_list_127a_1033 NULL +#define pci_ss_list_127a_1034 NULL +#define pci_ss_list_127a_1035 NULL +#define pci_ss_list_127a_1036 NULL +#define pci_ss_list_127a_1085 NULL +static const pciSubsystemInfo *pci_ss_list_127a_2005[] = { + &pci_ss_info_127a_2005_104d_8044, + &pci_ss_info_127a_2005_104d_8045, + &pci_ss_info_127a_2005_104d_8055, + &pci_ss_info_127a_2005_104d_8056, + &pci_ss_info_127a_2005_104d_805a, + &pci_ss_info_127a_2005_104d_805f, + &pci_ss_info_127a_2005_104d_8074, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_2013[] = { + &pci_ss_info_127a_2013_1179_0001, + &pci_ss_info_127a_2013_1179_ff00, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_2014[] = { + &pci_ss_info_127a_2014_10cf_1057, + &pci_ss_info_127a_2014_122d_4050, + &pci_ss_info_127a_2014_122d_4055, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_2015[] = { + &pci_ss_info_127a_2015_10cf_1063, + &pci_ss_info_127a_2015_10cf_1064, + &pci_ss_info_127a_2015_1468_2015, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_2016[] = { + &pci_ss_info_127a_2016_122d_4051, + &pci_ss_info_127a_2016_122d_4052, + &pci_ss_info_127a_2016_122d_4054, + &pci_ss_info_127a_2016_122d_4056, + &pci_ss_info_127a_2016_122d_4057, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_4311[] = { + &pci_ss_info_127a_4311_127a_4311, + &pci_ss_info_127a_4311_13e0_0210, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_4320[] = { + &pci_ss_info_127a_4320_1235_4320, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_4321[] = { + &pci_ss_info_127a_4321_1235_4321, + &pci_ss_info_127a_4321_1235_4324, + &pci_ss_info_127a_4321_13e0_0210, + &pci_ss_info_127a_4321_144d_2321, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_4322[] = { + &pci_ss_info_127a_4322_1235_4322, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_127a_8234[] = { + &pci_ss_info_127a_8234_108d_0022, + &pci_ss_info_127a_8234_108d_0027, + NULL +}; +#endif +#define pci_ss_list_1282_9009 NULL +#define pci_ss_list_1282_9100 NULL +#define pci_ss_list_1282_9102 NULL +#define pci_ss_list_1282_9132 NULL +#define pci_ss_list_1283_673a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1283_8211[] = { + &pci_ss_info_1283_8211_1043_8138, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1283_8212[] = { + &pci_ss_info_1283_8212_1283_0001, + NULL +}; +#define pci_ss_list_1283_8330 NULL +#define pci_ss_list_1283_8872 NULL +#define pci_ss_list_1283_8888 NULL +#define pci_ss_list_1283_8889 NULL +#define pci_ss_list_1283_e886 NULL +#endif +#define pci_ss_list_1285_0100 NULL +#define pci_ss_list_1287_001e NULL +#define pci_ss_list_1287_001f NULL +#define pci_ss_list_128d_0021 NULL +#define pci_ss_list_128e_0008 NULL +#define pci_ss_list_128e_0009 NULL +#define pci_ss_list_128e_000a NULL +#define pci_ss_list_128e_000b NULL +#define pci_ss_list_128e_000c NULL +#define pci_ss_list_129a_0615 NULL +#define pci_ss_list_12a3_8105 NULL +#define pci_ss_list_12ab_0002 NULL +#define pci_ss_list_12ab_3000 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12ae_0001[] = { + &pci_ss_info_12ae_0001_1014_0104, + &pci_ss_info_12ae_0001_12ae_0001, + &pci_ss_info_12ae_0001_1410_0104, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12ae_0002[] = { + &pci_ss_info_12ae_0002_10a9_8002, + &pci_ss_info_12ae_0002_12ae_0002, + NULL +}; +#define pci_ss_list_12ae_00fa NULL +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12b9_1006[] = { + &pci_ss_info_12b9_1006_12b9_005c, + &pci_ss_info_12b9_1006_12b9_005e, + &pci_ss_info_12b9_1006_12b9_0062, + &pci_ss_info_12b9_1006_12b9_0068, + &pci_ss_info_12b9_1006_12b9_007a, + &pci_ss_info_12b9_1006_12b9_007f, + &pci_ss_info_12b9_1006_12b9_0080, + &pci_ss_info_12b9_1006_12b9_0081, + &pci_ss_info_12b9_1006_12b9_0091, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12b9_1007[] = { + &pci_ss_info_12b9_1007_12b9_00a3, + &pci_ss_info_12b9_1007_12b9_00c4, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12b9_1008[] = { + &pci_ss_info_12b9_1008_12b9_00a2, + &pci_ss_info_12b9_1008_12b9_00aa, + &pci_ss_info_12b9_1008_12b9_00ab, + &pci_ss_info_12b9_1008_12b9_00ac, + &pci_ss_info_12b9_1008_12b9_00ad, + NULL +}; +#endif +#define pci_ss_list_12be_3041 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12be_3042[] = { + &pci_ss_info_12be_3042_12be_3042, + NULL +}; +#endif +#define pci_ss_list_12c3_0058 NULL +#define pci_ss_list_12c3_5598 NULL +#define pci_ss_list_12c4_0001 NULL +#define pci_ss_list_12c4_0002 NULL +#define pci_ss_list_12c4_0003 NULL +#define pci_ss_list_12c4_0004 NULL +#define pci_ss_list_12c4_0005 NULL +#define pci_ss_list_12c4_0006 NULL +#define pci_ss_list_12c4_0007 NULL +#define pci_ss_list_12c4_0008 NULL +#define pci_ss_list_12c4_0009 NULL +#define pci_ss_list_12c4_000a NULL +#define pci_ss_list_12c4_000b NULL +#define pci_ss_list_12c4_000c NULL +#define pci_ss_list_12c4_000d NULL +#define pci_ss_list_12c4_0100 NULL +#define pci_ss_list_12c4_0201 NULL +#define pci_ss_list_12c4_0202 NULL +#define pci_ss_list_12c4_0300 NULL +#define pci_ss_list_12c4_0301 NULL +#define pci_ss_list_12c4_0302 NULL +#define pci_ss_list_12c4_0310 NULL +#define pci_ss_list_12c4_0311 NULL +#define pci_ss_list_12c4_0312 NULL +#define pci_ss_list_12c4_0320 NULL +#define pci_ss_list_12c4_0321 NULL +#define pci_ss_list_12c4_0322 NULL +#define pci_ss_list_12c4_0330 NULL +#define pci_ss_list_12c4_0331 NULL +#define pci_ss_list_12c4_0332 NULL +#define pci_ss_list_12c5_007e NULL +#define pci_ss_list_12c5_007f NULL +#define pci_ss_list_12c5_0081 NULL +#define pci_ss_list_12c5_0085 NULL +#define pci_ss_list_12c5_0086 NULL +#define pci_ss_list_12d2_0008 NULL +#define pci_ss_list_12d2_0009 NULL +static const pciSubsystemInfo *pci_ss_list_12d2_0018[] = { + &pci_ss_info_12d2_0018_1048_0c10, + &pci_ss_info_12d2_0018_107b_8030, + &pci_ss_info_12d2_0018_1092_0350, + &pci_ss_info_12d2_0018_1092_1092, + &pci_ss_info_12d2_0018_10b4_1b1b, + &pci_ss_info_12d2_0018_10b4_1b1d, + &pci_ss_info_12d2_0018_10b4_1b1e, + &pci_ss_info_12d2_0018_10b4_1b20, + &pci_ss_info_12d2_0018_10b4_1b21, + &pci_ss_info_12d2_0018_10b4_1b22, + &pci_ss_info_12d2_0018_10b4_1b23, + &pci_ss_info_12d2_0018_10b4_1b27, + &pci_ss_info_12d2_0018_10b4_1b88, + &pci_ss_info_12d2_0018_10b4_222a, + &pci_ss_info_12d2_0018_10b4_2230, + &pci_ss_info_12d2_0018_10b4_2232, + &pci_ss_info_12d2_0018_10b4_2235, + &pci_ss_info_12d2_0018_2a15_54a3, + NULL +}; +#define pci_ss_list_12d2_0019 NULL +#define pci_ss_list_12d2_0020 NULL +#define pci_ss_list_12d2_0028 NULL +#define pci_ss_list_12d2_0029 NULL +#define pci_ss_list_12d2_002c NULL +#define pci_ss_list_12d2_00a0 NULL +#define pci_ss_list_12d4_0200 NULL +#define pci_ss_list_12d5_0003 NULL +#define pci_ss_list_12d5_1000 NULL +#define pci_ss_list_12d8_8150 NULL +#define pci_ss_list_12d9_0002 NULL +#define pci_ss_list_12d9_0004 NULL +#define pci_ss_list_12d9_0005 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12d9_1078[] = { + &pci_ss_info_12d9_1078_12d9_000d, + NULL +}; +#endif +#define pci_ss_list_12de_0200 NULL +#define pci_ss_list_12e0_0010 NULL +#define pci_ss_list_12e0_0020 NULL +#define pci_ss_list_12e0_0030 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12eb_0001[] = { + &pci_ss_info_12eb_0001_104d_8036, + &pci_ss_info_12eb_0001_1092_2000, + &pci_ss_info_12eb_0001_1092_2100, + &pci_ss_info_12eb_0001_1092_2110, + &pci_ss_info_12eb_0001_1092_2200, + &pci_ss_info_12eb_0001_122d_1002, + &pci_ss_info_12eb_0001_12eb_0001, + &pci_ss_info_12eb_0001_5053_3355, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12eb_0002[] = { + &pci_ss_info_12eb_0002_104d_8049, + &pci_ss_info_12eb_0002_104d_807b, + &pci_ss_info_12eb_0002_1092_3000, + &pci_ss_info_12eb_0002_1092_3001, + &pci_ss_info_12eb_0002_1092_3002, + &pci_ss_info_12eb_0002_1092_3003, + &pci_ss_info_12eb_0002_1092_3004, + &pci_ss_info_12eb_0002_12eb_0002, + &pci_ss_info_12eb_0002_12eb_0088, + &pci_ss_info_12eb_0002_144d_3510, + &pci_ss_info_12eb_0002_5053_3356, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12eb_0003[] = { + &pci_ss_info_12eb_0003_104d_8049, + &pci_ss_info_12eb_0003_104d_8077, + &pci_ss_info_12eb_0003_109f_1000, + &pci_ss_info_12eb_0003_12eb_0003, + &pci_ss_info_12eb_0003_1462_6780, + &pci_ss_info_12eb_0003_14a4_2073, + &pci_ss_info_12eb_0003_14a4_2091, + &pci_ss_info_12eb_0003_14a4_2104, + &pci_ss_info_12eb_0003_14a4_2106, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_12eb_8803[] = { + &pci_ss_info_12eb_8803_12eb_8803, + NULL +}; +#endif +#define pci_ss_list_12f8_0002 NULL +#define pci_ss_list_12fb_0001 NULL +#define pci_ss_list_12fb_00f5 NULL +#define pci_ss_list_12fb_02ad NULL +#define pci_ss_list_12fb_2adc NULL +#define pci_ss_list_12fb_3100 NULL +#define pci_ss_list_12fb_3500 NULL +#define pci_ss_list_12fb_4d4f NULL +#define pci_ss_list_12fb_8120 NULL +#define pci_ss_list_12fb_da62 NULL +#define pci_ss_list_12fb_db62 NULL +#define pci_ss_list_12fb_dc62 NULL +#define pci_ss_list_12fb_dd62 NULL +#define pci_ss_list_12fb_eddc NULL +#define pci_ss_list_12fb_fa01 NULL +#define pci_ss_list_1307_0001 NULL +#define pci_ss_list_1307_000b NULL +#define pci_ss_list_1307_000c NULL +#define pci_ss_list_1307_000d NULL +#define pci_ss_list_1307_000f NULL +#define pci_ss_list_1307_0010 NULL +#define pci_ss_list_1307_0014 NULL +#define pci_ss_list_1307_0015 NULL +#define pci_ss_list_1307_0016 NULL +#define pci_ss_list_1307_0017 NULL +#define pci_ss_list_1307_0018 NULL +#define pci_ss_list_1307_0019 NULL +#define pci_ss_list_1307_001a NULL +#define pci_ss_list_1307_001b NULL +#define pci_ss_list_1307_001c NULL +#define pci_ss_list_1307_001d NULL +#define pci_ss_list_1307_001e NULL +#define pci_ss_list_1307_001f NULL +#define pci_ss_list_1307_0020 NULL +#define pci_ss_list_1307_0021 NULL +#define pci_ss_list_1307_0022 NULL +#define pci_ss_list_1307_0023 NULL +#define pci_ss_list_1307_0024 NULL +#define pci_ss_list_1307_0025 NULL +#define pci_ss_list_1307_0026 NULL +#define pci_ss_list_1307_0027 NULL +#define pci_ss_list_1307_0028 NULL +#define pci_ss_list_1307_0029 NULL +#define pci_ss_list_1307_002c NULL +#define pci_ss_list_1307_0033 NULL +#define pci_ss_list_1307_0034 NULL +#define pci_ss_list_1307_0035 NULL +#define pci_ss_list_1307_0036 NULL +#define pci_ss_list_1307_0037 NULL +#define pci_ss_list_1307_004c NULL +#define pci_ss_list_1307_004d NULL +#define pci_ss_list_1307_0052 NULL +#define pci_ss_list_1307_0054 NULL +#define pci_ss_list_1307_005e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1308_0001[] = { + &pci_ss_info_1308_0001_1308_0001, + NULL +}; +#endif +#define pci_ss_list_1317_0981 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1317_0985[] = { + &pci_ss_info_1317_0985_1734_100c, + NULL +}; +#define pci_ss_list_1317_1985 NULL +#define pci_ss_list_1317_2850 NULL +#define pci_ss_list_1317_5120 NULL +static const pciSubsystemInfo *pci_ss_list_1317_8201[] = { + &pci_ss_info_1317_8201_10b8_2635, + &pci_ss_info_1317_8201_1317_8201, + NULL +}; +#define pci_ss_list_1317_8211 NULL +#define pci_ss_list_1317_9511 NULL +#endif +#define pci_ss_list_1318_0911 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1319_0801[] = { + &pci_ss_info_1319_0801_1319_1319, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1319_0802[] = { + &pci_ss_info_1319_0802_1319_1319, + NULL +}; +#define pci_ss_list_1319_1000 NULL +#define pci_ss_list_1319_1001 NULL +#endif +#define pci_ss_list_131f_1000 NULL +#define pci_ss_list_131f_1001 NULL +#define pci_ss_list_131f_1002 NULL +#define pci_ss_list_131f_1010 NULL +#define pci_ss_list_131f_1011 NULL +#define pci_ss_list_131f_1012 NULL +#define pci_ss_list_131f_1020 NULL +#define pci_ss_list_131f_1021 NULL +#define pci_ss_list_131f_1030 NULL +#define pci_ss_list_131f_1031 NULL +#define pci_ss_list_131f_1032 NULL +#define pci_ss_list_131f_1034 NULL +#define pci_ss_list_131f_1035 NULL +#define pci_ss_list_131f_1036 NULL +#define pci_ss_list_131f_1050 NULL +#define pci_ss_list_131f_1051 NULL +#define pci_ss_list_131f_1052 NULL +#define pci_ss_list_131f_2000 NULL +#define pci_ss_list_131f_2001 NULL +#define pci_ss_list_131f_2002 NULL +#define pci_ss_list_131f_2010 NULL +#define pci_ss_list_131f_2011 NULL +#define pci_ss_list_131f_2012 NULL +#define pci_ss_list_131f_2020 NULL +#define pci_ss_list_131f_2021 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_131f_2030[] = { + &pci_ss_info_131f_2030_131f_2030, + NULL +}; +#define pci_ss_list_131f_2031 NULL +#define pci_ss_list_131f_2032 NULL +#define pci_ss_list_131f_2040 NULL +#define pci_ss_list_131f_2041 NULL +#define pci_ss_list_131f_2042 NULL +#define pci_ss_list_131f_2050 NULL +#define pci_ss_list_131f_2051 NULL +#define pci_ss_list_131f_2052 NULL +#define pci_ss_list_131f_2060 NULL +#define pci_ss_list_131f_2061 NULL +#define pci_ss_list_131f_2062 NULL +#define pci_ss_list_131f_2081 NULL +#endif +#define pci_ss_list_1331_0030 NULL +#define pci_ss_list_1331_8200 NULL +#define pci_ss_list_1331_8201 NULL +#define pci_ss_list_1331_8202 NULL +#define pci_ss_list_1331_8210 NULL +#define pci_ss_list_1332_5415 NULL +#define pci_ss_list_1332_5425 NULL +#define pci_ss_list_1332_6140 NULL +#define pci_ss_list_134a_0001 NULL +#define pci_ss_list_134a_0002 NULL +#define pci_ss_list_134d_2189 NULL +#define pci_ss_list_134d_2486 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_134d_7890[] = { + &pci_ss_info_134d_7890_134d_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_134d_7891[] = { + &pci_ss_info_134d_7891_134d_0001, + NULL +}; +#define pci_ss_list_134d_7892 NULL +#define pci_ss_list_134d_7893 NULL +#define pci_ss_list_134d_7894 NULL +#define pci_ss_list_134d_7895 NULL +#define pci_ss_list_134d_7896 NULL +#define pci_ss_list_134d_7897 NULL +#endif +#define pci_ss_list_1353_0002 NULL +#define pci_ss_list_1353_0003 NULL +#define pci_ss_list_1353_0004 NULL +#define pci_ss_list_1353_0005 NULL +#define pci_ss_list_135c_0010 NULL +#define pci_ss_list_135c_0020 NULL +#define pci_ss_list_135c_0030 NULL +#define pci_ss_list_135c_0040 NULL +#define pci_ss_list_135c_0050 NULL +#define pci_ss_list_135c_0060 NULL +#define pci_ss_list_135c_00f0 NULL +#define pci_ss_list_135c_0170 NULL +#define pci_ss_list_135c_0180 NULL +#define pci_ss_list_135c_0190 NULL +#define pci_ss_list_135c_01a0 NULL +#define pci_ss_list_135c_01b0 NULL +#define pci_ss_list_135c_01c0 NULL +#define pci_ss_list_135e_5101 NULL +#define pci_ss_list_135e_7101 NULL +#define pci_ss_list_135e_7201 NULL +#define pci_ss_list_135e_7202 NULL +#define pci_ss_list_135e_7401 NULL +#define pci_ss_list_135e_7402 NULL +#define pci_ss_list_135e_7801 NULL +#define pci_ss_list_135e_7804 NULL +#define pci_ss_list_135e_8001 NULL +#define pci_ss_list_1360_0101 NULL +#define pci_ss_list_1360_0102 NULL +#define pci_ss_list_1360_0103 NULL +#define pci_ss_list_1360_0104 NULL +#define pci_ss_list_1360_0201 NULL +#define pci_ss_list_1360_0202 NULL +#define pci_ss_list_1360_0203 NULL +#define pci_ss_list_1360_0204 NULL +#define pci_ss_list_1360_0301 NULL +#define pci_ss_list_1360_0302 NULL +#define pci_ss_list_1360_0303 NULL +#define pci_ss_list_136a_0004 NULL +#define pci_ss_list_136a_0007 NULL +#define pci_ss_list_136a_0008 NULL +#define pci_ss_list_136a_000a NULL +#define pci_ss_list_136b_ff01 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1371_434e[] = { + &pci_ss_info_1371_434e_1371_434e, + NULL +}; +#endif +#define pci_ss_list_1374_0024 NULL +#define pci_ss_list_1374_0025 NULL +#define pci_ss_list_1374_0026 NULL +#define pci_ss_list_1374_0027 NULL +#define pci_ss_list_1374_0029 NULL +#define pci_ss_list_1374_002a NULL +#define pci_ss_list_1374_002b NULL +#define pci_ss_list_1374_002c NULL +#define pci_ss_list_1374_002d NULL +#define pci_ss_list_1374_002e NULL +#define pci_ss_list_1374_002f NULL +#define pci_ss_list_1374_0030 NULL +#define pci_ss_list_1374_0031 NULL +#define pci_ss_list_1374_0032 NULL +#define pci_ss_list_1374_0034 NULL +#define pci_ss_list_1374_0035 NULL +#define pci_ss_list_1374_0036 NULL +#define pci_ss_list_1374_0037 NULL +#define pci_ss_list_1374_0038 NULL +#define pci_ss_list_1374_0039 NULL +#define pci_ss_list_1374_003a NULL +#define pci_ss_list_137a_0001 NULL +#define pci_ss_list_1382_0001 NULL +#define pci_ss_list_1382_2008 NULL +#define pci_ss_list_1382_2048 NULL +#define pci_ss_list_1382_2088 NULL +#define pci_ss_list_1382_20c8 NULL +#define pci_ss_list_1382_4008 NULL +#define pci_ss_list_1382_4010 NULL +#define pci_ss_list_1382_4048 NULL +#define pci_ss_list_1382_4088 NULL +#define pci_ss_list_1382_4248 NULL +#define pci_ss_list_1382_4424 NULL +#define pci_ss_list_1385_0013 NULL +#define pci_ss_list_1385_311a NULL +#define pci_ss_list_1385_4100 NULL +#define pci_ss_list_1385_4105 NULL +#define pci_ss_list_1385_4251 NULL +#define pci_ss_list_1385_4400 NULL +#define pci_ss_list_1385_4600 NULL +#define pci_ss_list_1385_4601 NULL +#define pci_ss_list_1385_4610 NULL +#define pci_ss_list_1385_4800 NULL +#define pci_ss_list_1385_4900 NULL +#define pci_ss_list_1385_4a00 NULL +#define pci_ss_list_1385_4b00 NULL +#define pci_ss_list_1385_4c00 NULL +#define pci_ss_list_1385_4d00 NULL +#define pci_ss_list_1385_4e00 NULL +#define pci_ss_list_1385_4f00 NULL +#define pci_ss_list_1385_5200 NULL +#define pci_ss_list_1385_620a NULL +#define pci_ss_list_1385_622a NULL +#define pci_ss_list_1385_630a NULL +#define pci_ss_list_1385_6b00 NULL +#define pci_ss_list_1385_6d00 NULL +#define pci_ss_list_1385_7b00 NULL +#define pci_ss_list_1385_7c00 NULL +#define pci_ss_list_1385_7d00 NULL +#define pci_ss_list_1385_7e00 NULL +#define pci_ss_list_1385_f004 NULL +#define pci_ss_list_1389_0001 NULL +#define pci_ss_list_1393_1040 NULL +#define pci_ss_list_1393_1141 NULL +#define pci_ss_list_1393_1680 NULL +#define pci_ss_list_1393_2040 NULL +#define pci_ss_list_1393_2180 NULL +#define pci_ss_list_1393_3200 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1394_0001[] = { + &pci_ss_info_1394_0001_1394_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1397_08b4[] = { + &pci_ss_info_1397_08b4_1397_b520, + &pci_ss_info_1397_08b4_1397_b540, + NULL +}; +#define pci_ss_list_1397_16b8 NULL +static const pciSubsystemInfo *pci_ss_list_1397_2bd0[] = { + &pci_ss_info_1397_2bd0_0675_1704, + &pci_ss_info_1397_2bd0_0675_1708, + &pci_ss_info_1397_2bd0_1397_2bd0, + &pci_ss_info_1397_2bd0_e4bf_1000, + NULL +}; +#endif +#define pci_ss_list_139a_0001 NULL +#define pci_ss_list_139a_0003 NULL +#define pci_ss_list_139a_0005 NULL +#define pci_ss_list_13a3_0005 NULL +#define pci_ss_list_13a3_0006 NULL +#define pci_ss_list_13a3_0007 NULL +#define pci_ss_list_13a3_0012 NULL +#define pci_ss_list_13a3_0014 NULL +#define pci_ss_list_13a3_0016 NULL +#define pci_ss_list_13a3_0017 NULL +#define pci_ss_list_13a3_0018 NULL +#define pci_ss_list_13a3_001d NULL +#define pci_ss_list_13a3_0020 NULL +#define pci_ss_list_13a3_0026 NULL +#define pci_ss_list_13a8_0152 NULL +#define pci_ss_list_13a8_0154 NULL +#define pci_ss_list_13a8_0158 NULL +#define pci_ss_list_13c0_0010 NULL +#define pci_ss_list_13c0_0020 NULL +#define pci_ss_list_13c0_0030 NULL +#define pci_ss_list_13c0_0210 NULL +#define pci_ss_list_13c1_1000 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13c1_1001[] = { + &pci_ss_info_13c1_1001_13c1_1001, + NULL +}; +#define pci_ss_list_13c1_1002 NULL +#define pci_ss_list_13c1_1003 NULL +#endif +#define pci_ss_list_13c2_000e NULL +#define pci_ss_list_13c6_0520 NULL +#define pci_ss_list_13c6_0620 NULL +#define pci_ss_list_13c6_0820 NULL +#define pci_ss_list_13d0_2103 NULL +#define pci_ss_list_13d0_2200 NULL +#define pci_ss_list_13d1_ab02 NULL +#define pci_ss_list_13d1_ab03 NULL +#define pci_ss_list_13d1_ab06 NULL +#define pci_ss_list_13d1_ab08 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13df_0001[] = { + &pci_ss_info_13df_0001_13df_0001, + NULL +}; +#endif +#define pci_ss_list_13ec_000a NULL +#define pci_ss_list_13f0_0200 NULL +#define pci_ss_list_13f0_0201 NULL +#define pci_ss_list_13f0_1023 NULL +#define pci_ss_list_13f4_1401 NULL +#define pci_ss_list_13f6_0011 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13f6_0100[] = { + &pci_ss_info_13f6_0100_13f6_ffff, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_13f6_0101[] = { + &pci_ss_info_13f6_0101_13f6_0101, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_13f6_0111[] = { + &pci_ss_info_13f6_0111_1019_0970, + &pci_ss_info_13f6_0111_1043_8035, + &pci_ss_info_13f6_0111_1043_8077, + &pci_ss_info_13f6_0111_1043_80e2, + &pci_ss_info_13f6_0111_13f6_0111, + &pci_ss_info_13f6_0111_1681_a000, + NULL +}; +#define pci_ss_list_13f6_0211 NULL +#endif +#define pci_ss_list_13fe_1240 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13fe_1600[] = { + &pci_ss_info_13fe_1600_1601_0002, + &pci_ss_info_13fe_1600_1602_0002, + &pci_ss_info_13fe_1600_1612_0004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_13fe_16ff[] = { + &pci_ss_info_13fe_16ff_1601_0000, + &pci_ss_info_13fe_16ff_1602_0000, + &pci_ss_info_13fe_16ff_1612_0000, + NULL +}; +#define pci_ss_list_13fe_1733 NULL +#define pci_ss_list_13fe_1752 NULL +#define pci_ss_list_13fe_1754 NULL +#define pci_ss_list_13fe_1756 NULL +#endif +#define pci_ss_list_1400_1401 NULL +#define pci_ss_list_1407_0100 NULL +#define pci_ss_list_1407_0101 NULL +#define pci_ss_list_1407_0102 NULL +#define pci_ss_list_1407_0110 NULL +#define pci_ss_list_1407_0111 NULL +#define pci_ss_list_1407_0120 NULL +#define pci_ss_list_1407_0121 NULL +#define pci_ss_list_1407_0180 NULL +#define pci_ss_list_1407_0181 NULL +#define pci_ss_list_1407_0200 NULL +#define pci_ss_list_1407_0201 NULL +#define pci_ss_list_1407_0202 NULL +#define pci_ss_list_1407_0220 NULL +#define pci_ss_list_1407_0221 NULL +#define pci_ss_list_1407_0500 NULL +#define pci_ss_list_1407_0600 NULL +#define pci_ss_list_1407_8000 NULL +#define pci_ss_list_1407_8001 NULL +#define pci_ss_list_1407_8002 NULL +#define pci_ss_list_1407_8003 NULL +#define pci_ss_list_1407_8800 NULL +#define pci_ss_list_1409_7168 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1412_1712[] = { + &pci_ss_info_1412_1712_1412_1712, + &pci_ss_info_1412_1712_1412_d630, + &pci_ss_info_1412_1712_1412_d631, + &pci_ss_info_1412_1712_1412_d632, + &pci_ss_info_1412_1712_1412_d633, + &pci_ss_info_1412_1712_1412_d634, + &pci_ss_info_1412_1712_1412_d635, + &pci_ss_info_1412_1712_1412_d637, + &pci_ss_info_1412_1712_1412_d638, + &pci_ss_info_1412_1712_1412_d63b, + &pci_ss_info_1412_1712_1412_d63c, + &pci_ss_info_1412_1712_1416_1712, + &pci_ss_info_1412_1712_153b_1115, + &pci_ss_info_1412_1712_153b_1125, + &pci_ss_info_1412_1712_153b_112b, + &pci_ss_info_1412_1712_153b_112c, + &pci_ss_info_1412_1712_153b_1130, + &pci_ss_info_1412_1712_153b_1138, + &pci_ss_info_1412_1712_153b_1151, + &pci_ss_info_1412_1712_16ce_1040, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1412_1724[] = { + &pci_ss_info_1412_1724_1412_1724, + &pci_ss_info_1412_1724_1412_3630, + &pci_ss_info_1412_1724_1412_3631, + &pci_ss_info_1412_1724_153b_1145, + &pci_ss_info_1412_1724_153b_1147, + &pci_ss_info_1412_1724_153b_1153, + &pci_ss_info_1412_1724_270f_f641, + &pci_ss_info_1412_1724_270f_f645, + NULL +}; +#endif +#define pci_ss_list_1415_8403 NULL +#define pci_ss_list_1415_9500 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1415_9501[] = { + &pci_ss_info_1415_9501_12c4_0201, + &pci_ss_info_1415_9501_12c4_0202, + &pci_ss_info_1415_9501_12c4_0203, + &pci_ss_info_1415_9501_12c4_0210, + &pci_ss_info_1415_9501_131f_2050, + &pci_ss_info_1415_9501_131f_2051, + &pci_ss_info_1415_9501_15ed_2000, + &pci_ss_info_1415_9501_15ed_2001, + NULL +}; +#define pci_ss_list_1415_950a NULL +#define pci_ss_list_1415_950b NULL +static const pciSubsystemInfo *pci_ss_list_1415_9510[] = { + &pci_ss_info_1415_9510_12c4_0200, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1415_9511[] = { + &pci_ss_info_1415_9511_12c4_0211, + &pci_ss_info_1415_9511_15ed_2000, + &pci_ss_info_1415_9511_15ed_2001, + NULL +}; +#define pci_ss_list_1415_9512 NULL +#define pci_ss_list_1415_9513 NULL +#define pci_ss_list_1415_9521 NULL +#define pci_ss_list_1415_9523 NULL +#endif +#define pci_ss_list_1420_8002 NULL +#define pci_ss_list_1420_8003 NULL +#define pci_ss_list_1425_000b NULL +#define pci_ss_list_142e_4020 NULL +#define pci_ss_list_142e_4337 NULL +#define pci_ss_list_1432_9130 NULL +#define pci_ss_list_1435_4520 NULL +#define pci_ss_list_1435_6020 NULL +#define pci_ss_list_1435_6030 NULL +#define pci_ss_list_1435_6420 NULL +#define pci_ss_list_1435_6430 NULL +#define pci_ss_list_1435_7520 NULL +#define pci_ss_list_1435_7820 NULL +#define pci_ss_list_144a_7296 NULL +#define pci_ss_list_144a_7432 NULL +#define pci_ss_list_144a_7433 NULL +#define pci_ss_list_144a_7434 NULL +#define pci_ss_list_144a_7841 NULL +#define pci_ss_list_144a_8133 NULL +#define pci_ss_list_144a_8164 NULL +#define pci_ss_list_144a_8554 NULL +#define pci_ss_list_144a_9111 NULL +#define pci_ss_list_144a_9113 NULL +#define pci_ss_list_144a_9114 NULL +#define pci_ss_list_144d_c00c NULL +#define pci_ss_list_1458_0c11 NULL +#define pci_ss_list_1458_e911 NULL +#define pci_ss_list_145f_0001 NULL +#define pci_ss_list_1461_f436 NULL +#define pci_ss_list_1462_5501 NULL +#define pci_ss_list_1462_6819 NULL +#define pci_ss_list_1462_6825 NULL +#define pci_ss_list_1462_6834 NULL +#define pci_ss_list_1462_7125 NULL +#define pci_ss_list_1462_8725 NULL +#define pci_ss_list_1462_9000 NULL +#define pci_ss_list_1462_9110 NULL +#define pci_ss_list_1462_9119 NULL +#define pci_ss_list_1462_9123 NULL +#define pci_ss_list_1462_9510 NULL +#define pci_ss_list_1462_9511 NULL +#define pci_ss_list_1462_9591 NULL +#define pci_ss_list_146c_1430 NULL +#define pci_ss_list_148d_1003 NULL +#define pci_ss_list_1497_1497 NULL +#define pci_ss_list_1498_0330 NULL +#define pci_ss_list_1498_0385 NULL +#define pci_ss_list_1498_21cc NULL +#define pci_ss_list_1498_21cd NULL +#define pci_ss_list_1498_30c8 NULL +#define pci_ss_list_149d_0001 NULL +#define pci_ss_list_14af_7102 NULL +#define pci_ss_list_14b3_0000 NULL +#define pci_ss_list_14b5_0200 NULL +#define pci_ss_list_14b5_0300 NULL +#define pci_ss_list_14b5_0400 NULL +#define pci_ss_list_14b5_0600 NULL +#define pci_ss_list_14b5_0800 NULL +#define pci_ss_list_14b5_0900 NULL +#define pci_ss_list_14b5_0a00 NULL +#define pci_ss_list_14b5_0b00 NULL +#define pci_ss_list_14b7_0001 NULL +#define pci_ss_list_14b9_0001 NULL +#define pci_ss_list_14b9_0340 NULL +#define pci_ss_list_14b9_0350 NULL +#define pci_ss_list_14b9_4500 NULL +#define pci_ss_list_14b9_4800 NULL +#define pci_ss_list_14b9_a504 NULL +#define pci_ss_list_14b9_a505 NULL +#define pci_ss_list_14b9_a506 NULL +#define pci_ss_list_14bc_d002 NULL +#define pci_ss_list_14bc_d00f NULL +#define pci_ss_list_14c1_0008 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14c1_8043[] = { + &pci_ss_info_14c1_8043_103c_1240, + NULL +}; +#endif +#define pci_ss_list_14d2_8001 NULL +#define pci_ss_list_14d2_8002 NULL +#define pci_ss_list_14d2_8010 NULL +#define pci_ss_list_14d2_8011 NULL +#define pci_ss_list_14d2_8020 NULL +#define pci_ss_list_14d2_8021 NULL +#define pci_ss_list_14d2_8040 NULL +#define pci_ss_list_14d2_8080 NULL +#define pci_ss_list_14d2_a000 NULL +#define pci_ss_list_14d2_a001 NULL +#define pci_ss_list_14d2_a003 NULL +#define pci_ss_list_14d2_a004 NULL +#define pci_ss_list_14d2_a005 NULL +#define pci_ss_list_14d2_e001 NULL +#define pci_ss_list_14d2_e010 NULL +#define pci_ss_list_14d2_e020 NULL +#define pci_ss_list_14d9_0010 NULL +#define pci_ss_list_14d9_9000 NULL +#define pci_ss_list_14db_2120 NULL +#define pci_ss_list_14db_2182 NULL +#define pci_ss_list_14dc_0000 NULL +#define pci_ss_list_14dc_0001 NULL +#define pci_ss_list_14dc_0002 NULL +#define pci_ss_list_14dc_0003 NULL +#define pci_ss_list_14dc_0004 NULL +#define pci_ss_list_14dc_0005 NULL +#define pci_ss_list_14dc_0006 NULL +#define pci_ss_list_14dc_0007 NULL +#define pci_ss_list_14dc_0008 NULL +#define pci_ss_list_14dc_0009 NULL +#define pci_ss_list_14dc_000a NULL +#define pci_ss_list_14dc_000b NULL +#define pci_ss_list_14e4_0800 NULL +#define pci_ss_list_14e4_0804 NULL +#define pci_ss_list_14e4_0805 NULL +#define pci_ss_list_14e4_0806 NULL +#define pci_ss_list_14e4_080b NULL +#define pci_ss_list_14e4_080f NULL +#define pci_ss_list_14e4_0811 NULL +#define pci_ss_list_14e4_0816 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14e4_1600[] = { + &pci_ss_info_14e4_1600_107b_5048, + NULL +}; +#define pci_ss_list_14e4_1601 NULL +static const pciSubsystemInfo *pci_ss_list_14e4_1644[] = { + &pci_ss_info_14e4_1644_1014_0277, + &pci_ss_info_14e4_1644_1028_00d1, + &pci_ss_info_14e4_1644_1028_0106, + &pci_ss_info_14e4_1644_1028_0109, + &pci_ss_info_14e4_1644_1028_010a, + &pci_ss_info_14e4_1644_10b7_1000, + &pci_ss_info_14e4_1644_10b7_1001, + &pci_ss_info_14e4_1644_10b7_1002, + &pci_ss_info_14e4_1644_10b7_1003, + &pci_ss_info_14e4_1644_10b7_1004, + &pci_ss_info_14e4_1644_10b7_1005, + &pci_ss_info_14e4_1644_10b7_1008, + &pci_ss_info_14e4_1644_14e4_0002, + &pci_ss_info_14e4_1644_14e4_0003, + &pci_ss_info_14e4_1644_14e4_0004, + &pci_ss_info_14e4_1644_14e4_1028, + &pci_ss_info_14e4_1644_14e4_1644, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1645[] = { + &pci_ss_info_14e4_1645_0e11_007c, + &pci_ss_info_14e4_1645_0e11_007d, + &pci_ss_info_14e4_1645_0e11_0085, + &pci_ss_info_14e4_1645_0e11_0099, + &pci_ss_info_14e4_1645_0e11_009a, + &pci_ss_info_14e4_1645_0e11_00c1, + &pci_ss_info_14e4_1645_1028_0121, + &pci_ss_info_14e4_1645_103c_128a, + &pci_ss_info_14e4_1645_103c_128b, + &pci_ss_info_14e4_1645_103c_12a4, + &pci_ss_info_14e4_1645_103c_12c1, + &pci_ss_info_14e4_1645_103c_1300, + &pci_ss_info_14e4_1645_10a9_8010, + &pci_ss_info_14e4_1645_10a9_8011, + &pci_ss_info_14e4_1645_10a9_8012, + &pci_ss_info_14e4_1645_10b7_1004, + &pci_ss_info_14e4_1645_10b7_1006, + &pci_ss_info_14e4_1645_10b7_1007, + &pci_ss_info_14e4_1645_10b7_1008, + &pci_ss_info_14e4_1645_14e4_0001, + &pci_ss_info_14e4_1645_14e4_0005, + &pci_ss_info_14e4_1645_14e4_0006, + &pci_ss_info_14e4_1645_14e4_0007, + &pci_ss_info_14e4_1645_14e4_0008, + &pci_ss_info_14e4_1645_14e4_8008, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1646[] = { + &pci_ss_info_14e4_1646_0e11_00bb, + &pci_ss_info_14e4_1646_1028_0126, + &pci_ss_info_14e4_1646_14e4_8009, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1647[] = { + &pci_ss_info_14e4_1647_0e11_0099, + &pci_ss_info_14e4_1647_0e11_009a, + &pci_ss_info_14e4_1647_10a9_8010, + &pci_ss_info_14e4_1647_14e4_0009, + &pci_ss_info_14e4_1647_14e4_000a, + &pci_ss_info_14e4_1647_14e4_000b, + &pci_ss_info_14e4_1647_14e4_8009, + &pci_ss_info_14e4_1647_14e4_800a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1648[] = { + &pci_ss_info_14e4_1648_0e11_00cf, + &pci_ss_info_14e4_1648_0e11_00d0, + &pci_ss_info_14e4_1648_0e11_00d1, + &pci_ss_info_14e4_1648_10a9_8013, + &pci_ss_info_14e4_1648_10a9_8018, + &pci_ss_info_14e4_1648_10a9_801a, + &pci_ss_info_14e4_1648_10a9_801b, + &pci_ss_info_14e4_1648_10b7_2000, + &pci_ss_info_14e4_1648_10b7_3000, + &pci_ss_info_14e4_1648_1166_1648, + &pci_ss_info_14e4_1648_1734_100b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_164a[] = { + &pci_ss_info_14e4_164a_103c_3070, + &pci_ss_info_14e4_164a_103c_3101, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_164c[] = { + &pci_ss_info_14e4_164c_103c_7037, + &pci_ss_info_14e4_164c_103c_7038, + NULL +}; +#define pci_ss_list_14e4_164d NULL +static const pciSubsystemInfo *pci_ss_list_14e4_1653[] = { + &pci_ss_info_14e4_1653_0e11_00e3, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1654[] = { + &pci_ss_info_14e4_1654_0e11_00e3, + &pci_ss_info_14e4_1654_103c_3100, + &pci_ss_info_14e4_1654_103c_3226, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1659[] = { + &pci_ss_info_14e4_1659_1014_02c6, + &pci_ss_info_14e4_1659_103c_7031, + &pci_ss_info_14e4_1659_103c_7032, + &pci_ss_info_14e4_1659_1734_1061, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_165d[] = { + &pci_ss_info_14e4_165d_1028_865d, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_165e[] = { + &pci_ss_info_14e4_165e_103c_088c, + &pci_ss_info_14e4_165e_103c_0890, + &pci_ss_info_14e4_165e_103c_099c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_1668[] = { + &pci_ss_info_14e4_1668_103c_7039, + NULL +}; +#define pci_ss_list_14e4_1669 NULL +#define pci_ss_list_14e4_166a NULL +#define pci_ss_list_14e4_166b NULL +#define pci_ss_list_14e4_166e NULL +#define pci_ss_list_14e4_1672 NULL +#define pci_ss_list_14e4_1673 NULL +static const pciSubsystemInfo *pci_ss_list_14e4_1677[] = { + &pci_ss_info_14e4_1677_1028_0179, + &pci_ss_info_14e4_1677_1028_0182, + &pci_ss_info_14e4_1677_1028_0187, + &pci_ss_info_14e4_1677_1028_01ad, + &pci_ss_info_14e4_1677_103c_3006, + &pci_ss_info_14e4_1677_1734_105d, + NULL +}; +#define pci_ss_list_14e4_1678 NULL +static const pciSubsystemInfo *pci_ss_list_14e4_1679[] = { + &pci_ss_info_14e4_1679_103c_1707, + &pci_ss_info_14e4_1679_103c_170c, + &pci_ss_info_14e4_1679_103c_703c, + NULL +}; +#define pci_ss_list_14e4_167a NULL +#define pci_ss_list_14e4_167b NULL +static const pciSubsystemInfo *pci_ss_list_14e4_167d[] = { + &pci_ss_info_14e4_167d_17aa_2081, + NULL +}; +#define pci_ss_list_14e4_167e NULL +#define pci_ss_list_14e4_1693 NULL +static const pciSubsystemInfo *pci_ss_list_14e4_1696[] = { + &pci_ss_info_14e4_1696_103c_12bc, + &pci_ss_info_14e4_1696_14e4_000d, + NULL +}; +#define pci_ss_list_14e4_169a NULL +#define pci_ss_list_14e4_169b NULL +static const pciSubsystemInfo *pci_ss_list_14e4_169c[] = { + &pci_ss_info_14e4_169c_103c_308b, + NULL +}; +#define pci_ss_list_14e4_169d NULL +static const pciSubsystemInfo *pci_ss_list_14e4_16a6[] = { + &pci_ss_info_14e4_16a6_0e11_00bb, + &pci_ss_info_14e4_16a6_1028_0126, + &pci_ss_info_14e4_16a6_14e4_000c, + &pci_ss_info_14e4_16a6_14e4_8009, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_16a7[] = { + &pci_ss_info_14e4_16a7_0e11_00ca, + &pci_ss_info_14e4_16a7_0e11_00cb, + &pci_ss_info_14e4_16a7_14e4_0009, + &pci_ss_info_14e4_16a7_14e4_000a, + &pci_ss_info_14e4_16a7_14e4_000b, + &pci_ss_info_14e4_16a7_14e4_800a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_16a8[] = { + &pci_ss_info_14e4_16a8_10a9_8014, + &pci_ss_info_14e4_16a8_10a9_801c, + &pci_ss_info_14e4_16a8_10b7_2001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_16aa[] = { + &pci_ss_info_14e4_16aa_103c_3102, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_16ac[] = { + &pci_ss_info_14e4_16ac_103c_1706, + &pci_ss_info_14e4_16ac_103c_703b, + &pci_ss_info_14e4_16ac_103c_703d, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_16c6[] = { + &pci_ss_info_14e4_16c6_10b7_1100, + &pci_ss_info_14e4_16c6_14e4_000c, + &pci_ss_info_14e4_16c6_14e4_8009, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_16c7[] = { + &pci_ss_info_14e4_16c7_0e11_00ca, + &pci_ss_info_14e4_16c7_0e11_00cb, + &pci_ss_info_14e4_16c7_103c_12c3, + &pci_ss_info_14e4_16c7_103c_12ca, + &pci_ss_info_14e4_16c7_14e4_0009, + &pci_ss_info_14e4_16c7_14e4_000a, + NULL +}; +#define pci_ss_list_14e4_16dd NULL +#define pci_ss_list_14e4_16f7 NULL +#define pci_ss_list_14e4_16fd NULL +#define pci_ss_list_14e4_16fe NULL +static const pciSubsystemInfo *pci_ss_list_14e4_170c[] = { + &pci_ss_info_14e4_170c_1028_0188, + &pci_ss_info_14e4_170c_1028_0196, + &pci_ss_info_14e4_170c_103c_099c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_170d[] = { + &pci_ss_info_14e4_170d_1014_0545, + NULL +}; +#define pci_ss_list_14e4_170e NULL +#define pci_ss_list_14e4_3352 NULL +#define pci_ss_list_14e4_3360 NULL +#define pci_ss_list_14e4_4210 NULL +#define pci_ss_list_14e4_4211 NULL +#define pci_ss_list_14e4_4212 NULL +static const pciSubsystemInfo *pci_ss_list_14e4_4301[] = { + &pci_ss_info_14e4_4301_1028_0407, + &pci_ss_info_14e4_4301_1043_0120, + NULL +}; +#define pci_ss_list_14e4_4305 NULL +#define pci_ss_list_14e4_4306 NULL +#define pci_ss_list_14e4_4307 NULL +#define pci_ss_list_14e4_4310 NULL +#define pci_ss_list_14e4_4311 NULL +#define pci_ss_list_14e4_4312 NULL +#define pci_ss_list_14e4_4313 NULL +#define pci_ss_list_14e4_4315 NULL +static const pciSubsystemInfo *pci_ss_list_14e4_4318[] = { + &pci_ss_info_14e4_4318_103c_1356, + &pci_ss_info_14e4_4318_1043_120f, + &pci_ss_info_14e4_4318_1468_0311, + &pci_ss_info_14e4_4318_1468_0312, + &pci_ss_info_14e4_4318_14e4_0449, + &pci_ss_info_14e4_4318_14e4_4318, + &pci_ss_info_14e4_4318_16ec_0119, + &pci_ss_info_14e4_4318_1737_0048, + NULL +}; +#define pci_ss_list_14e4_4319 NULL +static const pciSubsystemInfo *pci_ss_list_14e4_4320[] = { + &pci_ss_info_14e4_4320_1028_0001, + &pci_ss_info_14e4_4320_1028_0003, + &pci_ss_info_14e4_4320_103c_12f4, + &pci_ss_info_14e4_4320_103c_12fa, + &pci_ss_info_14e4_4320_1043_100f, + &pci_ss_info_14e4_4320_1057_7025, + &pci_ss_info_14e4_4320_106b_004e, + &pci_ss_info_14e4_4320_1154_0330, + &pci_ss_info_14e4_4320_144f_7050, + &pci_ss_info_14e4_4320_14e4_4320, + &pci_ss_info_14e4_4320_1737_4320, + &pci_ss_info_14e4_4320_1799_7001, + &pci_ss_info_14e4_4320_1799_7010, + &pci_ss_info_14e4_4320_1799_7011, + &pci_ss_info_14e4_4320_185f_1220, + NULL +}; +#define pci_ss_list_14e4_4321 NULL +#define pci_ss_list_14e4_4322 NULL +static const pciSubsystemInfo *pci_ss_list_14e4_4324[] = { + &pci_ss_info_14e4_4324_1028_0001, + &pci_ss_info_14e4_4324_1028_0003, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14e4_4325[] = { + &pci_ss_info_14e4_4325_1414_0003, + &pci_ss_info_14e4_4325_1414_0004, + NULL +}; +#define pci_ss_list_14e4_4326 NULL +#define pci_ss_list_14e4_4329 NULL +static const pciSubsystemInfo *pci_ss_list_14e4_4401[] = { + &pci_ss_info_14e4_4401_103c_08b0, + &pci_ss_info_14e4_4401_1043_80a8, + NULL +}; +#define pci_ss_list_14e4_4402 NULL +#define pci_ss_list_14e4_4403 NULL +#define pci_ss_list_14e4_4410 NULL +#define pci_ss_list_14e4_4411 NULL +#define pci_ss_list_14e4_4412 NULL +#define pci_ss_list_14e4_4430 NULL +#define pci_ss_list_14e4_4432 NULL +#define pci_ss_list_14e4_4610 NULL +#define pci_ss_list_14e4_4611 NULL +#define pci_ss_list_14e4_4612 NULL +#define pci_ss_list_14e4_4613 NULL +#define pci_ss_list_14e4_4614 NULL +#define pci_ss_list_14e4_4615 NULL +#define pci_ss_list_14e4_4704 NULL +#define pci_ss_list_14e4_4705 NULL +#define pci_ss_list_14e4_4706 NULL +#define pci_ss_list_14e4_4707 NULL +#define pci_ss_list_14e4_4708 NULL +#define pci_ss_list_14e4_4710 NULL +#define pci_ss_list_14e4_4711 NULL +#define pci_ss_list_14e4_4712 NULL +#define pci_ss_list_14e4_4713 NULL +#define pci_ss_list_14e4_4714 NULL +#define pci_ss_list_14e4_4715 NULL +#define pci_ss_list_14e4_4716 NULL +#define pci_ss_list_14e4_4717 NULL +#define pci_ss_list_14e4_4718 NULL +#define pci_ss_list_14e4_4719 NULL +#define pci_ss_list_14e4_4720 NULL +#define pci_ss_list_14e4_5365 NULL +#define pci_ss_list_14e4_5600 NULL +#define pci_ss_list_14e4_5605 NULL +#define pci_ss_list_14e4_5615 NULL +#define pci_ss_list_14e4_5625 NULL +#define pci_ss_list_14e4_5645 NULL +#define pci_ss_list_14e4_5670 NULL +#define pci_ss_list_14e4_5680 NULL +#define pci_ss_list_14e4_5690 NULL +#define pci_ss_list_14e4_5691 NULL +#define pci_ss_list_14e4_5692 NULL +#define pci_ss_list_14e4_5820 NULL +#define pci_ss_list_14e4_5821 NULL +#define pci_ss_list_14e4_5822 NULL +#define pci_ss_list_14e4_5823 NULL +#define pci_ss_list_14e4_5824 NULL +#define pci_ss_list_14e4_5840 NULL +#define pci_ss_list_14e4_5841 NULL +#define pci_ss_list_14e4_5850 NULL +#endif +#define pci_ss_list_14ea_ab06 NULL +#define pci_ss_list_14ea_ab07 NULL +#define pci_ss_list_14ea_ab08 NULL +#define pci_ss_list_14f1_1002 NULL +#define pci_ss_list_14f1_1003 NULL +#define pci_ss_list_14f1_1004 NULL +#define pci_ss_list_14f1_1005 NULL +#define pci_ss_list_14f1_1006 NULL +#define pci_ss_list_14f1_1022 NULL +#define pci_ss_list_14f1_1023 NULL +#define pci_ss_list_14f1_1024 NULL +#define pci_ss_list_14f1_1025 NULL +#define pci_ss_list_14f1_1026 NULL +#define pci_ss_list_14f1_1032 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14f1_1033[] = { + &pci_ss_info_14f1_1033_1033_8077, + &pci_ss_info_14f1_1033_122d_4027, + &pci_ss_info_14f1_1033_122d_4030, + &pci_ss_info_14f1_1033_122d_4034, + &pci_ss_info_14f1_1033_13e0_020d, + &pci_ss_info_14f1_1033_13e0_020e, + &pci_ss_info_14f1_1033_13e0_0261, + &pci_ss_info_14f1_1033_13e0_0290, + &pci_ss_info_14f1_1033_13e0_02a0, + &pci_ss_info_14f1_1033_13e0_02b0, + &pci_ss_info_14f1_1033_13e0_02c0, + &pci_ss_info_14f1_1033_13e0_02d0, + &pci_ss_info_14f1_1033_144f_1500, + &pci_ss_info_14f1_1033_144f_1501, + &pci_ss_info_14f1_1033_144f_150a, + &pci_ss_info_14f1_1033_144f_150b, + &pci_ss_info_14f1_1033_144f_1510, + NULL +}; +#define pci_ss_list_14f1_1034 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1035[] = { + &pci_ss_info_14f1_1035_10cf_1098, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14f1_1036[] = { + &pci_ss_info_14f1_1036_104d_8067, + &pci_ss_info_14f1_1036_122d_4029, + &pci_ss_info_14f1_1036_122d_4031, + &pci_ss_info_14f1_1036_13e0_0209, + &pci_ss_info_14f1_1036_13e0_020a, + &pci_ss_info_14f1_1036_13e0_0260, + &pci_ss_info_14f1_1036_13e0_0270, + NULL +}; +#define pci_ss_list_14f1_1052 NULL +#define pci_ss_list_14f1_1053 NULL +#define pci_ss_list_14f1_1054 NULL +#define pci_ss_list_14f1_1055 NULL +#define pci_ss_list_14f1_1056 NULL +#define pci_ss_list_14f1_1057 NULL +#define pci_ss_list_14f1_1059 NULL +#define pci_ss_list_14f1_1063 NULL +#define pci_ss_list_14f1_1064 NULL +#define pci_ss_list_14f1_1065 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1066[] = { + &pci_ss_info_14f1_1066_122d_4033, + NULL +}; +#define pci_ss_list_14f1_1085 NULL +#define pci_ss_list_14f1_1433 NULL +#define pci_ss_list_14f1_1434 NULL +#define pci_ss_list_14f1_1435 NULL +#define pci_ss_list_14f1_1436 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1453[] = { + &pci_ss_info_14f1_1453_13e0_0240, + &pci_ss_info_14f1_1453_13e0_0250, + &pci_ss_info_14f1_1453_144f_1502, + &pci_ss_info_14f1_1453_144f_1503, + NULL +}; +#define pci_ss_list_14f1_1454 NULL +#define pci_ss_list_14f1_1455 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1456[] = { + &pci_ss_info_14f1_1456_122d_4035, + &pci_ss_info_14f1_1456_122d_4302, + NULL +}; +#define pci_ss_list_14f1_1610 NULL +#define pci_ss_list_14f1_1611 NULL +#define pci_ss_list_14f1_1620 NULL +#define pci_ss_list_14f1_1621 NULL +#define pci_ss_list_14f1_1622 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1803[] = { + &pci_ss_info_14f1_1803_0e11_0023, + &pci_ss_info_14f1_1803_0e11_0043, + NULL +}; +#define pci_ss_list_14f1_1811 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_1815[] = { + &pci_ss_info_14f1_1815_0e11_0022, + &pci_ss_info_14f1_1815_0e11_0042, + NULL +}; +#define pci_ss_list_14f1_2003 NULL +#define pci_ss_list_14f1_2004 NULL +#define pci_ss_list_14f1_2005 NULL +#define pci_ss_list_14f1_2006 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_2013[] = { + &pci_ss_info_14f1_2013_0e11_b195, + &pci_ss_info_14f1_2013_0e11_b196, + &pci_ss_info_14f1_2013_0e11_b1be, + &pci_ss_info_14f1_2013_1025_8013, + &pci_ss_info_14f1_2013_1033_809d, + &pci_ss_info_14f1_2013_1033_80bc, + &pci_ss_info_14f1_2013_155d_6793, + &pci_ss_info_14f1_2013_155d_8850, + NULL +}; +#define pci_ss_list_14f1_2014 NULL +#define pci_ss_list_14f1_2015 NULL +#define pci_ss_list_14f1_2016 NULL +#define pci_ss_list_14f1_2043 NULL +#define pci_ss_list_14f1_2044 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_2045[] = { + &pci_ss_info_14f1_2045_14f1_2045, + NULL +}; +#define pci_ss_list_14f1_2046 NULL +#define pci_ss_list_14f1_2063 NULL +#define pci_ss_list_14f1_2064 NULL +#define pci_ss_list_14f1_2065 NULL +#define pci_ss_list_14f1_2066 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_2093[] = { + &pci_ss_info_14f1_2093_155d_2f07, + NULL +}; +#define pci_ss_list_14f1_2143 NULL +#define pci_ss_list_14f1_2144 NULL +#define pci_ss_list_14f1_2145 NULL +#define pci_ss_list_14f1_2146 NULL +#define pci_ss_list_14f1_2163 NULL +#define pci_ss_list_14f1_2164 NULL +#define pci_ss_list_14f1_2165 NULL +#define pci_ss_list_14f1_2166 NULL +#define pci_ss_list_14f1_2343 NULL +#define pci_ss_list_14f1_2344 NULL +#define pci_ss_list_14f1_2345 NULL +#define pci_ss_list_14f1_2346 NULL +#define pci_ss_list_14f1_2363 NULL +#define pci_ss_list_14f1_2364 NULL +#define pci_ss_list_14f1_2365 NULL +#define pci_ss_list_14f1_2366 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_2443[] = { + &pci_ss_info_14f1_2443_104d_8075, + &pci_ss_info_14f1_2443_104d_8083, + &pci_ss_info_14f1_2443_104d_8097, + NULL +}; +#define pci_ss_list_14f1_2444 NULL +#define pci_ss_list_14f1_2445 NULL +#define pci_ss_list_14f1_2446 NULL +#define pci_ss_list_14f1_2463 NULL +#define pci_ss_list_14f1_2464 NULL +#define pci_ss_list_14f1_2465 NULL +#define pci_ss_list_14f1_2466 NULL +#define pci_ss_list_14f1_2bfa NULL +static const pciSubsystemInfo *pci_ss_list_14f1_2f00[] = { + &pci_ss_info_14f1_2f00_13e0_8d84, + &pci_ss_info_14f1_2f00_13e0_8d85, + &pci_ss_info_14f1_2f00_14f1_2004, + NULL +}; +#define pci_ss_list_14f1_2f02 NULL +#define pci_ss_list_14f1_2f11 NULL +#define pci_ss_list_14f1_2f20 NULL +#define pci_ss_list_14f1_8234 NULL +static const pciSubsystemInfo *pci_ss_list_14f1_8800[] = { + &pci_ss_info_14f1_8800_0070_2801, + &pci_ss_info_14f1_8800_0070_3401, + &pci_ss_info_14f1_8800_0070_9001, + &pci_ss_info_14f1_8800_0070_9200, + &pci_ss_info_14f1_8800_0070_9202, + &pci_ss_info_14f1_8800_0070_9402, + &pci_ss_info_14f1_8800_0070_9802, + &pci_ss_info_14f1_8800_1002_00f8, + &pci_ss_info_14f1_8800_1002_a101, + &pci_ss_info_14f1_8800_1043_4823, + &pci_ss_info_14f1_8800_107d_6613, + &pci_ss_info_14f1_8800_107d_6620, + &pci_ss_info_14f1_8800_107d_663c, + &pci_ss_info_14f1_8800_107d_665f, + &pci_ss_info_14f1_8800_10fc_d003, + &pci_ss_info_14f1_8800_10fc_d035, + &pci_ss_info_14f1_8800_1421_0334, + &pci_ss_info_14f1_8800_1461_000a, + &pci_ss_info_14f1_8800_1461_000b, + &pci_ss_info_14f1_8800_1461_8011, + &pci_ss_info_14f1_8800_1462_8606, + &pci_ss_info_14f1_8800_14c7_0107, + &pci_ss_info_14f1_8800_14f1_0187, + &pci_ss_info_14f1_8800_14f1_0342, + &pci_ss_info_14f1_8800_153b_1166, + &pci_ss_info_14f1_8800_1540_2580, + &pci_ss_info_14f1_8800_1554_4811, + &pci_ss_info_14f1_8800_1554_4813, + &pci_ss_info_14f1_8800_17de_08a1, + &pci_ss_info_14f1_8800_17de_08a6, + &pci_ss_info_14f1_8800_17de_08b2, + &pci_ss_info_14f1_8800_17de_a8a6, + &pci_ss_info_14f1_8800_1822_0025, + &pci_ss_info_14f1_8800_18ac_d500, + &pci_ss_info_14f1_8800_18ac_d810, + &pci_ss_info_14f1_8800_18ac_d820, + &pci_ss_info_14f1_8800_18ac_db00, + &pci_ss_info_14f1_8800_18ac_db11, + &pci_ss_info_14f1_8800_18ac_db50, + &pci_ss_info_14f1_8800_7063_3000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14f1_8801[] = { + &pci_ss_info_14f1_8801_0070_2801, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14f1_8802[] = { + &pci_ss_info_14f1_8802_0070_2801, + &pci_ss_info_14f1_8802_0070_9002, + &pci_ss_info_14f1_8802_1043_4823, + &pci_ss_info_14f1_8802_107d_663c, + &pci_ss_info_14f1_8802_14f1_0187, + &pci_ss_info_14f1_8802_17de_08a1, + &pci_ss_info_14f1_8802_17de_08a6, + &pci_ss_info_14f1_8802_18ac_d500, + &pci_ss_info_14f1_8802_18ac_d810, + &pci_ss_info_14f1_8802_18ac_d820, + &pci_ss_info_14f1_8802_18ac_db00, + &pci_ss_info_14f1_8802_18ac_db10, + &pci_ss_info_14f1_8802_7063_3000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14f1_8804[] = { + &pci_ss_info_14f1_8804_0070_9002, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_14f1_8811[] = { + &pci_ss_info_14f1_8811_0070_3401, + &pci_ss_info_14f1_8811_1462_8606, + &pci_ss_info_14f1_8811_18ac_d500, + &pci_ss_info_14f1_8811_18ac_d810, + &pci_ss_info_14f1_8811_18ac_d820, + &pci_ss_info_14f1_8811_18ac_db00, + NULL +}; +#endif +#define pci_ss_list_14f2_0120 NULL +#define pci_ss_list_14f2_0121 NULL +#define pci_ss_list_14f2_0122 NULL +#define pci_ss_list_14f2_0123 NULL +#define pci_ss_list_14f2_0124 NULL +#define pci_ss_list_14f3_2030 NULL +#define pci_ss_list_14f3_2050 NULL +#define pci_ss_list_14f3_2060 NULL +#define pci_ss_list_14f8_2077 NULL +#define pci_ss_list_14fc_0000 NULL +#define pci_ss_list_14fc_0001 NULL +#define pci_ss_list_14fc_0002 NULL +#define pci_ss_list_1500_1360 NULL +#define pci_ss_list_1507_0001 NULL +#define pci_ss_list_1507_0002 NULL +#define pci_ss_list_1507_0003 NULL +#define pci_ss_list_1507_0100 NULL +#define pci_ss_list_1507_0431 NULL +#define pci_ss_list_1507_4801 NULL +#define pci_ss_list_1507_4802 NULL +#define pci_ss_list_1507_4803 NULL +#define pci_ss_list_1507_4806 NULL +#define pci_ss_list_1516_0800 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1516_0803[] = { + &pci_ss_info_1516_0803_1320_10bd, + NULL +}; +#define pci_ss_list_1516_0891 NULL +#endif +#define pci_ss_list_151a_1002 NULL +#define pci_ss_list_151a_1004 NULL +#define pci_ss_list_151a_1008 NULL +#define pci_ss_list_151c_0003 NULL +#define pci_ss_list_151c_4000 NULL +#define pci_ss_list_151f_0000 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1522_0100[] = { + &pci_ss_info_1522_0100_1522_0200, + &pci_ss_info_1522_0100_1522_0300, + &pci_ss_info_1522_0100_1522_0400, + &pci_ss_info_1522_0100_1522_0500, + &pci_ss_info_1522_0100_1522_0600, + &pci_ss_info_1522_0100_1522_0700, + &pci_ss_info_1522_0100_1522_0800, + &pci_ss_info_1522_0100_1522_0c00, + &pci_ss_info_1522_0100_1522_0d00, + &pci_ss_info_1522_0100_1522_1d00, + &pci_ss_info_1522_0100_1522_2000, + &pci_ss_info_1522_0100_1522_2100, + &pci_ss_info_1522_0100_1522_2200, + &pci_ss_info_1522_0100_1522_2300, + &pci_ss_info_1522_0100_1522_2400, + &pci_ss_info_1522_0100_1522_2500, + &pci_ss_info_1522_0100_1522_2600, + &pci_ss_info_1522_0100_1522_2700, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1524_0510[] = { + &pci_ss_info_1524_0510_103c_006a, + NULL +}; +#define pci_ss_list_1524_0520 NULL +#define pci_ss_list_1524_0530 NULL +#define pci_ss_list_1524_0550 NULL +#define pci_ss_list_1524_0610 NULL +#define pci_ss_list_1524_1211 NULL +#define pci_ss_list_1524_1225 NULL +static const pciSubsystemInfo *pci_ss_list_1524_1410[] = { + &pci_ss_info_1524_1410_1025_003c, + &pci_ss_info_1524_1410_1025_005a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1524_1411[] = { + &pci_ss_info_1524_1411_103c_006a, + NULL +}; +#define pci_ss_list_1524_1412 NULL +#define pci_ss_list_1524_1420 NULL +#define pci_ss_list_1524_1421 NULL +#define pci_ss_list_1524_1422 NULL +#endif +#define pci_ss_list_1532_0020 NULL +#define pci_ss_list_1538_0303 NULL +#define pci_ss_list_153b_1144 NULL +#define pci_ss_list_153b_1147 NULL +#define pci_ss_list_153b_1158 NULL +#define pci_ss_list_153f_0001 NULL +#define pci_ss_list_1542_9260 NULL +#define pci_ss_list_1543_3052 NULL +#define pci_ss_list_1543_4c22 NULL +#define pci_ss_list_1571_a001 NULL +#define pci_ss_list_1571_a002 NULL +#define pci_ss_list_1571_a003 NULL +#define pci_ss_list_1571_a004 NULL +#define pci_ss_list_1571_a005 NULL +#define pci_ss_list_1571_a006 NULL +#define pci_ss_list_1571_a007 NULL +#define pci_ss_list_1571_a008 NULL +#define pci_ss_list_1571_a009 NULL +#define pci_ss_list_1571_a00a NULL +#define pci_ss_list_1571_a00b NULL +#define pci_ss_list_1571_a00c NULL +#define pci_ss_list_1571_a00d NULL +#define pci_ss_list_1571_a201 NULL +#define pci_ss_list_1571_a202 NULL +#define pci_ss_list_1571_a203 NULL +#define pci_ss_list_1571_a204 NULL +#define pci_ss_list_1571_a205 NULL +#define pci_ss_list_1571_a206 NULL +#define pci_ss_list_1578_5615 NULL +#define pci_ss_list_157c_8001 NULL +#define pci_ss_list_1592_0781 NULL +#define pci_ss_list_1592_0782 NULL +#define pci_ss_list_1592_0783 NULL +#define pci_ss_list_1592_0785 NULL +#define pci_ss_list_1592_0786 NULL +#define pci_ss_list_1592_0787 NULL +#define pci_ss_list_1592_0788 NULL +#define pci_ss_list_1592_078a NULL +#define pci_ss_list_15a2_0001 NULL +#define pci_ss_list_15ad_0405 NULL +#define pci_ss_list_15ad_0710 NULL +#define pci_ss_list_15ad_0720 NULL +#define pci_ss_list_15b3_5274 NULL +#define pci_ss_list_15b3_5a44 NULL +#define pci_ss_list_15b3_5a45 NULL +#define pci_ss_list_15b3_5a46 NULL +#define pci_ss_list_15b3_5e8d NULL +#define pci_ss_list_15b3_6274 NULL +#define pci_ss_list_15b3_6278 NULL +#define pci_ss_list_15b3_6279 NULL +#define pci_ss_list_15b3_6282 NULL +#define pci_ss_list_15bc_1100 NULL +#define pci_ss_list_15bc_2922 NULL +#define pci_ss_list_15bc_2928 NULL +#define pci_ss_list_15bc_2929 NULL +#define pci_ss_list_15c5_8010 NULL +#define pci_ss_list_15c7_0349 NULL +#define pci_ss_list_15dc_0001 NULL +#define pci_ss_list_15e8_0130 NULL +#define pci_ss_list_15e9_1841 NULL +#define pci_ss_list_15ec_3101 NULL +#define pci_ss_list_15ec_5102 NULL +#define pci_ss_list_1619_0400 NULL +#define pci_ss_list_1619_0440 NULL +#define pci_ss_list_1619_0610 NULL +#define pci_ss_list_1619_0620 NULL +#define pci_ss_list_1619_0640 NULL +#define pci_ss_list_1619_1610 NULL +#define pci_ss_list_1619_2610 NULL +#define pci_ss_list_1626_8410 NULL +#define pci_ss_list_1629_1003 NULL +#define pci_ss_list_1629_2002 NULL +#define pci_ss_list_1637_3874 NULL +#define pci_ss_list_1638_1100 NULL +#define pci_ss_list_163c_3052 NULL +#define pci_ss_list_163c_5449 NULL +#define pci_ss_list_165a_c100 NULL +#define pci_ss_list_165a_d200 NULL +#define pci_ss_list_165a_d300 NULL +#define pci_ss_list_165f_1020 NULL +#define pci_ss_list_1668_0100 NULL +#define pci_ss_list_166d_0001 NULL +#define pci_ss_list_166d_0002 NULL +#define pci_ss_list_1677_104e NULL +#define pci_ss_list_1677_12d7 NULL +#define pci_ss_list_1677_20ad NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_167b_2102[] = { + &pci_ss_info_167b_2102_187e_3406, + NULL +}; +#endif +#define pci_ss_list_167d_a000 NULL +#define pci_ss_list_1681_0010 NULL +#define pci_ss_list_1688_1170 NULL +#define pci_ss_list_168c_0007 NULL +#define pci_ss_list_168c_0011 NULL +#define pci_ss_list_168c_0012 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_168c_0013[] = { + &pci_ss_info_168c_0013_1113_d301, + &pci_ss_info_168c_0013_1186_3202, + &pci_ss_info_168c_0013_1186_3203, + &pci_ss_info_168c_0013_1186_3a12, + &pci_ss_info_168c_0013_1186_3a13, + &pci_ss_info_168c_0013_1186_3a14, + &pci_ss_info_168c_0013_1186_3a17, + &pci_ss_info_168c_0013_1186_3a18, + &pci_ss_info_168c_0013_1186_3a63, + &pci_ss_info_168c_0013_1186_3a93, + &pci_ss_info_168c_0013_1186_3a94, + &pci_ss_info_168c_0013_1186_3ab0, + &pci_ss_info_168c_0013_1385_4d00, + &pci_ss_info_168c_0013_1458_e911, + &pci_ss_info_168c_0013_14b7_0a60, + &pci_ss_info_168c_0013_1668_1026, + &pci_ss_info_168c_0013_168c_0013, + &pci_ss_info_168c_0013_168c_1025, + &pci_ss_info_168c_0013_168c_1027, + &pci_ss_info_168c_0013_168c_1042, + &pci_ss_info_168c_0013_168c_2026, + &pci_ss_info_168c_0013_168c_2041, + &pci_ss_info_168c_0013_168c_2042, + &pci_ss_info_168c_0013_168c_2051, + &pci_ss_info_168c_0013_16ab_7302, + &pci_ss_info_168c_0013_185f_2012, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_168c_001a[] = { + &pci_ss_info_168c_001a_1113_ee20, + &pci_ss_info_168c_001a_1113_ee24, + &pci_ss_info_168c_001a_1186_3a15, + &pci_ss_info_168c_001a_1186_3a16, + &pci_ss_info_168c_001a_1186_3a23, + &pci_ss_info_168c_001a_1186_3a24, + &pci_ss_info_168c_001a_168c_001a, + &pci_ss_info_168c_001a_168c_1052, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_168c_001b[] = { + &pci_ss_info_168c_001b_1186_3a19, + &pci_ss_info_168c_001b_1186_3a22, + &pci_ss_info_168c_001b_168c_2062, + &pci_ss_info_168c_001b_168c_2063, + NULL +}; +#define pci_ss_list_168c_0020 NULL +static const pciSubsystemInfo *pci_ss_list_168c_1014[] = { + &pci_ss_info_168c_1014_1014_058a, + NULL +}; +#endif +#define pci_ss_list_169c_0044 NULL +#define pci_ss_list_16ab_1100 NULL +#define pci_ss_list_16ab_1101 NULL +#define pci_ss_list_16ab_1102 NULL +#define pci_ss_list_16ab_8501 NULL +#define pci_ss_list_16ae_1141 NULL +#define pci_ss_list_16c6_8695 NULL +#define pci_ss_list_16ca_0001 NULL +#define pci_ss_list_16d5_4d4e NULL +#define pci_ss_list_16e3_1e0f NULL +#define pci_ss_list_16e5_6000 NULL +#define pci_ss_list_16ec_00ff NULL +#define pci_ss_list_16ec_0116 NULL +#define pci_ss_list_16ec_2f00 NULL +#define pci_ss_list_16ec_3685 NULL +#define pci_ss_list_16ed_1001 NULL +#define pci_ss_list_16f4_8000 NULL +#define pci_ss_list_170b_0100 NULL +#define pci_ss_list_1725_7174 NULL +#define pci_ss_list_172a_13c8 NULL +#define pci_ss_list_1734_1078 NULL +#define pci_ss_list_1737_0013 NULL +#define pci_ss_list_1737_0015 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1737_1032[] = { + &pci_ss_info_1737_1032_1737_0015, + &pci_ss_info_1737_1032_1737_0024, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1737_1064[] = { + &pci_ss_info_1737_1064_1737_0016, + NULL +}; +#define pci_ss_list_1737_ab08 NULL +#define pci_ss_list_1737_ab09 NULL +#endif +#define pci_ss_list_173b_03e8 NULL +#define pci_ss_list_173b_03e9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_173b_03ea[] = { + &pci_ss_info_173b_03ea_173b_0001, + NULL +}; +#define pci_ss_list_173b_03eb NULL +#endif +#define pci_ss_list_1743_8139 NULL +#define pci_ss_list_1796_0001 NULL +#define pci_ss_list_1796_0002 NULL +#define pci_ss_list_1796_0003 NULL +#define pci_ss_list_1796_0004 NULL +#define pci_ss_list_1796_0005 NULL +#define pci_ss_list_1796_0006 NULL +#define pci_ss_list_1799_6001 NULL +#define pci_ss_list_1799_6020 NULL +#define pci_ss_list_1799_6060 NULL +#define pci_ss_list_1799_7000 NULL +#define pci_ss_list_1799_700a NULL +#define pci_ss_list_1799_7010 NULL +#define pci_ss_list_179c_0557 NULL +#define pci_ss_list_179c_0566 NULL +#define pci_ss_list_179c_5031 NULL +#define pci_ss_list_179c_5121 NULL +#define pci_ss_list_179c_5211 NULL +#define pci_ss_list_179c_5679 NULL +#define pci_ss_list_17a0_8033 NULL +#define pci_ss_list_17a0_8034 NULL +#define pci_ss_list_17b3_ab08 NULL +#define pci_ss_list_17b4_0011 NULL +#define pci_ss_list_17cb_0001 NULL +#define pci_ss_list_17cb_0002 NULL +#define pci_ss_list_17cc_2280 NULL +#define pci_ss_list_17d3_1110 NULL +#define pci_ss_list_17d3_1120 NULL +#define pci_ss_list_17d3_1130 NULL +#define pci_ss_list_17d3_1160 NULL +#define pci_ss_list_17d3_1210 NULL +#define pci_ss_list_17d3_1220 NULL +#define pci_ss_list_17d3_1230 NULL +#define pci_ss_list_17d3_1260 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17d5_5831[] = { + &pci_ss_info_17d5_5831_103c_12d5, + &pci_ss_info_17d5_5831_10a9_8020, + &pci_ss_info_17d5_5831_10a9_8024, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_17d5_5832[] = { + &pci_ss_info_17d5_5832_10a9_8021, + NULL +}; +#endif +#define pci_ss_list_17e4_0001 NULL +#define pci_ss_list_17e4_0002 NULL +#define pci_ss_list_17e6_0010 NULL +#define pci_ss_list_17e6_0011 NULL +#define pci_ss_list_17e6_0021 NULL +#define pci_ss_list_17fe_2120 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17fe_2220[] = { + &pci_ss_info_17fe_2220_17fe_2220, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1813_4000[] = { + &pci_ss_info_1813_4000_16be_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1813_4100[] = { + &pci_ss_info_1813_4100_16be_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1814_0101[] = { + &pci_ss_info_1814_0101_1043_0127, + &pci_ss_info_1814_0101_1462_6828, + NULL +}; +#define pci_ss_list_1814_0200 NULL +static const pciSubsystemInfo *pci_ss_list_1814_0201[] = { + &pci_ss_info_1814_0201_1043_130f, + &pci_ss_info_1814_0201_1371_001e, + &pci_ss_info_1814_0201_1371_001f, + &pci_ss_info_1814_0201_1371_0020, + &pci_ss_info_1814_0201_1458_e381, + &pci_ss_info_1814_0201_1458_e931, + &pci_ss_info_1814_0201_1462_6835, + &pci_ss_info_1814_0201_1737_0032, + &pci_ss_info_1814_0201_1799_700a, + &pci_ss_info_1814_0201_1799_701a, + &pci_ss_info_1814_0201_185f_22a0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1814_0301[] = { + &pci_ss_info_1814_0301_1186_3c08, + &pci_ss_info_1814_0301_1186_3c09, + &pci_ss_info_1814_0301_1737_0055, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1814_0302[] = { + &pci_ss_info_1814_0302_1186_3c08, + &pci_ss_info_1814_0302_1186_3c09, + NULL +}; +#define pci_ss_list_1814_0401 NULL +#endif +#define pci_ss_list_1822_4e35 NULL +#define pci_ss_list_182d_3069 NULL +#define pci_ss_list_182d_9790 NULL +#define pci_ss_list_182e_0008 NULL +#define pci_ss_list_183b_08a7 NULL +#define pci_ss_list_183b_08a8 NULL +#define pci_ss_list_183b_08a9 NULL +#define pci_ss_list_183b_08b0 NULL +#define pci_ss_list_1864_2110 NULL +#define pci_ss_list_1867_5a44 NULL +#define pci_ss_list_1867_5a45 NULL +#define pci_ss_list_1867_5a46 NULL +#define pci_ss_list_1867_6278 NULL +#define pci_ss_list_1867_6282 NULL +#define pci_ss_list_187e_3403 NULL +#define pci_ss_list_187e_340e NULL +#define pci_ss_list_1888_0301 NULL +#define pci_ss_list_1888_0601 NULL +#define pci_ss_list_1888_0710 NULL +#define pci_ss_list_1888_0720 NULL +#define pci_ss_list_18ac_d500 NULL +#define pci_ss_list_18ac_d800 NULL +#define pci_ss_list_18ac_d810 NULL +#define pci_ss_list_18ac_d820 NULL +#define pci_ss_list_18b8_b001 NULL +#define pci_ss_list_18ca_0020 NULL +#define pci_ss_list_18ca_0040 NULL +#define pci_ss_list_18d2_3069 NULL +#define pci_ss_list_18dd_4c6f NULL +#define pci_ss_list_18e6_0001 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_18ec_c006[] = { + &pci_ss_info_18ec_c006_18ec_d001, + &pci_ss_info_18ec_c006_18ec_d002, + &pci_ss_info_18ec_c006_18ec_d003, + &pci_ss_info_18ec_c006_18ec_d004, + NULL +}; +#define pci_ss_list_18ec_c045 NULL +#define pci_ss_list_18ec_c050 NULL +static const pciSubsystemInfo *pci_ss_list_18ec_c058[] = { + &pci_ss_info_18ec_c058_18ec_d001, + &pci_ss_info_18ec_c058_18ec_d002, + &pci_ss_info_18ec_c058_18ec_d003, + &pci_ss_info_18ec_c058_18ec_d004, + NULL +}; +#endif +#define pci_ss_list_18f6_1000 NULL +#define pci_ss_list_18f6_1050 NULL +#define pci_ss_list_18f6_2000 NULL +#define pci_ss_list_18f7_0001 NULL +#define pci_ss_list_18f7_0002 NULL +#define pci_ss_list_18f7_0004 NULL +#define pci_ss_list_18f7_0005 NULL +#define pci_ss_list_18f7_000a NULL +#define pci_ss_list_1904_8139 NULL +#define pci_ss_list_1923_0040 NULL +#define pci_ss_list_1923_0100 NULL +#define pci_ss_list_1923_0300 NULL +#define pci_ss_list_1923_0400 NULL +#define pci_ss_list_1931_000c NULL +#define pci_ss_list_1942_e511 NULL +#define pci_ss_list_194a_1111 NULL +#define pci_ss_list_194a_1112 NULL +#define pci_ss_list_194a_1113 NULL +#define pci_ss_list_194a_1114 NULL +#define pci_ss_list_194a_1115 NULL +#define pci_ss_list_1957_0012 NULL +#define pci_ss_list_1957_0080 NULL +#define pci_ss_list_1957_0081 NULL +#define pci_ss_list_1957_0082 NULL +#define pci_ss_list_1957_0083 NULL +#define pci_ss_list_1957_0084 NULL +#define pci_ss_list_1957_0085 NULL +#define pci_ss_list_1957_0086 NULL +#define pci_ss_list_1957_0087 NULL +#define pci_ss_list_1966_1975 NULL +#define pci_ss_list_1969_1048 NULL +#define pci_ss_list_196a_0101 NULL +#define pci_ss_list_196a_0102 NULL +#define pci_ss_list_197b_2360 NULL +#define pci_ss_list_197b_2361 NULL +#define pci_ss_list_197b_2363 NULL +#define pci_ss_list_197b_2365 NULL +#define pci_ss_list_197b_2366 NULL +#define pci_ss_list_1989_0001 NULL +#define pci_ss_list_1989_8001 NULL +#define pci_ss_list_19ac_0001 NULL +#define pci_ss_list_19ae_0520 NULL +#define pci_ss_list_19e7_1001 NULL +#define pci_ss_list_19e7_1002 NULL +#define pci_ss_list_19e7_1003 NULL +#define pci_ss_list_19e7_1004 NULL +#define pci_ss_list_19e7_1005 NULL +#define pci_ss_list_1a03_2000 NULL +#define pci_ss_list_1a08_0000 NULL +#define pci_ss_list_1c1c_0001 NULL +#define pci_ss_list_1d44_a400 NULL +#define pci_ss_list_1de1_0391 NULL +#define pci_ss_list_1de1_2020 NULL +#define pci_ss_list_1de1_690c NULL +#define pci_ss_list_1de1_dc29 NULL +#define pci_ss_list_1fc0_0300 NULL +#define pci_ss_list_1fc1_000d NULL +#define pci_ss_list_1fc1_0010 NULL +#define pci_ss_list_1fce_0001 NULL +#define pci_ss_list_2348_2010 NULL +#define pci_ss_list_3388_0013 NULL +#define pci_ss_list_3388_0014 NULL +#define pci_ss_list_3388_0020 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_3388_0021[] = { + &pci_ss_info_3388_0021_1775_ce90, + &pci_ss_info_3388_0021_4c53_1050, + &pci_ss_info_3388_0021_4c53_1080, + &pci_ss_info_3388_0021_4c53_1090, + &pci_ss_info_3388_0021_4c53_10a0, + &pci_ss_info_3388_0021_4c53_3010, + &pci_ss_info_3388_0021_4c53_3011, + &pci_ss_info_3388_0021_4c53_4000, + NULL +}; +#define pci_ss_list_3388_0022 NULL +#define pci_ss_list_3388_0026 NULL +#define pci_ss_list_3388_101a NULL +#define pci_ss_list_3388_101b NULL +static const pciSubsystemInfo *pci_ss_list_3388_8011[] = { + &pci_ss_info_3388_8011_3388_8011, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3388_8012[] = { + &pci_ss_info_3388_8012_3388_8012, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3388_8013[] = { + &pci_ss_info_3388_8013_3388_8013, + NULL +}; +#endif +#define pci_ss_list_3842_c370 NULL +#define pci_ss_list_3d3d_0001 NULL +static const pciSubsystemInfo *pci_ss_list_3d3d_0002[] = { + &pci_ss_info_3d3d_0002_0000_0000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3d3d_0003[] = { + &pci_ss_info_3d3d_0003_0000_0000, + NULL +}; +#define pci_ss_list_3d3d_0004 NULL +#define pci_ss_list_3d3d_0005 NULL +static const pciSubsystemInfo *pci_ss_list_3d3d_0006[] = { + &pci_ss_info_3d3d_0006_0000_0000, + &pci_ss_info_3d3d_0006_1048_0a42, + NULL +}; +#define pci_ss_list_3d3d_0007 NULL +static const pciSubsystemInfo *pci_ss_list_3d3d_0008[] = { + &pci_ss_info_3d3d_0008_1048_0a42, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3d3d_0009[] = { + &pci_ss_info_3d3d_0009_1040_0011, + &pci_ss_info_3d3d_0009_1048_0a42, + &pci_ss_info_3d3d_0009_13e9_1000, + &pci_ss_info_3d3d_0009_3d3d_0100, + &pci_ss_info_3d3d_0009_3d3d_0111, + &pci_ss_info_3d3d_0009_3d3d_0114, + &pci_ss_info_3d3d_0009_3d3d_0116, + &pci_ss_info_3d3d_0009_3d3d_0119, + &pci_ss_info_3d3d_0009_3d3d_0120, + &pci_ss_info_3d3d_0009_3d3d_0125, + &pci_ss_info_3d3d_0009_3d3d_0127, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3d3d_000a[] = { + &pci_ss_info_3d3d_000a_3d3d_0121, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_3d3d_000c[] = { + &pci_ss_info_3d3d_000c_3d3d_0144, + NULL +}; +#define pci_ss_list_3d3d_000d NULL +#define pci_ss_list_3d3d_0011 NULL +#define pci_ss_list_3d3d_0012 NULL +#define pci_ss_list_3d3d_0013 NULL +#define pci_ss_list_3d3d_0020 NULL +#define pci_ss_list_3d3d_0022 NULL +#define pci_ss_list_3d3d_0024 NULL +#define pci_ss_list_3d3d_0100 NULL +#define pci_ss_list_3d3d_07a1 NULL +#define pci_ss_list_3d3d_07a2 NULL +#define pci_ss_list_3d3d_07a3 NULL +#define pci_ss_list_3d3d_1004 NULL +#define pci_ss_list_3d3d_3d04 NULL +#define pci_ss_list_3d3d_ffff NULL +#define pci_ss_list_4005_0300 NULL +#define pci_ss_list_4005_0308 NULL +#define pci_ss_list_4005_0309 NULL +#define pci_ss_list_4005_1064 NULL +#define pci_ss_list_4005_2064 NULL +#define pci_ss_list_4005_2128 NULL +#define pci_ss_list_4005_2301 NULL +#define pci_ss_list_4005_2302 NULL +#define pci_ss_list_4005_2303 NULL +#define pci_ss_list_4005_2364 NULL +#define pci_ss_list_4005_2464 NULL +#define pci_ss_list_4005_2501 NULL +static const pciSubsystemInfo *pci_ss_list_4005_4000[] = { + &pci_ss_info_4005_4000_4005_4000, + NULL +}; +#define pci_ss_list_4005_4710 NULL +#define pci_ss_list_4033_1360 NULL +#define pci_ss_list_4144_0044 NULL +#define pci_ss_list_416c_0100 NULL +#define pci_ss_list_416c_0200 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_4444_0016[] = { + &pci_ss_info_4444_0016_0070_0003, + &pci_ss_info_4444_0016_0070_0009, + &pci_ss_info_4444_0016_0070_0801, + &pci_ss_info_4444_0016_0070_0807, + &pci_ss_info_4444_0016_0070_4001, + &pci_ss_info_4444_0016_0070_4009, + &pci_ss_info_4444_0016_0070_4801, + &pci_ss_info_4444_0016_0070_4803, + &pci_ss_info_4444_0016_0070_8003, + &pci_ss_info_4444_0016_0070_8801, + &pci_ss_info_4444_0016_0070_c801, + &pci_ss_info_4444_0016_0070_e807, + &pci_ss_info_4444_0016_0070_e817, + &pci_ss_info_4444_0016_0070_ff92, + &pci_ss_info_4444_0016_0270_0801, + &pci_ss_info_4444_0016_10fc_d038, + &pci_ss_info_4444_0016_10fc_d039, + &pci_ss_info_4444_0016_12ab_fff3, + &pci_ss_info_4444_0016_12ab_ffff, + &pci_ss_info_4444_0016_1461_c019, + &pci_ss_info_4444_0016_9005_0092, + &pci_ss_info_4444_0016_9005_0093, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_4444_0803[] = { + &pci_ss_info_4444_0803_0070_4000, + &pci_ss_info_4444_0803_0070_4001, + &pci_ss_info_4444_0803_0070_4800, + &pci_ss_info_4444_0803_12ab_0000, + &pci_ss_info_4444_0803_1461_a3ce, + &pci_ss_info_4444_0803_1461_a3cf, + NULL +}; +#endif +#define pci_ss_list_4916_1960 NULL +#define pci_ss_list_494f_10e8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_4a14_5000[] = { + &pci_ss_info_4a14_5000_4a14_5000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_4c53_0000[] = { + &pci_ss_info_4c53_0000_4c53_3000, + &pci_ss_info_4c53_0000_4c53_3001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_4c53_0001[] = { + &pci_ss_info_4c53_0001_4c53_3002, + NULL +}; +#endif +#define pci_ss_list_4d51_0200 NULL +#define pci_ss_list_4ddc_0100 NULL +#define pci_ss_list_4ddc_0801 NULL +#define pci_ss_list_4ddc_0802 NULL +#define pci_ss_list_4ddc_0811 NULL +#define pci_ss_list_4ddc_0812 NULL +#define pci_ss_list_4ddc_0881 NULL +#define pci_ss_list_4ddc_0882 NULL +#define pci_ss_list_4ddc_0891 NULL +#define pci_ss_list_4ddc_0892 NULL +#define pci_ss_list_4ddc_0901 NULL +#define pci_ss_list_4ddc_0902 NULL +#define pci_ss_list_4ddc_0903 NULL +#define pci_ss_list_4ddc_0904 NULL +#define pci_ss_list_4ddc_0b01 NULL +#define pci_ss_list_4ddc_0b02 NULL +#define pci_ss_list_4ddc_0b03 NULL +#define pci_ss_list_4ddc_0b04 NULL +#define pci_ss_list_5046_1001 NULL +#define pci_ss_list_5053_2010 NULL +#define pci_ss_list_5145_3031 NULL +#define pci_ss_list_5168_0300 NULL +#define pci_ss_list_5168_0301 NULL +#define pci_ss_list_5301_0001 NULL +#define pci_ss_list_5333_0551 NULL +#define pci_ss_list_5333_5631 NULL +#define pci_ss_list_5333_8800 NULL +#define pci_ss_list_5333_8801 NULL +#define pci_ss_list_5333_8810 NULL +#define pci_ss_list_5333_8811 NULL +#define pci_ss_list_5333_8812 NULL +#define pci_ss_list_5333_8813 NULL +#define pci_ss_list_5333_8814 NULL +#define pci_ss_list_5333_8815 NULL +#define pci_ss_list_5333_883d NULL +#define pci_ss_list_5333_8870 NULL +#define pci_ss_list_5333_8880 NULL +#define pci_ss_list_5333_8881 NULL +#define pci_ss_list_5333_8882 NULL +#define pci_ss_list_5333_8883 NULL +#define pci_ss_list_5333_88b0 NULL +#define pci_ss_list_5333_88b1 NULL +#define pci_ss_list_5333_88b2 NULL +#define pci_ss_list_5333_88b3 NULL +#define pci_ss_list_5333_88c0 NULL +#define pci_ss_list_5333_88c1 NULL +#define pci_ss_list_5333_88c2 NULL +#define pci_ss_list_5333_88c3 NULL +#define pci_ss_list_5333_88d0 NULL +#define pci_ss_list_5333_88d1 NULL +#define pci_ss_list_5333_88d2 NULL +#define pci_ss_list_5333_88d3 NULL +#define pci_ss_list_5333_88f0 NULL +#define pci_ss_list_5333_88f1 NULL +#define pci_ss_list_5333_88f2 NULL +#define pci_ss_list_5333_88f3 NULL +static const pciSubsystemInfo *pci_ss_list_5333_8900[] = { + &pci_ss_info_5333_8900_5333_8900, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8901[] = { + &pci_ss_info_5333_8901_5333_8901, + NULL +}; +#define pci_ss_list_5333_8902 NULL +#define pci_ss_list_5333_8903 NULL +static const pciSubsystemInfo *pci_ss_list_5333_8904[] = { + &pci_ss_info_5333_8904_1014_00db, + &pci_ss_info_5333_8904_5333_8904, + NULL +}; +#define pci_ss_list_5333_8905 NULL +#define pci_ss_list_5333_8906 NULL +#define pci_ss_list_5333_8907 NULL +#define pci_ss_list_5333_8908 NULL +#define pci_ss_list_5333_8909 NULL +#define pci_ss_list_5333_890a NULL +#define pci_ss_list_5333_890b NULL +#define pci_ss_list_5333_890c NULL +#define pci_ss_list_5333_890d NULL +#define pci_ss_list_5333_890e NULL +#define pci_ss_list_5333_890f NULL +static const pciSubsystemInfo *pci_ss_list_5333_8a01[] = { + &pci_ss_info_5333_8a01_0e11_b032, + &pci_ss_info_5333_8a01_10b4_1617, + &pci_ss_info_5333_8a01_10b4_1717, + &pci_ss_info_5333_8a01_5333_8a01, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a10[] = { + &pci_ss_info_5333_8a10_1092_8a10, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a13[] = { + &pci_ss_info_5333_8a13_5333_8a13, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a20[] = { + &pci_ss_info_5333_8a20_5333_8a20, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a21[] = { + &pci_ss_info_5333_8a21_5333_8a21, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8a22[] = { + &pci_ss_info_5333_8a22_1033_8068, + &pci_ss_info_5333_8a22_1033_8069, + &pci_ss_info_5333_8a22_1033_8110, + &pci_ss_info_5333_8a22_105d_0018, + &pci_ss_info_5333_8a22_105d_002a, + &pci_ss_info_5333_8a22_105d_003a, + &pci_ss_info_5333_8a22_105d_092f, + &pci_ss_info_5333_8a22_1092_4207, + &pci_ss_info_5333_8a22_1092_4800, + &pci_ss_info_5333_8a22_1092_4807, + &pci_ss_info_5333_8a22_1092_4808, + &pci_ss_info_5333_8a22_1092_4809, + &pci_ss_info_5333_8a22_1092_480e, + &pci_ss_info_5333_8a22_1092_4904, + &pci_ss_info_5333_8a22_1092_4905, + &pci_ss_info_5333_8a22_1092_4a09, + &pci_ss_info_5333_8a22_1092_4a0b, + &pci_ss_info_5333_8a22_1092_4a0f, + &pci_ss_info_5333_8a22_1092_4e01, + &pci_ss_info_5333_8a22_1102_101d, + &pci_ss_info_5333_8a22_1102_101e, + &pci_ss_info_5333_8a22_5333_8100, + &pci_ss_info_5333_8a22_5333_8110, + &pci_ss_info_5333_8a22_5333_8125, + &pci_ss_info_5333_8a22_5333_8143, + &pci_ss_info_5333_8a22_5333_8a22, + &pci_ss_info_5333_8a22_5333_8a2e, + &pci_ss_info_5333_8a22_5333_9125, + &pci_ss_info_5333_8a22_5333_9143, + NULL +}; +#define pci_ss_list_5333_8a23 NULL +#define pci_ss_list_5333_8a25 NULL +#define pci_ss_list_5333_8a26 NULL +#define pci_ss_list_5333_8c00 NULL +static const pciSubsystemInfo *pci_ss_list_5333_8c01[] = { + &pci_ss_info_5333_8c01_1179_0001, + NULL +}; +#define pci_ss_list_5333_8c02 NULL +#define pci_ss_list_5333_8c03 NULL +#define pci_ss_list_5333_8c10 NULL +#define pci_ss_list_5333_8c11 NULL +static const pciSubsystemInfo *pci_ss_list_5333_8c12[] = { + &pci_ss_info_5333_8c12_1014_017f, + &pci_ss_info_5333_8c12_1179_0001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_5333_8c13[] = { + &pci_ss_info_5333_8c13_1179_0001, + NULL +}; +#define pci_ss_list_5333_8c22 NULL +#define pci_ss_list_5333_8c24 NULL +#define pci_ss_list_5333_8c26 NULL +#define pci_ss_list_5333_8c2a NULL +#define pci_ss_list_5333_8c2b NULL +#define pci_ss_list_5333_8c2c NULL +#define pci_ss_list_5333_8c2d NULL +static const pciSubsystemInfo *pci_ss_list_5333_8c2e[] = { + &pci_ss_info_5333_8c2e_1014_01fc, + NULL +}; +#define pci_ss_list_5333_8c2f NULL +#define pci_ss_list_5333_8d01 NULL +#define pci_ss_list_5333_8d02 NULL +#define pci_ss_list_5333_8d03 NULL +#define pci_ss_list_5333_8d04 NULL +static const pciSubsystemInfo *pci_ss_list_5333_9102[] = { + &pci_ss_info_5333_9102_1092_5932, + &pci_ss_info_5333_9102_1092_5934, + &pci_ss_info_5333_9102_1092_5952, + &pci_ss_info_5333_9102_1092_5954, + &pci_ss_info_5333_9102_1092_5a35, + &pci_ss_info_5333_9102_1092_5a37, + &pci_ss_info_5333_9102_1092_5a55, + &pci_ss_info_5333_9102_1092_5a57, + NULL +}; +#define pci_ss_list_5333_ca00 NULL +#define pci_ss_list_544c_0350 NULL +#define pci_ss_list_5455_4458 NULL +#define pci_ss_list_5544_0001 NULL +#define pci_ss_list_5555_0003 NULL +#define pci_ss_list_5654_3132 NULL +#define pci_ss_list_6374_6773 NULL +#define pci_ss_list_6666_0001 NULL +#define pci_ss_list_6666_0002 NULL +#define pci_ss_list_6666_0004 NULL +#define pci_ss_list_6666_0101 NULL +#define pci_ss_list_7063_2000 NULL +#define pci_ss_list_7063_3000 NULL +#define pci_ss_list_7063_5500 NULL +#define pci_ss_list_8008_0010 NULL +#define pci_ss_list_8008_0011 NULL +#define pci_ss_list_8086_0007 NULL +#define pci_ss_list_8086_0008 NULL +#define pci_ss_list_8086_0039 NULL +#define pci_ss_list_8086_0122 NULL +#define pci_ss_list_8086_0309 NULL +#define pci_ss_list_8086_030d NULL +#define pci_ss_list_8086_0326 NULL +#define pci_ss_list_8086_0327 NULL +#define pci_ss_list_8086_0329 NULL +#define pci_ss_list_8086_032a NULL +#define pci_ss_list_8086_032c NULL +#define pci_ss_list_8086_0330 NULL +#define pci_ss_list_8086_0331 NULL +#define pci_ss_list_8086_0332 NULL +#define pci_ss_list_8086_0333 NULL +#define pci_ss_list_8086_0334 NULL +#define pci_ss_list_8086_0335 NULL +#define pci_ss_list_8086_0336 NULL +#define pci_ss_list_8086_0340 NULL +#define pci_ss_list_8086_0341 NULL +#define pci_ss_list_8086_0370 NULL +#define pci_ss_list_8086_0371 NULL +#define pci_ss_list_8086_0372 NULL +#define pci_ss_list_8086_0373 NULL +#define pci_ss_list_8086_0374 NULL +#define pci_ss_list_8086_0482 NULL +#define pci_ss_list_8086_0483 NULL +#define pci_ss_list_8086_0484 NULL +#define pci_ss_list_8086_0486 NULL +#define pci_ss_list_8086_04a3 NULL +#define pci_ss_list_8086_04d0 NULL +#define pci_ss_list_8086_0500 NULL +#define pci_ss_list_8086_0501 NULL +#define pci_ss_list_8086_0502 NULL +#define pci_ss_list_8086_0503 NULL +#define pci_ss_list_8086_0510 NULL +#define pci_ss_list_8086_0511 NULL +#define pci_ss_list_8086_0512 NULL +#define pci_ss_list_8086_0513 NULL +#define pci_ss_list_8086_0514 NULL +#define pci_ss_list_8086_0515 NULL +#define pci_ss_list_8086_0516 NULL +#define pci_ss_list_8086_0530 NULL +#define pci_ss_list_8086_0531 NULL +#define pci_ss_list_8086_0532 NULL +#define pci_ss_list_8086_0533 NULL +#define pci_ss_list_8086_0534 NULL +#define pci_ss_list_8086_0535 NULL +#define pci_ss_list_8086_0536 NULL +#define pci_ss_list_8086_0537 NULL +static const pciSubsystemInfo *pci_ss_list_8086_0600[] = { + &pci_ss_info_8086_0600_8086_01af, + &pci_ss_info_8086_0600_8086_01c1, + &pci_ss_info_8086_0600_8086_01f7, + NULL +}; +#define pci_ss_list_8086_061f NULL +#define pci_ss_list_8086_0960 NULL +#define pci_ss_list_8086_0962 NULL +#define pci_ss_list_8086_0964 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1000[] = { + &pci_ss_info_8086_1000_0e11_b0df, + &pci_ss_info_8086_1000_0e11_b0e0, + &pci_ss_info_8086_1000_0e11_b123, + &pci_ss_info_8086_1000_1014_0119, + &pci_ss_info_8086_1000_8086_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1001[] = { + &pci_ss_info_8086_1001_0e11_004a, + &pci_ss_info_8086_1001_1014_01ea, + &pci_ss_info_8086_1001_8086_1002, + &pci_ss_info_8086_1001_8086_1003, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1002[] = { + &pci_ss_info_8086_1002_8086_200e, + &pci_ss_info_8086_1002_8086_2013, + &pci_ss_info_8086_1002_8086_2017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1004[] = { + &pci_ss_info_8086_1004_0e11_0049, + &pci_ss_info_8086_1004_0e11_b1a4, + &pci_ss_info_8086_1004_1014_10f2, + &pci_ss_info_8086_1004_8086_1004, + &pci_ss_info_8086_1004_8086_2004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1008[] = { + &pci_ss_info_8086_1008_1014_0269, + &pci_ss_info_8086_1008_1028_011c, + &pci_ss_info_8086_1008_8086_1107, + &pci_ss_info_8086_1008_8086_2107, + &pci_ss_info_8086_1008_8086_2110, + &pci_ss_info_8086_1008_8086_3108, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1009[] = { + &pci_ss_info_8086_1009_1014_0268, + &pci_ss_info_8086_1009_8086_1109, + &pci_ss_info_8086_1009_8086_2109, + NULL +}; +#define pci_ss_list_8086_100a NULL +static const pciSubsystemInfo *pci_ss_list_8086_100c[] = { + &pci_ss_info_8086_100c_8086_1112, + &pci_ss_info_8086_100c_8086_2112, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_100d[] = { + &pci_ss_info_8086_100d_1028_0123, + &pci_ss_info_8086_100d_1079_891f, + &pci_ss_info_8086_100d_4c53_1080, + &pci_ss_info_8086_100d_8086_110d, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_100e[] = { + &pci_ss_info_8086_100e_1014_0265, + &pci_ss_info_8086_100e_1014_0267, + &pci_ss_info_8086_100e_1014_026a, + &pci_ss_info_8086_100e_1028_002e, + &pci_ss_info_8086_100e_1028_0134, + &pci_ss_info_8086_100e_1028_0151, + &pci_ss_info_8086_100e_107b_8920, + &pci_ss_info_8086_100e_8086_001e, + &pci_ss_info_8086_100e_8086_002e, + &pci_ss_info_8086_100e_8086_1376, + &pci_ss_info_8086_100e_8086_1476, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_100f[] = { + &pci_ss_info_8086_100f_1014_0269, + &pci_ss_info_8086_100f_1014_028e, + &pci_ss_info_8086_100f_8086_1000, + &pci_ss_info_8086_100f_8086_1001, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1010[] = { + &pci_ss_info_8086_1010_0e11_00db, + &pci_ss_info_8086_1010_1014_027c, + &pci_ss_info_8086_1010_18fb_7872, + &pci_ss_info_8086_1010_1fc1_0026, + &pci_ss_info_8086_1010_4c53_1080, + &pci_ss_info_8086_1010_4c53_10a0, + &pci_ss_info_8086_1010_8086_1011, + &pci_ss_info_8086_1010_8086_1012, + &pci_ss_info_8086_1010_8086_101a, + &pci_ss_info_8086_1010_8086_3424, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1011[] = { + &pci_ss_info_8086_1011_1014_0268, + &pci_ss_info_8086_1011_8086_1002, + &pci_ss_info_8086_1011_8086_1003, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1012[] = { + &pci_ss_info_8086_1012_0e11_00dc, + &pci_ss_info_8086_1012_8086_1012, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1013[] = { + &pci_ss_info_8086_1013_8086_0013, + &pci_ss_info_8086_1013_8086_1013, + &pci_ss_info_8086_1013_8086_1113, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1014[] = { + &pci_ss_info_8086_1014_8086_0014, + &pci_ss_info_8086_1014_8086_1014, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1015[] = { + &pci_ss_info_8086_1015_8086_1015, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1016[] = { + &pci_ss_info_8086_1016_1014_052c, + &pci_ss_info_8086_1016_1179_0001, + &pci_ss_info_8086_1016_8086_1016, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1017[] = { + &pci_ss_info_8086_1017_8086_1017, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1018[] = { + &pci_ss_info_8086_1018_8086_1018, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1019[] = { + &pci_ss_info_8086_1019_1458_1019, + &pci_ss_info_8086_1019_1458_e000, + &pci_ss_info_8086_1019_8086_1019, + &pci_ss_info_8086_1019_8086_301f, + &pci_ss_info_8086_1019_8086_302c, + &pci_ss_info_8086_1019_8086_3427, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_101a[] = { + &pci_ss_info_8086_101a_8086_101a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_101d[] = { + &pci_ss_info_8086_101d_8086_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_101e[] = { + &pci_ss_info_8086_101e_1014_0549, + &pci_ss_info_8086_101e_1179_0001, + &pci_ss_info_8086_101e_8086_101e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1026[] = { + &pci_ss_info_8086_1026_1028_0169, + &pci_ss_info_8086_1026_8086_1000, + &pci_ss_info_8086_1026_8086_1001, + &pci_ss_info_8086_1026_8086_1002, + &pci_ss_info_8086_1026_8086_1003, + &pci_ss_info_8086_1026_8086_1026, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1027[] = { + &pci_ss_info_8086_1027_103c_3103, + &pci_ss_info_8086_1027_8086_1001, + &pci_ss_info_8086_1027_8086_1002, + &pci_ss_info_8086_1027_8086_1003, + &pci_ss_info_8086_1027_8086_1027, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1028[] = { + &pci_ss_info_8086_1028_8086_1028, + NULL +}; +#define pci_ss_list_8086_1029 NULL +#define pci_ss_list_8086_1030 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1031[] = { + &pci_ss_info_8086_1031_1014_0209, + &pci_ss_info_8086_1031_104d_80e7, + &pci_ss_info_8086_1031_104d_813c, + &pci_ss_info_8086_1031_107b_5350, + &pci_ss_info_8086_1031_1179_0001, + &pci_ss_info_8086_1031_144d_c000, + &pci_ss_info_8086_1031_144d_c001, + &pci_ss_info_8086_1031_144d_c003, + &pci_ss_info_8086_1031_144d_c006, + NULL +}; +#define pci_ss_list_8086_1032 NULL +#define pci_ss_list_8086_1033 NULL +#define pci_ss_list_8086_1034 NULL +#define pci_ss_list_8086_1035 NULL +#define pci_ss_list_8086_1036 NULL +#define pci_ss_list_8086_1037 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1038[] = { + &pci_ss_info_8086_1038_0e11_0098, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1039[] = { + &pci_ss_info_8086_1039_1014_0267, + NULL +}; +#define pci_ss_list_8086_103a NULL +#define pci_ss_list_8086_103b NULL +#define pci_ss_list_8086_103c NULL +static const pciSubsystemInfo *pci_ss_list_8086_103d[] = { + &pci_ss_info_8086_103d_1014_0522, + NULL +}; +#define pci_ss_list_8086_103e NULL +static const pciSubsystemInfo *pci_ss_list_8086_1040[] = { + &pci_ss_info_8086_1040_16be_1040, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1043[] = { + &pci_ss_info_8086_1043_103c_08b0, + &pci_ss_info_8086_1043_8086_2527, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1048[] = { + &pci_ss_info_8086_1048_8086_a01f, + &pci_ss_info_8086_1048_8086_a11f, + NULL +}; +#define pci_ss_list_8086_1049 NULL +#define pci_ss_list_8086_104a NULL +#define pci_ss_list_8086_104b NULL +#define pci_ss_list_8086_104c NULL +#define pci_ss_list_8086_104d NULL +static const pciSubsystemInfo *pci_ss_list_8086_1050[] = { + &pci_ss_info_8086_1050_1462_728c, + &pci_ss_info_8086_1050_1462_758c, + &pci_ss_info_8086_1050_8086_3020, + &pci_ss_info_8086_1050_8086_302f, + &pci_ss_info_8086_1050_8086_3427, + NULL +}; +#define pci_ss_list_8086_1051 NULL +#define pci_ss_list_8086_1052 NULL +#define pci_ss_list_8086_1053 NULL +#define pci_ss_list_8086_1059 NULL +#define pci_ss_list_8086_105b NULL +static const pciSubsystemInfo *pci_ss_list_8086_105e[] = { + &pci_ss_info_8086_105e_103c_7044, + &pci_ss_info_8086_105e_1775_6003, + &pci_ss_info_8086_105e_8086_005e, + &pci_ss_info_8086_105e_8086_105e, + &pci_ss_info_8086_105e_8086_115e, + &pci_ss_info_8086_105e_8086_116e, + &pci_ss_info_8086_105e_8086_125e, + &pci_ss_info_8086_105e_8086_135e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_105f[] = { + &pci_ss_info_8086_105f_8086_115f, + &pci_ss_info_8086_105f_8086_116f, + &pci_ss_info_8086_105f_8086_125f, + &pci_ss_info_8086_105f_8086_135f, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1060[] = { + &pci_ss_info_8086_1060_8086_0060, + &pci_ss_info_8086_1060_8086_1060, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1064[] = { + &pci_ss_info_8086_1064_1043_80f8, + NULL +}; +#define pci_ss_list_8086_1065 NULL +#define pci_ss_list_8086_1066 NULL +#define pci_ss_list_8086_1067 NULL +#define pci_ss_list_8086_1068 NULL +#define pci_ss_list_8086_1069 NULL +#define pci_ss_list_8086_106a NULL +#define pci_ss_list_8086_106b NULL +static const pciSubsystemInfo *pci_ss_list_8086_1075[] = { + &pci_ss_info_8086_1075_1028_0165, + &pci_ss_info_8086_1075_8086_0075, + &pci_ss_info_8086_1075_8086_1075, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1076[] = { + &pci_ss_info_8086_1076_1028_0165, + &pci_ss_info_8086_1076_1028_019a, + &pci_ss_info_8086_1076_8086_0076, + &pci_ss_info_8086_1076_8086_1076, + &pci_ss_info_8086_1076_8086_1176, + &pci_ss_info_8086_1076_8086_1276, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1077[] = { + &pci_ss_info_8086_1077_1179_0001, + &pci_ss_info_8086_1077_8086_0077, + &pci_ss_info_8086_1077_8086_1077, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1078[] = { + &pci_ss_info_8086_1078_8086_1078, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1079[] = { + &pci_ss_info_8086_1079_103c_12a6, + &pci_ss_info_8086_1079_103c_12cf, + &pci_ss_info_8086_1079_1775_10d0, + &pci_ss_info_8086_1079_1775_ce90, + &pci_ss_info_8086_1079_1fc1_0027, + &pci_ss_info_8086_1079_4c53_1090, + &pci_ss_info_8086_1079_4c53_10b0, + &pci_ss_info_8086_1079_8086_0079, + &pci_ss_info_8086_1079_8086_1079, + &pci_ss_info_8086_1079_8086_1179, + &pci_ss_info_8086_1079_8086_117a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_107a[] = { + &pci_ss_info_8086_107a_103c_12a8, + &pci_ss_info_8086_107a_8086_107a, + &pci_ss_info_8086_107a_8086_127a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_107b[] = { + &pci_ss_info_8086_107b_8086_007b, + &pci_ss_info_8086_107b_8086_107b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_107c[] = { + &pci_ss_info_8086_107c_8086_1376, + &pci_ss_info_8086_107c_8086_1476, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_107d[] = { + &pci_ss_info_8086_107d_8086_1082, + &pci_ss_info_8086_107d_8086_1092, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_107e[] = { + &pci_ss_info_8086_107e_8086_1084, + &pci_ss_info_8086_107e_8086_1094, + NULL +}; +#define pci_ss_list_8086_107f NULL +#define pci_ss_list_8086_1080 NULL +#define pci_ss_list_8086_1081 NULL +#define pci_ss_list_8086_1082 NULL +#define pci_ss_list_8086_1083 NULL +#define pci_ss_list_8086_1084 NULL +#define pci_ss_list_8086_1085 NULL +#define pci_ss_list_8086_1086 NULL +#define pci_ss_list_8086_1087 NULL +#define pci_ss_list_8086_1089 NULL +static const pciSubsystemInfo *pci_ss_list_8086_108a[] = { + &pci_ss_info_8086_108a_8086_108a, + &pci_ss_info_8086_108a_8086_118a, + NULL +}; +#define pci_ss_list_8086_108b NULL +#define pci_ss_list_8086_108c NULL +#define pci_ss_list_8086_108e NULL +#define pci_ss_list_8086_108f NULL +#define pci_ss_list_8086_1092 NULL +#define pci_ss_list_8086_1096 NULL +#define pci_ss_list_8086_1097 NULL +#define pci_ss_list_8086_1098 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1099[] = { + &pci_ss_info_8086_1099_8086_1099, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_109a[] = { + &pci_ss_info_8086_109a_17aa_2001, + &pci_ss_info_8086_109a_17aa_207e, + &pci_ss_info_8086_109a_8086_109a, + NULL +}; +#define pci_ss_list_8086_109b NULL +#define pci_ss_list_8086_10a0 NULL +#define pci_ss_list_8086_10a1 NULL +#define pci_ss_list_8086_10b0 NULL +#define pci_ss_list_8086_10b2 NULL +#define pci_ss_list_8086_10b3 NULL +#define pci_ss_list_8086_10b4 NULL +static const pciSubsystemInfo *pci_ss_list_8086_10b5[] = { + &pci_ss_info_8086_10b5_103c_3109, + &pci_ss_info_8086_10b5_8086_1099, + &pci_ss_info_8086_10b5_8086_1199, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_10b9[] = { + &pci_ss_info_8086_10b9_8086_1083, + &pci_ss_info_8086_10b9_8086_1093, + NULL +}; +#define pci_ss_list_8086_10ba NULL +#define pci_ss_list_8086_10bb NULL +#define pci_ss_list_8086_1107 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1130[] = { + &pci_ss_info_8086_1130_1025_1016, + &pci_ss_info_8086_1130_1043_8027, + &pci_ss_info_8086_1130_104d_80df, + &pci_ss_info_8086_1130_8086_4532, + &pci_ss_info_8086_1130_8086_4557, + NULL +}; +#define pci_ss_list_8086_1131 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1132[] = { + &pci_ss_info_8086_1132_1025_1016, + &pci_ss_info_8086_1132_104d_80df, + &pci_ss_info_8086_1132_8086_4532, + &pci_ss_info_8086_1132_8086_4541, + &pci_ss_info_8086_1132_8086_4557, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1161[] = { + &pci_ss_info_8086_1161_8086_1161, + NULL +}; +#define pci_ss_list_8086_1162 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1200[] = { + &pci_ss_info_8086_1200_172a_0000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1209[] = { + &pci_ss_info_8086_1209_4c53_1050, + &pci_ss_info_8086_1209_4c53_1051, + &pci_ss_info_8086_1209_4c53_1070, + NULL +}; +#define pci_ss_list_8086_1221 NULL +#define pci_ss_list_8086_1222 NULL +#define pci_ss_list_8086_1223 NULL +#define pci_ss_list_8086_1225 NULL +#define pci_ss_list_8086_1226 NULL +#define pci_ss_list_8086_1227 NULL +#define pci_ss_list_8086_1228 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1229[] = { + &pci_ss_info_8086_1229_0e11_3001, + &pci_ss_info_8086_1229_0e11_3002, + &pci_ss_info_8086_1229_0e11_3003, + &pci_ss_info_8086_1229_0e11_3004, + &pci_ss_info_8086_1229_0e11_3005, + &pci_ss_info_8086_1229_0e11_3006, + &pci_ss_info_8086_1229_0e11_3007, + &pci_ss_info_8086_1229_0e11_b01e, + &pci_ss_info_8086_1229_0e11_b01f, + &pci_ss_info_8086_1229_0e11_b02f, + &pci_ss_info_8086_1229_0e11_b04a, + &pci_ss_info_8086_1229_0e11_b0c6, + &pci_ss_info_8086_1229_0e11_b0c7, + &pci_ss_info_8086_1229_0e11_b0d7, + &pci_ss_info_8086_1229_0e11_b0dd, + &pci_ss_info_8086_1229_0e11_b0de, + &pci_ss_info_8086_1229_0e11_b0e1, + &pci_ss_info_8086_1229_0e11_b134, + &pci_ss_info_8086_1229_0e11_b13c, + &pci_ss_info_8086_1229_0e11_b144, + &pci_ss_info_8086_1229_0e11_b163, + &pci_ss_info_8086_1229_0e11_b164, + &pci_ss_info_8086_1229_0e11_b1a4, + &pci_ss_info_8086_1229_1014_005c, + &pci_ss_info_8086_1229_1014_01bc, + &pci_ss_info_8086_1229_1014_01f1, + &pci_ss_info_8086_1229_1014_01f2, + &pci_ss_info_8086_1229_1014_0207, + &pci_ss_info_8086_1229_1014_0232, + &pci_ss_info_8086_1229_1014_023a, + &pci_ss_info_8086_1229_1014_105c, + &pci_ss_info_8086_1229_1014_2205, + &pci_ss_info_8086_1229_1014_305c, + &pci_ss_info_8086_1229_1014_405c, + &pci_ss_info_8086_1229_1014_505c, + &pci_ss_info_8086_1229_1014_605c, + &pci_ss_info_8086_1229_1014_705c, + &pci_ss_info_8086_1229_1014_805c, + &pci_ss_info_8086_1229_1028_009b, + &pci_ss_info_8086_1229_1028_00ce, + &pci_ss_info_8086_1229_1033_8000, + &pci_ss_info_8086_1229_1033_8016, + &pci_ss_info_8086_1229_1033_801f, + &pci_ss_info_8086_1229_1033_8026, + &pci_ss_info_8086_1229_1033_8063, + &pci_ss_info_8086_1229_1033_8064, + &pci_ss_info_8086_1229_103c_10c0, + &pci_ss_info_8086_1229_103c_10c3, + &pci_ss_info_8086_1229_103c_10ca, + &pci_ss_info_8086_1229_103c_10cb, + &pci_ss_info_8086_1229_103c_10e3, + &pci_ss_info_8086_1229_103c_10e4, + &pci_ss_info_8086_1229_103c_1200, + &pci_ss_info_8086_1229_108e_10cf, + &pci_ss_info_8086_1229_10c3_1100, + &pci_ss_info_8086_1229_10cf_1115, + &pci_ss_info_8086_1229_10cf_1143, + &pci_ss_info_8086_1229_110a_008b, + &pci_ss_info_8086_1229_1179_0001, + &pci_ss_info_8086_1229_1179_0002, + &pci_ss_info_8086_1229_1179_0003, + &pci_ss_info_8086_1229_1259_2560, + &pci_ss_info_8086_1229_1259_2561, + &pci_ss_info_8086_1229_1266_0001, + &pci_ss_info_8086_1229_13e9_1000, + &pci_ss_info_8086_1229_144d_2501, + &pci_ss_info_8086_1229_144d_2502, + &pci_ss_info_8086_1229_1668_1100, + &pci_ss_info_8086_1229_1775_ce90, + &pci_ss_info_8086_1229_4c53_1080, + &pci_ss_info_8086_1229_4c53_10e0, + &pci_ss_info_8086_1229_8086_0001, + &pci_ss_info_8086_1229_8086_0002, + &pci_ss_info_8086_1229_8086_0003, + &pci_ss_info_8086_1229_8086_0004, + &pci_ss_info_8086_1229_8086_0005, + &pci_ss_info_8086_1229_8086_0006, + &pci_ss_info_8086_1229_8086_0007, + &pci_ss_info_8086_1229_8086_0008, + &pci_ss_info_8086_1229_8086_000a, + &pci_ss_info_8086_1229_8086_000b, + &pci_ss_info_8086_1229_8086_000c, + &pci_ss_info_8086_1229_8086_000d, + &pci_ss_info_8086_1229_8086_000e, + &pci_ss_info_8086_1229_8086_000f, + &pci_ss_info_8086_1229_8086_0010, + &pci_ss_info_8086_1229_8086_0011, + &pci_ss_info_8086_1229_8086_0012, + &pci_ss_info_8086_1229_8086_0013, + &pci_ss_info_8086_1229_8086_0030, + &pci_ss_info_8086_1229_8086_0031, + &pci_ss_info_8086_1229_8086_0040, + &pci_ss_info_8086_1229_8086_0041, + &pci_ss_info_8086_1229_8086_0042, + &pci_ss_info_8086_1229_8086_0050, + &pci_ss_info_8086_1229_8086_1009, + &pci_ss_info_8086_1229_8086_100c, + &pci_ss_info_8086_1229_8086_1012, + &pci_ss_info_8086_1229_8086_1013, + &pci_ss_info_8086_1229_8086_1015, + &pci_ss_info_8086_1229_8086_1017, + &pci_ss_info_8086_1229_8086_1030, + &pci_ss_info_8086_1229_8086_1040, + &pci_ss_info_8086_1229_8086_1041, + &pci_ss_info_8086_1229_8086_1042, + &pci_ss_info_8086_1229_8086_1050, + &pci_ss_info_8086_1229_8086_1051, + &pci_ss_info_8086_1229_8086_1052, + &pci_ss_info_8086_1229_8086_10f0, + &pci_ss_info_8086_1229_8086_2009, + &pci_ss_info_8086_1229_8086_200d, + &pci_ss_info_8086_1229_8086_200e, + &pci_ss_info_8086_1229_8086_200f, + &pci_ss_info_8086_1229_8086_2010, + &pci_ss_info_8086_1229_8086_2013, + &pci_ss_info_8086_1229_8086_2016, + &pci_ss_info_8086_1229_8086_2017, + &pci_ss_info_8086_1229_8086_2018, + &pci_ss_info_8086_1229_8086_2019, + &pci_ss_info_8086_1229_8086_2101, + &pci_ss_info_8086_1229_8086_2102, + &pci_ss_info_8086_1229_8086_2103, + &pci_ss_info_8086_1229_8086_2104, + &pci_ss_info_8086_1229_8086_2105, + &pci_ss_info_8086_1229_8086_2106, + &pci_ss_info_8086_1229_8086_2107, + &pci_ss_info_8086_1229_8086_2108, + &pci_ss_info_8086_1229_8086_2200, + &pci_ss_info_8086_1229_8086_2201, + &pci_ss_info_8086_1229_8086_2202, + &pci_ss_info_8086_1229_8086_2203, + &pci_ss_info_8086_1229_8086_2204, + &pci_ss_info_8086_1229_8086_2205, + &pci_ss_info_8086_1229_8086_2206, + &pci_ss_info_8086_1229_8086_2207, + &pci_ss_info_8086_1229_8086_2208, + &pci_ss_info_8086_1229_8086_2402, + &pci_ss_info_8086_1229_8086_2407, + &pci_ss_info_8086_1229_8086_2408, + &pci_ss_info_8086_1229_8086_2409, + &pci_ss_info_8086_1229_8086_240f, + &pci_ss_info_8086_1229_8086_2410, + &pci_ss_info_8086_1229_8086_2411, + &pci_ss_info_8086_1229_8086_2412, + &pci_ss_info_8086_1229_8086_2413, + &pci_ss_info_8086_1229_8086_3000, + &pci_ss_info_8086_1229_8086_3001, + &pci_ss_info_8086_1229_8086_3002, + &pci_ss_info_8086_1229_8086_3006, + &pci_ss_info_8086_1229_8086_3007, + &pci_ss_info_8086_1229_8086_3008, + &pci_ss_info_8086_1229_8086_3010, + &pci_ss_info_8086_1229_8086_3011, + &pci_ss_info_8086_1229_8086_3012, + &pci_ss_info_8086_1229_8086_3411, + NULL +}; +#define pci_ss_list_8086_122d NULL +#define pci_ss_list_8086_122e NULL +#define pci_ss_list_8086_1230 NULL +#define pci_ss_list_8086_1231 NULL +#define pci_ss_list_8086_1234 NULL +#define pci_ss_list_8086_1235 NULL +#define pci_ss_list_8086_1237 NULL +#define pci_ss_list_8086_1239 NULL +#define pci_ss_list_8086_123b NULL +#define pci_ss_list_8086_123c NULL +#define pci_ss_list_8086_123d NULL +#define pci_ss_list_8086_123e NULL +#define pci_ss_list_8086_123f NULL +#define pci_ss_list_8086_1240 NULL +#define pci_ss_list_8086_124b NULL +#define pci_ss_list_8086_1250 NULL +#define pci_ss_list_8086_1360 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1361[] = { + &pci_ss_info_8086_1361_8086_1361, + &pci_ss_info_8086_1361_8086_8000, + NULL +}; +#define pci_ss_list_8086_1460 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1461[] = { + &pci_ss_info_8086_1461_15d9_3480, + &pci_ss_info_8086_1461_4c53_1090, + NULL +}; +#define pci_ss_list_8086_1462 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1960[] = { + &pci_ss_info_8086_1960_101e_0431, + &pci_ss_info_8086_1960_101e_0438, + &pci_ss_info_8086_1960_101e_0466, + &pci_ss_info_8086_1960_101e_0467, + &pci_ss_info_8086_1960_101e_0490, + &pci_ss_info_8086_1960_101e_0762, + &pci_ss_info_8086_1960_101e_09a0, + &pci_ss_info_8086_1960_1028_0467, + &pci_ss_info_8086_1960_1028_1111, + &pci_ss_info_8086_1960_103c_03a2, + &pci_ss_info_8086_1960_103c_10c6, + &pci_ss_info_8086_1960_103c_10c7, + &pci_ss_info_8086_1960_103c_10cc, + &pci_ss_info_8086_1960_103c_10cd, + &pci_ss_info_8086_1960_105a_0000, + &pci_ss_info_8086_1960_105a_2168, + &pci_ss_info_8086_1960_105a_5168, + &pci_ss_info_8086_1960_1111_1111, + &pci_ss_info_8086_1960_1111_1112, + &pci_ss_info_8086_1960_113c_03a2, + &pci_ss_info_8086_1960_e4bf_1010, + &pci_ss_info_8086_1960_e4bf_1020, + &pci_ss_info_8086_1960_e4bf_1040, + &pci_ss_info_8086_1960_e4bf_3100, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_1962[] = { + &pci_ss_info_8086_1962_105a_0000, + NULL +}; +#define pci_ss_list_8086_1a21 NULL +#define pci_ss_list_8086_1a23 NULL +#define pci_ss_list_8086_1a24 NULL +static const pciSubsystemInfo *pci_ss_list_8086_1a30[] = { + &pci_ss_info_8086_1a30_1028_010e, + NULL +}; +#define pci_ss_list_8086_1a31 NULL +#define pci_ss_list_8086_1a38 NULL +#define pci_ss_list_8086_1a48 NULL +#define pci_ss_list_8086_2410 NULL +#define pci_ss_list_8086_2411 NULL +#define pci_ss_list_8086_2412 NULL +#define pci_ss_list_8086_2413 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2415[] = { + &pci_ss_info_8086_2415_1028_0095, + &pci_ss_info_8086_2415_110a_0051, + &pci_ss_info_8086_2415_11d4_0040, + &pci_ss_info_8086_2415_11d4_0048, + &pci_ss_info_8086_2415_11d4_5340, + &pci_ss_info_8086_2415_1734_1025, + NULL +}; +#define pci_ss_list_8086_2416 NULL +#define pci_ss_list_8086_2418 NULL +#define pci_ss_list_8086_2420 NULL +#define pci_ss_list_8086_2421 NULL +#define pci_ss_list_8086_2422 NULL +#define pci_ss_list_8086_2423 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2425[] = { + &pci_ss_info_8086_2425_11d4_0040, + &pci_ss_info_8086_2425_11d4_0048, + NULL +}; +#define pci_ss_list_8086_2426 NULL +#define pci_ss_list_8086_2428 NULL +#define pci_ss_list_8086_2440 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2442[] = { + &pci_ss_info_8086_2442_1014_01c6, + &pci_ss_info_8086_2442_1025_1016, + &pci_ss_info_8086_2442_1028_00c7, + &pci_ss_info_8086_2442_1028_010e, + &pci_ss_info_8086_2442_1043_8027, + &pci_ss_info_8086_2442_104d_80df, + &pci_ss_info_8086_2442_147b_0507, + &pci_ss_info_8086_2442_8086_4532, + &pci_ss_info_8086_2442_8086_4557, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2443[] = { + &pci_ss_info_8086_2443_1014_01c6, + &pci_ss_info_8086_2443_1025_1016, + &pci_ss_info_8086_2443_1028_00c7, + &pci_ss_info_8086_2443_1028_010e, + &pci_ss_info_8086_2443_1043_8027, + &pci_ss_info_8086_2443_104d_80df, + &pci_ss_info_8086_2443_147b_0507, + &pci_ss_info_8086_2443_8086_4532, + &pci_ss_info_8086_2443_8086_4557, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2444[] = { + &pci_ss_info_8086_2444_1025_1016, + &pci_ss_info_8086_2444_1028_00c7, + &pci_ss_info_8086_2444_1028_010e, + &pci_ss_info_8086_2444_1043_8027, + &pci_ss_info_8086_2444_104d_80df, + &pci_ss_info_8086_2444_147b_0507, + &pci_ss_info_8086_2444_8086_4532, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2445[] = { + &pci_ss_info_8086_2445_0e11_0088, + &pci_ss_info_8086_2445_1014_01c6, + &pci_ss_info_8086_2445_1025_1016, + &pci_ss_info_8086_2445_104d_80df, + &pci_ss_info_8086_2445_1462_3370, + &pci_ss_info_8086_2445_147b_0507, + &pci_ss_info_8086_2445_8086_4557, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2446[] = { + &pci_ss_info_8086_2446_1025_1016, + &pci_ss_info_8086_2446_104d_80df, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2448[] = { + &pci_ss_info_8086_2448_103c_099c, + &pci_ss_info_8086_2448_1734_1055, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2449[] = { + &pci_ss_info_8086_2449_0e11_0012, + &pci_ss_info_8086_2449_0e11_0091, + &pci_ss_info_8086_2449_1014_01ce, + &pci_ss_info_8086_2449_1014_01dc, + &pci_ss_info_8086_2449_1014_01eb, + &pci_ss_info_8086_2449_1014_01ec, + &pci_ss_info_8086_2449_1014_0202, + &pci_ss_info_8086_2449_1014_0205, + &pci_ss_info_8086_2449_1014_0217, + &pci_ss_info_8086_2449_1014_0234, + &pci_ss_info_8086_2449_1014_023d, + &pci_ss_info_8086_2449_1014_0244, + &pci_ss_info_8086_2449_1014_0245, + &pci_ss_info_8086_2449_1014_0265, + &pci_ss_info_8086_2449_1014_0267, + &pci_ss_info_8086_2449_1014_026a, + &pci_ss_info_8086_2449_109f_315d, + &pci_ss_info_8086_2449_109f_3181, + &pci_ss_info_8086_2449_1179_ff01, + &pci_ss_info_8086_2449_1186_7801, + &pci_ss_info_8086_2449_144d_2602, + &pci_ss_info_8086_2449_8086_3010, + &pci_ss_info_8086_2449_8086_3011, + &pci_ss_info_8086_2449_8086_3012, + &pci_ss_info_8086_2449_8086_3013, + &pci_ss_info_8086_2449_8086_3014, + &pci_ss_info_8086_2449_8086_3015, + &pci_ss_info_8086_2449_8086_3016, + &pci_ss_info_8086_2449_8086_3017, + &pci_ss_info_8086_2449_8086_3018, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_244a[] = { + &pci_ss_info_8086_244a_1025_1016, + &pci_ss_info_8086_244a_104d_80df, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_244b[] = { + &pci_ss_info_8086_244b_1014_01c6, + &pci_ss_info_8086_244b_1028_00c7, + &pci_ss_info_8086_244b_1028_010e, + &pci_ss_info_8086_244b_1043_8027, + &pci_ss_info_8086_244b_147b_0507, + &pci_ss_info_8086_244b_8086_4532, + &pci_ss_info_8086_244b_8086_4557, + NULL +}; +#define pci_ss_list_8086_244c NULL +static const pciSubsystemInfo *pci_ss_list_8086_244e[] = { + &pci_ss_info_8086_244e_1014_0267, + NULL +}; +#define pci_ss_list_8086_2450 NULL +#define pci_ss_list_8086_2452 NULL +#define pci_ss_list_8086_2453 NULL +#define pci_ss_list_8086_2459 NULL +#define pci_ss_list_8086_245b NULL +#define pci_ss_list_8086_245d NULL +#define pci_ss_list_8086_245e NULL +#define pci_ss_list_8086_2480 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2482[] = { + &pci_ss_info_8086_2482_0e11_0030, + &pci_ss_info_8086_2482_1014_0220, + &pci_ss_info_8086_2482_104d_80e7, + &pci_ss_info_8086_2482_15d9_3480, + &pci_ss_info_8086_2482_8086_1958, + &pci_ss_info_8086_2482_8086_3424, + &pci_ss_info_8086_2482_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2483[] = { + &pci_ss_info_8086_2483_1014_0220, + &pci_ss_info_8086_2483_104d_80e7, + &pci_ss_info_8086_2483_15d9_3480, + &pci_ss_info_8086_2483_8086_1958, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2484[] = { + &pci_ss_info_8086_2484_0e11_0030, + &pci_ss_info_8086_2484_1014_0220, + &pci_ss_info_8086_2484_104d_80e7, + &pci_ss_info_8086_2484_15d9_3480, + &pci_ss_info_8086_2484_8086_1958, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2485[] = { + &pci_ss_info_8086_2485_1013_5959, + &pci_ss_info_8086_2485_1014_0222, + &pci_ss_info_8086_2485_1014_0508, + &pci_ss_info_8086_2485_1014_051c, + &pci_ss_info_8086_2485_104d_80e7, + &pci_ss_info_8086_2485_144d_c006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2486[] = { + &pci_ss_info_8086_2486_1014_0223, + &pci_ss_info_8086_2486_1014_0503, + &pci_ss_info_8086_2486_1014_051a, + &pci_ss_info_8086_2486_101f_1025, + &pci_ss_info_8086_2486_104d_80e7, + &pci_ss_info_8086_2486_134d_4c21, + &pci_ss_info_8086_2486_144d_2115, + &pci_ss_info_8086_2486_14f1_5421, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2487[] = { + &pci_ss_info_8086_2487_0e11_0030, + &pci_ss_info_8086_2487_1014_0220, + &pci_ss_info_8086_2487_104d_80e7, + &pci_ss_info_8086_2487_15d9_3480, + &pci_ss_info_8086_2487_8086_1958, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_248a[] = { + &pci_ss_info_8086_248a_0e11_0030, + &pci_ss_info_8086_248a_1014_0220, + &pci_ss_info_8086_248a_104d_80e7, + &pci_ss_info_8086_248a_8086_1958, + &pci_ss_info_8086_248a_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_248b[] = { + &pci_ss_info_8086_248b_15d9_3480, + NULL +}; +#define pci_ss_list_8086_248c NULL +static const pciSubsystemInfo *pci_ss_list_8086_24c0[] = { + &pci_ss_info_8086_24c0_1014_0267, + &pci_ss_info_8086_24c0_1462_5800, + NULL +}; +#define pci_ss_list_8086_24c1 NULL +static const pciSubsystemInfo *pci_ss_list_8086_24c2[] = { + &pci_ss_info_8086_24c2_1014_0267, + &pci_ss_info_8086_24c2_1014_052d, + &pci_ss_info_8086_24c2_1025_005a, + &pci_ss_info_8086_24c2_1028_0126, + &pci_ss_info_8086_24c2_1028_0163, + &pci_ss_info_8086_24c2_1028_0196, + &pci_ss_info_8086_24c2_103c_088c, + &pci_ss_info_8086_24c2_103c_0890, + &pci_ss_info_8086_24c2_103c_08b0, + &pci_ss_info_8086_24c2_1071_8160, + &pci_ss_info_8086_24c2_1462_5800, + &pci_ss_info_8086_24c2_1509_2990, + &pci_ss_info_8086_24c2_1734_1004, + &pci_ss_info_8086_24c2_1734_1055, + &pci_ss_info_8086_24c2_4c53_1090, + &pci_ss_info_8086_24c2_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24c3[] = { + &pci_ss_info_8086_24c3_1014_0267, + &pci_ss_info_8086_24c3_1014_052d, + &pci_ss_info_8086_24c3_1025_005a, + &pci_ss_info_8086_24c3_1028_0126, + &pci_ss_info_8086_24c3_103c_088c, + &pci_ss_info_8086_24c3_103c_0890, + &pci_ss_info_8086_24c3_103c_08b0, + &pci_ss_info_8086_24c3_1071_8160, + &pci_ss_info_8086_24c3_1458_24c2, + &pci_ss_info_8086_24c3_1462_5800, + &pci_ss_info_8086_24c3_1734_1004, + &pci_ss_info_8086_24c3_1734_1055, + &pci_ss_info_8086_24c3_4c53_1090, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24c4[] = { + &pci_ss_info_8086_24c4_1014_0267, + &pci_ss_info_8086_24c4_1014_052d, + &pci_ss_info_8086_24c4_1025_005a, + &pci_ss_info_8086_24c4_1028_0126, + &pci_ss_info_8086_24c4_1028_0163, + &pci_ss_info_8086_24c4_1028_0196, + &pci_ss_info_8086_24c4_103c_088c, + &pci_ss_info_8086_24c4_103c_0890, + &pci_ss_info_8086_24c4_103c_08b0, + &pci_ss_info_8086_24c4_1071_8160, + &pci_ss_info_8086_24c4_1462_5800, + &pci_ss_info_8086_24c4_1509_2990, + &pci_ss_info_8086_24c4_1734_1004, + &pci_ss_info_8086_24c4_4c53_1090, + &pci_ss_info_8086_24c4_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24c5[] = { + &pci_ss_info_8086_24c5_0e11_00b8, + &pci_ss_info_8086_24c5_1014_0267, + &pci_ss_info_8086_24c5_1014_055f, + &pci_ss_info_8086_24c5_1025_005a, + &pci_ss_info_8086_24c5_1028_0139, + &pci_ss_info_8086_24c5_1028_0163, + &pci_ss_info_8086_24c5_1028_0196, + &pci_ss_info_8086_24c5_103c_088c, + &pci_ss_info_8086_24c5_103c_0890, + &pci_ss_info_8086_24c5_103c_08b0, + &pci_ss_info_8086_24c5_1071_8160, + &pci_ss_info_8086_24c5_1458_a002, + &pci_ss_info_8086_24c5_1462_5800, + &pci_ss_info_8086_24c5_1734_1005, + &pci_ss_info_8086_24c5_1734_1055, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24c6[] = { + &pci_ss_info_8086_24c6_1014_0559, + &pci_ss_info_8086_24c6_1025_003c, + &pci_ss_info_8086_24c6_1025_005a, + &pci_ss_info_8086_24c6_1028_0196, + &pci_ss_info_8086_24c6_103c_088c, + &pci_ss_info_8086_24c6_103c_0890, + &pci_ss_info_8086_24c6_103c_08b0, + &pci_ss_info_8086_24c6_1071_8160, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24c7[] = { + &pci_ss_info_8086_24c7_1014_0267, + &pci_ss_info_8086_24c7_1014_052d, + &pci_ss_info_8086_24c7_1025_005a, + &pci_ss_info_8086_24c7_1028_0126, + &pci_ss_info_8086_24c7_1028_0163, + &pci_ss_info_8086_24c7_1028_0196, + &pci_ss_info_8086_24c7_103c_088c, + &pci_ss_info_8086_24c7_103c_0890, + &pci_ss_info_8086_24c7_103c_08b0, + &pci_ss_info_8086_24c7_1071_8160, + &pci_ss_info_8086_24c7_1462_5800, + &pci_ss_info_8086_24c7_1509_2990, + &pci_ss_info_8086_24c7_1734_1004, + &pci_ss_info_8086_24c7_4c53_1090, + &pci_ss_info_8086_24c7_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24ca[] = { + &pci_ss_info_8086_24ca_1014_052d, + &pci_ss_info_8086_24ca_1025_005a, + &pci_ss_info_8086_24ca_1028_0163, + &pci_ss_info_8086_24ca_1028_0196, + &pci_ss_info_8086_24ca_103c_088c, + &pci_ss_info_8086_24ca_103c_0890, + &pci_ss_info_8086_24ca_103c_08b0, + &pci_ss_info_8086_24ca_1071_8160, + &pci_ss_info_8086_24ca_1734_1055, + &pci_ss_info_8086_24ca_8086_4541, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24cb[] = { + &pci_ss_info_8086_24cb_1014_0267, + &pci_ss_info_8086_24cb_1028_0126, + &pci_ss_info_8086_24cb_1458_24c2, + &pci_ss_info_8086_24cb_1462_5800, + &pci_ss_info_8086_24cb_1734_1004, + &pci_ss_info_8086_24cb_4c53_1090, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24cc[] = { + &pci_ss_info_8086_24cc_1734_1055, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24cd[] = { + &pci_ss_info_8086_24cd_1014_0267, + &pci_ss_info_8086_24cd_1014_052e, + &pci_ss_info_8086_24cd_1025_005a, + &pci_ss_info_8086_24cd_1028_011d, + &pci_ss_info_8086_24cd_1028_0126, + &pci_ss_info_8086_24cd_1028_0139, + &pci_ss_info_8086_24cd_1028_0163, + &pci_ss_info_8086_24cd_1028_0196, + &pci_ss_info_8086_24cd_103c_088c, + &pci_ss_info_8086_24cd_103c_0890, + &pci_ss_info_8086_24cd_103c_08b0, + &pci_ss_info_8086_24cd_1071_8160, + &pci_ss_info_8086_24cd_1179_ff00, + &pci_ss_info_8086_24cd_1462_3981, + &pci_ss_info_8086_24cd_1509_1968, + &pci_ss_info_8086_24cd_1734_1004, + &pci_ss_info_8086_24cd_1734_1055, + &pci_ss_info_8086_24cd_4c53_1090, + NULL +}; +#define pci_ss_list_8086_24d0 NULL +static const pciSubsystemInfo *pci_ss_list_8086_24d1[] = { + &pci_ss_info_8086_24d1_1028_0169, + &pci_ss_info_8086_24d1_1028_019a, + &pci_ss_info_8086_24d1_103c_12bc, + &pci_ss_info_8086_24d1_1043_80a6, + &pci_ss_info_8086_24d1_1458_24d1, + &pci_ss_info_8086_24d1_1462_7280, + &pci_ss_info_8086_24d1_15d9_4580, + &pci_ss_info_8086_24d1_8086_3427, + &pci_ss_info_8086_24d1_8086_4246, + &pci_ss_info_8086_24d1_8086_4c43, + &pci_ss_info_8086_24d1_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24d2[] = { + &pci_ss_info_8086_24d2_1014_02ed, + &pci_ss_info_8086_24d2_1028_0169, + &pci_ss_info_8086_24d2_1028_0183, + &pci_ss_info_8086_24d2_1028_019a, + &pci_ss_info_8086_24d2_103c_006a, + &pci_ss_info_8086_24d2_103c_12bc, + &pci_ss_info_8086_24d2_1043_80a6, + &pci_ss_info_8086_24d2_1458_24d2, + &pci_ss_info_8086_24d2_1462_7280, + &pci_ss_info_8086_24d2_15d9_4580, + &pci_ss_info_8086_24d2_1734_101c, + &pci_ss_info_8086_24d2_8086_3427, + &pci_ss_info_8086_24d2_8086_4246, + &pci_ss_info_8086_24d2_8086_4c43, + &pci_ss_info_8086_24d2_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24d3[] = { + &pci_ss_info_8086_24d3_1014_02ed, + &pci_ss_info_8086_24d3_1028_0156, + &pci_ss_info_8086_24d3_1028_0169, + &pci_ss_info_8086_24d3_1043_80a6, + &pci_ss_info_8086_24d3_1458_24d2, + &pci_ss_info_8086_24d3_1462_7280, + &pci_ss_info_8086_24d3_15d9_4580, + &pci_ss_info_8086_24d3_1734_101c, + &pci_ss_info_8086_24d3_8086_3427, + &pci_ss_info_8086_24d3_8086_4246, + &pci_ss_info_8086_24d3_8086_4c43, + &pci_ss_info_8086_24d3_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24d4[] = { + &pci_ss_info_8086_24d4_1014_02ed, + &pci_ss_info_8086_24d4_1028_0169, + &pci_ss_info_8086_24d4_1028_0183, + &pci_ss_info_8086_24d4_1028_019a, + &pci_ss_info_8086_24d4_103c_006a, + &pci_ss_info_8086_24d4_103c_12bc, + &pci_ss_info_8086_24d4_1043_80a6, + &pci_ss_info_8086_24d4_1458_24d2, + &pci_ss_info_8086_24d4_1462_7280, + &pci_ss_info_8086_24d4_15d9_4580, + &pci_ss_info_8086_24d4_1734_101c, + &pci_ss_info_8086_24d4_8086_3427, + &pci_ss_info_8086_24d4_8086_4246, + &pci_ss_info_8086_24d4_8086_4c43, + &pci_ss_info_8086_24d4_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24d5[] = { + &pci_ss_info_8086_24d5_1028_0169, + &pci_ss_info_8086_24d5_103c_006a, + &pci_ss_info_8086_24d5_103c_12bc, + &pci_ss_info_8086_24d5_1043_80f3, + &pci_ss_info_8086_24d5_1043_810f, + &pci_ss_info_8086_24d5_1458_a002, + &pci_ss_info_8086_24d5_1462_0080, + &pci_ss_info_8086_24d5_1462_7280, + &pci_ss_info_8086_24d5_8086_a000, + &pci_ss_info_8086_24d5_8086_e000, + &pci_ss_info_8086_24d5_8086_e001, + &pci_ss_info_8086_24d5_8086_e002, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24d6[] = { + &pci_ss_info_8086_24d6_103c_006a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24d7[] = { + &pci_ss_info_8086_24d7_1014_02ed, + &pci_ss_info_8086_24d7_1028_0169, + &pci_ss_info_8086_24d7_1028_0183, + &pci_ss_info_8086_24d7_103c_006a, + &pci_ss_info_8086_24d7_103c_12bc, + &pci_ss_info_8086_24d7_1043_80a6, + &pci_ss_info_8086_24d7_1458_24d2, + &pci_ss_info_8086_24d7_1462_7280, + &pci_ss_info_8086_24d7_15d9_4580, + &pci_ss_info_8086_24d7_1734_101c, + &pci_ss_info_8086_24d7_8086_3427, + &pci_ss_info_8086_24d7_8086_4246, + &pci_ss_info_8086_24d7_8086_4c43, + &pci_ss_info_8086_24d7_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24db[] = { + &pci_ss_info_8086_24db_1014_02ed, + &pci_ss_info_8086_24db_1028_0169, + &pci_ss_info_8086_24db_1028_019a, + &pci_ss_info_8086_24db_103c_006a, + &pci_ss_info_8086_24db_103c_12bc, + &pci_ss_info_8086_24db_1043_80a6, + &pci_ss_info_8086_24db_1458_24d2, + &pci_ss_info_8086_24db_1462_7280, + &pci_ss_info_8086_24db_1462_7580, + &pci_ss_info_8086_24db_15d9_4580, + &pci_ss_info_8086_24db_1734_101c, + &pci_ss_info_8086_24db_8086_24db, + &pci_ss_info_8086_24db_8086_3427, + &pci_ss_info_8086_24db_8086_4246, + &pci_ss_info_8086_24db_8086_4c43, + &pci_ss_info_8086_24db_8086_524c, + NULL +}; +#define pci_ss_list_8086_24dc NULL +static const pciSubsystemInfo *pci_ss_list_8086_24dd[] = { + &pci_ss_info_8086_24dd_1014_02ed, + &pci_ss_info_8086_24dd_1028_0169, + &pci_ss_info_8086_24dd_1028_0183, + &pci_ss_info_8086_24dd_1028_019a, + &pci_ss_info_8086_24dd_103c_006a, + &pci_ss_info_8086_24dd_103c_12bc, + &pci_ss_info_8086_24dd_1043_80a6, + &pci_ss_info_8086_24dd_1458_5006, + &pci_ss_info_8086_24dd_1462_7280, + &pci_ss_info_8086_24dd_8086_3427, + &pci_ss_info_8086_24dd_8086_4246, + &pci_ss_info_8086_24dd_8086_4c43, + &pci_ss_info_8086_24dd_8086_524c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_24de[] = { + &pci_ss_info_8086_24de_1014_02ed, + &pci_ss_info_8086_24de_1028_0169, + &pci_ss_info_8086_24de_1043_80a6, + &pci_ss_info_8086_24de_1458_24d2, + &pci_ss_info_8086_24de_1462_7280, + &pci_ss_info_8086_24de_15d9_4580, + &pci_ss_info_8086_24de_1734_101c, + &pci_ss_info_8086_24de_8086_3427, + &pci_ss_info_8086_24de_8086_4246, + &pci_ss_info_8086_24de_8086_4c43, + &pci_ss_info_8086_24de_8086_524c, + NULL +}; +#define pci_ss_list_8086_24df NULL +static const pciSubsystemInfo *pci_ss_list_8086_2500[] = { + &pci_ss_info_8086_2500_1028_0095, + &pci_ss_info_8086_2500_1043_801c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2501[] = { + &pci_ss_info_8086_2501_1043_801c, + NULL +}; +#define pci_ss_list_8086_250b NULL +#define pci_ss_list_8086_250f NULL +#define pci_ss_list_8086_2520 NULL +#define pci_ss_list_8086_2521 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2530[] = { + &pci_ss_info_8086_2530_1028_00c7, + &pci_ss_info_8086_2530_147b_0507, + NULL +}; +#define pci_ss_list_8086_2531 NULL +#define pci_ss_list_8086_2532 NULL +#define pci_ss_list_8086_2533 NULL +#define pci_ss_list_8086_2534 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2540[] = { + &pci_ss_info_8086_2540_15d9_3480, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2541[] = { + &pci_ss_info_8086_2541_15d9_3480, + &pci_ss_info_8086_2541_4c53_1090, + &pci_ss_info_8086_2541_8086_3424, + NULL +}; +#define pci_ss_list_8086_2543 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2544[] = { + &pci_ss_info_8086_2544_4c53_1090, + NULL +}; +#define pci_ss_list_8086_2545 NULL +#define pci_ss_list_8086_2546 NULL +#define pci_ss_list_8086_2547 NULL +#define pci_ss_list_8086_2548 NULL +static const pciSubsystemInfo *pci_ss_list_8086_254c[] = { + &pci_ss_info_8086_254c_4c53_1090, + &pci_ss_info_8086_254c_8086_3424, + NULL +}; +#define pci_ss_list_8086_2550 NULL +#define pci_ss_list_8086_2551 NULL +#define pci_ss_list_8086_2552 NULL +#define pci_ss_list_8086_2553 NULL +#define pci_ss_list_8086_2554 NULL +#define pci_ss_list_8086_255d NULL +static const pciSubsystemInfo *pci_ss_list_8086_2560[] = { + &pci_ss_info_8086_2560_1028_0126, + &pci_ss_info_8086_2560_1458_2560, + &pci_ss_info_8086_2560_1462_5800, + NULL +}; +#define pci_ss_list_8086_2561 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2562[] = { + &pci_ss_info_8086_2562_0e11_00b9, + &pci_ss_info_8086_2562_1014_0267, + &pci_ss_info_8086_2562_1734_1004, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2570[] = { + &pci_ss_info_8086_2570_103c_006a, + &pci_ss_info_8086_2570_1043_80f2, + &pci_ss_info_8086_2570_1458_2570, + NULL +}; +#define pci_ss_list_8086_2571 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2572[] = { + &pci_ss_info_8086_2572_1028_019d, + &pci_ss_info_8086_2572_103c_12bc, + &pci_ss_info_8086_2572_1043_80a5, + &pci_ss_info_8086_2572_8086_4246, + &pci_ss_info_8086_2572_8086_4c43, + NULL +}; +#define pci_ss_list_8086_2573 NULL +#define pci_ss_list_8086_2576 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2578[] = { + &pci_ss_info_8086_2578_1458_2578, + &pci_ss_info_8086_2578_1462_7580, + &pci_ss_info_8086_2578_15d9_4580, + NULL +}; +#define pci_ss_list_8086_2579 NULL +#define pci_ss_list_8086_257b NULL +#define pci_ss_list_8086_257e NULL +static const pciSubsystemInfo *pci_ss_list_8086_2580[] = { + &pci_ss_info_8086_2580_1458_2580, + &pci_ss_info_8086_2580_1462_7028, + &pci_ss_info_8086_2580_1734_105b, + NULL +}; +#define pci_ss_list_8086_2581 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2582[] = { + &pci_ss_info_8086_2582_1028_1079, + &pci_ss_info_8086_2582_103c_3006, + &pci_ss_info_8086_2582_1043_2582, + &pci_ss_info_8086_2582_1458_2582, + &pci_ss_info_8086_2582_1734_105b, + NULL +}; +#define pci_ss_list_8086_2584 NULL +#define pci_ss_list_8086_2585 NULL +#define pci_ss_list_8086_2588 NULL +#define pci_ss_list_8086_2589 NULL +#define pci_ss_list_8086_258a NULL +static const pciSubsystemInfo *pci_ss_list_8086_2590[] = { + &pci_ss_info_8086_2590_1028_0182, + &pci_ss_info_8086_2590_103c_099c, + &pci_ss_info_8086_2590_a304_81b7, + NULL +}; +#define pci_ss_list_8086_2591 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2592[] = { + &pci_ss_info_8086_2592_103c_099c, + &pci_ss_info_8086_2592_103c_308a, + &pci_ss_info_8086_2592_1043_1881, + NULL +}; +#define pci_ss_list_8086_25a1 NULL +static const pciSubsystemInfo *pci_ss_list_8086_25a2[] = { + &pci_ss_info_8086_25a2_1775_10d0, + &pci_ss_info_8086_25a2_1775_ce90, + &pci_ss_info_8086_25a2_4c53_10b0, + &pci_ss_info_8086_25a2_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25a3[] = { + &pci_ss_info_8086_25a3_1775_ce90, + &pci_ss_info_8086_25a3_4c53_10b0, + &pci_ss_info_8086_25a3_4c53_10d0, + &pci_ss_info_8086_25a3_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25a4[] = { + &pci_ss_info_8086_25a4_1775_10d0, + &pci_ss_info_8086_25a4_1775_ce90, + &pci_ss_info_8086_25a4_4c53_10b0, + &pci_ss_info_8086_25a4_4c53_10d0, + &pci_ss_info_8086_25a4_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25a6[] = { + &pci_ss_info_8086_25a6_1775_ce90, + &pci_ss_info_8086_25a6_4c53_10b0, + NULL +}; +#define pci_ss_list_8086_25a7 NULL +static const pciSubsystemInfo *pci_ss_list_8086_25a9[] = { + &pci_ss_info_8086_25a9_1775_10d0, + &pci_ss_info_8086_25a9_1775_ce90, + &pci_ss_info_8086_25a9_4c53_10b0, + &pci_ss_info_8086_25a9_4c53_10d0, + &pci_ss_info_8086_25a9_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25aa[] = { + &pci_ss_info_8086_25aa_1775_ce90, + &pci_ss_info_8086_25aa_4c53_10b0, + &pci_ss_info_8086_25aa_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25ab[] = { + &pci_ss_info_8086_25ab_1775_10d0, + &pci_ss_info_8086_25ab_1775_ce90, + &pci_ss_info_8086_25ab_4c53_10b0, + &pci_ss_info_8086_25ab_4c53_10d0, + &pci_ss_info_8086_25ab_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25ac[] = { + &pci_ss_info_8086_25ac_1775_10d0, + &pci_ss_info_8086_25ac_1775_ce90, + &pci_ss_info_8086_25ac_4c53_10b0, + &pci_ss_info_8086_25ac_4c53_10d0, + &pci_ss_info_8086_25ac_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_25ad[] = { + &pci_ss_info_8086_25ad_1775_10d0, + &pci_ss_info_8086_25ad_1775_ce90, + &pci_ss_info_8086_25ad_4c53_10b0, + &pci_ss_info_8086_25ad_4c53_10d0, + &pci_ss_info_8086_25ad_4c53_10e0, + NULL +}; +#define pci_ss_list_8086_25ae NULL +static const pciSubsystemInfo *pci_ss_list_8086_25b0[] = { + &pci_ss_info_8086_25b0_4c53_10d0, + &pci_ss_info_8086_25b0_4c53_10e0, + NULL +}; +#define pci_ss_list_8086_25c0 NULL +#define pci_ss_list_8086_25d0 NULL +#define pci_ss_list_8086_25d4 NULL +#define pci_ss_list_8086_25d8 NULL +#define pci_ss_list_8086_25e2 NULL +#define pci_ss_list_8086_25e3 NULL +#define pci_ss_list_8086_25e4 NULL +#define pci_ss_list_8086_25e5 NULL +#define pci_ss_list_8086_25e6 NULL +#define pci_ss_list_8086_25e7 NULL +#define pci_ss_list_8086_25f0 NULL +#define pci_ss_list_8086_25f1 NULL +#define pci_ss_list_8086_25f3 NULL +#define pci_ss_list_8086_25f5 NULL +#define pci_ss_list_8086_25f6 NULL +#define pci_ss_list_8086_25f7 NULL +#define pci_ss_list_8086_25f8 NULL +#define pci_ss_list_8086_25f9 NULL +#define pci_ss_list_8086_25fa NULL +#define pci_ss_list_8086_2600 NULL +#define pci_ss_list_8086_2601 NULL +#define pci_ss_list_8086_2602 NULL +#define pci_ss_list_8086_2603 NULL +#define pci_ss_list_8086_2604 NULL +#define pci_ss_list_8086_2605 NULL +#define pci_ss_list_8086_2606 NULL +#define pci_ss_list_8086_2607 NULL +#define pci_ss_list_8086_2608 NULL +#define pci_ss_list_8086_2609 NULL +#define pci_ss_list_8086_260a NULL +#define pci_ss_list_8086_260c NULL +#define pci_ss_list_8086_2610 NULL +#define pci_ss_list_8086_2611 NULL +#define pci_ss_list_8086_2612 NULL +#define pci_ss_list_8086_2613 NULL +#define pci_ss_list_8086_2614 NULL +#define pci_ss_list_8086_2615 NULL +#define pci_ss_list_8086_2617 NULL +#define pci_ss_list_8086_2618 NULL +#define pci_ss_list_8086_2619 NULL +#define pci_ss_list_8086_261a NULL +#define pci_ss_list_8086_261b NULL +#define pci_ss_list_8086_261c NULL +#define pci_ss_list_8086_261d NULL +#define pci_ss_list_8086_261e NULL +#define pci_ss_list_8086_2620 NULL +#define pci_ss_list_8086_2621 NULL +#define pci_ss_list_8086_2622 NULL +#define pci_ss_list_8086_2623 NULL +#define pci_ss_list_8086_2624 NULL +#define pci_ss_list_8086_2625 NULL +#define pci_ss_list_8086_2626 NULL +#define pci_ss_list_8086_2627 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2640[] = { + &pci_ss_info_8086_2640_1462_7028, + &pci_ss_info_8086_2640_1734_105c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2641[] = { + &pci_ss_info_8086_2641_103c_099c, + NULL +}; +#define pci_ss_list_8086_2642 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2651[] = { + &pci_ss_info_8086_2651_1028_0179, + &pci_ss_info_8086_2651_1043_2601, + &pci_ss_info_8086_2651_1734_105c, + &pci_ss_info_8086_2651_8086_4147, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2652[] = { + &pci_ss_info_8086_2652_1462_7028, + NULL +}; +#define pci_ss_list_8086_2653 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2658[] = { + &pci_ss_info_8086_2658_1028_0179, + &pci_ss_info_8086_2658_103c_099c, + &pci_ss_info_8086_2658_1043_80a6, + &pci_ss_info_8086_2658_1458_2558, + &pci_ss_info_8086_2658_1462_7028, + &pci_ss_info_8086_2658_1734_105c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2659[] = { + &pci_ss_info_8086_2659_1028_0179, + &pci_ss_info_8086_2659_103c_099c, + &pci_ss_info_8086_2659_1043_80a6, + &pci_ss_info_8086_2659_1458_2659, + &pci_ss_info_8086_2659_1462_7028, + &pci_ss_info_8086_2659_1734_105c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_265a[] = { + &pci_ss_info_8086_265a_1028_0179, + &pci_ss_info_8086_265a_103c_099c, + &pci_ss_info_8086_265a_1043_80a6, + &pci_ss_info_8086_265a_1458_265a, + &pci_ss_info_8086_265a_1462_7028, + &pci_ss_info_8086_265a_1734_105c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_265b[] = { + &pci_ss_info_8086_265b_1028_0179, + &pci_ss_info_8086_265b_103c_099c, + &pci_ss_info_8086_265b_1043_80a6, + &pci_ss_info_8086_265b_1458_265a, + &pci_ss_info_8086_265b_1462_7028, + &pci_ss_info_8086_265b_1734_105c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_265c[] = { + &pci_ss_info_8086_265c_1028_0179, + &pci_ss_info_8086_265c_103c_099c, + &pci_ss_info_8086_265c_1043_80a6, + &pci_ss_info_8086_265c_1458_5006, + &pci_ss_info_8086_265c_1462_7028, + &pci_ss_info_8086_265c_1734_105c, + &pci_ss_info_8086_265c_8086_265c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2660[] = { + &pci_ss_info_8086_2660_103c_099c, + NULL +}; +#define pci_ss_list_8086_2662 NULL +#define pci_ss_list_8086_2664 NULL +#define pci_ss_list_8086_2666 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2668[] = { + &pci_ss_info_8086_2668_103c_2a09, + &pci_ss_info_8086_2668_1043_814e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_266a[] = { + &pci_ss_info_8086_266a_1028_0179, + &pci_ss_info_8086_266a_1043_80a6, + &pci_ss_info_8086_266a_1458_266a, + &pci_ss_info_8086_266a_1462_7028, + &pci_ss_info_8086_266a_1734_105c, + NULL +}; +#define pci_ss_list_8086_266c NULL +static const pciSubsystemInfo *pci_ss_list_8086_266d[] = { + &pci_ss_info_8086_266d_1025_006a, + &pci_ss_info_8086_266d_103c_099c, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_266e[] = { + &pci_ss_info_8086_266e_1025_006a, + &pci_ss_info_8086_266e_1028_0179, + &pci_ss_info_8086_266e_1028_0182, + &pci_ss_info_8086_266e_1028_0188, + &pci_ss_info_8086_266e_103c_0944, + &pci_ss_info_8086_266e_103c_099c, + &pci_ss_info_8086_266e_103c_3006, + &pci_ss_info_8086_266e_1458_a002, + &pci_ss_info_8086_266e_152d_0745, + &pci_ss_info_8086_266e_1734_105a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_266f[] = { + &pci_ss_info_8086_266f_103c_099c, + &pci_ss_info_8086_266f_1043_80a6, + &pci_ss_info_8086_266f_1458_266f, + &pci_ss_info_8086_266f_1462_7028, + &pci_ss_info_8086_266f_1734_105c, + NULL +}; +#define pci_ss_list_8086_2670 NULL +#define pci_ss_list_8086_2680 NULL +#define pci_ss_list_8086_2681 NULL +#define pci_ss_list_8086_2682 NULL +#define pci_ss_list_8086_2683 NULL +#define pci_ss_list_8086_2688 NULL +#define pci_ss_list_8086_2689 NULL +#define pci_ss_list_8086_268a NULL +#define pci_ss_list_8086_268b NULL +#define pci_ss_list_8086_268c NULL +#define pci_ss_list_8086_2690 NULL +#define pci_ss_list_8086_2692 NULL +#define pci_ss_list_8086_2694 NULL +#define pci_ss_list_8086_2696 NULL +#define pci_ss_list_8086_2698 NULL +#define pci_ss_list_8086_2699 NULL +#define pci_ss_list_8086_269a NULL +#define pci_ss_list_8086_269b NULL +#define pci_ss_list_8086_269e NULL +static const pciSubsystemInfo *pci_ss_list_8086_2770[] = { + &pci_ss_info_8086_2770_107b_5048, + &pci_ss_info_8086_2770_8086_544e, + NULL +}; +#define pci_ss_list_8086_2771 NULL +static const pciSubsystemInfo *pci_ss_list_8086_2772[] = { + &pci_ss_info_8086_2772_8086_544e, + NULL +}; +#define pci_ss_list_8086_2774 NULL +#define pci_ss_list_8086_2775 NULL +#define pci_ss_list_8086_2776 NULL +#define pci_ss_list_8086_2778 NULL +#define pci_ss_list_8086_2779 NULL +#define pci_ss_list_8086_277a NULL +#define pci_ss_list_8086_277c NULL +#define pci_ss_list_8086_277d NULL +static const pciSubsystemInfo *pci_ss_list_8086_2782[] = { + &pci_ss_info_8086_2782_1043_2582, + &pci_ss_info_8086_2782_1734_105b, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_2792[] = { + &pci_ss_info_8086_2792_103c_099c, + &pci_ss_info_8086_2792_1043_1881, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_27a0[] = { + &pci_ss_info_8086_27a0_17aa_2017, + NULL +}; +#define pci_ss_list_8086_27a1 NULL +static const pciSubsystemInfo *pci_ss_list_8086_27a2[] = { + &pci_ss_info_8086_27a2_17aa_201a, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_27a6[] = { + &pci_ss_info_8086_27a6_17aa_201a, + NULL +}; +#define pci_ss_list_8086_27b0 NULL +static const pciSubsystemInfo *pci_ss_list_8086_27b8[] = { + &pci_ss_info_8086_27b8_107b_5048, + &pci_ss_info_8086_27b8_8086_544e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_27b9[] = { + &pci_ss_info_8086_27b9_17aa_2009, + NULL +}; +#define pci_ss_list_8086_27bd NULL +static const pciSubsystemInfo *pci_ss_list_8086_27c0[] = { + &pci_ss_info_8086_27c0_107b_5048, + &pci_ss_info_8086_27c0_8086_544e, + NULL +}; +#define pci_ss_list_8086_27c1 NULL +#define pci_ss_list_8086_27c3 NULL +#define pci_ss_list_8086_27c4 NULL +static const pciSubsystemInfo *pci_ss_list_8086_27c5[] = { + &pci_ss_info_8086_27c5_17aa_200d, + NULL +}; +#define pci_ss_list_8086_27c6 NULL +static const pciSubsystemInfo *pci_ss_list_8086_27c8[] = { + &pci_ss_info_8086_27c8_107b_5048, + &pci_ss_info_8086_27c8_17aa_200a, + &pci_ss_info_8086_27c8_8086_544e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_27c9[] = { + &pci_ss_info_8086_27c9_107b_5048, + &pci_ss_info_8086_27c9_17aa_200a, + &pci_ss_info_8086_27c9_8086_544e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_27ca[] = { + &pci_ss_info_8086_27ca_107b_5048, + &pci_ss_info_8086_27ca_17aa_200a, + &pci_ss_info_8086_27ca_8086_544e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_27cb[] = { + &pci_ss_info_8086_27cb_107b_5048, + &pci_ss_info_8086_27cb_17aa_200a, + &pci_ss_info_8086_27cb_8086_544e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_27cc[] = { + &pci_ss_info_8086_27cc_17aa_200b, + &pci_ss_info_8086_27cc_8086_544e, + NULL +}; +#define pci_ss_list_8086_27d0 NULL +#define pci_ss_list_8086_27d2 NULL +#define pci_ss_list_8086_27d4 NULL +#define pci_ss_list_8086_27d6 NULL +static const pciSubsystemInfo *pci_ss_list_8086_27d8[] = { + &pci_ss_info_8086_27d8_107b_5048, + &pci_ss_info_8086_27d8_152d_0753, + &pci_ss_info_8086_27d8_17aa_2010, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_27da[] = { + &pci_ss_info_8086_27da_17aa_200f, + &pci_ss_info_8086_27da_8086_544e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_27dc[] = { + &pci_ss_info_8086_27dc_8086_308d, + NULL +}; +#define pci_ss_list_8086_27dd NULL +#define pci_ss_list_8086_27de NULL +static const pciSubsystemInfo *pci_ss_list_8086_27df[] = { + &pci_ss_info_8086_27df_107b_5048, + &pci_ss_info_8086_27df_17aa_200c, + &pci_ss_info_8086_27df_8086_544e, + NULL +}; +#define pci_ss_list_8086_27e0 NULL +#define pci_ss_list_8086_27e2 NULL +#define pci_ss_list_8086_2810 NULL +#define pci_ss_list_8086_2811 NULL +#define pci_ss_list_8086_2812 NULL +#define pci_ss_list_8086_2814 NULL +#define pci_ss_list_8086_2815 NULL +#define pci_ss_list_8086_2820 NULL +#define pci_ss_list_8086_2821 NULL +#define pci_ss_list_8086_2822 NULL +#define pci_ss_list_8086_2824 NULL +#define pci_ss_list_8086_2825 NULL +#define pci_ss_list_8086_2828 NULL +#define pci_ss_list_8086_2829 NULL +#define pci_ss_list_8086_282a NULL +#define pci_ss_list_8086_2830 NULL +#define pci_ss_list_8086_2831 NULL +#define pci_ss_list_8086_2832 NULL +#define pci_ss_list_8086_2834 NULL +#define pci_ss_list_8086_2835 NULL +#define pci_ss_list_8086_2836 NULL +#define pci_ss_list_8086_283a NULL +#define pci_ss_list_8086_283e NULL +#define pci_ss_list_8086_283f NULL +#define pci_ss_list_8086_2841 NULL +#define pci_ss_list_8086_2843 NULL +#define pci_ss_list_8086_2845 NULL +#define pci_ss_list_8086_2847 NULL +#define pci_ss_list_8086_2849 NULL +#define pci_ss_list_8086_284b NULL +#define pci_ss_list_8086_284f NULL +#define pci_ss_list_8086_2850 NULL +#define pci_ss_list_8086_2970 NULL +#define pci_ss_list_8086_2971 NULL +#define pci_ss_list_8086_2972 NULL +#define pci_ss_list_8086_2973 NULL +#define pci_ss_list_8086_2974 NULL +#define pci_ss_list_8086_2975 NULL +#define pci_ss_list_8086_2976 NULL +#define pci_ss_list_8086_2977 NULL +#define pci_ss_list_8086_2980 NULL +#define pci_ss_list_8086_2981 NULL +#define pci_ss_list_8086_2982 NULL +#define pci_ss_list_8086_2990 NULL +#define pci_ss_list_8086_2991 NULL +#define pci_ss_list_8086_2992 NULL +#define pci_ss_list_8086_2993 NULL +#define pci_ss_list_8086_2994 NULL +#define pci_ss_list_8086_2995 NULL +#define pci_ss_list_8086_2996 NULL +#define pci_ss_list_8086_2997 NULL +#define pci_ss_list_8086_29a0 NULL +#define pci_ss_list_8086_29a1 NULL +#define pci_ss_list_8086_29a2 NULL +#define pci_ss_list_8086_29a3 NULL +#define pci_ss_list_8086_29a4 NULL +#define pci_ss_list_8086_29a5 NULL +#define pci_ss_list_8086_29a6 NULL +#define pci_ss_list_8086_29a7 NULL +#define pci_ss_list_8086_2a00 NULL +#define pci_ss_list_8086_2a01 NULL +#define pci_ss_list_8086_2a02 NULL +#define pci_ss_list_8086_2a03 NULL +#define pci_ss_list_8086_2a04 NULL +#define pci_ss_list_8086_2a05 NULL +#define pci_ss_list_8086_2a06 NULL +#define pci_ss_list_8086_2a07 NULL +#define pci_ss_list_8086_3092 NULL +#define pci_ss_list_8086_3200 NULL +static const pciSubsystemInfo *pci_ss_list_8086_3340[] = { + &pci_ss_info_8086_3340_1025_005a, + &pci_ss_info_8086_3340_103c_088c, + &pci_ss_info_8086_3340_103c_0890, + &pci_ss_info_8086_3340_103c_08b0, + NULL +}; +#define pci_ss_list_8086_3341 NULL +#define pci_ss_list_8086_3500 NULL +#define pci_ss_list_8086_3501 NULL +#define pci_ss_list_8086_3504 NULL +#define pci_ss_list_8086_3505 NULL +#define pci_ss_list_8086_350c NULL +#define pci_ss_list_8086_350d NULL +#define pci_ss_list_8086_3510 NULL +#define pci_ss_list_8086_3511 NULL +#define pci_ss_list_8086_3514 NULL +#define pci_ss_list_8086_3515 NULL +#define pci_ss_list_8086_3518 NULL +#define pci_ss_list_8086_3519 NULL +static const pciSubsystemInfo *pci_ss_list_8086_3575[] = { + &pci_ss_info_8086_3575_0e11_0030, + &pci_ss_info_8086_3575_1014_021d, + &pci_ss_info_8086_3575_104d_80e7, + NULL +}; +#define pci_ss_list_8086_3576 NULL +static const pciSubsystemInfo *pci_ss_list_8086_3577[] = { + &pci_ss_info_8086_3577_1014_0513, + NULL +}; +#define pci_ss_list_8086_3578 NULL +static const pciSubsystemInfo *pci_ss_list_8086_3580[] = { + &pci_ss_info_8086_3580_1014_055c, + &pci_ss_info_8086_3580_1028_0139, + &pci_ss_info_8086_3580_1028_0163, + &pci_ss_info_8086_3580_1028_0196, + &pci_ss_info_8086_3580_1734_1055, + &pci_ss_info_8086_3580_1775_10d0, + &pci_ss_info_8086_3580_1775_ce90, + &pci_ss_info_8086_3580_4c53_10b0, + &pci_ss_info_8086_3580_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3581[] = { + &pci_ss_info_8086_3581_1734_1055, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3582[] = { + &pci_ss_info_8086_3582_1014_0562, + &pci_ss_info_8086_3582_1028_0139, + &pci_ss_info_8086_3582_1028_0163, + &pci_ss_info_8086_3582_1775_10d0, + &pci_ss_info_8086_3582_1775_ce90, + &pci_ss_info_8086_3582_4c53_10b0, + &pci_ss_info_8086_3582_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3584[] = { + &pci_ss_info_8086_3584_1014_055d, + &pci_ss_info_8086_3584_1028_0139, + &pci_ss_info_8086_3584_1028_0163, + &pci_ss_info_8086_3584_1028_0196, + &pci_ss_info_8086_3584_1734_1055, + &pci_ss_info_8086_3584_1775_10d0, + &pci_ss_info_8086_3584_1775_ce90, + &pci_ss_info_8086_3584_4c53_10b0, + &pci_ss_info_8086_3584_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3585[] = { + &pci_ss_info_8086_3585_1014_055e, + &pci_ss_info_8086_3585_1028_0139, + &pci_ss_info_8086_3585_1028_0163, + &pci_ss_info_8086_3585_1028_0196, + &pci_ss_info_8086_3585_1734_1055, + &pci_ss_info_8086_3585_1775_10d0, + &pci_ss_info_8086_3585_1775_ce90, + &pci_ss_info_8086_3585_4c53_10b0, + &pci_ss_info_8086_3585_4c53_10e0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3590[] = { + &pci_ss_info_8086_3590_1028_019a, + &pci_ss_info_8086_3590_1734_103e, + &pci_ss_info_8086_3590_4c53_10d0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_3591[] = { + &pci_ss_info_8086_3591_1028_0169, + &pci_ss_info_8086_3591_4c53_10d0, + NULL +}; +#define pci_ss_list_8086_3592 NULL +#define pci_ss_list_8086_3593 NULL +static const pciSubsystemInfo *pci_ss_list_8086_3594[] = { + &pci_ss_info_8086_3594_4c53_10d0, + NULL +}; +#define pci_ss_list_8086_3595 NULL +#define pci_ss_list_8086_3596 NULL +#define pci_ss_list_8086_3597 NULL +#define pci_ss_list_8086_3598 NULL +#define pci_ss_list_8086_3599 NULL +#define pci_ss_list_8086_359a NULL +#define pci_ss_list_8086_359b NULL +static const pciSubsystemInfo *pci_ss_list_8086_359e[] = { + &pci_ss_info_8086_359e_1028_0169, + NULL +}; +#define pci_ss_list_8086_35b0 NULL +#define pci_ss_list_8086_35b1 NULL +#define pci_ss_list_8086_35b5 NULL +#define pci_ss_list_8086_35b6 NULL +#define pci_ss_list_8086_35b7 NULL +#define pci_ss_list_8086_35c8 NULL +#define pci_ss_list_8086_4220 NULL +static const pciSubsystemInfo *pci_ss_list_8086_4222[] = { + &pci_ss_info_8086_4222_8086_1005, + &pci_ss_info_8086_4222_8086_1034, + &pci_ss_info_8086_4222_8086_1044, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_4223[] = { + &pci_ss_info_8086_4223_1351_103c, + NULL +}; +#define pci_ss_list_8086_4224 NULL +static const pciSubsystemInfo *pci_ss_list_8086_4227[] = { + &pci_ss_info_8086_4227_8086_1011, + &pci_ss_info_8086_4227_8086_1014, + NULL +}; +#define pci_ss_list_8086_5001 NULL +#define pci_ss_list_8086_5200 NULL +static const pciSubsystemInfo *pci_ss_list_8086_5201[] = { + &pci_ss_info_8086_5201_8086_0001, + NULL +}; +#define pci_ss_list_8086_530d NULL +#define pci_ss_list_8086_7000 NULL +#define pci_ss_list_8086_7010 NULL +#define pci_ss_list_8086_7020 NULL +#define pci_ss_list_8086_7030 NULL +#define pci_ss_list_8086_7050 NULL +#define pci_ss_list_8086_7051 NULL +#define pci_ss_list_8086_7100 NULL +static const pciSubsystemInfo *pci_ss_list_8086_7110[] = { + &pci_ss_info_8086_7110_15ad_1976, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7111[] = { + &pci_ss_info_8086_7111_15ad_1976, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7112[] = { + &pci_ss_info_8086_7112_15ad_1976, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7113[] = { + &pci_ss_info_8086_7113_15ad_1976, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7120[] = { + &pci_ss_info_8086_7120_4c53_1040, + &pci_ss_info_8086_7120_4c53_1060, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7121[] = { + &pci_ss_info_8086_7121_4c53_1040, + &pci_ss_info_8086_7121_4c53_1060, + &pci_ss_info_8086_7121_8086_4341, + NULL +}; +#define pci_ss_list_8086_7122 NULL +#define pci_ss_list_8086_7123 NULL +#define pci_ss_list_8086_7124 NULL +#define pci_ss_list_8086_7125 NULL +#define pci_ss_list_8086_7126 NULL +#define pci_ss_list_8086_7128 NULL +#define pci_ss_list_8086_712a NULL +#define pci_ss_list_8086_7180 NULL +#define pci_ss_list_8086_7181 NULL +static const pciSubsystemInfo *pci_ss_list_8086_7190[] = { + &pci_ss_info_8086_7190_0e11_0500, + &pci_ss_info_8086_7190_0e11_b110, + &pci_ss_info_8086_7190_1028_008e, + &pci_ss_info_8086_7190_1179_0001, + &pci_ss_info_8086_7190_15ad_1976, + &pci_ss_info_8086_7190_4c53_1050, + &pci_ss_info_8086_7190_4c53_1051, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7191[] = { + &pci_ss_info_8086_7191_1028_008e, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7192[] = { + &pci_ss_info_8086_7192_0e11_0460, + &pci_ss_info_8086_7192_4c53_1000, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7194[] = { + &pci_ss_info_8086_7194_1033_0000, + &pci_ss_info_8086_7194_4c53_10a0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_8086_7195[] = { + &pci_ss_info_8086_7195_1033_80cc, + &pci_ss_info_8086_7195_10cf_1099, + &pci_ss_info_8086_7195_11d4_0040, + &pci_ss_info_8086_7195_11d4_0048, + NULL +}; +#define pci_ss_list_8086_7196 NULL +#define pci_ss_list_8086_7198 NULL +#define pci_ss_list_8086_7199 NULL +#define pci_ss_list_8086_719a NULL +#define pci_ss_list_8086_719b NULL +static const pciSubsystemInfo *pci_ss_list_8086_71a0[] = { + &pci_ss_info_8086_71a0_4c53_1050, + &pci_ss_info_8086_71a0_4c53_1051, + NULL +}; +#define pci_ss_list_8086_71a1 NULL +static const pciSubsystemInfo *pci_ss_list_8086_71a2[] = { + &pci_ss_info_8086_71a2_4c53_1000, + NULL +}; +#define pci_ss_list_8086_7600 NULL +#define pci_ss_list_8086_7601 NULL +#define pci_ss_list_8086_7602 NULL +#define pci_ss_list_8086_7603 NULL +static const pciSubsystemInfo *pci_ss_list_8086_7800[] = { + &pci_ss_info_8086_7800_003d_0008, + &pci_ss_info_8086_7800_003d_000b, + &pci_ss_info_8086_7800_1092_0100, + &pci_ss_info_8086_7800_10b4_201a, + &pci_ss_info_8086_7800_10b4_202f, + &pci_ss_info_8086_7800_8086_0000, + &pci_ss_info_8086_7800_8086_0100, + NULL +}; +#define pci_ss_list_8086_84c4 NULL +#define pci_ss_list_8086_84c5 NULL +#define pci_ss_list_8086_84ca NULL +#define pci_ss_list_8086_84cb NULL +#define pci_ss_list_8086_84e0 NULL +#define pci_ss_list_8086_84e1 NULL +#define pci_ss_list_8086_84e2 NULL +#define pci_ss_list_8086_84e3 NULL +#define pci_ss_list_8086_84e4 NULL +#define pci_ss_list_8086_84e6 NULL +#define pci_ss_list_8086_84ea NULL +static const pciSubsystemInfo *pci_ss_list_8086_8500[] = { + &pci_ss_info_8086_8500_1993_0ded, + &pci_ss_info_8086_8500_1993_0dee, + &pci_ss_info_8086_8500_1993_0def, + NULL +}; +#define pci_ss_list_8086_9000 NULL +#define pci_ss_list_8086_9001 NULL +#define pci_ss_list_8086_9002 NULL +#define pci_ss_list_8086_9004 NULL +#define pci_ss_list_8086_9621 NULL +#define pci_ss_list_8086_9622 NULL +#define pci_ss_list_8086_9641 NULL +#define pci_ss_list_8086_96a1 NULL +#define pci_ss_list_8086_b152 NULL +#define pci_ss_list_8086_b154 NULL +static const pciSubsystemInfo *pci_ss_list_8086_b555[] = { + &pci_ss_info_8086_b555_12c7_5005, + &pci_ss_info_8086_b555_12c7_5006, + &pci_ss_info_8086_b555_12d9_000a, + &pci_ss_info_8086_b555_4c53_1050, + &pci_ss_info_8086_b555_4c53_1051, + &pci_ss_info_8086_b555_e4bf_1000, + NULL +}; +#define pci_ss_list_8686_1010 NULL +#define pci_ss_list_8800_2008 NULL +#define pci_ss_list_8c4a_1980 NULL +#define pci_ss_list_8e2e_3000 NULL +#define pci_ss_list_9004_0078 NULL +#define pci_ss_list_9004_1078 NULL +#define pci_ss_list_9004_1160 NULL +#define pci_ss_list_9004_2178 NULL +#define pci_ss_list_9004_3860 NULL +#define pci_ss_list_9004_3b78 NULL +#define pci_ss_list_9004_5075 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_9004_5078[] = { + &pci_ss_info_9004_5078_9004_7850, + NULL +}; +#define pci_ss_list_9004_5175 NULL +#define pci_ss_list_9004_5178 NULL +#define pci_ss_list_9004_5275 NULL +#define pci_ss_list_9004_5278 NULL +#define pci_ss_list_9004_5375 NULL +#define pci_ss_list_9004_5378 NULL +#define pci_ss_list_9004_5475 NULL +#define pci_ss_list_9004_5478 NULL +#define pci_ss_list_9004_5575 NULL +#define pci_ss_list_9004_5578 NULL +static const pciSubsystemInfo *pci_ss_list_9004_5647[] = { + &pci_ss_info_9004_5647_9004_7710, + &pci_ss_info_9004_5647_9004_7711, + NULL +}; +#define pci_ss_list_9004_5675 NULL +#define pci_ss_list_9004_5678 NULL +#define pci_ss_list_9004_5775 NULL +#define pci_ss_list_9004_5778 NULL +#define pci_ss_list_9004_5800 NULL +#define pci_ss_list_9004_5900 NULL +#define pci_ss_list_9004_5905 NULL +#define pci_ss_list_9004_6038 NULL +static const pciSubsystemInfo *pci_ss_list_9004_6075[] = { + &pci_ss_info_9004_6075_9004_7560, + NULL +}; +#define pci_ss_list_9004_6078 NULL +static const pciSubsystemInfo *pci_ss_list_9004_6178[] = { + &pci_ss_info_9004_6178_9004_7861, + NULL +}; +#define pci_ss_list_9004_6278 NULL +#define pci_ss_list_9004_6378 NULL +#define pci_ss_list_9004_6478 NULL +#define pci_ss_list_9004_6578 NULL +#define pci_ss_list_9004_6678 NULL +#define pci_ss_list_9004_6778 NULL +static const pciSubsystemInfo *pci_ss_list_9004_6915[] = { + &pci_ss_info_9004_6915_9004_0008, + &pci_ss_info_9004_6915_9004_0009, + &pci_ss_info_9004_6915_9004_0010, + &pci_ss_info_9004_6915_9004_0018, + &pci_ss_info_9004_6915_9004_0019, + &pci_ss_info_9004_6915_9004_0020, + &pci_ss_info_9004_6915_9004_0028, + &pci_ss_info_9004_6915_9004_8008, + &pci_ss_info_9004_6915_9004_8009, + &pci_ss_info_9004_6915_9004_8010, + &pci_ss_info_9004_6915_9004_8018, + &pci_ss_info_9004_6915_9004_8019, + &pci_ss_info_9004_6915_9004_8020, + &pci_ss_info_9004_6915_9004_8028, + NULL +}; +#define pci_ss_list_9004_7078 NULL +#define pci_ss_list_9004_7178 NULL +#define pci_ss_list_9004_7278 NULL +#define pci_ss_list_9004_7378 NULL +#define pci_ss_list_9004_7478 NULL +#define pci_ss_list_9004_7578 NULL +#define pci_ss_list_9004_7678 NULL +#define pci_ss_list_9004_7710 NULL +#define pci_ss_list_9004_7711 NULL +#define pci_ss_list_9004_7778 NULL +#define pci_ss_list_9004_7810 NULL +static const pciSubsystemInfo *pci_ss_list_9004_7815[] = { + &pci_ss_info_9004_7815_9004_7815, + &pci_ss_info_9004_7815_9004_7840, + NULL +}; +#define pci_ss_list_9004_7850 NULL +#define pci_ss_list_9004_7855 NULL +#define pci_ss_list_9004_7860 NULL +#define pci_ss_list_9004_7870 NULL +#define pci_ss_list_9004_7871 NULL +#define pci_ss_list_9004_7872 NULL +#define pci_ss_list_9004_7873 NULL +#define pci_ss_list_9004_7874 NULL +#define pci_ss_list_9004_7880 NULL +#define pci_ss_list_9004_7890 NULL +#define pci_ss_list_9004_7891 NULL +#define pci_ss_list_9004_7892 NULL +#define pci_ss_list_9004_7893 NULL +#define pci_ss_list_9004_7894 NULL +static const pciSubsystemInfo *pci_ss_list_9004_7895[] = { + &pci_ss_info_9004_7895_9004_7890, + &pci_ss_info_9004_7895_9004_7891, + &pci_ss_info_9004_7895_9004_7892, + &pci_ss_info_9004_7895_9004_7894, + &pci_ss_info_9004_7895_9004_7895, + &pci_ss_info_9004_7895_9004_7896, + &pci_ss_info_9004_7895_9004_7897, + NULL +}; +#define pci_ss_list_9004_7896 NULL +#define pci_ss_list_9004_7897 NULL +static const pciSubsystemInfo *pci_ss_list_9004_8078[] = { + &pci_ss_info_9004_8078_9004_7880, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9004_8178[] = { + &pci_ss_info_9004_8178_9004_7881, + NULL +}; +#define pci_ss_list_9004_8278 NULL +#define pci_ss_list_9004_8378 NULL +#define pci_ss_list_9004_8478 NULL +#define pci_ss_list_9004_8578 NULL +#define pci_ss_list_9004_8678 NULL +static const pciSubsystemInfo *pci_ss_list_9004_8778[] = { + &pci_ss_info_9004_8778_9004_7887, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9004_8878[] = { + &pci_ss_info_9004_8878_9004_7888, + NULL +}; +#define pci_ss_list_9004_8b78 NULL +#define pci_ss_list_9004_ec78 NULL +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_9005_0010[] = { + &pci_ss_info_9005_0010_9005_2180, + &pci_ss_info_9005_0010_9005_8100, + &pci_ss_info_9005_0010_9005_a100, + &pci_ss_info_9005_0010_9005_a180, + &pci_ss_info_9005_0010_9005_e100, + NULL +}; +#define pci_ss_list_9005_0011 NULL +static const pciSubsystemInfo *pci_ss_list_9005_0013[] = { + &pci_ss_info_9005_0013_9005_0003, + &pci_ss_info_9005_0013_9005_000f, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_001f[] = { + &pci_ss_info_9005_001f_9005_000f, + &pci_ss_info_9005_001f_9005_a180, + NULL +}; +#define pci_ss_list_9005_0020 NULL +#define pci_ss_list_9005_002f NULL +#define pci_ss_list_9005_0030 NULL +#define pci_ss_list_9005_003f NULL +static const pciSubsystemInfo *pci_ss_list_9005_0050[] = { + &pci_ss_info_9005_0050_9005_f500, + &pci_ss_info_9005_0050_9005_ffff, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0051[] = { + &pci_ss_info_9005_0051_9005_b500, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0053[] = { + &pci_ss_info_9005_0053_9005_ffff, + NULL +}; +#define pci_ss_list_9005_005f NULL +static const pciSubsystemInfo *pci_ss_list_9005_0080[] = { + &pci_ss_info_9005_0080_0e11_e2a0, + &pci_ss_info_9005_0080_9005_6220, + &pci_ss_info_9005_0080_9005_62a0, + &pci_ss_info_9005_0080_9005_e220, + &pci_ss_info_9005_0080_9005_e2a0, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0081[] = { + &pci_ss_info_9005_0081_9005_62a1, + NULL +}; +#define pci_ss_list_9005_0083 NULL +static const pciSubsystemInfo *pci_ss_list_9005_008f[] = { + &pci_ss_info_9005_008f_1179_0001, + &pci_ss_info_9005_008f_15d9_9005, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_00c0[] = { + &pci_ss_info_9005_00c0_0e11_f620, + &pci_ss_info_9005_00c0_9005_f620, + NULL +}; +#define pci_ss_list_9005_00c1 NULL +#define pci_ss_list_9005_00c3 NULL +static const pciSubsystemInfo *pci_ss_list_9005_00c5[] = { + &pci_ss_info_9005_00c5_1028_00c5, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_00cf[] = { + &pci_ss_info_9005_00cf_1028_00ce, + &pci_ss_info_9005_00cf_1028_00d1, + &pci_ss_info_9005_00cf_1028_00d9, + &pci_ss_info_9005_00cf_10f1_2462, + &pci_ss_info_9005_00cf_15d9_9005, + &pci_ss_info_9005_00cf_8086_3411, + NULL +}; +#define pci_ss_list_9005_0241 NULL +static const pciSubsystemInfo *pci_ss_list_9005_0250[] = { + &pci_ss_info_9005_0250_1014_0279, + &pci_ss_info_9005_0250_1014_028c, + NULL +}; +#define pci_ss_list_9005_0279 NULL +static const pciSubsystemInfo *pci_ss_list_9005_0283[] = { + &pci_ss_info_9005_0283_9005_0283, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0284[] = { + &pci_ss_info_9005_0284_9005_0284, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0285[] = { + &pci_ss_info_9005_0285_0e11_0295, + &pci_ss_info_9005_0285_1014_02f2, + &pci_ss_info_9005_0285_1028_0287, + &pci_ss_info_9005_0285_1028_0291, + &pci_ss_info_9005_0285_103c_3227, + &pci_ss_info_9005_0285_17aa_0286, + &pci_ss_info_9005_0285_17aa_0287, + &pci_ss_info_9005_0285_9005_0285, + &pci_ss_info_9005_0285_9005_0286, + &pci_ss_info_9005_0285_9005_0287, + &pci_ss_info_9005_0285_9005_0288, + &pci_ss_info_9005_0285_9005_0289, + &pci_ss_info_9005_0285_9005_028a, + &pci_ss_info_9005_0285_9005_028b, + &pci_ss_info_9005_0285_9005_028e, + &pci_ss_info_9005_0285_9005_028f, + &pci_ss_info_9005_0285_9005_0290, + &pci_ss_info_9005_0285_9005_0292, + &pci_ss_info_9005_0285_9005_0293, + &pci_ss_info_9005_0285_9005_0294, + &pci_ss_info_9005_0285_9005_0296, + &pci_ss_info_9005_0285_9005_0297, + &pci_ss_info_9005_0285_9005_0298, + &pci_ss_info_9005_0285_9005_0299, + &pci_ss_info_9005_0285_9005_029a, + &pci_ss_info_9005_0285_9005_02b5, + &pci_ss_info_9005_0285_9005_02b6, + &pci_ss_info_9005_0285_9005_02b7, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0286[] = { + &pci_ss_info_9005_0286_1014_034d, + &pci_ss_info_9005_0286_1014_9540, + &pci_ss_info_9005_0286_1014_9580, + &pci_ss_info_9005_0286_9005_028c, + &pci_ss_info_9005_0286_9005_028d, + &pci_ss_info_9005_0286_9005_029b, + &pci_ss_info_9005_0286_9005_029c, + &pci_ss_info_9005_0286_9005_029d, + &pci_ss_info_9005_0286_9005_029e, + &pci_ss_info_9005_0286_9005_029f, + &pci_ss_info_9005_0286_9005_02a0, + &pci_ss_info_9005_0286_9005_02a1, + &pci_ss_info_9005_0286_9005_02a2, + &pci_ss_info_9005_0286_9005_02a3, + &pci_ss_info_9005_0286_9005_02a4, + &pci_ss_info_9005_0286_9005_02a5, + &pci_ss_info_9005_0286_9005_02a6, + &pci_ss_info_9005_0286_9005_02a7, + &pci_ss_info_9005_0286_9005_02a8, + &pci_ss_info_9005_0286_9005_02a9, + &pci_ss_info_9005_0286_9005_02aa, + &pci_ss_info_9005_0286_9005_02ac, + &pci_ss_info_9005_0286_9005_02b3, + &pci_ss_info_9005_0286_9005_02b4, + &pci_ss_info_9005_0286_9005_0800, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0410[] = { + &pci_ss_info_9005_0410_9005_0410, + &pci_ss_info_9005_0410_9005_0411, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0412[] = { + &pci_ss_info_9005_0412_9005_0412, + &pci_ss_info_9005_0412_9005_0413, + NULL +}; +#define pci_ss_list_9005_041e NULL +static const pciSubsystemInfo *pci_ss_list_9005_041f[] = { + &pci_ss_info_9005_041f_9005_041f, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0430[] = { + &pci_ss_info_9005_0430_9005_0430, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0432[] = { + &pci_ss_info_9005_0432_9005_0432, + NULL +}; +#define pci_ss_list_9005_043e NULL +#define pci_ss_list_9005_043f NULL +static const pciSubsystemInfo *pci_ss_list_9005_0500[] = { + &pci_ss_info_9005_0500_1014_02c1, + &pci_ss_info_9005_0500_1014_02c2, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9005_0503[] = { + &pci_ss_info_9005_0503_1014_02bf, + &pci_ss_info_9005_0503_1014_02d5, + NULL +}; +#define pci_ss_list_9005_0910 NULL +#define pci_ss_list_9005_091e NULL +#define pci_ss_list_9005_8000 NULL +#define pci_ss_list_9005_800f NULL +#define pci_ss_list_9005_8010 NULL +static const pciSubsystemInfo *pci_ss_list_9005_8011[] = { + &pci_ss_info_9005_8011_0e11_00ac, + &pci_ss_info_9005_8011_9005_0041, + NULL +}; +#define pci_ss_list_9005_8012 NULL +#define pci_ss_list_9005_8013 NULL +#define pci_ss_list_9005_8014 NULL +#define pci_ss_list_9005_8015 NULL +#define pci_ss_list_9005_8016 NULL +#define pci_ss_list_9005_8017 NULL +#define pci_ss_list_9005_801c NULL +#define pci_ss_list_9005_801d NULL +#define pci_ss_list_9005_801e NULL +static const pciSubsystemInfo *pci_ss_list_9005_801f[] = { + &pci_ss_info_9005_801f_1734_1011, + NULL +}; +#define pci_ss_list_9005_8080 NULL +#define pci_ss_list_9005_808f NULL +#define pci_ss_list_9005_8090 NULL +#define pci_ss_list_9005_8091 NULL +#define pci_ss_list_9005_8092 NULL +#define pci_ss_list_9005_8093 NULL +#define pci_ss_list_9005_8094 NULL +#define pci_ss_list_9005_8095 NULL +#define pci_ss_list_9005_8096 NULL +#define pci_ss_list_9005_8097 NULL +#define pci_ss_list_9005_809c NULL +#define pci_ss_list_9005_809d NULL +#define pci_ss_list_9005_809e NULL +#define pci_ss_list_9005_809f NULL +#endif +#define pci_ss_list_907f_2015 NULL +#define pci_ss_list_9412_6565 NULL +#define pci_ss_list_9699_6565 NULL +#define pci_ss_list_9710_7780 NULL +#define pci_ss_list_9710_9805 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_9710_9815[] = { + &pci_ss_info_9710_9815_1000_0020, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9710_9835[] = { + &pci_ss_info_9710_9835_1000_0002, + &pci_ss_info_9710_9835_1000_0012, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9710_9845[] = { + &pci_ss_info_9710_9845_1000_0004, + &pci_ss_info_9710_9845_1000_0006, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_9710_9855[] = { + &pci_ss_info_9710_9855_1000_0014, + NULL +}; +#endif +#define pci_ss_list_9902_0001 NULL +#define pci_ss_list_9902_0002 NULL +#define pci_ss_list_9902_0003 NULL +#define pci_ss_list_a727_0013 NULL +#define pci_ss_list_aecb_6250 NULL +#define pci_ss_list_affe_02e1 NULL +#define pci_ss_list_affe_dead NULL +#define pci_ss_list_cafe_0003 NULL +#define pci_ss_list_cddd_0101 NULL +#define pci_ss_list_cddd_0200 NULL +#define pci_ss_list_d161_0205 NULL +#define pci_ss_list_d161_0210 NULL +#define pci_ss_list_d161_0405 NULL +#define pci_ss_list_d161_0406 NULL +#define pci_ss_list_d161_0410 NULL +#define pci_ss_list_d161_0411 NULL +#define pci_ss_list_d161_2400 NULL +#define pci_ss_list_d4d4_0601 NULL +#define pci_ss_list_deaf_9050 NULL +#define pci_ss_list_deaf_9051 NULL +#define pci_ss_list_deaf_9052 NULL +#define pci_ss_list_e000_e000 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_e159_0001[] = { + &pci_ss_info_e159_0001_0059_0001, + &pci_ss_info_e159_0001_0059_0003, + &pci_ss_info_e159_0001_00a7_0001, + &pci_ss_info_e159_0001_8086_0003, + NULL +}; +#define pci_ss_list_e159_0002 NULL +#endif +#define pci_ss_list_ea01_000a NULL +#define pci_ss_list_ea01_0032 NULL +#define pci_ss_list_ea01_003e NULL +#define pci_ss_list_ea01_0041 NULL +#define pci_ss_list_ea01_0043 NULL +#define pci_ss_list_ea01_0046 NULL +#define pci_ss_list_ea01_0052 NULL +#define pci_ss_list_ea01_0800 NULL +#define pci_ss_list_ea60_9896 NULL +#define pci_ss_list_ea60_9897 NULL +#define pci_ss_list_ea60_9898 NULL +#define pci_ss_list_eace_3100 NULL +#define pci_ss_list_eace_3200 NULL +#define pci_ss_list_eace_320e NULL +#define pci_ss_list_eace_340e NULL +#define pci_ss_list_eace_341e NULL +#define pci_ss_list_eace_3500 NULL +#define pci_ss_list_eace_351c NULL +#define pci_ss_list_eace_4100 NULL +#define pci_ss_list_eace_4110 NULL +#define pci_ss_list_eace_4220 NULL +#define pci_ss_list_eace_422e NULL +#define pci_ss_list_ec80_ec00 NULL +#define pci_ss_list_edd8_a091 NULL +#define pci_ss_list_edd8_a099 NULL +#define pci_ss_list_edd8_a0a1 NULL +#define pci_ss_list_edd8_a0a9 NULL +#define pci_ss_list_f1d0_c0fe NULL +#define pci_ss_list_f1d0_c0ff NULL +#define pci_ss_list_f1d0_cafe NULL +#define pci_ss_list_f1d0_cfee NULL +#define pci_ss_list_f1d0_dcaf NULL +#define pci_ss_list_f1d0_dfee NULL +#define pci_ss_list_f1d0_efac NULL +#define pci_ss_list_f1d0_facd NULL +#define pci_ss_list_fa57_0001 NULL +#define pci_ss_list_feda_a0fa NULL +#define pci_ss_list_feda_a10e NULL +#define pci_ss_list_fede_0003 NULL +#define pci_ss_list_fffd_0101 NULL +#define pci_ss_list_fffe_0405 NULL +#define pci_ss_list_fffe_0710 NULL +#ifdef INIT_VENDOR_SUBSYS_INFO +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0000[] = { + &pci_ss_info_0000_0000, + &pci_ss_info_0000_4091, + NULL +}; +#endif +#define pci_ss_list_001a NULL +#define pci_ss_list_0033 NULL +static const pciSubsystemInfo *pci_ss_list_003d[] = { + &pci_ss_info_003d_0008, + &pci_ss_info_003d_000b, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0059[] = { + &pci_ss_info_0059_0001, + &pci_ss_info_0059_0003, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0070[] = { + &pci_ss_info_0070_0003, + &pci_ss_info_0070_0009, + &pci_ss_info_0070_0801, + &pci_ss_info_0070_0807, + &pci_ss_info_0070_13eb, + &pci_ss_info_0070_2801, + &pci_ss_info_0070_3401, + &pci_ss_info_0070_4000, + &pci_ss_info_0070_4001, + &pci_ss_info_0070_4009, + &pci_ss_info_0070_4800, + &pci_ss_info_0070_4801, + &pci_ss_info_0070_4803, + &pci_ss_info_0070_8003, + &pci_ss_info_0070_8801, + &pci_ss_info_0070_9001, + &pci_ss_info_0070_9002, + &pci_ss_info_0070_9200, + &pci_ss_info_0070_9202, + &pci_ss_info_0070_9402, + &pci_ss_info_0070_9802, + &pci_ss_info_0070_c801, + &pci_ss_info_0070_e807, + &pci_ss_info_0070_e817, + &pci_ss_info_0070_ff01, + &pci_ss_info_0070_ff92, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0071[] = { + &pci_ss_info_0071_0101, + NULL +}; +#endif +#define pci_ss_list_0095 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_00a7[] = { + &pci_ss_info_00a7_0001, + NULL +}; +#endif +#define pci_ss_list_00f5 NULL +#define pci_ss_list_0100 NULL +#define pci_ss_list_0123 NULL +#define pci_ss_list_018a NULL +#define pci_ss_list_021b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0270[] = { + &pci_ss_info_0270_0801, + NULL +}; +#endif +#define pci_ss_list_0291 NULL +#define pci_ss_list_02ac NULL +#define pci_ss_list_0315 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0357[] = { + &pci_ss_info_0357_000a, + NULL +}; +#endif +#define pci_ss_list_0432 NULL +#define pci_ss_list_045e NULL +#define pci_ss_list_0482 NULL +#define pci_ss_list_04cf NULL +#define pci_ss_list_050d NULL +#define pci_ss_list_05a9 NULL +#define pci_ss_list_05e3 NULL +#define pci_ss_list_066f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0675[] = { + &pci_ss_info_0675_1704, + &pci_ss_info_0675_1707, + &pci_ss_info_0675_1708, + NULL +}; +#endif +#define pci_ss_list_067b NULL +#define pci_ss_list_0721 NULL +#define pci_ss_list_07e2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_0925[] = { + &pci_ss_info_0925_1234, + NULL +}; +#endif +#define pci_ss_list_093a NULL +#define pci_ss_list_09c1 NULL +#define pci_ss_list_0a89 NULL +#define pci_ss_list_0b0b NULL +#define pci_ss_list_0b49 NULL +#define pci_ss_list_0ccd NULL +static const pciSubsystemInfo *pci_ss_list_0e11[] = { + &pci_ss_info_0e11_0012, + &pci_ss_info_0e11_001e, + &pci_ss_info_0e11_0022, + &pci_ss_info_0e11_0023, + &pci_ss_info_0e11_0024, + &pci_ss_info_0e11_0030, + &pci_ss_info_0e11_0042, + &pci_ss_info_0e11_0043, + &pci_ss_info_0e11_0049, + &pci_ss_info_0e11_004a, + &pci_ss_info_0e11_004e, + &pci_ss_info_0e11_005d, + &pci_ss_info_0e11_007c, + &pci_ss_info_0e11_007d, + &pci_ss_info_0e11_007e, + &pci_ss_info_0e11_0085, + &pci_ss_info_0e11_0088, + &pci_ss_info_0e11_0091, + &pci_ss_info_0e11_0097, + &pci_ss_info_0e11_0098, + &pci_ss_info_0e11_0099, + &pci_ss_info_0e11_009a, + &pci_ss_info_0e11_00ac, + &pci_ss_info_0e11_00b8, + &pci_ss_info_0e11_00b9, + &pci_ss_info_0e11_00bb, + &pci_ss_info_0e11_00c1, + &pci_ss_info_0e11_00ca, + &pci_ss_info_0e11_00cb, + &pci_ss_info_0e11_00cf, + &pci_ss_info_0e11_00d0, + &pci_ss_info_0e11_00d1, + &pci_ss_info_0e11_00da, + &pci_ss_info_0e11_00db, + &pci_ss_info_0e11_00dc, + &pci_ss_info_0e11_00e3, + &pci_ss_info_0e11_0295, + &pci_ss_info_0e11_0460, + &pci_ss_info_0e11_0500, + &pci_ss_info_0e11_3001, + &pci_ss_info_0e11_3002, + &pci_ss_info_0e11_3003, + &pci_ss_info_0e11_3004, + &pci_ss_info_0e11_3005, + &pci_ss_info_0e11_3006, + &pci_ss_info_0e11_3007, + &pci_ss_info_0e11_4030, + &pci_ss_info_0e11_4031, + &pci_ss_info_0e11_4032, + &pci_ss_info_0e11_4033, + &pci_ss_info_0e11_4040, + &pci_ss_info_0e11_4048, + &pci_ss_info_0e11_4050, + &pci_ss_info_0e11_4051, + &pci_ss_info_0e11_4058, + &pci_ss_info_0e11_4080, + &pci_ss_info_0e11_4082, + &pci_ss_info_0e11_4083, + &pci_ss_info_0e11_409a, + &pci_ss_info_0e11_409b, + &pci_ss_info_0e11_409c, + &pci_ss_info_0e11_409d, + &pci_ss_info_0e11_6004, + &pci_ss_info_0e11_7004, + &pci_ss_info_0e11_b01e, + &pci_ss_info_0e11_b01f, + &pci_ss_info_0e11_b02f, + &pci_ss_info_0e11_b032, + &pci_ss_info_0e11_b03b, + &pci_ss_info_0e11_b03c, + &pci_ss_info_0e11_b03d, + &pci_ss_info_0e11_b03e, + &pci_ss_info_0e11_b03f, + &pci_ss_info_0e11_b049, + &pci_ss_info_0e11_b04a, + &pci_ss_info_0e11_b0bc, + &pci_ss_info_0e11_b0c6, + &pci_ss_info_0e11_b0c7, + &pci_ss_info_0e11_b0d1, + &pci_ss_info_0e11_b0d7, + &pci_ss_info_0e11_b0dd, + &pci_ss_info_0e11_b0de, + &pci_ss_info_0e11_b0df, + &pci_ss_info_0e11_b0e0, + &pci_ss_info_0e11_b0e1, + &pci_ss_info_0e11_b0e7, + &pci_ss_info_0e11_b0e8, + &pci_ss_info_0e11_b0fd, + &pci_ss_info_0e11_b10e, + &pci_ss_info_0e11_b110, + &pci_ss_info_0e11_b111, + &pci_ss_info_0e11_b112, + &pci_ss_info_0e11_b113, + &pci_ss_info_0e11_b114, + &pci_ss_info_0e11_b121, + &pci_ss_info_0e11_b123, + &pci_ss_info_0e11_b126, + &pci_ss_info_0e11_b134, + &pci_ss_info_0e11_b13c, + &pci_ss_info_0e11_b143, + &pci_ss_info_0e11_b144, + &pci_ss_info_0e11_b14d, + &pci_ss_info_0e11_b15a, + &pci_ss_info_0e11_b160, + &pci_ss_info_0e11_b163, + &pci_ss_info_0e11_b164, + &pci_ss_info_0e11_b16e, + &pci_ss_info_0e11_b16f, + &pci_ss_info_0e11_b194, + &pci_ss_info_0e11_b195, + &pci_ss_info_0e11_b196, + &pci_ss_info_0e11_b1a4, + &pci_ss_info_0e11_b1a7, + &pci_ss_info_0e11_b1be, + &pci_ss_info_0e11_e2a0, + &pci_ss_info_0e11_f620, + NULL +}; +#define pci_ss_list_0e21 NULL +#define pci_ss_list_0e55 NULL +#define pci_ss_list_0eac NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1000[] = { + &pci_ss_info_1000_0001, + &pci_ss_info_1000_0002, + &pci_ss_info_1000_0004, + &pci_ss_info_1000_0006, + &pci_ss_info_1000_0012, + &pci_ss_info_1000_0014, + &pci_ss_info_1000_0020, + &pci_ss_info_1000_0033, + &pci_ss_info_1000_0062, + &pci_ss_info_1000_0066, + &pci_ss_info_1000_0518, + &pci_ss_info_1000_0520, + &pci_ss_info_1000_0522, + &pci_ss_info_1000_0523, + &pci_ss_info_1000_0530, + &pci_ss_info_1000_0531, + &pci_ss_info_1000_0532, + &pci_ss_info_1000_1000, + &pci_ss_info_1000_1001, + &pci_ss_info_1000_1002, + &pci_ss_info_1000_1003, + &pci_ss_info_1000_1004, + &pci_ss_info_1000_1005, + &pci_ss_info_1000_100c, + &pci_ss_info_1000_100d, + &pci_ss_info_1000_1010, + &pci_ss_info_1000_1020, + &pci_ss_info_1000_2004, + &pci_ss_info_1000_2005, + &pci_ss_info_1000_3004, + &pci_ss_info_1000_3008, + &pci_ss_info_1000_4523, + &pci_ss_info_1000_a520, + NULL +}; +#endif +#define pci_ss_list_1001 NULL +static const pciSubsystemInfo *pci_ss_list_1002[] = { + &pci_ss_info_1002_0001, + &pci_ss_info_1002_0002, + &pci_ss_info_1002_0003, + &pci_ss_info_1002_0004, + &pci_ss_info_1002_0008, + &pci_ss_info_1002_0009, + &pci_ss_info_1002_000a, + &pci_ss_info_1002_000b, + &pci_ss_info_1002_0014, + &pci_ss_info_1002_0018, + &pci_ss_info_1002_001a, + &pci_ss_info_1002_001c, + &pci_ss_info_1002_0028, + &pci_ss_info_1002_0029, + &pci_ss_info_1002_002a, + &pci_ss_info_1002_002b, + &pci_ss_info_1002_0038, + &pci_ss_info_1002_0039, + &pci_ss_info_1002_003a, + &pci_ss_info_1002_0040, + &pci_ss_info_1002_0044, + &pci_ss_info_1002_0048, + &pci_ss_info_1002_0061, + &pci_ss_info_1002_0062, + &pci_ss_info_1002_0063, + &pci_ss_info_1002_0068, + &pci_ss_info_1002_0080, + &pci_ss_info_1002_0084, + &pci_ss_info_1002_0087, + &pci_ss_info_1002_0088, + &pci_ss_info_1002_008a, + &pci_ss_info_1002_00ba, + &pci_ss_info_1002_00f8, + &pci_ss_info_1002_010a, + &pci_ss_info_1002_0139, + &pci_ss_info_1002_013a, + &pci_ss_info_1002_0152, + &pci_ss_info_1002_0162, + &pci_ss_info_1002_0172, + &pci_ss_info_1002_028a, + &pci_ss_info_1002_02aa, + &pci_ss_info_1002_0322, + &pci_ss_info_1002_0323, + &pci_ss_info_1002_0448, + &pci_ss_info_1002_053a, + &pci_ss_info_1002_0908, + &pci_ss_info_1002_0b12, + &pci_ss_info_1002_0b13, + &pci_ss_info_1002_0d02, + &pci_ss_info_1002_0d03, + &pci_ss_info_1002_103a, + &pci_ss_info_1002_2000, + &pci_ss_info_1002_2001, + &pci_ss_info_1002_2f72, + &pci_ss_info_1002_4336, + &pci_ss_info_1002_4722, + &pci_ss_info_1002_4723, + &pci_ss_info_1002_4742, + &pci_ss_info_1002_4744, + &pci_ss_info_1002_474d, + &pci_ss_info_1002_474e, + &pci_ss_info_1002_474f, + &pci_ss_info_1002_4750, + &pci_ss_info_1002_4752, + &pci_ss_info_1002_4753, + &pci_ss_info_1002_4756, + &pci_ss_info_1002_4757, + &pci_ss_info_1002_475a, + &pci_ss_info_1002_4772, + &pci_ss_info_1002_4773, + &pci_ss_info_1002_4c42, + &pci_ss_info_1002_4c49, + &pci_ss_info_1002_4c50, + &pci_ss_info_1002_4e71, + &pci_ss_info_1002_515e, + &pci_ss_info_1002_5654, + &pci_ss_info_1002_5954, + &pci_ss_info_1002_5955, + &pci_ss_info_1002_5965, + &pci_ss_info_1002_5c63, + &pci_ss_info_1002_8001, + &pci_ss_info_1002_8008, + &pci_ss_info_1002_a101, + NULL +}; +#define pci_ss_list_1003 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1004[] = { + &pci_ss_info_1004_0304, + &pci_ss_info_1004_0305, + &pci_ss_info_1004_0306, + NULL +}; +#endif +static const pciSubsystemInfo *pci_ss_list_1005[] = { + &pci_ss_info_1005_127a, + NULL +}; +#define pci_ss_list_1006 NULL +#define pci_ss_list_1007 NULL +#define pci_ss_list_1008 NULL +#define pci_ss_list_100a NULL +#define pci_ss_list_100b NULL +#define pci_ss_list_100c NULL +#define pci_ss_list_100d NULL +#define pci_ss_list_100e NULL +static const pciSubsystemInfo *pci_ss_list_1010[] = { + &pci_ss_info_1010_0020, + &pci_ss_info_1010_0080, + &pci_ss_info_1010_0088, + &pci_ss_info_1010_0090, + &pci_ss_info_1010_0098, + &pci_ss_info_1010_00a0, + &pci_ss_info_1010_00a8, + &pci_ss_info_1010_0120, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1011[] = { + &pci_ss_info_1011_4d10, + &pci_ss_info_1011_500a, + &pci_ss_info_1011_500b, + &pci_ss_info_1011_def1, + NULL +}; +#define pci_ss_list_1012 NULL +static const pciSubsystemInfo *pci_ss_list_1013[] = { + &pci_ss_info_1013_00bc, + &pci_ss_info_1013_4280, + &pci_ss_info_1013_4281, + &pci_ss_info_1013_5959, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1014[] = { + &pci_ss_info_1014_0001, + &pci_ss_info_1014_002e, + &pci_ss_info_1014_0031, + &pci_ss_info_1014_003e, + &pci_ss_info_1014_005c, + &pci_ss_info_1014_008e, + &pci_ss_info_1014_0092, + &pci_ss_info_1014_0097, + &pci_ss_info_1014_0098, + &pci_ss_info_1014_0099, + &pci_ss_info_1014_00ba, + &pci_ss_info_1014_00cd, + &pci_ss_info_1014_00ce, + &pci_ss_info_1014_00cf, + &pci_ss_info_1014_00db, + &pci_ss_info_1014_00dd, + &pci_ss_info_1014_00e4, + &pci_ss_info_1014_00e5, + &pci_ss_info_1014_0104, + &pci_ss_info_1014_0119, + &pci_ss_info_1014_0130, + &pci_ss_info_1014_0131, + &pci_ss_info_1014_0143, + &pci_ss_info_1014_0145, + &pci_ss_info_1014_0148, + &pci_ss_info_1014_0153, + &pci_ss_info_1014_0154, + &pci_ss_info_1014_0166, + &pci_ss_info_1014_016d, + &pci_ss_info_1014_017f, + &pci_ss_info_1014_0181, + &pci_ss_info_1014_0182, + &pci_ss_info_1014_0183, + &pci_ss_info_1014_0184, + &pci_ss_info_1014_0185, + &pci_ss_info_1014_01b6, + &pci_ss_info_1014_01b7, + &pci_ss_info_1014_01bc, + &pci_ss_info_1014_01be, + &pci_ss_info_1014_01bf, + &pci_ss_info_1014_01c6, + &pci_ss_info_1014_01ce, + &pci_ss_info_1014_01cf, + &pci_ss_info_1014_01dc, + &pci_ss_info_1014_01ea, + &pci_ss_info_1014_01eb, + &pci_ss_info_1014_01ec, + &pci_ss_info_1014_01f1, + &pci_ss_info_1014_01f2, + &pci_ss_info_1014_01fc, + &pci_ss_info_1014_0202, + &pci_ss_info_1014_0205, + &pci_ss_info_1014_0207, + &pci_ss_info_1014_0208, + &pci_ss_info_1014_0209, + &pci_ss_info_1014_020c, + &pci_ss_info_1014_020e, + &pci_ss_info_1014_0217, + &pci_ss_info_1014_021a, + &pci_ss_info_1014_021d, + &pci_ss_info_1014_0220, + &pci_ss_info_1014_0222, + &pci_ss_info_1014_0223, + &pci_ss_info_1014_022e, + &pci_ss_info_1014_0232, + &pci_ss_info_1014_0234, + &pci_ss_info_1014_0235, + &pci_ss_info_1014_0239, + &pci_ss_info_1014_023a, + &pci_ss_info_1014_023b, + &pci_ss_info_1014_023d, + &pci_ss_info_1014_0241, + &pci_ss_info_1014_0242, + &pci_ss_info_1014_0244, + &pci_ss_info_1014_0245, + &pci_ss_info_1014_0251, + &pci_ss_info_1014_0252, + &pci_ss_info_1014_0258, + &pci_ss_info_1014_0259, + &pci_ss_info_1014_0264, + &pci_ss_info_1014_0265, + &pci_ss_info_1014_0266, + &pci_ss_info_1014_0267, + &pci_ss_info_1014_0268, + &pci_ss_info_1014_0269, + &pci_ss_info_1014_026a, + &pci_ss_info_1014_0277, + &pci_ss_info_1014_0278, + &pci_ss_info_1014_0279, + &pci_ss_info_1014_027c, + &pci_ss_info_1014_028c, + &pci_ss_info_1014_028d, + &pci_ss_info_1014_028e, + &pci_ss_info_1014_029a, + &pci_ss_info_1014_02be, + &pci_ss_info_1014_02bf, + &pci_ss_info_1014_02c0, + &pci_ss_info_1014_02c1, + &pci_ss_info_1014_02c2, + &pci_ss_info_1014_02c6, + &pci_ss_info_1014_02c8, + &pci_ss_info_1014_02d3, + &pci_ss_info_1014_02d4, + &pci_ss_info_1014_02d5, + &pci_ss_info_1014_02ed, + &pci_ss_info_1014_02f2, + &pci_ss_info_1014_030d, + &pci_ss_info_1014_034d, + &pci_ss_info_1014_0502, + &pci_ss_info_1014_0503, + &pci_ss_info_1014_0506, + &pci_ss_info_1014_0508, + &pci_ss_info_1014_050f, + &pci_ss_info_1014_0510, + &pci_ss_info_1014_0511, + &pci_ss_info_1014_0512, + &pci_ss_info_1014_0513, + &pci_ss_info_1014_0517, + &pci_ss_info_1014_051a, + &pci_ss_info_1014_051c, + &pci_ss_info_1014_0522, + &pci_ss_info_1014_0528, + &pci_ss_info_1014_052c, + &pci_ss_info_1014_052d, + &pci_ss_info_1014_052e, + &pci_ss_info_1014_0535, + &pci_ss_info_1014_053a, + &pci_ss_info_1014_053b, + &pci_ss_info_1014_053c, + &pci_ss_info_1014_053d, + &pci_ss_info_1014_053e, + &pci_ss_info_1014_0540, + &pci_ss_info_1014_0545, + &pci_ss_info_1014_0549, + &pci_ss_info_1014_0556, + &pci_ss_info_1014_0559, + &pci_ss_info_1014_055c, + &pci_ss_info_1014_055d, + &pci_ss_info_1014_055e, + &pci_ss_info_1014_055f, + &pci_ss_info_1014_0562, + &pci_ss_info_1014_058a, + &pci_ss_info_1014_0598, + &pci_ss_info_1014_1010, + &pci_ss_info_1014_1025, + &pci_ss_info_1014_105c, + &pci_ss_info_1014_10f2, + &pci_ss_info_1014_1181, + &pci_ss_info_1014_1182, + &pci_ss_info_1014_2000, + &pci_ss_info_1014_2205, + &pci_ss_info_1014_305c, + &pci_ss_info_1014_405c, + &pci_ss_info_1014_505c, + &pci_ss_info_1014_605c, + &pci_ss_info_1014_705c, + &pci_ss_info_1014_805c, + &pci_ss_info_1014_8181, + &pci_ss_info_1014_9181, + &pci_ss_info_1014_9540, + &pci_ss_info_1014_9580, + &pci_ss_info_1014_9750, + &pci_ss_info_1014_ff03, + NULL +}; +#endif +#define pci_ss_list_1015 NULL +#define pci_ss_list_1016 NULL +#define pci_ss_list_1017 NULL +#define pci_ss_list_1018 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1019[] = { + &pci_ss_info_1019_0970, + &pci_ss_info_1019_0985, + &pci_ss_info_1019_0987, + &pci_ss_info_1019_0a14, + &pci_ss_info_1019_0a81, + &pci_ss_info_1019_0f38, + &pci_ss_info_1019_4c30, + &pci_ss_info_1019_4cb4, + &pci_ss_info_1019_4cb5, + &pci_ss_info_1019_7018, + &pci_ss_info_1019_8001, + NULL +}; +#endif +#define pci_ss_list_101a NULL +#define pci_ss_list_101b NULL +#define pci_ss_list_101c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_101e[] = { + &pci_ss_info_101e_0431, + &pci_ss_info_101e_0438, + &pci_ss_info_101e_0466, + &pci_ss_info_101e_0467, + &pci_ss_info_101e_0471, + &pci_ss_info_101e_0475, + &pci_ss_info_101e_0477, + &pci_ss_info_101e_0490, + &pci_ss_info_101e_0493, + &pci_ss_info_101e_0494, + &pci_ss_info_101e_0503, + &pci_ss_info_101e_0511, + &pci_ss_info_101e_0522, + &pci_ss_info_101e_0649, + &pci_ss_info_101e_0762, + &pci_ss_info_101e_0767, + &pci_ss_info_101e_09a0, + &pci_ss_info_101e_8471, + &pci_ss_info_101e_8493, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_101f[] = { + &pci_ss_info_101f_1025, + NULL +}; +#endif +#define pci_ss_list_1020 NULL +#define pci_ss_list_1021 NULL +static const pciSubsystemInfo *pci_ss_list_1022[] = { + &pci_ss_info_1022_2000, + &pci_ss_info_1022_2b80, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1023[] = { + &pci_ss_info_1023_8400, + &pci_ss_info_1023_8520, + &pci_ss_info_1023_9750, + &pci_ss_info_1023_9880, + NULL +}; +#define pci_ss_list_1024 NULL +static const pciSubsystemInfo *pci_ss_list_1025[] = { + &pci_ss_info_1025_000e, + &pci_ss_info_1025_0018, + &pci_ss_info_1025_003c, + &pci_ss_info_1025_004d, + &pci_ss_info_1025_005a, + &pci_ss_info_1025_006a, + &pci_ss_info_1025_0079, + &pci_ss_info_1025_0080, + &pci_ss_info_1025_0310, + &pci_ss_info_1025_0315, + &pci_ss_info_1025_1003, + &pci_ss_info_1025_1007, + &pci_ss_info_1025_1016, + &pci_ss_info_1025_1605, + &pci_ss_info_1025_8013, + &pci_ss_info_1025_8920, + &pci_ss_info_1025_8921, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_1028[] = { + &pci_ss_info_1028_0001, + &pci_ss_info_1028_0002, + &pci_ss_info_1028_0003, + &pci_ss_info_1028_002e, + &pci_ss_info_1028_0074, + &pci_ss_info_1028_0075, + &pci_ss_info_1028_007d, + &pci_ss_info_1028_007e, + &pci_ss_info_1028_0080, + &pci_ss_info_1028_0081, + &pci_ss_info_1028_0082, + &pci_ss_info_1028_0083, + &pci_ss_info_1028_0084, + &pci_ss_info_1028_0085, + &pci_ss_info_1028_0086, + &pci_ss_info_1028_0087, + &pci_ss_info_1028_0088, + &pci_ss_info_1028_0089, + &pci_ss_info_1028_008e, + &pci_ss_info_1028_008f, + &pci_ss_info_1028_0090, + &pci_ss_info_1028_0091, + &pci_ss_info_1028_0092, + &pci_ss_info_1028_0093, + &pci_ss_info_1028_0094, + &pci_ss_info_1028_0095, + &pci_ss_info_1028_0096, + &pci_ss_info_1028_0097, + &pci_ss_info_1028_0098, + &pci_ss_info_1028_0099, + &pci_ss_info_1028_009b, + &pci_ss_info_1028_00aa, + &pci_ss_info_1028_00b1, + &pci_ss_info_1028_00bb, + &pci_ss_info_1028_00c5, + &pci_ss_info_1028_00c7, + &pci_ss_info_1028_00ce, + &pci_ss_info_1028_00d1, + &pci_ss_info_1028_00d9, + &pci_ss_info_1028_00e6, + &pci_ss_info_1028_00fe, + &pci_ss_info_1028_0106, + &pci_ss_info_1028_0109, + &pci_ss_info_1028_010a, + &pci_ss_info_1028_010e, + &pci_ss_info_1028_011c, + &pci_ss_info_1028_011d, + &pci_ss_info_1028_0121, + &pci_ss_info_1028_0123, + &pci_ss_info_1028_0126, + &pci_ss_info_1028_012a, + &pci_ss_info_1028_0134, + &pci_ss_info_1028_0139, + &pci_ss_info_1028_013f, + &pci_ss_info_1028_014a, + &pci_ss_info_1028_014e, + &pci_ss_info_1028_0151, + &pci_ss_info_1028_0156, + &pci_ss_info_1028_0163, + &pci_ss_info_1028_0165, + &pci_ss_info_1028_0169, + &pci_ss_info_1028_016c, + &pci_ss_info_1028_016d, + &pci_ss_info_1028_016e, + &pci_ss_info_1028_016f, + &pci_ss_info_1028_0170, + &pci_ss_info_1028_0179, + &pci_ss_info_1028_0182, + &pci_ss_info_1028_0183, + &pci_ss_info_1028_0187, + &pci_ss_info_1028_0188, + &pci_ss_info_1028_0196, + &pci_ss_info_1028_019a, + &pci_ss_info_1028_019d, + &pci_ss_info_1028_01a2, + &pci_ss_info_1028_01ad, + &pci_ss_info_1028_0287, + &pci_ss_info_1028_0291, + &pci_ss_info_1028_0407, + &pci_ss_info_1028_0467, + &pci_ss_info_1028_0471, + &pci_ss_info_1028_0475, + &pci_ss_info_1028_0493, + &pci_ss_info_1028_0511, + &pci_ss_info_1028_0518, + &pci_ss_info_1028_0520, + &pci_ss_info_1028_0531, + &pci_ss_info_1028_0533, + &pci_ss_info_1028_1010, + &pci_ss_info_1028_1079, + &pci_ss_info_1028_1111, + &pci_ss_info_1028_1f0a, + &pci_ss_info_1028_1f0b, + &pci_ss_info_1028_1f0c, + &pci_ss_info_1028_1f0d, + &pci_ss_info_1028_4082, + &pci_ss_info_1028_4134, + &pci_ss_info_1028_8082, + &pci_ss_info_1028_865d, + &pci_ss_info_1028_c082, + &pci_ss_info_1028_c134, + NULL +}; +#define pci_ss_list_1029 NULL +#define pci_ss_list_102a NULL +static const pciSubsystemInfo *pci_ss_list_102b[] = { + &pci_ss_info_102b_0100, + &pci_ss_info_102b_0328, + &pci_ss_info_102b_0338, + &pci_ss_info_102b_0378, + &pci_ss_info_102b_051b, + &pci_ss_info_102b_0541, + &pci_ss_info_102b_0542, + &pci_ss_info_102b_0543, + &pci_ss_info_102b_0641, + &pci_ss_info_102b_0642, + &pci_ss_info_102b_0643, + &pci_ss_info_102b_07c0, + &pci_ss_info_102b_07c1, + &pci_ss_info_102b_0840, + &pci_ss_info_102b_0850, + &pci_ss_info_102b_08c7, + &pci_ss_info_102b_0907, + &pci_ss_info_102b_0d41, + &pci_ss_info_102b_0d42, + &pci_ss_info_102b_0d43, + &pci_ss_info_102b_0e00, + &pci_ss_info_102b_0e01, + &pci_ss_info_102b_0e02, + &pci_ss_info_102b_0e03, + &pci_ss_info_102b_0f80, + &pci_ss_info_102b_0f81, + &pci_ss_info_102b_0f82, + &pci_ss_info_102b_0f83, + &pci_ss_info_102b_0f84, + &pci_ss_info_102b_1001, + &pci_ss_info_102b_1020, + &pci_ss_info_102b_1030, + &pci_ss_info_102b_1047, + &pci_ss_info_102b_1087, + &pci_ss_info_102b_1100, + &pci_ss_info_102b_1200, + &pci_ss_info_102b_14e1, + &pci_ss_info_102b_1820, + &pci_ss_info_102b_1830, + &pci_ss_info_102b_19d8, + &pci_ss_info_102b_19f8, + &pci_ss_info_102b_1c10, + &pci_ss_info_102b_1e41, + &pci_ss_info_102b_2021, + &pci_ss_info_102b_2159, + &pci_ss_info_102b_2179, + &pci_ss_info_102b_217d, + &pci_ss_info_102b_23c0, + &pci_ss_info_102b_23c1, + &pci_ss_info_102b_23c2, + &pci_ss_info_102b_23c3, + &pci_ss_info_102b_2538, + &pci_ss_info_102b_2811, + &pci_ss_info_102b_2c11, + &pci_ss_info_102b_2f58, + &pci_ss_info_102b_2f78, + &pci_ss_info_102b_3007, + &pci_ss_info_102b_3693, + &pci_ss_info_102b_48d0, + &pci_ss_info_102b_48e9, + &pci_ss_info_102b_48f8, + &pci_ss_info_102b_4a60, + &pci_ss_info_102b_4a64, + &pci_ss_info_102b_5dd0, + &pci_ss_info_102b_5f50, + &pci_ss_info_102b_5f51, + &pci_ss_info_102b_5f52, + &pci_ss_info_102b_9010, + &pci_ss_info_102b_c93c, + &pci_ss_info_102b_c9b0, + &pci_ss_info_102b_c9bc, + &pci_ss_info_102b_ca60, + &pci_ss_info_102b_ca6c, + &pci_ss_info_102b_dbbc, + &pci_ss_info_102b_dbc2, + &pci_ss_info_102b_dbc3, + &pci_ss_info_102b_dbc8, + &pci_ss_info_102b_dbd2, + &pci_ss_info_102b_dbd3, + &pci_ss_info_102b_dbd4, + &pci_ss_info_102b_dbd5, + &pci_ss_info_102b_dbd8, + &pci_ss_info_102b_dbd9, + &pci_ss_info_102b_dbe2, + &pci_ss_info_102b_dbe3, + &pci_ss_info_102b_dbe8, + &pci_ss_info_102b_dbf2, + &pci_ss_info_102b_dbf3, + &pci_ss_info_102b_dbf4, + &pci_ss_info_102b_dbf5, + &pci_ss_info_102b_dbf8, + &pci_ss_info_102b_dbf9, + &pci_ss_info_102b_f806, + &pci_ss_info_102b_ff00, + &pci_ss_info_102b_ff01, + &pci_ss_info_102b_ff02, + &pci_ss_info_102b_ff03, + &pci_ss_info_102b_ff04, + &pci_ss_info_102b_ff05, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_102c[] = { + &pci_ss_info_102c_00c0, + NULL +}; +#define pci_ss_list_102d NULL +#define pci_ss_list_102e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_102f[] = { + &pci_ss_info_102f_00f8, + NULL +}; +#endif +#define pci_ss_list_1030 NULL +static const pciSubsystemInfo *pci_ss_list_1031[] = { + &pci_ss_info_1031_7efe, + &pci_ss_info_1031_fc00, + NULL +}; +#define pci_ss_list_1032 NULL +static const pciSubsystemInfo *pci_ss_list_1033[] = { + &pci_ss_info_1033_0000, + &pci_ss_info_1033_0035, + &pci_ss_info_1033_8000, + &pci_ss_info_1033_800c, + &pci_ss_info_1033_800d, + &pci_ss_info_1033_8014, + &pci_ss_info_1033_8015, + &pci_ss_info_1033_8016, + &pci_ss_info_1033_801f, + &pci_ss_info_1033_8026, + &pci_ss_info_1033_8029, + &pci_ss_info_1033_802b, + &pci_ss_info_1033_802f, + &pci_ss_info_1033_803c, + &pci_ss_info_1033_8047, + &pci_ss_info_1033_804d, + &pci_ss_info_1033_804f, + &pci_ss_info_1033_8051, + &pci_ss_info_1033_8054, + &pci_ss_info_1033_8058, + &pci_ss_info_1033_8063, + &pci_ss_info_1033_8064, + &pci_ss_info_1033_8065, + &pci_ss_info_1033_8066, + &pci_ss_info_1033_8068, + &pci_ss_info_1033_8069, + &pci_ss_info_1033_806a, + &pci_ss_info_1033_8077, + &pci_ss_info_1033_809d, + &pci_ss_info_1033_80a8, + &pci_ss_info_1033_80ac, + &pci_ss_info_1033_80bc, + &pci_ss_info_1033_80cc, + &pci_ss_info_1033_80cd, + &pci_ss_info_1033_80e5, + &pci_ss_info_1033_8110, + &pci_ss_info_1033_8112, + &pci_ss_info_1033_8287, + NULL +}; +#define pci_ss_list_1034 NULL +#define pci_ss_list_1035 NULL +#define pci_ss_list_1036 NULL +#define pci_ss_list_1037 NULL +#define pci_ss_list_1038 NULL +static const pciSubsystemInfo *pci_ss_list_1039[] = { + &pci_ss_info_1039_0000, + &pci_ss_info_1039_0900, + &pci_ss_info_1039_5513, + &pci_ss_info_1039_6306, + &pci_ss_info_1039_6326, + &pci_ss_info_1039_6330, + &pci_ss_info_1039_7000, + &pci_ss_info_1039_7016, + &pci_ss_info_1039_7018, + NULL +}; +#define pci_ss_list_103a NULL +#define pci_ss_list_103b NULL +static const pciSubsystemInfo *pci_ss_list_103c[] = { + &pci_ss_info_103c_0007, + &pci_ss_info_103c_0008, + &pci_ss_info_103c_000d, + &pci_ss_info_103c_0024, + &pci_ss_info_103c_006a, + &pci_ss_info_103c_0131, + &pci_ss_info_103c_03a2, + &pci_ss_info_103c_0850, + &pci_ss_info_103c_088c, + &pci_ss_info_103c_0890, + &pci_ss_info_103c_08b0, + &pci_ss_info_103c_0944, + &pci_ss_info_103c_099c, + &pci_ss_info_103c_1040, + &pci_ss_info_103c_1041, + &pci_ss_info_103c_1042, + &pci_ss_info_103c_1049, + &pci_ss_info_103c_104a, + &pci_ss_info_103c_104b, + &pci_ss_info_103c_104c, + &pci_ss_info_103c_1064, + &pci_ss_info_103c_1065, + &pci_ss_info_103c_106c, + &pci_ss_info_103c_106e, + &pci_ss_info_103c_10c0, + &pci_ss_info_103c_10c2, + &pci_ss_info_103c_10c3, + &pci_ss_info_103c_10c6, + &pci_ss_info_103c_10c7, + &pci_ss_info_103c_10ca, + &pci_ss_info_103c_10cb, + &pci_ss_info_103c_10cc, + &pci_ss_info_103c_10cd, + &pci_ss_info_103c_10e1, + &pci_ss_info_103c_10e3, + &pci_ss_info_103c_10e4, + &pci_ss_info_103c_10ea, + &pci_ss_info_103c_10eb, + &pci_ss_info_103c_10ec, + &pci_ss_info_103c_1200, + &pci_ss_info_103c_1207, + &pci_ss_info_103c_1223, + &pci_ss_info_103c_1226, + &pci_ss_info_103c_1227, + &pci_ss_info_103c_1240, + &pci_ss_info_103c_125a, + &pci_ss_info_103c_1279, + &pci_ss_info_103c_1282, + &pci_ss_info_103c_128a, + &pci_ss_info_103c_128b, + &pci_ss_info_103c_1292, + &pci_ss_info_103c_12a4, + &pci_ss_info_103c_12a6, + &pci_ss_info_103c_12a8, + &pci_ss_info_103c_12ba, + &pci_ss_info_103c_12bc, + &pci_ss_info_103c_12c1, + &pci_ss_info_103c_12c3, + &pci_ss_info_103c_12c5, + &pci_ss_info_103c_12ca, + &pci_ss_info_103c_12cf, + &pci_ss_info_103c_12d5, + &pci_ss_info_103c_12d7, + &pci_ss_info_103c_12dd, + &pci_ss_info_103c_12f4, + &pci_ss_info_103c_12fa, + &pci_ss_info_103c_1300, + &pci_ss_info_103c_1301, + &pci_ss_info_103c_1330, + &pci_ss_info_103c_1340, + &pci_ss_info_103c_1356, + &pci_ss_info_103c_1706, + &pci_ss_info_103c_1707, + &pci_ss_info_103c_170c, + &pci_ss_info_103c_2a09, + &pci_ss_info_103c_2a0d, + &pci_ss_info_103c_3006, + &pci_ss_info_103c_3070, + &pci_ss_info_103c_308a, + &pci_ss_info_103c_308b, + &pci_ss_info_103c_309f, + &pci_ss_info_103c_3100, + &pci_ss_info_103c_3101, + &pci_ss_info_103c_3102, + &pci_ss_info_103c_3103, + &pci_ss_info_103c_3109, + &pci_ss_info_103c_3225, + &pci_ss_info_103c_3226, + &pci_ss_info_103c_3227, + &pci_ss_info_103c_60e7, + &pci_ss_info_103c_7031, + &pci_ss_info_103c_7032, + &pci_ss_info_103c_7037, + &pci_ss_info_103c_7038, + &pci_ss_info_103c_7039, + &pci_ss_info_103c_703b, + &pci_ss_info_103c_703c, + &pci_ss_info_103c_703d, + &pci_ss_info_103c_7044, + &pci_ss_info_103c_def1, + NULL +}; +#define pci_ss_list_103e NULL +#define pci_ss_list_103f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1040[] = { + &pci_ss_info_1040_000f, + &pci_ss_info_1040_0011, + NULL +}; +#endif +#define pci_ss_list_1041 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1042[] = { + &pci_ss_info_1042_1854, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1043[] = { + &pci_ss_info_1043_002a, + &pci_ss_info_1043_010c, + &pci_ss_info_1043_010d, + &pci_ss_info_1043_0120, + &pci_ss_info_1043_0127, + &pci_ss_info_1043_0200, + &pci_ss_info_1043_0201, + &pci_ss_info_1043_0202, + &pci_ss_info_1043_0205, + &pci_ss_info_1043_0210, + &pci_ss_info_1043_032e, + &pci_ss_info_1043_0c11, + &pci_ss_info_1043_100f, + &pci_ss_info_1043_1106, + &pci_ss_info_1043_120f, + &pci_ss_info_1043_130f, + &pci_ss_info_1043_1702, + &pci_ss_info_1043_1703, + &pci_ss_info_1043_1707, + &pci_ss_info_1043_173c, + &pci_ss_info_1043_1881, + &pci_ss_info_1043_1967, + &pci_ss_info_1043_1987, + &pci_ss_info_1043_2582, + &pci_ss_info_1043_2601, + &pci_ss_info_1043_4000, + &pci_ss_info_1043_4008, + &pci_ss_info_1043_4009, + &pci_ss_info_1043_400a, + &pci_ss_info_1043_400b, + &pci_ss_info_1043_4015, + &pci_ss_info_1043_4016, + &pci_ss_info_1043_402f, + &pci_ss_info_1043_4031, + &pci_ss_info_1043_405b, + &pci_ss_info_1043_405f, + &pci_ss_info_1043_4823, + &pci_ss_info_1043_4840, + &pci_ss_info_1043_4842, + &pci_ss_info_1043_4843, + &pci_ss_info_1043_4845, + &pci_ss_info_1043_4862, + &pci_ss_info_1043_800b, + &pci_ss_info_1043_801c, + &pci_ss_info_1043_8023, + &pci_ss_info_1043_8025, + &pci_ss_info_1043_8027, + &pci_ss_info_1043_802c, + &pci_ss_info_1043_8033, + &pci_ss_info_1043_8035, + &pci_ss_info_1043_803e, + &pci_ss_info_1043_8040, + &pci_ss_info_1043_8042, + &pci_ss_info_1043_8044, + &pci_ss_info_1043_8052, + &pci_ss_info_1043_8053, + &pci_ss_info_1043_8063, + &pci_ss_info_1043_8064, + &pci_ss_info_1043_806f, + &pci_ss_info_1043_8077, + &pci_ss_info_1043_807e, + &pci_ss_info_1043_807f, + &pci_ss_info_1043_8080, + &pci_ss_info_1043_808a, + &pci_ss_info_1043_808b, + &pci_ss_info_1043_808c, + &pci_ss_info_1043_808d, + &pci_ss_info_1043_8095, + &pci_ss_info_1043_809e, + &pci_ss_info_1043_80a1, + &pci_ss_info_1043_80a3, + &pci_ss_info_1043_80a5, + &pci_ss_info_1043_80a6, + &pci_ss_info_1043_80a7, + &pci_ss_info_1043_80a8, + &pci_ss_info_1043_80ab, + &pci_ss_info_1043_80ad, + &pci_ss_info_1043_80b0, + &pci_ss_info_1043_80e2, + &pci_ss_info_1043_80eb, + &pci_ss_info_1043_80ed, + &pci_ss_info_1043_80f2, + &pci_ss_info_1043_80f3, + &pci_ss_info_1043_80f4, + &pci_ss_info_1043_80f5, + &pci_ss_info_1043_80f8, + &pci_ss_info_1043_8109, + &pci_ss_info_1043_810f, + &pci_ss_info_1043_811a, + &pci_ss_info_1043_812a, + &pci_ss_info_1043_8134, + &pci_ss_info_1043_8138, + &pci_ss_info_1043_8141, + &pci_ss_info_1043_8142, + &pci_ss_info_1043_8145, + &pci_ss_info_1043_814a, + &pci_ss_info_1043_814e, + &pci_ss_info_1043_815a, + &pci_ss_info_1043_817b, + &pci_ss_info_1043_81a6, + &pci_ss_info_1043_c002, + &pci_ss_info_1043_c003, + &pci_ss_info_1043_c004, + &pci_ss_info_1043_c005, + &pci_ss_info_1043_c006, + &pci_ss_info_1043_c01a, + &pci_ss_info_1043_c01b, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1044[] = { + &pci_ss_info_1044_c001, + &pci_ss_info_1044_c002, + &pci_ss_info_1044_c003, + &pci_ss_info_1044_c004, + &pci_ss_info_1044_c005, + &pci_ss_info_1044_c00a, + &pci_ss_info_1044_c00b, + &pci_ss_info_1044_c00c, + &pci_ss_info_1044_c00d, + &pci_ss_info_1044_c00e, + &pci_ss_info_1044_c00f, + &pci_ss_info_1044_c014, + &pci_ss_info_1044_c015, + &pci_ss_info_1044_c016, + &pci_ss_info_1044_c01e, + &pci_ss_info_1044_c01f, + &pci_ss_info_1044_c020, + &pci_ss_info_1044_c021, + &pci_ss_info_1044_c028, + &pci_ss_info_1044_c029, + &pci_ss_info_1044_c02a, + &pci_ss_info_1044_c032, + &pci_ss_info_1044_c035, + &pci_ss_info_1044_c03c, + &pci_ss_info_1044_c03d, + &pci_ss_info_1044_c03e, + &pci_ss_info_1044_c046, + &pci_ss_info_1044_c047, + &pci_ss_info_1044_c048, + &pci_ss_info_1044_c050, + &pci_ss_info_1044_c051, + &pci_ss_info_1044_c052, + &pci_ss_info_1044_c05a, + &pci_ss_info_1044_c05b, + &pci_ss_info_1044_c064, + &pci_ss_info_1044_c065, + &pci_ss_info_1044_c066, + NULL +}; +#endif +#define pci_ss_list_1045 NULL +#define pci_ss_list_1046 NULL +#define pci_ss_list_1047 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1048[] = { + &pci_ss_info_1048_0935, + &pci_ss_info_1048_0a31, + &pci_ss_info_1048_0a32, + &pci_ss_info_1048_0a34, + &pci_ss_info_1048_0a35, + &pci_ss_info_1048_0a36, + &pci_ss_info_1048_0a42, + &pci_ss_info_1048_0a43, + &pci_ss_info_1048_0a44, + &pci_ss_info_1048_0c10, + &pci_ss_info_1048_0c18, + &pci_ss_info_1048_0c19, + &pci_ss_info_1048_0c1b, + &pci_ss_info_1048_0c1c, + &pci_ss_info_1048_0c20, + &pci_ss_info_1048_0c21, + &pci_ss_info_1048_0c28, + &pci_ss_info_1048_0c29, + &pci_ss_info_1048_0c2a, + &pci_ss_info_1048_0c2b, + &pci_ss_info_1048_0c2e, + &pci_ss_info_1048_0c2f, + &pci_ss_info_1048_0c30, + &pci_ss_info_1048_0c31, + &pci_ss_info_1048_0c32, + &pci_ss_info_1048_0c33, + &pci_ss_info_1048_0c34, + &pci_ss_info_1048_0c3a, + &pci_ss_info_1048_0c3b, + &pci_ss_info_1048_0c40, + &pci_ss_info_1048_0c41, + &pci_ss_info_1048_0c42, + &pci_ss_info_1048_0c43, + &pci_ss_info_1048_0c44, + &pci_ss_info_1048_0c45, + &pci_ss_info_1048_0c48, + &pci_ss_info_1048_0c4a, + &pci_ss_info_1048_0c4b, + &pci_ss_info_1048_0c50, + &pci_ss_info_1048_0c52, + &pci_ss_info_1048_0c56, + &pci_ss_info_1048_0c60, + &pci_ss_info_1048_0c61, + &pci_ss_info_1048_0c63, + &pci_ss_info_1048_0c64, + &pci_ss_info_1048_0c65, + &pci_ss_info_1048_0c66, + &pci_ss_info_1048_0c70, + &pci_ss_info_1048_1500, + &pci_ss_info_1048_226b, + NULL +}; +#endif +#define pci_ss_list_1049 NULL +static const pciSubsystemInfo *pci_ss_list_104a[] = { + &pci_ss_info_104a_0500, + NULL +}; +#define pci_ss_list_104b NULL +static const pciSubsystemInfo *pci_ss_list_104c[] = { + &pci_ss_info_104c_9066, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_104d[] = { + &pci_ss_info_104d_801b, + &pci_ss_info_104d_802f, + &pci_ss_info_104d_8032, + &pci_ss_info_104d_8036, + &pci_ss_info_104d_8044, + &pci_ss_info_104d_8045, + &pci_ss_info_104d_8049, + &pci_ss_info_104d_8055, + &pci_ss_info_104d_8056, + &pci_ss_info_104d_805a, + &pci_ss_info_104d_805f, + &pci_ss_info_104d_8067, + &pci_ss_info_104d_8074, + &pci_ss_info_104d_8075, + &pci_ss_info_104d_8077, + &pci_ss_info_104d_807b, + &pci_ss_info_104d_8083, + &pci_ss_info_104d_8097, + &pci_ss_info_104d_80df, + &pci_ss_info_104d_80e7, + &pci_ss_info_104d_810f, + &pci_ss_info_104d_813c, + &pci_ss_info_104d_8140, + &pci_ss_info_104d_830b, + NULL +}; +#define pci_ss_list_104e NULL +#define pci_ss_list_104f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1050[] = { + &pci_ss_info_1050_0001, + &pci_ss_info_1050_0840, + NULL +}; +#endif +#define pci_ss_list_1051 NULL +#define pci_ss_list_1052 NULL +#define pci_ss_list_1053 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1054[] = { + &pci_ss_info_1054_3016, + &pci_ss_info_1054_7018, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1055[] = { + &pci_ss_info_1055_e000, + &pci_ss_info_1055_e002, + &pci_ss_info_1055_e100, + &pci_ss_info_1055_e102, + &pci_ss_info_1055_e300, + &pci_ss_info_1055_e302, + NULL +}; +#endif +#define pci_ss_list_1056 NULL +static const pciSubsystemInfo *pci_ss_list_1057[] = { + &pci_ss_info_1057_0300, + &pci_ss_info_1057_0301, + &pci_ss_info_1057_0302, + &pci_ss_info_1057_5600, + &pci_ss_info_1057_7025, + NULL +}; +#define pci_ss_list_1058 NULL +#define pci_ss_list_1059 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_105a[] = { + &pci_ss_info_105a_0000, + &pci_ss_info_105a_0275, + &pci_ss_info_105a_1275, + &pci_ss_info_105a_2168, + &pci_ss_info_105a_4d30, + &pci_ss_info_105a_4d33, + &pci_ss_info_105a_4d39, + &pci_ss_info_105a_4d68, + &pci_ss_info_105a_5168, + &pci_ss_info_105a_6269, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_105b[] = { + &pci_ss_info_105b_0c19, + &pci_ss_info_105b_0c43, + NULL +}; +#endif +#define pci_ss_list_105c NULL +static const pciSubsystemInfo *pci_ss_list_105d[] = { + &pci_ss_info_105d_0000, + &pci_ss_info_105d_0001, + &pci_ss_info_105d_0002, + &pci_ss_info_105d_0003, + &pci_ss_info_105d_0004, + &pci_ss_info_105d_0005, + &pci_ss_info_105d_0006, + &pci_ss_info_105d_0007, + &pci_ss_info_105d_0008, + &pci_ss_info_105d_0009, + &pci_ss_info_105d_000a, + &pci_ss_info_105d_000b, + &pci_ss_info_105d_0018, + &pci_ss_info_105d_002a, + &pci_ss_info_105d_0037, + &pci_ss_info_105d_003a, + &pci_ss_info_105d_092f, + NULL +}; +#define pci_ss_list_105e NULL +#define pci_ss_list_105f NULL +#define pci_ss_list_1060 NULL +#define pci_ss_list_1061 NULL +#define pci_ss_list_1062 NULL +#define pci_ss_list_1063 NULL +#define pci_ss_list_1064 NULL +#define pci_ss_list_1065 NULL +#define pci_ss_list_1066 NULL +#define pci_ss_list_1067 NULL +#define pci_ss_list_1068 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1069[] = { + &pci_ss_info_1069_0020, + &pci_ss_info_1069_0030, + &pci_ss_info_1069_0040, + &pci_ss_info_1069_0050, + &pci_ss_info_1069_0052, + &pci_ss_info_1069_0054, + &pci_ss_info_1069_0072, + &pci_ss_info_1069_0200, + &pci_ss_info_1069_0202, + &pci_ss_info_1069_0204, + &pci_ss_info_1069_0206, + NULL +}; +#endif +#define pci_ss_list_106a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_106b[] = { + &pci_ss_info_106b_004e, + &pci_ss_info_106b_5811, + NULL +}; +#endif +#define pci_ss_list_106c NULL +#define pci_ss_list_106d NULL +#define pci_ss_list_106e NULL +#define pci_ss_list_106f NULL +#define pci_ss_list_1070 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1071[] = { + &pci_ss_info_1071_7150, + &pci_ss_info_1071_8160, + NULL +}; +#endif +#define pci_ss_list_1072 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1073[] = { + &pci_ss_info_1073_0004, + &pci_ss_info_1073_0005, + &pci_ss_info_1073_0006, + &pci_ss_info_1073_0008, + &pci_ss_info_1073_000a, + &pci_ss_info_1073_000d, + &pci_ss_info_1073_0010, + &pci_ss_info_1073_0012, + &pci_ss_info_1073_2000, + NULL +}; +#endif +#define pci_ss_list_1074 NULL +#define pci_ss_list_1075 NULL +#define pci_ss_list_1076 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1077[] = { + &pci_ss_info_1077_0001, + &pci_ss_info_1077_0002, + NULL +}; +#endif +#define pci_ss_list_1078 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1079[] = { + &pci_ss_info_1079_891f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_107a[] = { + &pci_ss_info_107a_000c, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_107b[] = { + &pci_ss_info_107b_0300, + &pci_ss_info_107b_1040, + &pci_ss_info_107b_3015, + &pci_ss_info_107b_4009, + &pci_ss_info_107b_5048, + &pci_ss_info_107b_5350, + &pci_ss_info_107b_6400, + &pci_ss_info_107b_8030, + &pci_ss_info_107b_8054, + &pci_ss_info_107b_8920, + NULL +}; +#endif +#define pci_ss_list_107c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_107d[] = { + &pci_ss_info_107d_2134, + &pci_ss_info_107d_2633, + &pci_ss_info_107d_2720, + &pci_ss_info_107d_2822, + &pci_ss_info_107d_2840, + &pci_ss_info_107d_2842, + &pci_ss_info_107d_2896, + &pci_ss_info_107d_5330, + &pci_ss_info_107d_5350, + &pci_ss_info_107d_6606, + &pci_ss_info_107d_6613, + &pci_ss_info_107d_6620, + &pci_ss_info_107d_663c, + &pci_ss_info_107d_665f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_107e[] = { + &pci_ss_info_107e_000e, + &pci_ss_info_107e_000f, + NULL +}; +#endif +#define pci_ss_list_107f NULL +#define pci_ss_list_1080 NULL +#define pci_ss_list_1081 NULL +#define pci_ss_list_1082 NULL +#define pci_ss_list_1083 NULL +#define pci_ss_list_1084 NULL +#define pci_ss_list_1085 NULL +#define pci_ss_list_1086 NULL +#define pci_ss_list_1087 NULL +#define pci_ss_list_1088 NULL +#define pci_ss_list_1089 NULL +#define pci_ss_list_108a NULL +#define pci_ss_list_108c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_108d[] = { + &pci_ss_info_108d_0004, + &pci_ss_info_108d_0007, + &pci_ss_info_108d_0008, + &pci_ss_info_108d_0016, + &pci_ss_info_108d_0017, + &pci_ss_info_108d_0022, + &pci_ss_info_108d_0027, + NULL +}; +#endif +static const pciSubsystemInfo *pci_ss_list_108e[] = { + &pci_ss_info_108e_10cf, + NULL +}; +#define pci_ss_list_108f NULL +#define pci_ss_list_1090 NULL +#define pci_ss_list_1091 NULL +static const pciSubsystemInfo *pci_ss_list_1092[] = { + &pci_ss_info_1092_0003, + &pci_ss_info_1092_00b8, + &pci_ss_info_1092_0100, + &pci_ss_info_1092_0127, + &pci_ss_info_1092_0136, + &pci_ss_info_1092_0141, + &pci_ss_info_1092_0146, + &pci_ss_info_1092_0148, + &pci_ss_info_1092_0149, + &pci_ss_info_1092_0152, + &pci_ss_info_1092_0154, + &pci_ss_info_1092_0155, + &pci_ss_info_1092_0156, + &pci_ss_info_1092_0157, + &pci_ss_info_1092_0350, + &pci_ss_info_1092_0440, + &pci_ss_info_1092_0550, + &pci_ss_info_1092_0552, + &pci_ss_info_1092_094c, + &pci_ss_info_1092_0a50, + &pci_ss_info_1092_0a70, + &pci_ss_info_1092_0a78, + &pci_ss_info_1092_1092, + &pci_ss_info_1092_2000, + &pci_ss_info_1092_2100, + &pci_ss_info_1092_2110, + &pci_ss_info_1092_2200, + &pci_ss_info_1092_3000, + &pci_ss_info_1092_3001, + &pci_ss_info_1092_3002, + &pci_ss_info_1092_3003, + &pci_ss_info_1092_3004, + &pci_ss_info_1092_4000, + &pci_ss_info_1092_4002, + &pci_ss_info_1092_4100, + &pci_ss_info_1092_4207, + &pci_ss_info_1092_4800, + &pci_ss_info_1092_4801, + &pci_ss_info_1092_4803, + &pci_ss_info_1092_4804, + &pci_ss_info_1092_4807, + &pci_ss_info_1092_4808, + &pci_ss_info_1092_4809, + &pci_ss_info_1092_480e, + &pci_ss_info_1092_4810, + &pci_ss_info_1092_4812, + &pci_ss_info_1092_4815, + &pci_ss_info_1092_4820, + &pci_ss_info_1092_4822, + &pci_ss_info_1092_4904, + &pci_ss_info_1092_4905, + &pci_ss_info_1092_4910, + &pci_ss_info_1092_4914, + &pci_ss_info_1092_4920, + &pci_ss_info_1092_4a00, + &pci_ss_info_1092_4a02, + &pci_ss_info_1092_4a09, + &pci_ss_info_1092_4a0b, + &pci_ss_info_1092_4a0f, + &pci_ss_info_1092_4e01, + &pci_ss_info_1092_5932, + &pci_ss_info_1092_5934, + &pci_ss_info_1092_5952, + &pci_ss_info_1092_5954, + &pci_ss_info_1092_5a00, + &pci_ss_info_1092_5a35, + &pci_ss_info_1092_5a37, + &pci_ss_info_1092_5a55, + &pci_ss_info_1092_5a57, + &pci_ss_info_1092_6820, + &pci_ss_info_1092_6a02, + &pci_ss_info_1092_7a02, + &pci_ss_info_1092_8000, + &pci_ss_info_1092_8030, + &pci_ss_info_1092_8035, + &pci_ss_info_1092_8225, + &pci_ss_info_1092_8760, + &pci_ss_info_1092_8a10, + NULL +}; +#define pci_ss_list_1093 NULL +#define pci_ss_list_1094 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1095[] = { + &pci_ss_info_1095_0670, + &pci_ss_info_1095_10cf, + &pci_ss_info_1095_3112, + &pci_ss_info_1095_3114, + &pci_ss_info_1095_3124, + &pci_ss_info_1095_3512, + &pci_ss_info_1095_3680, + &pci_ss_info_1095_6112, + &pci_ss_info_1095_6114, + &pci_ss_info_1095_6512, + NULL +}; +#endif +#define pci_ss_list_1096 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1097[] = { + &pci_ss_info_1097_3d01, + NULL +}; +#endif +#define pci_ss_list_1098 NULL +#define pci_ss_list_1099 NULL +#define pci_ss_list_109a NULL +#define pci_ss_list_109b NULL +#define pci_ss_list_109c NULL +#define pci_ss_list_109d NULL +#define pci_ss_list_109e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_109f[] = { + &pci_ss_info_109f_1000, + &pci_ss_info_109f_315d, + &pci_ss_info_109f_3181, + &pci_ss_info_109f_3197, + NULL +}; +#endif +#define pci_ss_list_10a0 NULL +#define pci_ss_list_10a1 NULL +#define pci_ss_list_10a2 NULL +#define pci_ss_list_10a3 NULL +#define pci_ss_list_10a4 NULL +#define pci_ss_list_10a5 NULL +#define pci_ss_list_10a6 NULL +#define pci_ss_list_10a7 NULL +#define pci_ss_list_10a8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10a9[] = { + &pci_ss_info_10a9_8002, + &pci_ss_info_10a9_8010, + &pci_ss_info_10a9_8011, + &pci_ss_info_10a9_8012, + &pci_ss_info_10a9_8013, + &pci_ss_info_10a9_8014, + &pci_ss_info_10a9_8018, + &pci_ss_info_10a9_801a, + &pci_ss_info_10a9_801b, + &pci_ss_info_10a9_801c, + &pci_ss_info_10a9_8020, + &pci_ss_info_10a9_8021, + &pci_ss_info_10a9_8024, + NULL +}; +#endif +#define pci_ss_list_10aa NULL +#define pci_ss_list_10ab NULL +#define pci_ss_list_10ac NULL +#define pci_ss_list_10ad NULL +#define pci_ss_list_10ae NULL +#define pci_ss_list_10af NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b0[] = { + &pci_ss_info_10b0_0001, + &pci_ss_info_10b0_0002, + NULL +}; +#endif +#define pci_ss_list_10b1 NULL +#define pci_ss_list_10b2 NULL +#define pci_ss_list_10b3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b4[] = { + &pci_ss_info_10b4_1617, + &pci_ss_info_10b4_1717, + &pci_ss_info_10b4_1b1b, + &pci_ss_info_10b4_1b1d, + &pci_ss_info_10b4_1b1e, + &pci_ss_info_10b4_1b20, + &pci_ss_info_10b4_1b21, + &pci_ss_info_10b4_1b22, + &pci_ss_info_10b4_1b23, + &pci_ss_info_10b4_1b27, + &pci_ss_info_10b4_1b88, + &pci_ss_info_10b4_201a, + &pci_ss_info_10b4_202f, + &pci_ss_info_10b4_222a, + &pci_ss_info_10b4_2230, + &pci_ss_info_10b4_2232, + &pci_ss_info_10b4_2235, + &pci_ss_info_10b4_237e, + &pci_ss_info_10b4_273d, + &pci_ss_info_10b4_273e, + &pci_ss_info_10b4_2740, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b5[] = { + &pci_ss_info_10b5_1067, + &pci_ss_info_10b5_1123, + &pci_ss_info_10b5_1172, + &pci_ss_info_10b5_2036, + &pci_ss_info_10b5_2221, + &pci_ss_info_10b5_2273, + &pci_ss_info_10b5_2431, + &pci_ss_info_10b5_2455, + &pci_ss_info_10b5_2696, + &pci_ss_info_10b5_2717, + &pci_ss_info_10b5_2844, + &pci_ss_info_10b5_2862, + &pci_ss_info_10b5_2905, + &pci_ss_info_10b5_2906, + &pci_ss_info_10b5_2940, + &pci_ss_info_10b5_2977, + &pci_ss_info_10b5_2978, + &pci_ss_info_10b5_2979, + &pci_ss_info_10b5_3025, + &pci_ss_info_10b5_3068, + &pci_ss_info_10b5_9050, + &pci_ss_info_10b5_9080, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b6[] = { + &pci_ss_info_10b6_0002, + &pci_ss_info_10b6_0003, + &pci_ss_info_10b6_0006, + &pci_ss_info_10b6_0007, + &pci_ss_info_10b6_0008, + &pci_ss_info_10b6_0009, + &pci_ss_info_10b6_000a, + &pci_ss_info_10b6_000b, + &pci_ss_info_10b6_000c, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b7[] = { + &pci_ss_info_10b7_0010, + &pci_ss_info_10b7_0020, + &pci_ss_info_10b7_1000, + &pci_ss_info_10b7_1001, + &pci_ss_info_10b7_1002, + &pci_ss_info_10b7_1003, + &pci_ss_info_10b7_1004, + &pci_ss_info_10b7_1005, + &pci_ss_info_10b7_1006, + &pci_ss_info_10b7_1007, + &pci_ss_info_10b7_1008, + &pci_ss_info_10b7_1100, + &pci_ss_info_10b7_1101, + &pci_ss_info_10b7_1102, + &pci_ss_info_10b7_1201, + &pci_ss_info_10b7_1202, + &pci_ss_info_10b7_2000, + &pci_ss_info_10b7_2001, + &pci_ss_info_10b7_2031, + &pci_ss_info_10b7_2101, + &pci_ss_info_10b7_2102, + &pci_ss_info_10b7_3000, + &pci_ss_info_10b7_3590, + &pci_ss_info_10b7_5a57, + &pci_ss_info_10b7_5b57, + &pci_ss_info_10b7_5c57, + &pci_ss_info_10b7_615c, + &pci_ss_info_10b7_6556, + &pci_ss_info_10b7_656a, + &pci_ss_info_10b7_656b, + &pci_ss_info_10b7_7000, + &pci_ss_info_10b7_9004, + &pci_ss_info_10b7_9005, + &pci_ss_info_10b7_9054, + &pci_ss_info_10b7_9055, + &pci_ss_info_10b7_9800, + &pci_ss_info_10b7_9805, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b8[] = { + &pci_ss_info_10b8_2001, + &pci_ss_info_10b8_2002, + &pci_ss_info_10b8_2003, + &pci_ss_info_10b8_2005, + &pci_ss_info_10b8_2011, + &pci_ss_info_10b8_2635, + &pci_ss_info_10b8_2802, + &pci_ss_info_10b8_2835, + &pci_ss_info_10b8_8034, + &pci_ss_info_10b8_a011, + &pci_ss_info_10b8_a012, + &pci_ss_info_10b8_a014, + &pci_ss_info_10b8_a015, + &pci_ss_info_10b8_a016, + &pci_ss_info_10b8_a017, + &pci_ss_info_10b8_a835, + &pci_ss_info_10b8_b452, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10b9[] = { + &pci_ss_info_10b9_0111, + &pci_ss_info_10b9_1521, + &pci_ss_info_10b9_1523, + &pci_ss_info_10b9_1533, + &pci_ss_info_10b9_1541, + &pci_ss_info_10b9_5451, + &pci_ss_info_10b9_7101, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10ba[] = { + &pci_ss_info_10ba_0e00, + NULL +}; +#endif +#define pci_ss_list_10bb NULL +#define pci_ss_list_10bc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10bd[] = { + &pci_ss_info_10bd_0000, + &pci_ss_info_10bd_0320, + NULL +}; +#endif +#define pci_ss_list_10be NULL +#define pci_ss_list_10bf NULL +#define pci_ss_list_10c0 NULL +#define pci_ss_list_10c1 NULL +#define pci_ss_list_10c2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10c3[] = { + &pci_ss_info_10c3_1100, + NULL +}; +#endif +#define pci_ss_list_10c4 NULL +#define pci_ss_list_10c5 NULL +#define pci_ss_list_10c6 NULL +#define pci_ss_list_10c7 NULL +static const pciSubsystemInfo *pci_ss_list_10c8[] = { + &pci_ss_info_10c8_0004, + &pci_ss_info_10c8_0016, + &pci_ss_info_10c8_8005, + NULL +}; +#define pci_ss_list_10c9 NULL +#define pci_ss_list_10ca NULL +#define pci_ss_list_10cb NULL +#define pci_ss_list_10cc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10cd[] = { + &pci_ss_info_10cd_1310, + NULL +}; +#endif +#define pci_ss_list_10ce NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10cf[] = { + &pci_ss_info_10cf_1029, + &pci_ss_info_10cf_102c, + &pci_ss_info_10cf_103c, + &pci_ss_info_10cf_104a, + &pci_ss_info_10cf_1055, + &pci_ss_info_10cf_1056, + &pci_ss_info_10cf_1057, + &pci_ss_info_10cf_1059, + &pci_ss_info_10cf_105e, + &pci_ss_info_10cf_105f, + &pci_ss_info_10cf_1063, + &pci_ss_info_10cf_1064, + &pci_ss_info_10cf_106a, + &pci_ss_info_10cf_1072, + &pci_ss_info_10cf_1094, + &pci_ss_info_10cf_1095, + &pci_ss_info_10cf_1098, + &pci_ss_info_10cf_1099, + &pci_ss_info_10cf_10a8, + &pci_ss_info_10cf_10a9, + &pci_ss_info_10cf_10aa, + &pci_ss_info_10cf_10ab, + &pci_ss_info_10cf_10ac, + &pci_ss_info_10cf_10ad, + &pci_ss_info_10cf_10b4, + &pci_ss_info_10cf_1115, + &pci_ss_info_10cf_1143, + NULL +}; +#endif +#define pci_ss_list_10d1 NULL +#define pci_ss_list_10d2 NULL +#define pci_ss_list_10d3 NULL +#define pci_ss_list_10d4 NULL +#define pci_ss_list_10d5 NULL +#define pci_ss_list_10d6 NULL +#define pci_ss_list_10d7 NULL +#define pci_ss_list_10d8 NULL +#define pci_ss_list_10d9 NULL +#define pci_ss_list_10da NULL +#define pci_ss_list_10db NULL +#define pci_ss_list_10dc NULL +#define pci_ss_list_10dd NULL +static const pciSubsystemInfo *pci_ss_list_10de[] = { + &pci_ss_info_10de_0005, + &pci_ss_info_10de_0008, + &pci_ss_info_10de_000f, + &pci_ss_info_10de_001e, + &pci_ss_info_10de_0020, + &pci_ss_info_10de_002e, + &pci_ss_info_10de_006b, + &pci_ss_info_10de_0091, + &pci_ss_info_10de_00a1, + &pci_ss_info_10de_0179, + &pci_ss_info_10de_01dc, + &pci_ss_info_10de_029b, + &pci_ss_info_10de_0c11, + NULL +}; +#define pci_ss_list_10df NULL +#define pci_ss_list_10e0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10e1[] = { + &pci_ss_info_10e1_0391, + &pci_ss_info_10e1_10cf, + NULL +}; +#endif +#define pci_ss_list_10e2 NULL +#define pci_ss_list_10e3 NULL +#define pci_ss_list_10e4 NULL +#define pci_ss_list_10e5 NULL +#define pci_ss_list_10e6 NULL +#define pci_ss_list_10e7 NULL +#define pci_ss_list_10e8 NULL +#define pci_ss_list_10e9 NULL +#define pci_ss_list_10ea NULL +#define pci_ss_list_10eb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10ec[] = { + &pci_ss_info_10ec_8029, + &pci_ss_info_10ec_8129, + &pci_ss_info_10ec_8138, + &pci_ss_info_10ec_8139, + NULL +}; +#endif +#define pci_ss_list_10ed NULL +#define pci_ss_list_10ee NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10ef[] = { + &pci_ss_info_10ef_8169, + NULL +}; +#endif +#define pci_ss_list_10f0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10f1[] = { + &pci_ss_info_10f1_0002, + &pci_ss_info_10f1_2462, + &pci_ss_info_10f1_2466, + &pci_ss_info_10f1_2891, + NULL +}; +#endif +#define pci_ss_list_10f2 NULL +#define pci_ss_list_10f3 NULL +#define pci_ss_list_10f4 NULL +#define pci_ss_list_10f5 NULL +#define pci_ss_list_10f6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10f7[] = { + &pci_ss_info_10f7_8308, + &pci_ss_info_10f7_8309, + &pci_ss_info_10f7_830b, + &pci_ss_info_10f7_830d, + &pci_ss_info_10f7_8312, + &pci_ss_info_10f7_8338, + NULL +}; +#endif +#define pci_ss_list_10f8 NULL +#define pci_ss_list_10f9 NULL +#define pci_ss_list_10fa NULL +#define pci_ss_list_10fb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10fc[] = { + &pci_ss_info_10fc_d003, + &pci_ss_info_10fc_d035, + &pci_ss_info_10fc_d038, + &pci_ss_info_10fc_d039, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_10fd[] = { + &pci_ss_info_10fd_a430, + NULL +}; +#endif +#define pci_ss_list_10fe NULL +#define pci_ss_list_10ff NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1100[] = { + &pci_ss_info_1100_102b, + NULL +}; +#endif +#define pci_ss_list_1101 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1102[] = { + &pci_ss_info_1102_0007, + &pci_ss_info_1102_0008, + &pci_ss_info_1102_0010, + &pci_ss_info_1102_0020, + &pci_ss_info_1102_0021, + &pci_ss_info_1102_002f, + &pci_ss_info_1102_0040, + &pci_ss_info_1102_0051, + &pci_ss_info_1102_0053, + &pci_ss_info_1102_0058, + &pci_ss_info_1102_1001, + &pci_ss_info_1102_1002, + &pci_ss_info_1102_1003, + &pci_ss_info_1102_1006, + &pci_ss_info_1102_1007, + &pci_ss_info_1102_100a, + &pci_ss_info_1102_100f, + &pci_ss_info_1102_1015, + &pci_ss_info_1102_1016, + &pci_ss_info_1102_1018, + &pci_ss_info_1102_101d, + &pci_ss_info_1102_101e, + &pci_ss_info_1102_1020, + &pci_ss_info_1102_1021, + &pci_ss_info_1102_1023, + &pci_ss_info_1102_1024, + &pci_ss_info_1102_1026, + &pci_ss_info_1102_1029, + &pci_ss_info_1102_102c, + &pci_ss_info_1102_102d, + &pci_ss_info_1102_102e, + &pci_ss_info_1102_102f, + &pci_ss_info_1102_1031, + &pci_ss_info_1102_1034, + &pci_ss_info_1102_2002, + &pci_ss_info_1102_4001, + &pci_ss_info_1102_8022, + &pci_ss_info_1102_8023, + &pci_ss_info_1102_8024, + &pci_ss_info_1102_8025, + &pci_ss_info_1102_8026, + &pci_ss_info_1102_8027, + &pci_ss_info_1102_8028, + &pci_ss_info_1102_8031, + &pci_ss_info_1102_8040, + &pci_ss_info_1102_8051, + &pci_ss_info_1102_8061, + &pci_ss_info_1102_8064, + &pci_ss_info_1102_8065, + &pci_ss_info_1102_8067, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1103[] = { + &pci_ss_info_1103_0001, + &pci_ss_info_1103_0004, + &pci_ss_info_1103_0005, + NULL +}; +#endif +#define pci_ss_list_1104 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1105[] = { + &pci_ss_info_1105_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1106[] = { + &pci_ss_info_1106_0000, + &pci_ss_info_1106_0100, + &pci_ss_info_1106_0102, + &pci_ss_info_1106_0571, + &pci_ss_info_1106_0686, + &pci_ss_info_1106_3059, + &pci_ss_info_1106_3227, + &pci_ss_info_1106_4161, + &pci_ss_info_1106_4170, + &pci_ss_info_1106_4511, + &pci_ss_info_1106_4552, + NULL +}; +#endif +#define pci_ss_list_1107 NULL +#define pci_ss_list_1108 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1109[] = { + &pci_ss_info_1109_2400, + &pci_ss_info_1109_2a00, + &pci_ss_info_1109_2b00, + &pci_ss_info_1109_3000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_110a[] = { + &pci_ss_info_110a_0000, + &pci_ss_info_110a_0018, + &pci_ss_info_110a_001e, + &pci_ss_info_110a_0021, + &pci_ss_info_110a_0032, + &pci_ss_info_110a_0051, + &pci_ss_info_110a_008b, + &pci_ss_info_110a_5938, + &pci_ss_info_110a_8005, + &pci_ss_info_110a_ffff, + NULL +}; +#endif +#define pci_ss_list_110b NULL +#define pci_ss_list_110c NULL +#define pci_ss_list_110d NULL +#define pci_ss_list_110e NULL +#define pci_ss_list_110f NULL +#define pci_ss_list_1110 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1111[] = { + &pci_ss_info_1111_1111, + &pci_ss_info_1111_1112, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1112[] = { + &pci_ss_info_1112_2300, + &pci_ss_info_1112_2320, + &pci_ss_info_1112_2340, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1113[] = { + &pci_ss_info_1113_1207, + &pci_ss_info_1113_1208, + &pci_ss_info_1113_1211, + &pci_ss_info_1113_1220, + &pci_ss_info_1113_2220, + &pci_ss_info_1113_2242, + &pci_ss_info_1113_4203, + &pci_ss_info_1113_9211, + &pci_ss_info_1113_d301, + &pci_ss_info_1113_ec01, + &pci_ss_info_1113_ee03, + &pci_ss_info_1113_ee08, + &pci_ss_info_1113_ee20, + &pci_ss_info_1113_ee24, + NULL +}; +#endif +#define pci_ss_list_1114 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1115[] = { + &pci_ss_info_1115_1181, + NULL +}; +#endif +#define pci_ss_list_1116 NULL +#define pci_ss_list_1117 NULL +#define pci_ss_list_1118 NULL +#define pci_ss_list_1119 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_111a[] = { + &pci_ss_info_111a_0000, + &pci_ss_info_111a_0001, + &pci_ss_info_111a_0009, + &pci_ss_info_111a_0101, + &pci_ss_info_111a_0109, + &pci_ss_info_111a_0809, + &pci_ss_info_111a_0909, + &pci_ss_info_111a_0a09, + &pci_ss_info_111a_1001, + &pci_ss_info_111a_1020, + NULL +}; +#endif +#define pci_ss_list_111b NULL +#define pci_ss_list_111c NULL +#define pci_ss_list_111d NULL +#define pci_ss_list_111e NULL +#define pci_ss_list_111f NULL +#define pci_ss_list_1120 NULL +#define pci_ss_list_1121 NULL +#define pci_ss_list_1122 NULL +#define pci_ss_list_1123 NULL +#define pci_ss_list_1124 NULL +#define pci_ss_list_1125 NULL +#define pci_ss_list_1126 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1127[] = { + &pci_ss_info_1127_0400, + NULL +}; +#endif +#define pci_ss_list_1129 NULL +#define pci_ss_list_112a NULL +#define pci_ss_list_112b NULL +#define pci_ss_list_112c NULL +#define pci_ss_list_112d NULL +#define pci_ss_list_112e NULL +#define pci_ss_list_112f NULL +#define pci_ss_list_1130 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1131[] = { + &pci_ss_info_1131_0000, + &pci_ss_info_1131_2001, + &pci_ss_info_1131_2004, + &pci_ss_info_1131_2005, + &pci_ss_info_1131_2018, + &pci_ss_info_1131_4e85, + &pci_ss_info_1131_4ee9, + &pci_ss_info_1131_4f56, + &pci_ss_info_1131_4f60, + &pci_ss_info_1131_4f61, + &pci_ss_info_1131_5f61, + &pci_ss_info_1131_6752, + NULL +}; +#endif +#define pci_ss_list_1132 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1133[] = { + &pci_ss_info_1133_1300, + &pci_ss_info_1133_1800, + &pci_ss_info_1133_1c01, + &pci_ss_info_1133_1c02, + &pci_ss_info_1133_1c03, + &pci_ss_info_1133_1c04, + &pci_ss_info_1133_1c05, + &pci_ss_info_1133_1c06, + &pci_ss_info_1133_1c07, + &pci_ss_info_1133_1c08, + &pci_ss_info_1133_1c09, + &pci_ss_info_1133_1c0a, + &pci_ss_info_1133_1c0b, + &pci_ss_info_1133_1c0c, + &pci_ss_info_1133_2400, + &pci_ss_info_1133_2800, + &pci_ss_info_1133_e013, + &pci_ss_info_1133_e015, + &pci_ss_info_1133_e017, + &pci_ss_info_1133_e018, + &pci_ss_info_1133_e019, + &pci_ss_info_1133_e01b, + &pci_ss_info_1133_e024, + &pci_ss_info_1133_e028, + NULL +}; +#endif +#define pci_ss_list_1134 NULL +#define pci_ss_list_1135 NULL +#define pci_ss_list_1136 NULL +#define pci_ss_list_1137 NULL +#define pci_ss_list_1138 NULL +#define pci_ss_list_1139 NULL +#define pci_ss_list_113a NULL +#define pci_ss_list_113b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_113c[] = { + &pci_ss_info_113c_03a2, + NULL +}; +#endif +#define pci_ss_list_113d NULL +#define pci_ss_list_113e NULL +#define pci_ss_list_113f NULL +#define pci_ss_list_1140 NULL +#define pci_ss_list_1141 NULL +#define pci_ss_list_1142 NULL +#define pci_ss_list_1143 NULL +#define pci_ss_list_1144 NULL +#define pci_ss_list_1145 NULL +#define pci_ss_list_1146 NULL +#define pci_ss_list_1147 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1148[] = { + &pci_ss_info_1148_0121, + &pci_ss_info_1148_0221, + &pci_ss_info_1148_0321, + &pci_ss_info_1148_0421, + &pci_ss_info_1148_0621, + &pci_ss_info_1148_0721, + &pci_ss_info_1148_0821, + &pci_ss_info_1148_0921, + &pci_ss_info_1148_1121, + &pci_ss_info_1148_1221, + &pci_ss_info_1148_2100, + &pci_ss_info_1148_21d0, + &pci_ss_info_1148_2200, + &pci_ss_info_1148_3221, + &pci_ss_info_1148_5021, + &pci_ss_info_1148_5041, + &pci_ss_info_1148_5043, + &pci_ss_info_1148_5051, + &pci_ss_info_1148_5061, + &pci_ss_info_1148_5071, + &pci_ss_info_1148_5521, + &pci_ss_info_1148_5522, + &pci_ss_info_1148_5541, + &pci_ss_info_1148_5543, + &pci_ss_info_1148_5544, + &pci_ss_info_1148_5821, + &pci_ss_info_1148_5822, + &pci_ss_info_1148_5841, + &pci_ss_info_1148_5843, + &pci_ss_info_1148_5844, + &pci_ss_info_1148_8100, + &pci_ss_info_1148_8200, + &pci_ss_info_1148_9100, + &pci_ss_info_1148_9200, + &pci_ss_info_1148_9521, + &pci_ss_info_1148_9821, + &pci_ss_info_1148_9822, + &pci_ss_info_1148_9841, + &pci_ss_info_1148_9842, + &pci_ss_info_1148_9843, + &pci_ss_info_1148_9844, + &pci_ss_info_1148_9861, + &pci_ss_info_1148_9862, + &pci_ss_info_1148_9871, + &pci_ss_info_1148_9872, + NULL +}; +#endif +#define pci_ss_list_1149 NULL +#define pci_ss_list_114a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_114b[] = { + &pci_ss_info_114b_2003, + NULL +}; +#endif +#define pci_ss_list_114c NULL +#define pci_ss_list_114d NULL +#define pci_ss_list_114e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_114f[] = { + &pci_ss_info_114f_0030, + &pci_ss_info_114f_0031, + &pci_ss_info_114f_0050, + &pci_ss_info_114f_0051, + &pci_ss_info_114f_0052, + &pci_ss_info_114f_0053, + NULL +}; +#endif +#define pci_ss_list_1150 NULL +#define pci_ss_list_1151 NULL +#define pci_ss_list_1152 NULL +#define pci_ss_list_1153 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1154[] = { + &pci_ss_info_1154_0330, + NULL +}; +#endif +#define pci_ss_list_1155 NULL +#define pci_ss_list_1156 NULL +#define pci_ss_list_1157 NULL +#define pci_ss_list_1158 NULL +#define pci_ss_list_1159 NULL +#define pci_ss_list_115a NULL +#define pci_ss_list_115b NULL +#define pci_ss_list_115c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_115d[] = { + &pci_ss_info_115d_0002, + &pci_ss_info_115d_0181, + &pci_ss_info_115d_0182, + &pci_ss_info_115d_0183, + &pci_ss_info_115d_1081, + &pci_ss_info_115d_1181, + &pci_ss_info_115d_1182, + NULL +}; +#endif +#define pci_ss_list_115e NULL +#define pci_ss_list_115f NULL +#define pci_ss_list_1160 NULL +#define pci_ss_list_1161 NULL +#define pci_ss_list_1162 NULL +#define pci_ss_list_1163 NULL +#define pci_ss_list_1164 NULL +#define pci_ss_list_1165 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1166[] = { + &pci_ss_info_1166_0132, + &pci_ss_info_1166_1648, + NULL +}; +#endif +#define pci_ss_list_1167 NULL +#define pci_ss_list_1168 NULL +#define pci_ss_list_1169 NULL +#define pci_ss_list_116a NULL +#define pci_ss_list_116b NULL +#define pci_ss_list_116c NULL +#define pci_ss_list_116d NULL +#define pci_ss_list_116e NULL +#define pci_ss_list_116f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1170[] = { + &pci_ss_info_1170_3209, + NULL +}; +#endif +#define pci_ss_list_1171 NULL +#define pci_ss_list_1172 NULL +#define pci_ss_list_1173 NULL +#define pci_ss_list_1174 NULL +#define pci_ss_list_1175 NULL +#define pci_ss_list_1176 NULL +#define pci_ss_list_1177 NULL +#define pci_ss_list_1178 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1179[] = { + &pci_ss_info_1179_0001, + &pci_ss_info_1179_0002, + &pci_ss_info_1179_0003, + &pci_ss_info_1179_0181, + &pci_ss_info_1179_0203, + &pci_ss_info_1179_0204, + &pci_ss_info_1179_ff00, + &pci_ss_info_1179_ff01, + &pci_ss_info_1179_ff10, + NULL +}; +#endif +#define pci_ss_list_117a NULL +#define pci_ss_list_117b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_117c[] = { + &pci_ss_info_117c_8013, + &pci_ss_info_117c_8014, + NULL +}; +#endif +#define pci_ss_list_117d NULL +#define pci_ss_list_117e NULL +#define pci_ss_list_117f NULL +#define pci_ss_list_1180 NULL +#define pci_ss_list_1181 NULL +#define pci_ss_list_1183 NULL +#define pci_ss_list_1184 NULL +#define pci_ss_list_1185 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1186[] = { + &pci_ss_info_1186_0100, + &pci_ss_info_1186_0300, + &pci_ss_info_1186_1002, + &pci_ss_info_1186_1012, + &pci_ss_info_1186_1100, + &pci_ss_info_1186_1101, + &pci_ss_info_1186_1102, + &pci_ss_info_1186_1112, + &pci_ss_info_1186_1140, + &pci_ss_info_1186_1142, + &pci_ss_info_1186_1200, + &pci_ss_info_1186_1300, + &pci_ss_info_1186_1301, + &pci_ss_info_1186_1303, + &pci_ss_info_1186_1320, + &pci_ss_info_1186_1400, + &pci_ss_info_1186_1401, + &pci_ss_info_1186_1403, + &pci_ss_info_1186_3202, + &pci_ss_info_1186_3203, + &pci_ss_info_1186_3501, + &pci_ss_info_1186_3700, + &pci_ss_info_1186_3a12, + &pci_ss_info_1186_3a13, + &pci_ss_info_1186_3a14, + &pci_ss_info_1186_3a15, + &pci_ss_info_1186_3a16, + &pci_ss_info_1186_3a17, + &pci_ss_info_1186_3a18, + &pci_ss_info_1186_3a19, + &pci_ss_info_1186_3a22, + &pci_ss_info_1186_3a23, + &pci_ss_info_1186_3a24, + &pci_ss_info_1186_3a63, + &pci_ss_info_1186_3a93, + &pci_ss_info_1186_3a94, + &pci_ss_info_1186_3ab0, + &pci_ss_info_1186_3b00, + &pci_ss_info_1186_3b01, + &pci_ss_info_1186_3b04, + &pci_ss_info_1186_3b05, + &pci_ss_info_1186_3c08, + &pci_ss_info_1186_3c09, + &pci_ss_info_1186_4c00, + &pci_ss_info_1186_7801, + &pci_ss_info_1186_8139, + NULL +}; +#endif +#define pci_ss_list_1187 NULL +#define pci_ss_list_1188 NULL +#define pci_ss_list_1189 NULL +#define pci_ss_list_118a NULL +#define pci_ss_list_118b NULL +#define pci_ss_list_118c NULL +#define pci_ss_list_118d NULL +#define pci_ss_list_118e NULL +#define pci_ss_list_118f NULL +#define pci_ss_list_1190 NULL +#define pci_ss_list_1191 NULL +#define pci_ss_list_1192 NULL +#define pci_ss_list_1193 NULL +#define pci_ss_list_1194 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1195[] = { + &pci_ss_info_1195_1320, + NULL +}; +#endif +#define pci_ss_list_1196 NULL +#define pci_ss_list_1197 NULL +#define pci_ss_list_1198 NULL +#define pci_ss_list_1199 NULL +#define pci_ss_list_119a NULL +#define pci_ss_list_119b NULL +#define pci_ss_list_119c NULL +#define pci_ss_list_119d NULL +#define pci_ss_list_119e NULL +#define pci_ss_list_119f NULL +#define pci_ss_list_11a0 NULL +#define pci_ss_list_11a1 NULL +#define pci_ss_list_11a2 NULL +#define pci_ss_list_11a3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11a4[] = { + &pci_ss_info_11a4_000a, + &pci_ss_info_11a4_000b, + &pci_ss_info_11a4_0028, + &pci_ss_info_11a4_0038, + NULL +}; +#endif +#define pci_ss_list_11a5 NULL +#define pci_ss_list_11a6 NULL +#define pci_ss_list_11a7 NULL +#define pci_ss_list_11a8 NULL +#define pci_ss_list_11a9 NULL +#define pci_ss_list_11aa NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11ab[] = { + &pci_ss_info_11ab_0121, + &pci_ss_info_11ab_0321, + &pci_ss_info_11ab_1021, + &pci_ss_info_11ab_3521, + &pci_ss_info_11ab_3621, + &pci_ss_info_11ab_4320, + &pci_ss_info_11ab_5021, + &pci_ss_info_11ab_5221, + &pci_ss_info_11ab_5321, + &pci_ss_info_11ab_9521, + NULL +}; +#endif +#define pci_ss_list_11ac NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11ad[] = { + &pci_ss_info_11ad_0002, + &pci_ss_info_11ad_0003, + &pci_ss_info_11ad_c001, + &pci_ss_info_11ad_f003, + &pci_ss_info_11ad_ffff, + NULL +}; +#endif +#define pci_ss_list_11ae NULL +#define pci_ss_list_11af NULL +#define pci_ss_list_11b0 NULL +#define pci_ss_list_11b1 NULL +#define pci_ss_list_11b2 NULL +#define pci_ss_list_11b3 NULL +#define pci_ss_list_11b4 NULL +#define pci_ss_list_11b5 NULL +#define pci_ss_list_11b6 NULL +#define pci_ss_list_11b7 NULL +#define pci_ss_list_11b8 NULL +#define pci_ss_list_11b9 NULL +#define pci_ss_list_11ba NULL +#define pci_ss_list_11bb NULL +#define pci_ss_list_11bc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11bd[] = { + &pci_ss_info_11bd_0006, + &pci_ss_info_11bd_000a, + &pci_ss_info_11bd_000e, + &pci_ss_info_11bd_000f, + &pci_ss_info_11bd_0012, + &pci_ss_info_11bd_001c, + &pci_ss_info_11bd_002b, + &pci_ss_info_11bd_002d, + &pci_ss_info_11bd_002e, + NULL +}; +#endif +#define pci_ss_list_11be NULL +#define pci_ss_list_11bf NULL +#define pci_ss_list_11c0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11c1[] = { + &pci_ss_info_11c1_0440, + &pci_ss_info_11c1_0441, + &pci_ss_info_11c1_0442, + &pci_ss_info_11c1_ab12, + &pci_ss_info_11c1_ab13, + &pci_ss_info_11c1_ab15, + &pci_ss_info_11c1_ab16, + NULL +}; +#endif +#define pci_ss_list_11c2 NULL +#define pci_ss_list_11c3 NULL +#define pci_ss_list_11c4 NULL +#define pci_ss_list_11c5 NULL +#define pci_ss_list_11c6 NULL +#define pci_ss_list_11c7 NULL +#define pci_ss_list_11c8 NULL +#define pci_ss_list_11c9 NULL +#define pci_ss_list_11ca NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11cb[] = { + &pci_ss_info_11cb_0200, + &pci_ss_info_11cb_b008, + NULL +}; +#endif +#define pci_ss_list_11cc NULL +#define pci_ss_list_11cd NULL +#define pci_ss_list_11ce NULL +#define pci_ss_list_11cf NULL +#define pci_ss_list_11d0 NULL +#define pci_ss_list_11d1 NULL +#define pci_ss_list_11d2 NULL +#define pci_ss_list_11d3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11d4[] = { + &pci_ss_info_11d4_0040, + &pci_ss_info_11d4_0048, + &pci_ss_info_11d4_5340, + NULL +}; +#endif +#define pci_ss_list_11d5 NULL +#define pci_ss_list_11d6 NULL +#define pci_ss_list_11d7 NULL +#define pci_ss_list_11d8 NULL +#define pci_ss_list_11d9 NULL +#define pci_ss_list_11da NULL +#define pci_ss_list_11db NULL +#define pci_ss_list_11dc NULL +#define pci_ss_list_11dd NULL +#define pci_ss_list_11de NULL +#define pci_ss_list_11df NULL +#define pci_ss_list_11e0 NULL +#define pci_ss_list_11e1 NULL +#define pci_ss_list_11e2 NULL +#define pci_ss_list_11e3 NULL +#define pci_ss_list_11e4 NULL +#define pci_ss_list_11e5 NULL +#define pci_ss_list_11e6 NULL +#define pci_ss_list_11e7 NULL +#define pci_ss_list_11e8 NULL +#define pci_ss_list_11e9 NULL +#define pci_ss_list_11ea NULL +#define pci_ss_list_11eb NULL +#define pci_ss_list_11ec NULL +#define pci_ss_list_11ed NULL +#define pci_ss_list_11ee NULL +#define pci_ss_list_11ef NULL +#define pci_ss_list_11f0 NULL +#define pci_ss_list_11f1 NULL +#define pci_ss_list_11f2 NULL +#define pci_ss_list_11f3 NULL +#define pci_ss_list_11f4 NULL +#define pci_ss_list_11f5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_11f6[] = { + &pci_ss_info_11f6_0503, + &pci_ss_info_11f6_2011, + &pci_ss_info_11f6_8139, + NULL +}; +#endif +#define pci_ss_list_11f7 NULL +#define pci_ss_list_11f8 NULL +#define pci_ss_list_11f9 NULL +#define pci_ss_list_11fa NULL +#define pci_ss_list_11fb NULL +#define pci_ss_list_11fc NULL +#define pci_ss_list_11fd NULL +#define pci_ss_list_11fe NULL +#define pci_ss_list_11ff NULL +#define pci_ss_list_1200 NULL +#define pci_ss_list_1201 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1202[] = { + &pci_ss_info_1202_9841, + &pci_ss_info_1202_9842, + &pci_ss_info_1202_9843, + &pci_ss_info_1202_9844, + NULL +}; +#endif +#define pci_ss_list_1203 NULL +#define pci_ss_list_1204 NULL +#define pci_ss_list_1205 NULL +#define pci_ss_list_1206 NULL +#define pci_ss_list_1208 NULL +#define pci_ss_list_1209 NULL +#define pci_ss_list_120a NULL +#define pci_ss_list_120b NULL +#define pci_ss_list_120c NULL +#define pci_ss_list_120d NULL +#define pci_ss_list_120e NULL +#define pci_ss_list_120f NULL +#define pci_ss_list_1210 NULL +#define pci_ss_list_1211 NULL +#define pci_ss_list_1212 NULL +#define pci_ss_list_1213 NULL +#define pci_ss_list_1214 NULL +#define pci_ss_list_1215 NULL +#define pci_ss_list_1216 NULL +#define pci_ss_list_1217 NULL +#define pci_ss_list_1218 NULL +#define pci_ss_list_1219 NULL +static const pciSubsystemInfo *pci_ss_list_121a[] = { + &pci_ss_info_121a_0001, + &pci_ss_info_121a_0003, + &pci_ss_info_121a_0004, + &pci_ss_info_121a_0009, + &pci_ss_info_121a_0030, + &pci_ss_info_121a_0031, + &pci_ss_info_121a_0034, + &pci_ss_info_121a_0036, + &pci_ss_info_121a_0037, + &pci_ss_info_121a_0038, + &pci_ss_info_121a_003a, + &pci_ss_info_121a_0044, + &pci_ss_info_121a_004b, + &pci_ss_info_121a_004c, + &pci_ss_info_121a_004d, + &pci_ss_info_121a_004e, + &pci_ss_info_121a_0051, + &pci_ss_info_121a_0052, + &pci_ss_info_121a_0057, + &pci_ss_info_121a_0060, + &pci_ss_info_121a_0061, + &pci_ss_info_121a_0062, + NULL +}; +#define pci_ss_list_121b NULL +#define pci_ss_list_121c NULL +#define pci_ss_list_121d NULL +#define pci_ss_list_121e NULL +#define pci_ss_list_121f NULL +#define pci_ss_list_1220 NULL +#define pci_ss_list_1221 NULL +#define pci_ss_list_1222 NULL +#define pci_ss_list_1223 NULL +#define pci_ss_list_1224 NULL +#define pci_ss_list_1225 NULL +#define pci_ss_list_1227 NULL +#define pci_ss_list_1228 NULL +#define pci_ss_list_1229 NULL +#define pci_ss_list_122a NULL +#define pci_ss_list_122b NULL +#define pci_ss_list_122c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_122d[] = { + &pci_ss_info_122d_0001, + &pci_ss_info_122d_1002, + &pci_ss_info_122d_1206, + &pci_ss_info_122d_1207, + &pci_ss_info_122d_1208, + &pci_ss_info_122d_1400, + &pci_ss_info_122d_4002, + &pci_ss_info_122d_4003, + &pci_ss_info_122d_4005, + &pci_ss_info_122d_4006, + &pci_ss_info_122d_4007, + &pci_ss_info_122d_4008, + &pci_ss_info_122d_4009, + &pci_ss_info_122d_4010, + &pci_ss_info_122d_4011, + &pci_ss_info_122d_4012, + &pci_ss_info_122d_4013, + &pci_ss_info_122d_4015, + &pci_ss_info_122d_4016, + &pci_ss_info_122d_4017, + &pci_ss_info_122d_4018, + &pci_ss_info_122d_4019, + &pci_ss_info_122d_4020, + &pci_ss_info_122d_4021, + &pci_ss_info_122d_4022, + &pci_ss_info_122d_4023, + &pci_ss_info_122d_4024, + &pci_ss_info_122d_4025, + &pci_ss_info_122d_4027, + &pci_ss_info_122d_4029, + &pci_ss_info_122d_4030, + &pci_ss_info_122d_4031, + &pci_ss_info_122d_4033, + &pci_ss_info_122d_4034, + &pci_ss_info_122d_4035, + &pci_ss_info_122d_4050, + &pci_ss_info_122d_4051, + &pci_ss_info_122d_4052, + &pci_ss_info_122d_4054, + &pci_ss_info_122d_4055, + &pci_ss_info_122d_4056, + &pci_ss_info_122d_4057, + &pci_ss_info_122d_4100, + &pci_ss_info_122d_4101, + &pci_ss_info_122d_4102, + &pci_ss_info_122d_4302, + NULL +}; +#endif +#define pci_ss_list_122e NULL +#define pci_ss_list_122f NULL +#define pci_ss_list_1230 NULL +#define pci_ss_list_1231 NULL +#define pci_ss_list_1232 NULL +#define pci_ss_list_1233 NULL +#define pci_ss_list_1234 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1235[] = { + &pci_ss_info_1235_4320, + &pci_ss_info_1235_4321, + &pci_ss_info_1235_4322, + &pci_ss_info_1235_4324, + NULL +}; +#endif +#define pci_ss_list_1236 NULL +#define pci_ss_list_1237 NULL +#define pci_ss_list_1238 NULL +#define pci_ss_list_1239 NULL +#define pci_ss_list_123a NULL +#define pci_ss_list_123b NULL +#define pci_ss_list_123c NULL +#define pci_ss_list_123d NULL +#define pci_ss_list_123e NULL +#define pci_ss_list_123f NULL +#define pci_ss_list_1240 NULL +#define pci_ss_list_1241 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1242[] = { + &pci_ss_info_1242_6562, + &pci_ss_info_1242_656a, + NULL +}; +#endif +#define pci_ss_list_1243 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1244[] = { + &pci_ss_info_1244_0a00, + &pci_ss_info_1244_0f00, + NULL +}; +#endif +#define pci_ss_list_1245 NULL +#define pci_ss_list_1246 NULL +#define pci_ss_list_1247 NULL +#define pci_ss_list_1248 NULL +#define pci_ss_list_1249 NULL +#define pci_ss_list_124a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_124b[] = { + &pci_ss_info_124b_1070, + &pci_ss_info_124b_1170, + &pci_ss_info_124b_9080, + NULL +}; +#endif +#define pci_ss_list_124c NULL +#define pci_ss_list_124d NULL +#define pci_ss_list_124e NULL +#define pci_ss_list_124f NULL +#define pci_ss_list_1250 NULL +#define pci_ss_list_1251 NULL +#define pci_ss_list_1253 NULL +#define pci_ss_list_1254 NULL +#define pci_ss_list_1255 NULL +#define pci_ss_list_1256 NULL +#define pci_ss_list_1257 NULL +#define pci_ss_list_1258 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1259[] = { + &pci_ss_info_1259_2400, + &pci_ss_info_1259_2450, + &pci_ss_info_1259_2454, + &pci_ss_info_1259_2500, + &pci_ss_info_1259_2503, + &pci_ss_info_1259_2560, + &pci_ss_info_1259_2561, + &pci_ss_info_1259_2700, + &pci_ss_info_1259_2701, + &pci_ss_info_1259_2702, + &pci_ss_info_1259_2703, + &pci_ss_info_1259_2704, + &pci_ss_info_1259_2800, + &pci_ss_info_1259_2970, + &pci_ss_info_1259_2971, + &pci_ss_info_1259_2972, + &pci_ss_info_1259_2973, + &pci_ss_info_1259_2974, + &pci_ss_info_1259_2975, + &pci_ss_info_1259_2976, + &pci_ss_info_1259_2977, + &pci_ss_info_1259_c104, + &pci_ss_info_1259_c107, + NULL +}; +#endif +#define pci_ss_list_125a NULL +#define pci_ss_list_125b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_125c[] = { + &pci_ss_info_125c_0640, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_125d[] = { + &pci_ss_info_125d_0424, + &pci_ss_info_125d_0425, + &pci_ss_info_125d_0426, + &pci_ss_info_125d_0427, + &pci_ss_info_125d_0428, + &pci_ss_info_125d_0429, + &pci_ss_info_125d_1988, + &pci_ss_info_125d_1989, + &pci_ss_info_125d_8888, + NULL +}; +#endif +#define pci_ss_list_125e NULL +#define pci_ss_list_125f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1260[] = { + &pci_ss_info_1260_0000, + NULL +}; +#endif +#define pci_ss_list_1261 NULL +#define pci_ss_list_1262 NULL +#define pci_ss_list_1263 NULL +#define pci_ss_list_1264 NULL +#define pci_ss_list_1265 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1266[] = { + &pci_ss_info_1266_0001, + &pci_ss_info_1266_0004, + &pci_ss_info_1266_1910, + NULL +}; +#endif +#define pci_ss_list_1267 NULL +#define pci_ss_list_1268 NULL +#define pci_ss_list_1269 NULL +#define pci_ss_list_126a NULL +#define pci_ss_list_126b NULL +#define pci_ss_list_126c NULL +#define pci_ss_list_126d NULL +#define pci_ss_list_126e NULL +#define pci_ss_list_126f NULL +#define pci_ss_list_1270 NULL +#define pci_ss_list_1271 NULL +#define pci_ss_list_1272 NULL +#define pci_ss_list_1273 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1274[] = { + &pci_ss_info_1274_1371, + &pci_ss_info_1274_2000, + &pci_ss_info_1274_2003, + &pci_ss_info_1274_5880, + &pci_ss_info_1274_8001, + NULL +}; +#endif +#define pci_ss_list_1275 NULL +#define pci_ss_list_1276 NULL +#define pci_ss_list_1277 NULL +#define pci_ss_list_1278 NULL +#define pci_ss_list_1279 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_127a[] = { + &pci_ss_info_127a_0001, + &pci_ss_info_127a_0002, + &pci_ss_info_127a_0003, + &pci_ss_info_127a_0044, + &pci_ss_info_127a_0048, + &pci_ss_info_127a_0122, + &pci_ss_info_127a_0144, + &pci_ss_info_127a_0222, + &pci_ss_info_127a_0244, + &pci_ss_info_127a_0322, + &pci_ss_info_127a_0422, + &pci_ss_info_127a_1002, + &pci_ss_info_127a_1122, + &pci_ss_info_127a_1222, + &pci_ss_info_127a_1322, + &pci_ss_info_127a_1522, + &pci_ss_info_127a_1622, + &pci_ss_info_127a_1722, + &pci_ss_info_127a_4311, + NULL +}; +#endif +#define pci_ss_list_127b NULL +#define pci_ss_list_127c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_127d[] = { + &pci_ss_info_127d_0000, + NULL +}; +#endif +#define pci_ss_list_127e NULL +#define pci_ss_list_127f NULL +#define pci_ss_list_1280 NULL +#define pci_ss_list_1281 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1282[] = { + &pci_ss_info_1282_9100, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1283[] = { + &pci_ss_info_1283_0001, + NULL +}; +#endif +#define pci_ss_list_1284 NULL +#define pci_ss_list_1285 NULL +#define pci_ss_list_1286 NULL +#define pci_ss_list_1287 NULL +#define pci_ss_list_1288 NULL +#define pci_ss_list_1289 NULL +#define pci_ss_list_128a NULL +#define pci_ss_list_128b NULL +#define pci_ss_list_128c NULL +#define pci_ss_list_128d NULL +#define pci_ss_list_128e NULL +#define pci_ss_list_128f NULL +#define pci_ss_list_1290 NULL +#define pci_ss_list_1291 NULL +#define pci_ss_list_1292 NULL +#define pci_ss_list_1293 NULL +#define pci_ss_list_1294 NULL +#define pci_ss_list_1295 NULL +#define pci_ss_list_1296 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1297[] = { + &pci_ss_info_1297_c160, + &pci_ss_info_1297_c240, + &pci_ss_info_1297_c241, + &pci_ss_info_1297_c242, + &pci_ss_info_1297_c243, + &pci_ss_info_1297_c244, + &pci_ss_info_1297_f641, + NULL +}; +#endif +#define pci_ss_list_1298 NULL +#define pci_ss_list_1299 NULL +#define pci_ss_list_129a NULL +#define pci_ss_list_129b NULL +#define pci_ss_list_129c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_129d[] = { + &pci_ss_info_129d_0002, + NULL +}; +#endif +#define pci_ss_list_129e NULL +#define pci_ss_list_129f NULL +#define pci_ss_list_12a0 NULL +#define pci_ss_list_12a1 NULL +#define pci_ss_list_12a2 NULL +#define pci_ss_list_12a3 NULL +#define pci_ss_list_12a4 NULL +#define pci_ss_list_12a5 NULL +#define pci_ss_list_12a6 NULL +#define pci_ss_list_12a7 NULL +#define pci_ss_list_12a8 NULL +#define pci_ss_list_12a9 NULL +#define pci_ss_list_12aa NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12ab[] = { + &pci_ss_info_12ab_0000, + &pci_ss_info_12ab_0800, + &pci_ss_info_12ab_5961, + &pci_ss_info_12ab_fff3, + &pci_ss_info_12ab_ffff, + NULL +}; +#endif +#define pci_ss_list_12ac NULL +#define pci_ss_list_12ad NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12ae[] = { + &pci_ss_info_12ae_0001, + &pci_ss_info_12ae_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12af[] = { + &pci_ss_info_12af_0019, + NULL +}; +#endif +#define pci_ss_list_12b0 NULL +#define pci_ss_list_12b1 NULL +#define pci_ss_list_12b2 NULL +#define pci_ss_list_12b3 NULL +#define pci_ss_list_12b4 NULL +#define pci_ss_list_12b5 NULL +#define pci_ss_list_12b6 NULL +#define pci_ss_list_12b7 NULL +#define pci_ss_list_12b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12b9[] = { + &pci_ss_info_12b9_005c, + &pci_ss_info_12b9_005e, + &pci_ss_info_12b9_0062, + &pci_ss_info_12b9_0068, + &pci_ss_info_12b9_007a, + &pci_ss_info_12b9_007f, + &pci_ss_info_12b9_0080, + &pci_ss_info_12b9_0081, + &pci_ss_info_12b9_0091, + &pci_ss_info_12b9_00a2, + &pci_ss_info_12b9_00a3, + &pci_ss_info_12b9_00aa, + &pci_ss_info_12b9_00ab, + &pci_ss_info_12b9_00ac, + &pci_ss_info_12b9_00ad, + &pci_ss_info_12b9_00c4, + NULL +}; +#endif +#define pci_ss_list_12ba NULL +#define pci_ss_list_12bb NULL +#define pci_ss_list_12bc NULL +#define pci_ss_list_12bd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12be[] = { + &pci_ss_info_12be_3042, + NULL +}; +#endif +#define pci_ss_list_12bf NULL +#define pci_ss_list_12c0 NULL +#define pci_ss_list_12c1 NULL +#define pci_ss_list_12c2 NULL +#define pci_ss_list_12c3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12c4[] = { + &pci_ss_info_12c4_0200, + &pci_ss_info_12c4_0201, + &pci_ss_info_12c4_0202, + &pci_ss_info_12c4_0203, + &pci_ss_info_12c4_0210, + &pci_ss_info_12c4_0211, + NULL +}; +#endif +#define pci_ss_list_12c5 NULL +#define pci_ss_list_12c6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12c7[] = { + &pci_ss_info_12c7_4001, + &pci_ss_info_12c7_5005, + &pci_ss_info_12c7_5006, + NULL +}; +#endif +#define pci_ss_list_12c8 NULL +#define pci_ss_list_12c9 NULL +#define pci_ss_list_12ca NULL +#define pci_ss_list_12cb NULL +#define pci_ss_list_12cc NULL +#define pci_ss_list_12cd NULL +#define pci_ss_list_12ce NULL +#define pci_ss_list_12cf NULL +#define pci_ss_list_12d0 NULL +#define pci_ss_list_12d1 NULL +#define pci_ss_list_12d2 NULL +#define pci_ss_list_12d3 NULL +#define pci_ss_list_12d4 NULL +#define pci_ss_list_12d5 NULL +#define pci_ss_list_12d6 NULL +#define pci_ss_list_12d7 NULL +#define pci_ss_list_12d8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12d9[] = { + &pci_ss_info_12d9_0002, + &pci_ss_info_12d9_000a, + &pci_ss_info_12d9_000c, + &pci_ss_info_12d9_000d, + NULL +}; +#endif +#define pci_ss_list_12da NULL +#define pci_ss_list_12db NULL +#define pci_ss_list_12dc NULL +#define pci_ss_list_12dd NULL +#define pci_ss_list_12de NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12df[] = { + &pci_ss_info_12df_4422, + NULL +}; +#endif +#define pci_ss_list_12e0 NULL +#define pci_ss_list_12e1 NULL +#define pci_ss_list_12e2 NULL +#define pci_ss_list_12e3 NULL +#define pci_ss_list_12e4 NULL +#define pci_ss_list_12e5 NULL +#define pci_ss_list_12e6 NULL +#define pci_ss_list_12e7 NULL +#define pci_ss_list_12e8 NULL +#define pci_ss_list_12e9 NULL +#define pci_ss_list_12ea NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12eb[] = { + &pci_ss_info_12eb_0001, + &pci_ss_info_12eb_0002, + &pci_ss_info_12eb_0003, + &pci_ss_info_12eb_0088, + &pci_ss_info_12eb_8803, + NULL +}; +#endif +#define pci_ss_list_12ec NULL +#define pci_ss_list_12ed NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12ee[] = { + &pci_ss_info_12ee_7000, + &pci_ss_info_12ee_7001, + &pci_ss_info_12ee_8011, + NULL +}; +#endif +#define pci_ss_list_12ef NULL +#define pci_ss_list_12f0 NULL +#define pci_ss_list_12f1 NULL +#define pci_ss_list_12f2 NULL +#define pci_ss_list_12f3 NULL +#define pci_ss_list_12f4 NULL +#define pci_ss_list_12f5 NULL +#define pci_ss_list_12f6 NULL +#define pci_ss_list_12f7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_12f8[] = { + &pci_ss_info_12f8_8a02, + NULL +}; +#endif +#define pci_ss_list_12f9 NULL +#define pci_ss_list_12fb NULL +#define pci_ss_list_12fc NULL +#define pci_ss_list_12fd NULL +#define pci_ss_list_12fe NULL +#define pci_ss_list_12ff NULL +#define pci_ss_list_1300 NULL +#define pci_ss_list_1302 NULL +#define pci_ss_list_1303 NULL +#define pci_ss_list_1304 NULL +#define pci_ss_list_1305 NULL +#define pci_ss_list_1306 NULL +#define pci_ss_list_1307 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1308[] = { + &pci_ss_info_1308_0001, + NULL +}; +#endif +#define pci_ss_list_1309 NULL +#define pci_ss_list_130a NULL +#define pci_ss_list_130b NULL +#define pci_ss_list_130c NULL +#define pci_ss_list_130d NULL +#define pci_ss_list_130e NULL +#define pci_ss_list_130f NULL +#define pci_ss_list_1310 NULL +#define pci_ss_list_1311 NULL +#define pci_ss_list_1312 NULL +#define pci_ss_list_1313 NULL +#define pci_ss_list_1316 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1317[] = { + &pci_ss_info_1317_8201, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1318[] = { + &pci_ss_info_1318_0000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1319[] = { + &pci_ss_info_1319_1319, + NULL +}; +#endif +#define pci_ss_list_131a NULL +#define pci_ss_list_131c NULL +#define pci_ss_list_131d NULL +#define pci_ss_list_131e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_131f[] = { + &pci_ss_info_131f_2030, + &pci_ss_info_131f_2050, + &pci_ss_info_131f_2051, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1320[] = { + &pci_ss_info_1320_10bd, + NULL +}; +#endif +#define pci_ss_list_1321 NULL +#define pci_ss_list_1322 NULL +#define pci_ss_list_1323 NULL +#define pci_ss_list_1324 NULL +#define pci_ss_list_1325 NULL +#define pci_ss_list_1326 NULL +#define pci_ss_list_1327 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1328[] = { + &pci_ss_info_1328_0001, + &pci_ss_info_1328_f001, + NULL +}; +#endif +#define pci_ss_list_1329 NULL +#define pci_ss_list_132a NULL +#define pci_ss_list_132b NULL +#define pci_ss_list_132c NULL +#define pci_ss_list_132d NULL +#define pci_ss_list_1330 NULL +#define pci_ss_list_1331 NULL +#define pci_ss_list_1332 NULL +#define pci_ss_list_1334 NULL +#define pci_ss_list_1335 NULL +#define pci_ss_list_1337 NULL +#define pci_ss_list_1338 NULL +#define pci_ss_list_133a NULL +#define pci_ss_list_133b NULL +#define pci_ss_list_133c NULL +#define pci_ss_list_133d NULL +#define pci_ss_list_133e NULL +#define pci_ss_list_133f NULL +#define pci_ss_list_1340 NULL +#define pci_ss_list_1341 NULL +#define pci_ss_list_1342 NULL +#define pci_ss_list_1343 NULL +#define pci_ss_list_1344 NULL +#define pci_ss_list_1345 NULL +#define pci_ss_list_1347 NULL +#define pci_ss_list_1349 NULL +#define pci_ss_list_134a NULL +#define pci_ss_list_134b NULL +#define pci_ss_list_134c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_134d[] = { + &pci_ss_info_134d_0001, + &pci_ss_info_134d_4c21, + NULL +}; +#endif +#define pci_ss_list_134e NULL +#define pci_ss_list_134f NULL +#define pci_ss_list_1350 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1351[] = { + &pci_ss_info_1351_103c, + NULL +}; +#endif +#define pci_ss_list_1353 NULL +#define pci_ss_list_1354 NULL +#define pci_ss_list_1355 NULL +#define pci_ss_list_1356 NULL +#define pci_ss_list_1359 NULL +#define pci_ss_list_135a NULL +#define pci_ss_list_135b NULL +#define pci_ss_list_135c NULL +#define pci_ss_list_135d NULL +#define pci_ss_list_135e NULL +#define pci_ss_list_135f NULL +#define pci_ss_list_1360 NULL +#define pci_ss_list_1361 NULL +#define pci_ss_list_1362 NULL +#define pci_ss_list_1363 NULL +#define pci_ss_list_1364 NULL +#define pci_ss_list_1365 NULL +#define pci_ss_list_1366 NULL +#define pci_ss_list_1367 NULL +#define pci_ss_list_1368 NULL +#define pci_ss_list_1369 NULL +#define pci_ss_list_136a NULL +#define pci_ss_list_136b NULL +#define pci_ss_list_136c NULL +#define pci_ss_list_136d NULL +#define pci_ss_list_136f NULL +#define pci_ss_list_1370 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1371[] = { + &pci_ss_info_1371_001e, + &pci_ss_info_1371_001f, + &pci_ss_info_1371_0020, + &pci_ss_info_1371_434e, + NULL +}; +#endif +#define pci_ss_list_1373 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1374[] = { + &pci_ss_info_1374_0001, + &pci_ss_info_1374_0002, + &pci_ss_info_1374_0003, + &pci_ss_info_1374_0007, + &pci_ss_info_1374_0008, + NULL +}; +#endif +#define pci_ss_list_1375 NULL +#define pci_ss_list_1376 NULL +#define pci_ss_list_1377 NULL +#define pci_ss_list_1378 NULL +#define pci_ss_list_1379 NULL +#define pci_ss_list_137a NULL +#define pci_ss_list_137b NULL +#define pci_ss_list_137c NULL +#define pci_ss_list_137d NULL +#define pci_ss_list_137e NULL +#define pci_ss_list_137f NULL +#define pci_ss_list_1380 NULL +#define pci_ss_list_1381 NULL +#define pci_ss_list_1382 NULL +#define pci_ss_list_1383 NULL +#define pci_ss_list_1384 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1385[] = { + &pci_ss_info_1385_1100, + &pci_ss_info_1385_2100, + &pci_ss_info_1385_4105, + &pci_ss_info_1385_4800, + &pci_ss_info_1385_4d00, + &pci_ss_info_1385_4e00, + &pci_ss_info_1385_f004, + &pci_ss_info_1385_f311, + NULL +}; +#endif +#define pci_ss_list_1386 NULL +#define pci_ss_list_1387 NULL +#define pci_ss_list_1388 NULL +#define pci_ss_list_1389 NULL +#define pci_ss_list_138a NULL +#define pci_ss_list_138b NULL +#define pci_ss_list_138c NULL +#define pci_ss_list_138d NULL +#define pci_ss_list_138e NULL +#define pci_ss_list_138f NULL +#define pci_ss_list_1390 NULL +#define pci_ss_list_1391 NULL +#define pci_ss_list_1392 NULL +#define pci_ss_list_1393 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1394[] = { + &pci_ss_info_1394_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1395[] = { + &pci_ss_info_1395_0001, + NULL +}; +#endif +#define pci_ss_list_1396 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1397[] = { + &pci_ss_info_1397_2bd0, + &pci_ss_info_1397_3136, + &pci_ss_info_1397_3137, + &pci_ss_info_1397_b520, + &pci_ss_info_1397_b540, + NULL +}; +#endif +#define pci_ss_list_1398 NULL +#define pci_ss_list_1399 NULL +#define pci_ss_list_139a NULL +#define pci_ss_list_139b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_139c[] = { + &pci_ss_info_139c_0016, + &pci_ss_info_139c_0017, + NULL +}; +#endif +#define pci_ss_list_139d NULL +#define pci_ss_list_139e NULL +#define pci_ss_list_139f NULL +#define pci_ss_list_13a0 NULL +#define pci_ss_list_13a1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13a2[] = { + &pci_ss_info_13a2_8002, + &pci_ss_info_13a2_8006, + NULL +}; +#endif +#define pci_ss_list_13a3 NULL +#define pci_ss_list_13a4 NULL +#define pci_ss_list_13a5 NULL +#define pci_ss_list_13a6 NULL +#define pci_ss_list_13a7 NULL +#define pci_ss_list_13a8 NULL +#define pci_ss_list_13a9 NULL +#define pci_ss_list_13aa NULL +#define pci_ss_list_13ab NULL +#define pci_ss_list_13ac NULL +#define pci_ss_list_13ad NULL +#define pci_ss_list_13ae NULL +#define pci_ss_list_13af NULL +#define pci_ss_list_13b0 NULL +#define pci_ss_list_13b1 NULL +#define pci_ss_list_13b2 NULL +#define pci_ss_list_13b3 NULL +#define pci_ss_list_13b4 NULL +#define pci_ss_list_13b5 NULL +#define pci_ss_list_13b6 NULL +#define pci_ss_list_13b7 NULL +#define pci_ss_list_13b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13b9[] = { + &pci_ss_info_13b9_1421, + NULL +}; +#endif +#define pci_ss_list_13ba NULL +#define pci_ss_list_13bb NULL +#define pci_ss_list_13bc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13bd[] = { + &pci_ss_info_13bd_100c, + &pci_ss_info_13bd_100d, + &pci_ss_info_13bd_100e, + &pci_ss_info_13bd_1019, + &pci_ss_info_13bd_f6f1, + NULL +}; +#endif +#define pci_ss_list_13be NULL +#define pci_ss_list_13bf NULL +#define pci_ss_list_13c0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13c1[] = { + &pci_ss_info_13c1_1001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13c2[] = { + &pci_ss_info_13c2_0000, + &pci_ss_info_13c2_0001, + &pci_ss_info_13c2_0002, + &pci_ss_info_13c2_0003, + &pci_ss_info_13c2_0004, + &pci_ss_info_13c2_0006, + &pci_ss_info_13c2_0008, + &pci_ss_info_13c2_000a, + &pci_ss_info_13c2_1003, + &pci_ss_info_13c2_1004, + &pci_ss_info_13c2_1005, + &pci_ss_info_13c2_100c, + &pci_ss_info_13c2_100f, + &pci_ss_info_13c2_1011, + &pci_ss_info_13c2_1013, + &pci_ss_info_13c2_1016, + &pci_ss_info_13c2_1102, + NULL +}; +#endif +#define pci_ss_list_13c3 NULL +#define pci_ss_list_13c4 NULL +#define pci_ss_list_13c5 NULL +#define pci_ss_list_13c6 NULL +#define pci_ss_list_13c7 NULL +#define pci_ss_list_13c8 NULL +#define pci_ss_list_13c9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13ca[] = { + &pci_ss_info_13ca_4231, + NULL +}; +#endif +#define pci_ss_list_13cb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13cc[] = { + &pci_ss_info_13cc_0000, + &pci_ss_info_13cc_0002, + &pci_ss_info_13cc_0003, + &pci_ss_info_13cc_0004, + &pci_ss_info_13cc_0005, + &pci_ss_info_13cc_0006, + &pci_ss_info_13cc_0007, + &pci_ss_info_13cc_0008, + &pci_ss_info_13cc_0009, + &pci_ss_info_13cc_000a, + &pci_ss_info_13cc_000c, + NULL +}; +#endif +#define pci_ss_list_13cd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13ce[] = { + &pci_ss_info_13ce_8031, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13cf[] = { + &pci_ss_info_13cf_8031, + NULL +}; +#endif +#define pci_ss_list_13d0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13d1[] = { + &pci_ss_info_13d1_ab01, + &pci_ss_info_13d1_aba0, + &pci_ss_info_13d1_ac11, + &pci_ss_info_13d1_ac12, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13d2[] = { + &pci_ss_info_13d2_0300, + &pci_ss_info_13d2_0301, + &pci_ss_info_13d2_0302, + NULL +}; +#endif +#define pci_ss_list_13d3 NULL +#define pci_ss_list_13d4 NULL +#define pci_ss_list_13d5 NULL +#define pci_ss_list_13d6 NULL +#define pci_ss_list_13d7 NULL +#define pci_ss_list_13d8 NULL +#define pci_ss_list_13d9 NULL +#define pci_ss_list_13da NULL +#define pci_ss_list_13db NULL +#define pci_ss_list_13dc NULL +#define pci_ss_list_13dd NULL +#define pci_ss_list_13de NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13df[] = { + &pci_ss_info_13df_0001, + &pci_ss_info_13df_1003, + &pci_ss_info_13df_1005, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13e0[] = { + &pci_ss_info_13e0_0012, + &pci_ss_info_13e0_0020, + &pci_ss_info_13e0_0030, + &pci_ss_info_13e0_0040, + &pci_ss_info_13e0_0041, + &pci_ss_info_13e0_0042, + &pci_ss_info_13e0_0100, + &pci_ss_info_13e0_0117, + &pci_ss_info_13e0_0147, + &pci_ss_info_13e0_0187, + &pci_ss_info_13e0_0197, + &pci_ss_info_13e0_01a7, + &pci_ss_info_13e0_01b7, + &pci_ss_info_13e0_01c7, + &pci_ss_info_13e0_01d7, + &pci_ss_info_13e0_01f7, + &pci_ss_info_13e0_0209, + &pci_ss_info_13e0_020a, + &pci_ss_info_13e0_020d, + &pci_ss_info_13e0_020e, + &pci_ss_info_13e0_0210, + &pci_ss_info_13e0_0240, + &pci_ss_info_13e0_0247, + &pci_ss_info_13e0_0250, + &pci_ss_info_13e0_0260, + &pci_ss_info_13e0_0261, + &pci_ss_info_13e0_0270, + &pci_ss_info_13e0_0290, + &pci_ss_info_13e0_0297, + &pci_ss_info_13e0_02a0, + &pci_ss_info_13e0_02b0, + &pci_ss_info_13e0_02c0, + &pci_ss_info_13e0_02c7, + &pci_ss_info_13e0_02d0, + &pci_ss_info_13e0_0410, + &pci_ss_info_13e0_0412, + &pci_ss_info_13e0_0420, + &pci_ss_info_13e0_0440, + &pci_ss_info_13e0_0441, + &pci_ss_info_13e0_0442, + &pci_ss_info_13e0_0443, + &pci_ss_info_13e0_0450, + &pci_ss_info_13e0_8d84, + &pci_ss_info_13e0_8d85, + &pci_ss_info_13e0_f100, + &pci_ss_info_13e0_f101, + &pci_ss_info_13e0_f102, + NULL +}; +#endif +#define pci_ss_list_13e1 NULL +#define pci_ss_list_13e2 NULL +#define pci_ss_list_13e3 NULL +#define pci_ss_list_13e4 NULL +#define pci_ss_list_13e5 NULL +#define pci_ss_list_13e6 NULL +#define pci_ss_list_13e7 NULL +#define pci_ss_list_13e8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13e9[] = { + &pci_ss_info_13e9_0070, + &pci_ss_info_13e9_1000, + NULL +}; +#endif +#define pci_ss_list_13ea NULL +#define pci_ss_list_13eb NULL +#define pci_ss_list_13ec NULL +#define pci_ss_list_13ed NULL +#define pci_ss_list_13ee NULL +#define pci_ss_list_13ef NULL +#define pci_ss_list_13f0 NULL +#define pci_ss_list_13f1 NULL +#define pci_ss_list_13f2 NULL +#define pci_ss_list_13f3 NULL +#define pci_ss_list_13f4 NULL +#define pci_ss_list_13f5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13f6[] = { + &pci_ss_info_13f6_0101, + &pci_ss_info_13f6_0111, + &pci_ss_info_13f6_ffff, + NULL +}; +#endif +#define pci_ss_list_13f7 NULL +#define pci_ss_list_13f8 NULL +#define pci_ss_list_13f9 NULL +#define pci_ss_list_13fa NULL +#define pci_ss_list_13fb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_13fc[] = { + &pci_ss_info_13fc_2471, + NULL +}; +#endif +#define pci_ss_list_13fd NULL +#define pci_ss_list_13fe NULL +#define pci_ss_list_13ff NULL +#define pci_ss_list_1400 NULL +#define pci_ss_list_1401 NULL +#define pci_ss_list_1402 NULL +#define pci_ss_list_1403 NULL +#define pci_ss_list_1404 NULL +#define pci_ss_list_1405 NULL +#define pci_ss_list_1406 NULL +#define pci_ss_list_1407 NULL +#define pci_ss_list_1408 NULL +#define pci_ss_list_1409 NULL +#define pci_ss_list_140a NULL +#define pci_ss_list_140b NULL +#define pci_ss_list_140c NULL +#define pci_ss_list_140d NULL +#define pci_ss_list_140e NULL +#define pci_ss_list_140f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1410[] = { + &pci_ss_info_1410_0104, + NULL +}; +#endif +#define pci_ss_list_1411 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1412[] = { + &pci_ss_info_1412_1712, + &pci_ss_info_1412_1724, + &pci_ss_info_1412_3630, + &pci_ss_info_1412_3631, + &pci_ss_info_1412_d630, + &pci_ss_info_1412_d631, + &pci_ss_info_1412_d632, + &pci_ss_info_1412_d633, + &pci_ss_info_1412_d634, + &pci_ss_info_1412_d635, + &pci_ss_info_1412_d637, + &pci_ss_info_1412_d638, + &pci_ss_info_1412_d63b, + &pci_ss_info_1412_d63c, + NULL +}; +#endif +#define pci_ss_list_1413 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1414[] = { + &pci_ss_info_1414_0003, + &pci_ss_info_1414_0004, + NULL +}; +#endif +#define pci_ss_list_1415 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1416[] = { + &pci_ss_info_1416_1712, + &pci_ss_info_1416_9804, + NULL +}; +#endif +#define pci_ss_list_1417 NULL +#define pci_ss_list_1418 NULL +#define pci_ss_list_1419 NULL +#define pci_ss_list_141a NULL +#define pci_ss_list_141b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_141d[] = { + &pci_ss_info_141d_0440, + NULL +}; +#endif +#define pci_ss_list_141e NULL +#define pci_ss_list_141f NULL +#define pci_ss_list_1420 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1421[] = { + &pci_ss_info_1421_0334, + &pci_ss_info_1421_0335, + &pci_ss_info_1421_1370, + NULL +}; +#endif +#define pci_ss_list_1422 NULL +#define pci_ss_list_1423 NULL +#define pci_ss_list_1424 NULL +#define pci_ss_list_1425 NULL +#define pci_ss_list_1426 NULL +#define pci_ss_list_1427 NULL +#define pci_ss_list_1428 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1429[] = { + &pci_ss_info_1429_d010, + NULL +}; +#endif +#define pci_ss_list_142a NULL +#define pci_ss_list_142b NULL +#define pci_ss_list_142c NULL +#define pci_ss_list_142d NULL +#define pci_ss_list_142e NULL +#define pci_ss_list_142f NULL +#define pci_ss_list_1430 NULL +#define pci_ss_list_1431 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1432[] = { + &pci_ss_info_1432_9130, + NULL +}; +#endif +#define pci_ss_list_1433 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1435[] = { + &pci_ss_info_1435_7330, + &pci_ss_info_1435_7350, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1436[] = { + &pci_ss_info_1436_0300, + &pci_ss_info_1436_0301, + &pci_ss_info_1436_0302, + &pci_ss_info_1436_0440, + &pci_ss_info_1436_1003, + &pci_ss_info_1436_1005, + &pci_ss_info_1436_1103, + &pci_ss_info_1436_1105, + &pci_ss_info_1436_1203, + &pci_ss_info_1436_1303, + &pci_ss_info_1436_1602, + &pci_ss_info_1436_8139, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1437[] = { + &pci_ss_info_1437_1105, + NULL +}; +#endif +#define pci_ss_list_1438 NULL +#define pci_ss_list_1439 NULL +#define pci_ss_list_143a NULL +#define pci_ss_list_143b NULL +#define pci_ss_list_143c NULL +#define pci_ss_list_143d NULL +#define pci_ss_list_143e NULL +#define pci_ss_list_143f NULL +#define pci_ss_list_1440 NULL +#define pci_ss_list_1441 NULL +#define pci_ss_list_1442 NULL +#define pci_ss_list_1443 NULL +#define pci_ss_list_1444 NULL +#define pci_ss_list_1445 NULL +#define pci_ss_list_1446 NULL +#define pci_ss_list_1447 NULL +#define pci_ss_list_1448 NULL +#define pci_ss_list_1449 NULL +#define pci_ss_list_144a NULL +#define pci_ss_list_144b NULL +#define pci_ss_list_144c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_144d[] = { + &pci_ss_info_144d_2101, + &pci_ss_info_144d_2104, + &pci_ss_info_144d_2115, + &pci_ss_info_144d_2321, + &pci_ss_info_144d_2501, + &pci_ss_info_144d_2502, + &pci_ss_info_144d_2602, + &pci_ss_info_144d_3510, + &pci_ss_info_144d_c000, + &pci_ss_info_144d_c001, + &pci_ss_info_144d_c003, + &pci_ss_info_144d_c006, + &pci_ss_info_144d_c00c, + &pci_ss_info_144d_c018, + NULL +}; +#endif +#define pci_ss_list_144e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_144f[] = { + &pci_ss_info_144f_0441, + &pci_ss_info_144f_0449, + &pci_ss_info_144f_1005, + &pci_ss_info_144f_100c, + &pci_ss_info_144f_1104, + &pci_ss_info_144f_110d, + &pci_ss_info_144f_1500, + &pci_ss_info_144f_1501, + &pci_ss_info_144f_1502, + &pci_ss_info_144f_1503, + &pci_ss_info_144f_150a, + &pci_ss_info_144f_150b, + &pci_ss_info_144f_1510, + &pci_ss_info_144f_1702, + &pci_ss_info_144f_1703, + &pci_ss_info_144f_1707, + &pci_ss_info_144f_3000, + &pci_ss_info_144f_4005, + &pci_ss_info_144f_7050, + NULL +}; +#endif +#define pci_ss_list_1450 NULL +#define pci_ss_list_1451 NULL +#define pci_ss_list_1453 NULL +#define pci_ss_list_1454 NULL +#define pci_ss_list_1455 NULL +#define pci_ss_list_1456 NULL +#define pci_ss_list_1457 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1458[] = { + &pci_ss_info_1458_0400, + &pci_ss_info_1458_0596, + &pci_ss_info_1458_0691, + &pci_ss_info_1458_0c11, + &pci_ss_info_1458_1000, + &pci_ss_info_1458_1019, + &pci_ss_info_1458_24c2, + &pci_ss_info_1458_24d1, + &pci_ss_info_1458_24d2, + &pci_ss_info_1458_2558, + &pci_ss_info_1458_2560, + &pci_ss_info_1458_2570, + &pci_ss_info_1458_2578, + &pci_ss_info_1458_2580, + &pci_ss_info_1458_2582, + &pci_ss_info_1458_2659, + &pci_ss_info_1458_265a, + &pci_ss_info_1458_266a, + &pci_ss_info_1458_266f, + &pci_ss_info_1458_3124, + &pci_ss_info_1458_4000, + &pci_ss_info_1458_4002, + &pci_ss_info_1458_4018, + &pci_ss_info_1458_4019, + &pci_ss_info_1458_4024, + &pci_ss_info_1458_4025, + &pci_ss_info_1458_4032, + &pci_ss_info_1458_5000, + &pci_ss_info_1458_5001, + &pci_ss_info_1458_5002, + &pci_ss_info_1458_5004, + &pci_ss_info_1458_5006, + &pci_ss_info_1458_7600, + &pci_ss_info_1458_a000, + &pci_ss_info_1458_a002, + &pci_ss_info_1458_b001, + &pci_ss_info_1458_b003, + &pci_ss_info_1458_d000, + &pci_ss_info_1458_e000, + &pci_ss_info_1458_e381, + &pci_ss_info_1458_e911, + &pci_ss_info_1458_e931, + NULL +}; +#endif +#define pci_ss_list_1459 NULL +#define pci_ss_list_145a NULL +#define pci_ss_list_145b NULL +#define pci_ss_list_145c NULL +#define pci_ss_list_145d NULL +#define pci_ss_list_145e NULL +#define pci_ss_list_145f NULL +#define pci_ss_list_1460 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1461[] = { + &pci_ss_info_1461_0002, + &pci_ss_info_1461_0003, + &pci_ss_info_1461_0004, + &pci_ss_info_1461_000a, + &pci_ss_info_1461_000b, + &pci_ss_info_1461_050c, + &pci_ss_info_1461_0761, + &pci_ss_info_1461_0771, + &pci_ss_info_1461_1044, + &pci_ss_info_1461_10ff, + &pci_ss_info_1461_2108, + &pci_ss_info_1461_2115, + &pci_ss_info_1461_2c00, + &pci_ss_info_1461_8011, + &pci_ss_info_1461_9715, + &pci_ss_info_1461_a3ce, + &pci_ss_info_1461_a3cf, + &pci_ss_info_1461_a70a, + &pci_ss_info_1461_a70b, + &pci_ss_info_1461_c019, + &pci_ss_info_1461_d6ee, + &pci_ss_info_1461_f31f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1462[] = { + &pci_ss_info_1462_0080, + &pci_ss_info_1462_0311, + &pci_ss_info_1462_0345, + &pci_ss_info_1462_0400, + &pci_ss_info_1462_0402, + &pci_ss_info_1462_0403, + &pci_ss_info_1462_052c, + &pci_ss_info_1462_058c, + &pci_ss_info_1462_0622, + &pci_ss_info_1462_1009, + &pci_ss_info_1462_207d, + &pci_ss_info_1462_3091, + &pci_ss_info_1462_309e, + &pci_ss_info_1462_3300, + &pci_ss_info_1462_3370, + &pci_ss_info_1462_3800, + &pci_ss_info_1462_3981, + &pci_ss_info_1462_400a, + &pci_ss_info_1462_5470, + &pci_ss_info_1462_5506, + &pci_ss_info_1462_5800, + &pci_ss_info_1462_6231, + &pci_ss_info_1462_6470, + &pci_ss_info_1462_6560, + &pci_ss_info_1462_6630, + &pci_ss_info_1462_6631, + &pci_ss_info_1462_6632, + &pci_ss_info_1462_6633, + &pci_ss_info_1462_6780, + &pci_ss_info_1462_6820, + &pci_ss_info_1462_6822, + &pci_ss_info_1462_6828, + &pci_ss_info_1462_6830, + &pci_ss_info_1462_6835, + &pci_ss_info_1462_6880, + &pci_ss_info_1462_6900, + &pci_ss_info_1462_6910, + &pci_ss_info_1462_6930, + &pci_ss_info_1462_6990, + &pci_ss_info_1462_6991, + &pci_ss_info_1462_7020, + &pci_ss_info_1462_7028, + &pci_ss_info_1462_702c, + &pci_ss_info_1462_702d, + &pci_ss_info_1462_702e, + &pci_ss_info_1462_7030, + &pci_ss_info_1462_7100, + &pci_ss_info_1462_7207, + &pci_ss_info_1462_7280, + &pci_ss_info_1462_728c, + &pci_ss_info_1462_7580, + &pci_ss_info_1462_758c, + &pci_ss_info_1462_788c, + &pci_ss_info_1462_8606, + &pci_ss_info_1462_8661, + &pci_ss_info_1462_8730, + &pci_ss_info_1462_8808, + &pci_ss_info_1462_8817, + &pci_ss_info_1462_8831, + &pci_ss_info_1462_8852, + &pci_ss_info_1462_8880, + &pci_ss_info_1462_8900, + &pci_ss_info_1462_9171, + &pci_ss_info_1462_932c, + &pci_ss_info_1462_9350, + &pci_ss_info_1462_9360, + &pci_ss_info_1462_971d, + NULL +}; +#endif +#define pci_ss_list_1463 NULL +#define pci_ss_list_1464 NULL +#define pci_ss_list_1465 NULL +#define pci_ss_list_1466 NULL +#define pci_ss_list_1467 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1468[] = { + &pci_ss_info_1468_0202, + &pci_ss_info_1468_0311, + &pci_ss_info_1468_0312, + &pci_ss_info_1468_0410, + &pci_ss_info_1468_0440, + &pci_ss_info_1468_0441, + &pci_ss_info_1468_0449, + &pci_ss_info_1468_0450, + &pci_ss_info_1468_2015, + NULL +}; +#endif +#define pci_ss_list_1469 NULL +#define pci_ss_list_146a NULL +#define pci_ss_list_146b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_146c[] = { + &pci_ss_info_146c_1439, + NULL +}; +#endif +#define pci_ss_list_146d NULL +#define pci_ss_list_146e NULL +#define pci_ss_list_146f NULL +#define pci_ss_list_1470 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1471[] = { + &pci_ss_info_1471_b7e9, + NULL +}; +#endif +#define pci_ss_list_1472 NULL +#define pci_ss_list_1473 NULL +#define pci_ss_list_1474 NULL +#define pci_ss_list_1475 NULL +#define pci_ss_list_1476 NULL +#define pci_ss_list_1477 NULL +#define pci_ss_list_1478 NULL +#define pci_ss_list_1479 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_147a[] = { + &pci_ss_info_147a_c001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_147b[] = { + &pci_ss_info_147b_0507, + &pci_ss_info_147b_1406, + &pci_ss_info_147b_1407, + &pci_ss_info_147b_1408, + &pci_ss_info_147b_1c09, + &pci_ss_info_147b_1c0b, + &pci_ss_info_147b_1c1a, + &pci_ss_info_147b_6191, + &pci_ss_info_147b_8f00, + &pci_ss_info_147b_8f09, + &pci_ss_info_147b_8f0d, + &pci_ss_info_147b_a401, + &pci_ss_info_147b_a702, + NULL +}; +#endif +#define pci_ss_list_147c NULL +#define pci_ss_list_147d NULL +#define pci_ss_list_147e NULL +#define pci_ss_list_147f NULL +#define pci_ss_list_1480 NULL +#define pci_ss_list_1481 NULL +#define pci_ss_list_1482 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1483[] = { + &pci_ss_info_1483_5020, + &pci_ss_info_1483_5021, + &pci_ss_info_1483_5022, + NULL +}; +#endif +#define pci_ss_list_1484 NULL +#define pci_ss_list_1485 NULL +#define pci_ss_list_1486 NULL +#define pci_ss_list_1487 NULL +#define pci_ss_list_1488 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1489[] = { + &pci_ss_info_1489_0214, + &pci_ss_info_1489_6001, + &pci_ss_info_1489_6002, + NULL +}; +#endif +#define pci_ss_list_148a NULL +#define pci_ss_list_148b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_148c[] = { + &pci_ss_info_148c_2003, + &pci_ss_info_148c_2023, + &pci_ss_info_148c_2024, + &pci_ss_info_148c_2025, + &pci_ss_info_148c_2026, + &pci_ss_info_148c_2036, + &pci_ss_info_148c_2039, + &pci_ss_info_148c_2064, + &pci_ss_info_148c_2066, + &pci_ss_info_148c_2067, + &pci_ss_info_148c_2073, + &pci_ss_info_148c_2116, + &pci_ss_info_148c_2117, + NULL +}; +#endif +#define pci_ss_list_148d NULL +#define pci_ss_list_148e NULL +#define pci_ss_list_148f NULL +#define pci_ss_list_1490 NULL +#define pci_ss_list_1491 NULL +#define pci_ss_list_1492 NULL +#define pci_ss_list_1493 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1494[] = { + &pci_ss_info_1494_0300, + &pci_ss_info_1494_0301, + NULL +}; +#endif +#define pci_ss_list_1495 NULL +#define pci_ss_list_1496 NULL +#define pci_ss_list_1497 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1498[] = { + &pci_ss_info_1498_000a, + &pci_ss_info_1498_000b, + &pci_ss_info_1498_000c, + &pci_ss_info_1498_0362, + NULL +}; +#endif +#define pci_ss_list_1499 NULL +#define pci_ss_list_149a NULL +#define pci_ss_list_149b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_149c[] = { + &pci_ss_info_149c_139a, + &pci_ss_info_149c_8139, + NULL +}; +#endif +#define pci_ss_list_149d NULL +#define pci_ss_list_149e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_149f[] = { + &pci_ss_info_149f_0440, + NULL +}; +#endif +#define pci_ss_list_14a0 NULL +#define pci_ss_list_14a1 NULL +#define pci_ss_list_14a2 NULL +#define pci_ss_list_14a3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14a4[] = { + &pci_ss_info_14a4_2073, + &pci_ss_info_14a4_2077, + &pci_ss_info_14a4_2089, + &pci_ss_info_14a4_2091, + &pci_ss_info_14a4_2104, + &pci_ss_info_14a4_2105, + &pci_ss_info_14a4_2106, + &pci_ss_info_14a4_2107, + &pci_ss_info_14a4_2172, + NULL +}; +#endif +#define pci_ss_list_14a5 NULL +#define pci_ss_list_14a6 NULL +#define pci_ss_list_14a7 NULL +#define pci_ss_list_14a8 NULL +#define pci_ss_list_14a9 NULL +#define pci_ss_list_14aa NULL +#define pci_ss_list_14ab NULL +#define pci_ss_list_14ac NULL +#define pci_ss_list_14ad NULL +#define pci_ss_list_14ae NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14af[] = { + &pci_ss_info_14af_0002, + &pci_ss_info_14af_5008, + &pci_ss_info_14af_5021, + &pci_ss_info_14af_5022, + &pci_ss_info_14af_5810, + &pci_ss_info_14af_5820, + &pci_ss_info_14af_7102, + &pci_ss_info_14af_7103, + NULL +}; +#endif +#define pci_ss_list_14b0 NULL +#define pci_ss_list_14b1 NULL +#define pci_ss_list_14b2 NULL +#define pci_ss_list_14b3 NULL +#define pci_ss_list_14b4 NULL +#define pci_ss_list_14b5 NULL +#define pci_ss_list_14b6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14b7[] = { + &pci_ss_info_14b7_0a60, + NULL +}; +#endif +#define pci_ss_list_14b8 NULL +#define pci_ss_list_14b9 NULL +#define pci_ss_list_14ba NULL +#define pci_ss_list_14bb NULL +#define pci_ss_list_14bc NULL +#define pci_ss_list_14bd NULL +#define pci_ss_list_14be NULL +#define pci_ss_list_14bf NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14c0[] = { + &pci_ss_info_14c0_0004, + &pci_ss_info_14c0_000c, + &pci_ss_info_14c0_0012, + &pci_ss_info_14c0_1212, + NULL +}; +#endif +#define pci_ss_list_14c1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14c2[] = { + &pci_ss_info_14c2_0105, + &pci_ss_info_14c2_0205, + NULL +}; +#endif +#define pci_ss_list_14c3 NULL +#define pci_ss_list_14c4 NULL +#define pci_ss_list_14c5 NULL +#define pci_ss_list_14c6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14c7[] = { + &pci_ss_info_14c7_0107, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14c8[] = { + &pci_ss_info_14c8_0300, + &pci_ss_info_14c8_0302, + NULL +}; +#endif +#define pci_ss_list_14c9 NULL +#define pci_ss_list_14ca NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14cb[] = { + &pci_ss_info_14cb_0100, + &pci_ss_info_14cb_0200, + NULL +}; +#endif +#define pci_ss_list_14cc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14cd[] = { + &pci_ss_info_14cd_2012, + &pci_ss_info_14cd_2194, + NULL +}; +#endif +#define pci_ss_list_14ce NULL +#define pci_ss_list_14cf NULL +#define pci_ss_list_14d0 NULL +#define pci_ss_list_14d1 NULL +#define pci_ss_list_14d2 NULL +#define pci_ss_list_14d3 NULL +#define pci_ss_list_14d4 NULL +#define pci_ss_list_14d5 NULL +#define pci_ss_list_14d6 NULL +#define pci_ss_list_14d7 NULL +#define pci_ss_list_14d8 NULL +#define pci_ss_list_14d9 NULL +#define pci_ss_list_14da NULL +#define pci_ss_list_14db NULL +#define pci_ss_list_14dc NULL +#define pci_ss_list_14dd NULL +#define pci_ss_list_14de NULL +#define pci_ss_list_14df NULL +#define pci_ss_list_14e1 NULL +#define pci_ss_list_14e2 NULL +#define pci_ss_list_14e3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14e4[] = { + &pci_ss_info_14e4_0001, + &pci_ss_info_14e4_0002, + &pci_ss_info_14e4_0003, + &pci_ss_info_14e4_0004, + &pci_ss_info_14e4_0005, + &pci_ss_info_14e4_0006, + &pci_ss_info_14e4_0007, + &pci_ss_info_14e4_0008, + &pci_ss_info_14e4_0009, + &pci_ss_info_14e4_000a, + &pci_ss_info_14e4_000b, + &pci_ss_info_14e4_000c, + &pci_ss_info_14e4_000d, + &pci_ss_info_14e4_0449, + &pci_ss_info_14e4_1028, + &pci_ss_info_14e4_1644, + &pci_ss_info_14e4_4318, + &pci_ss_info_14e4_4320, + &pci_ss_info_14e4_8008, + &pci_ss_info_14e4_8009, + &pci_ss_info_14e4_800a, + NULL +}; +#endif +#define pci_ss_list_14e5 NULL +#define pci_ss_list_14e6 NULL +#define pci_ss_list_14e7 NULL +#define pci_ss_list_14e8 NULL +#define pci_ss_list_14e9 NULL +#define pci_ss_list_14ea NULL +#define pci_ss_list_14eb NULL +#define pci_ss_list_14ec NULL +#define pci_ss_list_14ed NULL +#define pci_ss_list_14ee NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14ef[] = { + &pci_ss_info_14ef_0220, + NULL +}; +#endif +#define pci_ss_list_14f0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14f1[] = { + &pci_ss_info_14f1_0001, + &pci_ss_info_14f1_0002, + &pci_ss_info_14f1_0003, + &pci_ss_info_14f1_0044, + &pci_ss_info_14f1_0048, + &pci_ss_info_14f1_0122, + &pci_ss_info_14f1_0144, + &pci_ss_info_14f1_0187, + &pci_ss_info_14f1_0222, + &pci_ss_info_14f1_0244, + &pci_ss_info_14f1_0322, + &pci_ss_info_14f1_0342, + &pci_ss_info_14f1_0422, + &pci_ss_info_14f1_1122, + &pci_ss_info_14f1_1222, + &pci_ss_info_14f1_1322, + &pci_ss_info_14f1_1522, + &pci_ss_info_14f1_1622, + &pci_ss_info_14f1_1722, + &pci_ss_info_14f1_2004, + &pci_ss_info_14f1_2045, + &pci_ss_info_14f1_5421, + NULL +}; +#endif +#define pci_ss_list_14f2 NULL +#define pci_ss_list_14f3 NULL +#define pci_ss_list_14f4 NULL +#define pci_ss_list_14f5 NULL +#define pci_ss_list_14f6 NULL +#define pci_ss_list_14f7 NULL +#define pci_ss_list_14f8 NULL +#define pci_ss_list_14f9 NULL +#define pci_ss_list_14fa NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14fb[] = { + &pci_ss_info_14fb_0101, + &pci_ss_info_14fb_0102, + &pci_ss_info_14fb_0202, + &pci_ss_info_14fb_0611, + &pci_ss_info_14fb_0612, + &pci_ss_info_14fb_0613, + &pci_ss_info_14fb_0614, + &pci_ss_info_14fb_0621, + &pci_ss_info_14fb_0622, + &pci_ss_info_14fb_0810, + NULL +}; +#endif +#define pci_ss_list_14fc NULL +#define pci_ss_list_14fd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14fe[] = { + &pci_ss_info_14fe_0428, + &pci_ss_info_14fe_0429, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_14ff[] = { + &pci_ss_info_14ff_0e70, + &pci_ss_info_14ff_1100, + &pci_ss_info_14ff_c401, + NULL +}; +#endif +#define pci_ss_list_1500 NULL +#define pci_ss_list_1501 NULL +#define pci_ss_list_1502 NULL +#define pci_ss_list_1503 NULL +#define pci_ss_list_1504 NULL +#define pci_ss_list_1505 NULL +#define pci_ss_list_1506 NULL +#define pci_ss_list_1507 NULL +#define pci_ss_list_1508 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1509[] = { + &pci_ss_info_1509_1930, + &pci_ss_info_1509_1968, + &pci_ss_info_1509_2990, + &pci_ss_info_1509_7002, + &pci_ss_info_1509_9902, + &pci_ss_info_1509_9903, + &pci_ss_info_1509_9904, + &pci_ss_info_1509_9905, + &pci_ss_info_1509_9a00, + NULL +}; +#endif +#define pci_ss_list_150a NULL +#define pci_ss_list_150b NULL +#define pci_ss_list_150c NULL +#define pci_ss_list_150d NULL +#define pci_ss_list_150e NULL +#define pci_ss_list_150f NULL +#define pci_ss_list_1510 NULL +#define pci_ss_list_1511 NULL +#define pci_ss_list_1512 NULL +#define pci_ss_list_1513 NULL +#define pci_ss_list_1514 NULL +#define pci_ss_list_1515 NULL +#define pci_ss_list_1516 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1517[] = { + &pci_ss_info_1517_000b, + &pci_ss_info_1517_000f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1518[] = { + &pci_ss_info_1518_0200, + NULL +}; +#endif +#define pci_ss_list_1519 NULL +#define pci_ss_list_151a NULL +#define pci_ss_list_151b NULL +#define pci_ss_list_151c NULL +#define pci_ss_list_151d NULL +#define pci_ss_list_151e NULL +#define pci_ss_list_151f NULL +#define pci_ss_list_1520 NULL +#define pci_ss_list_1521 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1522[] = { + &pci_ss_info_1522_0001, + &pci_ss_info_1522_0002, + &pci_ss_info_1522_0003, + &pci_ss_info_1522_0004, + &pci_ss_info_1522_0010, + &pci_ss_info_1522_0020, + &pci_ss_info_1522_0200, + &pci_ss_info_1522_0300, + &pci_ss_info_1522_0400, + &pci_ss_info_1522_0500, + &pci_ss_info_1522_0600, + &pci_ss_info_1522_0700, + &pci_ss_info_1522_0800, + &pci_ss_info_1522_0c00, + &pci_ss_info_1522_0d00, + &pci_ss_info_1522_1d00, + &pci_ss_info_1522_2000, + &pci_ss_info_1522_2100, + &pci_ss_info_1522_2200, + &pci_ss_info_1522_2300, + &pci_ss_info_1522_2400, + &pci_ss_info_1522_2500, + &pci_ss_info_1522_2600, + &pci_ss_info_1522_2700, + NULL +}; +#endif +#define pci_ss_list_1523 NULL +#define pci_ss_list_1524 NULL +#define pci_ss_list_1525 NULL +#define pci_ss_list_1526 NULL +#define pci_ss_list_1527 NULL +#define pci_ss_list_1528 NULL +#define pci_ss_list_1529 NULL +#define pci_ss_list_152a NULL +#define pci_ss_list_152b NULL +#define pci_ss_list_152c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_152d[] = { + &pci_ss_info_152d_0745, + &pci_ss_info_152d_0753, + &pci_ss_info_152d_8801, + &pci_ss_info_152d_8802, + &pci_ss_info_152d_8803, + &pci_ss_info_152d_8804, + &pci_ss_info_152d_8805, + &pci_ss_info_152d_8808, + NULL +}; +#endif +#define pci_ss_list_152e NULL +#define pci_ss_list_152f NULL +#define pci_ss_list_1530 NULL +#define pci_ss_list_1531 NULL +#define pci_ss_list_1532 NULL +#define pci_ss_list_1533 NULL +#define pci_ss_list_1534 NULL +#define pci_ss_list_1535 NULL +#define pci_ss_list_1537 NULL +#define pci_ss_list_1538 NULL +#define pci_ss_list_1539 NULL +#define pci_ss_list_153a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_153b[] = { + &pci_ss_info_153b_1115, + &pci_ss_info_153b_111b, + &pci_ss_info_153b_1125, + &pci_ss_info_153b_112b, + &pci_ss_info_153b_112c, + &pci_ss_info_153b_112e, + &pci_ss_info_153b_1130, + &pci_ss_info_153b_1136, + &pci_ss_info_153b_1138, + &pci_ss_info_153b_1142, + &pci_ss_info_153b_1143, + &pci_ss_info_153b_1145, + &pci_ss_info_153b_1147, + &pci_ss_info_153b_1151, + &pci_ss_info_153b_1152, + &pci_ss_info_153b_1153, + &pci_ss_info_153b_1156, + &pci_ss_info_153b_1158, + &pci_ss_info_153b_1160, + &pci_ss_info_153b_1162, + &pci_ss_info_153b_1166, + NULL +}; +#endif +#define pci_ss_list_153c NULL +#define pci_ss_list_153d NULL +#define pci_ss_list_153e NULL +#define pci_ss_list_153f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1540[] = { + &pci_ss_info_1540_2580, + &pci_ss_info_1540_9524, + NULL +}; +#endif +#define pci_ss_list_1541 NULL +#define pci_ss_list_1542 NULL +#define pci_ss_list_1543 NULL +#define pci_ss_list_1544 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1545[] = { + &pci_ss_info_1545_002f, + NULL +}; +#endif +#define pci_ss_list_1546 NULL +#define pci_ss_list_1547 NULL +#define pci_ss_list_1548 NULL +#define pci_ss_list_1549 NULL +#define pci_ss_list_154a NULL +#define pci_ss_list_154b NULL +#define pci_ss_list_154c NULL +#define pci_ss_list_154d NULL +#define pci_ss_list_154e NULL +#define pci_ss_list_154f NULL +#define pci_ss_list_1550 NULL +#define pci_ss_list_1551 NULL +#define pci_ss_list_1552 NULL +#define pci_ss_list_1553 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1554[] = { + &pci_ss_info_1554_1041, + &pci_ss_info_1554_4811, + &pci_ss_info_1554_4813, + NULL +}; +#endif +#define pci_ss_list_1555 NULL +#define pci_ss_list_1556 NULL +#define pci_ss_list_1557 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1558[] = { + &pci_ss_info_1558_04a0, + &pci_ss_info_1558_1103, + &pci_ss_info_1558_2200, + NULL +}; +#endif +#define pci_ss_list_1559 NULL +#define pci_ss_list_155a NULL +#define pci_ss_list_155b NULL +#define pci_ss_list_155c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_155d[] = { + &pci_ss_info_155d_2f07, + &pci_ss_info_155d_6793, + &pci_ss_info_155d_8850, + NULL +}; +#endif +#define pci_ss_list_155e NULL +#define pci_ss_list_155f NULL +#define pci_ss_list_1560 NULL +#define pci_ss_list_1561 NULL +#define pci_ss_list_1562 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1563[] = { + &pci_ss_info_1563_7018, + NULL +}; +#endif +#define pci_ss_list_1564 NULL +#define pci_ss_list_1565 NULL +#define pci_ss_list_1566 NULL +#define pci_ss_list_1567 NULL +#define pci_ss_list_1568 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1569[] = { + &pci_ss_info_1569_002d, + &pci_ss_info_1569_6326, + NULL +}; +#endif +#define pci_ss_list_156a NULL +#define pci_ss_list_156b NULL +#define pci_ss_list_156c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_156d[] = { + &pci_ss_info_156d_b400, + &pci_ss_info_156d_b550, + &pci_ss_info_156d_b560, + &pci_ss_info_156d_b700, + &pci_ss_info_156d_b795, + &pci_ss_info_156d_b797, + NULL +}; +#endif +#define pci_ss_list_156e NULL +#define pci_ss_list_156f NULL +#define pci_ss_list_1570 NULL +#define pci_ss_list_1571 NULL +#define pci_ss_list_1572 NULL +#define pci_ss_list_1573 NULL +#define pci_ss_list_1574 NULL +#define pci_ss_list_1575 NULL +#define pci_ss_list_1576 NULL +#define pci_ss_list_1578 NULL +#define pci_ss_list_1579 NULL +#define pci_ss_list_157a NULL +#define pci_ss_list_157b NULL +#define pci_ss_list_157c NULL +#define pci_ss_list_157d NULL +#define pci_ss_list_157e NULL +#define pci_ss_list_157f NULL +#define pci_ss_list_1580 NULL +#define pci_ss_list_1581 NULL +#define pci_ss_list_1582 NULL +#define pci_ss_list_1583 NULL +#define pci_ss_list_1584 NULL +#define pci_ss_list_1585 NULL +#define pci_ss_list_1586 NULL +#define pci_ss_list_1587 NULL +#define pci_ss_list_1588 NULL +#define pci_ss_list_1589 NULL +#define pci_ss_list_158a NULL +#define pci_ss_list_158b NULL +#define pci_ss_list_158c NULL +#define pci_ss_list_158d NULL +#define pci_ss_list_158e NULL +#define pci_ss_list_158f NULL +#define pci_ss_list_1590 NULL +#define pci_ss_list_1591 NULL +#define pci_ss_list_1592 NULL +#define pci_ss_list_1593 NULL +#define pci_ss_list_1594 NULL +#define pci_ss_list_1595 NULL +#define pci_ss_list_1596 NULL +#define pci_ss_list_1597 NULL +#define pci_ss_list_1598 NULL +#define pci_ss_list_1599 NULL +#define pci_ss_list_159a NULL +#define pci_ss_list_159b NULL +#define pci_ss_list_159c NULL +#define pci_ss_list_159d NULL +#define pci_ss_list_159e NULL +#define pci_ss_list_159f NULL +#define pci_ss_list_15a0 NULL +#define pci_ss_list_15a1 NULL +#define pci_ss_list_15a2 NULL +#define pci_ss_list_15a3 NULL +#define pci_ss_list_15a4 NULL +#define pci_ss_list_15a5 NULL +#define pci_ss_list_15a6 NULL +#define pci_ss_list_15a7 NULL +#define pci_ss_list_15a8 NULL +#define pci_ss_list_15aa NULL +#define pci_ss_list_15ab NULL +#define pci_ss_list_15ac NULL +static const pciSubsystemInfo *pci_ss_list_15ad[] = { + &pci_ss_info_15ad_1976, + NULL +}; +#define pci_ss_list_15ae NULL +#define pci_ss_list_15b0 NULL +#define pci_ss_list_15b1 NULL +#define pci_ss_list_15b2 NULL +#define pci_ss_list_15b3 NULL +#define pci_ss_list_15b4 NULL +#define pci_ss_list_15b5 NULL +#define pci_ss_list_15b6 NULL +#define pci_ss_list_15b7 NULL +#define pci_ss_list_15b8 NULL +#define pci_ss_list_15b9 NULL +#define pci_ss_list_15ba NULL +#define pci_ss_list_15bb NULL +#define pci_ss_list_15bc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15bd[] = { + &pci_ss_info_15bd_1001, + &pci_ss_info_15bd_1003, + NULL +}; +#endif +#define pci_ss_list_15be NULL +#define pci_ss_list_15bf NULL +#define pci_ss_list_15c0 NULL +#define pci_ss_list_15c1 NULL +#define pci_ss_list_15c2 NULL +#define pci_ss_list_15c3 NULL +#define pci_ss_list_15c4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15c5[] = { + &pci_ss_info_15c5_0111, + NULL +}; +#endif +#define pci_ss_list_15c6 NULL +#define pci_ss_list_15c7 NULL +#define pci_ss_list_15c8 NULL +#define pci_ss_list_15c9 NULL +#define pci_ss_list_15ca NULL +#define pci_ss_list_15cb NULL +#define pci_ss_list_15cc NULL +#define pci_ss_list_15cd NULL +#define pci_ss_list_15ce NULL +#define pci_ss_list_15cf NULL +#define pci_ss_list_15d1 NULL +#define pci_ss_list_15d2 NULL +#define pci_ss_list_15d3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15d4[] = { + &pci_ss_info_15d4_0047, + NULL +}; +#endif +#define pci_ss_list_15d5 NULL +#define pci_ss_list_15d6 NULL +#define pci_ss_list_15d7 NULL +#define pci_ss_list_15d8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15d9[] = { + &pci_ss_info_15d9_3480, + &pci_ss_info_15d9_4580, + &pci_ss_info_15d9_9005, + NULL +}; +#endif +#define pci_ss_list_15da NULL +#define pci_ss_list_15db NULL +#define pci_ss_list_15dc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15dd[] = { + &pci_ss_info_15dd_7609, + NULL +}; +#endif +#define pci_ss_list_15de NULL +#define pci_ss_list_15df NULL +#define pci_ss_list_15e0 NULL +#define pci_ss_list_15e1 NULL +#define pci_ss_list_15e2 NULL +#define pci_ss_list_15e3 NULL +#define pci_ss_list_15e4 NULL +#define pci_ss_list_15e5 NULL +#define pci_ss_list_15e6 NULL +#define pci_ss_list_15e7 NULL +#define pci_ss_list_15e8 NULL +#define pci_ss_list_15e9 NULL +#define pci_ss_list_15ea NULL +#define pci_ss_list_15eb NULL +#define pci_ss_list_15ec NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_15ed[] = { + &pci_ss_info_15ed_1000, + &pci_ss_info_15ed_1001, + &pci_ss_info_15ed_1002, + &pci_ss_info_15ed_1003, + &pci_ss_info_15ed_2000, + &pci_ss_info_15ed_2001, + NULL +}; +#endif +#define pci_ss_list_15ee NULL +#define pci_ss_list_15ef NULL +#define pci_ss_list_15f0 NULL +#define pci_ss_list_15f1 NULL +#define pci_ss_list_15f2 NULL +#define pci_ss_list_15f3 NULL +#define pci_ss_list_15f4 NULL +#define pci_ss_list_15f5 NULL +#define pci_ss_list_15f6 NULL +#define pci_ss_list_15f7 NULL +#define pci_ss_list_15f8 NULL +#define pci_ss_list_15f9 NULL +#define pci_ss_list_15fa NULL +#define pci_ss_list_15fb NULL +#define pci_ss_list_15fc NULL +#define pci_ss_list_15fd NULL +#define pci_ss_list_15fe NULL +#define pci_ss_list_15ff NULL +#define pci_ss_list_1600 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1601[] = { + &pci_ss_info_1601_0000, + &pci_ss_info_1601_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1602[] = { + &pci_ss_info_1602_0000, + &pci_ss_info_1602_0002, + NULL +}; +#endif +#define pci_ss_list_1603 NULL +#define pci_ss_list_1604 NULL +#define pci_ss_list_1605 NULL +#define pci_ss_list_1606 NULL +#define pci_ss_list_1607 NULL +#define pci_ss_list_1608 NULL +#define pci_ss_list_1609 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1612[] = { + &pci_ss_info_1612_0000, + &pci_ss_info_1612_0004, + NULL +}; +#endif +#define pci_ss_list_1619 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_161f[] = { + &pci_ss_info_161f_2029, + &pci_ss_info_161f_203c, + &pci_ss_info_161f_203d, + &pci_ss_info_161f_3017, + NULL +}; +#endif +#define pci_ss_list_1626 NULL +#define pci_ss_list_1629 NULL +#define pci_ss_list_1637 NULL +#define pci_ss_list_1638 NULL +#define pci_ss_list_163c NULL +#define pci_ss_list_1657 NULL +#define pci_ss_list_165a NULL +#define pci_ss_list_165d NULL +#define pci_ss_list_165f NULL +#define pci_ss_list_1661 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1668[] = { + &pci_ss_info_1668_0299, + &pci_ss_info_1668_0300, + &pci_ss_info_1668_0302, + &pci_ss_info_1668_0414, + &pci_ss_info_1668_0440, + &pci_ss_info_1668_1026, + &pci_ss_info_1668_1100, + &pci_ss_info_1668_2400, + NULL +}; +#endif +#define pci_ss_list_166d NULL +#define pci_ss_list_1677 NULL +#define pci_ss_list_167b NULL +#define pci_ss_list_167d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1681[] = { + &pci_ss_info_1681_0002, + &pci_ss_info_1681_0003, + &pci_ss_info_1681_0010, + &pci_ss_info_1681_0040, + &pci_ss_info_1681_0050, + &pci_ss_info_1681_a000, + &pci_ss_info_1681_a011, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1682[] = { + &pci_ss_info_1682_2109, + &pci_ss_info_1682_2119, + &pci_ss_info_1682_211c, + &pci_ss_info_1682_2120, + &pci_ss_info_1682_217e, + NULL +}; +#endif +#define pci_ss_list_1688 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_168c[] = { + &pci_ss_info_168c_0013, + &pci_ss_info_168c_001a, + &pci_ss_info_168c_1025, + &pci_ss_info_168c_1027, + &pci_ss_info_168c_1042, + &pci_ss_info_168c_1052, + &pci_ss_info_168c_2026, + &pci_ss_info_168c_2041, + &pci_ss_info_168c_2042, + &pci_ss_info_168c_2051, + &pci_ss_info_168c_2062, + &pci_ss_info_168c_2063, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1695[] = { + &pci_ss_info_1695_3005, + &pci_ss_info_1695_300c, + &pci_ss_info_1695_9001, + &pci_ss_info_1695_9025, + &pci_ss_info_1695_9029, + NULL +}; +#endif +#define pci_ss_list_169c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16a5[] = { + &pci_ss_info_16a5_1601, + &pci_ss_info_16a5_1605, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16ab[] = { + &pci_ss_info_16ab_7302, + &pci_ss_info_16ab_8501, + NULL +}; +#endif +#define pci_ss_list_16ae NULL +#define pci_ss_list_16af NULL +#define pci_ss_list_16b4 NULL +#define pci_ss_list_16b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16be[] = { + &pci_ss_info_16be_0001, + &pci_ss_info_16be_0002, + &pci_ss_info_16be_0003, + &pci_ss_info_16be_1040, + NULL +}; +#endif +#define pci_ss_list_16c6 NULL +#define pci_ss_list_16c8 NULL +#define pci_ss_list_16c9 NULL +#define pci_ss_list_16ca NULL +#define pci_ss_list_16cd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16ce[] = { + &pci_ss_info_16ce_1040, + NULL +}; +#endif +#define pci_ss_list_16d5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16df[] = { + &pci_ss_info_16df_0011, + &pci_ss_info_16df_0012, + &pci_ss_info_16df_0013, + &pci_ss_info_16df_0014, + &pci_ss_info_16df_0015, + &pci_ss_info_16df_0016, + NULL +}; +#endif +#define pci_ss_list_16e3 NULL +#define pci_ss_list_16e5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_16ec[] = { + &pci_ss_info_16ec_0119, + NULL +}; +#endif +#define pci_ss_list_16ed NULL +#define pci_ss_list_16f3 NULL +#define pci_ss_list_16f4 NULL +#define pci_ss_list_16f6 NULL +#define pci_ss_list_1702 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1705[] = { + &pci_ss_info_1705_0001, + &pci_ss_info_1705_0002, + &pci_ss_info_1705_0003, + &pci_ss_info_1705_0004, + NULL +}; +#endif +#define pci_ss_list_170b NULL +#define pci_ss_list_170c NULL +#define pci_ss_list_1725 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_172a[] = { + &pci_ss_info_172a_0000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1734[] = { + &pci_ss_info_1734_007a, + &pci_ss_info_1734_1004, + &pci_ss_info_1734_1005, + &pci_ss_info_1734_100b, + &pci_ss_info_1734_100c, + &pci_ss_info_1734_1011, + &pci_ss_info_1734_1012, + &pci_ss_info_1734_101c, + &pci_ss_info_1734_1025, + &pci_ss_info_1734_103e, + &pci_ss_info_1734_1052, + &pci_ss_info_1734_1055, + &pci_ss_info_1734_105a, + &pci_ss_info_1734_105b, + &pci_ss_info_1734_105c, + &pci_ss_info_1734_105d, + &pci_ss_info_1734_1061, + &pci_ss_info_1734_1065, + &pci_ss_info_1734_106c, + &pci_ss_info_1734_1081, + &pci_ss_info_1734_10a3, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1737[] = { + &pci_ss_info_1737_0015, + &pci_ss_info_1737_0016, + &pci_ss_info_1737_0024, + &pci_ss_info_1737_0032, + &pci_ss_info_1737_0033, + &pci_ss_info_1737_0048, + &pci_ss_info_1737_0055, + &pci_ss_info_1737_3874, + &pci_ss_info_1737_4320, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_173b[] = { + &pci_ss_info_173b_0001, + NULL +}; +#endif +#define pci_ss_list_1743 NULL +#define pci_ss_list_1749 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_174b[] = { + &pci_ss_info_174b_7112, + &pci_ss_info_174b_7146, + &pci_ss_info_174b_7147, + &pci_ss_info_174b_7149, + &pci_ss_info_174b_7161, + &pci_ss_info_174b_7176, + &pci_ss_info_174b_7192, + &pci_ss_info_174b_7c12, + &pci_ss_info_174b_7c13, + &pci_ss_info_174b_7c19, + &pci_ss_info_174b_7c28, + &pci_ss_info_174b_7c29, + NULL +}; +#endif +#define pci_ss_list_174d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_175c[] = { + &pci_ss_info_175c_4200, + &pci_ss_info_175c_4300, + &pci_ss_info_175c_4400, + &pci_ss_info_175c_5000, + &pci_ss_info_175c_5100, + &pci_ss_info_175c_6100, + &pci_ss_info_175c_6200, + &pci_ss_info_175c_6400, + &pci_ss_info_175c_8700, + &pci_ss_info_175c_8800, + NULL +}; +#endif +#define pci_ss_list_175e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1775[] = { + &pci_ss_info_1775_10d0, + &pci_ss_info_1775_10d1, + &pci_ss_info_1775_6003, + &pci_ss_info_1775_ce90, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1787[] = { + &pci_ss_info_1787_0202, + &pci_ss_info_1787_4002, + &pci_ss_info_1787_4003, + &pci_ss_info_1787_5964, + &pci_ss_info_1787_5965, + NULL +}; +#endif +#define pci_ss_list_1796 NULL +#define pci_ss_list_1797 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1799[] = { + &pci_ss_info_1799_0001, + &pci_ss_info_1799_0002, + &pci_ss_info_1799_5000, + &pci_ss_info_1799_7001, + &pci_ss_info_1799_700a, + &pci_ss_info_1799_7010, + &pci_ss_info_1799_7011, + &pci_ss_info_1799_701a, + NULL +}; +#endif +#define pci_ss_list_179c NULL +#define pci_ss_list_17a0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17aa[] = { + &pci_ss_info_17aa_0286, + &pci_ss_info_17aa_0287, + &pci_ss_info_17aa_2001, + &pci_ss_info_17aa_2007, + &pci_ss_info_17aa_2009, + &pci_ss_info_17aa_200a, + &pci_ss_info_17aa_200b, + &pci_ss_info_17aa_200c, + &pci_ss_info_17aa_200d, + &pci_ss_info_17aa_200f, + &pci_ss_info_17aa_2010, + &pci_ss_info_17aa_2012, + &pci_ss_info_17aa_2017, + &pci_ss_info_17aa_201a, + &pci_ss_info_17aa_201c, + &pci_ss_info_17aa_201d, + &pci_ss_info_17aa_201e, + &pci_ss_info_17aa_207e, + &pci_ss_info_17aa_2081, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17af[] = { + &pci_ss_info_17af_0202, + &pci_ss_info_17af_2005, + &pci_ss_info_17af_2006, + &pci_ss_info_17af_200c, + &pci_ss_info_17af_200d, + &pci_ss_info_17af_2012, + &pci_ss_info_17af_2013, + NULL +}; +#endif +#define pci_ss_list_17b3 NULL +#define pci_ss_list_17b4 NULL +#define pci_ss_list_17c0 NULL +#define pci_ss_list_17c2 NULL +#define pci_ss_list_17cb NULL +#define pci_ss_list_17cc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17cf[] = { + &pci_ss_info_17cf_0014, + &pci_ss_info_17cf_0020, + &pci_ss_info_17cf_0037, + NULL +}; +#endif +#define pci_ss_list_17d3 NULL +#define pci_ss_list_17d5 NULL +#define pci_ss_list_17db NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17de[] = { + &pci_ss_info_17de_08a1, + &pci_ss_info_17de_08a6, + &pci_ss_info_17de_08b2, + &pci_ss_info_17de_a8a6, + NULL +}; +#endif +#define pci_ss_list_17e4 NULL +#define pci_ss_list_17e6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17ee[] = { + &pci_ss_info_17ee_1001, + &pci_ss_info_17ee_2002, + &pci_ss_info_17ee_2003, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17f2[] = { + &pci_ss_info_17f2_1c03, + &pci_ss_info_17f2_2c08, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17fe[] = { + &pci_ss_info_17fe_2220, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_17ff[] = { + &pci_ss_info_17ff_0585, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1809[] = { + &pci_ss_info_1809_0016, + NULL +}; +#endif +#define pci_ss_list_1813 NULL +#define pci_ss_list_1814 NULL +#define pci_ss_list_1820 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1822[] = { + &pci_ss_info_1822_0001, + &pci_ss_info_1822_0025, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_182d[] = { + &pci_ss_info_182d_201d, + NULL +}; +#endif +#define pci_ss_list_182e NULL +#define pci_ss_list_1830 NULL +#define pci_ss_list_183b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1849[] = { + &pci_ss_info_1849_0571, + &pci_ss_info_1849_3038, + &pci_ss_info_1849_3065, + &pci_ss_info_1849_3099, + &pci_ss_info_1849_3104, + &pci_ss_info_1849_3149, + &pci_ss_info_1849_3177, + &pci_ss_info_1849_3189, + &pci_ss_info_1849_3227, + &pci_ss_info_1849_5229, + &pci_ss_info_1849_8052, + &pci_ss_info_1849_8053, + &pci_ss_info_1849_9761, + NULL +}; +#endif +#define pci_ss_list_184a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1851[] = { + &pci_ss_info_1851_1850, + &pci_ss_info_1851_1851, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1852[] = { + &pci_ss_info_1852_1852, + NULL +}; +#endif +#define pci_ss_list_1853 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1854[] = { + &pci_ss_info_1854_000b, + &pci_ss_info_1854_000c, + &pci_ss_info_1854_000d, + &pci_ss_info_1854_000e, + &pci_ss_info_1854_000f, + &pci_ss_info_1854_0010, + &pci_ss_info_1854_0011, + &pci_ss_info_1854_0012, + &pci_ss_info_1854_0013, + &pci_ss_info_1854_0014, + &pci_ss_info_1854_0015, + &pci_ss_info_1854_0016, + &pci_ss_info_1854_0017, + &pci_ss_info_1854_0018, + &pci_ss_info_1854_0019, + &pci_ss_info_1854_001a, + &pci_ss_info_1854_001b, + &pci_ss_info_1854_001c, + &pci_ss_info_1854_001d, + &pci_ss_info_1854_001e, + &pci_ss_info_1854_001f, + &pci_ss_info_1854_0020, + &pci_ss_info_1854_0021, + &pci_ss_info_1854_0022, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_185b[] = { + &pci_ss_info_185b_c100, + &pci_ss_info_185b_c200, + &pci_ss_info_185b_c900, + &pci_ss_info_185b_c901, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_185f[] = { + &pci_ss_info_185f_1220, + &pci_ss_info_185f_2012, + &pci_ss_info_185f_22a0, + NULL +}; +#endif +#define pci_ss_list_1864 NULL +#define pci_ss_list_1867 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_187e[] = { + &pci_ss_info_187e_3406, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1885[] = { + &pci_ss_info_1885_0700, + &pci_ss_info_1885_0701, + NULL +}; +#endif +#define pci_ss_list_1888 NULL +#define pci_ss_list_188a NULL +#define pci_ss_list_1890 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1894[] = { + &pci_ss_info_1894_a006, + &pci_ss_info_1894_fe01, + NULL +}; +#endif +#define pci_ss_list_1896 NULL +#define pci_ss_list_18a1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_18ac[] = { + &pci_ss_info_18ac_d500, + &pci_ss_info_18ac_d810, + &pci_ss_info_18ac_d820, + &pci_ss_info_18ac_db00, + &pci_ss_info_18ac_db10, + &pci_ss_info_18ac_db11, + &pci_ss_info_18ac_db50, + NULL +}; +#endif +#define pci_ss_list_18b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_18bc[] = { + &pci_ss_info_18bc_0050, + &pci_ss_info_18bc_0051, + &pci_ss_info_18bc_0053, + &pci_ss_info_18bc_0100, + &pci_ss_info_18bc_0101, + &pci_ss_info_18bc_0170, + &pci_ss_info_18bc_0171, + &pci_ss_info_18bc_0172, + &pci_ss_info_18bc_0173, + NULL +}; +#endif +#define pci_ss_list_18c3 NULL +#define pci_ss_list_18c8 NULL +#define pci_ss_list_18c9 NULL +#define pci_ss_list_18ca NULL +#define pci_ss_list_18d2 NULL +#define pci_ss_list_18dd NULL +#define pci_ss_list_18e6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_18ec[] = { + &pci_ss_info_18ec_d001, + &pci_ss_info_18ec_d002, + &pci_ss_info_18ec_d003, + &pci_ss_info_18ec_d004, + NULL +}; +#endif +#define pci_ss_list_18f6 NULL +#define pci_ss_list_18f7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_18fb[] = { + &pci_ss_info_18fb_7872, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1904[] = { + &pci_ss_info_1904_8139, + NULL +}; +#endif +#define pci_ss_list_1923 NULL +#define pci_ss_list_1924 NULL +#define pci_ss_list_192e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1931[] = { + &pci_ss_info_1931_000a, + &pci_ss_info_1931_000b, + NULL +}; +#endif +#define pci_ss_list_1942 NULL +#define pci_ss_list_194a NULL +#define pci_ss_list_1957 NULL +#define pci_ss_list_1958 NULL +#define pci_ss_list_1966 NULL +#define pci_ss_list_1969 NULL +#define pci_ss_list_196a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_196d[] = { + &pci_ss_info_196d_1086, + &pci_ss_info_196d_1087, + NULL +}; +#endif +#define pci_ss_list_197b NULL +#define pci_ss_list_1989 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1993[] = { + &pci_ss_info_1993_0ded, + &pci_ss_info_1993_0dee, + &pci_ss_info_1993_0def, + NULL +}; +#endif +#define pci_ss_list_199a NULL +#define pci_ss_list_19a8 NULL +#define pci_ss_list_19ac NULL +#define pci_ss_list_19ae NULL +#define pci_ss_list_19d4 NULL +#define pci_ss_list_19e2 NULL +#define pci_ss_list_19e7 NULL +#define pci_ss_list_1a03 NULL +#define pci_ss_list_1a08 NULL +#define pci_ss_list_1a1d NULL +#define pci_ss_list_1a29 NULL +#define pci_ss_list_1a51 NULL +#define pci_ss_list_1b13 NULL +#define pci_ss_list_1c1c NULL +#define pci_ss_list_1d44 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1de1[] = { + &pci_ss_info_1de1_1020, + &pci_ss_info_1de1_3904, + &pci_ss_info_1de1_3906, + &pci_ss_info_1de1_3907, + &pci_ss_info_1de1_9fff, + NULL +}; +#endif +#define pci_ss_list_1fc0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_1fc1[] = { + &pci_ss_info_1fc1_0026, + &pci_ss_info_1fc1_0027, + NULL +}; +#endif +#define pci_ss_list_1fce NULL +#define pci_ss_list_2000 NULL +#define pci_ss_list_2001 NULL +#define pci_ss_list_2003 NULL +#define pci_ss_list_2004 NULL +#define pci_ss_list_21c3 NULL +#define pci_ss_list_22b8 NULL +#define pci_ss_list_2348 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_2646[] = { + &pci_ss_info_2646_0001, + NULL +}; +#endif +#define pci_ss_list_270b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_270f[] = { + &pci_ss_info_270f_2001, + &pci_ss_info_270f_2200, + &pci_ss_info_270f_2801, + &pci_ss_info_270f_2803, + &pci_ss_info_270f_3000, + &pci_ss_info_270f_3100, + &pci_ss_info_270f_3102, + &pci_ss_info_270f_7040, + &pci_ss_info_270f_7060, + &pci_ss_info_270f_a171, + &pci_ss_info_270f_f641, + &pci_ss_info_270f_f645, + &pci_ss_info_270f_fc00, + NULL +}; +#endif +#define pci_ss_list_2711 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_2a15[] = { + &pci_ss_info_2a15_54a3, + NULL +}; +#endif +#define pci_ss_list_3000 NULL +#define pci_ss_list_3142 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_3388[] = { + &pci_ss_info_3388_8011, + &pci_ss_info_3388_8012, + &pci_ss_info_3388_8013, + NULL +}; +#endif +#define pci_ss_list_3411 NULL +#define pci_ss_list_3513 NULL +#define pci_ss_list_3842 NULL +#define pci_ss_list_38ef NULL +static const pciSubsystemInfo *pci_ss_list_3d3d[] = { + &pci_ss_info_3d3d_0100, + &pci_ss_info_3d3d_0111, + &pci_ss_info_3d3d_0114, + &pci_ss_info_3d3d_0116, + &pci_ss_info_3d3d_0119, + &pci_ss_info_3d3d_0120, + &pci_ss_info_3d3d_0121, + &pci_ss_info_3d3d_0125, + &pci_ss_info_3d3d_0127, + &pci_ss_info_3d3d_0144, + NULL +}; +static const pciSubsystemInfo *pci_ss_list_4005[] = { + &pci_ss_info_4005_144f, + &pci_ss_info_4005_4000, + &pci_ss_info_4005_4710, + NULL +}; +#define pci_ss_list_4033 NULL +#define pci_ss_list_4143 NULL +#define pci_ss_list_4144 NULL +#define pci_ss_list_416c NULL +#define pci_ss_list_4321 NULL +#define pci_ss_list_4444 NULL +#define pci_ss_list_4468 NULL +#define pci_ss_list_4594 NULL +#define pci_ss_list_45fb NULL +#define pci_ss_list_4680 NULL +#define pci_ss_list_4843 NULL +#define pci_ss_list_4916 NULL +#define pci_ss_list_4943 NULL +#define pci_ss_list_494f NULL +#define pci_ss_list_4978 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_4a14[] = { + &pci_ss_info_4a14_5000, + NULL +}; +#endif +#define pci_ss_list_4b10 NULL +#define pci_ss_list_4c48 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_4c53[] = { + &pci_ss_info_4c53_1000, + &pci_ss_info_4c53_1010, + &pci_ss_info_4c53_1020, + &pci_ss_info_4c53_1030, + &pci_ss_info_4c53_1040, + &pci_ss_info_4c53_1050, + &pci_ss_info_4c53_1051, + &pci_ss_info_4c53_1060, + &pci_ss_info_4c53_1070, + &pci_ss_info_4c53_1080, + &pci_ss_info_4c53_1090, + &pci_ss_info_4c53_10a0, + &pci_ss_info_4c53_10b0, + &pci_ss_info_4c53_10d0, + &pci_ss_info_4c53_10e0, + &pci_ss_info_4c53_1300, + &pci_ss_info_4c53_1310, + &pci_ss_info_4c53_3000, + &pci_ss_info_4c53_3001, + &pci_ss_info_4c53_3002, + &pci_ss_info_4c53_3010, + &pci_ss_info_4c53_3011, + &pci_ss_info_4c53_4000, + NULL +}; +#endif +#define pci_ss_list_4ca1 NULL +#define pci_ss_list_4d51 NULL +#define pci_ss_list_4d54 NULL +#define pci_ss_list_4ddc NULL +#define pci_ss_list_5046 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_5053[] = { + &pci_ss_info_5053_3355, + &pci_ss_info_5053_3356, + &pci_ss_info_5053_3357, + NULL +}; +#endif +#define pci_ss_list_5136 NULL +#define pci_ss_list_5143 NULL +#define pci_ss_list_5145 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_5168[] = { + &pci_ss_info_5168_0138, + &pci_ss_info_5168_0306, + &pci_ss_info_5168_0319, + &pci_ss_info_5168_0502, + &pci_ss_info_5168_0520, + &pci_ss_info_5168_1502, + &pci_ss_info_5168_2502, + &pci_ss_info_5168_2520, + &pci_ss_info_5168_3502, + &pci_ss_info_5168_3520, + NULL +}; +#endif +#define pci_ss_list_5301 NULL +static const pciSubsystemInfo *pci_ss_list_5333[] = { + &pci_ss_info_5333_8100, + &pci_ss_info_5333_8110, + &pci_ss_info_5333_8125, + &pci_ss_info_5333_8143, + &pci_ss_info_5333_8900, + &pci_ss_info_5333_8901, + &pci_ss_info_5333_8904, + &pci_ss_info_5333_8a01, + &pci_ss_info_5333_8a13, + &pci_ss_info_5333_8a20, + &pci_ss_info_5333_8a21, + &pci_ss_info_5333_8a22, + &pci_ss_info_5333_8a2e, + &pci_ss_info_5333_9125, + &pci_ss_info_5333_9143, + NULL +}; +#define pci_ss_list_544c NULL +#define pci_ss_list_5455 NULL +#define pci_ss_list_5519 NULL +#define pci_ss_list_5544 NULL +#define pci_ss_list_5555 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_5654[] = { + &pci_ss_info_5654_2036, + &pci_ss_info_5654_3132, + &pci_ss_info_5654_5634, + NULL +}; +#endif +#define pci_ss_list_5700 NULL +#define pci_ss_list_5851 NULL +#define pci_ss_list_6356 NULL +#define pci_ss_list_6374 NULL +#define pci_ss_list_6409 NULL +#define pci_ss_list_6666 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_7063[] = { + &pci_ss_info_7063_3000, + NULL +}; +#endif +#define pci_ss_list_7604 NULL +#define pci_ss_list_7bde NULL +#define pci_ss_list_7fed NULL +#define pci_ss_list_8008 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_807d[] = { + &pci_ss_info_807d_0035, + &pci_ss_info_807d_1043, + NULL +}; +#endif +static const pciSubsystemInfo *pci_ss_list_8086[] = { + &pci_ss_info_8086_0000, + &pci_ss_info_8086_0001, + &pci_ss_info_8086_0002, + &pci_ss_info_8086_0003, + &pci_ss_info_8086_0004, + &pci_ss_info_8086_0005, + &pci_ss_info_8086_0006, + &pci_ss_info_8086_0007, + &pci_ss_info_8086_0008, + &pci_ss_info_8086_000a, + &pci_ss_info_8086_000b, + &pci_ss_info_8086_000c, + &pci_ss_info_8086_000d, + &pci_ss_info_8086_000e, + &pci_ss_info_8086_000f, + &pci_ss_info_8086_0010, + &pci_ss_info_8086_0011, + &pci_ss_info_8086_0012, + &pci_ss_info_8086_0013, + &pci_ss_info_8086_0014, + &pci_ss_info_8086_001e, + &pci_ss_info_8086_002a, + &pci_ss_info_8086_002b, + &pci_ss_info_8086_002e, + &pci_ss_info_8086_0030, + &pci_ss_info_8086_0031, + &pci_ss_info_8086_0040, + &pci_ss_info_8086_0041, + &pci_ss_info_8086_0042, + &pci_ss_info_8086_0050, + &pci_ss_info_8086_005e, + &pci_ss_info_8086_0060, + &pci_ss_info_8086_0075, + &pci_ss_info_8086_0076, + &pci_ss_info_8086_0077, + &pci_ss_info_8086_0079, + &pci_ss_info_8086_007b, + &pci_ss_info_8086_0100, + &pci_ss_info_8086_01af, + &pci_ss_info_8086_01c1, + &pci_ss_info_8086_01f7, + &pci_ss_info_8086_0520, + &pci_ss_info_8086_0523, + &pci_ss_info_8086_0530, + &pci_ss_info_8086_0532, + &pci_ss_info_8086_1000, + &pci_ss_info_8086_1001, + &pci_ss_info_8086_1002, + &pci_ss_info_8086_1003, + &pci_ss_info_8086_1004, + &pci_ss_info_8086_1005, + &pci_ss_info_8086_1009, + &pci_ss_info_8086_100c, + &pci_ss_info_8086_1011, + &pci_ss_info_8086_1012, + &pci_ss_info_8086_1013, + &pci_ss_info_8086_1014, + &pci_ss_info_8086_1015, + &pci_ss_info_8086_1016, + &pci_ss_info_8086_1017, + &pci_ss_info_8086_1018, + &pci_ss_info_8086_1019, + &pci_ss_info_8086_101a, + &pci_ss_info_8086_101e, + &pci_ss_info_8086_1026, + &pci_ss_info_8086_1027, + &pci_ss_info_8086_1028, + &pci_ss_info_8086_1030, + &pci_ss_info_8086_1034, + &pci_ss_info_8086_1040, + &pci_ss_info_8086_1041, + &pci_ss_info_8086_1042, + &pci_ss_info_8086_1044, + &pci_ss_info_8086_1050, + &pci_ss_info_8086_1051, + &pci_ss_info_8086_1052, + &pci_ss_info_8086_105e, + &pci_ss_info_8086_1060, + &pci_ss_info_8086_1075, + &pci_ss_info_8086_1076, + &pci_ss_info_8086_1077, + &pci_ss_info_8086_1078, + &pci_ss_info_8086_1079, + &pci_ss_info_8086_107a, + &pci_ss_info_8086_107b, + &pci_ss_info_8086_1082, + &pci_ss_info_8086_1083, + &pci_ss_info_8086_1084, + &pci_ss_info_8086_108a, + &pci_ss_info_8086_1092, + &pci_ss_info_8086_1093, + &pci_ss_info_8086_1094, + &pci_ss_info_8086_1099, + &pci_ss_info_8086_109a, + &pci_ss_info_8086_10f0, + &pci_ss_info_8086_1107, + &pci_ss_info_8086_1109, + &pci_ss_info_8086_110d, + &pci_ss_info_8086_1112, + &pci_ss_info_8086_1113, + &pci_ss_info_8086_115e, + &pci_ss_info_8086_115f, + &pci_ss_info_8086_1161, + &pci_ss_info_8086_116e, + &pci_ss_info_8086_116f, + &pci_ss_info_8086_1176, + &pci_ss_info_8086_1179, + &pci_ss_info_8086_117a, + &pci_ss_info_8086_118a, + &pci_ss_info_8086_1199, + &pci_ss_info_8086_125e, + &pci_ss_info_8086_125f, + &pci_ss_info_8086_1276, + &pci_ss_info_8086_127a, + &pci_ss_info_8086_135e, + &pci_ss_info_8086_135f, + &pci_ss_info_8086_1361, + &pci_ss_info_8086_1376, + &pci_ss_info_8086_1476, + &pci_ss_info_8086_1958, + &pci_ss_info_8086_2004, + &pci_ss_info_8086_2009, + &pci_ss_info_8086_200d, + &pci_ss_info_8086_200e, + &pci_ss_info_8086_200f, + &pci_ss_info_8086_2010, + &pci_ss_info_8086_2013, + &pci_ss_info_8086_2016, + &pci_ss_info_8086_2017, + &pci_ss_info_8086_2018, + &pci_ss_info_8086_2019, + &pci_ss_info_8086_2101, + &pci_ss_info_8086_2102, + &pci_ss_info_8086_2103, + &pci_ss_info_8086_2104, + &pci_ss_info_8086_2105, + &pci_ss_info_8086_2106, + &pci_ss_info_8086_2107, + &pci_ss_info_8086_2108, + &pci_ss_info_8086_2109, + &pci_ss_info_8086_2110, + &pci_ss_info_8086_2112, + &pci_ss_info_8086_2200, + &pci_ss_info_8086_2201, + &pci_ss_info_8086_2202, + &pci_ss_info_8086_2203, + &pci_ss_info_8086_2204, + &pci_ss_info_8086_2205, + &pci_ss_info_8086_2206, + &pci_ss_info_8086_2207, + &pci_ss_info_8086_2208, + &pci_ss_info_8086_2402, + &pci_ss_info_8086_2407, + &pci_ss_info_8086_2408, + &pci_ss_info_8086_2409, + &pci_ss_info_8086_240f, + &pci_ss_info_8086_2410, + &pci_ss_info_8086_2411, + &pci_ss_info_8086_2412, + &pci_ss_info_8086_2413, + &pci_ss_info_8086_24db, + &pci_ss_info_8086_2513, + &pci_ss_info_8086_2527, + &pci_ss_info_8086_265c, + &pci_ss_info_8086_3000, + &pci_ss_info_8086_3001, + &pci_ss_info_8086_3002, + &pci_ss_info_8086_3006, + &pci_ss_info_8086_3007, + &pci_ss_info_8086_3008, + &pci_ss_info_8086_3010, + &pci_ss_info_8086_3011, + &pci_ss_info_8086_3012, + &pci_ss_info_8086_3013, + &pci_ss_info_8086_3014, + &pci_ss_info_8086_3015, + &pci_ss_info_8086_3016, + &pci_ss_info_8086_3017, + &pci_ss_info_8086_3018, + &pci_ss_info_8086_301f, + &pci_ss_info_8086_3020, + &pci_ss_info_8086_302c, + &pci_ss_info_8086_302f, + &pci_ss_info_8086_3063, + &pci_ss_info_8086_308d, + &pci_ss_info_8086_3108, + &pci_ss_info_8086_3411, + &pci_ss_info_8086_3424, + &pci_ss_info_8086_3427, + &pci_ss_info_8086_3431, + &pci_ss_info_8086_3439, + &pci_ss_info_8086_3499, + &pci_ss_info_8086_3500, + &pci_ss_info_8086_3501, + &pci_ss_info_8086_3504, + &pci_ss_info_8086_4147, + &pci_ss_info_8086_4152, + &pci_ss_info_8086_4246, + &pci_ss_info_8086_4249, + &pci_ss_info_8086_424c, + &pci_ss_info_8086_425a, + &pci_ss_info_8086_4341, + &pci_ss_info_8086_4343, + &pci_ss_info_8086_4532, + &pci_ss_info_8086_4541, + &pci_ss_info_8086_4557, + &pci_ss_info_8086_4649, + &pci_ss_info_8086_464a, + &pci_ss_info_8086_4c43, + &pci_ss_info_8086_4d4f, + &pci_ss_info_8086_4f43, + &pci_ss_info_8086_5243, + &pci_ss_info_8086_524c, + &pci_ss_info_8086_5352, + &pci_ss_info_8086_544e, + &pci_ss_info_8086_5643, + &pci_ss_info_8086_5753, + &pci_ss_info_8086_8000, + &pci_ss_info_8086_8181, + &pci_ss_info_8086_9181, + &pci_ss_info_8086_a000, + &pci_ss_info_8086_a01f, + &pci_ss_info_8086_a11f, + &pci_ss_info_8086_e000, + &pci_ss_info_8086_e001, + &pci_ss_info_8086_e002, + NULL +}; +#define pci_ss_list_8401 NULL +#define pci_ss_list_8686 NULL +#define pci_ss_list_8800 NULL +#define pci_ss_list_8866 NULL +#define pci_ss_list_8888 NULL +#define pci_ss_list_8912 NULL +#define pci_ss_list_8c4a NULL +#define pci_ss_list_8e0e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_8e2e[] = { + &pci_ss_info_8e2e_7000, + &pci_ss_info_8e2e_7100, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_9004[] = { + &pci_ss_info_9004_0008, + &pci_ss_info_9004_0009, + &pci_ss_info_9004_0010, + &pci_ss_info_9004_0018, + &pci_ss_info_9004_0019, + &pci_ss_info_9004_0020, + &pci_ss_info_9004_0028, + &pci_ss_info_9004_7560, + &pci_ss_info_9004_7710, + &pci_ss_info_9004_7711, + &pci_ss_info_9004_7815, + &pci_ss_info_9004_7840, + &pci_ss_info_9004_7850, + &pci_ss_info_9004_7861, + &pci_ss_info_9004_7880, + &pci_ss_info_9004_7881, + &pci_ss_info_9004_7887, + &pci_ss_info_9004_7888, + &pci_ss_info_9004_7890, + &pci_ss_info_9004_7891, + &pci_ss_info_9004_7892, + &pci_ss_info_9004_7894, + &pci_ss_info_9004_7895, + &pci_ss_info_9004_7896, + &pci_ss_info_9004_7897, + &pci_ss_info_9004_8008, + &pci_ss_info_9004_8009, + &pci_ss_info_9004_8010, + &pci_ss_info_9004_8018, + &pci_ss_info_9004_8019, + &pci_ss_info_9004_8020, + &pci_ss_info_9004_8028, + &pci_ss_info_9004_9110, + &pci_ss_info_9004_9111, + &pci_ss_info_9004_9210, + &pci_ss_info_9004_9211, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_9005[] = { + &pci_ss_info_9005_0003, + &pci_ss_info_9005_000f, + &pci_ss_info_9005_0041, + &pci_ss_info_9005_0092, + &pci_ss_info_9005_0093, + &pci_ss_info_9005_0106, + &pci_ss_info_9005_0250, + &pci_ss_info_9005_0283, + &pci_ss_info_9005_0284, + &pci_ss_info_9005_0285, + &pci_ss_info_9005_0286, + &pci_ss_info_9005_0287, + &pci_ss_info_9005_0288, + &pci_ss_info_9005_0289, + &pci_ss_info_9005_028a, + &pci_ss_info_9005_028b, + &pci_ss_info_9005_028c, + &pci_ss_info_9005_028d, + &pci_ss_info_9005_028e, + &pci_ss_info_9005_028f, + &pci_ss_info_9005_0290, + &pci_ss_info_9005_0292, + &pci_ss_info_9005_0293, + &pci_ss_info_9005_0294, + &pci_ss_info_9005_0296, + &pci_ss_info_9005_0297, + &pci_ss_info_9005_0298, + &pci_ss_info_9005_0299, + &pci_ss_info_9005_029a, + &pci_ss_info_9005_029b, + &pci_ss_info_9005_029c, + &pci_ss_info_9005_029d, + &pci_ss_info_9005_029e, + &pci_ss_info_9005_029f, + &pci_ss_info_9005_02a0, + &pci_ss_info_9005_02a1, + &pci_ss_info_9005_02a2, + &pci_ss_info_9005_02a3, + &pci_ss_info_9005_02a4, + &pci_ss_info_9005_02a5, + &pci_ss_info_9005_02a6, + &pci_ss_info_9005_02a7, + &pci_ss_info_9005_02a8, + &pci_ss_info_9005_02a9, + &pci_ss_info_9005_02aa, + &pci_ss_info_9005_02ac, + &pci_ss_info_9005_02b3, + &pci_ss_info_9005_02b4, + &pci_ss_info_9005_02b5, + &pci_ss_info_9005_02b6, + &pci_ss_info_9005_02b7, + &pci_ss_info_9005_0364, + &pci_ss_info_9005_0365, + &pci_ss_info_9005_0410, + &pci_ss_info_9005_0411, + &pci_ss_info_9005_0412, + &pci_ss_info_9005_0413, + &pci_ss_info_9005_041f, + &pci_ss_info_9005_0430, + &pci_ss_info_9005_0432, + &pci_ss_info_9005_0800, + &pci_ss_info_9005_1364, + &pci_ss_info_9005_1365, + &pci_ss_info_9005_2180, + &pci_ss_info_9005_6220, + &pci_ss_info_9005_62a0, + &pci_ss_info_9005_62a1, + &pci_ss_info_9005_8100, + &pci_ss_info_9005_a100, + &pci_ss_info_9005_a180, + &pci_ss_info_9005_b500, + &pci_ss_info_9005_e100, + &pci_ss_info_9005_e220, + &pci_ss_info_9005_e2a0, + &pci_ss_info_9005_f500, + &pci_ss_info_9005_f620, + &pci_ss_info_9005_ffff, + NULL +}; +#endif +#define pci_ss_list_907f NULL +#define pci_ss_list_919a NULL +#define pci_ss_list_9412 NULL +#define pci_ss_list_9699 NULL +#define pci_ss_list_9710 NULL +#define pci_ss_list_9902 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_a0a0[] = { + &pci_ss_info_a0a0_0007, + &pci_ss_info_a0a0_0022, + &pci_ss_info_a0a0_01b6, + &pci_ss_info_a0a0_0304, + &pci_ss_info_a0a0_0306, + &pci_ss_info_a0a0_03b2, + &pci_ss_info_a0a0_03b4, + &pci_ss_info_a0a0_03b5, + &pci_ss_info_a0a0_03b9, + &pci_ss_info_a0a0_03ba, + &pci_ss_info_a0a0_03bb, + &pci_ss_info_a0a0_0506, + &pci_ss_info_a0a0_0509, + NULL +}; +#endif +#define pci_ss_list_a0f1 NULL +#define pci_ss_list_a200 NULL +#define pci_ss_list_a259 NULL +#define pci_ss_list_a25b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_a304[] = { + &pci_ss_info_a304_81b7, + NULL +}; +#endif +#define pci_ss_list_a727 NULL +#define pci_ss_list_aa42 NULL +#define pci_ss_list_ac1e NULL +#define pci_ss_list_ac3d NULL +#define pci_ss_list_aecb NULL +#define pci_ss_list_affe NULL +#define pci_ss_list_b10b NULL +#define pci_ss_list_b1b3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_bd11[] = { + &pci_ss_info_bd11_1200, + NULL +}; +#endif +#define pci_ss_list_c001 NULL +#define pci_ss_list_c0a9 NULL +#define pci_ss_list_c0de NULL +#define pci_ss_list_c0fe NULL +#define pci_ss_list_ca50 NULL +#define pci_ss_list_cafe NULL +#define pci_ss_list_cccc NULL +#define pci_ss_list_ccec NULL +#define pci_ss_list_cddd NULL +#define pci_ss_list_d161 NULL +#define pci_ss_list_d4d4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_d531[] = { + &pci_ss_info_d531_c002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_d84d[] = { + &pci_ss_info_d84d_4006, + &pci_ss_info_d84d_4008, + &pci_ss_info_d84d_4014, + &pci_ss_info_d84d_4018, + &pci_ss_info_d84d_4025, + &pci_ss_info_d84d_4027, + &pci_ss_info_d84d_4028, + &pci_ss_info_d84d_4036, + &pci_ss_info_d84d_4037, + &pci_ss_info_d84d_4038, + &pci_ss_info_d84d_4052, + &pci_ss_info_d84d_4053, + &pci_ss_info_d84d_4055, + &pci_ss_info_d84d_4058, + &pci_ss_info_d84d_4065, + &pci_ss_info_d84d_4068, + &pci_ss_info_d84d_4078, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_dead[] = { + &pci_ss_info_dead_0800, + NULL +}; +#endif +#define pci_ss_list_deaf NULL +#define pci_ss_list_e000 NULL +#define pci_ss_list_e159 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_e4bf[] = { + &pci_ss_info_e4bf_1000, + &pci_ss_info_e4bf_1010, + &pci_ss_info_e4bf_1020, + &pci_ss_info_e4bf_1040, + &pci_ss_info_e4bf_3100, + NULL +}; +#endif +#define pci_ss_list_e55e NULL +#define pci_ss_list_ea01 NULL +#define pci_ss_list_ea60 NULL +#define pci_ss_list_eabb NULL +#define pci_ss_list_eace NULL +#define pci_ss_list_ec80 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciSubsystemInfo *pci_ss_list_ecc0[] = { + &pci_ss_info_ecc0_0010, + &pci_ss_info_ecc0_0020, + &pci_ss_info_ecc0_0030, + &pci_ss_info_ecc0_0031, + &pci_ss_info_ecc0_0040, + &pci_ss_info_ecc0_0041, + &pci_ss_info_ecc0_0050, + &pci_ss_info_ecc0_0051, + &pci_ss_info_ecc0_0060, + &pci_ss_info_ecc0_0070, + &pci_ss_info_ecc0_0071, + &pci_ss_info_ecc0_0072, + &pci_ss_info_ecc0_0080, + &pci_ss_info_ecc0_0081, + &pci_ss_info_ecc0_0090, + &pci_ss_info_ecc0_00a0, + &pci_ss_info_ecc0_00b0, + &pci_ss_info_ecc0_0100, + NULL +}; +#endif +#define pci_ss_list_edd8 NULL +#define pci_ss_list_f1d0 NULL +#define pci_ss_list_fa57 NULL +#define pci_ss_list_fab7 NULL +#define pci_ss_list_febd NULL +#define pci_ss_list_feda NULL +#define pci_ss_list_fede NULL +#define pci_ss_list_fffd NULL +#define pci_ss_list_fffe NULL +#define pci_ss_list_ffff NULL +#endif /* INIT_VENDOR_SUBSYS_INFO */ +#endif /* INIT_SUBSYS_INFO */ +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0095_0680 = { + 0x0680, pci_device_0095_0680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0095_0680, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_018a_0106 = { + 0x0106, pci_device_018a_0106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_018a_0106, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_021b_8139 = { + 0x8139, pci_device_021b_8139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_021b_8139, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0291_8212 = { + 0x8212, pci_device_0291_8212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0291_8212, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_02ac_1012 = { + 0x1012, pci_device_02ac_1012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_02ac_1012, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0357_000a = { + 0x000a, pci_device_0357_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0357_000a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0432_0001 = { + 0x0001, pci_device_0432_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0432_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_045e_006e = { + 0x006e, pci_device_045e_006e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_045e_006e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_045e_00c2 = { + 0x00c2, pci_device_045e_00c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_045e_00c2, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_04cf_8818 = { + 0x8818, pci_device_04cf_8818, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_04cf_8818, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_050d_001a = { + 0x001a, pci_device_050d_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_050d_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_050d_0109 = { + 0x0109, pci_device_050d_0109, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_050d_0109, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_050d_7050 = { + 0x7050, pci_device_050d_7050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_050d_7050, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_05a9_8519 = { + 0x8519, pci_device_05a9_8519, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_05a9_8519, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_05e3_0701 = { + 0x0701, pci_device_05e3_0701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_05e3_0701, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_066f_3410 = { + 0x3410, pci_device_066f_3410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_066f_3410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_066f_3500 = { + 0x3500, pci_device_066f_3500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_066f_3500, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0675_1700 = { + 0x1700, pci_device_0675_1700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0675_1700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0675_1702 = { + 0x1702, pci_device_0675_1702, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0675_1702, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0675_1703 = { + 0x1703, pci_device_0675_1703, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0675_1703, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0675_1704 = { + 0x1704, pci_device_0675_1704, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0675_1704, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_067b_2303 = { + 0x2303, pci_device_067b_2303, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_067b_2303, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_067b_3507 = { + 0x3507, pci_device_067b_3507, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_067b_3507, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_09c1_0704 = { + 0x0704, pci_device_09c1_0704, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_09c1_0704, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0b0b_0105 = { + 0x0105, pci_device_0b0b_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0b0b_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0b0b_0205 = { + 0x0205, pci_device_0b0b_0205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0b0b_0205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0b0b_0305 = { + 0x0305, pci_device_0b0b_0305, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0b0b_0305, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0b0b_0405 = { + 0x0405, pci_device_0b0b_0405, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0b0b_0405, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0b0b_0505 = { + 0x0505, pci_device_0b0b_0505, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0b0b_0505, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0b0b_0506 = { + 0x0506, pci_device_0b0b_0506, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0b0b_0506, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0b0b_0605 = { + 0x0605, pci_device_0b0b_0605, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0b0b_0605, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0b0b_0705 = { + 0x0705, pci_device_0b0b_0705, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0b0b_0705, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0b49_064f = { + 0x064f, pci_device_0b49_064f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0b49_064f, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_0ccd_0038 = { + 0x0038, pci_device_0ccd_0038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0ccd_0038, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_0e11_0001 = { + 0x0001, pci_device_0e11_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_0002 = { + 0x0002, pci_device_0e11_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_0046 = { + 0x0046, pci_device_0e11_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_0049 = { + 0x0049, pci_device_0e11_0049, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0049, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_004a = { + 0x004a, pci_device_0e11_004a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_004a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_005a = { + 0x005a, pci_device_0e11_005a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_005a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_007c = { + 0x007c, pci_device_0e11_007c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_007c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_007d = { + 0x007d, pci_device_0e11_007d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_007d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_0085 = { + 0x0085, pci_device_0e11_0085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00b1 = { + 0x00b1, pci_device_0e11_00b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00bb = { + 0x00bb, pci_device_0e11_00bb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00bb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00ca = { + 0x00ca, pci_device_0e11_00ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00cb = { + 0x00cb, pci_device_0e11_00cb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00cb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00cf = { + 0x00cf, pci_device_0e11_00cf, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00cf, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00d0 = { + 0x00d0, pci_device_0e11_00d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00d1 = { + 0x00d1, pci_device_0e11_00d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_00e3 = { + 0x00e3, pci_device_0e11_00e3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_00e3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_0508 = { + 0x0508, pci_device_0e11_0508, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_0508, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_1000 = { + 0x1000, pci_device_0e11_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_2000 = { + 0x2000, pci_device_0e11_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_3032 = { + 0x3032, pci_device_0e11_3032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_3032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_3033 = { + 0x3033, pci_device_0e11_3033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_3033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_3034 = { + 0x3034, pci_device_0e11_3034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_3034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4000 = { + 0x4000, pci_device_0e11_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4030 = { + 0x4030, pci_device_0e11_4030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4031 = { + 0x4031, pci_device_0e11_4031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4032 = { + 0x4032, pci_device_0e11_4032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4033 = { + 0x4033, pci_device_0e11_4033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4034 = { + 0x4034, pci_device_0e11_4034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4040 = { + 0x4040, pci_device_0e11_4040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4048 = { + 0x4048, pci_device_0e11_4048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4050 = { + 0x4050, pci_device_0e11_4050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4051 = { + 0x4051, pci_device_0e11_4051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4058 = { + 0x4058, pci_device_0e11_4058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4070 = { + 0x4070, pci_device_0e11_4070, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4070, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4080 = { + 0x4080, pci_device_0e11_4080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4082 = { + 0x4082, pci_device_0e11_4082, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4082, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4083 = { + 0x4083, pci_device_0e11_4083, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4083, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_4091 = { + 0x4091, pci_device_0e11_4091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_4091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_409a = { + 0x409a, pci_device_0e11_409a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_409a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_409b = { + 0x409b, pci_device_0e11_409b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_409b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_409c = { + 0x409c, pci_device_0e11_409c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_409c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_409d = { + 0x409d, pci_device_0e11_409d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_409d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_6010 = { + 0x6010, pci_device_0e11_6010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_6010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_7020 = { + 0x7020, pci_device_0e11_7020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_7020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0ec = { + 0xa0ec, pci_device_0e11_a0ec, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0ec, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0f0 = { + 0xa0f0, pci_device_0e11_a0f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0f3 = { + 0xa0f3, pci_device_0e11_a0f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0f7 = { + 0xa0f7, pci_device_0e11_a0f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0f7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0f8 = { + 0xa0f8, pci_device_0e11_a0f8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0f8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_a0fc = { + 0xa0fc, pci_device_0e11_a0fc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_a0fc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae10 = { + 0xae10, pci_device_0e11_ae10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae29 = { + 0xae29, pci_device_0e11_ae29, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae29, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae2a = { + 0xae2a, pci_device_0e11_ae2a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae2a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae2b = { + 0xae2b, pci_device_0e11_ae2b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae2b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae31 = { + 0xae31, pci_device_0e11_ae31, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae31, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae32 = { + 0xae32, pci_device_0e11_ae32, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae32, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae33 = { + 0xae33, pci_device_0e11_ae33, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae33, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae34 = { + 0xae34, pci_device_0e11_ae34, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae34, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae35 = { + 0xae35, pci_device_0e11_ae35, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae35, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae40 = { + 0xae40, pci_device_0e11_ae40, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae40, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae43 = { + 0xae43, pci_device_0e11_ae43, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae43, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae69 = { + 0xae69, pci_device_0e11_ae69, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae69, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae6c = { + 0xae6c, pci_device_0e11_ae6c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae6c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_ae6d = { + 0xae6d, pci_device_0e11_ae6d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_ae6d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b011 = { + 0xb011, pci_device_0e11_b011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b012 = { + 0xb012, pci_device_0e11_b012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b01e = { + 0xb01e, pci_device_0e11_b01e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b01e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b01f = { + 0xb01f, pci_device_0e11_b01f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b01f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b02f = { + 0xb02f, pci_device_0e11_b02f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b02f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b030 = { + 0xb030, pci_device_0e11_b030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b04a = { + 0xb04a, pci_device_0e11_b04a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b04a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b060 = { + 0xb060, pci_device_0e11_b060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0c6 = { + 0xb0c6, pci_device_0e11_b0c6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0c6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0c7 = { + 0xb0c7, pci_device_0e11_b0c7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0c7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0d7 = { + 0xb0d7, pci_device_0e11_b0d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0dd = { + 0xb0dd, pci_device_0e11_b0dd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0dd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0de = { + 0xb0de, pci_device_0e11_b0de, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0de, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0df = { + 0xb0df, pci_device_0e11_b0df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0e0 = { + 0xb0e0, pci_device_0e11_b0e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b0e1 = { + 0xb0e1, pci_device_0e11_b0e1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b0e1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b123 = { + 0xb123, pci_device_0e11_b123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b134 = { + 0xb134, pci_device_0e11_b134, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b134, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b13c = { + 0xb13c, pci_device_0e11_b13c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b13c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b144 = { + 0xb144, pci_device_0e11_b144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b163 = { + 0xb163, pci_device_0e11_b163, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b163, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b164 = { + 0xb164, pci_device_0e11_b164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b178 = { + 0xb178, pci_device_0e11_b178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b1a4 = { + 0xb1a4, pci_device_0e11_b1a4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b1a4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b200 = { + 0xb200, pci_device_0e11_b200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b203 = { + 0xb203, pci_device_0e11_b203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_b204 = { + 0xb204, pci_device_0e11_b204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_b204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_f130 = { + 0xf130, pci_device_0e11_f130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_f130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_0e11_f150 = { + 0xf150, pci_device_0e11_f150, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_0e11_f150, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1000_0001 = { + 0x0001, pci_device_1000_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0002 = { + 0x0002, pci_device_1000_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0003 = { + 0x0003, pci_device_1000_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0004 = { + 0x0004, pci_device_1000_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0005 = { + 0x0005, pci_device_1000_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0006 = { + 0x0006, pci_device_1000_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000a = { + 0x000a, pci_device_1000_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000b = { + 0x000b, pci_device_1000_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000c = { + 0x000c, pci_device_1000_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000d = { + 0x000d, pci_device_1000_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_000f = { + 0x000f, pci_device_1000_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0010 = { + 0x0010, pci_device_1000_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0012 = { + 0x0012, pci_device_1000_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0013 = { + 0x0013, pci_device_1000_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0020 = { + 0x0020, pci_device_1000_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0021 = { + 0x0021, pci_device_1000_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0030 = { + 0x0030, pci_device_1000_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0031 = { + 0x0031, pci_device_1000_0031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0032 = { + 0x0032, pci_device_1000_0032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0033 = { + 0x0033, pci_device_1000_0033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0040 = { + 0x0040, pci_device_1000_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0041 = { + 0x0041, pci_device_1000_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0050 = { + 0x0050, pci_device_1000_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0054 = { + 0x0054, pci_device_1000_0054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0056 = { + 0x0056, pci_device_1000_0056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0058 = { + 0x0058, pci_device_1000_0058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_005a = { + 0x005a, pci_device_1000_005a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_005a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_005c = { + 0x005c, pci_device_1000_005c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_005c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_005e = { + 0x005e, pci_device_1000_005e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_005e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0060 = { + 0x0060, pci_device_1000_0060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0062 = { + 0x0062, pci_device_1000_0062, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0062, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_008f = { + 0x008f, pci_device_1000_008f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_008f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0407 = { + 0x0407, pci_device_1000_0407, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0407, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0408 = { + 0x0408, pci_device_1000_0408, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0408, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0409 = { + 0x0409, pci_device_1000_0409, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0409, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0411 = { + 0x0411, pci_device_1000_0411, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0411, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0413 = { + 0x0413, pci_device_1000_0413, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0413, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0621 = { + 0x0621, pci_device_1000_0621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0622 = { + 0x0622, pci_device_1000_0622, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0622, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0623 = { + 0x0623, pci_device_1000_0623, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0623, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0624 = { + 0x0624, pci_device_1000_0624, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0624, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0625 = { + 0x0625, pci_device_1000_0625, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0625, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0626 = { + 0x0626, pci_device_1000_0626, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0626, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0627 = { + 0x0627, pci_device_1000_0627, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0627, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0628 = { + 0x0628, pci_device_1000_0628, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0628, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0629 = { + 0x0629, pci_device_1000_0629, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0629, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0640 = { + 0x0640, pci_device_1000_0640, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0640, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0642 = { + 0x0642, pci_device_1000_0642, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0642, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0646 = { + 0x0646, pci_device_1000_0646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0701 = { + 0x0701, pci_device_1000_0701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0701, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0702 = { + 0x0702, pci_device_1000_0702, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0702, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0804 = { + 0x0804, pci_device_1000_0804, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0804, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0805 = { + 0x0805, pci_device_1000_0805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0806 = { + 0x0806, pci_device_1000_0806, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0806, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0807 = { + 0x0807, pci_device_1000_0807, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0807, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_0901 = { + 0x0901, pci_device_1000_0901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_0901, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_1000 = { + 0x1000, pci_device_1000_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1000_1960 = { + 0x1960, pci_device_1000_1960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1000_1960, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1001_0010 = { + 0x0010, pci_device_1001_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0011 = { + 0x0011, pci_device_1001_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0012 = { + 0x0012, pci_device_1001_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0013 = { + 0x0013, pci_device_1001_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0014 = { + 0x0014, pci_device_1001_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0015 = { + 0x0015, pci_device_1001_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0016 = { + 0x0016, pci_device_1001_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_0017 = { + 0x0017, pci_device_1001_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1001_9100 = { + 0x9100, pci_device_1001_9100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1001_9100, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1002_3150 = { + 0x3150, pci_device_1002_3150, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3150, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_3152 = { + 0x3152, pci_device_1002_3152, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3152, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_3154 = { + 0x3154, pci_device_1002_3154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3154, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_3e50 = { + 0x3e50, pci_device_1002_3e50, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3e50, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_3e54 = { + 0x3e54, pci_device_1002_3e54, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3e54, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_3e70 = { + 0x3e70, pci_device_1002_3e70, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_3e70, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4136 = { + 0x4136, pci_device_1002_4136, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4136, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4137 = { + 0x4137, pci_device_1002_4137, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4137, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4144 = { + 0x4144, pci_device_1002_4144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4145 = { + 0x4145, pci_device_1002_4145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4146 = { + 0x4146, pci_device_1002_4146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4147 = { + 0x4147, pci_device_1002_4147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4148 = { + 0x4148, pci_device_1002_4148, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4148, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4149 = { + 0x4149, pci_device_1002_4149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_414a = { + 0x414a, pci_device_1002_414a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_414a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_414b = { + 0x414b, pci_device_1002_414b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_414b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4150 = { + 0x4150, pci_device_1002_4150, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4150, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4151 = { + 0x4151, pci_device_1002_4151, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4151, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4152 = { + 0x4152, pci_device_1002_4152, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4152, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4153 = { + 0x4153, pci_device_1002_4153, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4153, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4154 = { + 0x4154, pci_device_1002_4154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4154, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4155 = { + 0x4155, pci_device_1002_4155, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4155, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4156 = { + 0x4156, pci_device_1002_4156, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4156, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4157 = { + 0x4157, pci_device_1002_4157, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4157, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4158 = { + 0x4158, pci_device_1002_4158, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4158, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4164 = { + 0x4164, pci_device_1002_4164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4165 = { + 0x4165, pci_device_1002_4165, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4165, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4166 = { + 0x4166, pci_device_1002_4166, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4166, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4168 = { + 0x4168, pci_device_1002_4168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4170 = { + 0x4170, pci_device_1002_4170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4171 = { + 0x4171, pci_device_1002_4171, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4171, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4172 = { + 0x4172, pci_device_1002_4172, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4172, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4173 = { + 0x4173, pci_device_1002_4173, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4173, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4237 = { + 0x4237, pci_device_1002_4237, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4237, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4242 = { + 0x4242, pci_device_1002_4242, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4242, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4243 = { + 0x4243, pci_device_1002_4243, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4243, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4336 = { + 0x4336, pci_device_1002_4336, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4336, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4337 = { + 0x4337, pci_device_1002_4337, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4337, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4341 = { + 0x4341, pci_device_1002_4341, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4341, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4345 = { + 0x4345, pci_device_1002_4345, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4345, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4347 = { + 0x4347, pci_device_1002_4347, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4347, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4348 = { + 0x4348, pci_device_1002_4348, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4348, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4349 = { + 0x4349, pci_device_1002_4349, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4349, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_434d = { + 0x434d, pci_device_1002_434d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_434d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4353 = { + 0x4353, pci_device_1002_4353, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4353, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4354 = { + 0x4354, pci_device_1002_4354, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4354, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4358 = { + 0x4358, pci_device_1002_4358, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4358, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4363 = { + 0x4363, pci_device_1002_4363, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4363, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_436e = { + 0x436e, pci_device_1002_436e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_436e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4370 = { + 0x4370, pci_device_1002_4370, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4370, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4371 = { + 0x4371, pci_device_1002_4371, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4371, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4372 = { + 0x4372, pci_device_1002_4372, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4372, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4373 = { + 0x4373, pci_device_1002_4373, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4373, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4374 = { + 0x4374, pci_device_1002_4374, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4374, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4375 = { + 0x4375, pci_device_1002_4375, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4375, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4376 = { + 0x4376, pci_device_1002_4376, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4376, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4377 = { + 0x4377, pci_device_1002_4377, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4377, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4378 = { + 0x4378, pci_device_1002_4378, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4378, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4379 = { + 0x4379, pci_device_1002_4379, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4379, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_437a = { + 0x437a, pci_device_1002_437a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_437a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_437b = { + 0x437b, pci_device_1002_437b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_437b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4380 = { + 0x4380, pci_device_1002_4380, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4380, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4381 = { + 0x4381, pci_device_1002_4381, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4381, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4382 = { + 0x4382, pci_device_1002_4382, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4382, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4383 = { + 0x4383, pci_device_1002_4383, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4383, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4384 = { + 0x4384, pci_device_1002_4384, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4384, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4385 = { + 0x4385, pci_device_1002_4385, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4385, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4386 = { + 0x4386, pci_device_1002_4386, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4386, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4387 = { + 0x4387, pci_device_1002_4387, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4387, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4388 = { + 0x4388, pci_device_1002_4388, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4388, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4389 = { + 0x4389, pci_device_1002_4389, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4389, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_438a = { + 0x438a, pci_device_1002_438a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_438a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_438b = { + 0x438b, pci_device_1002_438b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_438b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_438c = { + 0x438c, pci_device_1002_438c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_438c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_438d = { + 0x438d, pci_device_1002_438d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_438d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_438e = { + 0x438e, pci_device_1002_438e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_438e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4437 = { + 0x4437, pci_device_1002_4437, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4437, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4554 = { + 0x4554, pci_device_1002_4554, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4554, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4654 = { + 0x4654, pci_device_1002_4654, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4654, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4742 = { + 0x4742, pci_device_1002_4742, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4742, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4744 = { + 0x4744, pci_device_1002_4744, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4744, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4747 = { + 0x4747, pci_device_1002_4747, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4747, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4749 = { + 0x4749, pci_device_1002_4749, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4749, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_474c = { + 0x474c, pci_device_1002_474c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_474c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_474d = { + 0x474d, pci_device_1002_474d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_474d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_474e = { + 0x474e, pci_device_1002_474e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_474e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_474f = { + 0x474f, pci_device_1002_474f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_474f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4750 = { + 0x4750, pci_device_1002_4750, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4750, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4751 = { + 0x4751, pci_device_1002_4751, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4751, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4752 = { + 0x4752, pci_device_1002_4752, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4752, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4753 = { + 0x4753, pci_device_1002_4753, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4753, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4754 = { + 0x4754, pci_device_1002_4754, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4754, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4755 = { + 0x4755, pci_device_1002_4755, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4755, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4756 = { + 0x4756, pci_device_1002_4756, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4756, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4757 = { + 0x4757, pci_device_1002_4757, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4757, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4758 = { + 0x4758, pci_device_1002_4758, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4758, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4759 = { + 0x4759, pci_device_1002_4759, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4759, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_475a = { + 0x475a, pci_device_1002_475a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_475a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4964 = { + 0x4964, pci_device_1002_4964, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4964, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4965 = { + 0x4965, pci_device_1002_4965, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4965, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4966 = { + 0x4966, pci_device_1002_4966, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4966, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4967 = { + 0x4967, pci_device_1002_4967, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4967, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_496e = { + 0x496e, pci_device_1002_496e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_496e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a48 = { + 0x4a48, pci_device_1002_4a48, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a48, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a49 = { + 0x4a49, pci_device_1002_4a49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a4a = { + 0x4a4a, pci_device_1002_4a4a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a4a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a4b = { + 0x4a4b, pci_device_1002_4a4b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a4b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a4c = { + 0x4a4c, pci_device_1002_4a4c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a4c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a4d = { + 0x4a4d, pci_device_1002_4a4d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a4d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a4e = { + 0x4a4e, pci_device_1002_4a4e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a4e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a50 = { + 0x4a50, pci_device_1002_4a50, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a50, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a54 = { + 0x4a54, pci_device_1002_4a54, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a54, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a69 = { + 0x4a69, pci_device_1002_4a69, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a69, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a6a = { + 0x4a6a, pci_device_1002_4a6a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a6a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a6b = { + 0x4a6b, pci_device_1002_4a6b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a6b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a70 = { + 0x4a70, pci_device_1002_4a70, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a70, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4a74 = { + 0x4a74, pci_device_1002_4a74, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4a74, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b49 = { + 0x4b49, pci_device_1002_4b49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b4b = { + 0x4b4b, pci_device_1002_4b4b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b4b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b4c = { + 0x4b4c, pci_device_1002_4b4c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b4c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b69 = { + 0x4b69, pci_device_1002_4b69, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b69, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b6b = { + 0x4b6b, pci_device_1002_4b6b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b6b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4b6c = { + 0x4b6c, pci_device_1002_4b6c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4b6c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c42 = { + 0x4c42, pci_device_1002_4c42, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c42, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c44 = { + 0x4c44, pci_device_1002_4c44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c45 = { + 0x4c45, pci_device_1002_4c45, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c45, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c46 = { + 0x4c46, pci_device_1002_4c46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c47 = { + 0x4c47, pci_device_1002_4c47, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c47, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c49 = { + 0x4c49, pci_device_1002_4c49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c4d = { + 0x4c4d, pci_device_1002_4c4d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c4d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c4e = { + 0x4c4e, pci_device_1002_4c4e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c4e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c50 = { + 0x4c50, pci_device_1002_4c50, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c50, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c51 = { + 0x4c51, pci_device_1002_4c51, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c51, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c52 = { + 0x4c52, pci_device_1002_4c52, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c52, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c53 = { + 0x4c53, pci_device_1002_4c53, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c53, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c54 = { + 0x4c54, pci_device_1002_4c54, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c54, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c57 = { + 0x4c57, pci_device_1002_4c57, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c57, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c58 = { + 0x4c58, pci_device_1002_4c58, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c58, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c59 = { + 0x4c59, pci_device_1002_4c59, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c59, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c5a = { + 0x4c5a, pci_device_1002_4c5a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c5a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c64 = { + 0x4c64, pci_device_1002_4c64, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c64, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c65 = { + 0x4c65, pci_device_1002_4c65, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c65, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c66 = { + 0x4c66, pci_device_1002_4c66, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c66, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c67 = { + 0x4c67, pci_device_1002_4c67, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c67, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4c6e = { + 0x4c6e, pci_device_1002_4c6e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4c6e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4d46 = { + 0x4d46, pci_device_1002_4d46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4d46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4d4c = { + 0x4d4c, pci_device_1002_4d4c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4d4c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e44 = { + 0x4e44, pci_device_1002_4e44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e45 = { + 0x4e45, pci_device_1002_4e45, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e45, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e46 = { + 0x4e46, pci_device_1002_4e46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e47 = { + 0x4e47, pci_device_1002_4e47, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e47, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e48 = { + 0x4e48, pci_device_1002_4e48, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e48, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e49 = { + 0x4e49, pci_device_1002_4e49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e4a = { + 0x4e4a, pci_device_1002_4e4a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e4a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e4b = { + 0x4e4b, pci_device_1002_4e4b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e4b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e50 = { + 0x4e50, pci_device_1002_4e50, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e50, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e51 = { + 0x4e51, pci_device_1002_4e51, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e51, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e52 = { + 0x4e52, pci_device_1002_4e52, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e52, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e53 = { + 0x4e53, pci_device_1002_4e53, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e53, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e54 = { + 0x4e54, pci_device_1002_4e54, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e54, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e56 = { + 0x4e56, pci_device_1002_4e56, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e56, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e64 = { + 0x4e64, pci_device_1002_4e64, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e64, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e65 = { + 0x4e65, pci_device_1002_4e65, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e65, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e66 = { + 0x4e66, pci_device_1002_4e66, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e66, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e67 = { + 0x4e67, pci_device_1002_4e67, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e67, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e68 = { + 0x4e68, pci_device_1002_4e68, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e68, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e69 = { + 0x4e69, pci_device_1002_4e69, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e69, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e6a = { + 0x4e6a, pci_device_1002_4e6a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e6a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4e71 = { + 0x4e71, pci_device_1002_4e71, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4e71, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4f72 = { + 0x4f72, pci_device_1002_4f72, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4f72, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_4f73 = { + 0x4f73, pci_device_1002_4f73, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_4f73, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5041 = { + 0x5041, pci_device_1002_5041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5042 = { + 0x5042, pci_device_1002_5042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5043 = { + 0x5043, pci_device_1002_5043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5044 = { + 0x5044, pci_device_1002_5044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5045 = { + 0x5045, pci_device_1002_5045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5046 = { + 0x5046, pci_device_1002_5046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5047 = { + 0x5047, pci_device_1002_5047, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5047, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5048 = { + 0x5048, pci_device_1002_5048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5049 = { + 0x5049, pci_device_1002_5049, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5049, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504a = { + 0x504a, pci_device_1002_504a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504b = { + 0x504b, pci_device_1002_504b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504c = { + 0x504c, pci_device_1002_504c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504d = { + 0x504d, pci_device_1002_504d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504e = { + 0x504e, pci_device_1002_504e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_504f = { + 0x504f, pci_device_1002_504f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_504f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5050 = { + 0x5050, pci_device_1002_5050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5051 = { + 0x5051, pci_device_1002_5051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5052 = { + 0x5052, pci_device_1002_5052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5053 = { + 0x5053, pci_device_1002_5053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5054 = { + 0x5054, pci_device_1002_5054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5055 = { + 0x5055, pci_device_1002_5055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5056 = { + 0x5056, pci_device_1002_5056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5057 = { + 0x5057, pci_device_1002_5057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5058 = { + 0x5058, pci_device_1002_5058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5144 = { + 0x5144, pci_device_1002_5144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5145 = { + 0x5145, pci_device_1002_5145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5146 = { + 0x5146, pci_device_1002_5146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5147 = { + 0x5147, pci_device_1002_5147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5148 = { + 0x5148, pci_device_1002_5148, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5148, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5149 = { + 0x5149, pci_device_1002_5149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514a = { + 0x514a, pci_device_1002_514a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514b = { + 0x514b, pci_device_1002_514b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514c = { + 0x514c, pci_device_1002_514c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514d = { + 0x514d, pci_device_1002_514d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514e = { + 0x514e, pci_device_1002_514e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_514f = { + 0x514f, pci_device_1002_514f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_514f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5154 = { + 0x5154, pci_device_1002_5154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5154, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5155 = { + 0x5155, pci_device_1002_5155, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5155, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5157 = { + 0x5157, pci_device_1002_5157, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5157, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5158 = { + 0x5158, pci_device_1002_5158, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5158, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5159 = { + 0x5159, pci_device_1002_5159, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5159, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_515a = { + 0x515a, pci_device_1002_515a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_515a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_515e = { + 0x515e, pci_device_1002_515e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_515e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_515f = { + 0x515f, pci_device_1002_515f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_515f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5168 = { + 0x5168, pci_device_1002_5168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5169 = { + 0x5169, pci_device_1002_5169, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5169, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_516a = { + 0x516a, pci_device_1002_516a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_516a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_516b = { + 0x516b, pci_device_1002_516b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_516b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_516c = { + 0x516c, pci_device_1002_516c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_516c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5245 = { + 0x5245, pci_device_1002_5245, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5245, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5246 = { + 0x5246, pci_device_1002_5246, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5246, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5247 = { + 0x5247, pci_device_1002_5247, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5247, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_524b = { + 0x524b, pci_device_1002_524b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_524b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_524c = { + 0x524c, pci_device_1002_524c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_524c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5345 = { + 0x5345, pci_device_1002_5345, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5345, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5346 = { + 0x5346, pci_device_1002_5346, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5346, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5347 = { + 0x5347, pci_device_1002_5347, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5347, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5348 = { + 0x5348, pci_device_1002_5348, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5348, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_534b = { + 0x534b, pci_device_1002_534b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_534b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_534c = { + 0x534c, pci_device_1002_534c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_534c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_534d = { + 0x534d, pci_device_1002_534d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_534d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_534e = { + 0x534e, pci_device_1002_534e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_534e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5354 = { + 0x5354, pci_device_1002_5354, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5354, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5446 = { + 0x5446, pci_device_1002_5446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_544c = { + 0x544c, pci_device_1002_544c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_544c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5452 = { + 0x5452, pci_device_1002_5452, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5452, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5453 = { + 0x5453, pci_device_1002_5453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5454 = { + 0x5454, pci_device_1002_5454, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5454, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5455 = { + 0x5455, pci_device_1002_5455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5460 = { + 0x5460, pci_device_1002_5460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5462 = { + 0x5462, pci_device_1002_5462, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5462, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5464 = { + 0x5464, pci_device_1002_5464, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5464, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5548 = { + 0x5548, pci_device_1002_5548, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5548, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5549 = { + 0x5549, pci_device_1002_5549, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5549, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_554a = { + 0x554a, pci_device_1002_554a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_554a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_554b = { + 0x554b, pci_device_1002_554b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_554b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_554d = { + 0x554d, pci_device_1002_554d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_554d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_554f = { + 0x554f, pci_device_1002_554f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_554f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5550 = { + 0x5550, pci_device_1002_5550, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5550, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5551 = { + 0x5551, pci_device_1002_5551, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5551, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5552 = { + 0x5552, pci_device_1002_5552, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5552, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5554 = { + 0x5554, pci_device_1002_5554, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5554, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5569 = { + 0x5569, pci_device_1002_5569, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5569, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_556b = { + 0x556b, pci_device_1002_556b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_556b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_556d = { + 0x556d, pci_device_1002_556d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_556d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_556f = { + 0x556f, pci_device_1002_556f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_556f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5571 = { + 0x5571, pci_device_1002_5571, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5571, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_564a = { + 0x564a, pci_device_1002_564a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_564a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_564b = { + 0x564b, pci_device_1002_564b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_564b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_564f = { + 0x564f, pci_device_1002_564f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_564f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5652 = { + 0x5652, pci_device_1002_5652, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5652, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5653 = { + 0x5653, pci_device_1002_5653, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5653, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5654 = { + 0x5654, pci_device_1002_5654, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5654, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5655 = { + 0x5655, pci_device_1002_5655, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5655, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5656 = { + 0x5656, pci_device_1002_5656, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5656, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5830 = { + 0x5830, pci_device_1002_5830, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5830, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5831 = { + 0x5831, pci_device_1002_5831, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5831, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5832 = { + 0x5832, pci_device_1002_5832, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5832, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5833 = { + 0x5833, pci_device_1002_5833, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5833, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5834 = { + 0x5834, pci_device_1002_5834, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5834, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5835 = { + 0x5835, pci_device_1002_5835, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5835, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5838 = { + 0x5838, pci_device_1002_5838, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5838, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5940 = { + 0x5940, pci_device_1002_5940, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5940, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5941 = { + 0x5941, pci_device_1002_5941, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5941, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5944 = { + 0x5944, pci_device_1002_5944, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5944, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5950 = { + 0x5950, pci_device_1002_5950, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5950, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5951 = { + 0x5951, pci_device_1002_5951, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5951, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5954 = { + 0x5954, pci_device_1002_5954, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5954, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5955 = { + 0x5955, pci_device_1002_5955, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5955, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5960 = { + 0x5960, pci_device_1002_5960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5960, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5961 = { + 0x5961, pci_device_1002_5961, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5961, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5962 = { + 0x5962, pci_device_1002_5962, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5962, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5964 = { + 0x5964, pci_device_1002_5964, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5964, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5969 = { + 0x5969, pci_device_1002_5969, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5969, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5974 = { + 0x5974, pci_device_1002_5974, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5974, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5975 = { + 0x5975, pci_device_1002_5975, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5975, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a33 = { + 0x5a33, pci_device_1002_5a33, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a33, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a34 = { + 0x5a34, pci_device_1002_5a34, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a34, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a36 = { + 0x5a36, pci_device_1002_5a36, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a36, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a38 = { + 0x5a38, pci_device_1002_5a38, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a38, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a39 = { + 0x5a39, pci_device_1002_5a39, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a39, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a3f = { + 0x5a3f, pci_device_1002_5a3f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a3f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a41 = { + 0x5a41, pci_device_1002_5a41, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a41, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a42 = { + 0x5a42, pci_device_1002_5a42, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a42, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a61 = { + 0x5a61, pci_device_1002_5a61, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a61, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5a62 = { + 0x5a62, pci_device_1002_5a62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5a62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b60 = { + 0x5b60, pci_device_1002_5b60, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b60, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b62 = { + 0x5b62, pci_device_1002_5b62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b63 = { + 0x5b63, pci_device_1002_5b63, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b63, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b64 = { + 0x5b64, pci_device_1002_5b64, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b64, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b65 = { + 0x5b65, pci_device_1002_5b65, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b65, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b70 = { + 0x5b70, pci_device_1002_5b70, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b70, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b72 = { + 0x5b72, pci_device_1002_5b72, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b72, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b73 = { + 0x5b73, pci_device_1002_5b73, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b73, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5b74 = { + 0x5b74, pci_device_1002_5b74, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5b74, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5c61 = { + 0x5c61, pci_device_1002_5c61, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5c61, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5c63 = { + 0x5c63, pci_device_1002_5c63, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5c63, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d44 = { + 0x5d44, pci_device_1002_5d44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d48 = { + 0x5d48, pci_device_1002_5d48, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d48, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d49 = { + 0x5d49, pci_device_1002_5d49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d4a = { + 0x5d4a, pci_device_1002_5d4a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d4a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d4d = { + 0x5d4d, pci_device_1002_5d4d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d4d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d4f = { + 0x5d4f, pci_device_1002_5d4f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d4f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d52 = { + 0x5d52, pci_device_1002_5d52, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d52, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d57 = { + 0x5d57, pci_device_1002_5d57, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d57, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d6d = { + 0x5d6d, pci_device_1002_5d6d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d6d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d6f = { + 0x5d6f, pci_device_1002_5d6f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d6f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d72 = { + 0x5d72, pci_device_1002_5d72, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d72, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5d77 = { + 0x5d77, pci_device_1002_5d77, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5d77, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e48 = { + 0x5e48, pci_device_1002_5e48, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e48, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e49 = { + 0x5e49, pci_device_1002_5e49, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e49, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e4a = { + 0x5e4a, pci_device_1002_5e4a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e4a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e4b = { + 0x5e4b, pci_device_1002_5e4b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e4b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e4c = { + 0x5e4c, pci_device_1002_5e4c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e4c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e4d = { + 0x5e4d, pci_device_1002_5e4d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e4d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e4f = { + 0x5e4f, pci_device_1002_5e4f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e4f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e6b = { + 0x5e6b, pci_device_1002_5e6b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e6b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5e6d = { + 0x5e6d, pci_device_1002_5e6d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5e6d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_5f57 = { + 0x5f57, pci_device_1002_5f57, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_5f57, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_700f = { + 0x700f, pci_device_1002_700f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_700f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7010 = { + 0x7010, pci_device_1002_7010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7100 = { + 0x7100, pci_device_1002_7100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7102 = { + 0x7102, pci_device_1002_7102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7103 = { + 0x7103, pci_device_1002_7103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7104 = { + 0x7104, pci_device_1002_7104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7105 = { + 0x7105, pci_device_1002_7105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7106 = { + 0x7106, pci_device_1002_7106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7108 = { + 0x7108, pci_device_1002_7108, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7108, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7109 = { + 0x7109, pci_device_1002_7109, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7109, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_710a = { + 0x710a, pci_device_1002_710a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_710a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_710b = { + 0x710b, pci_device_1002_710b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_710b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_710c = { + 0x710c, pci_device_1002_710c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_710c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7120 = { + 0x7120, pci_device_1002_7120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7124 = { + 0x7124, pci_device_1002_7124, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7124, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7129 = { + 0x7129, pci_device_1002_7129, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7129, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7140 = { + 0x7140, pci_device_1002_7140, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7140, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7142 = { + 0x7142, pci_device_1002_7142, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7142, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7145 = { + 0x7145, pci_device_1002_7145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7146 = { + 0x7146, pci_device_1002_7146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7149 = { + 0x7149, pci_device_1002_7149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_714a = { + 0x714a, pci_device_1002_714a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_714a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_714b = { + 0x714b, pci_device_1002_714b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_714b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_714c = { + 0x714c, pci_device_1002_714c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_714c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_714d = { + 0x714d, pci_device_1002_714d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_714d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_714e = { + 0x714e, pci_device_1002_714e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_714e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7152 = { + 0x7152, pci_device_1002_7152, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7152, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_715e = { + 0x715e, pci_device_1002_715e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_715e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7162 = { + 0x7162, pci_device_1002_7162, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7162, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7166 = { + 0x7166, pci_device_1002_7166, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7166, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7172 = { + 0x7172, pci_device_1002_7172, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7172, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7180 = { + 0x7180, pci_device_1002_7180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7181 = { + 0x7181, pci_device_1002_7181, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7181, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_71a0 = { + 0x71a0, pci_device_1002_71a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_71a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_71a1 = { + 0x71a1, pci_device_1002_71a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_71a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_71c0 = { + 0x71c0, pci_device_1002_71c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_71c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_71c2 = { + 0x71c2, pci_device_1002_71c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_71c2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_71c4 = { + 0x71c4, pci_device_1002_71c4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_71c4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_71c5 = { + 0x71c5, pci_device_1002_71c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_71c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_71c6 = { + 0x71c6, pci_device_1002_71c6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_71c6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_71ce = { + 0x71ce, pci_device_1002_71ce, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_71ce, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_71d5 = { + 0x71d5, pci_device_1002_71d5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_71d5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_71d6 = { + 0x71d6, pci_device_1002_71d6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_71d6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_71de = { + 0x71de, pci_device_1002_71de, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_71de, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_71e0 = { + 0x71e0, pci_device_1002_71e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_71e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_71e2 = { + 0x71e2, pci_device_1002_71e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_71e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7240 = { + 0x7240, pci_device_1002_7240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7241 = { + 0x7241, pci_device_1002_7241, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7241, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7242 = { + 0x7242, pci_device_1002_7242, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7242, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7243 = { + 0x7243, pci_device_1002_7243, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7243, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7244 = { + 0x7244, pci_device_1002_7244, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7244, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7245 = { + 0x7245, pci_device_1002_7245, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7245, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7246 = { + 0x7246, pci_device_1002_7246, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7246, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7247 = { + 0x7247, pci_device_1002_7247, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7247, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7248 = { + 0x7248, pci_device_1002_7248, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7248, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7249 = { + 0x7249, pci_device_1002_7249, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7249, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_724a = { + 0x724a, pci_device_1002_724a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_724a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_724b = { + 0x724b, pci_device_1002_724b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_724b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_724c = { + 0x724c, pci_device_1002_724c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_724c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_724d = { + 0x724d, pci_device_1002_724d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_724d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_724e = { + 0x724e, pci_device_1002_724e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_724e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7269 = { + 0x7269, pci_device_1002_7269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_726e = { + 0x726e, pci_device_1002_726e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_726e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7833 = { + 0x7833, pci_device_1002_7833, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7833, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7834 = { + 0x7834, pci_device_1002_7834, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7834, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7835 = { + 0x7835, pci_device_1002_7835, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7835, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7838 = { + 0x7838, pci_device_1002_7838, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7838, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_7c37 = { + 0x7c37, pci_device_1002_7c37, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_7c37, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_cab0 = { + 0xcab0, pci_device_1002_cab0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_cab0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_cab2 = { + 0xcab2, pci_device_1002_cab2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_cab2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_cab3 = { + 0xcab3, pci_device_1002_cab3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_cab3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1002_cbb2 = { + 0xcbb2, pci_device_1002_cbb2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1002_cbb2, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1003_0201 = { + 0x0201, pci_device_1003_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1003_0201, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1004_0005 = { + 0x0005, pci_device_1004_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0006 = { + 0x0006, pci_device_1004_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0007 = { + 0x0007, pci_device_1004_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0008 = { + 0x0008, pci_device_1004_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0009 = { + 0x0009, pci_device_1004_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_000c = { + 0x000c, pci_device_1004_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_000d = { + 0x000d, pci_device_1004_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0101 = { + 0x0101, pci_device_1004_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0102 = { + 0x0102, pci_device_1004_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0103 = { + 0x0103, pci_device_1004_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0104 = { + 0x0104, pci_device_1004_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0105 = { + 0x0105, pci_device_1004_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0200 = { + 0x0200, pci_device_1004_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0280 = { + 0x0280, pci_device_1004_0280, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0280, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0304 = { + 0x0304, pci_device_1004_0304, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0304, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0305 = { + 0x0305, pci_device_1004_0305, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0305, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0306 = { + 0x0306, pci_device_1004_0306, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0306, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0307 = { + 0x0307, pci_device_1004_0307, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0307, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0308 = { + 0x0308, pci_device_1004_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0702 = { + 0x0702, pci_device_1004_0702, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0702, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1004_0703 = { + 0x0703, pci_device_1004_0703, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1004_0703, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1005_2064 = { + 0x2064, pci_device_1005_2064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2128 = { + 0x2128, pci_device_1005_2128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2128, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2301 = { + 0x2301, pci_device_1005_2301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2302 = { + 0x2302, pci_device_1005_2302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2364 = { + 0x2364, pci_device_1005_2364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2464 = { + 0x2464, pci_device_1005_2464, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2464, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1005_2501 = { + 0x2501, pci_device_1005_2501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1005_2501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0001 = { + 0x0001, pci_device_100b_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0002 = { + 0x0002, pci_device_100b_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_000e = { + 0x000e, pci_device_100b_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_000e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_000f = { + 0x000f, pci_device_100b_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0011 = { + 0x0011, pci_device_100b_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0012 = { + 0x0012, pci_device_100b_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0020 = { + 0x0020, pci_device_100b_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0021 = { + 0x0021, pci_device_100b_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0022 = { + 0x0022, pci_device_100b_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0028 = { + 0x0028, pci_device_100b_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_002a = { + 0x002a, pci_device_100b_002a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_002a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_002b = { + 0x002b, pci_device_100b_002b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_002b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_002d = { + 0x002d, pci_device_100b_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_002e = { + 0x002e, pci_device_100b_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_002f = { + 0x002f, pci_device_100b_002f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_002f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0030 = { + 0x0030, pci_device_100b_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0035 = { + 0x0035, pci_device_100b_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0500 = { + 0x0500, pci_device_100b_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0501 = { + 0x0501, pci_device_100b_0501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0502 = { + 0x0502, pci_device_100b_0502, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0502, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0503 = { + 0x0503, pci_device_100b_0503, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0503, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0504 = { + 0x0504, pci_device_100b_0504, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0504, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0505 = { + 0x0505, pci_device_100b_0505, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0505, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0510 = { + 0x0510, pci_device_100b_0510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0511 = { + 0x0511, pci_device_100b_0511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_0515 = { + 0x0515, pci_device_100b_0515, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_0515, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100b_d001 = { + 0xd001, pci_device_100b_d001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100b_d001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3202 = { + 0x3202, pci_device_100c_3202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3205 = { + 0x3205, pci_device_100c_3205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3206 = { + 0x3206, pci_device_100c_3206, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3206, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3207 = { + 0x3207, pci_device_100c_3207, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3207, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_3208 = { + 0x3208, pci_device_100c_3208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_3208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100c_4702 = { + 0x4702, pci_device_100c_4702, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100c_4702, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100e_9000 = { + 0x9000, pci_device_100e_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100e_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100e_9001 = { + 0x9001, pci_device_100e_9001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100e_9001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100e_9002 = { + 0x9002, pci_device_100e_9002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100e_9002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_100e_9100 = { + 0x9100, pci_device_100e_9100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_100e_9100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0001 = { + 0x0001, pci_device_1011_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0002 = { + 0x0002, pci_device_1011_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0004 = { + 0x0004, pci_device_1011_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0007 = { + 0x0007, pci_device_1011_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0008 = { + 0x0008, pci_device_1011_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0009 = { + 0x0009, pci_device_1011_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_000a = { + 0x000a, pci_device_1011_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_000d = { + 0x000d, pci_device_1011_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_000f = { + 0x000f, pci_device_1011_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0014 = { + 0x0014, pci_device_1011_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0016 = { + 0x0016, pci_device_1011_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0017 = { + 0x0017, pci_device_1011_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0019 = { + 0x0019, pci_device_1011_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_001a = { + 0x001a, pci_device_1011_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0021 = { + 0x0021, pci_device_1011_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0022 = { + 0x0022, pci_device_1011_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0023 = { + 0x0023, pci_device_1011_0023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0024 = { + 0x0024, pci_device_1011_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0025 = { + 0x0025, pci_device_1011_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0026 = { + 0x0026, pci_device_1011_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0034 = { + 0x0034, pci_device_1011_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0045 = { + 0x0045, pci_device_1011_0045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_0046 = { + 0x0046, pci_device_1011_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1011_1065 = { + 0x1065, pci_device_1011_1065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1011_1065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_0038 = { + 0x0038, pci_device_1013_0038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_0038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_0040 = { + 0x0040, pci_device_1013_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_004c = { + 0x004c, pci_device_1013_004c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_004c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00a0 = { + 0x00a0, pci_device_1013_00a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00a2 = { + 0x00a2, pci_device_1013_00a2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00a2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00a4 = { + 0x00a4, pci_device_1013_00a4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00a4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00a8 = { + 0x00a8, pci_device_1013_00a8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00a8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00ac = { + 0x00ac, pci_device_1013_00ac, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00ac, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00b0 = { + 0x00b0, pci_device_1013_00b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00b8 = { + 0x00b8, pci_device_1013_00b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00bc = { + 0x00bc, pci_device_1013_00bc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00bc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d0 = { + 0x00d0, pci_device_1013_00d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d2 = { + 0x00d2, pci_device_1013_00d2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d4 = { + 0x00d4, pci_device_1013_00d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d5 = { + 0x00d5, pci_device_1013_00d5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00d6 = { + 0x00d6, pci_device_1013_00d6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00d6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_00e8 = { + 0x00e8, pci_device_1013_00e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_00e8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1100 = { + 0x1100, pci_device_1013_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1110 = { + 0x1110, pci_device_1013_1110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1112 = { + 0x1112, pci_device_1013_1112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1113 = { + 0x1113, pci_device_1013_1113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1200 = { + 0x1200, pci_device_1013_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1202 = { + 0x1202, pci_device_1013_1202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_1204 = { + 0x1204, pci_device_1013_1204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_1204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_4000 = { + 0x4000, pci_device_1013_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_4400 = { + 0x4400, pci_device_1013_4400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_4400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_6001 = { + 0x6001, pci_device_1013_6001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_6001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_6003 = { + 0x6003, pci_device_1013_6003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_6003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_6004 = { + 0x6004, pci_device_1013_6004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_6004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1013_6005 = { + 0x6005, pci_device_1013_6005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1013_6005, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1014_0002 = { + 0x0002, pci_device_1014_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0005 = { + 0x0005, pci_device_1014_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0007 = { + 0x0007, pci_device_1014_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_000a = { + 0x000a, pci_device_1014_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0017 = { + 0x0017, pci_device_1014_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0018 = { + 0x0018, pci_device_1014_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_001b = { + 0x001b, pci_device_1014_001b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_001b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_001c = { + 0x001c, pci_device_1014_001c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_001c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_001d = { + 0x001d, pci_device_1014_001d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_001d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0020 = { + 0x0020, pci_device_1014_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0022 = { + 0x0022, pci_device_1014_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_002d = { + 0x002d, pci_device_1014_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_002e = { + 0x002e, pci_device_1014_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0031 = { + 0x0031, pci_device_1014_0031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0036 = { + 0x0036, pci_device_1014_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0037 = { + 0x0037, pci_device_1014_0037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_003a = { + 0x003a, pci_device_1014_003a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_003a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_003c = { + 0x003c, pci_device_1014_003c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_003c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_003e = { + 0x003e, pci_device_1014_003e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_003e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0045 = { + 0x0045, pci_device_1014_0045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0046 = { + 0x0046, pci_device_1014_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0047 = { + 0x0047, pci_device_1014_0047, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0047, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0048 = { + 0x0048, pci_device_1014_0048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0049 = { + 0x0049, pci_device_1014_0049, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0049, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_004e = { + 0x004e, pci_device_1014_004e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_004e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_004f = { + 0x004f, pci_device_1014_004f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_004f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0050 = { + 0x0050, pci_device_1014_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0053 = { + 0x0053, pci_device_1014_0053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0054 = { + 0x0054, pci_device_1014_0054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0057 = { + 0x0057, pci_device_1014_0057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0058 = { + 0x0058, pci_device_1014_0058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_005c = { + 0x005c, pci_device_1014_005c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_005c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_005e = { + 0x005e, pci_device_1014_005e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_005e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_007c = { + 0x007c, pci_device_1014_007c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_007c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_007d = { + 0x007d, pci_device_1014_007d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_007d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_008b = { + 0x008b, pci_device_1014_008b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_008b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_008e = { + 0x008e, pci_device_1014_008e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_008e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0090 = { + 0x0090, pci_device_1014_0090, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0090, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0091 = { + 0x0091, pci_device_1014_0091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0095 = { + 0x0095, pci_device_1014_0095, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0095, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0096 = { + 0x0096, pci_device_1014_0096, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0096, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_009f = { + 0x009f, pci_device_1014_009f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_009f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00a5 = { + 0x00a5, pci_device_1014_00a5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00a5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00a6 = { + 0x00a6, pci_device_1014_00a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00b7 = { + 0x00b7, pci_device_1014_00b7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00b7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00b8 = { + 0x00b8, pci_device_1014_00b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00be = { + 0x00be, pci_device_1014_00be, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00be, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00dc = { + 0x00dc, pci_device_1014_00dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00dc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_00fc = { + 0x00fc, pci_device_1014_00fc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_00fc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0104 = { + 0x0104, pci_device_1014_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0105 = { + 0x0105, pci_device_1014_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_010f = { + 0x010f, pci_device_1014_010f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_010f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0142 = { + 0x0142, pci_device_1014_0142, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0142, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0144 = { + 0x0144, pci_device_1014_0144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0156 = { + 0x0156, pci_device_1014_0156, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0156, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_015e = { + 0x015e, pci_device_1014_015e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_015e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0160 = { + 0x0160, pci_device_1014_0160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0160, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_016e = { + 0x016e, pci_device_1014_016e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_016e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0170 = { + 0x0170, pci_device_1014_0170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_017d = { + 0x017d, pci_device_1014_017d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_017d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0180 = { + 0x0180, pci_device_1014_0180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0188 = { + 0x0188, pci_device_1014_0188, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0188, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_01a7 = { + 0x01a7, pci_device_1014_01a7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_01a7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_01bd = { + 0x01bd, pci_device_1014_01bd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_01bd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_01c1 = { + 0x01c1, pci_device_1014_01c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_01c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_01e6 = { + 0x01e6, pci_device_1014_01e6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_01e6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_01ff = { + 0x01ff, pci_device_1014_01ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_01ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0219 = { + 0x0219, pci_device_1014_0219, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0219, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_021b = { + 0x021b, pci_device_1014_021b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_021b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_021c = { + 0x021c, pci_device_1014_021c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_021c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0233 = { + 0x0233, pci_device_1014_0233, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0233, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0266 = { + 0x0266, pci_device_1014_0266, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0266, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0268 = { + 0x0268, pci_device_1014_0268, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0268, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0269 = { + 0x0269, pci_device_1014_0269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_028c = { + 0x028c, pci_device_1014_028c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_028c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_02a1 = { + 0x02a1, pci_device_1014_02a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_02a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_02bd = { + 0x02bd, pci_device_1014_02bd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_02bd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0302 = { + 0x0302, pci_device_1014_0302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0308 = { + 0x0308, pci_device_1014_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_0314 = { + 0x0314, pci_device_1014_0314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_0314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_3022 = { + 0x3022, pci_device_1014_3022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_3022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_4022 = { + 0x4022, pci_device_1014_4022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_4022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1014_ffff = { + 0xffff, pci_device_1014_ffff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1014_ffff, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1017_5343 = { + 0x5343, pci_device_1017_5343, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1017_5343, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_101a_0005 = { + 0x0005, pci_device_101a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101a_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_101c_0193 = { + 0x0193, pci_device_101c_0193, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_0193, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_0196 = { + 0x0196, pci_device_101c_0196, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_0196, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_0197 = { + 0x0197, pci_device_101c_0197, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_0197, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_0296 = { + 0x0296, pci_device_101c_0296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_0296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_3193 = { + 0x3193, pci_device_101c_3193, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_3193, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_3197 = { + 0x3197, pci_device_101c_3197, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_3197, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_3296 = { + 0x3296, pci_device_101c_3296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_3296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_4296 = { + 0x4296, pci_device_101c_4296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_4296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_9710 = { + 0x9710, pci_device_101c_9710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_9710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_9712 = { + 0x9712, pci_device_101c_9712, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_9712, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101c_c24a = { + 0xc24a, pci_device_101c_c24a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101c_c24a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_101e_0009 = { + 0x0009, pci_device_101e_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_1960 = { + 0x1960, pci_device_101e_1960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_1960, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9010 = { + 0x9010, pci_device_101e_9010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9030 = { + 0x9030, pci_device_101e_9030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9031 = { + 0x9031, pci_device_101e_9031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9032 = { + 0x9032, pci_device_101e_9032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9033 = { + 0x9033, pci_device_101e_9033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9040 = { + 0x9040, pci_device_101e_9040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9060 = { + 0x9060, pci_device_101e_9060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_101e_9063 = { + 0x9063, pci_device_101e_9063, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_101e_9063, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1022_1100 = { + 0x1100, pci_device_1022_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_1101 = { + 0x1101, pci_device_1022_1101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_1101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_1102 = { + 0x1102, pci_device_1022_1102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_1102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_1103 = { + 0x1103, pci_device_1022_1103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_1103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2000 = { + 0x2000, pci_device_1022_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2001 = { + 0x2001, pci_device_1022_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2003 = { + 0x2003, pci_device_1022_2003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2020 = { + 0x2020, pci_device_1022_2020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2040 = { + 0x2040, pci_device_1022_2040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2081 = { + 0x2081, pci_device_1022_2081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2082 = { + 0x2082, pci_device_1022_2082, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2082, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_208f = { + 0x208f, pci_device_1022_208f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_208f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2090 = { + 0x2090, pci_device_1022_2090, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2090, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2091 = { + 0x2091, pci_device_1022_2091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2093 = { + 0x2093, pci_device_1022_2093, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2093, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2094 = { + 0x2094, pci_device_1022_2094, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2094, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2095 = { + 0x2095, pci_device_1022_2095, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2095, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2096 = { + 0x2096, pci_device_1022_2096, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2096, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_2097 = { + 0x2097, pci_device_1022_2097, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_2097, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_209a = { + 0x209a, pci_device_1022_209a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_209a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_3000 = { + 0x3000, pci_device_1022_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_3000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7006 = { + 0x7006, pci_device_1022_7006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7007 = { + 0x7007, pci_device_1022_7007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700a = { + 0x700a, pci_device_1022_700a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700b = { + 0x700b, pci_device_1022_700b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700c = { + 0x700c, pci_device_1022_700c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700d = { + 0x700d, pci_device_1022_700d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700e = { + 0x700e, pci_device_1022_700e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_700f = { + 0x700f, pci_device_1022_700f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_700f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7400 = { + 0x7400, pci_device_1022_7400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7401 = { + 0x7401, pci_device_1022_7401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7403 = { + 0x7403, pci_device_1022_7403, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7403, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7404 = { + 0x7404, pci_device_1022_7404, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7404, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7408 = { + 0x7408, pci_device_1022_7408, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7408, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7409 = { + 0x7409, pci_device_1022_7409, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7409, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_740b = { + 0x740b, pci_device_1022_740b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_740b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_740c = { + 0x740c, pci_device_1022_740c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_740c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7410 = { + 0x7410, pci_device_1022_7410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7411 = { + 0x7411, pci_device_1022_7411, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7411, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7413 = { + 0x7413, pci_device_1022_7413, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7413, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7414 = { + 0x7414, pci_device_1022_7414, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7414, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7440 = { + 0x7440, pci_device_1022_7440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7441 = { + 0x7441, pci_device_1022_7441, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7441, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7443 = { + 0x7443, pci_device_1022_7443, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7443, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7445 = { + 0x7445, pci_device_1022_7445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7446 = { + 0x7446, pci_device_1022_7446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7448 = { + 0x7448, pci_device_1022_7448, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7448, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7449 = { + 0x7449, pci_device_1022_7449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7450 = { + 0x7450, pci_device_1022_7450, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7450, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7451 = { + 0x7451, pci_device_1022_7451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7454 = { + 0x7454, pci_device_1022_7454, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7454, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7455 = { + 0x7455, pci_device_1022_7455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7458 = { + 0x7458, pci_device_1022_7458, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7458, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7459 = { + 0x7459, pci_device_1022_7459, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7459, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7460 = { + 0x7460, pci_device_1022_7460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7461 = { + 0x7461, pci_device_1022_7461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7462 = { + 0x7462, pci_device_1022_7462, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7462, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7464 = { + 0x7464, pci_device_1022_7464, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7464, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7468 = { + 0x7468, pci_device_1022_7468, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7468, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_7469 = { + 0x7469, pci_device_1022_7469, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_7469, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_746a = { + 0x746a, pci_device_1022_746a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_746a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_746b = { + 0x746b, pci_device_1022_746b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_746b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_746d = { + 0x746d, pci_device_1022_746d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_746d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_746e = { + 0x746e, pci_device_1022_746e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_746e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1022_756b = { + 0x756b, pci_device_1022_756b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1022_756b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_0194 = { + 0x0194, pci_device_1023_0194, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_0194, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_2000 = { + 0x2000, pci_device_1023_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_2001 = { + 0x2001, pci_device_1023_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_2001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_2100 = { + 0x2100, pci_device_1023_2100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_2100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_2200 = { + 0x2200, pci_device_1023_2200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_2200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8400 = { + 0x8400, pci_device_1023_8400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8420 = { + 0x8420, pci_device_1023_8420, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8420, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8500 = { + 0x8500, pci_device_1023_8500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8520 = { + 0x8520, pci_device_1023_8520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8620 = { + 0x8620, pci_device_1023_8620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_8820 = { + 0x8820, pci_device_1023_8820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_8820, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9320 = { + 0x9320, pci_device_1023_9320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9350 = { + 0x9350, pci_device_1023_9350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9360 = { + 0x9360, pci_device_1023_9360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9382 = { + 0x9382, pci_device_1023_9382, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9382, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9383 = { + 0x9383, pci_device_1023_9383, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9383, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9385 = { + 0x9385, pci_device_1023_9385, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9385, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9386 = { + 0x9386, pci_device_1023_9386, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9386, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9388 = { + 0x9388, pci_device_1023_9388, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9388, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9397 = { + 0x9397, pci_device_1023_9397, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9397, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_939a = { + 0x939a, pci_device_1023_939a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_939a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9420 = { + 0x9420, pci_device_1023_9420, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9420, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9430 = { + 0x9430, pci_device_1023_9430, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9430, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9440 = { + 0x9440, pci_device_1023_9440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9460 = { + 0x9460, pci_device_1023_9460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9470 = { + 0x9470, pci_device_1023_9470, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9470, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9520 = { + 0x9520, pci_device_1023_9520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9525 = { + 0x9525, pci_device_1023_9525, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9525, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9540 = { + 0x9540, pci_device_1023_9540, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9540, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9660 = { + 0x9660, pci_device_1023_9660, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9660, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9680 = { + 0x9680, pci_device_1023_9680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9682 = { + 0x9682, pci_device_1023_9682, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9682, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9683 = { + 0x9683, pci_device_1023_9683, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9683, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9685 = { + 0x9685, pci_device_1023_9685, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9685, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9750 = { + 0x9750, pci_device_1023_9750, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9750, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9753 = { + 0x9753, pci_device_1023_9753, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9753, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9754 = { + 0x9754, pci_device_1023_9754, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9754, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9759 = { + 0x9759, pci_device_1023_9759, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9759, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9783 = { + 0x9783, pci_device_1023_9783, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9783, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9785 = { + 0x9785, pci_device_1023_9785, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9785, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9850 = { + 0x9850, pci_device_1023_9850, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9850, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9880 = { + 0x9880, pci_device_1023_9880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9910 = { + 0x9910, pci_device_1023_9910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9910, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1023_9930 = { + 0x9930, pci_device_1023_9930, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1023_9930, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_0090 = { + 0x0090, pci_device_1025_0090, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_0090, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1435 = { + 0x1435, pci_device_1025_1435, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1435, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1445 = { + 0x1445, pci_device_1025_1445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1449 = { + 0x1449, pci_device_1025_1449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1451 = { + 0x1451, pci_device_1025_1451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1461 = { + 0x1461, pci_device_1025_1461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1489 = { + 0x1489, pci_device_1025_1489, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1489, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1511 = { + 0x1511, pci_device_1025_1511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1512 = { + 0x1512, pci_device_1025_1512, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1512, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1513 = { + 0x1513, pci_device_1025_1513, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1513, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1521 = { + 0x1521, pci_device_1025_1521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1521, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1523 = { + 0x1523, pci_device_1025_1523, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1523, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1531 = { + 0x1531, pci_device_1025_1531, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1531, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1533 = { + 0x1533, pci_device_1025_1533, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1533, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1535 = { + 0x1535, pci_device_1025_1535, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1535, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1541 = { + 0x1541, pci_device_1025_1541, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1541, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1542 = { + 0x1542, pci_device_1025_1542, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1542, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1543 = { + 0x1543, pci_device_1025_1543, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1543, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1561 = { + 0x1561, pci_device_1025_1561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1621 = { + 0x1621, pci_device_1025_1621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1631 = { + 0x1631, pci_device_1025_1631, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1631, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1641 = { + 0x1641, pci_device_1025_1641, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1641, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1647 = { + 0x1647, pci_device_1025_1647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1671 = { + 0x1671, pci_device_1025_1671, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1671, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_1672 = { + 0x1672, pci_device_1025_1672, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_1672, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3141 = { + 0x3141, pci_device_1025_3141, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3141, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3143 = { + 0x3143, pci_device_1025_3143, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3143, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3145 = { + 0x3145, pci_device_1025_3145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3147 = { + 0x3147, pci_device_1025_3147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3149 = { + 0x3149, pci_device_1025_3149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3151 = { + 0x3151, pci_device_1025_3151, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3151, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3307 = { + 0x3307, pci_device_1025_3307, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3307, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3309 = { + 0x3309, pci_device_1025_3309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_3321 = { + 0x3321, pci_device_1025_3321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_3321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5212 = { + 0x5212, pci_device_1025_5212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5215 = { + 0x5215, pci_device_1025_5215, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5215, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5217 = { + 0x5217, pci_device_1025_5217, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5217, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5219 = { + 0x5219, pci_device_1025_5219, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5219, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5225 = { + 0x5225, pci_device_1025_5225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5229 = { + 0x5229, pci_device_1025_5229, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5229, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5235 = { + 0x5235, pci_device_1025_5235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5237 = { + 0x5237, pci_device_1025_5237, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5237, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5240 = { + 0x5240, pci_device_1025_5240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5241 = { + 0x5241, pci_device_1025_5241, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5241, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5242 = { + 0x5242, pci_device_1025_5242, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5242, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5243 = { + 0x5243, pci_device_1025_5243, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5243, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5244 = { + 0x5244, pci_device_1025_5244, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5244, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5247 = { + 0x5247, pci_device_1025_5247, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5247, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5251 = { + 0x5251, pci_device_1025_5251, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5251, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5427 = { + 0x5427, pci_device_1025_5427, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5427, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5451 = { + 0x5451, pci_device_1025_5451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_5453 = { + 0x5453, pci_device_1025_5453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_5453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1025_7101 = { + 0x7101, pci_device_1025_7101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1025_7101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0001 = { + 0x0001, pci_device_1028_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0002 = { + 0x0002, pci_device_1028_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0003 = { + 0x0003, pci_device_1028_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0006 = { + 0x0006, pci_device_1028_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0007 = { + 0x0007, pci_device_1028_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0008 = { + 0x0008, pci_device_1028_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0009 = { + 0x0009, pci_device_1028_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_000a = { + 0x000a, pci_device_1028_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_000c = { + 0x000c, pci_device_1028_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_000d = { + 0x000d, pci_device_1028_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_000e = { + 0x000e, pci_device_1028_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_000e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_000f = { + 0x000f, pci_device_1028_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0010 = { + 0x0010, pci_device_1028_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0011 = { + 0x0011, pci_device_1028_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0012 = { + 0x0012, pci_device_1028_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0013 = { + 0x0013, pci_device_1028_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0014 = { + 0x0014, pci_device_1028_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1028_0015 = { + 0x0015, pci_device_1028_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1028_0015, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_102a_0000 = { + 0x0000, pci_device_102a_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102a_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102a_0010 = { + 0x0010, pci_device_102a_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102a_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102a_001f = { + 0x001f, pci_device_102a_001f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102a_001f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102a_00c5 = { + 0x00c5, pci_device_102a_00c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102a_00c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102a_00cf = { + 0x00cf, pci_device_102a_00cf, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102a_00cf, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_102b_0010 = { + 0x0010, pci_device_102b_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0100 = { + 0x0100, pci_device_102b_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0518 = { + 0x0518, pci_device_102b_0518, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0518, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0519 = { + 0x0519, pci_device_102b_0519, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0519, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_051a = { + 0x051a, pci_device_102b_051a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_051a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_051b = { + 0x051b, pci_device_102b_051b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_051b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_051e = { + 0x051e, pci_device_102b_051e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_051e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_051f = { + 0x051f, pci_device_102b_051f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_051f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0520 = { + 0x0520, pci_device_102b_0520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0521 = { + 0x0521, pci_device_102b_0521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0521, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0522 = { + 0x0522, pci_device_102b_0522, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0522, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0525 = { + 0x0525, pci_device_102b_0525, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0525, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0527 = { + 0x0527, pci_device_102b_0527, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0527, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0528 = { + 0x0528, pci_device_102b_0528, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0528, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_0d10 = { + 0x0d10, pci_device_102b_0d10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_0d10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_1000 = { + 0x1000, pci_device_102b_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_1001 = { + 0x1001, pci_device_102b_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_2007 = { + 0x2007, pci_device_102b_2007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_2007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_2527 = { + 0x2527, pci_device_102b_2527, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_2527, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_2537 = { + 0x2537, pci_device_102b_2537, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_2537, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_2538 = { + 0x2538, pci_device_102b_2538, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_2538, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_4536 = { + 0x4536, pci_device_102b_4536, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_4536, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_4cdc = { + 0x4cdc, pci_device_102b_4cdc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_4cdc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_4fc5 = { + 0x4fc5, pci_device_102b_4fc5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_4fc5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_5e10 = { + 0x5e10, pci_device_102b_5e10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_5e10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102b_6573 = { + 0x6573, pci_device_102b_6573, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102b_6573, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00b8 = { + 0x00b8, pci_device_102c_00b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00c0 = { + 0x00c0, pci_device_102c_00c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00d0 = { + 0x00d0, pci_device_102c_00d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00d8 = { + 0x00d8, pci_device_102c_00d8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00d8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00dc = { + 0x00dc, pci_device_102c_00dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00dc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00e0 = { + 0x00e0, pci_device_102c_00e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00e4 = { + 0x00e4, pci_device_102c_00e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00e5 = { + 0x00e5, pci_device_102c_00e5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00e5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00f0 = { + 0x00f0, pci_device_102c_00f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00f4 = { + 0x00f4, pci_device_102c_00f4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00f4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_00f5 = { + 0x00f5, pci_device_102c_00f5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_00f5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102c_0c30 = { + 0x0c30, pci_device_102c_0c30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102c_0c30, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_102d_50dc = { + 0x50dc, pci_device_102d_50dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102d_50dc, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_102f_0009 = { + 0x0009, pci_device_102f_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_000a = { + 0x000a, pci_device_102f_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0020 = { + 0x0020, pci_device_102f_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0030 = { + 0x0030, pci_device_102f_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0031 = { + 0x0031, pci_device_102f_0031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0105 = { + 0x0105, pci_device_102f_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0106 = { + 0x0106, pci_device_102f_0106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0107 = { + 0x0107, pci_device_102f_0107, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0107, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0108 = { + 0x0108, pci_device_102f_0108, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0108, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0180 = { + 0x0180, pci_device_102f_0180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0181 = { + 0x0181, pci_device_102f_0181, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0181, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_102f_0182 = { + 0x0182, pci_device_102f_0182, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_102f_0182, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1031_5601 = { + 0x5601, pci_device_1031_5601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1031_5601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1031_5607 = { + 0x5607, pci_device_1031_5607, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1031_5607, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1031_5631 = { + 0x5631, pci_device_1031_5631, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1031_5631, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1031_6057 = { + 0x6057, pci_device_1031_6057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1031_6057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0000 = { + 0x0000, pci_device_1033_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0001 = { + 0x0001, pci_device_1033_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0002 = { + 0x0002, pci_device_1033_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0003 = { + 0x0003, pci_device_1033_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0004 = { + 0x0004, pci_device_1033_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0005 = { + 0x0005, pci_device_1033_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0006 = { + 0x0006, pci_device_1033_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0007 = { + 0x0007, pci_device_1033_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0008 = { + 0x0008, pci_device_1033_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0009 = { + 0x0009, pci_device_1033_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0016 = { + 0x0016, pci_device_1033_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_001a = { + 0x001a, pci_device_1033_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0021 = { + 0x0021, pci_device_1033_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0029 = { + 0x0029, pci_device_1033_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_002a = { + 0x002a, pci_device_1033_002a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_002a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_002c = { + 0x002c, pci_device_1033_002c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_002c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_002d = { + 0x002d, pci_device_1033_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0035 = { + 0x0035, pci_device_1033_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_003b = { + 0x003b, pci_device_1033_003b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_003b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_003e = { + 0x003e, pci_device_1033_003e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_003e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0046 = { + 0x0046, pci_device_1033_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_005a = { + 0x005a, pci_device_1033_005a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_005a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0063 = { + 0x0063, pci_device_1033_0063, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0063, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0067 = { + 0x0067, pci_device_1033_0067, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0067, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0072 = { + 0x0072, pci_device_1033_0072, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0072, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0074 = { + 0x0074, pci_device_1033_0074, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0074, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_009b = { + 0x009b, pci_device_1033_009b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_009b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00a5 = { + 0x00a5, pci_device_1033_00a5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00a5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00a6 = { + 0x00a6, pci_device_1033_00a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00cd = { + 0x00cd, pci_device_1033_00cd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00cd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00ce = { + 0x00ce, pci_device_1033_00ce, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00ce, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00df = { + 0x00df, pci_device_1033_00df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00e0 = { + 0x00e0, pci_device_1033_00e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00e7 = { + 0x00e7, pci_device_1033_00e7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00e7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00f2 = { + 0x00f2, pci_device_1033_00f2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00f2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_00f3 = { + 0x00f3, pci_device_1033_00f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_00f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_010c = { + 0x010c, pci_device_1033_010c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_010c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_0125 = { + 0x0125, pci_device_1033_0125, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_0125, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1033_013a = { + 0x013a, pci_device_1033_013a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1033_013a, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1036_0000 = { + 0x0000, pci_device_1036_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1036_0000, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1039_0001 = { + 0x0001, pci_device_1039_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0002 = { + 0x0002, pci_device_1039_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0003 = { + 0x0003, pci_device_1039_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0004 = { + 0x0004, pci_device_1039_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0006 = { + 0x0006, pci_device_1039_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0008 = { + 0x0008, pci_device_1039_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0009 = { + 0x0009, pci_device_1039_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_000a = { + 0x000a, pci_device_1039_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0016 = { + 0x0016, pci_device_1039_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0018 = { + 0x0018, pci_device_1039_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0180 = { + 0x0180, pci_device_1039_0180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0181 = { + 0x0181, pci_device_1039_0181, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0181, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0182 = { + 0x0182, pci_device_1039_0182, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0182, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0186 = { + 0x0186, pci_device_1039_0186, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0186, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0190 = { + 0x0190, pci_device_1039_0190, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0190, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0191 = { + 0x0191, pci_device_1039_0191, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0191, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0200 = { + 0x0200, pci_device_1039_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0204 = { + 0x0204, pci_device_1039_0204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0205 = { + 0x0205, pci_device_1039_0205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0300 = { + 0x0300, pci_device_1039_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0310 = { + 0x0310, pci_device_1039_0310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0315 = { + 0x0315, pci_device_1039_0315, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0315, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0325 = { + 0x0325, pci_device_1039_0325, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0325, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0330 = { + 0x0330, pci_device_1039_0330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0406 = { + 0x0406, pci_device_1039_0406, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0406, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0496 = { + 0x0496, pci_device_1039_0496, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0496, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0530 = { + 0x0530, pci_device_1039_0530, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0530, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0540 = { + 0x0540, pci_device_1039_0540, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0540, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0550 = { + 0x0550, pci_device_1039_0550, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0550, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0597 = { + 0x0597, pci_device_1039_0597, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0597, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0601 = { + 0x0601, pci_device_1039_0601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0620 = { + 0x0620, pci_device_1039_0620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0630 = { + 0x0630, pci_device_1039_0630, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0630, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0633 = { + 0x0633, pci_device_1039_0633, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0633, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0635 = { + 0x0635, pci_device_1039_0635, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0635, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0645 = { + 0x0645, pci_device_1039_0645, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0645, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0646 = { + 0x0646, pci_device_1039_0646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0648 = { + 0x0648, pci_device_1039_0648, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0648, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0650 = { + 0x0650, pci_device_1039_0650, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0650, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0651 = { + 0x0651, pci_device_1039_0651, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0651, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0655 = { + 0x0655, pci_device_1039_0655, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0655, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0660 = { + 0x0660, pci_device_1039_0660, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0660, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0661 = { + 0x0661, pci_device_1039_0661, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0661, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0662 = { + 0x0662, pci_device_1039_0662, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0662, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0730 = { + 0x0730, pci_device_1039_0730, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0730, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0733 = { + 0x0733, pci_device_1039_0733, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0733, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0735 = { + 0x0735, pci_device_1039_0735, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0735, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0740 = { + 0x0740, pci_device_1039_0740, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0740, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0741 = { + 0x0741, pci_device_1039_0741, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0741, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0745 = { + 0x0745, pci_device_1039_0745, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0745, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0746 = { + 0x0746, pci_device_1039_0746, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0746, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0755 = { + 0x0755, pci_device_1039_0755, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0755, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0760 = { + 0x0760, pci_device_1039_0760, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0760, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0761 = { + 0x0761, pci_device_1039_0761, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0761, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0900 = { + 0x0900, pci_device_1039_0900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0961 = { + 0x0961, pci_device_1039_0961, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0961, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0962 = { + 0x0962, pci_device_1039_0962, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0962, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0963 = { + 0x0963, pci_device_1039_0963, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0963, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0964 = { + 0x0964, pci_device_1039_0964, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0964, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0965 = { + 0x0965, pci_device_1039_0965, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0965, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0966 = { + 0x0966, pci_device_1039_0966, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0966, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_0968 = { + 0x0968, pci_device_1039_0968, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_0968, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_1180 = { + 0x1180, pci_device_1039_1180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_1180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_1182 = { + 0x1182, pci_device_1039_1182, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_1182, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_1183 = { + 0x1183, pci_device_1039_1183, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_1183, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_1184 = { + 0x1184, pci_device_1039_1184, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_1184, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_1185 = { + 0x1185, pci_device_1039_1185, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_1185, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_3602 = { + 0x3602, pci_device_1039_3602, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_3602, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5107 = { + 0x5107, pci_device_1039_5107, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5107, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5300 = { + 0x5300, pci_device_1039_5300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5315 = { + 0x5315, pci_device_1039_5315, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5315, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5401 = { + 0x5401, pci_device_1039_5401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5511 = { + 0x5511, pci_device_1039_5511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5513 = { + 0x5513, pci_device_1039_5513, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5513, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5517 = { + 0x5517, pci_device_1039_5517, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5517, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5571 = { + 0x5571, pci_device_1039_5571, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5571, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5581 = { + 0x5581, pci_device_1039_5581, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5581, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5582 = { + 0x5582, pci_device_1039_5582, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5582, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5591 = { + 0x5591, pci_device_1039_5591, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5591, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5596 = { + 0x5596, pci_device_1039_5596, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5596, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5597 = { + 0x5597, pci_device_1039_5597, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5597, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_5600 = { + 0x5600, pci_device_1039_5600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_5600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6204 = { + 0x6204, pci_device_1039_6204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6205 = { + 0x6205, pci_device_1039_6205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6236 = { + 0x6236, pci_device_1039_6236, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6236, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6300 = { + 0x6300, pci_device_1039_6300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6306 = { + 0x6306, pci_device_1039_6306, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6306, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6325 = { + 0x6325, pci_device_1039_6325, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6325, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6326 = { + 0x6326, pci_device_1039_6326, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6326, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6330 = { + 0x6330, pci_device_1039_6330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6350 = { + 0x6350, pci_device_1039_6350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_6351 = { + 0x6351, pci_device_1039_6351, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_6351, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7001 = { + 0x7001, pci_device_1039_7001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7002 = { + 0x7002, pci_device_1039_7002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7007 = { + 0x7007, pci_device_1039_7007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7012 = { + 0x7012, pci_device_1039_7012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7013 = { + 0x7013, pci_device_1039_7013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7016 = { + 0x7016, pci_device_1039_7016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7018 = { + 0x7018, pci_device_1039_7018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7019 = { + 0x7019, pci_device_1039_7019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1039_7502 = { + 0x7502, pci_device_1039_7502, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1039_7502, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_002a = { + 0x002a, pci_device_103c_002a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_002a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1005 = { + 0x1005, pci_device_103c_1005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1008 = { + 0x1008, pci_device_103c_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1028 = { + 0x1028, pci_device_103c_1028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1029 = { + 0x1029, pci_device_103c_1029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_102a = { + 0x102a, pci_device_103c_102a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_102a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1030 = { + 0x1030, pci_device_103c_1030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1031 = { + 0x1031, pci_device_103c_1031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1040 = { + 0x1040, pci_device_103c_1040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1041 = { + 0x1041, pci_device_103c_1041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1042 = { + 0x1042, pci_device_103c_1042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1048 = { + 0x1048, pci_device_103c_1048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1054 = { + 0x1054, pci_device_103c_1054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1064 = { + 0x1064, pci_device_103c_1064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_108b = { + 0x108b, pci_device_103c_108b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_108b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_10c1 = { + 0x10c1, pci_device_103c_10c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_10c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_10ed = { + 0x10ed, pci_device_103c_10ed, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_10ed, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_10f0 = { + 0x10f0, pci_device_103c_10f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_10f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_10f1 = { + 0x10f1, pci_device_103c_10f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_10f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1200 = { + 0x1200, pci_device_103c_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1219 = { + 0x1219, pci_device_103c_1219, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1219, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_121a = { + 0x121a, pci_device_103c_121a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_121a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_121b = { + 0x121b, pci_device_103c_121b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_121b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_121c = { + 0x121c, pci_device_103c_121c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_121c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1229 = { + 0x1229, pci_device_103c_1229, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1229, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_122a = { + 0x122a, pci_device_103c_122a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_122a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_122e = { + 0x122e, pci_device_103c_122e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_122e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_127b = { + 0x127b, pci_device_103c_127b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_127b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_127c = { + 0x127c, pci_device_103c_127c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_127c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1290 = { + 0x1290, pci_device_103c_1290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_1291 = { + 0x1291, pci_device_103c_1291, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_1291, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_12b4 = { + 0x12b4, pci_device_103c_12b4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_12b4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_12eb = { + 0x12eb, pci_device_103c_12eb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_12eb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_12ec = { + 0x12ec, pci_device_103c_12ec, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_12ec, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_12ee = { + 0x12ee, pci_device_103c_12ee, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_12ee, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_12f8 = { + 0x12f8, pci_device_103c_12f8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_12f8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_12fa = { + 0x12fa, pci_device_103c_12fa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_12fa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_2910 = { + 0x2910, pci_device_103c_2910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_2910, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_2925 = { + 0x2925, pci_device_103c_2925, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_2925, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_3080 = { + 0x3080, pci_device_103c_3080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_3080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_3085 = { + 0x3085, pci_device_103c_3085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_3085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_3220 = { + 0x3220, pci_device_103c_3220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_3220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_3230 = { + 0x3230, pci_device_103c_3230, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_3230, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_4030 = { + 0x4030, pci_device_103c_4030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_4030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_4031 = { + 0x4031, pci_device_103c_4031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_4031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_4037 = { + 0x4037, pci_device_103c_4037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_4037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_403b = { + 0x403b, pci_device_103c_403b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_403b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_103c_60e8 = { + 0x60e8, pci_device_103c_60e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_103c_60e8, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1042_1000 = { + 0x1000, pci_device_1042_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1042_1001 = { + 0x1001, pci_device_1042_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1042_3000 = { + 0x3000, pci_device_1042_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_3000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1042_3010 = { + 0x3010, pci_device_1042_3010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_3010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1042_3020 = { + 0x3020, pci_device_1042_3020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1042_3020, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1043_0675 = { + 0x0675, pci_device_1043_0675, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_0675, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_0c11 = { + 0x0c11, pci_device_1043_0c11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_0c11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_4015 = { + 0x4015, pci_device_1043_4015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_4015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_4021 = { + 0x4021, pci_device_1043_4021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_4021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_4057 = { + 0x4057, pci_device_1043_4057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_4057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_8043 = { + 0x8043, pci_device_1043_8043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_8043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_8047 = { + 0x8047, pci_device_1043_8047, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_8047, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_807b = { + 0x807b, pci_device_1043_807b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_807b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_8095 = { + 0x8095, pci_device_1043_8095, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_8095, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_80ac = { + 0x80ac, pci_device_1043_80ac, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_80ac, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_80bb = { + 0x80bb, pci_device_1043_80bb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_80bb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_80c5 = { + 0x80c5, pci_device_1043_80c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_80c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_80df = { + 0x80df, pci_device_1043_80df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_80df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_815a = { + 0x815a, pci_device_1043_815a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_815a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_8187 = { + 0x8187, pci_device_1043_8187, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_8187, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1043_8188 = { + 0x8188, pci_device_1043_8188, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1043_8188, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1044_1012 = { + 0x1012, pci_device_1044_1012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_1012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1044_a400 = { + 0xa400, pci_device_1044_a400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_a400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1044_a500 = { + 0xa500, pci_device_1044_a500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_a500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1044_a501 = { + 0xa501, pci_device_1044_a501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_a501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1044_a511 = { + 0xa511, pci_device_1044_a511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1044_a511, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1045_a0f8 = { + 0xa0f8, pci_device_1045_a0f8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_a0f8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c101 = { + 0xc101, pci_device_1045_c101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c178 = { + 0xc178, pci_device_1045_c178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c556 = { + 0xc556, pci_device_1045_c556, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c556, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c557 = { + 0xc557, pci_device_1045_c557, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c557, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c558 = { + 0xc558, pci_device_1045_c558, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c558, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c567 = { + 0xc567, pci_device_1045_c567, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c567, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c568 = { + 0xc568, pci_device_1045_c568, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c568, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c569 = { + 0xc569, pci_device_1045_c569, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c569, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c621 = { + 0xc621, pci_device_1045_c621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c700 = { + 0xc700, pci_device_1045_c700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c701 = { + 0xc701, pci_device_1045_c701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c701, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c814 = { + 0xc814, pci_device_1045_c814, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c814, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c822 = { + 0xc822, pci_device_1045_c822, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c822, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c824 = { + 0xc824, pci_device_1045_c824, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c824, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c825 = { + 0xc825, pci_device_1045_c825, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c825, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c832 = { + 0xc832, pci_device_1045_c832, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c832, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c861 = { + 0xc861, pci_device_1045_c861, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c861, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c895 = { + 0xc895, pci_device_1045_c895, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c895, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_c935 = { + 0xc935, pci_device_1045_c935, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_c935, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_d568 = { + 0xd568, pci_device_1045_d568, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_d568, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1045_d721 = { + 0xd721, pci_device_1045_d721, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1045_d721, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1048_0c60 = { + 0x0c60, pci_device_1048_0c60, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1048_0c60, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1048_0d22 = { + 0x0d22, pci_device_1048_0d22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1048_0d22, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1048_1000 = { + 0x1000, pci_device_1048_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1048_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1048_3000 = { + 0x3000, pci_device_1048_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1048_3000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1048_8901 = { + 0x8901, pci_device_1048_8901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1048_8901, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_104a_0008 = { + 0x0008, pci_device_104a_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0009 = { + 0x0009, pci_device_104a_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0010 = { + 0x0010, pci_device_104a_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0209 = { + 0x0209, pci_device_104a_0209, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0209, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_020a = { + 0x020a, pci_device_104a_020a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_020a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0210 = { + 0x0210, pci_device_104a_0210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_021a = { + 0x021a, pci_device_104a_021a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_021a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_021b = { + 0x021b, pci_device_104a_021b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_021b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0500 = { + 0x0500, pci_device_104a_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0564 = { + 0x0564, pci_device_104a_0564, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0564, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_0981 = { + 0x0981, pci_device_104a_0981, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_0981, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_1746 = { + 0x1746, pci_device_104a_1746, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_1746, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_2774 = { + 0x2774, pci_device_104a_2774, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_2774, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_3520 = { + 0x3520, pci_device_104a_3520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_3520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104a_55cc = { + 0x55cc, pci_device_104a_55cc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104a_55cc, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_104b_0140 = { + 0x0140, pci_device_104b_0140, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104b_0140, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104b_1040 = { + 0x1040, pci_device_104b_1040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104b_1040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104b_8130 = { + 0x8130, pci_device_104b_8130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104b_8130, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_104c_0500 = { + 0x0500, pci_device_104c_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_0508 = { + 0x0508, pci_device_104c_0508, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_0508, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_1000 = { + 0x1000, pci_device_104c_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_104c = { + 0x104c, pci_device_104c_104c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_104c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_3d04 = { + 0x3d04, pci_device_104c_3d04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_3d04, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_3d07 = { + 0x3d07, pci_device_104c_3d07, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_3d07, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8000 = { + 0x8000, pci_device_104c_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8009 = { + 0x8009, pci_device_104c_8009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8017 = { + 0x8017, pci_device_104c_8017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8019 = { + 0x8019, pci_device_104c_8019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8020 = { + 0x8020, pci_device_104c_8020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8021 = { + 0x8021, pci_device_104c_8021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8022 = { + 0x8022, pci_device_104c_8022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8023 = { + 0x8023, pci_device_104c_8023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8024 = { + 0x8024, pci_device_104c_8024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8025 = { + 0x8025, pci_device_104c_8025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8026 = { + 0x8026, pci_device_104c_8026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8027 = { + 0x8027, pci_device_104c_8027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8029 = { + 0x8029, pci_device_104c_8029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_802b = { + 0x802b, pci_device_104c_802b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_802b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_802e = { + 0x802e, pci_device_104c_802e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_802e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8031 = { + 0x8031, pci_device_104c_8031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8032 = { + 0x8032, pci_device_104c_8032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8033 = { + 0x8033, pci_device_104c_8033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8034 = { + 0x8034, pci_device_104c_8034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8035 = { + 0x8035, pci_device_104c_8035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8036 = { + 0x8036, pci_device_104c_8036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8038 = { + 0x8038, pci_device_104c_8038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8039 = { + 0x8039, pci_device_104c_8039, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8039, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_803a = { + 0x803a, pci_device_104c_803a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_803a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_803b = { + 0x803b, pci_device_104c_803b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_803b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_803c = { + 0x803c, pci_device_104c_803c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_803c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_803d = { + 0x803d, pci_device_104c_803d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_803d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8201 = { + 0x8201, pci_device_104c_8201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8204 = { + 0x8204, pci_device_104c_8204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8231 = { + 0x8231, pci_device_104c_8231, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8231, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8235 = { + 0x8235, pci_device_104c_8235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8400 = { + 0x8400, pci_device_104c_8400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_8401 = { + 0x8401, pci_device_104c_8401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_8401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_9000 = { + 0x9000, pci_device_104c_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_9065 = { + 0x9065, pci_device_104c_9065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_9065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_9066 = { + 0x9066, pci_device_104c_9066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_9066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_a001 = { + 0xa001, pci_device_104c_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_a001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_a100 = { + 0xa100, pci_device_104c_a100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_a100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_a102 = { + 0xa102, pci_device_104c_a102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_a102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_a106 = { + 0xa106, pci_device_104c_a106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_a106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac10 = { + 0xac10, pci_device_104c_ac10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac11 = { + 0xac11, pci_device_104c_ac11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac12 = { + 0xac12, pci_device_104c_ac12, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac12, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac13 = { + 0xac13, pci_device_104c_ac13, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac13, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac15 = { + 0xac15, pci_device_104c_ac15, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac15, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac16 = { + 0xac16, pci_device_104c_ac16, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac16, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac17 = { + 0xac17, pci_device_104c_ac17, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac17, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac18 = { + 0xac18, pci_device_104c_ac18, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac18, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac19 = { + 0xac19, pci_device_104c_ac19, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac19, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1a = { + 0xac1a, pci_device_104c_ac1a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1b = { + 0xac1b, pci_device_104c_ac1b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1c = { + 0xac1c, pci_device_104c_ac1c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1d = { + 0xac1d, pci_device_104c_ac1d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1e = { + 0xac1e, pci_device_104c_ac1e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac1f = { + 0xac1f, pci_device_104c_ac1f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac1f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac20 = { + 0xac20, pci_device_104c_ac20, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac20, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac21 = { + 0xac21, pci_device_104c_ac21, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac21, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac22 = { + 0xac22, pci_device_104c_ac22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac22, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac23 = { + 0xac23, pci_device_104c_ac23, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac23, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac28 = { + 0xac28, pci_device_104c_ac28, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac28, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac30 = { + 0xac30, pci_device_104c_ac30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac30, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac40 = { + 0xac40, pci_device_104c_ac40, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac40, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac41 = { + 0xac41, pci_device_104c_ac41, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac41, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac42 = { + 0xac42, pci_device_104c_ac42, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac42, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac44 = { + 0xac44, pci_device_104c_ac44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac46 = { + 0xac46, pci_device_104c_ac46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac47 = { + 0xac47, pci_device_104c_ac47, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac47, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac4a = { + 0xac4a, pci_device_104c_ac4a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac4a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac50 = { + 0xac50, pci_device_104c_ac50, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac50, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac51 = { + 0xac51, pci_device_104c_ac51, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac51, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac52 = { + 0xac52, pci_device_104c_ac52, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac52, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac53 = { + 0xac53, pci_device_104c_ac53, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac53, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac54 = { + 0xac54, pci_device_104c_ac54, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac54, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac55 = { + 0xac55, pci_device_104c_ac55, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac55, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac56 = { + 0xac56, pci_device_104c_ac56, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac56, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac60 = { + 0xac60, pci_device_104c_ac60, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac60, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac8d = { + 0xac8d, pci_device_104c_ac8d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac8d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac8e = { + 0xac8e, pci_device_104c_ac8e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac8e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_ac8f = { + 0xac8f, pci_device_104c_ac8f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_ac8f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_fe00 = { + 0xfe00, pci_device_104c_fe00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_fe00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104c_fe03 = { + 0xfe03, pci_device_104c_fe03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104c_fe03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104d_8004 = { + 0x8004, pci_device_104d_8004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104d_8004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104d_8009 = { + 0x8009, pci_device_104d_8009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104d_8009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104d_8039 = { + 0x8039, pci_device_104d_8039, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104d_8039, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104d_8056 = { + 0x8056, pci_device_104d_8056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104d_8056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104d_808a = { + 0x808a, pci_device_104d_808a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104d_808a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0017 = { + 0x0017, pci_device_104e_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0107 = { + 0x0107, pci_device_104e_0107, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0107, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0109 = { + 0x0109, pci_device_104e_0109, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0109, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0111 = { + 0x0111, pci_device_104e_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0217 = { + 0x0217, pci_device_104e_0217, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0217, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_104e_0317 = { + 0x0317, pci_device_104e_0317, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_104e_0317, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1050_0000 = { + 0x0000, pci_device_1050_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_0001 = { + 0x0001, pci_device_1050_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_0033 = { + 0x0033, pci_device_1050_0033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_0105 = { + 0x0105, pci_device_1050_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_0840 = { + 0x0840, pci_device_1050_0840, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0840, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_0940 = { + 0x0940, pci_device_1050_0940, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_0940, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_5a5a = { + 0x5a5a, pci_device_1050_5a5a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_5a5a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_6692 = { + 0x6692, pci_device_1050_6692, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_6692, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_9921 = { + 0x9921, pci_device_1050_9921, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_9921, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_9922 = { + 0x9922, pci_device_1050_9922, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_9922, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1050_9970 = { + 0x9970, pci_device_1050_9970, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1050_9970, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1055_9130 = { + 0x9130, pci_device_1055_9130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1055_9130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1055_9460 = { + 0x9460, pci_device_1055_9460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1055_9460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1055_9462 = { + 0x9462, pci_device_1055_9462, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1055_9462, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1055_9463 = { + 0x9463, pci_device_1055_9463, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1055_9463, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1057_0001 = { + 0x0001, pci_device_1057_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0002 = { + 0x0002, pci_device_1057_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0003 = { + 0x0003, pci_device_1057_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0004 = { + 0x0004, pci_device_1057_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0006 = { + 0x0006, pci_device_1057_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0008 = { + 0x0008, pci_device_1057_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0009 = { + 0x0009, pci_device_1057_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0012 = { + 0x0012, pci_device_1057_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0100 = { + 0x0100, pci_device_1057_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_0431 = { + 0x0431, pci_device_1057_0431, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_0431, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_1801 = { + 0x1801, pci_device_1057_1801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_1801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_18c0 = { + 0x18c0, pci_device_1057_18c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_18c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_18c1 = { + 0x18c1, pci_device_1057_18c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_18c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_3055 = { + 0x3055, pci_device_1057_3055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_3055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_3410 = { + 0x3410, pci_device_1057_3410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_3410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4801 = { + 0x4801, pci_device_1057_4801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4802 = { + 0x4802, pci_device_1057_4802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4803 = { + 0x4803, pci_device_1057_4803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4806 = { + 0x4806, pci_device_1057_4806, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4806, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_4d68 = { + 0x4d68, pci_device_1057_4d68, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_4d68, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_5600 = { + 0x5600, pci_device_1057_5600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_5600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_5608 = { + 0x5608, pci_device_1057_5608, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_5608, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_5803 = { + 0x5803, pci_device_1057_5803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_5803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_5806 = { + 0x5806, pci_device_1057_5806, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_5806, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_5808 = { + 0x5808, pci_device_1057_5808, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_5808, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_5809 = { + 0x5809, pci_device_1057_5809, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_5809, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_6400 = { + 0x6400, pci_device_1057_6400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_6400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1057_6405 = { + 0x6405, pci_device_1057_6405, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1057_6405, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_105a_0d30 = { + 0x0d30, pci_device_105a_0d30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_0d30, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_0d38 = { + 0x0d38, pci_device_105a_0d38, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_0d38, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_1275 = { + 0x1275, pci_device_105a_1275, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_1275, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3318 = { + 0x3318, pci_device_105a_3318, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3318, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3319 = { + 0x3319, pci_device_105a_3319, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3319, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3371 = { + 0x3371, pci_device_105a_3371, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3371, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3373 = { + 0x3373, pci_device_105a_3373, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3373, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3375 = { + 0x3375, pci_device_105a_3375, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3375, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3376 = { + 0x3376, pci_device_105a_3376, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3376, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3515 = { + 0x3515, pci_device_105a_3515, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3515, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3519 = { + 0x3519, pci_device_105a_3519, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3519, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3570 = { + 0x3570, pci_device_105a_3570, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3570, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3571 = { + 0x3571, pci_device_105a_3571, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3571, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3574 = { + 0x3574, pci_device_105a_3574, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3574, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3577 = { + 0x3577, pci_device_105a_3577, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3577, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3d17 = { + 0x3d17, pci_device_105a_3d17, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3d17, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3d18 = { + 0x3d18, pci_device_105a_3d18, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3d18, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3d73 = { + 0x3d73, pci_device_105a_3d73, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3d73, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_3d75 = { + 0x3d75, pci_device_105a_3d75, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_3d75, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4302 = { + 0x4302, pci_device_105a_4302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d30 = { + 0x4d30, pci_device_105a_4d30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d30, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d33 = { + 0x4d33, pci_device_105a_4d33, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d33, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d38 = { + 0x4d38, pci_device_105a_4d38, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d38, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d68 = { + 0x4d68, pci_device_105a_4d68, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d68, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_4d69 = { + 0x4d69, pci_device_105a_4d69, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_4d69, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_5275 = { + 0x5275, pci_device_105a_5275, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_5275, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_5300 = { + 0x5300, pci_device_105a_5300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_5300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6268 = { + 0x6268, pci_device_105a_6268, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6268, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6269 = { + 0x6269, pci_device_105a_6269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6621 = { + 0x6621, pci_device_105a_6621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6622 = { + 0x6622, pci_device_105a_6622, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6622, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6624 = { + 0x6624, pci_device_105a_6624, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6624, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6626 = { + 0x6626, pci_device_105a_6626, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6626, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_6629 = { + 0x6629, pci_device_105a_6629, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_6629, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_7275 = { + 0x7275, pci_device_105a_7275, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_7275, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_8002 = { + 0x8002, pci_device_105a_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_8350 = { + 0x8350, pci_device_105a_8350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_8350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105a_c350 = { + 0xc350, pci_device_105a_c350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105a_c350, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_105d_2309 = { + 0x2309, pci_device_105d_2309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105d_2309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105d_2339 = { + 0x2339, pci_device_105d_2339, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105d_2339, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105d_493d = { + 0x493d, pci_device_105d_493d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105d_493d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_105d_5348 = { + 0x5348, pci_device_105d_5348, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_105d_5348, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1060_0001 = { + 0x0001, pci_device_1060_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0002 = { + 0x0002, pci_device_1060_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0101 = { + 0x0101, pci_device_1060_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0881 = { + 0x0881, pci_device_1060_0881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0886 = { + 0x0886, pci_device_1060_0886, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0886, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_0891 = { + 0x0891, pci_device_1060_0891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_0891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_1001 = { + 0x1001, pci_device_1060_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_673a = { + 0x673a, pci_device_1060_673a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_673a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_673b = { + 0x673b, pci_device_1060_673b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_673b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_8710 = { + 0x8710, pci_device_1060_8710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_8710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_886a = { + 0x886a, pci_device_1060_886a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_886a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_8881 = { + 0x8881, pci_device_1060_8881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_8881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_8886 = { + 0x8886, pci_device_1060_8886, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_8886, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_888a = { + 0x888a, pci_device_1060_888a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_888a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_8891 = { + 0x8891, pci_device_1060_8891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_8891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_9017 = { + 0x9017, pci_device_1060_9017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_9017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_9018 = { + 0x9018, pci_device_1060_9018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_9018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_9026 = { + 0x9026, pci_device_1060_9026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_9026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_e881 = { + 0xe881, pci_device_1060_e881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_e881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_e886 = { + 0xe886, pci_device_1060_e886, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_e886, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_e88a = { + 0xe88a, pci_device_1060_e88a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_e88a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1060_e891 = { + 0xe891, pci_device_1060_e891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1060_e891, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1061_0001 = { + 0x0001, pci_device_1061_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1061_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1061_0002 = { + 0x0002, pci_device_1061_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1061_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1066_0000 = { + 0x0000, pci_device_1066_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0001 = { + 0x0001, pci_device_1066_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0002 = { + 0x0002, pci_device_1066_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0003 = { + 0x0003, pci_device_1066_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0004 = { + 0x0004, pci_device_1066_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_0005 = { + 0x0005, pci_device_1066_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1066_8002 = { + 0x8002, pci_device_1066_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1066_8002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1067_0301 = { + 0x0301, pci_device_1067_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1067_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1067_0304 = { + 0x0304, pci_device_1067_0304, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1067_0304, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1067_0308 = { + 0x0308, pci_device_1067_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1067_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1067_1002 = { + 0x1002, pci_device_1067_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1067_1002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1069_0001 = { + 0x0001, pci_device_1069_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_0002 = { + 0x0002, pci_device_1069_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_0010 = { + 0x0010, pci_device_1069_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_0020 = { + 0x0020, pci_device_1069_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_0050 = { + 0x0050, pci_device_1069_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_b166 = { + 0xb166, pci_device_1069_b166, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_b166, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_ba55 = { + 0xba55, pci_device_1069_ba55, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_ba55, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_ba56 = { + 0xba56, pci_device_1069_ba56, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_ba56, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1069_ba57 = { + 0xba57, pci_device_1069_ba57, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1069_ba57, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_106b_0001 = { + 0x0001, pci_device_106b_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0002 = { + 0x0002, pci_device_106b_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0003 = { + 0x0003, pci_device_106b_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0004 = { + 0x0004, pci_device_106b_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0007 = { + 0x0007, pci_device_106b_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_000c = { + 0x000c, pci_device_106b_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_000e = { + 0x000e, pci_device_106b_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_000e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0010 = { + 0x0010, pci_device_106b_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0017 = { + 0x0017, pci_device_106b_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0018 = { + 0x0018, pci_device_106b_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0019 = { + 0x0019, pci_device_106b_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_001e = { + 0x001e, pci_device_106b_001e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_001e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_001f = { + 0x001f, pci_device_106b_001f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_001f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0020 = { + 0x0020, pci_device_106b_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0021 = { + 0x0021, pci_device_106b_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0022 = { + 0x0022, pci_device_106b_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0024 = { + 0x0024, pci_device_106b_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0025 = { + 0x0025, pci_device_106b_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0026 = { + 0x0026, pci_device_106b_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0027 = { + 0x0027, pci_device_106b_0027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0028 = { + 0x0028, pci_device_106b_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0029 = { + 0x0029, pci_device_106b_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_002d = { + 0x002d, pci_device_106b_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_002e = { + 0x002e, pci_device_106b_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_002f = { + 0x002f, pci_device_106b_002f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_002f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0030 = { + 0x0030, pci_device_106b_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0031 = { + 0x0031, pci_device_106b_0031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0032 = { + 0x0032, pci_device_106b_0032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0033 = { + 0x0033, pci_device_106b_0033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0034 = { + 0x0034, pci_device_106b_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0035 = { + 0x0035, pci_device_106b_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0036 = { + 0x0036, pci_device_106b_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_003b = { + 0x003b, pci_device_106b_003b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_003b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_003e = { + 0x003e, pci_device_106b_003e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_003e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_003f = { + 0x003f, pci_device_106b_003f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_003f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0040 = { + 0x0040, pci_device_106b_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0041 = { + 0x0041, pci_device_106b_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0042 = { + 0x0042, pci_device_106b_0042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0043 = { + 0x0043, pci_device_106b_0043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0045 = { + 0x0045, pci_device_106b_0045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0046 = { + 0x0046, pci_device_106b_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0047 = { + 0x0047, pci_device_106b_0047, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0047, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0048 = { + 0x0048, pci_device_106b_0048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0049 = { + 0x0049, pci_device_106b_0049, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0049, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_004b = { + 0x004b, pci_device_106b_004b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_004b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_004c = { + 0x004c, pci_device_106b_004c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_004c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_004f = { + 0x004f, pci_device_106b_004f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_004f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0050 = { + 0x0050, pci_device_106b_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0051 = { + 0x0051, pci_device_106b_0051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0052 = { + 0x0052, pci_device_106b_0052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0053 = { + 0x0053, pci_device_106b_0053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0054 = { + 0x0054, pci_device_106b_0054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0055 = { + 0x0055, pci_device_106b_0055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0058 = { + 0x0058, pci_device_106b_0058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0059 = { + 0x0059, pci_device_106b_0059, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0059, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0066 = { + 0x0066, pci_device_106b_0066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0067 = { + 0x0067, pci_device_106b_0067, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0067, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0068 = { + 0x0068, pci_device_106b_0068, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0068, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_0069 = { + 0x0069, pci_device_106b_0069, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_0069, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_006a = { + 0x006a, pci_device_106b_006a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_006a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_006b = { + 0x006b, pci_device_106b_006b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_006b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106b_1645 = { + 0x1645, pci_device_106b_1645, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106b_1645, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_106c_8801 = { + 0x8801, pci_device_106c_8801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106c_8802 = { + 0x8802, pci_device_106c_8802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106c_8803 = { + 0x8803, pci_device_106c_8803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106c_8804 = { + 0x8804, pci_device_106c_8804, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8804, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_106c_8805 = { + 0x8805, pci_device_106c_8805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_106c_8805, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1071_8160 = { + 0x8160, pci_device_1071_8160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1071_8160, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1073_0001 = { + 0x0001, pci_device_1073_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0002 = { + 0x0002, pci_device_1073_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0003 = { + 0x0003, pci_device_1073_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0004 = { + 0x0004, pci_device_1073_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0005 = { + 0x0005, pci_device_1073_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0006 = { + 0x0006, pci_device_1073_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0008 = { + 0x0008, pci_device_1073_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_000a = { + 0x000a, pci_device_1073_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_000c = { + 0x000c, pci_device_1073_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_000d = { + 0x000d, pci_device_1073_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0010 = { + 0x0010, pci_device_1073_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0012 = { + 0x0012, pci_device_1073_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_0020 = { + 0x0020, pci_device_1073_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1073_2000 = { + 0x2000, pci_device_1073_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1073_2000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1074_4e78 = { + 0x4e78, pci_device_1074_4e78, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1074_4e78, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1077_1016 = { + 0x1016, pci_device_1077_1016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1020 = { + 0x1020, pci_device_1077_1020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1022 = { + 0x1022, pci_device_1077_1022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1080 = { + 0x1080, pci_device_1077_1080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1216 = { + 0x1216, pci_device_1077_1216, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1216, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1240 = { + 0x1240, pci_device_1077_1240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_1280 = { + 0x1280, pci_device_1077_1280, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_1280, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2020 = { + 0x2020, pci_device_1077_2020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2100 = { + 0x2100, pci_device_1077_2100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2200 = { + 0x2200, pci_device_1077_2200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2300 = { + 0x2300, pci_device_1077_2300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2312 = { + 0x2312, pci_device_1077_2312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2322 = { + 0x2322, pci_device_1077_2322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2322, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2422 = { + 0x2422, pci_device_1077_2422, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2422, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_2432 = { + 0x2432, pci_device_1077_2432, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_2432, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_3010 = { + 0x3010, pci_device_1077_3010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_3010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_3022 = { + 0x3022, pci_device_1077_3022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_3022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_4010 = { + 0x4010, pci_device_1077_4010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_4010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_4022 = { + 0x4022, pci_device_1077_4022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_4022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_6312 = { + 0x6312, pci_device_1077_6312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_6312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1077_6322 = { + 0x6322, pci_device_1077_6322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1077_6322, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1078_0000 = { + 0x0000, pci_device_1078_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0001 = { + 0x0001, pci_device_1078_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0002 = { + 0x0002, pci_device_1078_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0100 = { + 0x0100, pci_device_1078_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0101 = { + 0x0101, pci_device_1078_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0102 = { + 0x0102, pci_device_1078_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0103 = { + 0x0103, pci_device_1078_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0104 = { + 0x0104, pci_device_1078_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0400 = { + 0x0400, pci_device_1078_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0401 = { + 0x0401, pci_device_1078_0401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0402 = { + 0x0402, pci_device_1078_0402, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0402, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1078_0403 = { + 0x0403, pci_device_1078_0403, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1078_0403, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_107d_0000 = { + 0x0000, pci_device_107d_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107d_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107d_204d = { + 0x204d, pci_device_107d_204d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107d_204d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107d_2134 = { + 0x2134, pci_device_107d_2134, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107d_2134, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107d_2971 = { + 0x2971, pci_device_107d_2971, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107d_2971, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_107e_0001 = { + 0x0001, pci_device_107e_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_0002 = { + 0x0002, pci_device_107e_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_0004 = { + 0x0004, pci_device_107e_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_0005 = { + 0x0005, pci_device_107e_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_0008 = { + 0x0008, pci_device_107e_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9003 = { + 0x9003, pci_device_107e_9003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9007 = { + 0x9007, pci_device_107e_9007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9008 = { + 0x9008, pci_device_107e_9008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_900c = { + 0x900c, pci_device_107e_900c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_900c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_900e = { + 0x900e, pci_device_107e_900e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_900e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9011 = { + 0x9011, pci_device_107e_9011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9013 = { + 0x9013, pci_device_107e_9013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9023 = { + 0x9023, pci_device_107e_9023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9027 = { + 0x9027, pci_device_107e_9027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9031 = { + 0x9031, pci_device_107e_9031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_107e_9033 = { + 0x9033, pci_device_107e_9033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107e_9033, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_107f_0802 = { + 0x0802, pci_device_107f_0802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_107f_0802, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1080_0600 = { + 0x0600, pci_device_1080_0600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1080_0600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1080_c691 = { + 0xc691, pci_device_1080_c691, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1080_c691, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1080_c693 = { + 0xc693, pci_device_1080_c693, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1080_c693, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1081_0d47 = { + 0x0d47, pci_device_1081_0d47, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1081_0d47, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1083_0001 = { + 0x0001, pci_device_1083_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1083_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_108a_0001 = { + 0x0001, pci_device_108a_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108a_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108a_0010 = { + 0x0010, pci_device_108a_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108a_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108a_0040 = { + 0x0040, pci_device_108a_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108a_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108a_3000 = { + 0x3000, pci_device_108a_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108a_3000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_108d_0001 = { + 0x0001, pci_device_108d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0002 = { + 0x0002, pci_device_108d_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0004 = { + 0x0004, pci_device_108d_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0005 = { + 0x0005, pci_device_108d_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0006 = { + 0x0006, pci_device_108d_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0007 = { + 0x0007, pci_device_108d_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0008 = { + 0x0008, pci_device_108d_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0011 = { + 0x0011, pci_device_108d_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0012 = { + 0x0012, pci_device_108d_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0013 = { + 0x0013, pci_device_108d_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0014 = { + 0x0014, pci_device_108d_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0019 = { + 0x0019, pci_device_108d_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0021 = { + 0x0021, pci_device_108d_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108d_0022 = { + 0x0022, pci_device_108d_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108d_0022, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_108e_0001 = { + 0x0001, pci_device_108e_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1000 = { + 0x1000, pci_device_108e_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1001 = { + 0x1001, pci_device_108e_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1100 = { + 0x1100, pci_device_108e_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1101 = { + 0x1101, pci_device_108e_1101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1102 = { + 0x1102, pci_device_108e_1102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1103 = { + 0x1103, pci_device_108e_1103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_1648 = { + 0x1648, pci_device_108e_1648, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_1648, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_2bad = { + 0x2bad, pci_device_108e_2bad, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_2bad, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_5000 = { + 0x5000, pci_device_108e_5000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_5000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_5043 = { + 0x5043, pci_device_108e_5043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_5043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_8000 = { + 0x8000, pci_device_108e_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_8000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_8001 = { + 0x8001, pci_device_108e_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_8001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_8002 = { + 0x8002, pci_device_108e_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_a000 = { + 0xa000, pci_device_108e_a000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_a000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_a001 = { + 0xa001, pci_device_108e_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_a001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_a801 = { + 0xa801, pci_device_108e_a801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_a801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_108e_abba = { + 0xabba, pci_device_108e_abba, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_108e_abba, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1091_0020 = { + 0x0020, pci_device_1091_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0021 = { + 0x0021, pci_device_1091_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0040 = { + 0x0040, pci_device_1091_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0041 = { + 0x0041, pci_device_1091_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0060 = { + 0x0060, pci_device_1091_0060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_00e4 = { + 0x00e4, pci_device_1091_00e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_00e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_0720 = { + 0x0720, pci_device_1091_0720, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_0720, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_07a0 = { + 0x07a0, pci_device_1091_07a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_07a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1091_1091 = { + 0x1091, pci_device_1091_1091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1091_1091, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1092_00a0 = { + 0x00a0, pci_device_1092_00a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_00a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_00a8 = { + 0x00a8, pci_device_1092_00a8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_00a8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_0550 = { + 0x0550, pci_device_1092_0550, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_0550, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_08d4 = { + 0x08d4, pci_device_1092_08d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_08d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_094c = { + 0x094c, pci_device_1092_094c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_094c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_1092 = { + 0x1092, pci_device_1092_1092, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_1092, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_6120 = { + 0x6120, pci_device_1092_6120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_6120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_8810 = { + 0x8810, pci_device_1092_8810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_8810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_8811 = { + 0x8811, pci_device_1092_8811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_8811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_8880 = { + 0x8880, pci_device_1092_8880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_8880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_8881 = { + 0x8881, pci_device_1092_8881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_8881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88b0 = { + 0x88b0, pci_device_1092_88b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88b1 = { + 0x88b1, pci_device_1092_88b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88c0 = { + 0x88c0, pci_device_1092_88c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88c1 = { + 0x88c1, pci_device_1092_88c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88d0 = { + 0x88d0, pci_device_1092_88d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88d1 = { + 0x88d1, pci_device_1092_88d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88f0 = { + 0x88f0, pci_device_1092_88f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_88f1 = { + 0x88f1, pci_device_1092_88f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_88f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1092_9999 = { + 0x9999, pci_device_1092_9999, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1092_9999, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1093_0160 = { + 0x0160, pci_device_1093_0160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_0160, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_0162 = { + 0x0162, pci_device_1093_0162, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_0162, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1150 = { + 0x1150, pci_device_1093_1150, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1150, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1170 = { + 0x1170, pci_device_1093_1170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1180 = { + 0x1180, pci_device_1093_1180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1190 = { + 0x1190, pci_device_1093_1190, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1190, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1310 = { + 0x1310, pci_device_1093_1310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1330 = { + 0x1330, pci_device_1093_1330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1350 = { + 0x1350, pci_device_1093_1350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_14e0 = { + 0x14e0, pci_device_1093_14e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_14e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_14f0 = { + 0x14f0, pci_device_1093_14f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_14f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_17d0 = { + 0x17d0, pci_device_1093_17d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_17d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1870 = { + 0x1870, pci_device_1093_1870, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1870, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_1880 = { + 0x1880, pci_device_1093_1880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_1880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_18b0 = { + 0x18b0, pci_device_1093_18b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_18b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2410 = { + 0x2410, pci_device_1093_2410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2890 = { + 0x2890, pci_device_1093_2890, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2890, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2a60 = { + 0x2a60, pci_device_1093_2a60, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2a60, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2a70 = { + 0x2a70, pci_device_1093_2a70, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2a70, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2a80 = { + 0x2a80, pci_device_1093_2a80, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2a80, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2c80 = { + 0x2c80, pci_device_1093_2c80, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2c80, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_2ca0 = { + 0x2ca0, pci_device_1093_2ca0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_2ca0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_70a9 = { + 0x70a9, pci_device_1093_70a9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_70a9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_70b8 = { + 0x70b8, pci_device_1093_70b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_70b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b001 = { + 0xb001, pci_device_1093_b001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b011 = { + 0xb011, pci_device_1093_b011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b021 = { + 0xb021, pci_device_1093_b021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b031 = { + 0xb031, pci_device_1093_b031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b041 = { + 0xb041, pci_device_1093_b041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b051 = { + 0xb051, pci_device_1093_b051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b061 = { + 0xb061, pci_device_1093_b061, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b061, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b071 = { + 0xb071, pci_device_1093_b071, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b071, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b081 = { + 0xb081, pci_device_1093_b081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_b091 = { + 0xb091, pci_device_1093_b091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_b091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_c801 = { + 0xc801, pci_device_1093_c801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_c801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1093_c831 = { + 0xc831, pci_device_1093_c831, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1093_c831, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1095_0240 = { + 0x0240, pci_device_1095_0240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0640 = { + 0x0640, pci_device_1095_0640, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0640, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0643 = { + 0x0643, pci_device_1095_0643, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0643, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0646 = { + 0x0646, pci_device_1095_0646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0647 = { + 0x0647, pci_device_1095_0647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0648 = { + 0x0648, pci_device_1095_0648, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0648, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0649 = { + 0x0649, pci_device_1095_0649, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0649, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0650 = { + 0x0650, pci_device_1095_0650, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0650, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0670 = { + 0x0670, pci_device_1095_0670, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0670, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0673 = { + 0x0673, pci_device_1095_0673, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0673, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_0680 = { + 0x0680, pci_device_1095_0680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_0680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_3112 = { + 0x3112, pci_device_1095_3112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_3112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_3114 = { + 0x3114, pci_device_1095_3114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_3114, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_3124 = { + 0x3124, pci_device_1095_3124, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_3124, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_3132 = { + 0x3132, pci_device_1095_3132, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_3132, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1095_3512 = { + 0x3512, pci_device_1095_3512, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1095_3512, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1098_0001 = { + 0x0001, pci_device_1098_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1098_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1098_0002 = { + 0x0002, pci_device_1098_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1098_0002, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_109e_032e = { + 0x032e, pci_device_109e_032e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_032e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0350 = { + 0x0350, pci_device_109e_0350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0351 = { + 0x0351, pci_device_109e_0351, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0351, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0369 = { + 0x0369, pci_device_109e_0369, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0369, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_036c = { + 0x036c, pci_device_109e_036c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_036c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_036e = { + 0x036e, pci_device_109e_036e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_036e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_036f = { + 0x036f, pci_device_109e_036f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_036f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0370 = { + 0x0370, pci_device_109e_0370, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0370, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0878 = { + 0x0878, pci_device_109e_0878, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0878, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0879 = { + 0x0879, pci_device_109e_0879, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0879, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_0880 = { + 0x0880, pci_device_109e_0880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_0880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_2115 = { + 0x2115, pci_device_109e_2115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_2115, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_2125 = { + 0x2125, pci_device_109e_2125, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_2125, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_2164 = { + 0x2164, pci_device_109e_2164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_2164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_2165 = { + 0x2165, pci_device_109e_2165, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_2165, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_8230 = { + 0x8230, pci_device_109e_8230, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_8230, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_8472 = { + 0x8472, pci_device_109e_8472, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_8472, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_109e_8474 = { + 0x8474, pci_device_109e_8474, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_109e_8474, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10a5_3052 = { + 0x3052, pci_device_10a5_3052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a5_3052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a5_5449 = { + 0x5449, pci_device_10a5_5449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a5_5449, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10a8_0000 = { + 0x0000, pci_device_10a8_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a8_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10a9_0001 = { + 0x0001, pci_device_10a9_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0002 = { + 0x0002, pci_device_10a9_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0003 = { + 0x0003, pci_device_10a9_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0004 = { + 0x0004, pci_device_10a9_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0005 = { + 0x0005, pci_device_10a9_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0006 = { + 0x0006, pci_device_10a9_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0007 = { + 0x0007, pci_device_10a9_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0008 = { + 0x0008, pci_device_10a9_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0009 = { + 0x0009, pci_device_10a9_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0010 = { + 0x0010, pci_device_10a9_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0011 = { + 0x0011, pci_device_10a9_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_0012 = { + 0x0012, pci_device_10a9_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1001 = { + 0x1001, pci_device_10a9_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1002 = { + 0x1002, pci_device_10a9_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1003 = { + 0x1003, pci_device_10a9_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1004 = { + 0x1004, pci_device_10a9_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1005 = { + 0x1005, pci_device_10a9_1005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1006 = { + 0x1006, pci_device_10a9_1006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1007 = { + 0x1007, pci_device_10a9_1007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_1008 = { + 0x1008, pci_device_10a9_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_1008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_100a = { + 0x100a, pci_device_10a9_100a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_100a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_2001 = { + 0x2001, pci_device_10a9_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_2001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_2002 = { + 0x2002, pci_device_10a9_2002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_2002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_4001 = { + 0x4001, pci_device_10a9_4001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_4001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_4002 = { + 0x4002, pci_device_10a9_4002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_4002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_8001 = { + 0x8001, pci_device_10a9_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_8001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10a9_8002 = { + 0x8002, pci_device_10a9_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10a9_8002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10aa_0000 = { + 0x0000, pci_device_10aa_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10aa_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ad_0001 = { + 0x0001, pci_device_10ad_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0003 = { + 0x0003, pci_device_10ad_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0005 = { + 0x0005, pci_device_10ad_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0103 = { + 0x0103, pci_device_10ad_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0105 = { + 0x0105, pci_device_10ad_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ad_0565 = { + 0x0565, pci_device_10ad_0565, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ad_0565, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b3_3106 = { + 0x3106, pci_device_10b3_3106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b3_3106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b3_b106 = { + 0xb106, pci_device_10b3_b106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b3_b106, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b4_1b1d = { + 0x1b1d, pci_device_10b4_1b1d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b4_1b1d, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b5_0001 = { + 0x0001, pci_device_10b5_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1042 = { + 0x1042, pci_device_10b5_1042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1076 = { + 0x1076, pci_device_10b5_1076, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1076, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1077 = { + 0x1077, pci_device_10b5_1077, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1077, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1078 = { + 0x1078, pci_device_10b5_1078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1103 = { + 0x1103, pci_device_10b5_1103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1146 = { + 0x1146, pci_device_10b5_1146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_1147 = { + 0x1147, pci_device_10b5_1147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_1147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_2540 = { + 0x2540, pci_device_10b5_2540, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_2540, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_2724 = { + 0x2724, pci_device_10b5_2724, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_2724, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_6540 = { + 0x6540, pci_device_10b5_6540, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_6540, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_6541 = { + 0x6541, pci_device_10b5_6541, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_6541, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_6542 = { + 0x6542, pci_device_10b5_6542, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_6542, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_8111 = { + 0x8111, pci_device_10b5_8111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_8111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_8114 = { + 0x8114, pci_device_10b5_8114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_8114, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_8516 = { + 0x8516, pci_device_10b5_8516, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_8516, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_8532 = { + 0x8532, pci_device_10b5_8532, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_8532, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9030 = { + 0x9030, pci_device_10b5_9030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9036 = { + 0x9036, pci_device_10b5_9036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9050 = { + 0x9050, pci_device_10b5_9050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9054 = { + 0x9054, pci_device_10b5_9054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9056 = { + 0x9056, pci_device_10b5_9056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9060 = { + 0x9060, pci_device_10b5_9060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_906d = { + 0x906d, pci_device_10b5_906d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_906d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_906e = { + 0x906e, pci_device_10b5_906e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_906e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9080 = { + 0x9080, pci_device_10b5_9080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_9656 = { + 0x9656, pci_device_10b5_9656, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_9656, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_bb04 = { + 0xbb04, pci_device_10b5_bb04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_bb04, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b5_c001 = { + 0xc001, pci_device_10b5_c001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b5_c001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b6_0001 = { + 0x0001, pci_device_10b6_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0002 = { + 0x0002, pci_device_10b6_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0003 = { + 0x0003, pci_device_10b6_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0004 = { + 0x0004, pci_device_10b6_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0006 = { + 0x0006, pci_device_10b6_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0007 = { + 0x0007, pci_device_10b6_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_0009 = { + 0x0009, pci_device_10b6_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_000a = { + 0x000a, pci_device_10b6_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_000b = { + 0x000b, pci_device_10b6_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_000c = { + 0x000c, pci_device_10b6_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_1000 = { + 0x1000, pci_device_10b6_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b6_1001 = { + 0x1001, pci_device_10b6_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b6_1001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b7_0001 = { + 0x0001, pci_device_10b7_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_0013 = { + 0x0013, pci_device_10b7_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_0910 = { + 0x0910, pci_device_10b7_0910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_0910, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_1006 = { + 0x1006, pci_device_10b7_1006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_1006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_1007 = { + 0x1007, pci_device_10b7_1007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_1007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_1201 = { + 0x1201, pci_device_10b7_1201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_1201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_1202 = { + 0x1202, pci_device_10b7_1202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_1202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_1700 = { + 0x1700, pci_device_10b7_1700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_1700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_3390 = { + 0x3390, pci_device_10b7_3390, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_3390, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_3590 = { + 0x3590, pci_device_10b7_3590, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_3590, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_4500 = { + 0x4500, pci_device_10b7_4500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_4500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5055 = { + 0x5055, pci_device_10b7_5055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5057 = { + 0x5057, pci_device_10b7_5057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5157 = { + 0x5157, pci_device_10b7_5157, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5157, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5257 = { + 0x5257, pci_device_10b7_5257, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5257, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5900 = { + 0x5900, pci_device_10b7_5900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5920 = { + 0x5920, pci_device_10b7_5920, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5920, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5950 = { + 0x5950, pci_device_10b7_5950, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5950, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5951 = { + 0x5951, pci_device_10b7_5951, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5951, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5952 = { + 0x5952, pci_device_10b7_5952, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5952, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5970 = { + 0x5970, pci_device_10b7_5970, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5970, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_5b57 = { + 0x5b57, pci_device_10b7_5b57, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_5b57, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6000 = { + 0x6000, pci_device_10b7_6000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6001 = { + 0x6001, pci_device_10b7_6001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6055 = { + 0x6055, pci_device_10b7_6055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6056 = { + 0x6056, pci_device_10b7_6056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6560 = { + 0x6560, pci_device_10b7_6560, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6560, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6561 = { + 0x6561, pci_device_10b7_6561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6562 = { + 0x6562, pci_device_10b7_6562, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6562, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6563 = { + 0x6563, pci_device_10b7_6563, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6563, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_6564 = { + 0x6564, pci_device_10b7_6564, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_6564, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_7646 = { + 0x7646, pci_device_10b7_7646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_7646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_7770 = { + 0x7770, pci_device_10b7_7770, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_7770, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_7940 = { + 0x7940, pci_device_10b7_7940, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_7940, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_7980 = { + 0x7980, pci_device_10b7_7980, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_7980, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_7990 = { + 0x7990, pci_device_10b7_7990, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_7990, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_80eb = { + 0x80eb, pci_device_10b7_80eb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_80eb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_8811 = { + 0x8811, pci_device_10b7_8811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_8811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9000 = { + 0x9000, pci_device_10b7_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9001 = { + 0x9001, pci_device_10b7_9001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9004 = { + 0x9004, pci_device_10b7_9004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9005 = { + 0x9005, pci_device_10b7_9005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9006 = { + 0x9006, pci_device_10b7_9006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_900a = { + 0x900a, pci_device_10b7_900a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_900a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9050 = { + 0x9050, pci_device_10b7_9050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9051 = { + 0x9051, pci_device_10b7_9051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9054 = { + 0x9054, pci_device_10b7_9054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9055 = { + 0x9055, pci_device_10b7_9055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9056 = { + 0x9056, pci_device_10b7_9056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9058 = { + 0x9058, pci_device_10b7_9058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_905a = { + 0x905a, pci_device_10b7_905a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_905a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9200 = { + 0x9200, pci_device_10b7_9200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9201 = { + 0x9201, pci_device_10b7_9201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9202 = { + 0x9202, pci_device_10b7_9202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9210 = { + 0x9210, pci_device_10b7_9210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9300 = { + 0x9300, pci_device_10b7_9300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9800 = { + 0x9800, pci_device_10b7_9800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9805 = { + 0x9805, pci_device_10b7_9805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9900 = { + 0x9900, pci_device_10b7_9900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9902 = { + 0x9902, pci_device_10b7_9902, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9902, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9903 = { + 0x9903, pci_device_10b7_9903, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9903, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9904 = { + 0x9904, pci_device_10b7_9904, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9904, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9905 = { + 0x9905, pci_device_10b7_9905, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9905, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9908 = { + 0x9908, pci_device_10b7_9908, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9908, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_9909 = { + 0x9909, pci_device_10b7_9909, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_9909, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_990a = { + 0x990a, pci_device_10b7_990a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_990a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b7_990b = { + 0x990b, pci_device_10b7_990b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b7_990b, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b8_0005 = { + 0x0005, pci_device_10b8_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_0006 = { + 0x0006, pci_device_10b8_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_1000 = { + 0x1000, pci_device_10b8_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_1001 = { + 0x1001, pci_device_10b8_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_2802 = { + 0x2802, pci_device_10b8_2802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_2802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_a011 = { + 0xa011, pci_device_10b8_a011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_a011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b8_b106 = { + 0xb106, pci_device_10b8_b106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b8_b106, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10b9_0101 = { + 0x0101, pci_device_10b9_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_0111 = { + 0x0111, pci_device_10b9_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_0780 = { + 0x0780, pci_device_10b9_0780, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_0780, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_0782 = { + 0x0782, pci_device_10b9_0782, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_0782, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1435 = { + 0x1435, pci_device_10b9_1435, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1435, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1445 = { + 0x1445, pci_device_10b9_1445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1449 = { + 0x1449, pci_device_10b9_1449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1451 = { + 0x1451, pci_device_10b9_1451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1461 = { + 0x1461, pci_device_10b9_1461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1489 = { + 0x1489, pci_device_10b9_1489, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1489, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1511 = { + 0x1511, pci_device_10b9_1511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1512 = { + 0x1512, pci_device_10b9_1512, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1512, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1513 = { + 0x1513, pci_device_10b9_1513, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1513, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1521 = { + 0x1521, pci_device_10b9_1521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1521, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1523 = { + 0x1523, pci_device_10b9_1523, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1523, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1531 = { + 0x1531, pci_device_10b9_1531, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1531, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1533 = { + 0x1533, pci_device_10b9_1533, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1533, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1541 = { + 0x1541, pci_device_10b9_1541, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1541, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1543 = { + 0x1543, pci_device_10b9_1543, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1543, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1563 = { + 0x1563, pci_device_10b9_1563, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1563, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1573 = { + 0x1573, pci_device_10b9_1573, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1573, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1621 = { + 0x1621, pci_device_10b9_1621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1631 = { + 0x1631, pci_device_10b9_1631, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1631, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1632 = { + 0x1632, pci_device_10b9_1632, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1632, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1641 = { + 0x1641, pci_device_10b9_1641, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1641, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1644 = { + 0x1644, pci_device_10b9_1644, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1644, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1646 = { + 0x1646, pci_device_10b9_1646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1647 = { + 0x1647, pci_device_10b9_1647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1651 = { + 0x1651, pci_device_10b9_1651, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1651, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1671 = { + 0x1671, pci_device_10b9_1671, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1671, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1672 = { + 0x1672, pci_device_10b9_1672, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1672, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1681 = { + 0x1681, pci_device_10b9_1681, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1681, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1687 = { + 0x1687, pci_device_10b9_1687, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1687, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1689 = { + 0x1689, pci_device_10b9_1689, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1689, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1695 = { + 0x1695, pci_device_10b9_1695, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1695, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_1697 = { + 0x1697, pci_device_10b9_1697, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_1697, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3141 = { + 0x3141, pci_device_10b9_3141, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3141, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3143 = { + 0x3143, pci_device_10b9_3143, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3143, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3145 = { + 0x3145, pci_device_10b9_3145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3147 = { + 0x3147, pci_device_10b9_3147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3149 = { + 0x3149, pci_device_10b9_3149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3151 = { + 0x3151, pci_device_10b9_3151, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3151, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3307 = { + 0x3307, pci_device_10b9_3307, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3307, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3309 = { + 0x3309, pci_device_10b9_3309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_3323 = { + 0x3323, pci_device_10b9_3323, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_3323, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5212 = { + 0x5212, pci_device_10b9_5212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5215 = { + 0x5215, pci_device_10b9_5215, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5215, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5217 = { + 0x5217, pci_device_10b9_5217, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5217, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5219 = { + 0x5219, pci_device_10b9_5219, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5219, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5225 = { + 0x5225, pci_device_10b9_5225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5228 = { + 0x5228, pci_device_10b9_5228, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5228, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5229 = { + 0x5229, pci_device_10b9_5229, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5229, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5235 = { + 0x5235, pci_device_10b9_5235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5237 = { + 0x5237, pci_device_10b9_5237, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5237, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5239 = { + 0x5239, pci_device_10b9_5239, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5239, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5243 = { + 0x5243, pci_device_10b9_5243, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5243, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5246 = { + 0x5246, pci_device_10b9_5246, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5246, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5247 = { + 0x5247, pci_device_10b9_5247, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5247, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5249 = { + 0x5249, pci_device_10b9_5249, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5249, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_524b = { + 0x524b, pci_device_10b9_524b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_524b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_524c = { + 0x524c, pci_device_10b9_524c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_524c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_524d = { + 0x524d, pci_device_10b9_524d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_524d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_524e = { + 0x524e, pci_device_10b9_524e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_524e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5251 = { + 0x5251, pci_device_10b9_5251, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5251, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5253 = { + 0x5253, pci_device_10b9_5253, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5253, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5261 = { + 0x5261, pci_device_10b9_5261, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5261, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5263 = { + 0x5263, pci_device_10b9_5263, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5263, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5281 = { + 0x5281, pci_device_10b9_5281, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5281, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5287 = { + 0x5287, pci_device_10b9_5287, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5287, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5288 = { + 0x5288, pci_device_10b9_5288, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5288, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5289 = { + 0x5289, pci_device_10b9_5289, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5289, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5450 = { + 0x5450, pci_device_10b9_5450, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5450, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5451 = { + 0x5451, pci_device_10b9_5451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5453 = { + 0x5453, pci_device_10b9_5453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5455 = { + 0x5455, pci_device_10b9_5455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5457 = { + 0x5457, pci_device_10b9_5457, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5457, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5459 = { + 0x5459, pci_device_10b9_5459, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5459, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_545a = { + 0x545a, pci_device_10b9_545a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_545a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5461 = { + 0x5461, pci_device_10b9_5461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5471 = { + 0x5471, pci_device_10b9_5471, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5471, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_5473 = { + 0x5473, pci_device_10b9_5473, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_5473, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10b9_7101 = { + 0x7101, pci_device_10b9_7101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10b9_7101, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ba_0301 = { + 0x0301, pci_device_10ba_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ba_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ba_0304 = { + 0x0304, pci_device_10ba_0304, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ba_0304, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ba_0308 = { + 0x0308, pci_device_10ba_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ba_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ba_1002 = { + 0x1002, pci_device_10ba_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ba_1002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10bd_0e34 = { + 0x0e34, pci_device_10bd_0e34, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10bd_0e34, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10c3_1100 = { + 0x1100, pci_device_10c3_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c3_1100, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_10c8_0001 = { + 0x0001, pci_device_10c8_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0002 = { + 0x0002, pci_device_10c8_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0003 = { + 0x0003, pci_device_10c8_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0004 = { + 0x0004, pci_device_10c8_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0005 = { + 0x0005, pci_device_10c8_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0006 = { + 0x0006, pci_device_10c8_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0016 = { + 0x0016, pci_device_10c8_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0025 = { + 0x0025, pci_device_10c8_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_0083 = { + 0x0083, pci_device_10c8_0083, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_0083, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_8005 = { + 0x8005, pci_device_10c8_8005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_8005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_8006 = { + 0x8006, pci_device_10c8_8006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_8006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10c8_8016 = { + 0x8016, pci_device_10c8_8016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10c8_8016, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10cc_0660 = { + 0x0660, pci_device_10cc_0660, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cc_0660, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10cc_0661 = { + 0x0661, pci_device_10cc_0661, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cc_0661, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10cd_1100 = { + 0x1100, pci_device_10cd_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10cd_1200 = { + 0x1200, pci_device_10cd_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_1200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10cd_1300 = { + 0x1300, pci_device_10cd_1300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_1300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10cd_2300 = { + 0x2300, pci_device_10cd_2300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_2300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10cd_2500 = { + 0x2500, pci_device_10cd_2500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cd_2500, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10cf_2001 = { + 0x2001, pci_device_10cf_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10cf_2001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10d9_0431 = { + 0x0431, pci_device_10d9_0431, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_0431, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10d9_0512 = { + 0x0512, pci_device_10d9_0512, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_0512, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10d9_0531 = { + 0x0531, pci_device_10d9_0531, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_0531, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10d9_8625 = { + 0x8625, pci_device_10d9_8625, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_8625, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10d9_8626 = { + 0x8626, pci_device_10d9_8626, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_8626, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10d9_8888 = { + 0x8888, pci_device_10d9_8888, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10d9_8888, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10da_0508 = { + 0x0508, pci_device_10da_0508, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10da_0508, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10da_3390 = { + 0x3390, pci_device_10da_3390, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10da_3390, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10dc_0001 = { + 0x0001, pci_device_10dc_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10dc_0002 = { + 0x0002, pci_device_10dc_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10dc_0021 = { + 0x0021, pci_device_10dc_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10dc_0022 = { + 0x0022, pci_device_10dc_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10dc_10dc = { + 0x10dc, pci_device_10dc_10dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dc_10dc, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10dd_0100 = { + 0x0100, pci_device_10dd_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10dd_0100, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_10de_0008 = { + 0x0008, pci_device_10de_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0009 = { + 0x0009, pci_device_10de_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0010 = { + 0x0010, pci_device_10de_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0020 = { + 0x0020, pci_device_10de_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0028 = { + 0x0028, pci_device_10de_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0029 = { + 0x0029, pci_device_10de_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002a = { + 0x002a, pci_device_10de_002a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002b = { + 0x002b, pci_device_10de_002b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002c = { + 0x002c, pci_device_10de_002c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002d = { + 0x002d, pci_device_10de_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002e = { + 0x002e, pci_device_10de_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_002f = { + 0x002f, pci_device_10de_002f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_002f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0034 = { + 0x0034, pci_device_10de_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0035 = { + 0x0035, pci_device_10de_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0036 = { + 0x0036, pci_device_10de_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0037 = { + 0x0037, pci_device_10de_0037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0038 = { + 0x0038, pci_device_10de_0038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_003a = { + 0x003a, pci_device_10de_003a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_003a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_003b = { + 0x003b, pci_device_10de_003b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_003b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_003c = { + 0x003c, pci_device_10de_003c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_003c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_003d = { + 0x003d, pci_device_10de_003d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_003d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_003e = { + 0x003e, pci_device_10de_003e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_003e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0040 = { + 0x0040, pci_device_10de_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0041 = { + 0x0041, pci_device_10de_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0042 = { + 0x0042, pci_device_10de_0042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0043 = { + 0x0043, pci_device_10de_0043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0044 = { + 0x0044, pci_device_10de_0044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0045 = { + 0x0045, pci_device_10de_0045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0046 = { + 0x0046, pci_device_10de_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0047 = { + 0x0047, pci_device_10de_0047, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0047, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0048 = { + 0x0048, pci_device_10de_0048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0049 = { + 0x0049, pci_device_10de_0049, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0049, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_004d = { + 0x004d, pci_device_10de_004d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_004d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_004e = { + 0x004e, pci_device_10de_004e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_004e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0050 = { + 0x0050, pci_device_10de_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0051 = { + 0x0051, pci_device_10de_0051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0052 = { + 0x0052, pci_device_10de_0052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0053 = { + 0x0053, pci_device_10de_0053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0054 = { + 0x0054, pci_device_10de_0054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0055 = { + 0x0055, pci_device_10de_0055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0056 = { + 0x0056, pci_device_10de_0056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0057 = { + 0x0057, pci_device_10de_0057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0058 = { + 0x0058, pci_device_10de_0058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0059 = { + 0x0059, pci_device_10de_0059, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0059, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005a = { + 0x005a, pci_device_10de_005a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005b = { + 0x005b, pci_device_10de_005b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005c = { + 0x005c, pci_device_10de_005c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005d = { + 0x005d, pci_device_10de_005d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005e = { + 0x005e, pci_device_10de_005e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_005f = { + 0x005f, pci_device_10de_005f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_005f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0060 = { + 0x0060, pci_device_10de_0060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0064 = { + 0x0064, pci_device_10de_0064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0065 = { + 0x0065, pci_device_10de_0065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0066 = { + 0x0066, pci_device_10de_0066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0067 = { + 0x0067, pci_device_10de_0067, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0067, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0068 = { + 0x0068, pci_device_10de_0068, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0068, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_006a = { + 0x006a, pci_device_10de_006a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_006a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_006b = { + 0x006b, pci_device_10de_006b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_006b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_006c = { + 0x006c, pci_device_10de_006c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_006c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_006d = { + 0x006d, pci_device_10de_006d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_006d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_006e = { + 0x006e, pci_device_10de_006e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_006e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0080 = { + 0x0080, pci_device_10de_0080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0084 = { + 0x0084, pci_device_10de_0084, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0084, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0085 = { + 0x0085, pci_device_10de_0085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0086 = { + 0x0086, pci_device_10de_0086, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0086, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0087 = { + 0x0087, pci_device_10de_0087, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0087, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0088 = { + 0x0088, pci_device_10de_0088, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0088, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_008a = { + 0x008a, pci_device_10de_008a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_008a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_008b = { + 0x008b, pci_device_10de_008b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_008b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_008c = { + 0x008c, pci_device_10de_008c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_008c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_008e = { + 0x008e, pci_device_10de_008e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_008e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0090 = { + 0x0090, pci_device_10de_0090, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0090, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0091 = { + 0x0091, pci_device_10de_0091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0092 = { + 0x0092, pci_device_10de_0092, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0092, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0093 = { + 0x0093, pci_device_10de_0093, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0093, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0098 = { + 0x0098, pci_device_10de_0098, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0098, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0099 = { + 0x0099, pci_device_10de_0099, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0099, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_009d = { + 0x009d, pci_device_10de_009d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_009d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00a0 = { + 0x00a0, pci_device_10de_00a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00c0 = { + 0x00c0, pci_device_10de_00c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00c1 = { + 0x00c1, pci_device_10de_00c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00c2 = { + 0x00c2, pci_device_10de_00c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00c2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00c3 = { + 0x00c3, pci_device_10de_00c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00c8 = { + 0x00c8, pci_device_10de_00c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00c8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00c9 = { + 0x00c9, pci_device_10de_00c9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00c9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00cc = { + 0x00cc, pci_device_10de_00cc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00cc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00cd = { + 0x00cd, pci_device_10de_00cd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00cd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00ce = { + 0x00ce, pci_device_10de_00ce, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00ce, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d0 = { + 0x00d0, pci_device_10de_00d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d1 = { + 0x00d1, pci_device_10de_00d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d2 = { + 0x00d2, pci_device_10de_00d2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d3 = { + 0x00d3, pci_device_10de_00d3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d4 = { + 0x00d4, pci_device_10de_00d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d5 = { + 0x00d5, pci_device_10de_00d5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d6 = { + 0x00d6, pci_device_10de_00d6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d7 = { + 0x00d7, pci_device_10de_00d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d8 = { + 0x00d8, pci_device_10de_00d8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00d9 = { + 0x00d9, pci_device_10de_00d9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00d9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00da = { + 0x00da, pci_device_10de_00da, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00da, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00dd = { + 0x00dd, pci_device_10de_00dd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00dd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00df = { + 0x00df, pci_device_10de_00df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e0 = { + 0x00e0, pci_device_10de_00e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e1 = { + 0x00e1, pci_device_10de_00e1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e2 = { + 0x00e2, pci_device_10de_00e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e3 = { + 0x00e3, pci_device_10de_00e3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e4 = { + 0x00e4, pci_device_10de_00e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e5 = { + 0x00e5, pci_device_10de_00e5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e6 = { + 0x00e6, pci_device_10de_00e6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e7 = { + 0x00e7, pci_device_10de_00e7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00e8 = { + 0x00e8, pci_device_10de_00e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00e8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00ea = { + 0x00ea, pci_device_10de_00ea, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00ea, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00ed = { + 0x00ed, pci_device_10de_00ed, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00ed, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00ee = { + 0x00ee, pci_device_10de_00ee, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00ee, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f0 = { + 0x00f0, pci_device_10de_00f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f1 = { + 0x00f1, pci_device_10de_00f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f2 = { + 0x00f2, pci_device_10de_00f2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f3 = { + 0x00f3, pci_device_10de_00f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f4 = { + 0x00f4, pci_device_10de_00f4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f5 = { + 0x00f5, pci_device_10de_00f5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f6 = { + 0x00f6, pci_device_10de_00f6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f8 = { + 0x00f8, pci_device_10de_00f8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00f9 = { + 0x00f9, pci_device_10de_00f9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00f9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00fa = { + 0x00fa, pci_device_10de_00fa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00fa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00fb = { + 0x00fb, pci_device_10de_00fb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00fb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00fc = { + 0x00fc, pci_device_10de_00fc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00fc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00fd = { + 0x00fd, pci_device_10de_00fd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00fd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00fe = { + 0x00fe, pci_device_10de_00fe, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00fe, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_00ff = { + 0x00ff, pci_device_10de_00ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_00ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0100 = { + 0x0100, pci_device_10de_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0101 = { + 0x0101, pci_device_10de_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0103 = { + 0x0103, pci_device_10de_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0110 = { + 0x0110, pci_device_10de_0110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0111 = { + 0x0111, pci_device_10de_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0112 = { + 0x0112, pci_device_10de_0112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0113 = { + 0x0113, pci_device_10de_0113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0140 = { + 0x0140, pci_device_10de_0140, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0140, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0141 = { + 0x0141, pci_device_10de_0141, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0141, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0142 = { + 0x0142, pci_device_10de_0142, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0142, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0144 = { + 0x0144, pci_device_10de_0144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0145 = { + 0x0145, pci_device_10de_0145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0146 = { + 0x0146, pci_device_10de_0146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0147 = { + 0x0147, pci_device_10de_0147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0148 = { + 0x0148, pci_device_10de_0148, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0148, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0149 = { + 0x0149, pci_device_10de_0149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_014a = { + 0x014a, pci_device_10de_014a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_014a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_014c = { + 0x014c, pci_device_10de_014c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_014c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_014d = { + 0x014d, pci_device_10de_014d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_014d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_014e = { + 0x014e, pci_device_10de_014e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_014e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_014f = { + 0x014f, pci_device_10de_014f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_014f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0150 = { + 0x0150, pci_device_10de_0150, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0150, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0151 = { + 0x0151, pci_device_10de_0151, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0151, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0152 = { + 0x0152, pci_device_10de_0152, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0152, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0153 = { + 0x0153, pci_device_10de_0153, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0153, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0160 = { + 0x0160, pci_device_10de_0160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0160, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0161 = { + 0x0161, pci_device_10de_0161, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0161, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0162 = { + 0x0162, pci_device_10de_0162, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0162, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0163 = { + 0x0163, pci_device_10de_0163, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0163, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0164 = { + 0x0164, pci_device_10de_0164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0165 = { + 0x0165, pci_device_10de_0165, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0165, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0166 = { + 0x0166, pci_device_10de_0166, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0166, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0167 = { + 0x0167, pci_device_10de_0167, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0167, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0168 = { + 0x0168, pci_device_10de_0168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0169 = { + 0x0169, pci_device_10de_0169, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0169, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0170 = { + 0x0170, pci_device_10de_0170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0171 = { + 0x0171, pci_device_10de_0171, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0171, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0172 = { + 0x0172, pci_device_10de_0172, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0172, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0173 = { + 0x0173, pci_device_10de_0173, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0173, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0174 = { + 0x0174, pci_device_10de_0174, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0174, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0175 = { + 0x0175, pci_device_10de_0175, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0175, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0176 = { + 0x0176, pci_device_10de_0176, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0176, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0177 = { + 0x0177, pci_device_10de_0177, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0177, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0178 = { + 0x0178, pci_device_10de_0178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0179 = { + 0x0179, pci_device_10de_0179, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0179, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_017a = { + 0x017a, pci_device_10de_017a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_017a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_017b = { + 0x017b, pci_device_10de_017b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_017b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_017c = { + 0x017c, pci_device_10de_017c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_017c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_017d = { + 0x017d, pci_device_10de_017d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_017d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0181 = { + 0x0181, pci_device_10de_0181, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0181, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0182 = { + 0x0182, pci_device_10de_0182, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0182, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0183 = { + 0x0183, pci_device_10de_0183, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0183, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0185 = { + 0x0185, pci_device_10de_0185, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0185, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0186 = { + 0x0186, pci_device_10de_0186, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0186, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0187 = { + 0x0187, pci_device_10de_0187, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0187, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0188 = { + 0x0188, pci_device_10de_0188, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0188, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_018a = { + 0x018a, pci_device_10de_018a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_018a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_018b = { + 0x018b, pci_device_10de_018b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_018b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_018c = { + 0x018c, pci_device_10de_018c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_018c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_018d = { + 0x018d, pci_device_10de_018d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_018d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01a0 = { + 0x01a0, pci_device_10de_01a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01a4 = { + 0x01a4, pci_device_10de_01a4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01a4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ab = { + 0x01ab, pci_device_10de_01ab, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ab, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ac = { + 0x01ac, pci_device_10de_01ac, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ac, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ad = { + 0x01ad, pci_device_10de_01ad, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ad, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b0 = { + 0x01b0, pci_device_10de_01b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b1 = { + 0x01b1, pci_device_10de_01b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b2 = { + 0x01b2, pci_device_10de_01b2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b4 = { + 0x01b4, pci_device_10de_01b4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b7 = { + 0x01b7, pci_device_10de_01b7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01b8 = { + 0x01b8, pci_device_10de_01b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01bc = { + 0x01bc, pci_device_10de_01bc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01bc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01c1 = { + 0x01c1, pci_device_10de_01c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01c2 = { + 0x01c2, pci_device_10de_01c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01c2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01c3 = { + 0x01c3, pci_device_10de_01c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01d1 = { + 0x01d1, pci_device_10de_01d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01d6 = { + 0x01d6, pci_device_10de_01d6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01d6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01d7 = { + 0x01d7, pci_device_10de_01d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01d8 = { + 0x01d8, pci_device_10de_01d8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01d8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01da = { + 0x01da, pci_device_10de_01da, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01da, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01de = { + 0x01de, pci_device_10de_01de, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01de, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01df = { + 0x01df, pci_device_10de_01df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01e0 = { + 0x01e0, pci_device_10de_01e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01e8 = { + 0x01e8, pci_device_10de_01e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01e8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ea = { + 0x01ea, pci_device_10de_01ea, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ea, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01eb = { + 0x01eb, pci_device_10de_01eb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01eb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ec = { + 0x01ec, pci_device_10de_01ec, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ec, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ed = { + 0x01ed, pci_device_10de_01ed, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ed, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ee = { + 0x01ee, pci_device_10de_01ee, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ee, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01ef = { + 0x01ef, pci_device_10de_01ef, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01ef, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_01f0 = { + 0x01f0, pci_device_10de_01f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_01f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0200 = { + 0x0200, pci_device_10de_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0201 = { + 0x0201, pci_device_10de_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0202 = { + 0x0202, pci_device_10de_0202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0203 = { + 0x0203, pci_device_10de_0203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0211 = { + 0x0211, pci_device_10de_0211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0212 = { + 0x0212, pci_device_10de_0212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0215 = { + 0x0215, pci_device_10de_0215, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0215, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0218 = { + 0x0218, pci_device_10de_0218, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0218, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0221 = { + 0x0221, pci_device_10de_0221, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0221, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0240 = { + 0x0240, pci_device_10de_0240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0241 = { + 0x0241, pci_device_10de_0241, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0241, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0242 = { + 0x0242, pci_device_10de_0242, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0242, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0243 = { + 0x0243, pci_device_10de_0243, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0243, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0244 = { + 0x0244, pci_device_10de_0244, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0244, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0245 = { + 0x0245, pci_device_10de_0245, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0245, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0246 = { + 0x0246, pci_device_10de_0246, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0246, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0247 = { + 0x0247, pci_device_10de_0247, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0247, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0248 = { + 0x0248, pci_device_10de_0248, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0248, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0249 = { + 0x0249, pci_device_10de_0249, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0249, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024a = { + 0x024a, pci_device_10de_024a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024b = { + 0x024b, pci_device_10de_024b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024c = { + 0x024c, pci_device_10de_024c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024d = { + 0x024d, pci_device_10de_024d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024e = { + 0x024e, pci_device_10de_024e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_024f = { + 0x024f, pci_device_10de_024f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_024f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0250 = { + 0x0250, pci_device_10de_0250, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0250, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0251 = { + 0x0251, pci_device_10de_0251, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0251, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0252 = { + 0x0252, pci_device_10de_0252, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0252, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0253 = { + 0x0253, pci_device_10de_0253, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0253, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0258 = { + 0x0258, pci_device_10de_0258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0259 = { + 0x0259, pci_device_10de_0259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_025b = { + 0x025b, pci_device_10de_025b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_025b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0260 = { + 0x0260, pci_device_10de_0260, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0260, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0261 = { + 0x0261, pci_device_10de_0261, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0261, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0262 = { + 0x0262, pci_device_10de_0262, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0262, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0263 = { + 0x0263, pci_device_10de_0263, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0263, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0264 = { + 0x0264, pci_device_10de_0264, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0264, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0265 = { + 0x0265, pci_device_10de_0265, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0265, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0266 = { + 0x0266, pci_device_10de_0266, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0266, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0267 = { + 0x0267, pci_device_10de_0267, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0267, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0268 = { + 0x0268, pci_device_10de_0268, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0268, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0269 = { + 0x0269, pci_device_10de_0269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026a = { + 0x026a, pci_device_10de_026a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026b = { + 0x026b, pci_device_10de_026b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026c = { + 0x026c, pci_device_10de_026c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026d = { + 0x026d, pci_device_10de_026d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026e = { + 0x026e, pci_device_10de_026e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_026f = { + 0x026f, pci_device_10de_026f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_026f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0270 = { + 0x0270, pci_device_10de_0270, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0270, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0271 = { + 0x0271, pci_device_10de_0271, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0271, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0272 = { + 0x0272, pci_device_10de_0272, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0272, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_027e = { + 0x027e, pci_device_10de_027e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_027e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_027f = { + 0x027f, pci_device_10de_027f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_027f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0280 = { + 0x0280, pci_device_10de_0280, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0280, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0281 = { + 0x0281, pci_device_10de_0281, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0281, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0282 = { + 0x0282, pci_device_10de_0282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0286 = { + 0x0286, pci_device_10de_0286, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0286, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0288 = { + 0x0288, pci_device_10de_0288, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0288, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0289 = { + 0x0289, pci_device_10de_0289, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0289, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_028c = { + 0x028c, pci_device_10de_028c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_028c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0290 = { + 0x0290, pci_device_10de_0290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0291 = { + 0x0291, pci_device_10de_0291, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0291, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0292 = { + 0x0292, pci_device_10de_0292, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0292, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0298 = { + 0x0298, pci_device_10de_0298, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0298, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0299 = { + 0x0299, pci_device_10de_0299, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0299, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_029a = { + 0x029a, pci_device_10de_029a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_029a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_029b = { + 0x029b, pci_device_10de_029b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_029b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_029c = { + 0x029c, pci_device_10de_029c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_029c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_029d = { + 0x029d, pci_device_10de_029d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_029d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_029e = { + 0x029e, pci_device_10de_029e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_029e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_029f = { + 0x029f, pci_device_10de_029f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_029f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02a0 = { + 0x02a0, pci_device_10de_02a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02e1 = { + 0x02e1, pci_device_10de_02e1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02e1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f0 = { + 0x02f0, pci_device_10de_02f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f1 = { + 0x02f1, pci_device_10de_02f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f2 = { + 0x02f2, pci_device_10de_02f2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f3 = { + 0x02f3, pci_device_10de_02f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f4 = { + 0x02f4, pci_device_10de_02f4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f5 = { + 0x02f5, pci_device_10de_02f5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f6 = { + 0x02f6, pci_device_10de_02f6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f7 = { + 0x02f7, pci_device_10de_02f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f8 = { + 0x02f8, pci_device_10de_02f8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02f9 = { + 0x02f9, pci_device_10de_02f9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02f9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02fa = { + 0x02fa, pci_device_10de_02fa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02fa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02fb = { + 0x02fb, pci_device_10de_02fb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02fb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02fc = { + 0x02fc, pci_device_10de_02fc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02fc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02fd = { + 0x02fd, pci_device_10de_02fd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02fd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02fe = { + 0x02fe, pci_device_10de_02fe, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02fe, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_02ff = { + 0x02ff, pci_device_10de_02ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_02ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0300 = { + 0x0300, pci_device_10de_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0301 = { + 0x0301, pci_device_10de_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0302 = { + 0x0302, pci_device_10de_0302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0308 = { + 0x0308, pci_device_10de_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0309 = { + 0x0309, pci_device_10de_0309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0311 = { + 0x0311, pci_device_10de_0311, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0311, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0312 = { + 0x0312, pci_device_10de_0312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0313 = { + 0x0313, pci_device_10de_0313, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0313, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0314 = { + 0x0314, pci_device_10de_0314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0316 = { + 0x0316, pci_device_10de_0316, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0316, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0317 = { + 0x0317, pci_device_10de_0317, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0317, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031a = { + 0x031a, pci_device_10de_031a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031b = { + 0x031b, pci_device_10de_031b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031c = { + 0x031c, pci_device_10de_031c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031d = { + 0x031d, pci_device_10de_031d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031e = { + 0x031e, pci_device_10de_031e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_031f = { + 0x031f, pci_device_10de_031f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_031f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0320 = { + 0x0320, pci_device_10de_0320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0321 = { + 0x0321, pci_device_10de_0321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0322 = { + 0x0322, pci_device_10de_0322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0322, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0323 = { + 0x0323, pci_device_10de_0323, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0323, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0324 = { + 0x0324, pci_device_10de_0324, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0324, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0325 = { + 0x0325, pci_device_10de_0325, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0325, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0326 = { + 0x0326, pci_device_10de_0326, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0326, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0327 = { + 0x0327, pci_device_10de_0327, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0327, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0328 = { + 0x0328, pci_device_10de_0328, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0328, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0329 = { + 0x0329, pci_device_10de_0329, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0329, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_032a = { + 0x032a, pci_device_10de_032a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_032a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_032b = { + 0x032b, pci_device_10de_032b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_032b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_032c = { + 0x032c, pci_device_10de_032c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_032c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_032d = { + 0x032d, pci_device_10de_032d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_032d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_032f = { + 0x032f, pci_device_10de_032f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_032f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0330 = { + 0x0330, pci_device_10de_0330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0331 = { + 0x0331, pci_device_10de_0331, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0331, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0332 = { + 0x0332, pci_device_10de_0332, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0332, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0333 = { + 0x0333, pci_device_10de_0333, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0333, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0334 = { + 0x0334, pci_device_10de_0334, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0334, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0338 = { + 0x0338, pci_device_10de_0338, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0338, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_033f = { + 0x033f, pci_device_10de_033f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_033f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0341 = { + 0x0341, pci_device_10de_0341, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0341, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0342 = { + 0x0342, pci_device_10de_0342, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0342, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0343 = { + 0x0343, pci_device_10de_0343, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0343, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0344 = { + 0x0344, pci_device_10de_0344, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0344, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0345 = { + 0x0345, pci_device_10de_0345, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0345, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0347 = { + 0x0347, pci_device_10de_0347, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0347, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0348 = { + 0x0348, pci_device_10de_0348, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0348, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0349 = { + 0x0349, pci_device_10de_0349, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0349, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_034b = { + 0x034b, pci_device_10de_034b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_034b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_034c = { + 0x034c, pci_device_10de_034c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_034c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_034e = { + 0x034e, pci_device_10de_034e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_034e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_034f = { + 0x034f, pci_device_10de_034f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_034f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0360 = { + 0x0360, pci_device_10de_0360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0361 = { + 0x0361, pci_device_10de_0361, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0361, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0362 = { + 0x0362, pci_device_10de_0362, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0362, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0363 = { + 0x0363, pci_device_10de_0363, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0363, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0364 = { + 0x0364, pci_device_10de_0364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0365 = { + 0x0365, pci_device_10de_0365, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0365, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0366 = { + 0x0366, pci_device_10de_0366, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0366, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0367 = { + 0x0367, pci_device_10de_0367, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0367, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0368 = { + 0x0368, pci_device_10de_0368, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0368, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0369 = { + 0x0369, pci_device_10de_0369, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0369, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_036a = { + 0x036a, pci_device_10de_036a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_036a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_036b = { + 0x036b, pci_device_10de_036b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_036b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_036c = { + 0x036c, pci_device_10de_036c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_036c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_036d = { + 0x036d, pci_device_10de_036d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_036d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_036e = { + 0x036e, pci_device_10de_036e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_036e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0370 = { + 0x0370, pci_device_10de_0370, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0370, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0371 = { + 0x0371, pci_device_10de_0371, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0371, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0372 = { + 0x0372, pci_device_10de_0372, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0372, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0373 = { + 0x0373, pci_device_10de_0373, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0373, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0374 = { + 0x0374, pci_device_10de_0374, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0374, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0375 = { + 0x0375, pci_device_10de_0375, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0375, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0376 = { + 0x0376, pci_device_10de_0376, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0376, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0377 = { + 0x0377, pci_device_10de_0377, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0377, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0378 = { + 0x0378, pci_device_10de_0378, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0378, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_037a = { + 0x037a, pci_device_10de_037a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_037a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_037e = { + 0x037e, pci_device_10de_037e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_037e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_037f = { + 0x037f, pci_device_10de_037f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_037f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0391 = { + 0x0391, pci_device_10de_0391, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0391, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0392 = { + 0x0392, pci_device_10de_0392, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0392, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0393 = { + 0x0393, pci_device_10de_0393, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0393, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0398 = { + 0x0398, pci_device_10de_0398, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0398, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_039e = { + 0x039e, pci_device_10de_039e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_039e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03a0 = { + 0x03a0, pci_device_10de_03a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03a1 = { + 0x03a1, pci_device_10de_03a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03a2 = { + 0x03a2, pci_device_10de_03a2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03a2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03a3 = { + 0x03a3, pci_device_10de_03a3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03a3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03a4 = { + 0x03a4, pci_device_10de_03a4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03a4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03a5 = { + 0x03a5, pci_device_10de_03a5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03a5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03a6 = { + 0x03a6, pci_device_10de_03a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03a7 = { + 0x03a7, pci_device_10de_03a7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03a7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03a8 = { + 0x03a8, pci_device_10de_03a8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03a8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03a9 = { + 0x03a9, pci_device_10de_03a9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03a9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03aa = { + 0x03aa, pci_device_10de_03aa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03aa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03ab = { + 0x03ab, pci_device_10de_03ab, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03ab, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03ac = { + 0x03ac, pci_device_10de_03ac, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03ac, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03ad = { + 0x03ad, pci_device_10de_03ad, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03ad, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03ae = { + 0x03ae, pci_device_10de_03ae, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03ae, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03af = { + 0x03af, pci_device_10de_03af, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03af, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03b0 = { + 0x03b0, pci_device_10de_03b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03b1 = { + 0x03b1, pci_device_10de_03b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03b2 = { + 0x03b2, pci_device_10de_03b2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03b2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03b3 = { + 0x03b3, pci_device_10de_03b3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03b3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03b4 = { + 0x03b4, pci_device_10de_03b4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03b4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03b5 = { + 0x03b5, pci_device_10de_03b5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03b5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03b6 = { + 0x03b6, pci_device_10de_03b6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03b6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03b7 = { + 0x03b7, pci_device_10de_03b7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03b7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03b8 = { + 0x03b8, pci_device_10de_03b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03b9 = { + 0x03b9, pci_device_10de_03b9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03b9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03ba = { + 0x03ba, pci_device_10de_03ba, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03ba, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03bb = { + 0x03bb, pci_device_10de_03bb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03bb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03d0 = { + 0x03d0, pci_device_10de_03d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03d1 = { + 0x03d1, pci_device_10de_03d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03d2 = { + 0x03d2, pci_device_10de_03d2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03d2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03d5 = { + 0x03d5, pci_device_10de_03d5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03d5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03e0 = { + 0x03e0, pci_device_10de_03e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03e1 = { + 0x03e1, pci_device_10de_03e1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03e1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03e2 = { + 0x03e2, pci_device_10de_03e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03e3 = { + 0x03e3, pci_device_10de_03e3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03e3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03e4 = { + 0x03e4, pci_device_10de_03e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03e5 = { + 0x03e5, pci_device_10de_03e5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03e5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03e6 = { + 0x03e6, pci_device_10de_03e6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03e6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03e7 = { + 0x03e7, pci_device_10de_03e7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03e7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03e8 = { + 0x03e8, pci_device_10de_03e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03e8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03e9 = { + 0x03e9, pci_device_10de_03e9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03e9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03ea = { + 0x03ea, pci_device_10de_03ea, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03ea, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03eb = { + 0x03eb, pci_device_10de_03eb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03eb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03ec = { + 0x03ec, pci_device_10de_03ec, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03ec, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03ee = { + 0x03ee, pci_device_10de_03ee, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03ee, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03ef = { + 0x03ef, pci_device_10de_03ef, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03ef, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03f0 = { + 0x03f0, pci_device_10de_03f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03f1 = { + 0x03f1, pci_device_10de_03f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03f2 = { + 0x03f2, pci_device_10de_03f2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03f2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03f3 = { + 0x03f3, pci_device_10de_03f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03f4 = { + 0x03f4, pci_device_10de_03f4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03f4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03f5 = { + 0x03f5, pci_device_10de_03f5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03f5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03f6 = { + 0x03f6, pci_device_10de_03f6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03f6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_03f7 = { + 0x03f7, pci_device_10de_03f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_03f7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0440 = { + 0x0440, pci_device_10de_0440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0441 = { + 0x0441, pci_device_10de_0441, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0441, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0442 = { + 0x0442, pci_device_10de_0442, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0442, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0443 = { + 0x0443, pci_device_10de_0443, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0443, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0444 = { + 0x0444, pci_device_10de_0444, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0444, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0445 = { + 0x0445, pci_device_10de_0445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0446 = { + 0x0446, pci_device_10de_0446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0447 = { + 0x0447, pci_device_10de_0447, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0447, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0448 = { + 0x0448, pci_device_10de_0448, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0448, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0449 = { + 0x0449, pci_device_10de_0449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_044a = { + 0x044a, pci_device_10de_044a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_044a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_044b = { + 0x044b, pci_device_10de_044b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_044b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_044c = { + 0x044c, pci_device_10de_044c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_044c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_044d = { + 0x044d, pci_device_10de_044d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_044d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_044e = { + 0x044e, pci_device_10de_044e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_044e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_044f = { + 0x044f, pci_device_10de_044f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_044f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0450 = { + 0x0450, pci_device_10de_0450, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0450, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0451 = { + 0x0451, pci_device_10de_0451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0452 = { + 0x0452, pci_device_10de_0452, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0452, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0453 = { + 0x0453, pci_device_10de_0453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0454 = { + 0x0454, pci_device_10de_0454, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0454, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0455 = { + 0x0455, pci_device_10de_0455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0456 = { + 0x0456, pci_device_10de_0456, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0456, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0457 = { + 0x0457, pci_device_10de_0457, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0457, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0458 = { + 0x0458, pci_device_10de_0458, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0458, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_0459 = { + 0x0459, pci_device_10de_0459, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_0459, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_045a = { + 0x045a, pci_device_10de_045a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_045a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_045c = { + 0x045c, pci_device_10de_045c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_045c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_045d = { + 0x045d, pci_device_10de_045d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_045d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_045e = { + 0x045e, pci_device_10de_045e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_045e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10de_045f = { + 0x045f, pci_device_10de_045f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10de_045f, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10df_1ae5 = { + 0x1ae5, pci_device_10df_1ae5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_1ae5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f085 = { + 0xf085, pci_device_10df_f085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f095 = { + 0xf095, pci_device_10df_f095, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f095, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f098 = { + 0xf098, pci_device_10df_f098, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f098, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0a1 = { + 0xf0a1, pci_device_10df_f0a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0a5 = { + 0xf0a5, pci_device_10df_f0a5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0a5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0b5 = { + 0xf0b5, pci_device_10df_f0b5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0b5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0d1 = { + 0xf0d1, pci_device_10df_f0d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0d5 = { + 0xf0d5, pci_device_10df_f0d5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0d5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0e1 = { + 0xf0e1, pci_device_10df_f0e1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0e1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0e5 = { + 0xf0e5, pci_device_10df_f0e5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0e5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f0f5 = { + 0xf0f5, pci_device_10df_f0f5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f0f5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f700 = { + 0xf700, pci_device_10df_f700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f701 = { + 0xf701, pci_device_10df_f701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f701, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f800 = { + 0xf800, pci_device_10df_f800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f801 = { + 0xf801, pci_device_10df_f801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f900 = { + 0xf900, pci_device_10df_f900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f901 = { + 0xf901, pci_device_10df_f901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f901, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f980 = { + 0xf980, pci_device_10df_f980, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f980, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f981 = { + 0xf981, pci_device_10df_f981, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f981, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_f982 = { + 0xf982, pci_device_10df_f982, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_f982, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fa00 = { + 0xfa00, pci_device_10df_fa00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fa00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fb00 = { + 0xfb00, pci_device_10df_fb00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fb00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fc00 = { + 0xfc00, pci_device_10df_fc00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fc00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fc10 = { + 0xfc10, pci_device_10df_fc10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fc10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fc20 = { + 0xfc20, pci_device_10df_fc20, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fc20, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fd00 = { + 0xfd00, pci_device_10df_fd00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fd00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_fe00 = { + 0xfe00, pci_device_10df_fe00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_fe00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10df_ff00 = { + 0xff00, pci_device_10df_ff00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10df_ff00, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_10e0_5026 = { + 0x5026, pci_device_10e0_5026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_5026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_5027 = { + 0x5027, pci_device_10e0_5027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_5027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_5028 = { + 0x5028, pci_device_10e0_5028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_5028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_8849 = { + 0x8849, pci_device_10e0_8849, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_8849, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_8853 = { + 0x8853, pci_device_10e0_8853, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_8853, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e0_9128 = { + 0x9128, pci_device_10e0_9128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e0_9128, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10e1_0391 = { + 0x0391, pci_device_10e1_0391, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e1_0391, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e1_690c = { + 0x690c, pci_device_10e1_690c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e1_690c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e1_dc29 = { + 0xdc29, pci_device_10e1_dc29, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e1_dc29, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10e3_0000 = { + 0x0000, pci_device_10e3_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e3_0108 = { + 0x0108, pci_device_10e3_0108, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_0108, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e3_0148 = { + 0x0148, pci_device_10e3_0148, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_0148, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e3_0860 = { + 0x0860, pci_device_10e3_0860, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_0860, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e3_0862 = { + 0x0862, pci_device_10e3_0862, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_0862, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e3_8260 = { + 0x8260, pci_device_10e3_8260, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_8260, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e3_8261 = { + 0x8261, pci_device_10e3_8261, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_8261, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e3_a108 = { + 0xa108, pci_device_10e3_a108, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e3_a108, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10e4_8029 = { + 0x8029, pci_device_10e4_8029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e4_8029, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10e8_1072 = { + 0x1072, pci_device_10e8_1072, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_1072, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_2011 = { + 0x2011, pci_device_10e8_2011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_2011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_4750 = { + 0x4750, pci_device_10e8_4750, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_4750, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_5920 = { + 0x5920, pci_device_10e8_5920, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_5920, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8043 = { + 0x8043, pci_device_10e8_8043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8062 = { + 0x8062, pci_device_10e8_8062, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8062, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_807d = { + 0x807d, pci_device_10e8_807d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_807d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8088 = { + 0x8088, pci_device_10e8_8088, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8088, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8089 = { + 0x8089, pci_device_10e8_8089, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8089, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_809c = { + 0x809c, pci_device_10e8_809c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_809c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_80d7 = { + 0x80d7, pci_device_10e8_80d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_80d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_80d9 = { + 0x80d9, pci_device_10e8_80d9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_80d9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_80da = { + 0x80da, pci_device_10e8_80da, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_80da, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_811a = { + 0x811a, pci_device_10e8_811a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_811a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_814c = { + 0x814c, pci_device_10e8_814c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_814c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8170 = { + 0x8170, pci_device_10e8_8170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_81e6 = { + 0x81e6, pci_device_10e8_81e6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_81e6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8291 = { + 0x8291, pci_device_10e8_8291, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8291, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82c4 = { + 0x82c4, pci_device_10e8_82c4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82c4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82c5 = { + 0x82c5, pci_device_10e8_82c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82c6 = { + 0x82c6, pci_device_10e8_82c6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82c6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82c7 = { + 0x82c7, pci_device_10e8_82c7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82c7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82ca = { + 0x82ca, pci_device_10e8_82ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82db = { + 0x82db, pci_device_10e8_82db, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82db, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_82e2 = { + 0x82e2, pci_device_10e8_82e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_82e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10e8_8851 = { + 0x8851, pci_device_10e8_8851, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10e8_8851, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_10ea_1680 = { + 0x1680, pci_device_10ea_1680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_1680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_1682 = { + 0x1682, pci_device_10ea_1682, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_1682, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_1683 = { + 0x1683, pci_device_10ea_1683, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_1683, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_2000 = { + 0x2000, pci_device_10ea_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_2010 = { + 0x2010, pci_device_10ea_2010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_2010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_5000 = { + 0x5000, pci_device_10ea_5000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_5000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_5050 = { + 0x5050, pci_device_10ea_5050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_5050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_5202 = { + 0x5202, pci_device_10ea_5202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_5202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ea_5252 = { + 0x5252, pci_device_10ea_5252, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ea_5252, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10eb_0101 = { + 0x0101, pci_device_10eb_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10eb_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10eb_8111 = { + 0x8111, pci_device_10eb_8111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10eb_8111, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ec_0139 = { + 0x0139, pci_device_10ec_0139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_0139, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_0883 = { + 0x0883, pci_device_10ec_0883, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_0883, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8029 = { + 0x8029, pci_device_10ec_8029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8129 = { + 0x8129, pci_device_10ec_8129, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8129, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8136 = { + 0x8136, pci_device_10ec_8136, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8136, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8138 = { + 0x8138, pci_device_10ec_8138, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8138, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8139 = { + 0x8139, pci_device_10ec_8139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8139, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8167 = { + 0x8167, pci_device_10ec_8167, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8167, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8168 = { + 0x8168, pci_device_10ec_8168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8169 = { + 0x8169, pci_device_10ec_8169, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8169, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8180 = { + 0x8180, pci_device_10ec_8180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8185 = { + 0x8185, pci_device_10ec_8185, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8185, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ec_8197 = { + 0x8197, pci_device_10ec_8197, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ec_8197, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ed_7310 = { + 0x7310, pci_device_10ed_7310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ed_7310, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ee_0205 = { + 0x0205, pci_device_10ee_0205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_0205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_0210 = { + 0x0210, pci_device_10ee_0210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_0210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_0314 = { + 0x0314, pci_device_10ee_0314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_0314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_0405 = { + 0x0405, pci_device_10ee_0405, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_0405, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_0410 = { + 0x0410, pci_device_10ee_0410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_0410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc0 = { + 0x3fc0, pci_device_10ee_3fc0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc1 = { + 0x3fc1, pci_device_10ee_3fc1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc2 = { + 0x3fc2, pci_device_10ee_3fc2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc3 = { + 0x3fc3, pci_device_10ee_3fc3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc4 = { + 0x3fc4, pci_device_10ee_3fc4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc5 = { + 0x3fc5, pci_device_10ee_3fc5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_3fc6 = { + 0x3fc6, pci_device_10ee_3fc6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_3fc6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_8381 = { + 0x8381, pci_device_10ee_8381, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_8381, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10ee_d154 = { + 0xd154, pci_device_10ee_d154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ee_d154, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10ef_8154 = { + 0x8154, pci_device_10ef_8154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10ef_8154, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10f1_2865 = { + 0x2865, pci_device_10f1_2865, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10f1_2865, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10f5_a001 = { + 0xa001, pci_device_10f5_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10f5_a001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10fa_000c = { + 0x000c, pci_device_10fa_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10fa_000c, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10fb_186f = { + 0x186f, pci_device_10fb_186f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10fb_186f, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_10fc_0003 = { + 0x0003, pci_device_10fc_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10fc_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_10fc_0005 = { + 0x0005, pci_device_10fc_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_10fc_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1101_1060 = { + 0x1060, pci_device_1101_1060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_1060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_1622 = { + 0x1622, pci_device_1101_1622, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_1622, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_9100 = { + 0x9100, pci_device_1101_9100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_9100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_9400 = { + 0x9400, pci_device_1101_9400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_9400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_9401 = { + 0x9401, pci_device_1101_9401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_9401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_9500 = { + 0x9500, pci_device_1101_9500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_9500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1101_9502 = { + 0x9502, pci_device_1101_9502, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1101_9502, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1102_0002 = { + 0x0002, pci_device_1102_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_0002, +#else + NULL, +#endif + 0x0401 +}; +static const pciDeviceInfo pci_dev_info_1102_0004 = { + 0x0004, pci_device_1102_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_0005 = { + 0x0005, pci_device_1102_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_0006 = { + 0x0006, pci_device_1102_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_0007 = { + 0x0007, pci_device_1102_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_0008 = { + 0x0008, pci_device_1102_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_4001 = { + 0x4001, pci_device_1102_4001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_4001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_7002 = { + 0x7002, pci_device_1102_7002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_7002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_7003 = { + 0x7003, pci_device_1102_7003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_7003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_7004 = { + 0x7004, pci_device_1102_7004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_7004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_7005 = { + 0x7005, pci_device_1102_7005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_7005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_8064 = { + 0x8064, pci_device_1102_8064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_8064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1102_8938 = { + 0x8938, pci_device_1102_8938, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1102_8938, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1103_0003 = { + 0x0003, pci_device_1103_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0004 = { + 0x0004, pci_device_1103_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0005 = { + 0x0005, pci_device_1103_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0006 = { + 0x0006, pci_device_1103_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0007 = { + 0x0007, pci_device_1103_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0008 = { + 0x0008, pci_device_1103_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1103_0009 = { + 0x0009, pci_device_1103_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1103_0009, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1105_1105 = { + 0x1105, pci_device_1105_1105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_1105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8300 = { + 0x8300, pci_device_1105_8300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8400 = { + 0x8400, pci_device_1105_8400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8401 = { + 0x8401, pci_device_1105_8401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8470 = { + 0x8470, pci_device_1105_8470, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8470, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8471 = { + 0x8471, pci_device_1105_8471, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8471, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8475 = { + 0x8475, pci_device_1105_8475, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8475, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8476 = { + 0x8476, pci_device_1105_8476, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8476, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8485 = { + 0x8485, pci_device_1105_8485, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8485, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1105_8486 = { + 0x8486, pci_device_1105_8486, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1105_8486, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1106_0102 = { + 0x0102, pci_device_1106_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0130 = { + 0x0130, pci_device_1106_0130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0204 = { + 0x0204, pci_device_1106_0204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0208 = { + 0x0208, pci_device_1106_0208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0238 = { + 0x0238, pci_device_1106_0238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0258 = { + 0x0258, pci_device_1106_0258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0259 = { + 0x0259, pci_device_1106_0259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0269 = { + 0x0269, pci_device_1106_0269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0282 = { + 0x0282, pci_device_1106_0282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0290 = { + 0x0290, pci_device_1106_0290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0293 = { + 0x0293, pci_device_1106_0293, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0293, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0296 = { + 0x0296, pci_device_1106_0296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0305 = { + 0x0305, pci_device_1106_0305, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0305, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0308 = { + 0x0308, pci_device_1106_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0314 = { + 0x0314, pci_device_1106_0314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0324 = { + 0x0324, pci_device_1106_0324, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0324, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0327 = { + 0x0327, pci_device_1106_0327, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0327, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0336 = { + 0x0336, pci_device_1106_0336, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0336, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0340 = { + 0x0340, pci_device_1106_0340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0351 = { + 0x0351, pci_device_1106_0351, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0351, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0364 = { + 0x0364, pci_device_1106_0364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0391 = { + 0x0391, pci_device_1106_0391, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0391, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0501 = { + 0x0501, pci_device_1106_0501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0505 = { + 0x0505, pci_device_1106_0505, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0505, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0561 = { + 0x0561, pci_device_1106_0561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0571 = { + 0x0571, pci_device_1106_0571, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0571, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0576 = { + 0x0576, pci_device_1106_0576, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0576, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0585 = { + 0x0585, pci_device_1106_0585, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0585, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0586 = { + 0x0586, pci_device_1106_0586, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0586, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0591 = { + 0x0591, pci_device_1106_0591, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0591, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0595 = { + 0x0595, pci_device_1106_0595, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0595, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0596 = { + 0x0596, pci_device_1106_0596, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0596, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0597 = { + 0x0597, pci_device_1106_0597, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0597, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0598 = { + 0x0598, pci_device_1106_0598, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0598, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0601 = { + 0x0601, pci_device_1106_0601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0605 = { + 0x0605, pci_device_1106_0605, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0605, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0680 = { + 0x0680, pci_device_1106_0680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0686 = { + 0x0686, pci_device_1106_0686, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0686, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0691 = { + 0x0691, pci_device_1106_0691, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0691, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0693 = { + 0x0693, pci_device_1106_0693, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0693, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0698 = { + 0x0698, pci_device_1106_0698, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0698, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_0926 = { + 0x0926, pci_device_1106_0926, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_0926, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1000 = { + 0x1000, pci_device_1106_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1106 = { + 0x1106, pci_device_1106_1106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1204 = { + 0x1204, pci_device_1106_1204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1208 = { + 0x1208, pci_device_1106_1208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1238 = { + 0x1238, pci_device_1106_1238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1258 = { + 0x1258, pci_device_1106_1258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1259 = { + 0x1259, pci_device_1106_1259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1269 = { + 0x1269, pci_device_1106_1269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1282 = { + 0x1282, pci_device_1106_1282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1290 = { + 0x1290, pci_device_1106_1290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1293 = { + 0x1293, pci_device_1106_1293, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1293, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1296 = { + 0x1296, pci_device_1106_1296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1308 = { + 0x1308, pci_device_1106_1308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1314 = { + 0x1314, pci_device_1106_1314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1324 = { + 0x1324, pci_device_1106_1324, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1324, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1327 = { + 0x1327, pci_device_1106_1327, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1327, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1336 = { + 0x1336, pci_device_1106_1336, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1336, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1340 = { + 0x1340, pci_device_1106_1340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1351 = { + 0x1351, pci_device_1106_1351, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1351, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1364 = { + 0x1364, pci_device_1106_1364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1571 = { + 0x1571, pci_device_1106_1571, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1571, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_1595 = { + 0x1595, pci_device_1106_1595, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_1595, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2204 = { + 0x2204, pci_device_1106_2204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2208 = { + 0x2208, pci_device_1106_2208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2238 = { + 0x2238, pci_device_1106_2238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2258 = { + 0x2258, pci_device_1106_2258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2259 = { + 0x2259, pci_device_1106_2259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2269 = { + 0x2269, pci_device_1106_2269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2282 = { + 0x2282, pci_device_1106_2282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2290 = { + 0x2290, pci_device_1106_2290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2293 = { + 0x2293, pci_device_1106_2293, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2293, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2296 = { + 0x2296, pci_device_1106_2296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2308 = { + 0x2308, pci_device_1106_2308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2314 = { + 0x2314, pci_device_1106_2314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2324 = { + 0x2324, pci_device_1106_2324, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2324, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2327 = { + 0x2327, pci_device_1106_2327, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2327, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2336 = { + 0x2336, pci_device_1106_2336, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2336, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2340 = { + 0x2340, pci_device_1106_2340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2351 = { + 0x2351, pci_device_1106_2351, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2351, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_2364 = { + 0x2364, pci_device_1106_2364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_2364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_287a = { + 0x287a, pci_device_1106_287a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_287a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_287b = { + 0x287b, pci_device_1106_287b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_287b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_287c = { + 0x287c, pci_device_1106_287c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_287c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_287d = { + 0x287d, pci_device_1106_287d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_287d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_287e = { + 0x287e, pci_device_1106_287e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_287e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3022 = { + 0x3022, pci_device_1106_3022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3038 = { + 0x3038, pci_device_1106_3038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3040 = { + 0x3040, pci_device_1106_3040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3043 = { + 0x3043, pci_device_1106_3043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3044 = { + 0x3044, pci_device_1106_3044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3050 = { + 0x3050, pci_device_1106_3050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3051 = { + 0x3051, pci_device_1106_3051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3053 = { + 0x3053, pci_device_1106_3053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3057 = { + 0x3057, pci_device_1106_3057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3058 = { + 0x3058, pci_device_1106_3058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3059 = { + 0x3059, pci_device_1106_3059, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3059, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3065 = { + 0x3065, pci_device_1106_3065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3068 = { + 0x3068, pci_device_1106_3068, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3068, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3074 = { + 0x3074, pci_device_1106_3074, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3074, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3091 = { + 0x3091, pci_device_1106_3091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3099 = { + 0x3099, pci_device_1106_3099, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3099, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3101 = { + 0x3101, pci_device_1106_3101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3102 = { + 0x3102, pci_device_1106_3102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3103 = { + 0x3103, pci_device_1106_3103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3104 = { + 0x3104, pci_device_1106_3104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3106 = { + 0x3106, pci_device_1106_3106, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3106, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3108 = { + 0x3108, pci_device_1106_3108, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3108, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3109 = { + 0x3109, pci_device_1106_3109, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3109, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3112 = { + 0x3112, pci_device_1106_3112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3113 = { + 0x3113, pci_device_1106_3113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3116 = { + 0x3116, pci_device_1106_3116, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3116, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3118 = { + 0x3118, pci_device_1106_3118, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3118, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3119 = { + 0x3119, pci_device_1106_3119, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3119, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3122 = { + 0x3122, pci_device_1106_3122, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3122, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3123 = { + 0x3123, pci_device_1106_3123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3128 = { + 0x3128, pci_device_1106_3128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3128, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3133 = { + 0x3133, pci_device_1106_3133, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3133, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3147 = { + 0x3147, pci_device_1106_3147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3148 = { + 0x3148, pci_device_1106_3148, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3148, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3149 = { + 0x3149, pci_device_1106_3149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3156 = { + 0x3156, pci_device_1106_3156, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3156, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3164 = { + 0x3164, pci_device_1106_3164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3168 = { + 0x3168, pci_device_1106_3168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3177 = { + 0x3177, pci_device_1106_3177, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3177, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3178 = { + 0x3178, pci_device_1106_3178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3188 = { + 0x3188, pci_device_1106_3188, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3188, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3189 = { + 0x3189, pci_device_1106_3189, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3189, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3204 = { + 0x3204, pci_device_1106_3204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3205 = { + 0x3205, pci_device_1106_3205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3208 = { + 0x3208, pci_device_1106_3208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3213 = { + 0x3213, pci_device_1106_3213, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3213, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3218 = { + 0x3218, pci_device_1106_3218, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3218, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3227 = { + 0x3227, pci_device_1106_3227, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3227, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3238 = { + 0x3238, pci_device_1106_3238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3249 = { + 0x3249, pci_device_1106_3249, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3249, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_324a = { + 0x324a, pci_device_1106_324a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_324a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_324b = { + 0x324b, pci_device_1106_324b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_324b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_324e = { + 0x324e, pci_device_1106_324e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_324e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3258 = { + 0x3258, pci_device_1106_3258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3259 = { + 0x3259, pci_device_1106_3259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3269 = { + 0x3269, pci_device_1106_3269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3282 = { + 0x3282, pci_device_1106_3282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3287 = { + 0x3287, pci_device_1106_3287, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3287, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3288 = { + 0x3288, pci_device_1106_3288, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3288, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3290 = { + 0x3290, pci_device_1106_3290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3296 = { + 0x3296, pci_device_1106_3296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3324 = { + 0x3324, pci_device_1106_3324, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3324, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3327 = { + 0x3327, pci_device_1106_3327, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3327, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3336 = { + 0x3336, pci_device_1106_3336, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3336, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3337 = { + 0x3337, pci_device_1106_3337, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3337, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3340 = { + 0x3340, pci_device_1106_3340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3344 = { + 0x3344, pci_device_1106_3344, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3344, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3349 = { + 0x3349, pci_device_1106_3349, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3349, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3351 = { + 0x3351, pci_device_1106_3351, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3351, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_3364 = { + 0x3364, pci_device_1106_3364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_3364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_337a = { + 0x337a, pci_device_1106_337a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_337a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_337b = { + 0x337b, pci_device_1106_337b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_337b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4149 = { + 0x4149, pci_device_1106_4149, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4149, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4204 = { + 0x4204, pci_device_1106_4204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4208 = { + 0x4208, pci_device_1106_4208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4238 = { + 0x4238, pci_device_1106_4238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4258 = { + 0x4258, pci_device_1106_4258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4259 = { + 0x4259, pci_device_1106_4259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4269 = { + 0x4269, pci_device_1106_4269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4282 = { + 0x4282, pci_device_1106_4282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4290 = { + 0x4290, pci_device_1106_4290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4293 = { + 0x4293, pci_device_1106_4293, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4293, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4296 = { + 0x4296, pci_device_1106_4296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4308 = { + 0x4308, pci_device_1106_4308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4314 = { + 0x4314, pci_device_1106_4314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4324 = { + 0x4324, pci_device_1106_4324, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4324, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4327 = { + 0x4327, pci_device_1106_4327, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4327, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4336 = { + 0x4336, pci_device_1106_4336, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4336, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4340 = { + 0x4340, pci_device_1106_4340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4351 = { + 0x4351, pci_device_1106_4351, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4351, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_4364 = { + 0x4364, pci_device_1106_4364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_4364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5030 = { + 0x5030, pci_device_1106_5030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5208 = { + 0x5208, pci_device_1106_5208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5238 = { + 0x5238, pci_device_1106_5238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5290 = { + 0x5290, pci_device_1106_5290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5308 = { + 0x5308, pci_device_1106_5308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5327 = { + 0x5327, pci_device_1106_5327, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5327, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5336 = { + 0x5336, pci_device_1106_5336, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5336, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5340 = { + 0x5340, pci_device_1106_5340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5351 = { + 0x5351, pci_device_1106_5351, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5351, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_5364 = { + 0x5364, pci_device_1106_5364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_5364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_6100 = { + 0x6100, pci_device_1106_6100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_6100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_6327 = { + 0x6327, pci_device_1106_6327, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_6327, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7204 = { + 0x7204, pci_device_1106_7204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7205 = { + 0x7205, pci_device_1106_7205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7208 = { + 0x7208, pci_device_1106_7208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7238 = { + 0x7238, pci_device_1106_7238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7258 = { + 0x7258, pci_device_1106_7258, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7258, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7259 = { + 0x7259, pci_device_1106_7259, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7259, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7269 = { + 0x7269, pci_device_1106_7269, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7269, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7282 = { + 0x7282, pci_device_1106_7282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7282, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7290 = { + 0x7290, pci_device_1106_7290, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7290, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7293 = { + 0x7293, pci_device_1106_7293, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7293, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7296 = { + 0x7296, pci_device_1106_7296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7308 = { + 0x7308, pci_device_1106_7308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7314 = { + 0x7314, pci_device_1106_7314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7324 = { + 0x7324, pci_device_1106_7324, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7324, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7327 = { + 0x7327, pci_device_1106_7327, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7327, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7336 = { + 0x7336, pci_device_1106_7336, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7336, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7340 = { + 0x7340, pci_device_1106_7340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7351 = { + 0x7351, pci_device_1106_7351, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7351, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_7364 = { + 0x7364, pci_device_1106_7364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_7364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8231 = { + 0x8231, pci_device_1106_8231, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8231, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8235 = { + 0x8235, pci_device_1106_8235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8305 = { + 0x8305, pci_device_1106_8305, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8305, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8324 = { + 0x8324, pci_device_1106_8324, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8324, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8391 = { + 0x8391, pci_device_1106_8391, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8391, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8501 = { + 0x8501, pci_device_1106_8501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8596 = { + 0x8596, pci_device_1106_8596, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8596, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8597 = { + 0x8597, pci_device_1106_8597, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8597, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8598 = { + 0x8598, pci_device_1106_8598, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8598, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8601 = { + 0x8601, pci_device_1106_8601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8605 = { + 0x8605, pci_device_1106_8605, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8605, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8691 = { + 0x8691, pci_device_1106_8691, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8691, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_8693 = { + 0x8693, pci_device_1106_8693, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_8693, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_a208 = { + 0xa208, pci_device_1106_a208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_a208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_a238 = { + 0xa238, pci_device_1106_a238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_a238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_a327 = { + 0xa327, pci_device_1106_a327, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_a327, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_a364 = { + 0xa364, pci_device_1106_a364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_a364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b091 = { + 0xb091, pci_device_1106_b091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b099 = { + 0xb099, pci_device_1106_b099, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b099, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b101 = { + 0xb101, pci_device_1106_b101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b102 = { + 0xb102, pci_device_1106_b102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b103 = { + 0xb103, pci_device_1106_b103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b112 = { + 0xb112, pci_device_1106_b112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b113 = { + 0xb113, pci_device_1106_b113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b115 = { + 0xb115, pci_device_1106_b115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b115, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b168 = { + 0xb168, pci_device_1106_b168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b188 = { + 0xb188, pci_device_1106_b188, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b188, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b198 = { + 0xb198, pci_device_1106_b198, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b198, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b213 = { + 0xb213, pci_device_1106_b213, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b213, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_b999 = { + 0xb999, pci_device_1106_b999, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_b999, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_c208 = { + 0xc208, pci_device_1106_c208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_c208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_c238 = { + 0xc238, pci_device_1106_c238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_c238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_c327 = { + 0xc327, pci_device_1106_c327, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_c327, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_c340 = { + 0xc340, pci_device_1106_c340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_c340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_c364 = { + 0xc364, pci_device_1106_c364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_c364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_d104 = { + 0xd104, pci_device_1106_d104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_d104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_d208 = { + 0xd208, pci_device_1106_d208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_d208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_d213 = { + 0xd213, pci_device_1106_d213, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_d213, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_d238 = { + 0xd238, pci_device_1106_d238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_d238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_d340 = { + 0xd340, pci_device_1106_d340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_d340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_e208 = { + 0xe208, pci_device_1106_e208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_e208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_e238 = { + 0xe238, pci_device_1106_e238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_e238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_e340 = { + 0xe340, pci_device_1106_e340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_e340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_f208 = { + 0xf208, pci_device_1106_f208, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_f208, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_f238 = { + 0xf238, pci_device_1106_f238, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_f238, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1106_f340 = { + 0xf340, pci_device_1106_f340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1106_f340, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1107_0576 = { + 0x0576, pci_device_1107_0576, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1107_0576, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1108_0100 = { + 0x0100, pci_device_1108_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0101 = { + 0x0101, pci_device_1108_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0105 = { + 0x0105, pci_device_1108_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0108 = { + 0x0108, pci_device_1108_0108, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0108, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0138 = { + 0x0138, pci_device_1108_0138, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0138, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_0139 = { + 0x0139, pci_device_1108_0139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_0139, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_013c = { + 0x013c, pci_device_1108_013c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_013c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1108_013d = { + 0x013d, pci_device_1108_013d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1108_013d, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1109_1400 = { + 0x1400, pci_device_1109_1400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1109_1400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_110a_0002 = { + 0x0002, pci_device_110a_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_0005 = { + 0x0005, pci_device_110a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_0006 = { + 0x0006, pci_device_110a_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_0015 = { + 0x0015, pci_device_110a_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_001d = { + 0x001d, pci_device_110a_001d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_001d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_007b = { + 0x007b, pci_device_110a_007b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_007b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_007c = { + 0x007c, pci_device_110a_007c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_007c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_007d = { + 0x007d, pci_device_110a_007d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_007d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_2101 = { + 0x2101, pci_device_110a_2101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_2101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_2102 = { + 0x2102, pci_device_110a_2102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_2102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_2104 = { + 0x2104, pci_device_110a_2104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_2104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_3142 = { + 0x3142, pci_device_110a_3142, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_3142, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_4021 = { + 0x4021, pci_device_110a_4021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_4021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_4029 = { + 0x4029, pci_device_110a_4029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_4029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_4942 = { + 0x4942, pci_device_110a_4942, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_4942, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110a_6120 = { + 0x6120, pci_device_110a_6120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110a_6120, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_110b_0001 = { + 0x0001, pci_device_110b_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110b_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_110b_0004 = { + 0x0004, pci_device_110b_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_110b_0004, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1110_6037 = { + 0x6037, pci_device_1110_6037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1110_6037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1110_6073 = { + 0x6073, pci_device_1110_6073, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1110_6073, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1112_2200 = { + 0x2200, pci_device_1112_2200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1112_2200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1112_2300 = { + 0x2300, pci_device_1112_2300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1112_2300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1112_2340 = { + 0x2340, pci_device_1112_2340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1112_2340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1112_2400 = { + 0x2400, pci_device_1112_2400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1112_2400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1113_1211 = { + 0x1211, pci_device_1113_1211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_1211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_1216 = { + 0x1216, pci_device_1113_1216, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_1216, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_1217 = { + 0x1217, pci_device_1113_1217, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_1217, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_5105 = { + 0x5105, pci_device_1113_5105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_5105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_9211 = { + 0x9211, pci_device_1113_9211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_9211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_9511 = { + 0x9511, pci_device_1113_9511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_9511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_d301 = { + 0xd301, pci_device_1113_d301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_d301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1113_ec02 = { + 0xec02, pci_device_1113_ec02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1113_ec02, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1114_0506 = { + 0x0506, pci_device_1114_0506, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1114_0506, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1116_0022 = { + 0x0022, pci_device_1116_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0023 = { + 0x0023, pci_device_1116_0023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0024 = { + 0x0024, pci_device_1116_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0025 = { + 0x0025, pci_device_1116_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0026 = { + 0x0026, pci_device_1116_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0027 = { + 0x0027, pci_device_1116_0027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1116_0028 = { + 0x0028, pci_device_1116_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1116_0028, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1117_9500 = { + 0x9500, pci_device_1117_9500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1117_9500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1117_9501 = { + 0x9501, pci_device_1117_9501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1117_9501, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1119_0000 = { + 0x0000, pci_device_1119_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0001 = { + 0x0001, pci_device_1119_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0002 = { + 0x0002, pci_device_1119_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0003 = { + 0x0003, pci_device_1119_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0004 = { + 0x0004, pci_device_1119_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0005 = { + 0x0005, pci_device_1119_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0006 = { + 0x0006, pci_device_1119_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0007 = { + 0x0007, pci_device_1119_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0008 = { + 0x0008, pci_device_1119_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0009 = { + 0x0009, pci_device_1119_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_000a = { + 0x000a, pci_device_1119_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_000b = { + 0x000b, pci_device_1119_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_000c = { + 0x000c, pci_device_1119_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_000d = { + 0x000d, pci_device_1119_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0010 = { + 0x0010, pci_device_1119_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0011 = { + 0x0011, pci_device_1119_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0012 = { + 0x0012, pci_device_1119_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0013 = { + 0x0013, pci_device_1119_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0100 = { + 0x0100, pci_device_1119_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0101 = { + 0x0101, pci_device_1119_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0102 = { + 0x0102, pci_device_1119_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0103 = { + 0x0103, pci_device_1119_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0104 = { + 0x0104, pci_device_1119_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0105 = { + 0x0105, pci_device_1119_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0110 = { + 0x0110, pci_device_1119_0110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0111 = { + 0x0111, pci_device_1119_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0112 = { + 0x0112, pci_device_1119_0112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0113 = { + 0x0113, pci_device_1119_0113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0114 = { + 0x0114, pci_device_1119_0114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0114, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0115 = { + 0x0115, pci_device_1119_0115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0115, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0118 = { + 0x0118, pci_device_1119_0118, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0118, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0119 = { + 0x0119, pci_device_1119_0119, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0119, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_011a = { + 0x011a, pci_device_1119_011a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_011a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_011b = { + 0x011b, pci_device_1119_011b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_011b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0120 = { + 0x0120, pci_device_1119_0120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0121 = { + 0x0121, pci_device_1119_0121, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0121, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0122 = { + 0x0122, pci_device_1119_0122, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0122, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0123 = { + 0x0123, pci_device_1119_0123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0124 = { + 0x0124, pci_device_1119_0124, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0124, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0125 = { + 0x0125, pci_device_1119_0125, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0125, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0136 = { + 0x0136, pci_device_1119_0136, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0136, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0137 = { + 0x0137, pci_device_1119_0137, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0137, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0138 = { + 0x0138, pci_device_1119_0138, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0138, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0139 = { + 0x0139, pci_device_1119_0139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0139, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013a = { + 0x013a, pci_device_1119_013a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013b = { + 0x013b, pci_device_1119_013b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013c = { + 0x013c, pci_device_1119_013c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013d = { + 0x013d, pci_device_1119_013d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013e = { + 0x013e, pci_device_1119_013e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_013f = { + 0x013f, pci_device_1119_013f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_013f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0166 = { + 0x0166, pci_device_1119_0166, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0166, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0167 = { + 0x0167, pci_device_1119_0167, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0167, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0168 = { + 0x0168, pci_device_1119_0168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0168, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0169 = { + 0x0169, pci_device_1119_0169, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0169, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016a = { + 0x016a, pci_device_1119_016a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016b = { + 0x016b, pci_device_1119_016b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016c = { + 0x016c, pci_device_1119_016c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016d = { + 0x016d, pci_device_1119_016d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016e = { + 0x016e, pci_device_1119_016e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_016f = { + 0x016f, pci_device_1119_016f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_016f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01d6 = { + 0x01d6, pci_device_1119_01d6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01d6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01d7 = { + 0x01d7, pci_device_1119_01d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01f6 = { + 0x01f6, pci_device_1119_01f6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01f6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01f7 = { + 0x01f7, pci_device_1119_01f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01f7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01fc = { + 0x01fc, pci_device_1119_01fc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01fc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01fd = { + 0x01fd, pci_device_1119_01fd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01fd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01fe = { + 0x01fe, pci_device_1119_01fe, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01fe, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_01ff = { + 0x01ff, pci_device_1119_01ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_01ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0210 = { + 0x0210, pci_device_1119_0210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0211 = { + 0x0211, pci_device_1119_0211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0260 = { + 0x0260, pci_device_1119_0260, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0260, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0261 = { + 0x0261, pci_device_1119_0261, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0261, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_02ff = { + 0x02ff, pci_device_1119_02ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_02ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1119_0300 = { + 0x0300, pci_device_1119_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1119_0300, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_111a_0000 = { + 0x0000, pci_device_111a_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111a_0002 = { + 0x0002, pci_device_111a_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111a_0003 = { + 0x0003, pci_device_111a_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111a_0005 = { + 0x0005, pci_device_111a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111a_0007 = { + 0x0007, pci_device_111a_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111a_1203 = { + 0x1203, pci_device_111a_1203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111a_1203, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_111c_0001 = { + 0x0001, pci_device_111c_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111c_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_111d_0001 = { + 0x0001, pci_device_111d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111d_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111d_0003 = { + 0x0003, pci_device_111d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111d_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111d_0004 = { + 0x0004, pci_device_111d_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111d_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111d_0005 = { + 0x0005, pci_device_111d_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111d_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_111f_4a47 = { + 0x4a47, pci_device_111f_4a47, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111f_4a47, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_111f_5243 = { + 0x5243, pci_device_111f_5243, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_111f_5243, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1124_2581 = { + 0x2581, pci_device_1124_2581, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1124_2581, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1127_0200 = { + 0x0200, pci_device_1127_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0210 = { + 0x0210, pci_device_1127_0210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0250 = { + 0x0250, pci_device_1127_0250, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0250, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0300 = { + 0x0300, pci_device_1127_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0310 = { + 0x0310, pci_device_1127_0310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1127_0400 = { + 0x0400, pci_device_1127_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1127_0400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_112f_0000 = { + 0x0000, pci_device_112f_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_112f_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_112f_0001 = { + 0x0001, pci_device_112f_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_112f_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_112f_0008 = { + 0x0008, pci_device_112f_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_112f_0008, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1131_1561 = { + 0x1561, pci_device_1131_1561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_1561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_1562 = { + 0x1562, pci_device_1131_1562, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_1562, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_3400 = { + 0x3400, pci_device_1131_3400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_3400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_5400 = { + 0x5400, pci_device_1131_5400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_5400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_5402 = { + 0x5402, pci_device_1131_5402, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_5402, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_5405 = { + 0x5405, pci_device_1131_5405, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_5405, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_5406 = { + 0x5406, pci_device_1131_5406, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_5406, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7130 = { + 0x7130, pci_device_1131_7130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7133 = { + 0x7133, pci_device_1131_7133, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7133, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7134 = { + 0x7134, pci_device_1131_7134, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7134, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7145 = { + 0x7145, pci_device_1131_7145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_7146 = { + 0x7146, pci_device_1131_7146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_7146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1131_9730 = { + 0x9730, pci_device_1131_9730, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1131_9730, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1133_7901 = { + 0x7901, pci_device_1133_7901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7901, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7902 = { + 0x7902, pci_device_1133_7902, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7902, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7911 = { + 0x7911, pci_device_1133_7911, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7911, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7912 = { + 0x7912, pci_device_1133_7912, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7912, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7941 = { + 0x7941, pci_device_1133_7941, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7941, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7942 = { + 0x7942, pci_device_1133_7942, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7942, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7943 = { + 0x7943, pci_device_1133_7943, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7943, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_7944 = { + 0x7944, pci_device_1133_7944, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_7944, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_b921 = { + 0xb921, pci_device_1133_b921, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_b921, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_b922 = { + 0xb922, pci_device_1133_b922, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_b922, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_b923 = { + 0xb923, pci_device_1133_b923, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_b923, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e001 = { + 0xe001, pci_device_1133_e001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e002 = { + 0xe002, pci_device_1133_e002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e003 = { + 0xe003, pci_device_1133_e003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e004 = { + 0xe004, pci_device_1133_e004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e005 = { + 0xe005, pci_device_1133_e005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e006 = { + 0xe006, pci_device_1133_e006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e007 = { + 0xe007, pci_device_1133_e007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e008 = { + 0xe008, pci_device_1133_e008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e009 = { + 0xe009, pci_device_1133_e009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e00a = { + 0xe00a, pci_device_1133_e00a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e00a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e00b = { + 0xe00b, pci_device_1133_e00b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e00b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e00c = { + 0xe00c, pci_device_1133_e00c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e00c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e00d = { + 0xe00d, pci_device_1133_e00d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e00d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e00e = { + 0xe00e, pci_device_1133_e00e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e00e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e010 = { + 0xe010, pci_device_1133_e010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e011 = { + 0xe011, pci_device_1133_e011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e012 = { + 0xe012, pci_device_1133_e012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e013 = { + 0xe013, pci_device_1133_e013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e014 = { + 0xe014, pci_device_1133_e014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e015 = { + 0xe015, pci_device_1133_e015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e016 = { + 0xe016, pci_device_1133_e016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e017 = { + 0xe017, pci_device_1133_e017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e018 = { + 0xe018, pci_device_1133_e018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e019 = { + 0xe019, pci_device_1133_e019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e01a = { + 0xe01a, pci_device_1133_e01a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e01a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e01b = { + 0xe01b, pci_device_1133_e01b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e01b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e01c = { + 0xe01c, pci_device_1133_e01c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e01c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e01e = { + 0xe01e, pci_device_1133_e01e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e01e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e020 = { + 0xe020, pci_device_1133_e020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e022 = { + 0xe022, pci_device_1133_e022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e024 = { + 0xe024, pci_device_1133_e024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e028 = { + 0xe028, pci_device_1133_e028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e02a = { + 0xe02a, pci_device_1133_e02a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e02a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1133_e02c = { + 0xe02c, pci_device_1133_e02c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1133_e02c, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1134_0001 = { + 0x0001, pci_device_1134_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1134_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1134_0002 = { + 0x0002, pci_device_1134_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1134_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1135_0001 = { + 0x0001, pci_device_1135_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1135_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1138_8905 = { + 0x8905, pci_device_1138_8905, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1138_8905, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1139_0001 = { + 0x0001, pci_device_1139_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1139_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_113c_0000 = { + 0x0000, pci_device_113c_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0001 = { + 0x0001, pci_device_113c_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0911 = { + 0x0911, pci_device_113c_0911, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0911, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0912 = { + 0x0912, pci_device_113c_0912, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0912, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0913 = { + 0x0913, pci_device_113c_0913, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0913, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113c_0914 = { + 0x0914, pci_device_113c_0914, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113c_0914, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_113f_0808 = { + 0x0808, pci_device_113f_0808, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_0808, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_1010 = { + 0x1010, pci_device_113f_1010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_1010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_80c0 = { + 0x80c0, pci_device_113f_80c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_80c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_80c4 = { + 0x80c4, pci_device_113f_80c4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_80c4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_80c8 = { + 0x80c8, pci_device_113f_80c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_80c8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_8888 = { + 0x8888, pci_device_113f_8888, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_8888, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_113f_9090 = { + 0x9090, pci_device_113f_9090, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_113f_9090, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1142_3210 = { + 0x3210, pci_device_1142_3210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_3210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1142_6422 = { + 0x6422, pci_device_1142_6422, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_6422, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1142_6424 = { + 0x6424, pci_device_1142_6424, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_6424, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1142_6425 = { + 0x6425, pci_device_1142_6425, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_6425, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1142_643d = { + 0x643d, pci_device_1142_643d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1142_643d, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1144_0001 = { + 0x0001, pci_device_1144_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1144_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1145_8007 = { + 0x8007, pci_device_1145_8007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_8007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f007 = { + 0xf007, pci_device_1145_f007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f010 = { + 0xf010, pci_device_1145_f010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f012 = { + 0xf012, pci_device_1145_f012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f013 = { + 0xf013, pci_device_1145_f013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f015 = { + 0xf015, pci_device_1145_f015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1145_f020 = { + 0xf020, pci_device_1145_f020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1145_f020, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1148_4000 = { + 0x4000, pci_device_1148_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_4200 = { + 0x4200, pci_device_1148_4200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_4300 = { + 0x4300, pci_device_1148_4300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_4320 = { + 0x4320, pci_device_1148_4320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_4400 = { + 0x4400, pci_device_1148_4400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_4500 = { + 0x4500, pci_device_1148_4500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_4500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_9000 = { + 0x9000, pci_device_1148_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_9843 = { + 0x9843, pci_device_1148_9843, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_9843, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1148_9e00 = { + 0x9e00, pci_device_1148_9e00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1148_9e00, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_114a_5579 = { + 0x5579, pci_device_114a_5579, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114a_5579, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114a_5587 = { + 0x5587, pci_device_114a_5587, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114a_5587, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114a_6504 = { + 0x6504, pci_device_114a_6504, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114a_6504, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114a_7587 = { + 0x7587, pci_device_114a_7587, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114a_7587, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_114f_0002 = { + 0x0002, pci_device_114f_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0003 = { + 0x0003, pci_device_114f_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0004 = { + 0x0004, pci_device_114f_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0005 = { + 0x0005, pci_device_114f_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0006 = { + 0x0006, pci_device_114f_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0009 = { + 0x0009, pci_device_114f_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_000a = { + 0x000a, pci_device_114f_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_000c = { + 0x000c, pci_device_114f_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_000d = { + 0x000d, pci_device_114f_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0011 = { + 0x0011, pci_device_114f_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0012 = { + 0x0012, pci_device_114f_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0014 = { + 0x0014, pci_device_114f_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0015 = { + 0x0015, pci_device_114f_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0016 = { + 0x0016, pci_device_114f_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0017 = { + 0x0017, pci_device_114f_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_001a = { + 0x001a, pci_device_114f_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_001b = { + 0x001b, pci_device_114f_001b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_001b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_001d = { + 0x001d, pci_device_114f_001d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_001d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0023 = { + 0x0023, pci_device_114f_0023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0024 = { + 0x0024, pci_device_114f_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0026 = { + 0x0026, pci_device_114f_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0027 = { + 0x0027, pci_device_114f_0027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0028 = { + 0x0028, pci_device_114f_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0029 = { + 0x0029, pci_device_114f_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0034 = { + 0x0034, pci_device_114f_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0035 = { + 0x0035, pci_device_114f_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0040 = { + 0x0040, pci_device_114f_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0042 = { + 0x0042, pci_device_114f_0042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0043 = { + 0x0043, pci_device_114f_0043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0044 = { + 0x0044, pci_device_114f_0044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0045 = { + 0x0045, pci_device_114f_0045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_004e = { + 0x004e, pci_device_114f_004e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_004e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0070 = { + 0x0070, pci_device_114f_0070, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0070, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0071 = { + 0x0071, pci_device_114f_0071, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0071, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0072 = { + 0x0072, pci_device_114f_0072, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0072, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_0073 = { + 0x0073, pci_device_114f_0073, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_0073, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00b0 = { + 0x00b0, pci_device_114f_00b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00b1 = { + 0x00b1, pci_device_114f_00b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00c8 = { + 0x00c8, pci_device_114f_00c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00c8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00c9 = { + 0x00c9, pci_device_114f_00c9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00c9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00ca = { + 0x00ca, pci_device_114f_00ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00cb = { + 0x00cb, pci_device_114f_00cb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00cb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00d0 = { + 0x00d0, pci_device_114f_00d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_00d1 = { + 0x00d1, pci_device_114f_00d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_00d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_114f_6001 = { + 0x6001, pci_device_114f_6001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_114f_6001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1158_3011 = { + 0x3011, pci_device_1158_3011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1158_3011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1158_9050 = { + 0x9050, pci_device_1158_9050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1158_9050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1158_9051 = { + 0x9051, pci_device_1158_9051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1158_9051, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1159_0001 = { + 0x0001, pci_device_1159_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1159_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_115d_0003 = { + 0x0003, pci_device_115d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_0005 = { + 0x0005, pci_device_115d_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_0007 = { + 0x0007, pci_device_115d_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_000b = { + 0x000b, pci_device_115d_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_000c = { + 0x000c, pci_device_115d_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_000f = { + 0x000f, pci_device_115d_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_00d4 = { + 0x00d4, pci_device_115d_00d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_00d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_0101 = { + 0x0101, pci_device_115d_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_115d_0103 = { + 0x0103, pci_device_115d_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_115d_0103, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_1163_0001 = { + 0x0001, pci_device_1163_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1163_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1163_2000 = { + 0x2000, pci_device_1163_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1163_2000, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1165_0001 = { + 0x0001, pci_device_1165_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1165_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1166_0000 = { + 0x0000, pci_device_1166_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0005 = { + 0x0005, pci_device_1166_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0006 = { + 0x0006, pci_device_1166_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0007 = { + 0x0007, pci_device_1166_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0008 = { + 0x0008, pci_device_1166_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0009 = { + 0x0009, pci_device_1166_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0010 = { + 0x0010, pci_device_1166_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0011 = { + 0x0011, pci_device_1166_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0012 = { + 0x0012, pci_device_1166_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0013 = { + 0x0013, pci_device_1166_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0014 = { + 0x0014, pci_device_1166_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0015 = { + 0x0015, pci_device_1166_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0016 = { + 0x0016, pci_device_1166_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0017 = { + 0x0017, pci_device_1166_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0036 = { + 0x0036, pci_device_1166_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0101 = { + 0x0101, pci_device_1166_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0103 = { + 0x0103, pci_device_1166_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0104 = { + 0x0104, pci_device_1166_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0110 = { + 0x0110, pci_device_1166_0110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0130 = { + 0x0130, pci_device_1166_0130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0132 = { + 0x0132, pci_device_1166_0132, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0132, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0140 = { + 0x0140, pci_device_1166_0140, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0140, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0141 = { + 0x0141, pci_device_1166_0141, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0141, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0142 = { + 0x0142, pci_device_1166_0142, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0142, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0200 = { + 0x0200, pci_device_1166_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0201 = { + 0x0201, pci_device_1166_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0203 = { + 0x0203, pci_device_1166_0203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0205 = { + 0x0205, pci_device_1166_0205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0211 = { + 0x0211, pci_device_1166_0211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0212 = { + 0x0212, pci_device_1166_0212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0213 = { + 0x0213, pci_device_1166_0213, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0213, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0214 = { + 0x0214, pci_device_1166_0214, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0214, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0217 = { + 0x0217, pci_device_1166_0217, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0217, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0220 = { + 0x0220, pci_device_1166_0220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0221 = { + 0x0221, pci_device_1166_0221, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0221, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0223 = { + 0x0223, pci_device_1166_0223, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0223, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0225 = { + 0x0225, pci_device_1166_0225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0227 = { + 0x0227, pci_device_1166_0227, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0227, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0230 = { + 0x0230, pci_device_1166_0230, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0230, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0234 = { + 0x0234, pci_device_1166_0234, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0234, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0240 = { + 0x0240, pci_device_1166_0240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0241 = { + 0x0241, pci_device_1166_0241, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0241, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_0242 = { + 0x0242, pci_device_1166_0242, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_0242, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_024a = { + 0x024a, pci_device_1166_024a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_024a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1166_024b = { + 0x024b, pci_device_1166_024b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1166_024b, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_116a_6100 = { + 0x6100, pci_device_116a_6100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_116a_6100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_116a_6800 = { + 0x6800, pci_device_116a_6800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_116a_6800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_116a_7100 = { + 0x7100, pci_device_116a_7100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_116a_7100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_116a_7800 = { + 0x7800, pci_device_116a_7800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_116a_7800, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1178_afa1 = { + 0xafa1, pci_device_1178_afa1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1178_afa1, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1179_0102 = { + 0x0102, pci_device_1179_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0103 = { + 0x0103, pci_device_1179_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0404 = { + 0x0404, pci_device_1179_0404, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0404, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0406 = { + 0x0406, pci_device_1179_0406, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0406, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0407 = { + 0x0407, pci_device_1179_0407, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0407, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0601 = { + 0x0601, pci_device_1179_0601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0603 = { + 0x0603, pci_device_1179_0603, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0603, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_060a = { + 0x060a, pci_device_1179_060a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_060a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_060f = { + 0x060f, pci_device_1179_060f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_060f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0617 = { + 0x0617, pci_device_1179_0617, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0617, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0618 = { + 0x0618, pci_device_1179_0618, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0618, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0701 = { + 0x0701, pci_device_1179_0701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0701, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0804 = { + 0x0804, pci_device_1179_0804, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0804, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0805 = { + 0x0805, pci_device_1179_0805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1179_0d01 = { + 0x0d01, pci_device_1179_0d01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1179_0d01, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_117c_0030 = { + 0x0030, pci_device_117c_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_117c_0030, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1180_0465 = { + 0x0465, pci_device_1180_0465, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0465, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0466 = { + 0x0466, pci_device_1180_0466, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0466, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0475 = { + 0x0475, pci_device_1180_0475, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0475, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0476 = { + 0x0476, pci_device_1180_0476, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0476, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0477 = { + 0x0477, pci_device_1180_0477, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0477, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0478 = { + 0x0478, pci_device_1180_0478, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0478, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0511 = { + 0x0511, pci_device_1180_0511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0522 = { + 0x0522, pci_device_1180_0522, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0522, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0551 = { + 0x0551, pci_device_1180_0551, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0551, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0552 = { + 0x0552, pci_device_1180_0552, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0552, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0554 = { + 0x0554, pci_device_1180_0554, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0554, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0575 = { + 0x0575, pci_device_1180_0575, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0575, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0576 = { + 0x0576, pci_device_1180_0576, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0576, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0592 = { + 0x0592, pci_device_1180_0592, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0592, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0811 = { + 0x0811, pci_device_1180_0811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0822 = { + 0x0822, pci_device_1180_0822, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0822, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0841 = { + 0x0841, pci_device_1180_0841, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0841, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1180_0852 = { + 0x0852, pci_device_1180_0852, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1180_0852, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1186_0100 = { + 0x0100, pci_device_1186_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1002 = { + 0x1002, pci_device_1186_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1025 = { + 0x1025, pci_device_1186_1025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1026 = { + 0x1026, pci_device_1186_1026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1043 = { + 0x1043, pci_device_1186_1043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1300 = { + 0x1300, pci_device_1186_1300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1340 = { + 0x1340, pci_device_1186_1340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1405 = { + 0x1405, pci_device_1186_1405, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1405, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1541 = { + 0x1541, pci_device_1186_1541, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1541, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_1561 = { + 0x1561, pci_device_1186_1561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_1561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_2027 = { + 0x2027, pci_device_1186_2027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_2027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3203 = { + 0x3203, pci_device_1186_3203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3300 = { + 0x3300, pci_device_1186_3300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a03 = { + 0x3a03, pci_device_1186_3a03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a04 = { + 0x3a04, pci_device_1186_3a04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a04, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a05 = { + 0x3a05, pci_device_1186_3a05, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a05, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a07 = { + 0x3a07, pci_device_1186_3a07, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a07, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a08 = { + 0x3a08, pci_device_1186_3a08, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a08, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a10 = { + 0x3a10, pci_device_1186_3a10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a11 = { + 0x3a11, pci_device_1186_3a11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a12 = { + 0x3a12, pci_device_1186_3a12, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a12, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a13 = { + 0x3a13, pci_device_1186_3a13, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a13, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a14 = { + 0x3a14, pci_device_1186_3a14, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a14, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_3a63 = { + 0x3a63, pci_device_1186_3a63, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_3a63, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_4000 = { + 0x4000, pci_device_1186_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_4300 = { + 0x4300, pci_device_1186_4300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_4300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_4800 = { + 0x4800, pci_device_1186_4800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_4800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_4b01 = { + 0x4b01, pci_device_1186_4b01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_4b01, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_4c00 = { + 0x4c00, pci_device_1186_4c00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_4c00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1186_8400 = { + 0x8400, pci_device_1186_8400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1186_8400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_118c_0014 = { + 0x0014, pci_device_118c_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118c_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118c_1117 = { + 0x1117, pci_device_118c_1117, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118c_1117, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_118d_0001 = { + 0x0001, pci_device_118d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0012 = { + 0x0012, pci_device_118d_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0014 = { + 0x0014, pci_device_118d_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0024 = { + 0x0024, pci_device_118d_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0044 = { + 0x0044, pci_device_118d_0044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0112 = { + 0x0112, pci_device_118d_0112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0114 = { + 0x0114, pci_device_118d_0114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0114, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0124 = { + 0x0124, pci_device_118d_0124, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0124, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0144 = { + 0x0144, pci_device_118d_0144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0212 = { + 0x0212, pci_device_118d_0212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0214 = { + 0x0214, pci_device_118d_0214, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0214, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0224 = { + 0x0224, pci_device_118d_0224, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0224, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0244 = { + 0x0244, pci_device_118d_0244, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0244, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0312 = { + 0x0312, pci_device_118d_0312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0314 = { + 0x0314, pci_device_118d_0314, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0314, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0324 = { + 0x0324, pci_device_118d_0324, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0324, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_118d_0344 = { + 0x0344, pci_device_118d_0344, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_118d_0344, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1190_c731 = { + 0xc731, pci_device_1190_c731, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1190_c731, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1191_0003 = { + 0x0003, pci_device_1191_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0004 = { + 0x0004, pci_device_1191_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0005 = { + 0x0005, pci_device_1191_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0006 = { + 0x0006, pci_device_1191_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0007 = { + 0x0007, pci_device_1191_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0008 = { + 0x0008, pci_device_1191_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_0009 = { + 0x0009, pci_device_1191_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8002 = { + 0x8002, pci_device_1191_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8010 = { + 0x8010, pci_device_1191_8010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8020 = { + 0x8020, pci_device_1191_8020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8030 = { + 0x8030, pci_device_1191_8030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8040 = { + 0x8040, pci_device_1191_8040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8050 = { + 0x8050, pci_device_1191_8050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8060 = { + 0x8060, pci_device_1191_8060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8080 = { + 0x8080, pci_device_1191_8080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_8081 = { + 0x8081, pci_device_1191_8081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_8081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1191_808a = { + 0x808a, pci_device_1191_808a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1191_808a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1193_0001 = { + 0x0001, pci_device_1193_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1193_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1193_0002 = { + 0x0002, pci_device_1193_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1193_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1197_010c = { + 0x010c, pci_device_1197_010c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1197_010c, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_119b_1221 = { + 0x1221, pci_device_119b_1221, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_119b_1221, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_119e_0001 = { + 0x0001, pci_device_119e_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_119e_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_119e_0003 = { + 0x0003, pci_device_119e_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_119e_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11a9_4240 = { + 0x4240, pci_device_11a9_4240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11a9_4240, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11ab_0146 = { + 0x0146, pci_device_11ab_0146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_0146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_138f = { + 0x138f, pci_device_11ab_138f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_138f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_1fa6 = { + 0x1fa6, pci_device_11ab_1fa6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_1fa6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_1fa7 = { + 0x1fa7, pci_device_11ab_1fa7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_1fa7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_1faa = { + 0x1faa, pci_device_11ab_1faa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_1faa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4320 = { + 0x4320, pci_device_11ab_4320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4340 = { + 0x4340, pci_device_11ab_4340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4341 = { + 0x4341, pci_device_11ab_4341, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4341, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4342 = { + 0x4342, pci_device_11ab_4342, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4342, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4343 = { + 0x4343, pci_device_11ab_4343, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4343, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4344 = { + 0x4344, pci_device_11ab_4344, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4344, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4345 = { + 0x4345, pci_device_11ab_4345, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4345, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4346 = { + 0x4346, pci_device_11ab_4346, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4346, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4347 = { + 0x4347, pci_device_11ab_4347, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4347, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4350 = { + 0x4350, pci_device_11ab_4350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4351 = { + 0x4351, pci_device_11ab_4351, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4351, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4352 = { + 0x4352, pci_device_11ab_4352, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4352, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4360 = { + 0x4360, pci_device_11ab_4360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4361 = { + 0x4361, pci_device_11ab_4361, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4361, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4362 = { + 0x4362, pci_device_11ab_4362, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4362, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4363 = { + 0x4363, pci_device_11ab_4363, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4363, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4611 = { + 0x4611, pci_device_11ab_4611, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4611, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4620 = { + 0x4620, pci_device_11ab_4620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_4801 = { + 0x4801, pci_device_11ab_4801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_4801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_5005 = { + 0x5005, pci_device_11ab_5005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_5005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_5040 = { + 0x5040, pci_device_11ab_5040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_5040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_5041 = { + 0x5041, pci_device_11ab_5041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_5041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_5080 = { + 0x5080, pci_device_11ab_5080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_5080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_5081 = { + 0x5081, pci_device_11ab_5081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_5081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_6041 = { + 0x6041, pci_device_11ab_6041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_6041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_6081 = { + 0x6081, pci_device_11ab_6081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_6081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_6460 = { + 0x6460, pci_device_11ab_6460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_6460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_6480 = { + 0x6480, pci_device_11ab_6480, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_6480, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_6485 = { + 0x6485, pci_device_11ab_6485, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_6485, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ab_f003 = { + 0xf003, pci_device_11ab_f003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ab_f003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11ad_0002 = { + 0x0002, pci_device_11ad_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ad_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11ad_c115 = { + 0xc115, pci_device_11ad_c115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ad_c115, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11af_0001 = { + 0x0001, pci_device_11af_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11af_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11af_ee40 = { + 0xee40, pci_device_11af_ee40, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11af_ee40, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11b0_0002 = { + 0x0002, pci_device_11b0_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b0_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11b0_0292 = { + 0x0292, pci_device_11b0_0292, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b0_0292, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11b0_0960 = { + 0x0960, pci_device_11b0_0960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b0_0960, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11b0_c960 = { + 0xc960, pci_device_11b0_c960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b0_c960, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11b8_0001 = { + 0x0001, pci_device_11b8_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b8_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11b9_c0ed = { + 0xc0ed, pci_device_11b9_c0ed, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11b9_c0ed, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11bc_0001 = { + 0x0001, pci_device_11bc_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11bc_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11bd_002e = { + 0x002e, pci_device_11bd_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11bd_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11bd_bede = { + 0xbede, pci_device_11bd_bede, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11bd_bede, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11c1_0440 = { + 0x0440, pci_device_11c1_0440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0441 = { + 0x0441, pci_device_11c1_0441, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0441, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0442 = { + 0x0442, pci_device_11c1_0442, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0442, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0443 = { + 0x0443, pci_device_11c1_0443, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0443, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0444 = { + 0x0444, pci_device_11c1_0444, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0444, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0445 = { + 0x0445, pci_device_11c1_0445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0446 = { + 0x0446, pci_device_11c1_0446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0447 = { + 0x0447, pci_device_11c1_0447, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0447, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0448 = { + 0x0448, pci_device_11c1_0448, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0448, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0449 = { + 0x0449, pci_device_11c1_0449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044a = { + 0x044a, pci_device_11c1_044a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044b = { + 0x044b, pci_device_11c1_044b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044c = { + 0x044c, pci_device_11c1_044c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044d = { + 0x044d, pci_device_11c1_044d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044e = { + 0x044e, pci_device_11c1_044e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_044f = { + 0x044f, pci_device_11c1_044f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_044f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0450 = { + 0x0450, pci_device_11c1_0450, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0450, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0451 = { + 0x0451, pci_device_11c1_0451, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0451, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0452 = { + 0x0452, pci_device_11c1_0452, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0452, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0453 = { + 0x0453, pci_device_11c1_0453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0454 = { + 0x0454, pci_device_11c1_0454, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0454, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0455 = { + 0x0455, pci_device_11c1_0455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0456 = { + 0x0456, pci_device_11c1_0456, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0456, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0457 = { + 0x0457, pci_device_11c1_0457, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0457, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0458 = { + 0x0458, pci_device_11c1_0458, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0458, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0459 = { + 0x0459, pci_device_11c1_0459, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0459, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_045a = { + 0x045a, pci_device_11c1_045a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_045a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_045c = { + 0x045c, pci_device_11c1_045c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_045c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0461 = { + 0x0461, pci_device_11c1_0461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0462 = { + 0x0462, pci_device_11c1_0462, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0462, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_0480 = { + 0x0480, pci_device_11c1_0480, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_0480, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_048c = { + 0x048c, pci_device_11c1_048c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_048c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_048f = { + 0x048f, pci_device_11c1_048f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_048f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_5801 = { + 0x5801, pci_device_11c1_5801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_5801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_5802 = { + 0x5802, pci_device_11c1_5802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_5802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_5803 = { + 0x5803, pci_device_11c1_5803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_5803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_5811 = { + 0x5811, pci_device_11c1_5811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_5811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_8110 = { + 0x8110, pci_device_11c1_8110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_8110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_ab10 = { + 0xab10, pci_device_11c1_ab10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_ab10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_ab11 = { + 0xab11, pci_device_11c1_ab11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_ab11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_ab20 = { + 0xab20, pci_device_11c1_ab20, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_ab20, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_ab21 = { + 0xab21, pci_device_11c1_ab21, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_ab21, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_ab30 = { + 0xab30, pci_device_11c1_ab30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_ab30, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_ed00 = { + 0xed00, pci_device_11c1_ed00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_ed00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c1_ed01 = { + 0xed01, pci_device_11c1_ed01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c1_ed01, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11c8_0658 = { + 0x0658, pci_device_11c8_0658, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c8_0658, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c8_d665 = { + 0xd665, pci_device_11c8_d665, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c8_d665, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c8_d667 = { + 0xd667, pci_device_11c8_d667, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c8_d667, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11c9_0010 = { + 0x0010, pci_device_11c9_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c9_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11c9_0011 = { + 0x0011, pci_device_11c9_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11c9_0011, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11cb_2000 = { + 0x2000, pci_device_11cb_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11cb_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11cb_4000 = { + 0x4000, pci_device_11cb_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11cb_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11cb_8000 = { + 0x8000, pci_device_11cb_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11cb_8000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11d1_01f7 = { + 0x01f7, pci_device_11d1_01f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d1_01f7, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11d4_1535 = { + 0x1535, pci_device_11d4_1535, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d4_1535, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11d4_1805 = { + 0x1805, pci_device_11d4_1805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d4_1805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11d4_1889 = { + 0x1889, pci_device_11d4_1889, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d4_1889, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11d4_1986 = { + 0x1986, pci_device_11d4_1986, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d4_1986, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11d4_5340 = { + 0x5340, pci_device_11d4_5340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d4_5340, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11d5_0115 = { + 0x0115, pci_device_11d5_0115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d5_0115, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11d5_0117 = { + 0x0117, pci_device_11d5_0117, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11d5_0117, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11de_6057 = { + 0x6057, pci_device_11de_6057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11de_6057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11de_6120 = { + 0x6120, pci_device_11de_6120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11de_6120, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11e3_0001 = { + 0x0001, pci_device_11e3_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11e3_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11e3_5030 = { + 0x5030, pci_device_11e3_5030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11e3_5030, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11f0_4231 = { + 0x4231, pci_device_11f0_4231, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4231, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4232 = { + 0x4232, pci_device_11f0_4232, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4232, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4233 = { + 0x4233, pci_device_11f0_4233, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4233, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4234 = { + 0x4234, pci_device_11f0_4234, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4234, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4235 = { + 0x4235, pci_device_11f0_4235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4236 = { + 0x4236, pci_device_11f0_4236, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4236, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f0_4731 = { + 0x4731, pci_device_11f0_4731, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f0_4731, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11f4_2915 = { + 0x2915, pci_device_11f4_2915, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f4_2915, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11f6_0112 = { + 0x0112, pci_device_11f6_0112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_0112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_0113 = { + 0x0113, pci_device_11f6_0113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_0113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_1401 = { + 0x1401, pci_device_11f6_1401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_1401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_2011 = { + 0x2011, pci_device_11f6_2011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_2011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_2201 = { + 0x2201, pci_device_11f6_2201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_2201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11f6_9881 = { + 0x9881, pci_device_11f6_9881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f6_9881, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11f8_7375 = { + 0x7375, pci_device_11f8_7375, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11f8_7375, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11fe_0001 = { + 0x0001, pci_device_11fe_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0002 = { + 0x0002, pci_device_11fe_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0003 = { + 0x0003, pci_device_11fe_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0004 = { + 0x0004, pci_device_11fe_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0005 = { + 0x0005, pci_device_11fe_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0006 = { + 0x0006, pci_device_11fe_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0007 = { + 0x0007, pci_device_11fe_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0008 = { + 0x0008, pci_device_11fe_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0009 = { + 0x0009, pci_device_11fe_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000a = { + 0x000a, pci_device_11fe_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000b = { + 0x000b, pci_device_11fe_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000c = { + 0x000c, pci_device_11fe_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000d = { + 0x000d, pci_device_11fe_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000e = { + 0x000e, pci_device_11fe_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_000f = { + 0x000f, pci_device_11fe_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0801 = { + 0x0801, pci_device_11fe_0801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0802 = { + 0x0802, pci_device_11fe_0802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0803 = { + 0x0803, pci_device_11fe_0803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0805 = { + 0x0805, pci_device_11fe_0805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_080c = { + 0x080c, pci_device_11fe_080c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_080c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_080d = { + 0x080d, pci_device_11fe_080d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_080d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0812 = { + 0x0812, pci_device_11fe_0812, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0812, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_0903 = { + 0x0903, pci_device_11fe_0903, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_0903, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_11fe_8015 = { + 0x8015, pci_device_11fe_8015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11fe_8015, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_11ff_0003 = { + 0x0003, pci_device_11ff_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_11ff_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1202_4300 = { + 0x4300, pci_device_1202_4300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1202_4300, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1208_4853 = { + 0x4853, pci_device_1208_4853, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1208_4853, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_120e_0100 = { + 0x0100, pci_device_120e_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0101 = { + 0x0101, pci_device_120e_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0102 = { + 0x0102, pci_device_120e_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0103 = { + 0x0103, pci_device_120e_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0104 = { + 0x0104, pci_device_120e_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0105 = { + 0x0105, pci_device_120e_0105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0200 = { + 0x0200, pci_device_120e_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0201 = { + 0x0201, pci_device_120e_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0300 = { + 0x0300, pci_device_120e_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0301 = { + 0x0301, pci_device_120e_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0310 = { + 0x0310, pci_device_120e_0310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0311 = { + 0x0311, pci_device_120e_0311, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0311, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0320 = { + 0x0320, pci_device_120e_0320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0321 = { + 0x0321, pci_device_120e_0321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_120e_0400 = { + 0x0400, pci_device_120e_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120e_0400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_120f_0001 = { + 0x0001, pci_device_120f_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_120f_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1217_00f7 = { + 0x00f7, pci_device_1217_00f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_00f7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6729 = { + 0x6729, pci_device_1217_6729, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6729, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_673a = { + 0x673a, pci_device_1217_673a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_673a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6832 = { + 0x6832, pci_device_1217_6832, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6832, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6836 = { + 0x6836, pci_device_1217_6836, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6836, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6872 = { + 0x6872, pci_device_1217_6872, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6872, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6925 = { + 0x6925, pci_device_1217_6925, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6925, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6933 = { + 0x6933, pci_device_1217_6933, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6933, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_6972 = { + 0x6972, pci_device_1217_6972, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_6972, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7110 = { + 0x7110, pci_device_1217_7110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7112 = { + 0x7112, pci_device_1217_7112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7113 = { + 0x7113, pci_device_1217_7113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7114 = { + 0x7114, pci_device_1217_7114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7114, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7120 = { + 0x7120, pci_device_1217_7120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7130 = { + 0x7130, pci_device_1217_7130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7134 = { + 0x7134, pci_device_1217_7134, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7134, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7135 = { + 0x7135, pci_device_1217_7135, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7135, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_71e2 = { + 0x71e2, pci_device_1217_71e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_71e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7212 = { + 0x7212, pci_device_1217_7212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7213 = { + 0x7213, pci_device_1217_7213, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7213, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7223 = { + 0x7223, pci_device_1217_7223, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7223, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1217_7233 = { + 0x7233, pci_device_1217_7233, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1217_7233, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_121a_0001 = { + 0x0001, pci_device_121a_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0002 = { + 0x0002, pci_device_121a_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0003 = { + 0x0003, pci_device_121a_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0004 = { + 0x0004, pci_device_121a_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0005 = { + 0x0005, pci_device_121a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0009 = { + 0x0009, pci_device_121a_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_121a_0057 = { + 0x0057, pci_device_121a_0057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121a_0057, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_121e_0201 = { + 0x0201, pci_device_121e_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_121e_0201, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1220_1220 = { + 0x1220, pci_device_1220_1220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1220_1220, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1223_0003 = { + 0x0003, pci_device_1223_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_0004 = { + 0x0004, pci_device_1223_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_0005 = { + 0x0005, pci_device_1223_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_0008 = { + 0x0008, pci_device_1223_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_0009 = { + 0x0009, pci_device_1223_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000a = { + 0x000a, pci_device_1223_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000b = { + 0x000b, pci_device_1223_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000c = { + 0x000c, pci_device_1223_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000d = { + 0x000d, pci_device_1223_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1223_000e = { + 0x000e, pci_device_1223_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1223_000e, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1227_0006 = { + 0x0006, pci_device_1227_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1227_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1227_0023 = { + 0x0023, pci_device_1227_0023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1227_0023, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_122d_1206 = { + 0x1206, pci_device_122d_1206, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_122d_1206, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_122d_1400 = { + 0x1400, pci_device_122d_1400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_122d_1400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_122d_50dc = { + 0x50dc, pci_device_122d_50dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_122d_50dc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_122d_80da = { + 0x80da, pci_device_122d_80da, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_122d_80da, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1236_0000 = { + 0x0000, pci_device_1236_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1236_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1236_6401 = { + 0x6401, pci_device_1236_6401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1236_6401, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_123d_0000 = { + 0x0000, pci_device_123d_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123d_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_123d_0002 = { + 0x0002, pci_device_123d_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123d_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_123d_0003 = { + 0x0003, pci_device_123d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123d_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_123f_00e4 = { + 0x00e4, pci_device_123f_00e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123f_00e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_123f_8120 = { + 0x8120, pci_device_123f_8120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123f_8120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_123f_8888 = { + 0x8888, pci_device_123f_8888, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_123f_8888, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1242_1560 = { + 0x1560, pci_device_1242_1560, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1242_1560, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1242_4643 = { + 0x4643, pci_device_1242_4643, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1242_4643, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1242_6562 = { + 0x6562, pci_device_1242_6562, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1242_6562, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1242_656a = { + 0x656a, pci_device_1242_656a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1242_656a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1244_0700 = { + 0x0700, pci_device_1244_0700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_0700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_0800 = { + 0x0800, pci_device_1244_0800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_0800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_0a00 = { + 0x0a00, pci_device_1244_0a00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_0a00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_0e00 = { + 0x0e00, pci_device_1244_0e00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_0e00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_1100 = { + 0x1100, pci_device_1244_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_1200 = { + 0x1200, pci_device_1244_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_1200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_2700 = { + 0x2700, pci_device_1244_2700, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_2700, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1244_2900 = { + 0x2900, pci_device_1244_2900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1244_2900, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_124b_0040 = { + 0x0040, pci_device_124b_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124b_0040, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_124d_0000 = { + 0x0000, pci_device_124d_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124d_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_124d_0002 = { + 0x0002, pci_device_124d_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124d_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_124d_0003 = { + 0x0003, pci_device_124d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124d_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_124d_0004 = { + 0x0004, pci_device_124d_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124d_0004, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_124f_0041 = { + 0x0041, pci_device_124f_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_124f_0041, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1255_1110 = { + 0x1110, pci_device_1255_1110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_1110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1255_1210 = { + 0x1210, pci_device_1255_1210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_1210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1255_2110 = { + 0x2110, pci_device_1255_2110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_2110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1255_2120 = { + 0x2120, pci_device_1255_2120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_2120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1255_2130 = { + 0x2130, pci_device_1255_2130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1255_2130, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1256_4201 = { + 0x4201, pci_device_1256_4201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1256_4201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1256_4401 = { + 0x4401, pci_device_1256_4401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1256_4401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1256_5201 = { + 0x5201, pci_device_1256_5201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1256_5201, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1259_2560 = { + 0x2560, pci_device_1259_2560, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1259_2560, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1259_a117 = { + 0xa117, pci_device_1259_a117, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1259_a117, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1259_a11e = { + 0xa11e, pci_device_1259_a11e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1259_a11e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1259_a120 = { + 0xa120, pci_device_1259_a120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1259_a120, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_125b_1400 = { + 0x1400, pci_device_125b_1400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125b_1400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_125c_0101 = { + 0x0101, pci_device_125c_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125c_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125c_0640 = { + 0x0640, pci_device_125c_0640, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125c_0640, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_125d_0000 = { + 0x0000, pci_device_125d_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1948 = { + 0x1948, pci_device_125d_1948, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1948, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1968 = { + 0x1968, pci_device_125d_1968, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1968, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1969 = { + 0x1969, pci_device_125d_1969, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1969, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1978 = { + 0x1978, pci_device_125d_1978, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1978, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1988 = { + 0x1988, pci_device_125d_1988, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1988, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1989 = { + 0x1989, pci_device_125d_1989, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1989, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1998 = { + 0x1998, pci_device_125d_1998, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1998, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_1999 = { + 0x1999, pci_device_125d_1999, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_1999, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_199a = { + 0x199a, pci_device_125d_199a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_199a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_199b = { + 0x199b, pci_device_125d_199b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_199b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_2808 = { + 0x2808, pci_device_125d_2808, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_2808, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_2838 = { + 0x2838, pci_device_125d_2838, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_2838, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_125d_2898 = { + 0x2898, pci_device_125d_2898, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_125d_2898, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1260_3872 = { + 0x3872, pci_device_1260_3872, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_3872, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_3873 = { + 0x3873, pci_device_1260_3873, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_3873, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_3886 = { + 0x3886, pci_device_1260_3886, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_3886, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_3890 = { + 0x3890, pci_device_1260_3890, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_3890, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_8130 = { + 0x8130, pci_device_1260_8130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_8130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_8131 = { + 0x8131, pci_device_1260_8131, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_8131, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1260_ffff = { + 0xffff, pci_device_1260_ffff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1260_ffff, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1266_0001 = { + 0x0001, pci_device_1266_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1266_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1266_1910 = { + 0x1910, pci_device_1266_1910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1266_1910, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1267_5352 = { + 0x5352, pci_device_1267_5352, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1267_5352, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1267_5a4b = { + 0x5a4b, pci_device_1267_5a4b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1267_5a4b, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_126c_1211 = { + 0x1211, pci_device_126c_1211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126c_1211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126c_126c = { + 0x126c, pci_device_126c_126c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126c_126c, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_126f_0501 = { + 0x0501, pci_device_126f_0501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0510 = { + 0x0510, pci_device_126f_0510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0710 = { + 0x0710, pci_device_126f_0710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0712 = { + 0x0712, pci_device_126f_0712, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0712, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0720 = { + 0x0720, pci_device_126f_0720, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0720, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0730 = { + 0x0730, pci_device_126f_0730, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0730, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0810 = { + 0x0810, pci_device_126f_0810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0811 = { + 0x0811, pci_device_126f_0811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0820 = { + 0x0820, pci_device_126f_0820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0820, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_126f_0910 = { + 0x0910, pci_device_126f_0910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_126f_0910, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1273_0002 = { + 0x0002, pci_device_1273_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1273_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1274_1171 = { + 0x1171, pci_device_1274_1171, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1274_1171, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1274_1371 = { + 0x1371, pci_device_1274_1371, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1274_1371, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1274_5000 = { + 0x5000, pci_device_1274_5000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1274_5000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1274_5880 = { + 0x5880, pci_device_1274_5880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1274_5880, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1278_0701 = { + 0x0701, pci_device_1278_0701, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1278_0701, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1278_0710 = { + 0x0710, pci_device_1278_0710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1278_0710, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1279_0060 = { + 0x0060, pci_device_1279_0060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1279_0061 = { + 0x0061, pci_device_1279_0061, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0061, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1279_0295 = { + 0x0295, pci_device_1279_0295, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0295, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1279_0395 = { + 0x0395, pci_device_1279_0395, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0395, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1279_0396 = { + 0x0396, pci_device_1279_0396, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0396, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1279_0397 = { + 0x0397, pci_device_1279_0397, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1279_0397, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_127a_1002 = { + 0x1002, pci_device_127a_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1003 = { + 0x1003, pci_device_127a_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1004 = { + 0x1004, pci_device_127a_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1005 = { + 0x1005, pci_device_127a_1005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1022 = { + 0x1022, pci_device_127a_1022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1023 = { + 0x1023, pci_device_127a_1023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1024 = { + 0x1024, pci_device_127a_1024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1025 = { + 0x1025, pci_device_127a_1025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1026 = { + 0x1026, pci_device_127a_1026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1032 = { + 0x1032, pci_device_127a_1032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1033 = { + 0x1033, pci_device_127a_1033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1034 = { + 0x1034, pci_device_127a_1034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1035 = { + 0x1035, pci_device_127a_1035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1036 = { + 0x1036, pci_device_127a_1036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_1085 = { + 0x1085, pci_device_127a_1085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_1085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2005 = { + 0x2005, pci_device_127a_2005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2013 = { + 0x2013, pci_device_127a_2013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2014 = { + 0x2014, pci_device_127a_2014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2015 = { + 0x2015, pci_device_127a_2015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_2016 = { + 0x2016, pci_device_127a_2016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_2016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_4311 = { + 0x4311, pci_device_127a_4311, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_4311, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_4320 = { + 0x4320, pci_device_127a_4320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_4320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_4321 = { + 0x4321, pci_device_127a_4321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_4321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_4322 = { + 0x4322, pci_device_127a_4322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_4322, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_127a_8234 = { + 0x8234, pci_device_127a_8234, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_127a_8234, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1282_9009 = { + 0x9009, pci_device_1282_9009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1282_9009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1282_9100 = { + 0x9100, pci_device_1282_9100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1282_9100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1282_9102 = { + 0x9102, pci_device_1282_9102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1282_9102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1282_9132 = { + 0x9132, pci_device_1282_9132, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1282_9132, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1283_673a = { + 0x673a, pci_device_1283_673a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_673a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8211 = { + 0x8211, pci_device_1283_8211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8212 = { + 0x8212, pci_device_1283_8212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8330 = { + 0x8330, pci_device_1283_8330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8872 = { + 0x8872, pci_device_1283_8872, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8872, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8888 = { + 0x8888, pci_device_1283_8888, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8888, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_8889 = { + 0x8889, pci_device_1283_8889, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_8889, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1283_e886 = { + 0xe886, pci_device_1283_e886, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1283_e886, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1285_0100 = { + 0x0100, pci_device_1285_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1285_0100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1287_001e = { + 0x001e, pci_device_1287_001e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1287_001e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1287_001f = { + 0x001f, pci_device_1287_001f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1287_001f, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_128d_0021 = { + 0x0021, pci_device_128d_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128d_0021, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_128e_0008 = { + 0x0008, pci_device_128e_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_128e_0009 = { + 0x0009, pci_device_128e_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_128e_000a = { + 0x000a, pci_device_128e_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_128e_000b = { + 0x000b, pci_device_128e_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_128e_000c = { + 0x000c, pci_device_128e_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_128e_000c, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_129a_0615 = { + 0x0615, pci_device_129a_0615, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_129a_0615, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12a3_8105 = { + 0x8105, pci_device_12a3_8105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12a3_8105, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12ab_0002 = { + 0x0002, pci_device_12ab_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ab_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12ab_3000 = { + 0x3000, pci_device_12ab_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ab_3000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12ae_0001 = { + 0x0001, pci_device_12ae_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ae_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12ae_0002 = { + 0x0002, pci_device_12ae_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ae_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12ae_00fa = { + 0x00fa, pci_device_12ae_00fa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12ae_00fa, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12b9_1006 = { + 0x1006, pci_device_12b9_1006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12b9_1006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12b9_1007 = { + 0x1007, pci_device_12b9_1007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12b9_1007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12b9_1008 = { + 0x1008, pci_device_12b9_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12b9_1008, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12be_3041 = { + 0x3041, pci_device_12be_3041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12be_3041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12be_3042 = { + 0x3042, pci_device_12be_3042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12be_3042, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12c3_0058 = { + 0x0058, pci_device_12c3_0058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c3_0058, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c3_5598 = { + 0x5598, pci_device_12c3_5598, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c3_5598, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12c4_0001 = { + 0x0001, pci_device_12c4_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0002 = { + 0x0002, pci_device_12c4_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0003 = { + 0x0003, pci_device_12c4_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0004 = { + 0x0004, pci_device_12c4_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0005 = { + 0x0005, pci_device_12c4_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0006 = { + 0x0006, pci_device_12c4_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0007 = { + 0x0007, pci_device_12c4_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0008 = { + 0x0008, pci_device_12c4_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0009 = { + 0x0009, pci_device_12c4_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_000a = { + 0x000a, pci_device_12c4_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_000b = { + 0x000b, pci_device_12c4_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_000c = { + 0x000c, pci_device_12c4_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_000d = { + 0x000d, pci_device_12c4_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0100 = { + 0x0100, pci_device_12c4_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0201 = { + 0x0201, pci_device_12c4_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0202 = { + 0x0202, pci_device_12c4_0202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0300 = { + 0x0300, pci_device_12c4_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0301 = { + 0x0301, pci_device_12c4_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0302 = { + 0x0302, pci_device_12c4_0302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0310 = { + 0x0310, pci_device_12c4_0310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0311 = { + 0x0311, pci_device_12c4_0311, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0311, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0312 = { + 0x0312, pci_device_12c4_0312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0320 = { + 0x0320, pci_device_12c4_0320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0321 = { + 0x0321, pci_device_12c4_0321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0322 = { + 0x0322, pci_device_12c4_0322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0322, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0330 = { + 0x0330, pci_device_12c4_0330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0331 = { + 0x0331, pci_device_12c4_0331, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0331, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c4_0332 = { + 0x0332, pci_device_12c4_0332, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c4_0332, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12c5_007e = { + 0x007e, pci_device_12c5_007e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_007e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c5_007f = { + 0x007f, pci_device_12c5_007f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_007f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c5_0081 = { + 0x0081, pci_device_12c5_0081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_0081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c5_0085 = { + 0x0085, pci_device_12c5_0085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_0085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12c5_0086 = { + 0x0086, pci_device_12c5_0086, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12c5_0086, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_12d2_0008 = { + 0x0008, pci_device_12d2_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0009 = { + 0x0009, pci_device_12d2_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0018 = { + 0x0018, pci_device_12d2_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0019 = { + 0x0019, pci_device_12d2_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0020 = { + 0x0020, pci_device_12d2_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0028 = { + 0x0028, pci_device_12d2_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_0029 = { + 0x0029, pci_device_12d2_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_002c = { + 0x002c, pci_device_12d2_002c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_002c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d2_00a0 = { + 0x00a0, pci_device_12d2_00a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d2_00a0, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12d4_0200 = { + 0x0200, pci_device_12d4_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d4_0200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12d5_0003 = { + 0x0003, pci_device_12d5_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d5_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d5_1000 = { + 0x1000, pci_device_12d5_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d5_1000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12d8_8150 = { + 0x8150, pci_device_12d8_8150, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d8_8150, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12d9_0002 = { + 0x0002, pci_device_12d9_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d9_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d9_0004 = { + 0x0004, pci_device_12d9_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d9_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d9_0005 = { + 0x0005, pci_device_12d9_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d9_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12d9_1078 = { + 0x1078, pci_device_12d9_1078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12d9_1078, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12de_0200 = { + 0x0200, pci_device_12de_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12de_0200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12e0_0010 = { + 0x0010, pci_device_12e0_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12e0_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12e0_0020 = { + 0x0020, pci_device_12e0_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12e0_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12e0_0030 = { + 0x0030, pci_device_12e0_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12e0_0030, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12eb_0001 = { + 0x0001, pci_device_12eb_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12eb_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12eb_0002 = { + 0x0002, pci_device_12eb_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12eb_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12eb_0003 = { + 0x0003, pci_device_12eb_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12eb_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12eb_8803 = { + 0x8803, pci_device_12eb_8803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12eb_8803, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12f8_0002 = { + 0x0002, pci_device_12f8_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12f8_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_12fb_0001 = { + 0x0001, pci_device_12fb_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_00f5 = { + 0x00f5, pci_device_12fb_00f5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_00f5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_02ad = { + 0x02ad, pci_device_12fb_02ad, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_02ad, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_2adc = { + 0x2adc, pci_device_12fb_2adc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_2adc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_3100 = { + 0x3100, pci_device_12fb_3100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_3100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_3500 = { + 0x3500, pci_device_12fb_3500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_3500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_4d4f = { + 0x4d4f, pci_device_12fb_4d4f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_4d4f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_8120 = { + 0x8120, pci_device_12fb_8120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_8120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_da62 = { + 0xda62, pci_device_12fb_da62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_da62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_db62 = { + 0xdb62, pci_device_12fb_db62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_db62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_dc62 = { + 0xdc62, pci_device_12fb_dc62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_dc62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_dd62 = { + 0xdd62, pci_device_12fb_dd62, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_dd62, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_eddc = { + 0xeddc, pci_device_12fb_eddc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_eddc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_12fb_fa01 = { + 0xfa01, pci_device_12fb_fa01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_12fb_fa01, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1307_0001 = { + 0x0001, pci_device_1307_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_000b = { + 0x000b, pci_device_1307_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_000b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_000c = { + 0x000c, pci_device_1307_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_000d = { + 0x000d, pci_device_1307_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_000f = { + 0x000f, pci_device_1307_000f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_000f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0010 = { + 0x0010, pci_device_1307_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0014 = { + 0x0014, pci_device_1307_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0015 = { + 0x0015, pci_device_1307_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0016 = { + 0x0016, pci_device_1307_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0017 = { + 0x0017, pci_device_1307_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0018 = { + 0x0018, pci_device_1307_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0019 = { + 0x0019, pci_device_1307_0019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001a = { + 0x001a, pci_device_1307_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001b = { + 0x001b, pci_device_1307_001b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001c = { + 0x001c, pci_device_1307_001c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001d = { + 0x001d, pci_device_1307_001d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001e = { + 0x001e, pci_device_1307_001e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_001f = { + 0x001f, pci_device_1307_001f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_001f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0020 = { + 0x0020, pci_device_1307_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0021 = { + 0x0021, pci_device_1307_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0022 = { + 0x0022, pci_device_1307_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0023 = { + 0x0023, pci_device_1307_0023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0024 = { + 0x0024, pci_device_1307_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0025 = { + 0x0025, pci_device_1307_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0026 = { + 0x0026, pci_device_1307_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0027 = { + 0x0027, pci_device_1307_0027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0028 = { + 0x0028, pci_device_1307_0028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0029 = { + 0x0029, pci_device_1307_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_002c = { + 0x002c, pci_device_1307_002c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_002c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0033 = { + 0x0033, pci_device_1307_0033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0034 = { + 0x0034, pci_device_1307_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0035 = { + 0x0035, pci_device_1307_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0036 = { + 0x0036, pci_device_1307_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0037 = { + 0x0037, pci_device_1307_0037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_004c = { + 0x004c, pci_device_1307_004c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_004c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_004d = { + 0x004d, pci_device_1307_004d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_004d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0052 = { + 0x0052, pci_device_1307_0052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_0054 = { + 0x0054, pci_device_1307_0054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_0054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1307_005e = { + 0x005e, pci_device_1307_005e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1307_005e, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1308_0001 = { + 0x0001, pci_device_1308_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1308_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1317_0981 = { + 0x0981, pci_device_1317_0981, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_0981, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_0985 = { + 0x0985, pci_device_1317_0985, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_0985, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_1985 = { + 0x1985, pci_device_1317_1985, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_1985, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_2850 = { + 0x2850, pci_device_1317_2850, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_2850, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_5120 = { + 0x5120, pci_device_1317_5120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_5120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_8201 = { + 0x8201, pci_device_1317_8201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_8201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_8211 = { + 0x8211, pci_device_1317_8211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_8211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1317_9511 = { + 0x9511, pci_device_1317_9511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1317_9511, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1318_0911 = { + 0x0911, pci_device_1318_0911, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1318_0911, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1319_0801 = { + 0x0801, pci_device_1319_0801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1319_0801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1319_0802 = { + 0x0802, pci_device_1319_0802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1319_0802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1319_1000 = { + 0x1000, pci_device_1319_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1319_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1319_1001 = { + 0x1001, pci_device_1319_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1319_1001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_131f_1000 = { + 0x1000, pci_device_131f_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1001 = { + 0x1001, pci_device_131f_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1002 = { + 0x1002, pci_device_131f_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1010 = { + 0x1010, pci_device_131f_1010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1011 = { + 0x1011, pci_device_131f_1011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1012 = { + 0x1012, pci_device_131f_1012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1020 = { + 0x1020, pci_device_131f_1020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1021 = { + 0x1021, pci_device_131f_1021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1030 = { + 0x1030, pci_device_131f_1030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1031 = { + 0x1031, pci_device_131f_1031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1032 = { + 0x1032, pci_device_131f_1032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1034 = { + 0x1034, pci_device_131f_1034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1035 = { + 0x1035, pci_device_131f_1035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1036 = { + 0x1036, pci_device_131f_1036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1050 = { + 0x1050, pci_device_131f_1050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1051 = { + 0x1051, pci_device_131f_1051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_1052 = { + 0x1052, pci_device_131f_1052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_1052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2000 = { + 0x2000, pci_device_131f_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2001 = { + 0x2001, pci_device_131f_2001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2002 = { + 0x2002, pci_device_131f_2002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2010 = { + 0x2010, pci_device_131f_2010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2011 = { + 0x2011, pci_device_131f_2011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2012 = { + 0x2012, pci_device_131f_2012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2020 = { + 0x2020, pci_device_131f_2020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2021 = { + 0x2021, pci_device_131f_2021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2030 = { + 0x2030, pci_device_131f_2030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2031 = { + 0x2031, pci_device_131f_2031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2032 = { + 0x2032, pci_device_131f_2032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2040 = { + 0x2040, pci_device_131f_2040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2041 = { + 0x2041, pci_device_131f_2041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2042 = { + 0x2042, pci_device_131f_2042, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2042, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2050 = { + 0x2050, pci_device_131f_2050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2051 = { + 0x2051, pci_device_131f_2051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2052 = { + 0x2052, pci_device_131f_2052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2060 = { + 0x2060, pci_device_131f_2060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2061 = { + 0x2061, pci_device_131f_2061, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2061, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2062 = { + 0x2062, pci_device_131f_2062, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2062, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_131f_2081 = { + 0x2081, pci_device_131f_2081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_131f_2081, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1331_0030 = { + 0x0030, pci_device_1331_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1331_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1331_8200 = { + 0x8200, pci_device_1331_8200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1331_8200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1331_8201 = { + 0x8201, pci_device_1331_8201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1331_8201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1331_8202 = { + 0x8202, pci_device_1331_8202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1331_8202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1331_8210 = { + 0x8210, pci_device_1331_8210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1331_8210, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1332_5415 = { + 0x5415, pci_device_1332_5415, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1332_5415, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1332_5425 = { + 0x5425, pci_device_1332_5425, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1332_5425, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1332_6140 = { + 0x6140, pci_device_1332_6140, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1332_6140, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_134a_0001 = { + 0x0001, pci_device_134a_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134a_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134a_0002 = { + 0x0002, pci_device_134a_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134a_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_134d_2189 = { + 0x2189, pci_device_134d_2189, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_2189, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_2486 = { + 0x2486, pci_device_134d_2486, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_2486, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7890 = { + 0x7890, pci_device_134d_7890, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7890, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7891 = { + 0x7891, pci_device_134d_7891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7892 = { + 0x7892, pci_device_134d_7892, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7892, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7893 = { + 0x7893, pci_device_134d_7893, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7893, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7894 = { + 0x7894, pci_device_134d_7894, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7894, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7895 = { + 0x7895, pci_device_134d_7895, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7895, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7896 = { + 0x7896, pci_device_134d_7896, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7896, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_134d_7897 = { + 0x7897, pci_device_134d_7897, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_134d_7897, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1353_0002 = { + 0x0002, pci_device_1353_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1353_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1353_0003 = { + 0x0003, pci_device_1353_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1353_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1353_0004 = { + 0x0004, pci_device_1353_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1353_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1353_0005 = { + 0x0005, pci_device_1353_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1353_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_135c_0010 = { + 0x0010, pci_device_135c_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0020 = { + 0x0020, pci_device_135c_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0030 = { + 0x0030, pci_device_135c_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0040 = { + 0x0040, pci_device_135c_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0050 = { + 0x0050, pci_device_135c_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0060 = { + 0x0060, pci_device_135c_0060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_00f0 = { + 0x00f0, pci_device_135c_00f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_00f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0170 = { + 0x0170, pci_device_135c_0170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0170, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0180 = { + 0x0180, pci_device_135c_0180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_0190 = { + 0x0190, pci_device_135c_0190, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_0190, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_01a0 = { + 0x01a0, pci_device_135c_01a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_01a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_01b0 = { + 0x01b0, pci_device_135c_01b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_01b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135c_01c0 = { + 0x01c0, pci_device_135c_01c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135c_01c0, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_135e_5101 = { + 0x5101, pci_device_135e_5101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_5101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7101 = { + 0x7101, pci_device_135e_7101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7201 = { + 0x7201, pci_device_135e_7201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7202 = { + 0x7202, pci_device_135e_7202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7401 = { + 0x7401, pci_device_135e_7401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7402 = { + 0x7402, pci_device_135e_7402, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7402, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7801 = { + 0x7801, pci_device_135e_7801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_7804 = { + 0x7804, pci_device_135e_7804, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_7804, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_135e_8001 = { + 0x8001, pci_device_135e_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_135e_8001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1360_0101 = { + 0x0101, pci_device_1360_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0102 = { + 0x0102, pci_device_1360_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0103 = { + 0x0103, pci_device_1360_0103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0104 = { + 0x0104, pci_device_1360_0104, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0104, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0201 = { + 0x0201, pci_device_1360_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0202 = { + 0x0202, pci_device_1360_0202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0203 = { + 0x0203, pci_device_1360_0203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0204 = { + 0x0204, pci_device_1360_0204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0301 = { + 0x0301, pci_device_1360_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0302 = { + 0x0302, pci_device_1360_0302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1360_0303 = { + 0x0303, pci_device_1360_0303, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1360_0303, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_136a_0004 = { + 0x0004, pci_device_136a_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_136a_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_136a_0007 = { + 0x0007, pci_device_136a_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_136a_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_136a_0008 = { + 0x0008, pci_device_136a_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_136a_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_136a_000a = { + 0x000a, pci_device_136a_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_136a_000a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_136b_ff01 = { + 0xff01, pci_device_136b_ff01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_136b_ff01, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1371_434e = { + 0x434e, pci_device_1371_434e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1371_434e, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1374_0024 = { + 0x0024, pci_device_1374_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0025 = { + 0x0025, pci_device_1374_0025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0026 = { + 0x0026, pci_device_1374_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0027 = { + 0x0027, pci_device_1374_0027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0029 = { + 0x0029, pci_device_1374_0029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002a = { + 0x002a, pci_device_1374_002a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002b = { + 0x002b, pci_device_1374_002b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002c = { + 0x002c, pci_device_1374_002c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002d = { + 0x002d, pci_device_1374_002d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002e = { + 0x002e, pci_device_1374_002e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_002f = { + 0x002f, pci_device_1374_002f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_002f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0030 = { + 0x0030, pci_device_1374_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0031 = { + 0x0031, pci_device_1374_0031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0032 = { + 0x0032, pci_device_1374_0032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0034 = { + 0x0034, pci_device_1374_0034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0035 = { + 0x0035, pci_device_1374_0035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0036 = { + 0x0036, pci_device_1374_0036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0037 = { + 0x0037, pci_device_1374_0037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0038 = { + 0x0038, pci_device_1374_0038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_0039 = { + 0x0039, pci_device_1374_0039, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_0039, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1374_003a = { + 0x003a, pci_device_1374_003a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1374_003a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_137a_0001 = { + 0x0001, pci_device_137a_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_137a_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1382_0001 = { + 0x0001, pci_device_1382_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_2008 = { + 0x2008, pci_device_1382_2008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_2008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_2048 = { + 0x2048, pci_device_1382_2048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_2048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_2088 = { + 0x2088, pci_device_1382_2088, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_2088, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_20c8 = { + 0x20c8, pci_device_1382_20c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_20c8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_4008 = { + 0x4008, pci_device_1382_4008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_4008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_4010 = { + 0x4010, pci_device_1382_4010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_4010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_4048 = { + 0x4048, pci_device_1382_4048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_4048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_4088 = { + 0x4088, pci_device_1382_4088, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_4088, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_4248 = { + 0x4248, pci_device_1382_4248, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_4248, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1382_4424 = { + 0x4424, pci_device_1382_4424, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1382_4424, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1385_0013 = { + 0x0013, pci_device_1385_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_311a = { + 0x311a, pci_device_1385_311a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_311a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4100 = { + 0x4100, pci_device_1385_4100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4105 = { + 0x4105, pci_device_1385_4105, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4105, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4251 = { + 0x4251, pci_device_1385_4251, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4251, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4400 = { + 0x4400, pci_device_1385_4400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4600 = { + 0x4600, pci_device_1385_4600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4601 = { + 0x4601, pci_device_1385_4601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4610 = { + 0x4610, pci_device_1385_4610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4800 = { + 0x4800, pci_device_1385_4800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4900 = { + 0x4900, pci_device_1385_4900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4a00 = { + 0x4a00, pci_device_1385_4a00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4a00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4b00 = { + 0x4b00, pci_device_1385_4b00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4b00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4c00 = { + 0x4c00, pci_device_1385_4c00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4c00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4d00 = { + 0x4d00, pci_device_1385_4d00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4d00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4e00 = { + 0x4e00, pci_device_1385_4e00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4e00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_4f00 = { + 0x4f00, pci_device_1385_4f00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_4f00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_5200 = { + 0x5200, pci_device_1385_5200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_5200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_620a = { + 0x620a, pci_device_1385_620a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_620a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_622a = { + 0x622a, pci_device_1385_622a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_622a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_630a = { + 0x630a, pci_device_1385_630a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_630a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_6b00 = { + 0x6b00, pci_device_1385_6b00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_6b00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_6d00 = { + 0x6d00, pci_device_1385_6d00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_6d00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_7b00 = { + 0x7b00, pci_device_1385_7b00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_7b00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_7c00 = { + 0x7c00, pci_device_1385_7c00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_7c00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_7d00 = { + 0x7d00, pci_device_1385_7d00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_7d00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_7e00 = { + 0x7e00, pci_device_1385_7e00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_7e00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1385_f004 = { + 0xf004, pci_device_1385_f004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1385_f004, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1389_0001 = { + 0x0001, pci_device_1389_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1389_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1393_1040 = { + 0x1040, pci_device_1393_1040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_1040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1393_1141 = { + 0x1141, pci_device_1393_1141, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_1141, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1393_1680 = { + 0x1680, pci_device_1393_1680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_1680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1393_2040 = { + 0x2040, pci_device_1393_2040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_2040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1393_2180 = { + 0x2180, pci_device_1393_2180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_2180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1393_3200 = { + 0x3200, pci_device_1393_3200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1393_3200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1394_0001 = { + 0x0001, pci_device_1394_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1394_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1397_08b4 = { + 0x08b4, pci_device_1397_08b4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1397_08b4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1397_16b8 = { + 0x16b8, pci_device_1397_16b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1397_16b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1397_2bd0 = { + 0x2bd0, pci_device_1397_2bd0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1397_2bd0, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_139a_0001 = { + 0x0001, pci_device_139a_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_139a_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_139a_0003 = { + 0x0003, pci_device_139a_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_139a_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_139a_0005 = { + 0x0005, pci_device_139a_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_139a_0005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13a3_0005 = { + 0x0005, pci_device_13a3_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0006 = { + 0x0006, pci_device_13a3_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0007 = { + 0x0007, pci_device_13a3_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0012 = { + 0x0012, pci_device_13a3_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0014 = { + 0x0014, pci_device_13a3_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0016 = { + 0x0016, pci_device_13a3_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0017 = { + 0x0017, pci_device_13a3_0017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0018 = { + 0x0018, pci_device_13a3_0018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_001d = { + 0x001d, pci_device_13a3_001d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_001d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0020 = { + 0x0020, pci_device_13a3_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a3_0026 = { + 0x0026, pci_device_13a3_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a3_0026, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13a8_0152 = { + 0x0152, pci_device_13a8_0152, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a8_0152, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a8_0154 = { + 0x0154, pci_device_13a8_0154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a8_0154, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13a8_0158 = { + 0x0158, pci_device_13a8_0158, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13a8_0158, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13c0_0010 = { + 0x0010, pci_device_13c0_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c0_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c0_0020 = { + 0x0020, pci_device_13c0_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c0_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c0_0030 = { + 0x0030, pci_device_13c0_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c0_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c0_0210 = { + 0x0210, pci_device_13c0_0210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c0_0210, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13c1_1000 = { + 0x1000, pci_device_13c1_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c1_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c1_1001 = { + 0x1001, pci_device_13c1_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c1_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c1_1002 = { + 0x1002, pci_device_13c1_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c1_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c1_1003 = { + 0x1003, pci_device_13c1_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c1_1003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13c2_000e = { + 0x000e, pci_device_13c2_000e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c2_000e, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13c6_0520 = { + 0x0520, pci_device_13c6_0520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c6_0520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c6_0620 = { + 0x0620, pci_device_13c6_0620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c6_0620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13c6_0820 = { + 0x0820, pci_device_13c6_0820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13c6_0820, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13d0_2103 = { + 0x2103, pci_device_13d0_2103, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d0_2103, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13d0_2200 = { + 0x2200, pci_device_13d0_2200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d0_2200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13d1_ab02 = { + 0xab02, pci_device_13d1_ab02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d1_ab02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13d1_ab03 = { + 0xab03, pci_device_13d1_ab03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d1_ab03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13d1_ab06 = { + 0xab06, pci_device_13d1_ab06, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d1_ab06, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13d1_ab08 = { + 0xab08, pci_device_13d1_ab08, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13d1_ab08, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13df_0001 = { + 0x0001, pci_device_13df_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13df_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13ec_000a = { + 0x000a, pci_device_13ec_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13ec_000a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13f0_0200 = { + 0x0200, pci_device_13f0_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f0_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f0_0201 = { + 0x0201, pci_device_13f0_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f0_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f0_1023 = { + 0x1023, pci_device_13f0_1023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f0_1023, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13f4_1401 = { + 0x1401, pci_device_13f4_1401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f4_1401, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13f6_0011 = { + 0x0011, pci_device_13f6_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f6_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f6_0100 = { + 0x0100, pci_device_13f6_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f6_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f6_0101 = { + 0x0101, pci_device_13f6_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f6_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f6_0111 = { + 0x0111, pci_device_13f6_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f6_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13f6_0211 = { + 0x0211, pci_device_13f6_0211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13f6_0211, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_13fe_1240 = { + 0x1240, pci_device_13fe_1240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13fe_1600 = { + 0x1600, pci_device_13fe_1600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13fe_16ff = { + 0x16ff, pci_device_13fe_16ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_16ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13fe_1733 = { + 0x1733, pci_device_13fe_1733, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1733, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13fe_1752 = { + 0x1752, pci_device_13fe_1752, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1752, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13fe_1754 = { + 0x1754, pci_device_13fe_1754, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1754, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_13fe_1756 = { + 0x1756, pci_device_13fe_1756, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_13fe_1756, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1400_1401 = { + 0x1401, pci_device_1400_1401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1400_1401, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1407_0100 = { + 0x0100, pci_device_1407_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0101 = { + 0x0101, pci_device_1407_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0102 = { + 0x0102, pci_device_1407_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0110 = { + 0x0110, pci_device_1407_0110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0111 = { + 0x0111, pci_device_1407_0111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0120 = { + 0x0120, pci_device_1407_0120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0121 = { + 0x0121, pci_device_1407_0121, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0121, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0180 = { + 0x0180, pci_device_1407_0180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0181 = { + 0x0181, pci_device_1407_0181, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0181, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0200 = { + 0x0200, pci_device_1407_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0201 = { + 0x0201, pci_device_1407_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0202 = { + 0x0202, pci_device_1407_0202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0220 = { + 0x0220, pci_device_1407_0220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0221 = { + 0x0221, pci_device_1407_0221, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0221, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0500 = { + 0x0500, pci_device_1407_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_0600 = { + 0x0600, pci_device_1407_0600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_0600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8000 = { + 0x8000, pci_device_1407_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8001 = { + 0x8001, pci_device_1407_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8002 = { + 0x8002, pci_device_1407_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8003 = { + 0x8003, pci_device_1407_8003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1407_8800 = { + 0x8800, pci_device_1407_8800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1407_8800, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1409_7168 = { + 0x7168, pci_device_1409_7168, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1409_7168, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1412_1712 = { + 0x1712, pci_device_1412_1712, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1412_1712, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1412_1724 = { + 0x1724, pci_device_1412_1724, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1412_1724, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1415_8403 = { + 0x8403, pci_device_1415_8403, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_8403, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9500 = { + 0x9500, pci_device_1415_9500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9501 = { + 0x9501, pci_device_1415_9501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_950a = { + 0x950a, pci_device_1415_950a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_950a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_950b = { + 0x950b, pci_device_1415_950b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_950b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9510 = { + 0x9510, pci_device_1415_9510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9511 = { + 0x9511, pci_device_1415_9511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9512 = { + 0x9512, pci_device_1415_9512, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9512, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9513 = { + 0x9513, pci_device_1415_9513, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9513, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9521 = { + 0x9521, pci_device_1415_9521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9521, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1415_9523 = { + 0x9523, pci_device_1415_9523, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1415_9523, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1420_8002 = { + 0x8002, pci_device_1420_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1420_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1420_8003 = { + 0x8003, pci_device_1420_8003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1420_8003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1425_000b = { + 0x000b, pci_device_1425_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1425_000b, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_142e_4020 = { + 0x4020, pci_device_142e_4020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_142e_4020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_142e_4337 = { + 0x4337, pci_device_142e_4337, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_142e_4337, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1432_9130 = { + 0x9130, pci_device_1432_9130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1432_9130, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1435_4520 = { + 0x4520, pci_device_1435_4520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1435_4520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1435_6020 = { + 0x6020, pci_device_1435_6020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1435_6020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1435_6030 = { + 0x6030, pci_device_1435_6030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1435_6030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1435_6420 = { + 0x6420, pci_device_1435_6420, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1435_6420, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1435_6430 = { + 0x6430, pci_device_1435_6430, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1435_6430, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1435_7520 = { + 0x7520, pci_device_1435_7520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1435_7520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1435_7820 = { + 0x7820, pci_device_1435_7820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1435_7820, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_144a_7296 = { + 0x7296, pci_device_144a_7296, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7296, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_7432 = { + 0x7432, pci_device_144a_7432, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7432, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_7433 = { + 0x7433, pci_device_144a_7433, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7433, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_7434 = { + 0x7434, pci_device_144a_7434, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7434, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_7841 = { + 0x7841, pci_device_144a_7841, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_7841, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_8133 = { + 0x8133, pci_device_144a_8133, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_8133, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_8164 = { + 0x8164, pci_device_144a_8164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_8164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_8554 = { + 0x8554, pci_device_144a_8554, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_8554, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_9111 = { + 0x9111, pci_device_144a_9111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_9111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_9113 = { + 0x9113, pci_device_144a_9113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_9113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_144a_9114 = { + 0x9114, pci_device_144a_9114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144a_9114, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_144d_c00c = { + 0xc00c, pci_device_144d_c00c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_144d_c00c, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1458_0c11 = { + 0x0c11, pci_device_1458_0c11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1458_0c11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1458_e911 = { + 0xe911, pci_device_1458_e911, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1458_e911, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_145f_0001 = { + 0x0001, pci_device_145f_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_145f_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1461_f436 = { + 0xf436, pci_device_1461_f436, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1461_f436, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1462_5501 = { + 0x5501, pci_device_1462_5501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_5501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_6819 = { + 0x6819, pci_device_1462_6819, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_6819, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_6825 = { + 0x6825, pci_device_1462_6825, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_6825, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_6834 = { + 0x6834, pci_device_1462_6834, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_6834, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_7125 = { + 0x7125, pci_device_1462_7125, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_7125, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_8725 = { + 0x8725, pci_device_1462_8725, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_8725, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_9000 = { + 0x9000, pci_device_1462_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_9110 = { + 0x9110, pci_device_1462_9110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_9110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_9119 = { + 0x9119, pci_device_1462_9119, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_9119, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_9123 = { + 0x9123, pci_device_1462_9123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_9123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_9510 = { + 0x9510, pci_device_1462_9510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_9510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_9511 = { + 0x9511, pci_device_1462_9511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_9511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1462_9591 = { + 0x9591, pci_device_1462_9591, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1462_9591, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_146c_1430 = { + 0x1430, pci_device_146c_1430, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_146c_1430, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_148d_1003 = { + 0x1003, pci_device_148d_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_148d_1003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1497_1497 = { + 0x1497, pci_device_1497_1497, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1497_1497, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1498_0330 = { + 0x0330, pci_device_1498_0330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1498_0330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1498_0385 = { + 0x0385, pci_device_1498_0385, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1498_0385, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1498_21cc = { + 0x21cc, pci_device_1498_21cc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1498_21cc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1498_21cd = { + 0x21cd, pci_device_1498_21cd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1498_21cd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1498_30c8 = { + 0x30c8, pci_device_1498_30c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1498_30c8, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_149d_0001 = { + 0x0001, pci_device_149d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_149d_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14af_7102 = { + 0x7102, pci_device_14af_7102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14af_7102, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14b3_0000 = { + 0x0000, pci_device_14b3_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b3_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14b5_0200 = { + 0x0200, pci_device_14b5_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0300 = { + 0x0300, pci_device_14b5_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0400 = { + 0x0400, pci_device_14b5_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0600 = { + 0x0600, pci_device_14b5_0600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0800 = { + 0x0800, pci_device_14b5_0800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0900 = { + 0x0900, pci_device_14b5_0900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0a00 = { + 0x0a00, pci_device_14b5_0a00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0a00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b5_0b00 = { + 0x0b00, pci_device_14b5_0b00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b5_0b00, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14b7_0001 = { + 0x0001, pci_device_14b7_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b7_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14b9_0001 = { + 0x0001, pci_device_14b9_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_0340 = { + 0x0340, pci_device_14b9_0340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_0340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_0350 = { + 0x0350, pci_device_14b9_0350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_0350, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_4500 = { + 0x4500, pci_device_14b9_4500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_4500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_4800 = { + 0x4800, pci_device_14b9_4800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_4800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_a504 = { + 0xa504, pci_device_14b9_a504, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_a504, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_a505 = { + 0xa505, pci_device_14b9_a505, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_a505, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14b9_a506 = { + 0xa506, pci_device_14b9_a506, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14b9_a506, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14bc_d002 = { + 0xd002, pci_device_14bc_d002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14bc_d002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14bc_d00f = { + 0xd00f, pci_device_14bc_d00f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14bc_d00f, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14c1_0008 = { + 0x0008, pci_device_14c1_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14c1_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14c1_8043 = { + 0x8043, pci_device_14c1_8043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14c1_8043, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14d2_8001 = { + 0x8001, pci_device_14d2_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8002 = { + 0x8002, pci_device_14d2_8002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8010 = { + 0x8010, pci_device_14d2_8010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8011 = { + 0x8011, pci_device_14d2_8011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8020 = { + 0x8020, pci_device_14d2_8020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8021 = { + 0x8021, pci_device_14d2_8021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8040 = { + 0x8040, pci_device_14d2_8040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_8080 = { + 0x8080, pci_device_14d2_8080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_8080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a000 = { + 0xa000, pci_device_14d2_a000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a001 = { + 0xa001, pci_device_14d2_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a003 = { + 0xa003, pci_device_14d2_a003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a004 = { + 0xa004, pci_device_14d2_a004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_a005 = { + 0xa005, pci_device_14d2_a005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_a005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_e001 = { + 0xe001, pci_device_14d2_e001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_e001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_e010 = { + 0xe010, pci_device_14d2_e010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_e010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d2_e020 = { + 0xe020, pci_device_14d2_e020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d2_e020, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14d9_0010 = { + 0x0010, pci_device_14d9_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d9_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14d9_9000 = { + 0x9000, pci_device_14d9_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14d9_9000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14db_2120 = { + 0x2120, pci_device_14db_2120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14db_2120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14db_2182 = { + 0x2182, pci_device_14db_2182, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14db_2182, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14dc_0000 = { + 0x0000, pci_device_14dc_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0001 = { + 0x0001, pci_device_14dc_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0002 = { + 0x0002, pci_device_14dc_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0003 = { + 0x0003, pci_device_14dc_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0004 = { + 0x0004, pci_device_14dc_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0005 = { + 0x0005, pci_device_14dc_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0006 = { + 0x0006, pci_device_14dc_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0007 = { + 0x0007, pci_device_14dc_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0008 = { + 0x0008, pci_device_14dc_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_0009 = { + 0x0009, pci_device_14dc_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_000a = { + 0x000a, pci_device_14dc_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14dc_000b = { + 0x000b, pci_device_14dc_000b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14dc_000b, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14e4_0800 = { + 0x0800, pci_device_14e4_0800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_0804 = { + 0x0804, pci_device_14e4_0804, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0804, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_0805 = { + 0x0805, pci_device_14e4_0805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_0806 = { + 0x0806, pci_device_14e4_0806, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0806, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_080b = { + 0x080b, pci_device_14e4_080b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_080b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_080f = { + 0x080f, pci_device_14e4_080f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_080f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_0811 = { + 0x0811, pci_device_14e4_0811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_0816 = { + 0x0816, pci_device_14e4_0816, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_0816, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1600 = { + 0x1600, pci_device_14e4_1600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1601 = { + 0x1601, pci_device_14e4_1601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1644 = { + 0x1644, pci_device_14e4_1644, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1644, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1645 = { + 0x1645, pci_device_14e4_1645, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1645, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1646 = { + 0x1646, pci_device_14e4_1646, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1646, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1647 = { + 0x1647, pci_device_14e4_1647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1648 = { + 0x1648, pci_device_14e4_1648, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1648, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_164a = { + 0x164a, pci_device_14e4_164a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_164a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_164c = { + 0x164c, pci_device_14e4_164c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_164c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_164d = { + 0x164d, pci_device_14e4_164d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_164d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1653 = { + 0x1653, pci_device_14e4_1653, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1653, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1654 = { + 0x1654, pci_device_14e4_1654, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1654, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1659 = { + 0x1659, pci_device_14e4_1659, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1659, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_165d = { + 0x165d, pci_device_14e4_165d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_165d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_165e = { + 0x165e, pci_device_14e4_165e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_165e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1668 = { + 0x1668, pci_device_14e4_1668, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1668, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1669 = { + 0x1669, pci_device_14e4_1669, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1669, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_166a = { + 0x166a, pci_device_14e4_166a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_166a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_166b = { + 0x166b, pci_device_14e4_166b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_166b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_166e = { + 0x166e, pci_device_14e4_166e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_166e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1672 = { + 0x1672, pci_device_14e4_1672, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1672, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1673 = { + 0x1673, pci_device_14e4_1673, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1673, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1677 = { + 0x1677, pci_device_14e4_1677, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1677, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1678 = { + 0x1678, pci_device_14e4_1678, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1678, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1679 = { + 0x1679, pci_device_14e4_1679, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1679, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_167a = { + 0x167a, pci_device_14e4_167a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_167a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_167b = { + 0x167b, pci_device_14e4_167b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_167b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_167d = { + 0x167d, pci_device_14e4_167d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_167d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_167e = { + 0x167e, pci_device_14e4_167e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_167e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1693 = { + 0x1693, pci_device_14e4_1693, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1693, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_1696 = { + 0x1696, pci_device_14e4_1696, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_1696, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_169a = { + 0x169a, pci_device_14e4_169a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_169a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_169b = { + 0x169b, pci_device_14e4_169b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_169b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_169c = { + 0x169c, pci_device_14e4_169c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_169c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_169d = { + 0x169d, pci_device_14e4_169d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_169d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16a6 = { + 0x16a6, pci_device_14e4_16a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16a7 = { + 0x16a7, pci_device_14e4_16a7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16a7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16a8 = { + 0x16a8, pci_device_14e4_16a8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16a8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16aa = { + 0x16aa, pci_device_14e4_16aa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16aa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16ac = { + 0x16ac, pci_device_14e4_16ac, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16ac, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16c6 = { + 0x16c6, pci_device_14e4_16c6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16c6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16c7 = { + 0x16c7, pci_device_14e4_16c7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16c7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16dd = { + 0x16dd, pci_device_14e4_16dd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16dd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16f7 = { + 0x16f7, pci_device_14e4_16f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16f7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16fd = { + 0x16fd, pci_device_14e4_16fd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16fd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_16fe = { + 0x16fe, pci_device_14e4_16fe, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_16fe, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_170c = { + 0x170c, pci_device_14e4_170c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_170c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_170d = { + 0x170d, pci_device_14e4_170d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_170d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_170e = { + 0x170e, pci_device_14e4_170e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_170e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_3352 = { + 0x3352, pci_device_14e4_3352, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_3352, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_3360 = { + 0x3360, pci_device_14e4_3360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_3360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4210 = { + 0x4210, pci_device_14e4_4210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4211 = { + 0x4211, pci_device_14e4_4211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4212 = { + 0x4212, pci_device_14e4_4212, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4212, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4301 = { + 0x4301, pci_device_14e4_4301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4305 = { + 0x4305, pci_device_14e4_4305, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4305, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4306 = { + 0x4306, pci_device_14e4_4306, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4306, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4307 = { + 0x4307, pci_device_14e4_4307, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4307, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4310 = { + 0x4310, pci_device_14e4_4310, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4310, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4311 = { + 0x4311, pci_device_14e4_4311, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4311, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4312 = { + 0x4312, pci_device_14e4_4312, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4312, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4313 = { + 0x4313, pci_device_14e4_4313, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4313, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4315 = { + 0x4315, pci_device_14e4_4315, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4315, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4318 = { + 0x4318, pci_device_14e4_4318, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4318, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4319 = { + 0x4319, pci_device_14e4_4319, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4319, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4320 = { + 0x4320, pci_device_14e4_4320, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4320, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4321 = { + 0x4321, pci_device_14e4_4321, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4321, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4322 = { + 0x4322, pci_device_14e4_4322, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4322, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4324 = { + 0x4324, pci_device_14e4_4324, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4324, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4325 = { + 0x4325, pci_device_14e4_4325, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4325, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4326 = { + 0x4326, pci_device_14e4_4326, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4326, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4329 = { + 0x4329, pci_device_14e4_4329, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4329, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4401 = { + 0x4401, pci_device_14e4_4401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4401, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4402 = { + 0x4402, pci_device_14e4_4402, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4402, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4403 = { + 0x4403, pci_device_14e4_4403, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4403, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4410 = { + 0x4410, pci_device_14e4_4410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4411 = { + 0x4411, pci_device_14e4_4411, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4411, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4412 = { + 0x4412, pci_device_14e4_4412, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4412, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4430 = { + 0x4430, pci_device_14e4_4430, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4430, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4432 = { + 0x4432, pci_device_14e4_4432, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4432, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4610 = { + 0x4610, pci_device_14e4_4610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4611 = { + 0x4611, pci_device_14e4_4611, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4611, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4612 = { + 0x4612, pci_device_14e4_4612, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4612, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4613 = { + 0x4613, pci_device_14e4_4613, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4613, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4614 = { + 0x4614, pci_device_14e4_4614, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4614, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4615 = { + 0x4615, pci_device_14e4_4615, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4615, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4704 = { + 0x4704, pci_device_14e4_4704, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4704, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4705 = { + 0x4705, pci_device_14e4_4705, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4705, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4706 = { + 0x4706, pci_device_14e4_4706, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4706, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4707 = { + 0x4707, pci_device_14e4_4707, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4707, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4708 = { + 0x4708, pci_device_14e4_4708, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4708, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4710 = { + 0x4710, pci_device_14e4_4710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4711 = { + 0x4711, pci_device_14e4_4711, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4711, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4712 = { + 0x4712, pci_device_14e4_4712, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4712, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4713 = { + 0x4713, pci_device_14e4_4713, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4713, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4714 = { + 0x4714, pci_device_14e4_4714, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4714, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4715 = { + 0x4715, pci_device_14e4_4715, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4715, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4716 = { + 0x4716, pci_device_14e4_4716, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4716, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4717 = { + 0x4717, pci_device_14e4_4717, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4717, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4718 = { + 0x4718, pci_device_14e4_4718, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4718, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4719 = { + 0x4719, pci_device_14e4_4719, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4719, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_4720 = { + 0x4720, pci_device_14e4_4720, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_4720, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5365 = { + 0x5365, pci_device_14e4_5365, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5365, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5600 = { + 0x5600, pci_device_14e4_5600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5605 = { + 0x5605, pci_device_14e4_5605, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5605, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5615 = { + 0x5615, pci_device_14e4_5615, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5615, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5625 = { + 0x5625, pci_device_14e4_5625, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5625, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5645 = { + 0x5645, pci_device_14e4_5645, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5645, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5670 = { + 0x5670, pci_device_14e4_5670, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5670, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5680 = { + 0x5680, pci_device_14e4_5680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5690 = { + 0x5690, pci_device_14e4_5690, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5690, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5691 = { + 0x5691, pci_device_14e4_5691, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5691, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5692 = { + 0x5692, pci_device_14e4_5692, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5692, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5820 = { + 0x5820, pci_device_14e4_5820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5820, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5821 = { + 0x5821, pci_device_14e4_5821, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5821, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5822 = { + 0x5822, pci_device_14e4_5822, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5822, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5823 = { + 0x5823, pci_device_14e4_5823, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5823, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5824 = { + 0x5824, pci_device_14e4_5824, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5824, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5840 = { + 0x5840, pci_device_14e4_5840, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5840, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5841 = { + 0x5841, pci_device_14e4_5841, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5841, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14e4_5850 = { + 0x5850, pci_device_14e4_5850, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14e4_5850, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14ea_ab06 = { + 0xab06, pci_device_14ea_ab06, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14ea_ab06, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14ea_ab07 = { + 0xab07, pci_device_14ea_ab07, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14ea_ab07, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14ea_ab08 = { + 0xab08, pci_device_14ea_ab08, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14ea_ab08, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14f1_1002 = { + 0x1002, pci_device_14f1_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1003 = { + 0x1003, pci_device_14f1_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1004 = { + 0x1004, pci_device_14f1_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1005 = { + 0x1005, pci_device_14f1_1005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1006 = { + 0x1006, pci_device_14f1_1006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1022 = { + 0x1022, pci_device_14f1_1022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1023 = { + 0x1023, pci_device_14f1_1023, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1023, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1024 = { + 0x1024, pci_device_14f1_1024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1025 = { + 0x1025, pci_device_14f1_1025, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1025, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1026 = { + 0x1026, pci_device_14f1_1026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1032 = { + 0x1032, pci_device_14f1_1032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1033 = { + 0x1033, pci_device_14f1_1033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1034 = { + 0x1034, pci_device_14f1_1034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1035 = { + 0x1035, pci_device_14f1_1035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1036 = { + 0x1036, pci_device_14f1_1036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1052 = { + 0x1052, pci_device_14f1_1052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1053 = { + 0x1053, pci_device_14f1_1053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1054 = { + 0x1054, pci_device_14f1_1054, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1054, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1055 = { + 0x1055, pci_device_14f1_1055, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1055, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1056 = { + 0x1056, pci_device_14f1_1056, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1056, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1057 = { + 0x1057, pci_device_14f1_1057, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1057, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1059 = { + 0x1059, pci_device_14f1_1059, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1059, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1063 = { + 0x1063, pci_device_14f1_1063, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1063, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1064 = { + 0x1064, pci_device_14f1_1064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1065 = { + 0x1065, pci_device_14f1_1065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1066 = { + 0x1066, pci_device_14f1_1066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1085 = { + 0x1085, pci_device_14f1_1085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1433 = { + 0x1433, pci_device_14f1_1433, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1433, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1434 = { + 0x1434, pci_device_14f1_1434, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1434, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1435 = { + 0x1435, pci_device_14f1_1435, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1435, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1436 = { + 0x1436, pci_device_14f1_1436, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1436, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1453 = { + 0x1453, pci_device_14f1_1453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1454 = { + 0x1454, pci_device_14f1_1454, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1454, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1455 = { + 0x1455, pci_device_14f1_1455, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1455, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1456 = { + 0x1456, pci_device_14f1_1456, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1456, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1610 = { + 0x1610, pci_device_14f1_1610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1611 = { + 0x1611, pci_device_14f1_1611, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1611, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1620 = { + 0x1620, pci_device_14f1_1620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1621 = { + 0x1621, pci_device_14f1_1621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1622 = { + 0x1622, pci_device_14f1_1622, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1622, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1803 = { + 0x1803, pci_device_14f1_1803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1811 = { + 0x1811, pci_device_14f1_1811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_1815 = { + 0x1815, pci_device_14f1_1815, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_1815, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2003 = { + 0x2003, pci_device_14f1_2003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2004 = { + 0x2004, pci_device_14f1_2004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2005 = { + 0x2005, pci_device_14f1_2005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2006 = { + 0x2006, pci_device_14f1_2006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2013 = { + 0x2013, pci_device_14f1_2013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2014 = { + 0x2014, pci_device_14f1_2014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2015 = { + 0x2015, pci_device_14f1_2015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2016 = { + 0x2016, pci_device_14f1_2016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2043 = { + 0x2043, pci_device_14f1_2043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2044 = { + 0x2044, pci_device_14f1_2044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2044, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2045 = { + 0x2045, pci_device_14f1_2045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2046 = { + 0x2046, pci_device_14f1_2046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2063 = { + 0x2063, pci_device_14f1_2063, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2063, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2064 = { + 0x2064, pci_device_14f1_2064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2065 = { + 0x2065, pci_device_14f1_2065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2066 = { + 0x2066, pci_device_14f1_2066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2093 = { + 0x2093, pci_device_14f1_2093, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2093, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2143 = { + 0x2143, pci_device_14f1_2143, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2143, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2144 = { + 0x2144, pci_device_14f1_2144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2145 = { + 0x2145, pci_device_14f1_2145, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2145, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2146 = { + 0x2146, pci_device_14f1_2146, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2146, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2163 = { + 0x2163, pci_device_14f1_2163, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2163, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2164 = { + 0x2164, pci_device_14f1_2164, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2164, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2165 = { + 0x2165, pci_device_14f1_2165, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2165, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2166 = { + 0x2166, pci_device_14f1_2166, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2166, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2343 = { + 0x2343, pci_device_14f1_2343, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2343, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2344 = { + 0x2344, pci_device_14f1_2344, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2344, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2345 = { + 0x2345, pci_device_14f1_2345, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2345, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2346 = { + 0x2346, pci_device_14f1_2346, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2346, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2363 = { + 0x2363, pci_device_14f1_2363, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2363, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2364 = { + 0x2364, pci_device_14f1_2364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2365 = { + 0x2365, pci_device_14f1_2365, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2365, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2366 = { + 0x2366, pci_device_14f1_2366, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2366, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2443 = { + 0x2443, pci_device_14f1_2443, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2443, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2444 = { + 0x2444, pci_device_14f1_2444, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2444, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2445 = { + 0x2445, pci_device_14f1_2445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2446 = { + 0x2446, pci_device_14f1_2446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2463 = { + 0x2463, pci_device_14f1_2463, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2463, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2464 = { + 0x2464, pci_device_14f1_2464, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2464, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2465 = { + 0x2465, pci_device_14f1_2465, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2465, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2466 = { + 0x2466, pci_device_14f1_2466, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2466, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2bfa = { + 0x2bfa, pci_device_14f1_2bfa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2bfa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2f00 = { + 0x2f00, pci_device_14f1_2f00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2f00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2f02 = { + 0x2f02, pci_device_14f1_2f02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2f02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2f11 = { + 0x2f11, pci_device_14f1_2f11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2f11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_2f20 = { + 0x2f20, pci_device_14f1_2f20, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_2f20, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8234 = { + 0x8234, pci_device_14f1_8234, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8234, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8800 = { + 0x8800, pci_device_14f1_8800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8801 = { + 0x8801, pci_device_14f1_8801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8802 = { + 0x8802, pci_device_14f1_8802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8804 = { + 0x8804, pci_device_14f1_8804, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8804, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f1_8811 = { + 0x8811, pci_device_14f1_8811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f1_8811, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14f2_0120 = { + 0x0120, pci_device_14f2_0120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f2_0120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f2_0121 = { + 0x0121, pci_device_14f2_0121, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f2_0121, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f2_0122 = { + 0x0122, pci_device_14f2_0122, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f2_0122, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f2_0123 = { + 0x0123, pci_device_14f2_0123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f2_0123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f2_0124 = { + 0x0124, pci_device_14f2_0124, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f2_0124, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14f3_2030 = { + 0x2030, pci_device_14f3_2030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f3_2030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f3_2050 = { + 0x2050, pci_device_14f3_2050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f3_2050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14f3_2060 = { + 0x2060, pci_device_14f3_2060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f3_2060, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14f8_2077 = { + 0x2077, pci_device_14f8_2077, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14f8_2077, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_14fc_0000 = { + 0x0000, pci_device_14fc_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14fc_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14fc_0001 = { + 0x0001, pci_device_14fc_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14fc_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_14fc_0002 = { + 0x0002, pci_device_14fc_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_14fc_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1500_1360 = { + 0x1360, pci_device_1500_1360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1500_1360, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1507_0001 = { + 0x0001, pci_device_1507_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_0002 = { + 0x0002, pci_device_1507_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_0003 = { + 0x0003, pci_device_1507_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_0100 = { + 0x0100, pci_device_1507_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_0431 = { + 0x0431, pci_device_1507_0431, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_0431, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_4801 = { + 0x4801, pci_device_1507_4801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_4801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_4802 = { + 0x4802, pci_device_1507_4802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_4802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_4803 = { + 0x4803, pci_device_1507_4803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_4803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1507_4806 = { + 0x4806, pci_device_1507_4806, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1507_4806, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1516_0800 = { + 0x0800, pci_device_1516_0800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1516_0800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1516_0803 = { + 0x0803, pci_device_1516_0803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1516_0803, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1516_0891 = { + 0x0891, pci_device_1516_0891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1516_0891, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_151a_1002 = { + 0x1002, pci_device_151a_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151a_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_151a_1004 = { + 0x1004, pci_device_151a_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151a_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_151a_1008 = { + 0x1008, pci_device_151a_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151a_1008, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_151c_0003 = { + 0x0003, pci_device_151c_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151c_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_151c_4000 = { + 0x4000, pci_device_151c_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151c_4000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_151f_0000 = { + 0x0000, pci_device_151f_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_151f_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1522_0100 = { + 0x0100, pci_device_1522_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1522_0100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1524_0510 = { + 0x0510, pci_device_1524_0510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_0510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_0520 = { + 0x0520, pci_device_1524_0520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_0520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_0530 = { + 0x0530, pci_device_1524_0530, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_0530, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_0550 = { + 0x0550, pci_device_1524_0550, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_0550, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_0610 = { + 0x0610, pci_device_1524_0610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_0610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1211 = { + 0x1211, pci_device_1524_1211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1225 = { + 0x1225, pci_device_1524_1225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1410 = { + 0x1410, pci_device_1524_1410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1411 = { + 0x1411, pci_device_1524_1411, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1411, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1412 = { + 0x1412, pci_device_1524_1412, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1412, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1420 = { + 0x1420, pci_device_1524_1420, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1420, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1421 = { + 0x1421, pci_device_1524_1421, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1421, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1524_1422 = { + 0x1422, pci_device_1524_1422, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1524_1422, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1532_0020 = { + 0x0020, pci_device_1532_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1532_0020, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1538_0303 = { + 0x0303, pci_device_1538_0303, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1538_0303, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_153b_1144 = { + 0x1144, pci_device_153b_1144, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_153b_1144, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_153b_1147 = { + 0x1147, pci_device_153b_1147, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_153b_1147, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_153b_1158 = { + 0x1158, pci_device_153b_1158, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_153b_1158, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_153f_0001 = { + 0x0001, pci_device_153f_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_153f_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1542_9260 = { + 0x9260, pci_device_1542_9260, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1542_9260, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1543_3052 = { + 0x3052, pci_device_1543_3052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1543_3052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1543_4c22 = { + 0x4c22, pci_device_1543_4c22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1543_4c22, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1571_a001 = { + 0xa001, pci_device_1571_a001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a002 = { + 0xa002, pci_device_1571_a002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a003 = { + 0xa003, pci_device_1571_a003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a004 = { + 0xa004, pci_device_1571_a004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a005 = { + 0xa005, pci_device_1571_a005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a006 = { + 0xa006, pci_device_1571_a006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a007 = { + 0xa007, pci_device_1571_a007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a008 = { + 0xa008, pci_device_1571_a008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a009 = { + 0xa009, pci_device_1571_a009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a00a = { + 0xa00a, pci_device_1571_a00a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a00a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a00b = { + 0xa00b, pci_device_1571_a00b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a00b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a00c = { + 0xa00c, pci_device_1571_a00c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a00c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a00d = { + 0xa00d, pci_device_1571_a00d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a00d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a201 = { + 0xa201, pci_device_1571_a201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a202 = { + 0xa202, pci_device_1571_a202, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a202, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a203 = { + 0xa203, pci_device_1571_a203, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a203, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a204 = { + 0xa204, pci_device_1571_a204, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a204, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a205 = { + 0xa205, pci_device_1571_a205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1571_a206 = { + 0xa206, pci_device_1571_a206, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1571_a206, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1578_5615 = { + 0x5615, pci_device_1578_5615, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1578_5615, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_157c_8001 = { + 0x8001, pci_device_157c_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_157c_8001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1592_0781 = { + 0x0781, pci_device_1592_0781, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0781, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0782 = { + 0x0782, pci_device_1592_0782, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0782, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0783 = { + 0x0783, pci_device_1592_0783, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0783, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0785 = { + 0x0785, pci_device_1592_0785, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0785, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0786 = { + 0x0786, pci_device_1592_0786, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0786, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0787 = { + 0x0787, pci_device_1592_0787, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0787, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_0788 = { + 0x0788, pci_device_1592_0788, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_0788, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1592_078a = { + 0x078a, pci_device_1592_078a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1592_078a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15a2_0001 = { + 0x0001, pci_device_15a2_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15a2_0001, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_15ad_0405 = { + 0x0405, pci_device_15ad_0405, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15ad_0405, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15ad_0710 = { + 0x0710, pci_device_15ad_0710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15ad_0710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15ad_0720 = { + 0x0720, pci_device_15ad_0720, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15ad_0720, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15b3_5274 = { + 0x5274, pci_device_15b3_5274, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_5274, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_5a44 = { + 0x5a44, pci_device_15b3_5a44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_5a44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_5a45 = { + 0x5a45, pci_device_15b3_5a45, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_5a45, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_5a46 = { + 0x5a46, pci_device_15b3_5a46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_5a46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_5e8d = { + 0x5e8d, pci_device_15b3_5e8d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_5e8d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_6274 = { + 0x6274, pci_device_15b3_6274, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_6274, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_6278 = { + 0x6278, pci_device_15b3_6278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_6278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_6279 = { + 0x6279, pci_device_15b3_6279, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_6279, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15b3_6282 = { + 0x6282, pci_device_15b3_6282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15b3_6282, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15bc_1100 = { + 0x1100, pci_device_15bc_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15bc_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15bc_2922 = { + 0x2922, pci_device_15bc_2922, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15bc_2922, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15bc_2928 = { + 0x2928, pci_device_15bc_2928, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15bc_2928, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15bc_2929 = { + 0x2929, pci_device_15bc_2929, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15bc_2929, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15c5_8010 = { + 0x8010, pci_device_15c5_8010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15c5_8010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15c7_0349 = { + 0x0349, pci_device_15c7_0349, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15c7_0349, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15dc_0001 = { + 0x0001, pci_device_15dc_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15dc_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15e8_0130 = { + 0x0130, pci_device_15e8_0130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15e8_0130, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15e9_1841 = { + 0x1841, pci_device_15e9_1841, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15e9_1841, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_15ec_3101 = { + 0x3101, pci_device_15ec_3101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15ec_3101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_15ec_5102 = { + 0x5102, pci_device_15ec_5102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_15ec_5102, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1619_0400 = { + 0x0400, pci_device_1619_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_0400, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_0440 = { + 0x0440, pci_device_1619_0440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_0440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_0610 = { + 0x0610, pci_device_1619_0610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_0610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_0620 = { + 0x0620, pci_device_1619_0620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_0620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_0640 = { + 0x0640, pci_device_1619_0640, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_0640, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_1610 = { + 0x1610, pci_device_1619_1610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_1610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1619_2610 = { + 0x2610, pci_device_1619_2610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1619_2610, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1626_8410 = { + 0x8410, pci_device_1626_8410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1626_8410, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1629_1003 = { + 0x1003, pci_device_1629_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1629_1003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1629_2002 = { + 0x2002, pci_device_1629_2002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1629_2002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1637_3874 = { + 0x3874, pci_device_1637_3874, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1637_3874, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1638_1100 = { + 0x1100, pci_device_1638_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1638_1100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_163c_3052 = { + 0x3052, pci_device_163c_3052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_163c_3052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_163c_5449 = { + 0x5449, pci_device_163c_5449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_163c_5449, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_165a_c100 = { + 0xc100, pci_device_165a_c100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_165a_c100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_165a_d200 = { + 0xd200, pci_device_165a_d200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_165a_d200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_165a_d300 = { + 0xd300, pci_device_165a_d300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_165a_d300, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_165f_1020 = { + 0x1020, pci_device_165f_1020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_165f_1020, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1668_0100 = { + 0x0100, pci_device_1668_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1668_0100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_166d_0001 = { + 0x0001, pci_device_166d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_166d_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_166d_0002 = { + 0x0002, pci_device_166d_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_166d_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1677_104e = { + 0x104e, pci_device_1677_104e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1677_104e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1677_12d7 = { + 0x12d7, pci_device_1677_12d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1677_12d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1677_20ad = { + 0x20ad, pci_device_1677_20ad, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1677_20ad, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_167b_2102 = { + 0x2102, pci_device_167b_2102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_167b_2102, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_167d_a000 = { + 0xa000, pci_device_167d_a000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_167d_a000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1681_0010 = { + 0x0010, pci_device_1681_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1681_0010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1688_1170 = { + 0x1170, pci_device_1688_1170, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1688_1170, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_168c_0007 = { + 0x0007, pci_device_168c_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_0011 = { + 0x0011, pci_device_168c_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_0012 = { + 0x0012, pci_device_168c_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_0013 = { + 0x0013, pci_device_168c_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_001a = { + 0x001a, pci_device_168c_001a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_001a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_001b = { + 0x001b, pci_device_168c_001b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_001b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_0020 = { + 0x0020, pci_device_168c_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_168c_1014 = { + 0x1014, pci_device_168c_1014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_168c_1014, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_169c_0044 = { + 0x0044, pci_device_169c_0044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_169c_0044, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16ab_1100 = { + 0x1100, pci_device_16ab_1100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ab_1100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_16ab_1101 = { + 0x1101, pci_device_16ab_1101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ab_1101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_16ab_1102 = { + 0x1102, pci_device_16ab_1102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ab_1102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_16ab_8501 = { + 0x8501, pci_device_16ab_8501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ab_8501, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16ae_1141 = { + 0x1141, pci_device_16ae_1141, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ae_1141, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16c6_8695 = { + 0x8695, pci_device_16c6_8695, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16c6_8695, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16ca_0001 = { + 0x0001, pci_device_16ca_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ca_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16d5_4d4e = { + 0x4d4e, pci_device_16d5_4d4e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16d5_4d4e, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16e3_1e0f = { + 0x1e0f, pci_device_16e3_1e0f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16e3_1e0f, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16e5_6000 = { + 0x6000, pci_device_16e5_6000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16e5_6000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16ec_00ff = { + 0x00ff, pci_device_16ec_00ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ec_00ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_16ec_0116 = { + 0x0116, pci_device_16ec_0116, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ec_0116, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_16ec_2f00 = { + 0x2f00, pci_device_16ec_2f00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ec_2f00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_16ec_3685 = { + 0x3685, pci_device_16ec_3685, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ec_3685, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16ed_1001 = { + 0x1001, pci_device_16ed_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16ed_1001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_16f4_8000 = { + 0x8000, pci_device_16f4_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_16f4_8000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_170b_0100 = { + 0x0100, pci_device_170b_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_170b_0100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1725_7174 = { + 0x7174, pci_device_1725_7174, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1725_7174, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_172a_13c8 = { + 0x13c8, pci_device_172a_13c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_172a_13c8, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1734_1078 = { + 0x1078, pci_device_1734_1078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1734_1078, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1737_0013 = { + 0x0013, pci_device_1737_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1737_0015 = { + 0x0015, pci_device_1737_0015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_0015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1737_1032 = { + 0x1032, pci_device_1737_1032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_1032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1737_1064 = { + 0x1064, pci_device_1737_1064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_1064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1737_ab08 = { + 0xab08, pci_device_1737_ab08, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_ab08, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1737_ab09 = { + 0xab09, pci_device_1737_ab09, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1737_ab09, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_173b_03e8 = { + 0x03e8, pci_device_173b_03e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_173b_03e8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_173b_03e9 = { + 0x03e9, pci_device_173b_03e9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_173b_03e9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_173b_03ea = { + 0x03ea, pci_device_173b_03ea, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_173b_03ea, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_173b_03eb = { + 0x03eb, pci_device_173b_03eb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_173b_03eb, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1743_8139 = { + 0x8139, pci_device_1743_8139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1743_8139, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1796_0001 = { + 0x0001, pci_device_1796_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0002 = { + 0x0002, pci_device_1796_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0003 = { + 0x0003, pci_device_1796_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0004 = { + 0x0004, pci_device_1796_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0005 = { + 0x0005, pci_device_1796_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1796_0006 = { + 0x0006, pci_device_1796_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1796_0006, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1799_6001 = { + 0x6001, pci_device_1799_6001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1799_6001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1799_6020 = { + 0x6020, pci_device_1799_6020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1799_6020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1799_6060 = { + 0x6060, pci_device_1799_6060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1799_6060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1799_7000 = { + 0x7000, pci_device_1799_7000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1799_7000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1799_700a = { + 0x700a, pci_device_1799_700a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1799_700a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1799_7010 = { + 0x7010, pci_device_1799_7010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1799_7010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_179c_0557 = { + 0x0557, pci_device_179c_0557, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_0557, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_179c_0566 = { + 0x0566, pci_device_179c_0566, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_0566, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_179c_5031 = { + 0x5031, pci_device_179c_5031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_5031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_179c_5121 = { + 0x5121, pci_device_179c_5121, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_5121, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_179c_5211 = { + 0x5211, pci_device_179c_5211, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_5211, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_179c_5679 = { + 0x5679, pci_device_179c_5679, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_179c_5679, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17a0_8033 = { + 0x8033, pci_device_17a0_8033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17a0_8033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17a0_8034 = { + 0x8034, pci_device_17a0_8034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17a0_8034, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17b3_ab08 = { + 0xab08, pci_device_17b3_ab08, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17b3_ab08, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17b4_0011 = { + 0x0011, pci_device_17b4_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17b4_0011, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17cb_0001 = { + 0x0001, pci_device_17cb_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17cb_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17cb_0002 = { + 0x0002, pci_device_17cb_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17cb_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17cc_2280 = { + 0x2280, pci_device_17cc_2280, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17cc_2280, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17d3_1110 = { + 0x1110, pci_device_17d3_1110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1120 = { + 0x1120, pci_device_17d3_1120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1130 = { + 0x1130, pci_device_17d3_1130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1160 = { + 0x1160, pci_device_17d3_1160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1160, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1210 = { + 0x1210, pci_device_17d3_1210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1220 = { + 0x1220, pci_device_17d3_1220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1230 = { + 0x1230, pci_device_17d3_1230, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1230, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d3_1260 = { + 0x1260, pci_device_17d3_1260, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d3_1260, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17d5_5831 = { + 0x5831, pci_device_17d5_5831, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d5_5831, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17d5_5832 = { + 0x5832, pci_device_17d5_5832, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17d5_5832, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17e4_0001 = { + 0x0001, pci_device_17e4_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17e4_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17e4_0002 = { + 0x0002, pci_device_17e4_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17e4_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17e6_0010 = { + 0x0010, pci_device_17e6_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17e6_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17e6_0011 = { + 0x0011, pci_device_17e6_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17e6_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17e6_0021 = { + 0x0021, pci_device_17e6_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17e6_0021, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_17fe_2120 = { + 0x2120, pci_device_17fe_2120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17fe_2120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_17fe_2220 = { + 0x2220, pci_device_17fe_2220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_17fe_2220, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1813_4000 = { + 0x4000, pci_device_1813_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1813_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1813_4100 = { + 0x4100, pci_device_1813_4100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1813_4100, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1814_0101 = { + 0x0101, pci_device_1814_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1814_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1814_0200 = { + 0x0200, pci_device_1814_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1814_0200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1814_0201 = { + 0x0201, pci_device_1814_0201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1814_0201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1814_0301 = { + 0x0301, pci_device_1814_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1814_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1814_0302 = { + 0x0302, pci_device_1814_0302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1814_0302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1814_0401 = { + 0x0401, pci_device_1814_0401, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1814_0401, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1822_4e35 = { + 0x4e35, pci_device_1822_4e35, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1822_4e35, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_182d_3069 = { + 0x3069, pci_device_182d_3069, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_182d_3069, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_182d_9790 = { + 0x9790, pci_device_182d_9790, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_182d_9790, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_182e_0008 = { + 0x0008, pci_device_182e_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_182e_0008, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_183b_08a7 = { + 0x08a7, pci_device_183b_08a7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_183b_08a7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_183b_08a8 = { + 0x08a8, pci_device_183b_08a8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_183b_08a8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_183b_08a9 = { + 0x08a9, pci_device_183b_08a9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_183b_08a9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_183b_08b0 = { + 0x08b0, pci_device_183b_08b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_183b_08b0, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1864_2110 = { + 0x2110, pci_device_1864_2110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1864_2110, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1867_5a44 = { + 0x5a44, pci_device_1867_5a44, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1867_5a44, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1867_5a45 = { + 0x5a45, pci_device_1867_5a45, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1867_5a45, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1867_5a46 = { + 0x5a46, pci_device_1867_5a46, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1867_5a46, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1867_6278 = { + 0x6278, pci_device_1867_6278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1867_6278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1867_6282 = { + 0x6282, pci_device_1867_6282, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1867_6282, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_187e_3403 = { + 0x3403, pci_device_187e_3403, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_187e_3403, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_187e_340e = { + 0x340e, pci_device_187e_340e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_187e_340e, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1888_0301 = { + 0x0301, pci_device_1888_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1888_0301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1888_0601 = { + 0x0601, pci_device_1888_0601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1888_0601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1888_0710 = { + 0x0710, pci_device_1888_0710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1888_0710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1888_0720 = { + 0x0720, pci_device_1888_0720, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1888_0720, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18ac_d500 = { + 0xd500, pci_device_18ac_d500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ac_d500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ac_d800 = { + 0xd800, pci_device_18ac_d800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ac_d800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ac_d810 = { + 0xd810, pci_device_18ac_d810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ac_d810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ac_d820 = { + 0xd820, pci_device_18ac_d820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ac_d820, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18b8_b001 = { + 0xb001, pci_device_18b8_b001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18b8_b001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18ca_0020 = { + 0x0020, pci_device_18ca_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ca_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ca_0040 = { + 0x0040, pci_device_18ca_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ca_0040, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18d2_3069 = { + 0x3069, pci_device_18d2_3069, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18d2_3069, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18dd_4c6f = { + 0x4c6f, pci_device_18dd_4c6f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18dd_4c6f, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18e6_0001 = { + 0x0001, pci_device_18e6_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18e6_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18ec_c006 = { + 0xc006, pci_device_18ec_c006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ec_c006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ec_c045 = { + 0xc045, pci_device_18ec_c045, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ec_c045, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ec_c050 = { + 0xc050, pci_device_18ec_c050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ec_c050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18ec_c058 = { + 0xc058, pci_device_18ec_c058, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18ec_c058, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18f6_1000 = { + 0x1000, pci_device_18f6_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18f6_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18f6_1050 = { + 0x1050, pci_device_18f6_1050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18f6_1050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18f6_2000 = { + 0x2000, pci_device_18f6_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18f6_2000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_18f7_0001 = { + 0x0001, pci_device_18f7_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18f7_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18f7_0002 = { + 0x0002, pci_device_18f7_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18f7_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18f7_0004 = { + 0x0004, pci_device_18f7_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18f7_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18f7_0005 = { + 0x0005, pci_device_18f7_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18f7_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_18f7_000a = { + 0x000a, pci_device_18f7_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_18f7_000a, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1904_8139 = { + 0x8139, pci_device_1904_8139, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1904_8139, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1923_0040 = { + 0x0040, pci_device_1923_0040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1923_0040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1923_0100 = { + 0x0100, pci_device_1923_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1923_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1923_0300 = { + 0x0300, pci_device_1923_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1923_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1923_0400 = { + 0x0400, pci_device_1923_0400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1923_0400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1931_000c = { + 0x000c, pci_device_1931_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1931_000c, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1942_e511 = { + 0xe511, pci_device_1942_e511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1942_e511, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_194a_1111 = { + 0x1111, pci_device_194a_1111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_194a_1111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_194a_1112 = { + 0x1112, pci_device_194a_1112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_194a_1112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_194a_1113 = { + 0x1113, pci_device_194a_1113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_194a_1113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_194a_1114 = { + 0x1114, pci_device_194a_1114, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_194a_1114, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_194a_1115 = { + 0x1115, pci_device_194a_1115, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_194a_1115, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1957_0012 = { + 0x0012, pci_device_1957_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0080 = { + 0x0080, pci_device_1957_0080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0081 = { + 0x0081, pci_device_1957_0081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0082 = { + 0x0082, pci_device_1957_0082, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0082, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0083 = { + 0x0083, pci_device_1957_0083, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0083, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0084 = { + 0x0084, pci_device_1957_0084, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0084, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0085 = { + 0x0085, pci_device_1957_0085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0086 = { + 0x0086, pci_device_1957_0086, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0086, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1957_0087 = { + 0x0087, pci_device_1957_0087, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1957_0087, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1966_1975 = { + 0x1975, pci_device_1966_1975, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1966_1975, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1969_1048 = { + 0x1048, pci_device_1969_1048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1969_1048, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_196a_0101 = { + 0x0101, pci_device_196a_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_196a_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_196a_0102 = { + 0x0102, pci_device_196a_0102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_196a_0102, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_197b_2360 = { + 0x2360, pci_device_197b_2360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_197b_2360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_197b_2361 = { + 0x2361, pci_device_197b_2361, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_197b_2361, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_197b_2363 = { + 0x2363, pci_device_197b_2363, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_197b_2363, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_197b_2365 = { + 0x2365, pci_device_197b_2365, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_197b_2365, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_197b_2366 = { + 0x2366, pci_device_197b_2366, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_197b_2366, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1989_0001 = { + 0x0001, pci_device_1989_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1989_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1989_8001 = { + 0x8001, pci_device_1989_8001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1989_8001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_19ac_0001 = { + 0x0001, pci_device_19ac_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_19ac_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_19ae_0520 = { + 0x0520, pci_device_19ae_0520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_19ae_0520, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_19e7_1001 = { + 0x1001, pci_device_19e7_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_19e7_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_19e7_1002 = { + 0x1002, pci_device_19e7_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_19e7_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_19e7_1003 = { + 0x1003, pci_device_19e7_1003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_19e7_1003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_19e7_1004 = { + 0x1004, pci_device_19e7_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_19e7_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_19e7_1005 = { + 0x1005, pci_device_19e7_1005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_19e7_1005, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1a03_2000 = { + 0x2000, pci_device_1a03_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1a03_2000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1a08_0000 = { + 0x0000, pci_device_1a08_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1a08_0000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1c1c_0001 = { + 0x0001, pci_device_1c1c_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1c1c_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1d44_a400 = { + 0xa400, pci_device_1d44_a400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1d44_a400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1de1_0391 = { + 0x0391, pci_device_1de1_0391, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1de1_0391, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1de1_2020 = { + 0x2020, pci_device_1de1_2020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1de1_2020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1de1_690c = { + 0x690c, pci_device_1de1_690c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1de1_690c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1de1_dc29 = { + 0xdc29, pci_device_1de1_dc29, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1de1_dc29, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1fc0_0300 = { + 0x0300, pci_device_1fc0_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1fc0_0300, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1fc1_000d = { + 0x000d, pci_device_1fc1_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1fc1_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_1fc1_0010 = { + 0x0010, pci_device_1fc1_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1fc1_0010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_1fce_0001 = { + 0x0001, pci_device_1fce_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_1fce_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_2348_2010 = { + 0x2010, pci_device_2348_2010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_2348_2010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_3388_0013 = { + 0x0013, pci_device_3388_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_0014 = { + 0x0014, pci_device_3388_0014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_0020 = { + 0x0020, pci_device_3388_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_0021 = { + 0x0021, pci_device_3388_0021, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0021, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_0022 = { + 0x0022, pci_device_3388_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_0026 = { + 0x0026, pci_device_3388_0026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_0026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_101a = { + 0x101a, pci_device_3388_101a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_101a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_101b = { + 0x101b, pci_device_3388_101b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_101b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_8011 = { + 0x8011, pci_device_3388_8011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_8011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_8012 = { + 0x8012, pci_device_3388_8012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_8012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3388_8013 = { + 0x8013, pci_device_3388_8013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3388_8013, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_3842_c370 = { + 0xc370, pci_device_3842_c370, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3842_c370, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_3d3d_0001 = { + 0x0001, pci_device_3d3d_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0002 = { + 0x0002, pci_device_3d3d_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0003 = { + 0x0003, pci_device_3d3d_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0003, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0004 = { + 0x0004, pci_device_3d3d_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0005 = { + 0x0005, pci_device_3d3d_0005, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0005, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0006 = { + 0x0006, pci_device_3d3d_0006, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0006, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0007 = { + 0x0007, pci_device_3d3d_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0008 = { + 0x0008, pci_device_3d3d_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0009 = { + 0x0009, pci_device_3d3d_0009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_000a = { + 0x000a, pci_device_3d3d_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_000c = { + 0x000c, pci_device_3d3d_000c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_000c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_000d = { + 0x000d, pci_device_3d3d_000d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_000d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0011 = { + 0x0011, pci_device_3d3d_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0012 = { + 0x0012, pci_device_3d3d_0012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0013 = { + 0x0013, pci_device_3d3d_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0020 = { + 0x0020, pci_device_3d3d_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0022 = { + 0x0022, pci_device_3d3d_0022, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0022, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0024 = { + 0x0024, pci_device_3d3d_0024, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0024, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_0100 = { + 0x0100, pci_device_3d3d_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_07a1 = { + 0x07a1, pci_device_3d3d_07a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_07a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_07a2 = { + 0x07a2, pci_device_3d3d_07a2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_07a2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_07a3 = { + 0x07a3, pci_device_3d3d_07a3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_07a3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_1004 = { + 0x1004, pci_device_3d3d_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_3d04 = { + 0x3d04, pci_device_3d3d_3d04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_3d04, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_3d3d_ffff = { + 0xffff, pci_device_3d3d_ffff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_3d3d_ffff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_0300 = { + 0x0300, pci_device_4005_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_0308 = { + 0x0308, pci_device_4005_0308, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_0308, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_0309 = { + 0x0309, pci_device_4005_0309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_0309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_1064 = { + 0x1064, pci_device_4005_1064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_1064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2064 = { + 0x2064, pci_device_4005_2064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2128 = { + 0x2128, pci_device_4005_2128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2128, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2301 = { + 0x2301, pci_device_4005_2301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2301, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2302 = { + 0x2302, pci_device_4005_2302, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2302, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2303 = { + 0x2303, pci_device_4005_2303, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2303, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2364 = { + 0x2364, pci_device_4005_2364, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2364, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2464 = { + 0x2464, pci_device_4005_2464, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2464, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_2501 = { + 0x2501, pci_device_4005_2501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_2501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_4000 = { + 0x4000, pci_device_4005_4000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_4000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4005_4710 = { + 0x4710, pci_device_4005_4710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4005_4710, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4033_1360 = { + 0x1360, pci_device_4033_1360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4033_1360, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4144_0044 = { + 0x0044, pci_device_4144_0044, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4144_0044, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_416c_0100 = { + 0x0100, pci_device_416c_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_416c_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_416c_0200 = { + 0x0200, pci_device_416c_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_416c_0200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4444_0016 = { + 0x0016, pci_device_4444_0016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4444_0016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4444_0803 = { + 0x0803, pci_device_4444_0803, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4444_0803, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4916_1960 = { + 0x1960, pci_device_4916_1960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4916_1960, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_494f_10e8 = { + 0x10e8, pci_device_494f_10e8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_494f_10e8, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4a14_5000 = { + 0x5000, pci_device_4a14_5000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4a14_5000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4c53_0000 = { + 0x0000, pci_device_4c53_0000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4c53_0000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4c53_0001 = { + 0x0001, pci_device_4c53_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4c53_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4d51_0200 = { + 0x0200, pci_device_4d51_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4d51_0200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_4ddc_0100 = { + 0x0100, pci_device_4ddc_0100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0801 = { + 0x0801, pci_device_4ddc_0801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0802 = { + 0x0802, pci_device_4ddc_0802, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0802, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0811 = { + 0x0811, pci_device_4ddc_0811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0812 = { + 0x0812, pci_device_4ddc_0812, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0812, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0881 = { + 0x0881, pci_device_4ddc_0881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0882 = { + 0x0882, pci_device_4ddc_0882, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0882, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0891 = { + 0x0891, pci_device_4ddc_0891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0892 = { + 0x0892, pci_device_4ddc_0892, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0892, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0901 = { + 0x0901, pci_device_4ddc_0901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0901, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0902 = { + 0x0902, pci_device_4ddc_0902, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0902, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0903 = { + 0x0903, pci_device_4ddc_0903, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0903, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0904 = { + 0x0904, pci_device_4ddc_0904, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0904, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0b01 = { + 0x0b01, pci_device_4ddc_0b01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0b01, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0b02 = { + 0x0b02, pci_device_4ddc_0b02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0b02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0b03 = { + 0x0b03, pci_device_4ddc_0b03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0b03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_4ddc_0b04 = { + 0x0b04, pci_device_4ddc_0b04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_4ddc_0b04, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5046_1001 = { + 0x1001, pci_device_5046_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5046_1001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5053_2010 = { + 0x2010, pci_device_5053_2010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5053_2010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5145_3031 = { + 0x3031, pci_device_5145_3031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5145_3031, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5168_0300 = { + 0x0300, pci_device_5168_0300, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5168_0300, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5168_0301 = { + 0x0301, pci_device_5168_0301, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5168_0301, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5301_0001 = { + 0x0001, pci_device_5301_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5301_0001, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_5333_0551 = { + 0x0551, pci_device_5333_0551, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_0551, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_5631 = { + 0x5631, pci_device_5333_5631, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_5631, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8800 = { + 0x8800, pci_device_5333_8800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8801 = { + 0x8801, pci_device_5333_8801, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8801, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8810 = { + 0x8810, pci_device_5333_8810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8811 = { + 0x8811, pci_device_5333_8811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8812 = { + 0x8812, pci_device_5333_8812, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8812, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8813 = { + 0x8813, pci_device_5333_8813, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8813, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8814 = { + 0x8814, pci_device_5333_8814, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8814, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8815 = { + 0x8815, pci_device_5333_8815, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8815, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_883d = { + 0x883d, pci_device_5333_883d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_883d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8870 = { + 0x8870, pci_device_5333_8870, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8870, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8880 = { + 0x8880, pci_device_5333_8880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8881 = { + 0x8881, pci_device_5333_8881, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8881, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8882 = { + 0x8882, pci_device_5333_8882, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8882, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8883 = { + 0x8883, pci_device_5333_8883, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8883, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88b0 = { + 0x88b0, pci_device_5333_88b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88b1 = { + 0x88b1, pci_device_5333_88b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88b2 = { + 0x88b2, pci_device_5333_88b2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88b2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88b3 = { + 0x88b3, pci_device_5333_88b3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88b3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88c0 = { + 0x88c0, pci_device_5333_88c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88c1 = { + 0x88c1, pci_device_5333_88c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88c2 = { + 0x88c2, pci_device_5333_88c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88c2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88c3 = { + 0x88c3, pci_device_5333_88c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88d0 = { + 0x88d0, pci_device_5333_88d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88d1 = { + 0x88d1, pci_device_5333_88d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88d2 = { + 0x88d2, pci_device_5333_88d2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88d2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88d3 = { + 0x88d3, pci_device_5333_88d3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88d3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88f0 = { + 0x88f0, pci_device_5333_88f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88f1 = { + 0x88f1, pci_device_5333_88f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88f2 = { + 0x88f2, pci_device_5333_88f2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88f2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_88f3 = { + 0x88f3, pci_device_5333_88f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_88f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8900 = { + 0x8900, pci_device_5333_8900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8901 = { + 0x8901, pci_device_5333_8901, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8901, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8902 = { + 0x8902, pci_device_5333_8902, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8902, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8903 = { + 0x8903, pci_device_5333_8903, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8903, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8904 = { + 0x8904, pci_device_5333_8904, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8904, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8905 = { + 0x8905, pci_device_5333_8905, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8905, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8906 = { + 0x8906, pci_device_5333_8906, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8906, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8907 = { + 0x8907, pci_device_5333_8907, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8907, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8908 = { + 0x8908, pci_device_5333_8908, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8908, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8909 = { + 0x8909, pci_device_5333_8909, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8909, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890a = { + 0x890a, pci_device_5333_890a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890b = { + 0x890b, pci_device_5333_890b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890c = { + 0x890c, pci_device_5333_890c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890d = { + 0x890d, pci_device_5333_890d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890e = { + 0x890e, pci_device_5333_890e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_890f = { + 0x890f, pci_device_5333_890f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_890f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a01 = { + 0x8a01, pci_device_5333_8a01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a01, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a10 = { + 0x8a10, pci_device_5333_8a10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a13 = { + 0x8a13, pci_device_5333_8a13, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a13, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a20 = { + 0x8a20, pci_device_5333_8a20, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a20, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a21 = { + 0x8a21, pci_device_5333_8a21, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a21, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a22 = { + 0x8a22, pci_device_5333_8a22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a22, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a23 = { + 0x8a23, pci_device_5333_8a23, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a23, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a25 = { + 0x8a25, pci_device_5333_8a25, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a25, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8a26 = { + 0x8a26, pci_device_5333_8a26, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8a26, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c00 = { + 0x8c00, pci_device_5333_8c00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c01 = { + 0x8c01, pci_device_5333_8c01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c01, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c02 = { + 0x8c02, pci_device_5333_8c02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c03 = { + 0x8c03, pci_device_5333_8c03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c10 = { + 0x8c10, pci_device_5333_8c10, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c10, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c11 = { + 0x8c11, pci_device_5333_8c11, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c11, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c12 = { + 0x8c12, pci_device_5333_8c12, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c12, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c13 = { + 0x8c13, pci_device_5333_8c13, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c13, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c22 = { + 0x8c22, pci_device_5333_8c22, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c22, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c24 = { + 0x8c24, pci_device_5333_8c24, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c24, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c26 = { + 0x8c26, pci_device_5333_8c26, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c26, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2a = { + 0x8c2a, pci_device_5333_8c2a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2b = { + 0x8c2b, pci_device_5333_8c2b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2c = { + 0x8c2c, pci_device_5333_8c2c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2d = { + 0x8c2d, pci_device_5333_8c2d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2e = { + 0x8c2e, pci_device_5333_8c2e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8c2f = { + 0x8c2f, pci_device_5333_8c2f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8c2f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8d01 = { + 0x8d01, pci_device_5333_8d01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8d01, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8d02 = { + 0x8d02, pci_device_5333_8d02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8d02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8d03 = { + 0x8d03, pci_device_5333_8d03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8d03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_8d04 = { + 0x8d04, pci_device_5333_8d04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_8d04, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_9102 = { + 0x9102, pci_device_5333_9102, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_9102, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_5333_ca00 = { + 0xca00, pci_device_5333_ca00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5333_ca00, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_544c_0350 = { + 0x0350, pci_device_544c_0350, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_544c_0350, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5455_4458 = { + 0x4458, pci_device_5455_4458, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5455_4458, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5544_0001 = { + 0x0001, pci_device_5544_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5544_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5555_0003 = { + 0x0003, pci_device_5555_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5555_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_5654_3132 = { + 0x3132, pci_device_5654_3132, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_5654_3132, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_6374_6773 = { + 0x6773, pci_device_6374_6773, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_6374_6773, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_6666_0001 = { + 0x0001, pci_device_6666_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_6666_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_6666_0002 = { + 0x0002, pci_device_6666_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_6666_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_6666_0004 = { + 0x0004, pci_device_6666_0004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_6666_0004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_6666_0101 = { + 0x0101, pci_device_6666_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_6666_0101, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_7063_2000 = { + 0x2000, pci_device_7063_2000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_7063_2000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_7063_3000 = { + 0x3000, pci_device_7063_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_7063_3000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_7063_5500 = { + 0x5500, pci_device_7063_5500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_7063_5500, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_8008_0010 = { + 0x0010, pci_device_8008_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8008_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8008_0011 = { + 0x0011, pci_device_8008_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8008_0011, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_8086_0007 = { + 0x0007, pci_device_8086_0007, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0007, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0008 = { + 0x0008, pci_device_8086_0008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0039 = { + 0x0039, pci_device_8086_0039, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0039, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0122 = { + 0x0122, pci_device_8086_0122, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0122, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0309 = { + 0x0309, pci_device_8086_0309, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0309, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_030d = { + 0x030d, pci_device_8086_030d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_030d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0326 = { + 0x0326, pci_device_8086_0326, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0326, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0327 = { + 0x0327, pci_device_8086_0327, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0327, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0329 = { + 0x0329, pci_device_8086_0329, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0329, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_032a = { + 0x032a, pci_device_8086_032a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_032a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_032c = { + 0x032c, pci_device_8086_032c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_032c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0330 = { + 0x0330, pci_device_8086_0330, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0330, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0331 = { + 0x0331, pci_device_8086_0331, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0331, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0332 = { + 0x0332, pci_device_8086_0332, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0332, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0333 = { + 0x0333, pci_device_8086_0333, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0333, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0334 = { + 0x0334, pci_device_8086_0334, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0334, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0335 = { + 0x0335, pci_device_8086_0335, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0335, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0336 = { + 0x0336, pci_device_8086_0336, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0336, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0340 = { + 0x0340, pci_device_8086_0340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0341 = { + 0x0341, pci_device_8086_0341, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0341, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0370 = { + 0x0370, pci_device_8086_0370, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0370, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0371 = { + 0x0371, pci_device_8086_0371, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0371, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0372 = { + 0x0372, pci_device_8086_0372, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0372, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0373 = { + 0x0373, pci_device_8086_0373, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0373, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0374 = { + 0x0374, pci_device_8086_0374, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0374, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0482 = { + 0x0482, pci_device_8086_0482, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0482, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0483 = { + 0x0483, pci_device_8086_0483, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0483, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0484 = { + 0x0484, pci_device_8086_0484, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0484, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0486 = { + 0x0486, pci_device_8086_0486, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0486, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_04a3 = { + 0x04a3, pci_device_8086_04a3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_04a3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_04d0 = { + 0x04d0, pci_device_8086_04d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_04d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0500 = { + 0x0500, pci_device_8086_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0501 = { + 0x0501, pci_device_8086_0501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0502 = { + 0x0502, pci_device_8086_0502, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0502, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0503 = { + 0x0503, pci_device_8086_0503, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0503, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0510 = { + 0x0510, pci_device_8086_0510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0511 = { + 0x0511, pci_device_8086_0511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0512 = { + 0x0512, pci_device_8086_0512, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0512, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0513 = { + 0x0513, pci_device_8086_0513, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0513, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0514 = { + 0x0514, pci_device_8086_0514, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0514, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0515 = { + 0x0515, pci_device_8086_0515, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0515, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0516 = { + 0x0516, pci_device_8086_0516, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0516, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0530 = { + 0x0530, pci_device_8086_0530, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0530, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0531 = { + 0x0531, pci_device_8086_0531, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0531, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0532 = { + 0x0532, pci_device_8086_0532, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0532, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0533 = { + 0x0533, pci_device_8086_0533, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0533, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0534 = { + 0x0534, pci_device_8086_0534, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0534, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0535 = { + 0x0535, pci_device_8086_0535, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0535, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0536 = { + 0x0536, pci_device_8086_0536, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0536, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0537 = { + 0x0537, pci_device_8086_0537, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0537, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0600 = { + 0x0600, pci_device_8086_0600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_061f = { + 0x061f, pci_device_8086_061f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_061f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0960 = { + 0x0960, pci_device_8086_0960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0960, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0962 = { + 0x0962, pci_device_8086_0962, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0962, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_0964 = { + 0x0964, pci_device_8086_0964, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_0964, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1000 = { + 0x1000, pci_device_8086_1000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1001 = { + 0x1001, pci_device_8086_1001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1002 = { + 0x1002, pci_device_8086_1002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1004 = { + 0x1004, pci_device_8086_1004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1008 = { + 0x1008, pci_device_8086_1008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1008, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1009 = { + 0x1009, pci_device_8086_1009, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1009, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_100a = { + 0x100a, pci_device_8086_100a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_100a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_100c = { + 0x100c, pci_device_8086_100c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_100c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_100d = { + 0x100d, pci_device_8086_100d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_100d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_100e = { + 0x100e, pci_device_8086_100e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_100e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_100f = { + 0x100f, pci_device_8086_100f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_100f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1010 = { + 0x1010, pci_device_8086_1010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1011 = { + 0x1011, pci_device_8086_1011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1012 = { + 0x1012, pci_device_8086_1012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1013 = { + 0x1013, pci_device_8086_1013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1014 = { + 0x1014, pci_device_8086_1014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1015 = { + 0x1015, pci_device_8086_1015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1016 = { + 0x1016, pci_device_8086_1016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1017 = { + 0x1017, pci_device_8086_1017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1018 = { + 0x1018, pci_device_8086_1018, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1018, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1019 = { + 0x1019, pci_device_8086_1019, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1019, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_101a = { + 0x101a, pci_device_8086_101a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_101a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_101d = { + 0x101d, pci_device_8086_101d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_101d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_101e = { + 0x101e, pci_device_8086_101e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_101e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1026 = { + 0x1026, pci_device_8086_1026, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1026, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1027 = { + 0x1027, pci_device_8086_1027, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1027, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1028 = { + 0x1028, pci_device_8086_1028, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1028, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1029 = { + 0x1029, pci_device_8086_1029, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1029, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1030 = { + 0x1030, pci_device_8086_1030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1031 = { + 0x1031, pci_device_8086_1031, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1031, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1032 = { + 0x1032, pci_device_8086_1032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1033 = { + 0x1033, pci_device_8086_1033, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1033, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1034 = { + 0x1034, pci_device_8086_1034, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1034, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1035 = { + 0x1035, pci_device_8086_1035, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1035, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1036 = { + 0x1036, pci_device_8086_1036, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1036, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1037 = { + 0x1037, pci_device_8086_1037, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1037, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1038 = { + 0x1038, pci_device_8086_1038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1039 = { + 0x1039, pci_device_8086_1039, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1039, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103a = { + 0x103a, pci_device_8086_103a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103b = { + 0x103b, pci_device_8086_103b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103c = { + 0x103c, pci_device_8086_103c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103d = { + 0x103d, pci_device_8086_103d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_103e = { + 0x103e, pci_device_8086_103e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_103e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1040 = { + 0x1040, pci_device_8086_1040, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1040, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1043 = { + 0x1043, pci_device_8086_1043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1048 = { + 0x1048, pci_device_8086_1048, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1048, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1049 = { + 0x1049, pci_device_8086_1049, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1049, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_104a = { + 0x104a, pci_device_8086_104a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_104a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_104b = { + 0x104b, pci_device_8086_104b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_104b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_104c = { + 0x104c, pci_device_8086_104c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_104c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_104d = { + 0x104d, pci_device_8086_104d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_104d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1050 = { + 0x1050, pci_device_8086_1050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1051 = { + 0x1051, pci_device_8086_1051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1052 = { + 0x1052, pci_device_8086_1052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1053 = { + 0x1053, pci_device_8086_1053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1059 = { + 0x1059, pci_device_8086_1059, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1059, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_105b = { + 0x105b, pci_device_8086_105b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_105b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_105e = { + 0x105e, pci_device_8086_105e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_105e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_105f = { + 0x105f, pci_device_8086_105f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_105f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1060 = { + 0x1060, pci_device_8086_1060, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1060, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1064 = { + 0x1064, pci_device_8086_1064, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1064, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1065 = { + 0x1065, pci_device_8086_1065, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1065, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1066 = { + 0x1066, pci_device_8086_1066, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1066, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1067 = { + 0x1067, pci_device_8086_1067, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1067, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1068 = { + 0x1068, pci_device_8086_1068, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1068, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1069 = { + 0x1069, pci_device_8086_1069, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1069, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_106a = { + 0x106a, pci_device_8086_106a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_106a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_106b = { + 0x106b, pci_device_8086_106b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_106b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1075 = { + 0x1075, pci_device_8086_1075, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1075, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1076 = { + 0x1076, pci_device_8086_1076, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1076, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1077 = { + 0x1077, pci_device_8086_1077, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1077, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1078 = { + 0x1078, pci_device_8086_1078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1079 = { + 0x1079, pci_device_8086_1079, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1079, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107a = { + 0x107a, pci_device_8086_107a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107b = { + 0x107b, pci_device_8086_107b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107c = { + 0x107c, pci_device_8086_107c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107d = { + 0x107d, pci_device_8086_107d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107e = { + 0x107e, pci_device_8086_107e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_107f = { + 0x107f, pci_device_8086_107f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_107f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1080 = { + 0x1080, pci_device_8086_1080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1081 = { + 0x1081, pci_device_8086_1081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1082 = { + 0x1082, pci_device_8086_1082, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1082, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1083 = { + 0x1083, pci_device_8086_1083, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1083, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1084 = { + 0x1084, pci_device_8086_1084, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1084, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1085 = { + 0x1085, pci_device_8086_1085, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1085, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1086 = { + 0x1086, pci_device_8086_1086, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1086, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1087 = { + 0x1087, pci_device_8086_1087, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1087, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1089 = { + 0x1089, pci_device_8086_1089, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1089, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_108a = { + 0x108a, pci_device_8086_108a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_108a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_108b = { + 0x108b, pci_device_8086_108b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_108b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_108c = { + 0x108c, pci_device_8086_108c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_108c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_108e = { + 0x108e, pci_device_8086_108e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_108e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_108f = { + 0x108f, pci_device_8086_108f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_108f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1092 = { + 0x1092, pci_device_8086_1092, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1092, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1096 = { + 0x1096, pci_device_8086_1096, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1096, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1097 = { + 0x1097, pci_device_8086_1097, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1097, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1098 = { + 0x1098, pci_device_8086_1098, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1098, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1099 = { + 0x1099, pci_device_8086_1099, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1099, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_109a = { + 0x109a, pci_device_8086_109a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_109a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_109b = { + 0x109b, pci_device_8086_109b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_109b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_10a0 = { + 0x10a0, pci_device_8086_10a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_10a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_10a1 = { + 0x10a1, pci_device_8086_10a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_10a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_10b0 = { + 0x10b0, pci_device_8086_10b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_10b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_10b2 = { + 0x10b2, pci_device_8086_10b2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_10b2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_10b3 = { + 0x10b3, pci_device_8086_10b3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_10b3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_10b4 = { + 0x10b4, pci_device_8086_10b4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_10b4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_10b5 = { + 0x10b5, pci_device_8086_10b5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_10b5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_10b9 = { + 0x10b9, pci_device_8086_10b9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_10b9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_10ba = { + 0x10ba, pci_device_8086_10ba, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_10ba, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_10bb = { + 0x10bb, pci_device_8086_10bb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_10bb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1107 = { + 0x1107, pci_device_8086_1107, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1107, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1130 = { + 0x1130, pci_device_8086_1130, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1130, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1131 = { + 0x1131, pci_device_8086_1131, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1131, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1132 = { + 0x1132, pci_device_8086_1132, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1132, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1161 = { + 0x1161, pci_device_8086_1161, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1161, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1162 = { + 0x1162, pci_device_8086_1162, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1162, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1200 = { + 0x1200, pci_device_8086_1200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1209 = { + 0x1209, pci_device_8086_1209, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1209, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1221 = { + 0x1221, pci_device_8086_1221, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1221, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1222 = { + 0x1222, pci_device_8086_1222, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1222, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1223 = { + 0x1223, pci_device_8086_1223, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1223, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1225 = { + 0x1225, pci_device_8086_1225, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1225, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1226 = { + 0x1226, pci_device_8086_1226, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1226, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1227 = { + 0x1227, pci_device_8086_1227, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1227, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1228 = { + 0x1228, pci_device_8086_1228, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1228, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1229 = { + 0x1229, pci_device_8086_1229, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1229, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_122d = { + 0x122d, pci_device_8086_122d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_122d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_122e = { + 0x122e, pci_device_8086_122e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_122e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1230 = { + 0x1230, pci_device_8086_1230, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1230, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1231 = { + 0x1231, pci_device_8086_1231, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1231, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1234 = { + 0x1234, pci_device_8086_1234, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1234, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1235 = { + 0x1235, pci_device_8086_1235, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1235, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1237 = { + 0x1237, pci_device_8086_1237, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1237, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1239 = { + 0x1239, pci_device_8086_1239, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1239, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_123b = { + 0x123b, pci_device_8086_123b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_123b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_123c = { + 0x123c, pci_device_8086_123c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_123c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_123d = { + 0x123d, pci_device_8086_123d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_123d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_123e = { + 0x123e, pci_device_8086_123e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_123e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_123f = { + 0x123f, pci_device_8086_123f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_123f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1240 = { + 0x1240, pci_device_8086_1240, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1240, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_124b = { + 0x124b, pci_device_8086_124b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_124b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1250 = { + 0x1250, pci_device_8086_1250, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1250, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1360 = { + 0x1360, pci_device_8086_1360, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1360, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1361 = { + 0x1361, pci_device_8086_1361, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1361, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1460 = { + 0x1460, pci_device_8086_1460, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1460, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1461 = { + 0x1461, pci_device_8086_1461, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1461, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1462 = { + 0x1462, pci_device_8086_1462, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1462, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1960 = { + 0x1960, pci_device_8086_1960, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1960, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1962 = { + 0x1962, pci_device_8086_1962, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1962, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a21 = { + 0x1a21, pci_device_8086_1a21, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a21, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a23 = { + 0x1a23, pci_device_8086_1a23, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a23, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a24 = { + 0x1a24, pci_device_8086_1a24, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a24, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a30 = { + 0x1a30, pci_device_8086_1a30, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a30, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a31 = { + 0x1a31, pci_device_8086_1a31, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a31, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a38 = { + 0x1a38, pci_device_8086_1a38, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a38, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_1a48 = { + 0x1a48, pci_device_8086_1a48, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_1a48, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2410 = { + 0x2410, pci_device_8086_2410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2411 = { + 0x2411, pci_device_8086_2411, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2411, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2412 = { + 0x2412, pci_device_8086_2412, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2412, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2413 = { + 0x2413, pci_device_8086_2413, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2413, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2415 = { + 0x2415, pci_device_8086_2415, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2415, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2416 = { + 0x2416, pci_device_8086_2416, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2416, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2418 = { + 0x2418, pci_device_8086_2418, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2418, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2420 = { + 0x2420, pci_device_8086_2420, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2420, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2421 = { + 0x2421, pci_device_8086_2421, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2421, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2422 = { + 0x2422, pci_device_8086_2422, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2422, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2423 = { + 0x2423, pci_device_8086_2423, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2423, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2425 = { + 0x2425, pci_device_8086_2425, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2425, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2426 = { + 0x2426, pci_device_8086_2426, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2426, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2428 = { + 0x2428, pci_device_8086_2428, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2428, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2440 = { + 0x2440, pci_device_8086_2440, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2440, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2442 = { + 0x2442, pci_device_8086_2442, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2442, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2443 = { + 0x2443, pci_device_8086_2443, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2443, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2444 = { + 0x2444, pci_device_8086_2444, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2444, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2445 = { + 0x2445, pci_device_8086_2445, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2445, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2446 = { + 0x2446, pci_device_8086_2446, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2446, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2448 = { + 0x2448, pci_device_8086_2448, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2448, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2449 = { + 0x2449, pci_device_8086_2449, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2449, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_244a = { + 0x244a, pci_device_8086_244a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_244a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_244b = { + 0x244b, pci_device_8086_244b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_244b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_244c = { + 0x244c, pci_device_8086_244c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_244c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_244e = { + 0x244e, pci_device_8086_244e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_244e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2450 = { + 0x2450, pci_device_8086_2450, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2450, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2452 = { + 0x2452, pci_device_8086_2452, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2452, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2453 = { + 0x2453, pci_device_8086_2453, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2453, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2459 = { + 0x2459, pci_device_8086_2459, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2459, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_245b = { + 0x245b, pci_device_8086_245b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_245b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_245d = { + 0x245d, pci_device_8086_245d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_245d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_245e = { + 0x245e, pci_device_8086_245e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_245e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2480 = { + 0x2480, pci_device_8086_2480, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2480, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2482 = { + 0x2482, pci_device_8086_2482, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2482, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2483 = { + 0x2483, pci_device_8086_2483, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2483, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2484 = { + 0x2484, pci_device_8086_2484, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2484, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2485 = { + 0x2485, pci_device_8086_2485, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2485, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2486 = { + 0x2486, pci_device_8086_2486, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2486, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2487 = { + 0x2487, pci_device_8086_2487, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2487, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_248a = { + 0x248a, pci_device_8086_248a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_248a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_248b = { + 0x248b, pci_device_8086_248b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_248b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_248c = { + 0x248c, pci_device_8086_248c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_248c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c0 = { + 0x24c0, pci_device_8086_24c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c1 = { + 0x24c1, pci_device_8086_24c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c2 = { + 0x24c2, pci_device_8086_24c2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c3 = { + 0x24c3, pci_device_8086_24c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c4 = { + 0x24c4, pci_device_8086_24c4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c5 = { + 0x24c5, pci_device_8086_24c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c6 = { + 0x24c6, pci_device_8086_24c6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24c7 = { + 0x24c7, pci_device_8086_24c7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24c7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24ca = { + 0x24ca, pci_device_8086_24ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24cb = { + 0x24cb, pci_device_8086_24cb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24cb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24cc = { + 0x24cc, pci_device_8086_24cc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24cc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24cd = { + 0x24cd, pci_device_8086_24cd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24cd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d0 = { + 0x24d0, pci_device_8086_24d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d1 = { + 0x24d1, pci_device_8086_24d1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d2 = { + 0x24d2, pci_device_8086_24d2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d3 = { + 0x24d3, pci_device_8086_24d3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d4 = { + 0x24d4, pci_device_8086_24d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d5 = { + 0x24d5, pci_device_8086_24d5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d6 = { + 0x24d6, pci_device_8086_24d6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24d7 = { + 0x24d7, pci_device_8086_24d7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24d7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24db = { + 0x24db, pci_device_8086_24db, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24db, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24dc = { + 0x24dc, pci_device_8086_24dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24dc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24dd = { + 0x24dd, pci_device_8086_24dd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24dd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24de = { + 0x24de, pci_device_8086_24de, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24de, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_24df = { + 0x24df, pci_device_8086_24df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_24df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2500 = { + 0x2500, pci_device_8086_2500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2501 = { + 0x2501, pci_device_8086_2501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_250b = { + 0x250b, pci_device_8086_250b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_250b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_250f = { + 0x250f, pci_device_8086_250f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_250f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2520 = { + 0x2520, pci_device_8086_2520, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2520, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2521 = { + 0x2521, pci_device_8086_2521, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2521, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2530 = { + 0x2530, pci_device_8086_2530, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2530, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2531 = { + 0x2531, pci_device_8086_2531, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2531, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2532 = { + 0x2532, pci_device_8086_2532, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2532, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2533 = { + 0x2533, pci_device_8086_2533, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2533, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2534 = { + 0x2534, pci_device_8086_2534, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2534, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2540 = { + 0x2540, pci_device_8086_2540, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2540, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2541 = { + 0x2541, pci_device_8086_2541, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2541, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2543 = { + 0x2543, pci_device_8086_2543, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2543, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2544 = { + 0x2544, pci_device_8086_2544, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2544, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2545 = { + 0x2545, pci_device_8086_2545, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2545, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2546 = { + 0x2546, pci_device_8086_2546, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2546, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2547 = { + 0x2547, pci_device_8086_2547, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2547, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2548 = { + 0x2548, pci_device_8086_2548, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2548, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_254c = { + 0x254c, pci_device_8086_254c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_254c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2550 = { + 0x2550, pci_device_8086_2550, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2550, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2551 = { + 0x2551, pci_device_8086_2551, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2551, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2552 = { + 0x2552, pci_device_8086_2552, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2552, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2553 = { + 0x2553, pci_device_8086_2553, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2553, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2554 = { + 0x2554, pci_device_8086_2554, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2554, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_255d = { + 0x255d, pci_device_8086_255d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_255d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2560 = { + 0x2560, pci_device_8086_2560, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2560, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2561 = { + 0x2561, pci_device_8086_2561, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2561, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2562 = { + 0x2562, pci_device_8086_2562, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2562, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2570 = { + 0x2570, pci_device_8086_2570, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2570, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2571 = { + 0x2571, pci_device_8086_2571, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2571, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2572 = { + 0x2572, pci_device_8086_2572, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2572, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2573 = { + 0x2573, pci_device_8086_2573, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2573, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2576 = { + 0x2576, pci_device_8086_2576, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2576, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2578 = { + 0x2578, pci_device_8086_2578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2579 = { + 0x2579, pci_device_8086_2579, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2579, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_257b = { + 0x257b, pci_device_8086_257b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_257b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_257e = { + 0x257e, pci_device_8086_257e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_257e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2580 = { + 0x2580, pci_device_8086_2580, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2580, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2581 = { + 0x2581, pci_device_8086_2581, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2581, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2582 = { + 0x2582, pci_device_8086_2582, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2582, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2584 = { + 0x2584, pci_device_8086_2584, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2584, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2585 = { + 0x2585, pci_device_8086_2585, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2585, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2588 = { + 0x2588, pci_device_8086_2588, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2588, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2589 = { + 0x2589, pci_device_8086_2589, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2589, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_258a = { + 0x258a, pci_device_8086_258a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_258a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2590 = { + 0x2590, pci_device_8086_2590, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2590, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2591 = { + 0x2591, pci_device_8086_2591, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2591, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2592 = { + 0x2592, pci_device_8086_2592, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2592, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a1 = { + 0x25a1, pci_device_8086_25a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a2 = { + 0x25a2, pci_device_8086_25a2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a3 = { + 0x25a3, pci_device_8086_25a3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a4 = { + 0x25a4, pci_device_8086_25a4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a6 = { + 0x25a6, pci_device_8086_25a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a7 = { + 0x25a7, pci_device_8086_25a7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25a9 = { + 0x25a9, pci_device_8086_25a9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25a9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25aa = { + 0x25aa, pci_device_8086_25aa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25aa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25ab = { + 0x25ab, pci_device_8086_25ab, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25ab, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25ac = { + 0x25ac, pci_device_8086_25ac, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25ac, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25ad = { + 0x25ad, pci_device_8086_25ad, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25ad, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25ae = { + 0x25ae, pci_device_8086_25ae, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25ae, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25b0 = { + 0x25b0, pci_device_8086_25b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25c0 = { + 0x25c0, pci_device_8086_25c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25d0 = { + 0x25d0, pci_device_8086_25d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25d4 = { + 0x25d4, pci_device_8086_25d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25d8 = { + 0x25d8, pci_device_8086_25d8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25d8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e2 = { + 0x25e2, pci_device_8086_25e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e3 = { + 0x25e3, pci_device_8086_25e3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e4 = { + 0x25e4, pci_device_8086_25e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e5 = { + 0x25e5, pci_device_8086_25e5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e6 = { + 0x25e6, pci_device_8086_25e6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25e7 = { + 0x25e7, pci_device_8086_25e7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25e7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f0 = { + 0x25f0, pci_device_8086_25f0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f1 = { + 0x25f1, pci_device_8086_25f1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f3 = { + 0x25f3, pci_device_8086_25f3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f5 = { + 0x25f5, pci_device_8086_25f5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f6 = { + 0x25f6, pci_device_8086_25f6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f7 = { + 0x25f7, pci_device_8086_25f7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f8 = { + 0x25f8, pci_device_8086_25f8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25f9 = { + 0x25f9, pci_device_8086_25f9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25f9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_25fa = { + 0x25fa, pci_device_8086_25fa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_25fa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2600 = { + 0x2600, pci_device_8086_2600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2601 = { + 0x2601, pci_device_8086_2601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2602 = { + 0x2602, pci_device_8086_2602, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2602, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2603 = { + 0x2603, pci_device_8086_2603, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2603, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2604 = { + 0x2604, pci_device_8086_2604, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2604, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2605 = { + 0x2605, pci_device_8086_2605, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2605, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2606 = { + 0x2606, pci_device_8086_2606, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2606, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2607 = { + 0x2607, pci_device_8086_2607, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2607, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2608 = { + 0x2608, pci_device_8086_2608, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2608, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2609 = { + 0x2609, pci_device_8086_2609, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2609, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_260a = { + 0x260a, pci_device_8086_260a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_260a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_260c = { + 0x260c, pci_device_8086_260c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_260c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2610 = { + 0x2610, pci_device_8086_2610, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2610, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2611 = { + 0x2611, pci_device_8086_2611, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2611, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2612 = { + 0x2612, pci_device_8086_2612, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2612, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2613 = { + 0x2613, pci_device_8086_2613, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2613, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2614 = { + 0x2614, pci_device_8086_2614, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2614, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2615 = { + 0x2615, pci_device_8086_2615, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2615, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2617 = { + 0x2617, pci_device_8086_2617, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2617, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2618 = { + 0x2618, pci_device_8086_2618, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2618, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2619 = { + 0x2619, pci_device_8086_2619, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2619, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_261a = { + 0x261a, pci_device_8086_261a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_261a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_261b = { + 0x261b, pci_device_8086_261b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_261b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_261c = { + 0x261c, pci_device_8086_261c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_261c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_261d = { + 0x261d, pci_device_8086_261d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_261d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_261e = { + 0x261e, pci_device_8086_261e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_261e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2620 = { + 0x2620, pci_device_8086_2620, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2620, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2621 = { + 0x2621, pci_device_8086_2621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2622 = { + 0x2622, pci_device_8086_2622, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2622, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2623 = { + 0x2623, pci_device_8086_2623, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2623, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2624 = { + 0x2624, pci_device_8086_2624, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2624, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2625 = { + 0x2625, pci_device_8086_2625, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2625, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2626 = { + 0x2626, pci_device_8086_2626, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2626, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2627 = { + 0x2627, pci_device_8086_2627, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2627, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2640 = { + 0x2640, pci_device_8086_2640, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2640, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2641 = { + 0x2641, pci_device_8086_2641, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2641, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2642 = { + 0x2642, pci_device_8086_2642, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2642, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2651 = { + 0x2651, pci_device_8086_2651, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2651, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2652 = { + 0x2652, pci_device_8086_2652, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2652, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2653 = { + 0x2653, pci_device_8086_2653, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2653, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2658 = { + 0x2658, pci_device_8086_2658, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2658, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2659 = { + 0x2659, pci_device_8086_2659, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2659, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_265a = { + 0x265a, pci_device_8086_265a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_265a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_265b = { + 0x265b, pci_device_8086_265b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_265b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_265c = { + 0x265c, pci_device_8086_265c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_265c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2660 = { + 0x2660, pci_device_8086_2660, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2660, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2662 = { + 0x2662, pci_device_8086_2662, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2662, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2664 = { + 0x2664, pci_device_8086_2664, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2664, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2666 = { + 0x2666, pci_device_8086_2666, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2666, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2668 = { + 0x2668, pci_device_8086_2668, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2668, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_266a = { + 0x266a, pci_device_8086_266a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_266a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_266c = { + 0x266c, pci_device_8086_266c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_266c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_266d = { + 0x266d, pci_device_8086_266d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_266d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_266e = { + 0x266e, pci_device_8086_266e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_266e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_266f = { + 0x266f, pci_device_8086_266f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_266f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2670 = { + 0x2670, pci_device_8086_2670, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2670, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2680 = { + 0x2680, pci_device_8086_2680, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2680, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2681 = { + 0x2681, pci_device_8086_2681, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2681, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2682 = { + 0x2682, pci_device_8086_2682, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2682, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2683 = { + 0x2683, pci_device_8086_2683, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2683, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2688 = { + 0x2688, pci_device_8086_2688, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2688, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2689 = { + 0x2689, pci_device_8086_2689, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2689, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_268a = { + 0x268a, pci_device_8086_268a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_268a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_268b = { + 0x268b, pci_device_8086_268b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_268b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_268c = { + 0x268c, pci_device_8086_268c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_268c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2690 = { + 0x2690, pci_device_8086_2690, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2690, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2692 = { + 0x2692, pci_device_8086_2692, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2692, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2694 = { + 0x2694, pci_device_8086_2694, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2694, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2696 = { + 0x2696, pci_device_8086_2696, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2696, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2698 = { + 0x2698, pci_device_8086_2698, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2698, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2699 = { + 0x2699, pci_device_8086_2699, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2699, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_269a = { + 0x269a, pci_device_8086_269a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_269a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_269b = { + 0x269b, pci_device_8086_269b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_269b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_269e = { + 0x269e, pci_device_8086_269e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_269e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2770 = { + 0x2770, pci_device_8086_2770, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2770, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2771 = { + 0x2771, pci_device_8086_2771, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2771, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2772 = { + 0x2772, pci_device_8086_2772, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2772, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2774 = { + 0x2774, pci_device_8086_2774, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2774, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2775 = { + 0x2775, pci_device_8086_2775, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2775, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2776 = { + 0x2776, pci_device_8086_2776, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2776, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2778 = { + 0x2778, pci_device_8086_2778, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2778, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2779 = { + 0x2779, pci_device_8086_2779, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2779, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_277a = { + 0x277a, pci_device_8086_277a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_277a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_277c = { + 0x277c, pci_device_8086_277c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_277c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_277d = { + 0x277d, pci_device_8086_277d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_277d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2782 = { + 0x2782, pci_device_8086_2782, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2782, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2792 = { + 0x2792, pci_device_8086_2792, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2792, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27a0 = { + 0x27a0, pci_device_8086_27a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27a1 = { + 0x27a1, pci_device_8086_27a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27a2 = { + 0x27a2, pci_device_8086_27a2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27a2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27a6 = { + 0x27a6, pci_device_8086_27a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27b0 = { + 0x27b0, pci_device_8086_27b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27b8 = { + 0x27b8, pci_device_8086_27b8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27b8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27b9 = { + 0x27b9, pci_device_8086_27b9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27b9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27bd = { + 0x27bd, pci_device_8086_27bd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27bd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c0 = { + 0x27c0, pci_device_8086_27c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c1 = { + 0x27c1, pci_device_8086_27c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c3 = { + 0x27c3, pci_device_8086_27c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c4 = { + 0x27c4, pci_device_8086_27c4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c5 = { + 0x27c5, pci_device_8086_27c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c6 = { + 0x27c6, pci_device_8086_27c6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c8 = { + 0x27c8, pci_device_8086_27c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27c9 = { + 0x27c9, pci_device_8086_27c9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27c9, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27ca = { + 0x27ca, pci_device_8086_27ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27cb = { + 0x27cb, pci_device_8086_27cb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27cb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27cc = { + 0x27cc, pci_device_8086_27cc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27cc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27d0 = { + 0x27d0, pci_device_8086_27d0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27d0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27d2 = { + 0x27d2, pci_device_8086_27d2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27d2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27d4 = { + 0x27d4, pci_device_8086_27d4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27d4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27d6 = { + 0x27d6, pci_device_8086_27d6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27d6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27d8 = { + 0x27d8, pci_device_8086_27d8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27d8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27da = { + 0x27da, pci_device_8086_27da, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27da, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27dc = { + 0x27dc, pci_device_8086_27dc, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27dc, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27dd = { + 0x27dd, pci_device_8086_27dd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27dd, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27de = { + 0x27de, pci_device_8086_27de, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27de, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27df = { + 0x27df, pci_device_8086_27df, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27df, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27e0 = { + 0x27e0, pci_device_8086_27e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_27e2 = { + 0x27e2, pci_device_8086_27e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_27e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2810 = { + 0x2810, pci_device_8086_2810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2811 = { + 0x2811, pci_device_8086_2811, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2811, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2812 = { + 0x2812, pci_device_8086_2812, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2812, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2814 = { + 0x2814, pci_device_8086_2814, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2814, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2815 = { + 0x2815, pci_device_8086_2815, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2815, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2820 = { + 0x2820, pci_device_8086_2820, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2820, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2821 = { + 0x2821, pci_device_8086_2821, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2821, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2822 = { + 0x2822, pci_device_8086_2822, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2822, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2824 = { + 0x2824, pci_device_8086_2824, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2824, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2825 = { + 0x2825, pci_device_8086_2825, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2825, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2828 = { + 0x2828, pci_device_8086_2828, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2828, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2829 = { + 0x2829, pci_device_8086_2829, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2829, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_282a = { + 0x282a, pci_device_8086_282a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_282a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2830 = { + 0x2830, pci_device_8086_2830, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2830, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2831 = { + 0x2831, pci_device_8086_2831, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2831, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2832 = { + 0x2832, pci_device_8086_2832, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2832, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2834 = { + 0x2834, pci_device_8086_2834, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2834, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2835 = { + 0x2835, pci_device_8086_2835, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2835, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2836 = { + 0x2836, pci_device_8086_2836, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2836, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_283a = { + 0x283a, pci_device_8086_283a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_283a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_283e = { + 0x283e, pci_device_8086_283e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_283e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_283f = { + 0x283f, pci_device_8086_283f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_283f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2841 = { + 0x2841, pci_device_8086_2841, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2841, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2843 = { + 0x2843, pci_device_8086_2843, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2843, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2845 = { + 0x2845, pci_device_8086_2845, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2845, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2847 = { + 0x2847, pci_device_8086_2847, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2847, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2849 = { + 0x2849, pci_device_8086_2849, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2849, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_284b = { + 0x284b, pci_device_8086_284b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_284b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_284f = { + 0x284f, pci_device_8086_284f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_284f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2850 = { + 0x2850, pci_device_8086_2850, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2850, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2970 = { + 0x2970, pci_device_8086_2970, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2970, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2971 = { + 0x2971, pci_device_8086_2971, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2971, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2972 = { + 0x2972, pci_device_8086_2972, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2972, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2973 = { + 0x2973, pci_device_8086_2973, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2973, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2974 = { + 0x2974, pci_device_8086_2974, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2974, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2975 = { + 0x2975, pci_device_8086_2975, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2975, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2976 = { + 0x2976, pci_device_8086_2976, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2976, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2977 = { + 0x2977, pci_device_8086_2977, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2977, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2980 = { + 0x2980, pci_device_8086_2980, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2980, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2981 = { + 0x2981, pci_device_8086_2981, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2981, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2982 = { + 0x2982, pci_device_8086_2982, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2982, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2990 = { + 0x2990, pci_device_8086_2990, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2990, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2991 = { + 0x2991, pci_device_8086_2991, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2991, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2992 = { + 0x2992, pci_device_8086_2992, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2992, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2993 = { + 0x2993, pci_device_8086_2993, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2993, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2994 = { + 0x2994, pci_device_8086_2994, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2994, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2995 = { + 0x2995, pci_device_8086_2995, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2995, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2996 = { + 0x2996, pci_device_8086_2996, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2996, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2997 = { + 0x2997, pci_device_8086_2997, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2997, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_29a0 = { + 0x29a0, pci_device_8086_29a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_29a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_29a1 = { + 0x29a1, pci_device_8086_29a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_29a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_29a2 = { + 0x29a2, pci_device_8086_29a2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_29a2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_29a3 = { + 0x29a3, pci_device_8086_29a3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_29a3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_29a4 = { + 0x29a4, pci_device_8086_29a4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_29a4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_29a5 = { + 0x29a5, pci_device_8086_29a5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_29a5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_29a6 = { + 0x29a6, pci_device_8086_29a6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_29a6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_29a7 = { + 0x29a7, pci_device_8086_29a7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_29a7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2a00 = { + 0x2a00, pci_device_8086_2a00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2a00, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2a01 = { + 0x2a01, pci_device_8086_2a01, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2a01, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2a02 = { + 0x2a02, pci_device_8086_2a02, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2a02, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2a03 = { + 0x2a03, pci_device_8086_2a03, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2a03, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2a04 = { + 0x2a04, pci_device_8086_2a04, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2a04, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2a05 = { + 0x2a05, pci_device_8086_2a05, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2a05, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2a06 = { + 0x2a06, pci_device_8086_2a06, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2a06, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_2a07 = { + 0x2a07, pci_device_8086_2a07, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_2a07, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3092 = { + 0x3092, pci_device_8086_3092, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3092, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3200 = { + 0x3200, pci_device_8086_3200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3340 = { + 0x3340, pci_device_8086_3340, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3340, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3341 = { + 0x3341, pci_device_8086_3341, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3341, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3500 = { + 0x3500, pci_device_8086_3500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3501 = { + 0x3501, pci_device_8086_3501, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3501, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3504 = { + 0x3504, pci_device_8086_3504, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3504, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3505 = { + 0x3505, pci_device_8086_3505, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3505, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_350c = { + 0x350c, pci_device_8086_350c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_350c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_350d = { + 0x350d, pci_device_8086_350d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_350d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3510 = { + 0x3510, pci_device_8086_3510, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3510, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3511 = { + 0x3511, pci_device_8086_3511, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3511, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3514 = { + 0x3514, pci_device_8086_3514, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3514, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3515 = { + 0x3515, pci_device_8086_3515, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3515, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3518 = { + 0x3518, pci_device_8086_3518, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3518, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3519 = { + 0x3519, pci_device_8086_3519, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3519, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3575 = { + 0x3575, pci_device_8086_3575, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3575, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3576 = { + 0x3576, pci_device_8086_3576, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3576, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3577 = { + 0x3577, pci_device_8086_3577, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3577, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3578 = { + 0x3578, pci_device_8086_3578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3580 = { + 0x3580, pci_device_8086_3580, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3580, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3581 = { + 0x3581, pci_device_8086_3581, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3581, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3582 = { + 0x3582, pci_device_8086_3582, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3582, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3584 = { + 0x3584, pci_device_8086_3584, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3584, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3585 = { + 0x3585, pci_device_8086_3585, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3585, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3590 = { + 0x3590, pci_device_8086_3590, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3590, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3591 = { + 0x3591, pci_device_8086_3591, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3591, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3592 = { + 0x3592, pci_device_8086_3592, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3592, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3593 = { + 0x3593, pci_device_8086_3593, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3593, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3594 = { + 0x3594, pci_device_8086_3594, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3594, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3595 = { + 0x3595, pci_device_8086_3595, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3595, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3596 = { + 0x3596, pci_device_8086_3596, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3596, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3597 = { + 0x3597, pci_device_8086_3597, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3597, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3598 = { + 0x3598, pci_device_8086_3598, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3598, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_3599 = { + 0x3599, pci_device_8086_3599, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_3599, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_359a = { + 0x359a, pci_device_8086_359a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_359a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_359b = { + 0x359b, pci_device_8086_359b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_359b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_359e = { + 0x359e, pci_device_8086_359e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_359e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_35b0 = { + 0x35b0, pci_device_8086_35b0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_35b0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_35b1 = { + 0x35b1, pci_device_8086_35b1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_35b1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_35b5 = { + 0x35b5, pci_device_8086_35b5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_35b5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_35b6 = { + 0x35b6, pci_device_8086_35b6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_35b6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_35b7 = { + 0x35b7, pci_device_8086_35b7, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_35b7, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_35c8 = { + 0x35c8, pci_device_8086_35c8, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_35c8, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_4220 = { + 0x4220, pci_device_8086_4220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_4220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_4222 = { + 0x4222, pci_device_8086_4222, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_4222, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_4223 = { + 0x4223, pci_device_8086_4223, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_4223, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_4224 = { + 0x4224, pci_device_8086_4224, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_4224, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_4227 = { + 0x4227, pci_device_8086_4227, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_4227, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_5001 = { + 0x5001, pci_device_8086_5001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_5001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_5200 = { + 0x5200, pci_device_8086_5200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_5200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_5201 = { + 0x5201, pci_device_8086_5201, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_5201, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_530d = { + 0x530d, pci_device_8086_530d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_530d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7000 = { + 0x7000, pci_device_8086_7000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7010 = { + 0x7010, pci_device_8086_7010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7020 = { + 0x7020, pci_device_8086_7020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7030 = { + 0x7030, pci_device_8086_7030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7050 = { + 0x7050, pci_device_8086_7050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7051 = { + 0x7051, pci_device_8086_7051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7100 = { + 0x7100, pci_device_8086_7100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7110 = { + 0x7110, pci_device_8086_7110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7111 = { + 0x7111, pci_device_8086_7111, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7111, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7112 = { + 0x7112, pci_device_8086_7112, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7112, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7113 = { + 0x7113, pci_device_8086_7113, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7113, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7120 = { + 0x7120, pci_device_8086_7120, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7120, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7121 = { + 0x7121, pci_device_8086_7121, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7121, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7122 = { + 0x7122, pci_device_8086_7122, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7122, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7123 = { + 0x7123, pci_device_8086_7123, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7123, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7124 = { + 0x7124, pci_device_8086_7124, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7124, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7125 = { + 0x7125, pci_device_8086_7125, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7125, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7126 = { + 0x7126, pci_device_8086_7126, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7126, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7128 = { + 0x7128, pci_device_8086_7128, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7128, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_712a = { + 0x712a, pci_device_8086_712a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_712a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7180 = { + 0x7180, pci_device_8086_7180, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7180, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7181 = { + 0x7181, pci_device_8086_7181, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7181, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7190 = { + 0x7190, pci_device_8086_7190, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7190, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7191 = { + 0x7191, pci_device_8086_7191, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7191, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7192 = { + 0x7192, pci_device_8086_7192, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7192, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7194 = { + 0x7194, pci_device_8086_7194, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7194, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7195 = { + 0x7195, pci_device_8086_7195, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7195, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7196 = { + 0x7196, pci_device_8086_7196, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7196, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7198 = { + 0x7198, pci_device_8086_7198, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7198, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7199 = { + 0x7199, pci_device_8086_7199, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7199, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_719a = { + 0x719a, pci_device_8086_719a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_719a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_719b = { + 0x719b, pci_device_8086_719b, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_719b, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_71a0 = { + 0x71a0, pci_device_8086_71a0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_71a0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_71a1 = { + 0x71a1, pci_device_8086_71a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_71a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_71a2 = { + 0x71a2, pci_device_8086_71a2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_71a2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7600 = { + 0x7600, pci_device_8086_7600, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7600, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7601 = { + 0x7601, pci_device_8086_7601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7601, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7602 = { + 0x7602, pci_device_8086_7602, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7602, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7603 = { + 0x7603, pci_device_8086_7603, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7603, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_7800 = { + 0x7800, pci_device_8086_7800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_7800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84c4 = { + 0x84c4, pci_device_8086_84c4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84c4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84c5 = { + 0x84c5, pci_device_8086_84c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84ca = { + 0x84ca, pci_device_8086_84ca, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84ca, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84cb = { + 0x84cb, pci_device_8086_84cb, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84cb, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e0 = { + 0x84e0, pci_device_8086_84e0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e1 = { + 0x84e1, pci_device_8086_84e1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e2 = { + 0x84e2, pci_device_8086_84e2, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e2, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e3 = { + 0x84e3, pci_device_8086_84e3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e4 = { + 0x84e4, pci_device_8086_84e4, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e4, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84e6 = { + 0x84e6, pci_device_8086_84e6, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84e6, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_84ea = { + 0x84ea, pci_device_8086_84ea, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_84ea, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_8500 = { + 0x8500, pci_device_8086_8500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_8500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9000 = { + 0x9000, pci_device_8086_9000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9001 = { + 0x9001, pci_device_8086_9001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9002 = { + 0x9002, pci_device_8086_9002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9004 = { + 0x9004, pci_device_8086_9004, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9004, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9621 = { + 0x9621, pci_device_8086_9621, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9621, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9622 = { + 0x9622, pci_device_8086_9622, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9622, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_9641 = { + 0x9641, pci_device_8086_9641, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_9641, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_96a1 = { + 0x96a1, pci_device_8086_96a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_96a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_b152 = { + 0xb152, pci_device_8086_b152, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_b152, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_b154 = { + 0xb154, pci_device_8086_b154, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_b154, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_8086_b555 = { + 0xb555, pci_device_8086_b555, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8086_b555, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_8686_1010 = { + 0x1010, pci_device_8686_1010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8686_1010, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_8800_2008 = { + 0x2008, pci_device_8800_2008, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8800_2008, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_8c4a_1980 = { + 0x1980, pci_device_8c4a_1980, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8c4a_1980, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_8e2e_3000 = { + 0x3000, pci_device_8e2e_3000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_8e2e_3000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_9004_0078 = { + 0x0078, pci_device_9004_0078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_0078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_1078 = { + 0x1078, pci_device_9004_1078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_1078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_1160 = { + 0x1160, pci_device_9004_1160, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_1160, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_2178 = { + 0x2178, pci_device_9004_2178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_2178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_3860 = { + 0x3860, pci_device_9004_3860, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_3860, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_3b78 = { + 0x3b78, pci_device_9004_3b78, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_3b78, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5075 = { + 0x5075, pci_device_9004_5075, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5075, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5078 = { + 0x5078, pci_device_9004_5078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5175 = { + 0x5175, pci_device_9004_5175, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5175, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5178 = { + 0x5178, pci_device_9004_5178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5275 = { + 0x5275, pci_device_9004_5275, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5275, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5278 = { + 0x5278, pci_device_9004_5278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5375 = { + 0x5375, pci_device_9004_5375, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5375, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5378 = { + 0x5378, pci_device_9004_5378, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5378, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5475 = { + 0x5475, pci_device_9004_5475, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5475, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5478 = { + 0x5478, pci_device_9004_5478, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5478, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5575 = { + 0x5575, pci_device_9004_5575, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5575, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5578 = { + 0x5578, pci_device_9004_5578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5647 = { + 0x5647, pci_device_9004_5647, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5647, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5675 = { + 0x5675, pci_device_9004_5675, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5675, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5678 = { + 0x5678, pci_device_9004_5678, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5678, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5775 = { + 0x5775, pci_device_9004_5775, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5775, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5778 = { + 0x5778, pci_device_9004_5778, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5778, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5800 = { + 0x5800, pci_device_9004_5800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5800, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5900 = { + 0x5900, pci_device_9004_5900, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5900, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_5905 = { + 0x5905, pci_device_9004_5905, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_5905, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6038 = { + 0x6038, pci_device_9004_6038, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6038, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6075 = { + 0x6075, pci_device_9004_6075, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6075, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6078 = { + 0x6078, pci_device_9004_6078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6178 = { + 0x6178, pci_device_9004_6178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6278 = { + 0x6278, pci_device_9004_6278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6378 = { + 0x6378, pci_device_9004_6378, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6378, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6478 = { + 0x6478, pci_device_9004_6478, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6478, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6578 = { + 0x6578, pci_device_9004_6578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6678 = { + 0x6678, pci_device_9004_6678, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6678, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6778 = { + 0x6778, pci_device_9004_6778, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6778, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_6915 = { + 0x6915, pci_device_9004_6915, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_6915, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7078 = { + 0x7078, pci_device_9004_7078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7178 = { + 0x7178, pci_device_9004_7178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7278 = { + 0x7278, pci_device_9004_7278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7378 = { + 0x7378, pci_device_9004_7378, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7378, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7478 = { + 0x7478, pci_device_9004_7478, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7478, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7578 = { + 0x7578, pci_device_9004_7578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7678 = { + 0x7678, pci_device_9004_7678, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7678, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7710 = { + 0x7710, pci_device_9004_7710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7710, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7711 = { + 0x7711, pci_device_9004_7711, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7711, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7778 = { + 0x7778, pci_device_9004_7778, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7778, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7810 = { + 0x7810, pci_device_9004_7810, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7810, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7815 = { + 0x7815, pci_device_9004_7815, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7815, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7850 = { + 0x7850, pci_device_9004_7850, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7850, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7855 = { + 0x7855, pci_device_9004_7855, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7855, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7860 = { + 0x7860, pci_device_9004_7860, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7860, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7870 = { + 0x7870, pci_device_9004_7870, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7870, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7871 = { + 0x7871, pci_device_9004_7871, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7871, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7872 = { + 0x7872, pci_device_9004_7872, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7872, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7873 = { + 0x7873, pci_device_9004_7873, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7873, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7874 = { + 0x7874, pci_device_9004_7874, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7874, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7880 = { + 0x7880, pci_device_9004_7880, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7880, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7890 = { + 0x7890, pci_device_9004_7890, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7890, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7891 = { + 0x7891, pci_device_9004_7891, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7891, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7892 = { + 0x7892, pci_device_9004_7892, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7892, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7893 = { + 0x7893, pci_device_9004_7893, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7893, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7894 = { + 0x7894, pci_device_9004_7894, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7894, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7895 = { + 0x7895, pci_device_9004_7895, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7895, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7896 = { + 0x7896, pci_device_9004_7896, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7896, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_7897 = { + 0x7897, pci_device_9004_7897, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_7897, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8078 = { + 0x8078, pci_device_9004_8078, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8078, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8178 = { + 0x8178, pci_device_9004_8178, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8178, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8278 = { + 0x8278, pci_device_9004_8278, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8278, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8378 = { + 0x8378, pci_device_9004_8378, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8378, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8478 = { + 0x8478, pci_device_9004_8478, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8478, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8578 = { + 0x8578, pci_device_9004_8578, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8578, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8678 = { + 0x8678, pci_device_9004_8678, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8678, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8778 = { + 0x8778, pci_device_9004_8778, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8778, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8878 = { + 0x8878, pci_device_9004_8878, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8878, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_8b78 = { + 0x8b78, pci_device_9004_8b78, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_8b78, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9004_ec78 = { + 0xec78, pci_device_9004_ec78, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9004_ec78, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_9005_0010 = { + 0x0010, pci_device_9005_0010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0011 = { + 0x0011, pci_device_9005_0011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0013 = { + 0x0013, pci_device_9005_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_001f = { + 0x001f, pci_device_9005_001f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_001f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0020 = { + 0x0020, pci_device_9005_0020, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0020, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_002f = { + 0x002f, pci_device_9005_002f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_002f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0030 = { + 0x0030, pci_device_9005_0030, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0030, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_003f = { + 0x003f, pci_device_9005_003f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_003f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0050 = { + 0x0050, pci_device_9005_0050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0051 = { + 0x0051, pci_device_9005_0051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0053 = { + 0x0053, pci_device_9005_0053, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0053, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_005f = { + 0x005f, pci_device_9005_005f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_005f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0080 = { + 0x0080, pci_device_9005_0080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0081 = { + 0x0081, pci_device_9005_0081, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0081, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0083 = { + 0x0083, pci_device_9005_0083, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0083, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_008f = { + 0x008f, pci_device_9005_008f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_008f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_00c0 = { + 0x00c0, pci_device_9005_00c0, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_00c0, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_00c1 = { + 0x00c1, pci_device_9005_00c1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_00c1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_00c3 = { + 0x00c3, pci_device_9005_00c3, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_00c3, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_00c5 = { + 0x00c5, pci_device_9005_00c5, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_00c5, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_00cf = { + 0x00cf, pci_device_9005_00cf, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_00cf, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0241 = { + 0x0241, pci_device_9005_0241, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0241, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0250 = { + 0x0250, pci_device_9005_0250, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0250, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0279 = { + 0x0279, pci_device_9005_0279, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0279, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0283 = { + 0x0283, pci_device_9005_0283, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0283, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0284 = { + 0x0284, pci_device_9005_0284, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0284, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0285 = { + 0x0285, pci_device_9005_0285, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0285, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0286 = { + 0x0286, pci_device_9005_0286, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0286, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0410 = { + 0x0410, pci_device_9005_0410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0412 = { + 0x0412, pci_device_9005_0412, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0412, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_041e = { + 0x041e, pci_device_9005_041e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_041e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_041f = { + 0x041f, pci_device_9005_041f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_041f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0430 = { + 0x0430, pci_device_9005_0430, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0430, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0432 = { + 0x0432, pci_device_9005_0432, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0432, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_043e = { + 0x043e, pci_device_9005_043e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_043e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_043f = { + 0x043f, pci_device_9005_043f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_043f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0500 = { + 0x0500, pci_device_9005_0500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0503 = { + 0x0503, pci_device_9005_0503, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0503, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_0910 = { + 0x0910, pci_device_9005_0910, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_0910, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_091e = { + 0x091e, pci_device_9005_091e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_091e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8000 = { + 0x8000, pci_device_9005_8000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8000, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_800f = { + 0x800f, pci_device_9005_800f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_800f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8010 = { + 0x8010, pci_device_9005_8010, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8010, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8011 = { + 0x8011, pci_device_9005_8011, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8011, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8012 = { + 0x8012, pci_device_9005_8012, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8012, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8013 = { + 0x8013, pci_device_9005_8013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8013, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8014 = { + 0x8014, pci_device_9005_8014, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8014, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8015 = { + 0x8015, pci_device_9005_8015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8015, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8016 = { + 0x8016, pci_device_9005_8016, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8016, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8017 = { + 0x8017, pci_device_9005_8017, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8017, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_801c = { + 0x801c, pci_device_9005_801c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_801c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_801d = { + 0x801d, pci_device_9005_801d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_801d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_801e = { + 0x801e, pci_device_9005_801e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_801e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_801f = { + 0x801f, pci_device_9005_801f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_801f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8080 = { + 0x8080, pci_device_9005_8080, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8080, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_808f = { + 0x808f, pci_device_9005_808f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_808f, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8090 = { + 0x8090, pci_device_9005_8090, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8090, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8091 = { + 0x8091, pci_device_9005_8091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8092 = { + 0x8092, pci_device_9005_8092, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8092, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8093 = { + 0x8093, pci_device_9005_8093, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8093, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8094 = { + 0x8094, pci_device_9005_8094, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8094, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8095 = { + 0x8095, pci_device_9005_8095, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8095, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8096 = { + 0x8096, pci_device_9005_8096, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8096, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_8097 = { + 0x8097, pci_device_9005_8097, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_8097, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_809c = { + 0x809c, pci_device_9005_809c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_809c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_809d = { + 0x809d, pci_device_9005_809d, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_809d, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_809e = { + 0x809e, pci_device_9005_809e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_809e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9005_809f = { + 0x809f, pci_device_9005_809f, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9005_809f, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_907f_2015 = { + 0x2015, pci_device_907f_2015, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_907f_2015, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_9412_6565 = { + 0x6565, pci_device_9412_6565, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9412_6565, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_9699_6565 = { + 0x6565, pci_device_9699_6565, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9699_6565, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_9710_7780 = { + 0x7780, pci_device_9710_7780, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9710_7780, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9710_9805 = { + 0x9805, pci_device_9710_9805, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9710_9805, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9710_9815 = { + 0x9815, pci_device_9710_9815, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9710_9815, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9710_9835 = { + 0x9835, pci_device_9710_9835, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9710_9835, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9710_9845 = { + 0x9845, pci_device_9710_9845, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9710_9845, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9710_9855 = { + 0x9855, pci_device_9710_9855, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9710_9855, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_9902_0001 = { + 0x0001, pci_device_9902_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9902_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9902_0002 = { + 0x0002, pci_device_9902_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9902_0002, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_9902_0003 = { + 0x0003, pci_device_9902_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_9902_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_a727_0013 = { + 0x0013, pci_device_a727_0013, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_a727_0013, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_aecb_6250 = { + 0x6250, pci_device_aecb_6250, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_aecb_6250, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_affe_02e1 = { + 0x02e1, pci_device_affe_02e1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_affe_02e1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_affe_dead = { + 0xdead, pci_device_affe_dead, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_affe_dead, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_cafe_0003 = { + 0x0003, pci_device_cafe_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_cafe_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_cddd_0101 = { + 0x0101, pci_device_cddd_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_cddd_0101, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_cddd_0200 = { + 0x0200, pci_device_cddd_0200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_cddd_0200, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_d161_0205 = { + 0x0205, pci_device_d161_0205, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_d161_0205, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_d161_0210 = { + 0x0210, pci_device_d161_0210, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_d161_0210, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_d161_0405 = { + 0x0405, pci_device_d161_0405, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_d161_0405, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_d161_0406 = { + 0x0406, pci_device_d161_0406, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_d161_0406, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_d161_0410 = { + 0x0410, pci_device_d161_0410, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_d161_0410, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_d161_0411 = { + 0x0411, pci_device_d161_0411, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_d161_0411, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_d161_2400 = { + 0x2400, pci_device_d161_2400, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_d161_2400, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_d4d4_0601 = { + 0x0601, pci_device_d4d4_0601, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_d4d4_0601, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_deaf_9050 = { + 0x9050, pci_device_deaf_9050, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_deaf_9050, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_deaf_9051 = { + 0x9051, pci_device_deaf_9051, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_deaf_9051, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_deaf_9052 = { + 0x9052, pci_device_deaf_9052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_deaf_9052, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_e000_e000 = { + 0xe000, pci_device_e000_e000, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_e000_e000, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_e159_0001 = { + 0x0001, pci_device_e159_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_e159_0001, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_e159_0002 = { + 0x0002, pci_device_e159_0002, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_e159_0002, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_ea01_000a = { + 0x000a, pci_device_ea01_000a, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea01_000a, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ea01_0032 = { + 0x0032, pci_device_ea01_0032, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea01_0032, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ea01_003e = { + 0x003e, pci_device_ea01_003e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea01_003e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ea01_0041 = { + 0x0041, pci_device_ea01_0041, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea01_0041, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ea01_0043 = { + 0x0043, pci_device_ea01_0043, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea01_0043, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ea01_0046 = { + 0x0046, pci_device_ea01_0046, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea01_0046, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ea01_0052 = { + 0x0052, pci_device_ea01_0052, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea01_0052, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ea01_0800 = { + 0x0800, pci_device_ea01_0800, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea01_0800, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_ea60_9896 = { + 0x9896, pci_device_ea60_9896, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea60_9896, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ea60_9897 = { + 0x9897, pci_device_ea60_9897, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea60_9897, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_ea60_9898 = { + 0x9898, pci_device_ea60_9898, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ea60_9898, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_eace_3100 = { + 0x3100, pci_device_eace_3100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_3100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_3200 = { + 0x3200, pci_device_eace_3200, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_3200, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_320e = { + 0x320e, pci_device_eace_320e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_320e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_340e = { + 0x340e, pci_device_eace_340e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_340e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_341e = { + 0x341e, pci_device_eace_341e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_341e, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_3500 = { + 0x3500, pci_device_eace_3500, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_3500, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_351c = { + 0x351c, pci_device_eace_351c, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_351c, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_4100 = { + 0x4100, pci_device_eace_4100, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_4100, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_4110 = { + 0x4110, pci_device_eace_4110, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_4110, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_4220 = { + 0x4220, pci_device_eace_4220, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_4220, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_eace_422e = { + 0x422e, pci_device_eace_422e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_eace_422e, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_ec80_ec00 = { + 0xec00, pci_device_ec80_ec00, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_ec80_ec00, +#else + NULL, +#endif + 0 +}; +#endif +static const pciDeviceInfo pci_dev_info_edd8_a091 = { + 0xa091, pci_device_edd8_a091, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_edd8_a091, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_edd8_a099 = { + 0xa099, pci_device_edd8_a099, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_edd8_a099, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_edd8_a0a1 = { + 0xa0a1, pci_device_edd8_a0a1, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_edd8_a0a1, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_edd8_a0a9 = { + 0xa0a9, pci_device_edd8_a0a9, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_edd8_a0a9, +#else + NULL, +#endif + 0 +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_f1d0_c0fe = { + 0xc0fe, pci_device_f1d0_c0fe, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_f1d0_c0fe, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_f1d0_c0ff = { + 0xc0ff, pci_device_f1d0_c0ff, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_f1d0_c0ff, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_f1d0_cafe = { + 0xcafe, pci_device_f1d0_cafe, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_f1d0_cafe, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_f1d0_cfee = { + 0xcfee, pci_device_f1d0_cfee, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_f1d0_cfee, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_f1d0_dcaf = { + 0xdcaf, pci_device_f1d0_dcaf, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_f1d0_dcaf, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_f1d0_dfee = { + 0xdfee, pci_device_f1d0_dfee, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_f1d0_dfee, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_f1d0_efac = { + 0xefac, pci_device_f1d0_efac, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_f1d0_efac, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_f1d0_facd = { + 0xfacd, pci_device_f1d0_facd, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_f1d0_facd, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_fa57_0001 = { + 0x0001, pci_device_fa57_0001, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_fa57_0001, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_feda_a0fa = { + 0xa0fa, pci_device_feda_a0fa, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_feda_a0fa, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_feda_a10e = { + 0xa10e, pci_device_feda_a10e, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_feda_a10e, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_fede_0003 = { + 0x0003, pci_device_fede_0003, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_fede_0003, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_fffd_0101 = { + 0x0101, pci_device_fffd_0101, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_fffd_0101, +#else + NULL, +#endif + 0 +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo pci_dev_info_fffe_0405 = { + 0x0405, pci_device_fffe_0405, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_fffe_0405, +#else + NULL, +#endif + 0 +}; +static const pciDeviceInfo pci_dev_info_fffe_0710 = { + 0x0710, pci_device_fffe_0710, +#ifdef INIT_SUBSYS_INFO + pci_ss_list_fffe_0710, +#else + NULL, +#endif + 0 +}; +#endif +#define pci_dev_list_0000 NULL +#define pci_dev_list_001a NULL +#define pci_dev_list_0033 NULL +#define pci_dev_list_003d NULL +#define pci_dev_list_0059 NULL +#define pci_dev_list_0070 NULL +#define pci_dev_list_0071 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0095[] = { + &pci_dev_info_0095_0680, + NULL +}; +#endif +#define pci_dev_list_00a7 NULL +#define pci_dev_list_00f5 NULL +#define pci_dev_list_0100 NULL +#define pci_dev_list_0123 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_018a[] = { + &pci_dev_info_018a_0106, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_021b[] = { + &pci_dev_info_021b_8139, + NULL +}; +#endif +#define pci_dev_list_0270 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0291[] = { + &pci_dev_info_0291_8212, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_02ac[] = { + &pci_dev_info_02ac_1012, + NULL +}; +#endif +#define pci_dev_list_0315 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0357[] = { + &pci_dev_info_0357_000a, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0432[] = { + &pci_dev_info_0432_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_045e[] = { + &pci_dev_info_045e_006e, + &pci_dev_info_045e_00c2, + NULL +}; +#endif +#define pci_dev_list_0482 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_04cf[] = { + &pci_dev_info_04cf_8818, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_050d[] = { + &pci_dev_info_050d_001a, + &pci_dev_info_050d_0109, + &pci_dev_info_050d_7050, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_05a9[] = { + &pci_dev_info_05a9_8519, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_05e3[] = { + &pci_dev_info_05e3_0701, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_066f[] = { + &pci_dev_info_066f_3410, + &pci_dev_info_066f_3500, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0675[] = { + &pci_dev_info_0675_1700, + &pci_dev_info_0675_1702, + &pci_dev_info_0675_1703, + &pci_dev_info_0675_1704, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_067b[] = { + &pci_dev_info_067b_2303, + &pci_dev_info_067b_3507, + NULL +}; +#endif +#define pci_dev_list_0721 NULL +#define pci_dev_list_07e2 NULL +#define pci_dev_list_0925 NULL +#define pci_dev_list_093a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_09c1[] = { + &pci_dev_info_09c1_0704, + NULL +}; +#endif +#define pci_dev_list_0a89 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0b0b[] = { + &pci_dev_info_0b0b_0105, + &pci_dev_info_0b0b_0205, + &pci_dev_info_0b0b_0305, + &pci_dev_info_0b0b_0405, + &pci_dev_info_0b0b_0505, + &pci_dev_info_0b0b_0506, + &pci_dev_info_0b0b_0605, + &pci_dev_info_0b0b_0705, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0b49[] = { + &pci_dev_info_0b49_064f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_0ccd[] = { + &pci_dev_info_0ccd_0038, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_0e11[] = { + &pci_dev_info_0e11_0001, + &pci_dev_info_0e11_0002, + &pci_dev_info_0e11_0046, + &pci_dev_info_0e11_0049, + &pci_dev_info_0e11_004a, + &pci_dev_info_0e11_005a, + &pci_dev_info_0e11_007c, + &pci_dev_info_0e11_007d, + &pci_dev_info_0e11_0085, + &pci_dev_info_0e11_00b1, + &pci_dev_info_0e11_00bb, + &pci_dev_info_0e11_00ca, + &pci_dev_info_0e11_00cb, + &pci_dev_info_0e11_00cf, + &pci_dev_info_0e11_00d0, + &pci_dev_info_0e11_00d1, + &pci_dev_info_0e11_00e3, + &pci_dev_info_0e11_0508, + &pci_dev_info_0e11_1000, + &pci_dev_info_0e11_2000, + &pci_dev_info_0e11_3032, + &pci_dev_info_0e11_3033, + &pci_dev_info_0e11_3034, + &pci_dev_info_0e11_4000, + &pci_dev_info_0e11_4030, + &pci_dev_info_0e11_4031, + &pci_dev_info_0e11_4032, + &pci_dev_info_0e11_4033, + &pci_dev_info_0e11_4034, + &pci_dev_info_0e11_4040, + &pci_dev_info_0e11_4048, + &pci_dev_info_0e11_4050, + &pci_dev_info_0e11_4051, + &pci_dev_info_0e11_4058, + &pci_dev_info_0e11_4070, + &pci_dev_info_0e11_4080, + &pci_dev_info_0e11_4082, + &pci_dev_info_0e11_4083, + &pci_dev_info_0e11_4091, + &pci_dev_info_0e11_409a, + &pci_dev_info_0e11_409b, + &pci_dev_info_0e11_409c, + &pci_dev_info_0e11_409d, + &pci_dev_info_0e11_6010, + &pci_dev_info_0e11_7020, + &pci_dev_info_0e11_a0ec, + &pci_dev_info_0e11_a0f0, + &pci_dev_info_0e11_a0f3, + &pci_dev_info_0e11_a0f7, + &pci_dev_info_0e11_a0f8, + &pci_dev_info_0e11_a0fc, + &pci_dev_info_0e11_ae10, + &pci_dev_info_0e11_ae29, + &pci_dev_info_0e11_ae2a, + &pci_dev_info_0e11_ae2b, + &pci_dev_info_0e11_ae31, + &pci_dev_info_0e11_ae32, + &pci_dev_info_0e11_ae33, + &pci_dev_info_0e11_ae34, + &pci_dev_info_0e11_ae35, + &pci_dev_info_0e11_ae40, + &pci_dev_info_0e11_ae43, + &pci_dev_info_0e11_ae69, + &pci_dev_info_0e11_ae6c, + &pci_dev_info_0e11_ae6d, + &pci_dev_info_0e11_b011, + &pci_dev_info_0e11_b012, + &pci_dev_info_0e11_b01e, + &pci_dev_info_0e11_b01f, + &pci_dev_info_0e11_b02f, + &pci_dev_info_0e11_b030, + &pci_dev_info_0e11_b04a, + &pci_dev_info_0e11_b060, + &pci_dev_info_0e11_b0c6, + &pci_dev_info_0e11_b0c7, + &pci_dev_info_0e11_b0d7, + &pci_dev_info_0e11_b0dd, + &pci_dev_info_0e11_b0de, + &pci_dev_info_0e11_b0df, + &pci_dev_info_0e11_b0e0, + &pci_dev_info_0e11_b0e1, + &pci_dev_info_0e11_b123, + &pci_dev_info_0e11_b134, + &pci_dev_info_0e11_b13c, + &pci_dev_info_0e11_b144, + &pci_dev_info_0e11_b163, + &pci_dev_info_0e11_b164, + &pci_dev_info_0e11_b178, + &pci_dev_info_0e11_b1a4, + &pci_dev_info_0e11_b200, + &pci_dev_info_0e11_b203, + &pci_dev_info_0e11_b204, + &pci_dev_info_0e11_f130, + &pci_dev_info_0e11_f150, + NULL +}; +#define pci_dev_list_0e21 NULL +#define pci_dev_list_0e55 NULL +#define pci_dev_list_0eac NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1000[] = { + &pci_dev_info_1000_0001, + &pci_dev_info_1000_0002, + &pci_dev_info_1000_0003, + &pci_dev_info_1000_0004, + &pci_dev_info_1000_0005, + &pci_dev_info_1000_0006, + &pci_dev_info_1000_000a, + &pci_dev_info_1000_000b, + &pci_dev_info_1000_000c, + &pci_dev_info_1000_000d, + &pci_dev_info_1000_000f, + &pci_dev_info_1000_0010, + &pci_dev_info_1000_0012, + &pci_dev_info_1000_0013, + &pci_dev_info_1000_0020, + &pci_dev_info_1000_0021, + &pci_dev_info_1000_0030, + &pci_dev_info_1000_0031, + &pci_dev_info_1000_0032, + &pci_dev_info_1000_0033, + &pci_dev_info_1000_0040, + &pci_dev_info_1000_0041, + &pci_dev_info_1000_0050, + &pci_dev_info_1000_0054, + &pci_dev_info_1000_0056, + &pci_dev_info_1000_0058, + &pci_dev_info_1000_005a, + &pci_dev_info_1000_005c, + &pci_dev_info_1000_005e, + &pci_dev_info_1000_0060, + &pci_dev_info_1000_0062, + &pci_dev_info_1000_008f, + &pci_dev_info_1000_0407, + &pci_dev_info_1000_0408, + &pci_dev_info_1000_0409, + &pci_dev_info_1000_0411, + &pci_dev_info_1000_0413, + &pci_dev_info_1000_0621, + &pci_dev_info_1000_0622, + &pci_dev_info_1000_0623, + &pci_dev_info_1000_0624, + &pci_dev_info_1000_0625, + &pci_dev_info_1000_0626, + &pci_dev_info_1000_0627, + &pci_dev_info_1000_0628, + &pci_dev_info_1000_0629, + &pci_dev_info_1000_0640, + &pci_dev_info_1000_0642, + &pci_dev_info_1000_0646, + &pci_dev_info_1000_0701, + &pci_dev_info_1000_0702, + &pci_dev_info_1000_0804, + &pci_dev_info_1000_0805, + &pci_dev_info_1000_0806, + &pci_dev_info_1000_0807, + &pci_dev_info_1000_0901, + &pci_dev_info_1000_1000, + &pci_dev_info_1000_1960, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1001[] = { + &pci_dev_info_1001_0010, + &pci_dev_info_1001_0011, + &pci_dev_info_1001_0012, + &pci_dev_info_1001_0013, + &pci_dev_info_1001_0014, + &pci_dev_info_1001_0015, + &pci_dev_info_1001_0016, + &pci_dev_info_1001_0017, + &pci_dev_info_1001_9100, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_1002[] = { + &pci_dev_info_1002_3150, + &pci_dev_info_1002_3152, + &pci_dev_info_1002_3154, + &pci_dev_info_1002_3e50, + &pci_dev_info_1002_3e54, + &pci_dev_info_1002_3e70, + &pci_dev_info_1002_4136, + &pci_dev_info_1002_4137, + &pci_dev_info_1002_4144, + &pci_dev_info_1002_4145, + &pci_dev_info_1002_4146, + &pci_dev_info_1002_4147, + &pci_dev_info_1002_4148, + &pci_dev_info_1002_4149, + &pci_dev_info_1002_414a, + &pci_dev_info_1002_414b, + &pci_dev_info_1002_4150, + &pci_dev_info_1002_4151, + &pci_dev_info_1002_4152, + &pci_dev_info_1002_4153, + &pci_dev_info_1002_4154, + &pci_dev_info_1002_4155, + &pci_dev_info_1002_4156, + &pci_dev_info_1002_4157, + &pci_dev_info_1002_4158, + &pci_dev_info_1002_4164, + &pci_dev_info_1002_4165, + &pci_dev_info_1002_4166, + &pci_dev_info_1002_4168, + &pci_dev_info_1002_4170, + &pci_dev_info_1002_4171, + &pci_dev_info_1002_4172, + &pci_dev_info_1002_4173, + &pci_dev_info_1002_4237, + &pci_dev_info_1002_4242, + &pci_dev_info_1002_4243, + &pci_dev_info_1002_4336, + &pci_dev_info_1002_4337, + &pci_dev_info_1002_4341, + &pci_dev_info_1002_4345, + &pci_dev_info_1002_4347, + &pci_dev_info_1002_4348, + &pci_dev_info_1002_4349, + &pci_dev_info_1002_434d, + &pci_dev_info_1002_4353, + &pci_dev_info_1002_4354, + &pci_dev_info_1002_4358, + &pci_dev_info_1002_4363, + &pci_dev_info_1002_436e, + &pci_dev_info_1002_4370, + &pci_dev_info_1002_4371, + &pci_dev_info_1002_4372, + &pci_dev_info_1002_4373, + &pci_dev_info_1002_4374, + &pci_dev_info_1002_4375, + &pci_dev_info_1002_4376, + &pci_dev_info_1002_4377, + &pci_dev_info_1002_4378, + &pci_dev_info_1002_4379, + &pci_dev_info_1002_437a, + &pci_dev_info_1002_437b, + &pci_dev_info_1002_4380, + &pci_dev_info_1002_4381, + &pci_dev_info_1002_4382, + &pci_dev_info_1002_4383, + &pci_dev_info_1002_4384, + &pci_dev_info_1002_4385, + &pci_dev_info_1002_4386, + &pci_dev_info_1002_4387, + &pci_dev_info_1002_4388, + &pci_dev_info_1002_4389, + &pci_dev_info_1002_438a, + &pci_dev_info_1002_438b, + &pci_dev_info_1002_438c, + &pci_dev_info_1002_438d, + &pci_dev_info_1002_438e, + &pci_dev_info_1002_4437, + &pci_dev_info_1002_4554, + &pci_dev_info_1002_4654, + &pci_dev_info_1002_4742, + &pci_dev_info_1002_4744, + &pci_dev_info_1002_4747, + &pci_dev_info_1002_4749, + &pci_dev_info_1002_474c, + &pci_dev_info_1002_474d, + &pci_dev_info_1002_474e, + &pci_dev_info_1002_474f, + &pci_dev_info_1002_4750, + &pci_dev_info_1002_4751, + &pci_dev_info_1002_4752, + &pci_dev_info_1002_4753, + &pci_dev_info_1002_4754, + &pci_dev_info_1002_4755, + &pci_dev_info_1002_4756, + &pci_dev_info_1002_4757, + &pci_dev_info_1002_4758, + &pci_dev_info_1002_4759, + &pci_dev_info_1002_475a, + &pci_dev_info_1002_4964, + &pci_dev_info_1002_4965, + &pci_dev_info_1002_4966, + &pci_dev_info_1002_4967, + &pci_dev_info_1002_496e, + &pci_dev_info_1002_4a48, + &pci_dev_info_1002_4a49, + &pci_dev_info_1002_4a4a, + &pci_dev_info_1002_4a4b, + &pci_dev_info_1002_4a4c, + &pci_dev_info_1002_4a4d, + &pci_dev_info_1002_4a4e, + &pci_dev_info_1002_4a50, + &pci_dev_info_1002_4a54, + &pci_dev_info_1002_4a69, + &pci_dev_info_1002_4a6a, + &pci_dev_info_1002_4a6b, + &pci_dev_info_1002_4a70, + &pci_dev_info_1002_4a74, + &pci_dev_info_1002_4b49, + &pci_dev_info_1002_4b4b, + &pci_dev_info_1002_4b4c, + &pci_dev_info_1002_4b69, + &pci_dev_info_1002_4b6b, + &pci_dev_info_1002_4b6c, + &pci_dev_info_1002_4c42, + &pci_dev_info_1002_4c44, + &pci_dev_info_1002_4c45, + &pci_dev_info_1002_4c46, + &pci_dev_info_1002_4c47, + &pci_dev_info_1002_4c49, + &pci_dev_info_1002_4c4d, + &pci_dev_info_1002_4c4e, + &pci_dev_info_1002_4c50, + &pci_dev_info_1002_4c51, + &pci_dev_info_1002_4c52, + &pci_dev_info_1002_4c53, + &pci_dev_info_1002_4c54, + &pci_dev_info_1002_4c57, + &pci_dev_info_1002_4c58, + &pci_dev_info_1002_4c59, + &pci_dev_info_1002_4c5a, + &pci_dev_info_1002_4c64, + &pci_dev_info_1002_4c65, + &pci_dev_info_1002_4c66, + &pci_dev_info_1002_4c67, + &pci_dev_info_1002_4c6e, + &pci_dev_info_1002_4d46, + &pci_dev_info_1002_4d4c, + &pci_dev_info_1002_4e44, + &pci_dev_info_1002_4e45, + &pci_dev_info_1002_4e46, + &pci_dev_info_1002_4e47, + &pci_dev_info_1002_4e48, + &pci_dev_info_1002_4e49, + &pci_dev_info_1002_4e4a, + &pci_dev_info_1002_4e4b, + &pci_dev_info_1002_4e50, + &pci_dev_info_1002_4e51, + &pci_dev_info_1002_4e52, + &pci_dev_info_1002_4e53, + &pci_dev_info_1002_4e54, + &pci_dev_info_1002_4e56, + &pci_dev_info_1002_4e64, + &pci_dev_info_1002_4e65, + &pci_dev_info_1002_4e66, + &pci_dev_info_1002_4e67, + &pci_dev_info_1002_4e68, + &pci_dev_info_1002_4e69, + &pci_dev_info_1002_4e6a, + &pci_dev_info_1002_4e71, + &pci_dev_info_1002_4f72, + &pci_dev_info_1002_4f73, + &pci_dev_info_1002_5041, + &pci_dev_info_1002_5042, + &pci_dev_info_1002_5043, + &pci_dev_info_1002_5044, + &pci_dev_info_1002_5045, + &pci_dev_info_1002_5046, + &pci_dev_info_1002_5047, + &pci_dev_info_1002_5048, + &pci_dev_info_1002_5049, + &pci_dev_info_1002_504a, + &pci_dev_info_1002_504b, + &pci_dev_info_1002_504c, + &pci_dev_info_1002_504d, + &pci_dev_info_1002_504e, + &pci_dev_info_1002_504f, + &pci_dev_info_1002_5050, + &pci_dev_info_1002_5051, + &pci_dev_info_1002_5052, + &pci_dev_info_1002_5053, + &pci_dev_info_1002_5054, + &pci_dev_info_1002_5055, + &pci_dev_info_1002_5056, + &pci_dev_info_1002_5057, + &pci_dev_info_1002_5058, + &pci_dev_info_1002_5144, + &pci_dev_info_1002_5145, + &pci_dev_info_1002_5146, + &pci_dev_info_1002_5147, + &pci_dev_info_1002_5148, + &pci_dev_info_1002_5149, + &pci_dev_info_1002_514a, + &pci_dev_info_1002_514b, + &pci_dev_info_1002_514c, + &pci_dev_info_1002_514d, + &pci_dev_info_1002_514e, + &pci_dev_info_1002_514f, + &pci_dev_info_1002_5154, + &pci_dev_info_1002_5155, + &pci_dev_info_1002_5157, + &pci_dev_info_1002_5158, + &pci_dev_info_1002_5159, + &pci_dev_info_1002_515a, + &pci_dev_info_1002_515e, + &pci_dev_info_1002_515f, + &pci_dev_info_1002_5168, + &pci_dev_info_1002_5169, + &pci_dev_info_1002_516a, + &pci_dev_info_1002_516b, + &pci_dev_info_1002_516c, + &pci_dev_info_1002_5245, + &pci_dev_info_1002_5246, + &pci_dev_info_1002_5247, + &pci_dev_info_1002_524b, + &pci_dev_info_1002_524c, + &pci_dev_info_1002_5345, + &pci_dev_info_1002_5346, + &pci_dev_info_1002_5347, + &pci_dev_info_1002_5348, + &pci_dev_info_1002_534b, + &pci_dev_info_1002_534c, + &pci_dev_info_1002_534d, + &pci_dev_info_1002_534e, + &pci_dev_info_1002_5354, + &pci_dev_info_1002_5446, + &pci_dev_info_1002_544c, + &pci_dev_info_1002_5452, + &pci_dev_info_1002_5453, + &pci_dev_info_1002_5454, + &pci_dev_info_1002_5455, + &pci_dev_info_1002_5460, + &pci_dev_info_1002_5462, + &pci_dev_info_1002_5464, + &pci_dev_info_1002_5548, + &pci_dev_info_1002_5549, + &pci_dev_info_1002_554a, + &pci_dev_info_1002_554b, + &pci_dev_info_1002_554d, + &pci_dev_info_1002_554f, + &pci_dev_info_1002_5550, + &pci_dev_info_1002_5551, + &pci_dev_info_1002_5552, + &pci_dev_info_1002_5554, + &pci_dev_info_1002_5569, + &pci_dev_info_1002_556b, + &pci_dev_info_1002_556d, + &pci_dev_info_1002_556f, + &pci_dev_info_1002_5571, + &pci_dev_info_1002_564a, + &pci_dev_info_1002_564b, + &pci_dev_info_1002_564f, + &pci_dev_info_1002_5652, + &pci_dev_info_1002_5653, + &pci_dev_info_1002_5654, + &pci_dev_info_1002_5655, + &pci_dev_info_1002_5656, + &pci_dev_info_1002_5830, + &pci_dev_info_1002_5831, + &pci_dev_info_1002_5832, + &pci_dev_info_1002_5833, + &pci_dev_info_1002_5834, + &pci_dev_info_1002_5835, + &pci_dev_info_1002_5838, + &pci_dev_info_1002_5940, + &pci_dev_info_1002_5941, + &pci_dev_info_1002_5944, + &pci_dev_info_1002_5950, + &pci_dev_info_1002_5951, + &pci_dev_info_1002_5954, + &pci_dev_info_1002_5955, + &pci_dev_info_1002_5960, + &pci_dev_info_1002_5961, + &pci_dev_info_1002_5962, + &pci_dev_info_1002_5964, + &pci_dev_info_1002_5969, + &pci_dev_info_1002_5974, + &pci_dev_info_1002_5975, + &pci_dev_info_1002_5a33, + &pci_dev_info_1002_5a34, + &pci_dev_info_1002_5a36, + &pci_dev_info_1002_5a38, + &pci_dev_info_1002_5a39, + &pci_dev_info_1002_5a3f, + &pci_dev_info_1002_5a41, + &pci_dev_info_1002_5a42, + &pci_dev_info_1002_5a61, + &pci_dev_info_1002_5a62, + &pci_dev_info_1002_5b60, + &pci_dev_info_1002_5b62, + &pci_dev_info_1002_5b63, + &pci_dev_info_1002_5b64, + &pci_dev_info_1002_5b65, + &pci_dev_info_1002_5b70, + &pci_dev_info_1002_5b72, + &pci_dev_info_1002_5b73, + &pci_dev_info_1002_5b74, + &pci_dev_info_1002_5c61, + &pci_dev_info_1002_5c63, + &pci_dev_info_1002_5d44, + &pci_dev_info_1002_5d48, + &pci_dev_info_1002_5d49, + &pci_dev_info_1002_5d4a, + &pci_dev_info_1002_5d4d, + &pci_dev_info_1002_5d4f, + &pci_dev_info_1002_5d52, + &pci_dev_info_1002_5d57, + &pci_dev_info_1002_5d6d, + &pci_dev_info_1002_5d6f, + &pci_dev_info_1002_5d72, + &pci_dev_info_1002_5d77, + &pci_dev_info_1002_5e48, + &pci_dev_info_1002_5e49, + &pci_dev_info_1002_5e4a, + &pci_dev_info_1002_5e4b, + &pci_dev_info_1002_5e4c, + &pci_dev_info_1002_5e4d, + &pci_dev_info_1002_5e4f, + &pci_dev_info_1002_5e6b, + &pci_dev_info_1002_5e6d, + &pci_dev_info_1002_5f57, + &pci_dev_info_1002_700f, + &pci_dev_info_1002_7010, + &pci_dev_info_1002_7100, + &pci_dev_info_1002_7102, + &pci_dev_info_1002_7103, + &pci_dev_info_1002_7104, + &pci_dev_info_1002_7105, + &pci_dev_info_1002_7106, + &pci_dev_info_1002_7108, + &pci_dev_info_1002_7109, + &pci_dev_info_1002_710a, + &pci_dev_info_1002_710b, + &pci_dev_info_1002_710c, + &pci_dev_info_1002_7120, + &pci_dev_info_1002_7124, + &pci_dev_info_1002_7129, + &pci_dev_info_1002_7140, + &pci_dev_info_1002_7142, + &pci_dev_info_1002_7145, + &pci_dev_info_1002_7146, + &pci_dev_info_1002_7149, + &pci_dev_info_1002_714a, + &pci_dev_info_1002_714b, + &pci_dev_info_1002_714c, + &pci_dev_info_1002_714d, + &pci_dev_info_1002_714e, + &pci_dev_info_1002_7152, + &pci_dev_info_1002_715e, + &pci_dev_info_1002_7162, + &pci_dev_info_1002_7166, + &pci_dev_info_1002_7172, + &pci_dev_info_1002_7180, + &pci_dev_info_1002_7181, + &pci_dev_info_1002_71a0, + &pci_dev_info_1002_71a1, + &pci_dev_info_1002_71c0, + &pci_dev_info_1002_71c2, + &pci_dev_info_1002_71c4, + &pci_dev_info_1002_71c5, + &pci_dev_info_1002_71c6, + &pci_dev_info_1002_71ce, + &pci_dev_info_1002_71d5, + &pci_dev_info_1002_71d6, + &pci_dev_info_1002_71de, + &pci_dev_info_1002_71e0, + &pci_dev_info_1002_71e2, + &pci_dev_info_1002_7240, + &pci_dev_info_1002_7241, + &pci_dev_info_1002_7242, + &pci_dev_info_1002_7243, + &pci_dev_info_1002_7244, + &pci_dev_info_1002_7245, + &pci_dev_info_1002_7246, + &pci_dev_info_1002_7247, + &pci_dev_info_1002_7248, + &pci_dev_info_1002_7249, + &pci_dev_info_1002_724a, + &pci_dev_info_1002_724b, + &pci_dev_info_1002_724c, + &pci_dev_info_1002_724d, + &pci_dev_info_1002_724e, + &pci_dev_info_1002_7269, + &pci_dev_info_1002_726e, + &pci_dev_info_1002_7833, + &pci_dev_info_1002_7834, + &pci_dev_info_1002_7835, + &pci_dev_info_1002_7838, + &pci_dev_info_1002_7c37, + &pci_dev_info_1002_cab0, + &pci_dev_info_1002_cab2, + &pci_dev_info_1002_cab3, + &pci_dev_info_1002_cbb2, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1003[] = { + &pci_dev_info_1003_0201, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1004[] = { + &pci_dev_info_1004_0005, + &pci_dev_info_1004_0006, + &pci_dev_info_1004_0007, + &pci_dev_info_1004_0008, + &pci_dev_info_1004_0009, + &pci_dev_info_1004_000c, + &pci_dev_info_1004_000d, + &pci_dev_info_1004_0101, + &pci_dev_info_1004_0102, + &pci_dev_info_1004_0103, + &pci_dev_info_1004_0104, + &pci_dev_info_1004_0105, + &pci_dev_info_1004_0200, + &pci_dev_info_1004_0280, + &pci_dev_info_1004_0304, + &pci_dev_info_1004_0305, + &pci_dev_info_1004_0306, + &pci_dev_info_1004_0307, + &pci_dev_info_1004_0308, + &pci_dev_info_1004_0702, + &pci_dev_info_1004_0703, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_1005[] = { + &pci_dev_info_1005_2064, + &pci_dev_info_1005_2128, + &pci_dev_info_1005_2301, + &pci_dev_info_1005_2302, + &pci_dev_info_1005_2364, + &pci_dev_info_1005_2464, + &pci_dev_info_1005_2501, + NULL +}; +#define pci_dev_list_1006 NULL +#define pci_dev_list_1007 NULL +#define pci_dev_list_1008 NULL +#define pci_dev_list_100a NULL +static const pciDeviceInfo *pci_dev_list_100b[] = { + &pci_dev_info_100b_0001, + &pci_dev_info_100b_0002, + &pci_dev_info_100b_000e, + &pci_dev_info_100b_000f, + &pci_dev_info_100b_0011, + &pci_dev_info_100b_0012, + &pci_dev_info_100b_0020, + &pci_dev_info_100b_0021, + &pci_dev_info_100b_0022, + &pci_dev_info_100b_0028, + &pci_dev_info_100b_002a, + &pci_dev_info_100b_002b, + &pci_dev_info_100b_002d, + &pci_dev_info_100b_002e, + &pci_dev_info_100b_002f, + &pci_dev_info_100b_0030, + &pci_dev_info_100b_0035, + &pci_dev_info_100b_0500, + &pci_dev_info_100b_0501, + &pci_dev_info_100b_0502, + &pci_dev_info_100b_0503, + &pci_dev_info_100b_0504, + &pci_dev_info_100b_0505, + &pci_dev_info_100b_0510, + &pci_dev_info_100b_0511, + &pci_dev_info_100b_0515, + &pci_dev_info_100b_d001, + NULL +}; +static const pciDeviceInfo *pci_dev_list_100c[] = { + &pci_dev_info_100c_3202, + &pci_dev_info_100c_3205, + &pci_dev_info_100c_3206, + &pci_dev_info_100c_3207, + &pci_dev_info_100c_3208, + &pci_dev_info_100c_4702, + NULL +}; +#define pci_dev_list_100d NULL +static const pciDeviceInfo *pci_dev_list_100e[] = { + &pci_dev_info_100e_9000, + &pci_dev_info_100e_9001, + &pci_dev_info_100e_9002, + &pci_dev_info_100e_9100, + NULL +}; +#define pci_dev_list_1010 NULL +static const pciDeviceInfo *pci_dev_list_1011[] = { + &pci_dev_info_1011_0001, + &pci_dev_info_1011_0002, + &pci_dev_info_1011_0004, + &pci_dev_info_1011_0007, + &pci_dev_info_1011_0008, + &pci_dev_info_1011_0009, + &pci_dev_info_1011_000a, + &pci_dev_info_1011_000d, + &pci_dev_info_1011_000f, + &pci_dev_info_1011_0014, + &pci_dev_info_1011_0016, + &pci_dev_info_1011_0017, + &pci_dev_info_1011_0019, + &pci_dev_info_1011_001a, + &pci_dev_info_1011_0021, + &pci_dev_info_1011_0022, + &pci_dev_info_1011_0023, + &pci_dev_info_1011_0024, + &pci_dev_info_1011_0025, + &pci_dev_info_1011_0026, + &pci_dev_info_1011_0034, + &pci_dev_info_1011_0045, + &pci_dev_info_1011_0046, + &pci_dev_info_1011_1065, + NULL +}; +#define pci_dev_list_1012 NULL +static const pciDeviceInfo *pci_dev_list_1013[] = { + &pci_dev_info_1013_0038, + &pci_dev_info_1013_0040, + &pci_dev_info_1013_004c, + &pci_dev_info_1013_00a0, + &pci_dev_info_1013_00a2, + &pci_dev_info_1013_00a4, + &pci_dev_info_1013_00a8, + &pci_dev_info_1013_00ac, + &pci_dev_info_1013_00b0, + &pci_dev_info_1013_00b8, + &pci_dev_info_1013_00bc, + &pci_dev_info_1013_00d0, + &pci_dev_info_1013_00d2, + &pci_dev_info_1013_00d4, + &pci_dev_info_1013_00d5, + &pci_dev_info_1013_00d6, + &pci_dev_info_1013_00e8, + &pci_dev_info_1013_1100, + &pci_dev_info_1013_1110, + &pci_dev_info_1013_1112, + &pci_dev_info_1013_1113, + &pci_dev_info_1013_1200, + &pci_dev_info_1013_1202, + &pci_dev_info_1013_1204, + &pci_dev_info_1013_4000, + &pci_dev_info_1013_4400, + &pci_dev_info_1013_6001, + &pci_dev_info_1013_6003, + &pci_dev_info_1013_6004, + &pci_dev_info_1013_6005, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1014[] = { + &pci_dev_info_1014_0002, + &pci_dev_info_1014_0005, + &pci_dev_info_1014_0007, + &pci_dev_info_1014_000a, + &pci_dev_info_1014_0017, + &pci_dev_info_1014_0018, + &pci_dev_info_1014_001b, + &pci_dev_info_1014_001c, + &pci_dev_info_1014_001d, + &pci_dev_info_1014_0020, + &pci_dev_info_1014_0022, + &pci_dev_info_1014_002d, + &pci_dev_info_1014_002e, + &pci_dev_info_1014_0031, + &pci_dev_info_1014_0036, + &pci_dev_info_1014_0037, + &pci_dev_info_1014_003a, + &pci_dev_info_1014_003c, + &pci_dev_info_1014_003e, + &pci_dev_info_1014_0045, + &pci_dev_info_1014_0046, + &pci_dev_info_1014_0047, + &pci_dev_info_1014_0048, + &pci_dev_info_1014_0049, + &pci_dev_info_1014_004e, + &pci_dev_info_1014_004f, + &pci_dev_info_1014_0050, + &pci_dev_info_1014_0053, + &pci_dev_info_1014_0054, + &pci_dev_info_1014_0057, + &pci_dev_info_1014_0058, + &pci_dev_info_1014_005c, + &pci_dev_info_1014_005e, + &pci_dev_info_1014_007c, + &pci_dev_info_1014_007d, + &pci_dev_info_1014_008b, + &pci_dev_info_1014_008e, + &pci_dev_info_1014_0090, + &pci_dev_info_1014_0091, + &pci_dev_info_1014_0095, + &pci_dev_info_1014_0096, + &pci_dev_info_1014_009f, + &pci_dev_info_1014_00a5, + &pci_dev_info_1014_00a6, + &pci_dev_info_1014_00b7, + &pci_dev_info_1014_00b8, + &pci_dev_info_1014_00be, + &pci_dev_info_1014_00dc, + &pci_dev_info_1014_00fc, + &pci_dev_info_1014_0104, + &pci_dev_info_1014_0105, + &pci_dev_info_1014_010f, + &pci_dev_info_1014_0142, + &pci_dev_info_1014_0144, + &pci_dev_info_1014_0156, + &pci_dev_info_1014_015e, + &pci_dev_info_1014_0160, + &pci_dev_info_1014_016e, + &pci_dev_info_1014_0170, + &pci_dev_info_1014_017d, + &pci_dev_info_1014_0180, + &pci_dev_info_1014_0188, + &pci_dev_info_1014_01a7, + &pci_dev_info_1014_01bd, + &pci_dev_info_1014_01c1, + &pci_dev_info_1014_01e6, + &pci_dev_info_1014_01ff, + &pci_dev_info_1014_0219, + &pci_dev_info_1014_021b, + &pci_dev_info_1014_021c, + &pci_dev_info_1014_0233, + &pci_dev_info_1014_0266, + &pci_dev_info_1014_0268, + &pci_dev_info_1014_0269, + &pci_dev_info_1014_028c, + &pci_dev_info_1014_02a1, + &pci_dev_info_1014_02bd, + &pci_dev_info_1014_0302, + &pci_dev_info_1014_0308, + &pci_dev_info_1014_0314, + &pci_dev_info_1014_3022, + &pci_dev_info_1014_4022, + &pci_dev_info_1014_ffff, + NULL +}; +#endif +#define pci_dev_list_1015 NULL +#define pci_dev_list_1016 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1017[] = { + &pci_dev_info_1017_5343, + NULL +}; +#endif +#define pci_dev_list_1018 NULL +#define pci_dev_list_1019 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_101a[] = { + &pci_dev_info_101a_0005, + NULL +}; +#endif +#define pci_dev_list_101b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_101c[] = { + &pci_dev_info_101c_0193, + &pci_dev_info_101c_0196, + &pci_dev_info_101c_0197, + &pci_dev_info_101c_0296, + &pci_dev_info_101c_3193, + &pci_dev_info_101c_3197, + &pci_dev_info_101c_3296, + &pci_dev_info_101c_4296, + &pci_dev_info_101c_9710, + &pci_dev_info_101c_9712, + &pci_dev_info_101c_c24a, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_101e[] = { + &pci_dev_info_101e_0009, + &pci_dev_info_101e_1960, + &pci_dev_info_101e_9010, + &pci_dev_info_101e_9030, + &pci_dev_info_101e_9031, + &pci_dev_info_101e_9032, + &pci_dev_info_101e_9033, + &pci_dev_info_101e_9040, + &pci_dev_info_101e_9060, + &pci_dev_info_101e_9063, + NULL +}; +#endif +#define pci_dev_list_101f NULL +#define pci_dev_list_1020 NULL +#define pci_dev_list_1021 NULL +static const pciDeviceInfo *pci_dev_list_1022[] = { + &pci_dev_info_1022_1100, + &pci_dev_info_1022_1101, + &pci_dev_info_1022_1102, + &pci_dev_info_1022_1103, + &pci_dev_info_1022_2000, + &pci_dev_info_1022_2001, + &pci_dev_info_1022_2003, + &pci_dev_info_1022_2020, + &pci_dev_info_1022_2040, + &pci_dev_info_1022_2081, + &pci_dev_info_1022_2082, + &pci_dev_info_1022_208f, + &pci_dev_info_1022_2090, + &pci_dev_info_1022_2091, + &pci_dev_info_1022_2093, + &pci_dev_info_1022_2094, + &pci_dev_info_1022_2095, + &pci_dev_info_1022_2096, + &pci_dev_info_1022_2097, + &pci_dev_info_1022_209a, + &pci_dev_info_1022_3000, + &pci_dev_info_1022_7006, + &pci_dev_info_1022_7007, + &pci_dev_info_1022_700a, + &pci_dev_info_1022_700b, + &pci_dev_info_1022_700c, + &pci_dev_info_1022_700d, + &pci_dev_info_1022_700e, + &pci_dev_info_1022_700f, + &pci_dev_info_1022_7400, + &pci_dev_info_1022_7401, + &pci_dev_info_1022_7403, + &pci_dev_info_1022_7404, + &pci_dev_info_1022_7408, + &pci_dev_info_1022_7409, + &pci_dev_info_1022_740b, + &pci_dev_info_1022_740c, + &pci_dev_info_1022_7410, + &pci_dev_info_1022_7411, + &pci_dev_info_1022_7413, + &pci_dev_info_1022_7414, + &pci_dev_info_1022_7440, + &pci_dev_info_1022_7441, + &pci_dev_info_1022_7443, + &pci_dev_info_1022_7445, + &pci_dev_info_1022_7446, + &pci_dev_info_1022_7448, + &pci_dev_info_1022_7449, + &pci_dev_info_1022_7450, + &pci_dev_info_1022_7451, + &pci_dev_info_1022_7454, + &pci_dev_info_1022_7455, + &pci_dev_info_1022_7458, + &pci_dev_info_1022_7459, + &pci_dev_info_1022_7460, + &pci_dev_info_1022_7461, + &pci_dev_info_1022_7462, + &pci_dev_info_1022_7464, + &pci_dev_info_1022_7468, + &pci_dev_info_1022_7469, + &pci_dev_info_1022_746a, + &pci_dev_info_1022_746b, + &pci_dev_info_1022_746d, + &pci_dev_info_1022_746e, + &pci_dev_info_1022_756b, + NULL +}; +static const pciDeviceInfo *pci_dev_list_1023[] = { + &pci_dev_info_1023_0194, + &pci_dev_info_1023_2000, + &pci_dev_info_1023_2001, + &pci_dev_info_1023_2100, + &pci_dev_info_1023_2200, + &pci_dev_info_1023_8400, + &pci_dev_info_1023_8420, + &pci_dev_info_1023_8500, + &pci_dev_info_1023_8520, + &pci_dev_info_1023_8620, + &pci_dev_info_1023_8820, + &pci_dev_info_1023_9320, + &pci_dev_info_1023_9350, + &pci_dev_info_1023_9360, + &pci_dev_info_1023_9382, + &pci_dev_info_1023_9383, + &pci_dev_info_1023_9385, + &pci_dev_info_1023_9386, + &pci_dev_info_1023_9388, + &pci_dev_info_1023_9397, + &pci_dev_info_1023_939a, + &pci_dev_info_1023_9420, + &pci_dev_info_1023_9430, + &pci_dev_info_1023_9440, + &pci_dev_info_1023_9460, + &pci_dev_info_1023_9470, + &pci_dev_info_1023_9520, + &pci_dev_info_1023_9525, + &pci_dev_info_1023_9540, + &pci_dev_info_1023_9660, + &pci_dev_info_1023_9680, + &pci_dev_info_1023_9682, + &pci_dev_info_1023_9683, + &pci_dev_info_1023_9685, + &pci_dev_info_1023_9750, + &pci_dev_info_1023_9753, + &pci_dev_info_1023_9754, + &pci_dev_info_1023_9759, + &pci_dev_info_1023_9783, + &pci_dev_info_1023_9785, + &pci_dev_info_1023_9850, + &pci_dev_info_1023_9880, + &pci_dev_info_1023_9910, + &pci_dev_info_1023_9930, + NULL +}; +#define pci_dev_list_1024 NULL +static const pciDeviceInfo *pci_dev_list_1025[] = { + &pci_dev_info_1025_0090, + &pci_dev_info_1025_1435, + &pci_dev_info_1025_1445, + &pci_dev_info_1025_1449, + &pci_dev_info_1025_1451, + &pci_dev_info_1025_1461, + &pci_dev_info_1025_1489, + &pci_dev_info_1025_1511, + &pci_dev_info_1025_1512, + &pci_dev_info_1025_1513, + &pci_dev_info_1025_1521, + &pci_dev_info_1025_1523, + &pci_dev_info_1025_1531, + &pci_dev_info_1025_1533, + &pci_dev_info_1025_1535, + &pci_dev_info_1025_1541, + &pci_dev_info_1025_1542, + &pci_dev_info_1025_1543, + &pci_dev_info_1025_1561, + &pci_dev_info_1025_1621, + &pci_dev_info_1025_1631, + &pci_dev_info_1025_1641, + &pci_dev_info_1025_1647, + &pci_dev_info_1025_1671, + &pci_dev_info_1025_1672, + &pci_dev_info_1025_3141, + &pci_dev_info_1025_3143, + &pci_dev_info_1025_3145, + &pci_dev_info_1025_3147, + &pci_dev_info_1025_3149, + &pci_dev_info_1025_3151, + &pci_dev_info_1025_3307, + &pci_dev_info_1025_3309, + &pci_dev_info_1025_3321, + &pci_dev_info_1025_5212, + &pci_dev_info_1025_5215, + &pci_dev_info_1025_5217, + &pci_dev_info_1025_5219, + &pci_dev_info_1025_5225, + &pci_dev_info_1025_5229, + &pci_dev_info_1025_5235, + &pci_dev_info_1025_5237, + &pci_dev_info_1025_5240, + &pci_dev_info_1025_5241, + &pci_dev_info_1025_5242, + &pci_dev_info_1025_5243, + &pci_dev_info_1025_5244, + &pci_dev_info_1025_5247, + &pci_dev_info_1025_5251, + &pci_dev_info_1025_5427, + &pci_dev_info_1025_5451, + &pci_dev_info_1025_5453, + &pci_dev_info_1025_7101, + NULL +}; +static const pciDeviceInfo *pci_dev_list_1028[] = { + &pci_dev_info_1028_0001, + &pci_dev_info_1028_0002, + &pci_dev_info_1028_0003, + &pci_dev_info_1028_0006, + &pci_dev_info_1028_0007, + &pci_dev_info_1028_0008, + &pci_dev_info_1028_0009, + &pci_dev_info_1028_000a, + &pci_dev_info_1028_000c, + &pci_dev_info_1028_000d, + &pci_dev_info_1028_000e, + &pci_dev_info_1028_000f, + &pci_dev_info_1028_0010, + &pci_dev_info_1028_0011, + &pci_dev_info_1028_0012, + &pci_dev_info_1028_0013, + &pci_dev_info_1028_0014, + &pci_dev_info_1028_0015, + NULL +}; +#define pci_dev_list_1029 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_102a[] = { + &pci_dev_info_102a_0000, + &pci_dev_info_102a_0010, + &pci_dev_info_102a_001f, + &pci_dev_info_102a_00c5, + &pci_dev_info_102a_00cf, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_102b[] = { + &pci_dev_info_102b_0010, + &pci_dev_info_102b_0100, + &pci_dev_info_102b_0518, + &pci_dev_info_102b_0519, + &pci_dev_info_102b_051a, + &pci_dev_info_102b_051b, + &pci_dev_info_102b_051e, + &pci_dev_info_102b_051f, + &pci_dev_info_102b_0520, + &pci_dev_info_102b_0521, + &pci_dev_info_102b_0522, + &pci_dev_info_102b_0525, + &pci_dev_info_102b_0527, + &pci_dev_info_102b_0528, + &pci_dev_info_102b_0d10, + &pci_dev_info_102b_1000, + &pci_dev_info_102b_1001, + &pci_dev_info_102b_2007, + &pci_dev_info_102b_2527, + &pci_dev_info_102b_2537, + &pci_dev_info_102b_2538, + &pci_dev_info_102b_4536, + &pci_dev_info_102b_4cdc, + &pci_dev_info_102b_4fc5, + &pci_dev_info_102b_5e10, + &pci_dev_info_102b_6573, + NULL +}; +static const pciDeviceInfo *pci_dev_list_102c[] = { + &pci_dev_info_102c_00b8, + &pci_dev_info_102c_00c0, + &pci_dev_info_102c_00d0, + &pci_dev_info_102c_00d8, + &pci_dev_info_102c_00dc, + &pci_dev_info_102c_00e0, + &pci_dev_info_102c_00e4, + &pci_dev_info_102c_00e5, + &pci_dev_info_102c_00f0, + &pci_dev_info_102c_00f4, + &pci_dev_info_102c_00f5, + &pci_dev_info_102c_0c30, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_102d[] = { + &pci_dev_info_102d_50dc, + NULL +}; +#endif +#define pci_dev_list_102e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_102f[] = { + &pci_dev_info_102f_0009, + &pci_dev_info_102f_000a, + &pci_dev_info_102f_0020, + &pci_dev_info_102f_0030, + &pci_dev_info_102f_0031, + &pci_dev_info_102f_0105, + &pci_dev_info_102f_0106, + &pci_dev_info_102f_0107, + &pci_dev_info_102f_0108, + &pci_dev_info_102f_0180, + &pci_dev_info_102f_0181, + &pci_dev_info_102f_0182, + NULL +}; +#endif +#define pci_dev_list_1030 NULL +static const pciDeviceInfo *pci_dev_list_1031[] = { + &pci_dev_info_1031_5601, + &pci_dev_info_1031_5607, + &pci_dev_info_1031_5631, + &pci_dev_info_1031_6057, + NULL +}; +#define pci_dev_list_1032 NULL +static const pciDeviceInfo *pci_dev_list_1033[] = { + &pci_dev_info_1033_0000, + &pci_dev_info_1033_0001, + &pci_dev_info_1033_0002, + &pci_dev_info_1033_0003, + &pci_dev_info_1033_0004, + &pci_dev_info_1033_0005, + &pci_dev_info_1033_0006, + &pci_dev_info_1033_0007, + &pci_dev_info_1033_0008, + &pci_dev_info_1033_0009, + &pci_dev_info_1033_0016, + &pci_dev_info_1033_001a, + &pci_dev_info_1033_0021, + &pci_dev_info_1033_0029, + &pci_dev_info_1033_002a, + &pci_dev_info_1033_002c, + &pci_dev_info_1033_002d, + &pci_dev_info_1033_0035, + &pci_dev_info_1033_003b, + &pci_dev_info_1033_003e, + &pci_dev_info_1033_0046, + &pci_dev_info_1033_005a, + &pci_dev_info_1033_0063, + &pci_dev_info_1033_0067, + &pci_dev_info_1033_0072, + &pci_dev_info_1033_0074, + &pci_dev_info_1033_009b, + &pci_dev_info_1033_00a5, + &pci_dev_info_1033_00a6, + &pci_dev_info_1033_00cd, + &pci_dev_info_1033_00ce, + &pci_dev_info_1033_00df, + &pci_dev_info_1033_00e0, + &pci_dev_info_1033_00e7, + &pci_dev_info_1033_00f2, + &pci_dev_info_1033_00f3, + &pci_dev_info_1033_010c, + &pci_dev_info_1033_0125, + &pci_dev_info_1033_013a, + NULL +}; +#define pci_dev_list_1034 NULL +#define pci_dev_list_1035 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1036[] = { + &pci_dev_info_1036_0000, + NULL +}; +#endif +#define pci_dev_list_1037 NULL +#define pci_dev_list_1038 NULL +static const pciDeviceInfo *pci_dev_list_1039[] = { + &pci_dev_info_1039_0001, + &pci_dev_info_1039_0002, + &pci_dev_info_1039_0003, + &pci_dev_info_1039_0004, + &pci_dev_info_1039_0006, + &pci_dev_info_1039_0008, + &pci_dev_info_1039_0009, + &pci_dev_info_1039_000a, + &pci_dev_info_1039_0016, + &pci_dev_info_1039_0018, + &pci_dev_info_1039_0180, + &pci_dev_info_1039_0181, + &pci_dev_info_1039_0182, + &pci_dev_info_1039_0186, + &pci_dev_info_1039_0190, + &pci_dev_info_1039_0191, + &pci_dev_info_1039_0200, + &pci_dev_info_1039_0204, + &pci_dev_info_1039_0205, + &pci_dev_info_1039_0300, + &pci_dev_info_1039_0310, + &pci_dev_info_1039_0315, + &pci_dev_info_1039_0325, + &pci_dev_info_1039_0330, + &pci_dev_info_1039_0406, + &pci_dev_info_1039_0496, + &pci_dev_info_1039_0530, + &pci_dev_info_1039_0540, + &pci_dev_info_1039_0550, + &pci_dev_info_1039_0597, + &pci_dev_info_1039_0601, + &pci_dev_info_1039_0620, + &pci_dev_info_1039_0630, + &pci_dev_info_1039_0633, + &pci_dev_info_1039_0635, + &pci_dev_info_1039_0645, + &pci_dev_info_1039_0646, + &pci_dev_info_1039_0648, + &pci_dev_info_1039_0650, + &pci_dev_info_1039_0651, + &pci_dev_info_1039_0655, + &pci_dev_info_1039_0660, + &pci_dev_info_1039_0661, + &pci_dev_info_1039_0662, + &pci_dev_info_1039_0730, + &pci_dev_info_1039_0733, + &pci_dev_info_1039_0735, + &pci_dev_info_1039_0740, + &pci_dev_info_1039_0741, + &pci_dev_info_1039_0745, + &pci_dev_info_1039_0746, + &pci_dev_info_1039_0755, + &pci_dev_info_1039_0760, + &pci_dev_info_1039_0761, + &pci_dev_info_1039_0900, + &pci_dev_info_1039_0961, + &pci_dev_info_1039_0962, + &pci_dev_info_1039_0963, + &pci_dev_info_1039_0964, + &pci_dev_info_1039_0965, + &pci_dev_info_1039_0966, + &pci_dev_info_1039_0968, + &pci_dev_info_1039_1180, + &pci_dev_info_1039_1182, + &pci_dev_info_1039_1183, + &pci_dev_info_1039_1184, + &pci_dev_info_1039_1185, + &pci_dev_info_1039_3602, + &pci_dev_info_1039_5107, + &pci_dev_info_1039_5300, + &pci_dev_info_1039_5315, + &pci_dev_info_1039_5401, + &pci_dev_info_1039_5511, + &pci_dev_info_1039_5513, + &pci_dev_info_1039_5517, + &pci_dev_info_1039_5571, + &pci_dev_info_1039_5581, + &pci_dev_info_1039_5582, + &pci_dev_info_1039_5591, + &pci_dev_info_1039_5596, + &pci_dev_info_1039_5597, + &pci_dev_info_1039_5600, + &pci_dev_info_1039_6204, + &pci_dev_info_1039_6205, + &pci_dev_info_1039_6236, + &pci_dev_info_1039_6300, + &pci_dev_info_1039_6306, + &pci_dev_info_1039_6325, + &pci_dev_info_1039_6326, + &pci_dev_info_1039_6330, + &pci_dev_info_1039_6350, + &pci_dev_info_1039_6351, + &pci_dev_info_1039_7001, + &pci_dev_info_1039_7002, + &pci_dev_info_1039_7007, + &pci_dev_info_1039_7012, + &pci_dev_info_1039_7013, + &pci_dev_info_1039_7016, + &pci_dev_info_1039_7018, + &pci_dev_info_1039_7019, + &pci_dev_info_1039_7502, + NULL +}; +#define pci_dev_list_103a NULL +#define pci_dev_list_103b NULL +static const pciDeviceInfo *pci_dev_list_103c[] = { + &pci_dev_info_103c_002a, + &pci_dev_info_103c_1005, + &pci_dev_info_103c_1008, + &pci_dev_info_103c_1028, + &pci_dev_info_103c_1029, + &pci_dev_info_103c_102a, + &pci_dev_info_103c_1030, + &pci_dev_info_103c_1031, + &pci_dev_info_103c_1040, + &pci_dev_info_103c_1041, + &pci_dev_info_103c_1042, + &pci_dev_info_103c_1048, + &pci_dev_info_103c_1054, + &pci_dev_info_103c_1064, + &pci_dev_info_103c_108b, + &pci_dev_info_103c_10c1, + &pci_dev_info_103c_10ed, + &pci_dev_info_103c_10f0, + &pci_dev_info_103c_10f1, + &pci_dev_info_103c_1200, + &pci_dev_info_103c_1219, + &pci_dev_info_103c_121a, + &pci_dev_info_103c_121b, + &pci_dev_info_103c_121c, + &pci_dev_info_103c_1229, + &pci_dev_info_103c_122a, + &pci_dev_info_103c_122e, + &pci_dev_info_103c_127b, + &pci_dev_info_103c_127c, + &pci_dev_info_103c_1290, + &pci_dev_info_103c_1291, + &pci_dev_info_103c_12b4, + &pci_dev_info_103c_12eb, + &pci_dev_info_103c_12ec, + &pci_dev_info_103c_12ee, + &pci_dev_info_103c_12f8, + &pci_dev_info_103c_12fa, + &pci_dev_info_103c_2910, + &pci_dev_info_103c_2925, + &pci_dev_info_103c_3080, + &pci_dev_info_103c_3085, + &pci_dev_info_103c_3220, + &pci_dev_info_103c_3230, + &pci_dev_info_103c_4030, + &pci_dev_info_103c_4031, + &pci_dev_info_103c_4037, + &pci_dev_info_103c_403b, + &pci_dev_info_103c_60e8, + NULL +}; +#define pci_dev_list_103e NULL +#define pci_dev_list_103f NULL +#define pci_dev_list_1040 NULL +#define pci_dev_list_1041 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1042[] = { + &pci_dev_info_1042_1000, + &pci_dev_info_1042_1001, + &pci_dev_info_1042_3000, + &pci_dev_info_1042_3010, + &pci_dev_info_1042_3020, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1043[] = { + &pci_dev_info_1043_0675, + &pci_dev_info_1043_0c11, + &pci_dev_info_1043_4015, + &pci_dev_info_1043_4021, + &pci_dev_info_1043_4057, + &pci_dev_info_1043_8043, + &pci_dev_info_1043_8047, + &pci_dev_info_1043_807b, + &pci_dev_info_1043_8095, + &pci_dev_info_1043_80ac, + &pci_dev_info_1043_80bb, + &pci_dev_info_1043_80c5, + &pci_dev_info_1043_80df, + &pci_dev_info_1043_815a, + &pci_dev_info_1043_8187, + &pci_dev_info_1043_8188, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1044[] = { + &pci_dev_info_1044_1012, + &pci_dev_info_1044_a400, + &pci_dev_info_1044_a500, + &pci_dev_info_1044_a501, + &pci_dev_info_1044_a511, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1045[] = { + &pci_dev_info_1045_a0f8, + &pci_dev_info_1045_c101, + &pci_dev_info_1045_c178, + &pci_dev_info_1045_c556, + &pci_dev_info_1045_c557, + &pci_dev_info_1045_c558, + &pci_dev_info_1045_c567, + &pci_dev_info_1045_c568, + &pci_dev_info_1045_c569, + &pci_dev_info_1045_c621, + &pci_dev_info_1045_c700, + &pci_dev_info_1045_c701, + &pci_dev_info_1045_c814, + &pci_dev_info_1045_c822, + &pci_dev_info_1045_c824, + &pci_dev_info_1045_c825, + &pci_dev_info_1045_c832, + &pci_dev_info_1045_c861, + &pci_dev_info_1045_c895, + &pci_dev_info_1045_c935, + &pci_dev_info_1045_d568, + &pci_dev_info_1045_d721, + NULL +}; +#endif +#define pci_dev_list_1046 NULL +#define pci_dev_list_1047 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1048[] = { + &pci_dev_info_1048_0c60, + &pci_dev_info_1048_0d22, + &pci_dev_info_1048_1000, + &pci_dev_info_1048_3000, + &pci_dev_info_1048_8901, + NULL +}; +#endif +#define pci_dev_list_1049 NULL +static const pciDeviceInfo *pci_dev_list_104a[] = { + &pci_dev_info_104a_0008, + &pci_dev_info_104a_0009, + &pci_dev_info_104a_0010, + &pci_dev_info_104a_0209, + &pci_dev_info_104a_020a, + &pci_dev_info_104a_0210, + &pci_dev_info_104a_021a, + &pci_dev_info_104a_021b, + &pci_dev_info_104a_0500, + &pci_dev_info_104a_0564, + &pci_dev_info_104a_0981, + &pci_dev_info_104a_1746, + &pci_dev_info_104a_2774, + &pci_dev_info_104a_3520, + &pci_dev_info_104a_55cc, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_104b[] = { + &pci_dev_info_104b_0140, + &pci_dev_info_104b_1040, + &pci_dev_info_104b_8130, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_104c[] = { + &pci_dev_info_104c_0500, + &pci_dev_info_104c_0508, + &pci_dev_info_104c_1000, + &pci_dev_info_104c_104c, + &pci_dev_info_104c_3d04, + &pci_dev_info_104c_3d07, + &pci_dev_info_104c_8000, + &pci_dev_info_104c_8009, + &pci_dev_info_104c_8017, + &pci_dev_info_104c_8019, + &pci_dev_info_104c_8020, + &pci_dev_info_104c_8021, + &pci_dev_info_104c_8022, + &pci_dev_info_104c_8023, + &pci_dev_info_104c_8024, + &pci_dev_info_104c_8025, + &pci_dev_info_104c_8026, + &pci_dev_info_104c_8027, + &pci_dev_info_104c_8029, + &pci_dev_info_104c_802b, + &pci_dev_info_104c_802e, + &pci_dev_info_104c_8031, + &pci_dev_info_104c_8032, + &pci_dev_info_104c_8033, + &pci_dev_info_104c_8034, + &pci_dev_info_104c_8035, + &pci_dev_info_104c_8036, + &pci_dev_info_104c_8038, + &pci_dev_info_104c_8039, + &pci_dev_info_104c_803a, + &pci_dev_info_104c_803b, + &pci_dev_info_104c_803c, + &pci_dev_info_104c_803d, + &pci_dev_info_104c_8201, + &pci_dev_info_104c_8204, + &pci_dev_info_104c_8231, + &pci_dev_info_104c_8235, + &pci_dev_info_104c_8400, + &pci_dev_info_104c_8401, + &pci_dev_info_104c_9000, + &pci_dev_info_104c_9065, + &pci_dev_info_104c_9066, + &pci_dev_info_104c_a001, + &pci_dev_info_104c_a100, + &pci_dev_info_104c_a102, + &pci_dev_info_104c_a106, + &pci_dev_info_104c_ac10, + &pci_dev_info_104c_ac11, + &pci_dev_info_104c_ac12, + &pci_dev_info_104c_ac13, + &pci_dev_info_104c_ac15, + &pci_dev_info_104c_ac16, + &pci_dev_info_104c_ac17, + &pci_dev_info_104c_ac18, + &pci_dev_info_104c_ac19, + &pci_dev_info_104c_ac1a, + &pci_dev_info_104c_ac1b, + &pci_dev_info_104c_ac1c, + &pci_dev_info_104c_ac1d, + &pci_dev_info_104c_ac1e, + &pci_dev_info_104c_ac1f, + &pci_dev_info_104c_ac20, + &pci_dev_info_104c_ac21, + &pci_dev_info_104c_ac22, + &pci_dev_info_104c_ac23, + &pci_dev_info_104c_ac28, + &pci_dev_info_104c_ac30, + &pci_dev_info_104c_ac40, + &pci_dev_info_104c_ac41, + &pci_dev_info_104c_ac42, + &pci_dev_info_104c_ac44, + &pci_dev_info_104c_ac46, + &pci_dev_info_104c_ac47, + &pci_dev_info_104c_ac4a, + &pci_dev_info_104c_ac50, + &pci_dev_info_104c_ac51, + &pci_dev_info_104c_ac52, + &pci_dev_info_104c_ac53, + &pci_dev_info_104c_ac54, + &pci_dev_info_104c_ac55, + &pci_dev_info_104c_ac56, + &pci_dev_info_104c_ac60, + &pci_dev_info_104c_ac8d, + &pci_dev_info_104c_ac8e, + &pci_dev_info_104c_ac8f, + &pci_dev_info_104c_fe00, + &pci_dev_info_104c_fe03, + NULL +}; +static const pciDeviceInfo *pci_dev_list_104d[] = { + &pci_dev_info_104d_8004, + &pci_dev_info_104d_8009, + &pci_dev_info_104d_8039, + &pci_dev_info_104d_8056, + &pci_dev_info_104d_808a, + NULL +}; +static const pciDeviceInfo *pci_dev_list_104e[] = { + &pci_dev_info_104e_0017, + &pci_dev_info_104e_0107, + &pci_dev_info_104e_0109, + &pci_dev_info_104e_0111, + &pci_dev_info_104e_0217, + &pci_dev_info_104e_0317, + NULL +}; +#define pci_dev_list_104f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1050[] = { + &pci_dev_info_1050_0000, + &pci_dev_info_1050_0001, + &pci_dev_info_1050_0033, + &pci_dev_info_1050_0105, + &pci_dev_info_1050_0840, + &pci_dev_info_1050_0940, + &pci_dev_info_1050_5a5a, + &pci_dev_info_1050_6692, + &pci_dev_info_1050_9921, + &pci_dev_info_1050_9922, + &pci_dev_info_1050_9970, + NULL +}; +#endif +#define pci_dev_list_1051 NULL +#define pci_dev_list_1052 NULL +#define pci_dev_list_1053 NULL +#define pci_dev_list_1054 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1055[] = { + &pci_dev_info_1055_9130, + &pci_dev_info_1055_9460, + &pci_dev_info_1055_9462, + &pci_dev_info_1055_9463, + NULL +}; +#endif +#define pci_dev_list_1056 NULL +static const pciDeviceInfo *pci_dev_list_1057[] = { + &pci_dev_info_1057_0001, + &pci_dev_info_1057_0002, + &pci_dev_info_1057_0003, + &pci_dev_info_1057_0004, + &pci_dev_info_1057_0006, + &pci_dev_info_1057_0008, + &pci_dev_info_1057_0009, + &pci_dev_info_1057_0012, + &pci_dev_info_1057_0100, + &pci_dev_info_1057_0431, + &pci_dev_info_1057_1801, + &pci_dev_info_1057_18c0, + &pci_dev_info_1057_18c1, + &pci_dev_info_1057_3055, + &pci_dev_info_1057_3410, + &pci_dev_info_1057_4801, + &pci_dev_info_1057_4802, + &pci_dev_info_1057_4803, + &pci_dev_info_1057_4806, + &pci_dev_info_1057_4d68, + &pci_dev_info_1057_5600, + &pci_dev_info_1057_5608, + &pci_dev_info_1057_5803, + &pci_dev_info_1057_5806, + &pci_dev_info_1057_5808, + &pci_dev_info_1057_5809, + &pci_dev_info_1057_6400, + &pci_dev_info_1057_6405, + NULL +}; +#define pci_dev_list_1058 NULL +#define pci_dev_list_1059 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_105a[] = { + &pci_dev_info_105a_0d30, + &pci_dev_info_105a_0d38, + &pci_dev_info_105a_1275, + &pci_dev_info_105a_3318, + &pci_dev_info_105a_3319, + &pci_dev_info_105a_3371, + &pci_dev_info_105a_3373, + &pci_dev_info_105a_3375, + &pci_dev_info_105a_3376, + &pci_dev_info_105a_3515, + &pci_dev_info_105a_3519, + &pci_dev_info_105a_3570, + &pci_dev_info_105a_3571, + &pci_dev_info_105a_3574, + &pci_dev_info_105a_3577, + &pci_dev_info_105a_3d17, + &pci_dev_info_105a_3d18, + &pci_dev_info_105a_3d73, + &pci_dev_info_105a_3d75, + &pci_dev_info_105a_4302, + &pci_dev_info_105a_4d30, + &pci_dev_info_105a_4d33, + &pci_dev_info_105a_4d38, + &pci_dev_info_105a_4d68, + &pci_dev_info_105a_4d69, + &pci_dev_info_105a_5275, + &pci_dev_info_105a_5300, + &pci_dev_info_105a_6268, + &pci_dev_info_105a_6269, + &pci_dev_info_105a_6621, + &pci_dev_info_105a_6622, + &pci_dev_info_105a_6624, + &pci_dev_info_105a_6626, + &pci_dev_info_105a_6629, + &pci_dev_info_105a_7275, + &pci_dev_info_105a_8002, + &pci_dev_info_105a_8350, + &pci_dev_info_105a_c350, + NULL +}; +#endif +#define pci_dev_list_105b NULL +#define pci_dev_list_105c NULL +static const pciDeviceInfo *pci_dev_list_105d[] = { + &pci_dev_info_105d_2309, + &pci_dev_info_105d_2339, + &pci_dev_info_105d_493d, + &pci_dev_info_105d_5348, + NULL +}; +#define pci_dev_list_105e NULL +#define pci_dev_list_105f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1060[] = { + &pci_dev_info_1060_0001, + &pci_dev_info_1060_0002, + &pci_dev_info_1060_0101, + &pci_dev_info_1060_0881, + &pci_dev_info_1060_0886, + &pci_dev_info_1060_0891, + &pci_dev_info_1060_1001, + &pci_dev_info_1060_673a, + &pci_dev_info_1060_673b, + &pci_dev_info_1060_8710, + &pci_dev_info_1060_886a, + &pci_dev_info_1060_8881, + &pci_dev_info_1060_8886, + &pci_dev_info_1060_888a, + &pci_dev_info_1060_8891, + &pci_dev_info_1060_9017, + &pci_dev_info_1060_9018, + &pci_dev_info_1060_9026, + &pci_dev_info_1060_e881, + &pci_dev_info_1060_e886, + &pci_dev_info_1060_e88a, + &pci_dev_info_1060_e891, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1061[] = { + &pci_dev_info_1061_0001, + &pci_dev_info_1061_0002, + NULL +}; +#endif +#define pci_dev_list_1062 NULL +#define pci_dev_list_1063 NULL +#define pci_dev_list_1064 NULL +#define pci_dev_list_1065 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1066[] = { + &pci_dev_info_1066_0000, + &pci_dev_info_1066_0001, + &pci_dev_info_1066_0002, + &pci_dev_info_1066_0003, + &pci_dev_info_1066_0004, + &pci_dev_info_1066_0005, + &pci_dev_info_1066_8002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1067[] = { + &pci_dev_info_1067_0301, + &pci_dev_info_1067_0304, + &pci_dev_info_1067_0308, + &pci_dev_info_1067_1002, + NULL +}; +#endif +#define pci_dev_list_1068 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1069[] = { + &pci_dev_info_1069_0001, + &pci_dev_info_1069_0002, + &pci_dev_info_1069_0010, + &pci_dev_info_1069_0020, + &pci_dev_info_1069_0050, + &pci_dev_info_1069_b166, + &pci_dev_info_1069_ba55, + &pci_dev_info_1069_ba56, + &pci_dev_info_1069_ba57, + NULL +}; +#endif +#define pci_dev_list_106a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_106b[] = { + &pci_dev_info_106b_0001, + &pci_dev_info_106b_0002, + &pci_dev_info_106b_0003, + &pci_dev_info_106b_0004, + &pci_dev_info_106b_0007, + &pci_dev_info_106b_000c, + &pci_dev_info_106b_000e, + &pci_dev_info_106b_0010, + &pci_dev_info_106b_0017, + &pci_dev_info_106b_0018, + &pci_dev_info_106b_0019, + &pci_dev_info_106b_001e, + &pci_dev_info_106b_001f, + &pci_dev_info_106b_0020, + &pci_dev_info_106b_0021, + &pci_dev_info_106b_0022, + &pci_dev_info_106b_0024, + &pci_dev_info_106b_0025, + &pci_dev_info_106b_0026, + &pci_dev_info_106b_0027, + &pci_dev_info_106b_0028, + &pci_dev_info_106b_0029, + &pci_dev_info_106b_002d, + &pci_dev_info_106b_002e, + &pci_dev_info_106b_002f, + &pci_dev_info_106b_0030, + &pci_dev_info_106b_0031, + &pci_dev_info_106b_0032, + &pci_dev_info_106b_0033, + &pci_dev_info_106b_0034, + &pci_dev_info_106b_0035, + &pci_dev_info_106b_0036, + &pci_dev_info_106b_003b, + &pci_dev_info_106b_003e, + &pci_dev_info_106b_003f, + &pci_dev_info_106b_0040, + &pci_dev_info_106b_0041, + &pci_dev_info_106b_0042, + &pci_dev_info_106b_0043, + &pci_dev_info_106b_0045, + &pci_dev_info_106b_0046, + &pci_dev_info_106b_0047, + &pci_dev_info_106b_0048, + &pci_dev_info_106b_0049, + &pci_dev_info_106b_004b, + &pci_dev_info_106b_004c, + &pci_dev_info_106b_004f, + &pci_dev_info_106b_0050, + &pci_dev_info_106b_0051, + &pci_dev_info_106b_0052, + &pci_dev_info_106b_0053, + &pci_dev_info_106b_0054, + &pci_dev_info_106b_0055, + &pci_dev_info_106b_0058, + &pci_dev_info_106b_0059, + &pci_dev_info_106b_0066, + &pci_dev_info_106b_0067, + &pci_dev_info_106b_0068, + &pci_dev_info_106b_0069, + &pci_dev_info_106b_006a, + &pci_dev_info_106b_006b, + &pci_dev_info_106b_1645, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_106c[] = { + &pci_dev_info_106c_8801, + &pci_dev_info_106c_8802, + &pci_dev_info_106c_8803, + &pci_dev_info_106c_8804, + &pci_dev_info_106c_8805, + NULL +}; +#endif +#define pci_dev_list_106d NULL +#define pci_dev_list_106e NULL +#define pci_dev_list_106f NULL +#define pci_dev_list_1070 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1071[] = { + &pci_dev_info_1071_8160, + NULL +}; +#endif +#define pci_dev_list_1072 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1073[] = { + &pci_dev_info_1073_0001, + &pci_dev_info_1073_0002, + &pci_dev_info_1073_0003, + &pci_dev_info_1073_0004, + &pci_dev_info_1073_0005, + &pci_dev_info_1073_0006, + &pci_dev_info_1073_0008, + &pci_dev_info_1073_000a, + &pci_dev_info_1073_000c, + &pci_dev_info_1073_000d, + &pci_dev_info_1073_0010, + &pci_dev_info_1073_0012, + &pci_dev_info_1073_0020, + &pci_dev_info_1073_2000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1074[] = { + &pci_dev_info_1074_4e78, + NULL +}; +#endif +#define pci_dev_list_1075 NULL +#define pci_dev_list_1076 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1077[] = { + &pci_dev_info_1077_1016, + &pci_dev_info_1077_1020, + &pci_dev_info_1077_1022, + &pci_dev_info_1077_1080, + &pci_dev_info_1077_1216, + &pci_dev_info_1077_1240, + &pci_dev_info_1077_1280, + &pci_dev_info_1077_2020, + &pci_dev_info_1077_2100, + &pci_dev_info_1077_2200, + &pci_dev_info_1077_2300, + &pci_dev_info_1077_2312, + &pci_dev_info_1077_2322, + &pci_dev_info_1077_2422, + &pci_dev_info_1077_2432, + &pci_dev_info_1077_3010, + &pci_dev_info_1077_3022, + &pci_dev_info_1077_4010, + &pci_dev_info_1077_4022, + &pci_dev_info_1077_6312, + &pci_dev_info_1077_6322, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_1078[] = { + &pci_dev_info_1078_0000, + &pci_dev_info_1078_0001, + &pci_dev_info_1078_0002, + &pci_dev_info_1078_0100, + &pci_dev_info_1078_0101, + &pci_dev_info_1078_0102, + &pci_dev_info_1078_0103, + &pci_dev_info_1078_0104, + &pci_dev_info_1078_0400, + &pci_dev_info_1078_0401, + &pci_dev_info_1078_0402, + &pci_dev_info_1078_0403, + NULL +}; +#define pci_dev_list_1079 NULL +#define pci_dev_list_107a NULL +#define pci_dev_list_107b NULL +#define pci_dev_list_107c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_107d[] = { + &pci_dev_info_107d_0000, + &pci_dev_info_107d_204d, + &pci_dev_info_107d_2134, + &pci_dev_info_107d_2971, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_107e[] = { + &pci_dev_info_107e_0001, + &pci_dev_info_107e_0002, + &pci_dev_info_107e_0004, + &pci_dev_info_107e_0005, + &pci_dev_info_107e_0008, + &pci_dev_info_107e_9003, + &pci_dev_info_107e_9007, + &pci_dev_info_107e_9008, + &pci_dev_info_107e_900c, + &pci_dev_info_107e_900e, + &pci_dev_info_107e_9011, + &pci_dev_info_107e_9013, + &pci_dev_info_107e_9023, + &pci_dev_info_107e_9027, + &pci_dev_info_107e_9031, + &pci_dev_info_107e_9033, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_107f[] = { + &pci_dev_info_107f_0802, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1080[] = { + &pci_dev_info_1080_0600, + &pci_dev_info_1080_c691, + &pci_dev_info_1080_c693, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1081[] = { + &pci_dev_info_1081_0d47, + NULL +}; +#endif +#define pci_dev_list_1082 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1083[] = { + &pci_dev_info_1083_0001, + NULL +}; +#endif +#define pci_dev_list_1084 NULL +#define pci_dev_list_1085 NULL +#define pci_dev_list_1086 NULL +#define pci_dev_list_1087 NULL +#define pci_dev_list_1088 NULL +#define pci_dev_list_1089 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_108a[] = { + &pci_dev_info_108a_0001, + &pci_dev_info_108a_0010, + &pci_dev_info_108a_0040, + &pci_dev_info_108a_3000, + NULL +}; +#endif +#define pci_dev_list_108c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_108d[] = { + &pci_dev_info_108d_0001, + &pci_dev_info_108d_0002, + &pci_dev_info_108d_0004, + &pci_dev_info_108d_0005, + &pci_dev_info_108d_0006, + &pci_dev_info_108d_0007, + &pci_dev_info_108d_0008, + &pci_dev_info_108d_0011, + &pci_dev_info_108d_0012, + &pci_dev_info_108d_0013, + &pci_dev_info_108d_0014, + &pci_dev_info_108d_0019, + &pci_dev_info_108d_0021, + &pci_dev_info_108d_0022, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_108e[] = { + &pci_dev_info_108e_0001, + &pci_dev_info_108e_1000, + &pci_dev_info_108e_1001, + &pci_dev_info_108e_1100, + &pci_dev_info_108e_1101, + &pci_dev_info_108e_1102, + &pci_dev_info_108e_1103, + &pci_dev_info_108e_1648, + &pci_dev_info_108e_2bad, + &pci_dev_info_108e_5000, + &pci_dev_info_108e_5043, + &pci_dev_info_108e_8000, + &pci_dev_info_108e_8001, + &pci_dev_info_108e_8002, + &pci_dev_info_108e_a000, + &pci_dev_info_108e_a001, + &pci_dev_info_108e_a801, + &pci_dev_info_108e_abba, + NULL +}; +#define pci_dev_list_108f NULL +#define pci_dev_list_1090 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1091[] = { + &pci_dev_info_1091_0020, + &pci_dev_info_1091_0021, + &pci_dev_info_1091_0040, + &pci_dev_info_1091_0041, + &pci_dev_info_1091_0060, + &pci_dev_info_1091_00e4, + &pci_dev_info_1091_0720, + &pci_dev_info_1091_07a0, + &pci_dev_info_1091_1091, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_1092[] = { + &pci_dev_info_1092_00a0, + &pci_dev_info_1092_00a8, + &pci_dev_info_1092_0550, + &pci_dev_info_1092_08d4, + &pci_dev_info_1092_094c, + &pci_dev_info_1092_1092, + &pci_dev_info_1092_6120, + &pci_dev_info_1092_8810, + &pci_dev_info_1092_8811, + &pci_dev_info_1092_8880, + &pci_dev_info_1092_8881, + &pci_dev_info_1092_88b0, + &pci_dev_info_1092_88b1, + &pci_dev_info_1092_88c0, + &pci_dev_info_1092_88c1, + &pci_dev_info_1092_88d0, + &pci_dev_info_1092_88d1, + &pci_dev_info_1092_88f0, + &pci_dev_info_1092_88f1, + &pci_dev_info_1092_9999, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1093[] = { + &pci_dev_info_1093_0160, + &pci_dev_info_1093_0162, + &pci_dev_info_1093_1150, + &pci_dev_info_1093_1170, + &pci_dev_info_1093_1180, + &pci_dev_info_1093_1190, + &pci_dev_info_1093_1310, + &pci_dev_info_1093_1330, + &pci_dev_info_1093_1350, + &pci_dev_info_1093_14e0, + &pci_dev_info_1093_14f0, + &pci_dev_info_1093_17d0, + &pci_dev_info_1093_1870, + &pci_dev_info_1093_1880, + &pci_dev_info_1093_18b0, + &pci_dev_info_1093_2410, + &pci_dev_info_1093_2890, + &pci_dev_info_1093_2a60, + &pci_dev_info_1093_2a70, + &pci_dev_info_1093_2a80, + &pci_dev_info_1093_2c80, + &pci_dev_info_1093_2ca0, + &pci_dev_info_1093_70a9, + &pci_dev_info_1093_70b8, + &pci_dev_info_1093_b001, + &pci_dev_info_1093_b011, + &pci_dev_info_1093_b021, + &pci_dev_info_1093_b031, + &pci_dev_info_1093_b041, + &pci_dev_info_1093_b051, + &pci_dev_info_1093_b061, + &pci_dev_info_1093_b071, + &pci_dev_info_1093_b081, + &pci_dev_info_1093_b091, + &pci_dev_info_1093_c801, + &pci_dev_info_1093_c831, + NULL +}; +#endif +#define pci_dev_list_1094 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1095[] = { + &pci_dev_info_1095_0240, + &pci_dev_info_1095_0640, + &pci_dev_info_1095_0643, + &pci_dev_info_1095_0646, + &pci_dev_info_1095_0647, + &pci_dev_info_1095_0648, + &pci_dev_info_1095_0649, + &pci_dev_info_1095_0650, + &pci_dev_info_1095_0670, + &pci_dev_info_1095_0673, + &pci_dev_info_1095_0680, + &pci_dev_info_1095_3112, + &pci_dev_info_1095_3114, + &pci_dev_info_1095_3124, + &pci_dev_info_1095_3132, + &pci_dev_info_1095_3512, + NULL +}; +#endif +#define pci_dev_list_1096 NULL +#define pci_dev_list_1097 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1098[] = { + &pci_dev_info_1098_0001, + &pci_dev_info_1098_0002, + NULL +}; +#endif +#define pci_dev_list_1099 NULL +#define pci_dev_list_109a NULL +#define pci_dev_list_109b NULL +#define pci_dev_list_109c NULL +#define pci_dev_list_109d NULL +static const pciDeviceInfo *pci_dev_list_109e[] = { + &pci_dev_info_109e_032e, + &pci_dev_info_109e_0350, + &pci_dev_info_109e_0351, + &pci_dev_info_109e_0369, + &pci_dev_info_109e_036c, + &pci_dev_info_109e_036e, + &pci_dev_info_109e_036f, + &pci_dev_info_109e_0370, + &pci_dev_info_109e_0878, + &pci_dev_info_109e_0879, + &pci_dev_info_109e_0880, + &pci_dev_info_109e_2115, + &pci_dev_info_109e_2125, + &pci_dev_info_109e_2164, + &pci_dev_info_109e_2165, + &pci_dev_info_109e_8230, + &pci_dev_info_109e_8472, + &pci_dev_info_109e_8474, + NULL +}; +#define pci_dev_list_109f NULL +#define pci_dev_list_10a0 NULL +#define pci_dev_list_10a1 NULL +#define pci_dev_list_10a2 NULL +#define pci_dev_list_10a3 NULL +#define pci_dev_list_10a4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10a5[] = { + &pci_dev_info_10a5_3052, + &pci_dev_info_10a5_5449, + NULL +}; +#endif +#define pci_dev_list_10a6 NULL +#define pci_dev_list_10a7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10a8[] = { + &pci_dev_info_10a8_0000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10a9[] = { + &pci_dev_info_10a9_0001, + &pci_dev_info_10a9_0002, + &pci_dev_info_10a9_0003, + &pci_dev_info_10a9_0004, + &pci_dev_info_10a9_0005, + &pci_dev_info_10a9_0006, + &pci_dev_info_10a9_0007, + &pci_dev_info_10a9_0008, + &pci_dev_info_10a9_0009, + &pci_dev_info_10a9_0010, + &pci_dev_info_10a9_0011, + &pci_dev_info_10a9_0012, + &pci_dev_info_10a9_1001, + &pci_dev_info_10a9_1002, + &pci_dev_info_10a9_1003, + &pci_dev_info_10a9_1004, + &pci_dev_info_10a9_1005, + &pci_dev_info_10a9_1006, + &pci_dev_info_10a9_1007, + &pci_dev_info_10a9_1008, + &pci_dev_info_10a9_100a, + &pci_dev_info_10a9_2001, + &pci_dev_info_10a9_2002, + &pci_dev_info_10a9_4001, + &pci_dev_info_10a9_4002, + &pci_dev_info_10a9_8001, + &pci_dev_info_10a9_8002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10aa[] = { + &pci_dev_info_10aa_0000, + NULL +}; +#endif +#define pci_dev_list_10ab NULL +#define pci_dev_list_10ac NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ad[] = { + &pci_dev_info_10ad_0001, + &pci_dev_info_10ad_0003, + &pci_dev_info_10ad_0005, + &pci_dev_info_10ad_0103, + &pci_dev_info_10ad_0105, + &pci_dev_info_10ad_0565, + NULL +}; +#endif +#define pci_dev_list_10ae NULL +#define pci_dev_list_10af NULL +#define pci_dev_list_10b0 NULL +#define pci_dev_list_10b1 NULL +#define pci_dev_list_10b2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b3[] = { + &pci_dev_info_10b3_3106, + &pci_dev_info_10b3_b106, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b4[] = { + &pci_dev_info_10b4_1b1d, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b5[] = { + &pci_dev_info_10b5_0001, + &pci_dev_info_10b5_1042, + &pci_dev_info_10b5_1076, + &pci_dev_info_10b5_1077, + &pci_dev_info_10b5_1078, + &pci_dev_info_10b5_1103, + &pci_dev_info_10b5_1146, + &pci_dev_info_10b5_1147, + &pci_dev_info_10b5_2540, + &pci_dev_info_10b5_2724, + &pci_dev_info_10b5_6540, + &pci_dev_info_10b5_6541, + &pci_dev_info_10b5_6542, + &pci_dev_info_10b5_8111, + &pci_dev_info_10b5_8114, + &pci_dev_info_10b5_8516, + &pci_dev_info_10b5_8532, + &pci_dev_info_10b5_9030, + &pci_dev_info_10b5_9036, + &pci_dev_info_10b5_9050, + &pci_dev_info_10b5_9054, + &pci_dev_info_10b5_9056, + &pci_dev_info_10b5_9060, + &pci_dev_info_10b5_906d, + &pci_dev_info_10b5_906e, + &pci_dev_info_10b5_9080, + &pci_dev_info_10b5_9656, + &pci_dev_info_10b5_bb04, + &pci_dev_info_10b5_c001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b6[] = { + &pci_dev_info_10b6_0001, + &pci_dev_info_10b6_0002, + &pci_dev_info_10b6_0003, + &pci_dev_info_10b6_0004, + &pci_dev_info_10b6_0006, + &pci_dev_info_10b6_0007, + &pci_dev_info_10b6_0009, + &pci_dev_info_10b6_000a, + &pci_dev_info_10b6_000b, + &pci_dev_info_10b6_000c, + &pci_dev_info_10b6_1000, + &pci_dev_info_10b6_1001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b7[] = { + &pci_dev_info_10b7_0001, + &pci_dev_info_10b7_0013, + &pci_dev_info_10b7_0910, + &pci_dev_info_10b7_1006, + &pci_dev_info_10b7_1007, + &pci_dev_info_10b7_1201, + &pci_dev_info_10b7_1202, + &pci_dev_info_10b7_1700, + &pci_dev_info_10b7_3390, + &pci_dev_info_10b7_3590, + &pci_dev_info_10b7_4500, + &pci_dev_info_10b7_5055, + &pci_dev_info_10b7_5057, + &pci_dev_info_10b7_5157, + &pci_dev_info_10b7_5257, + &pci_dev_info_10b7_5900, + &pci_dev_info_10b7_5920, + &pci_dev_info_10b7_5950, + &pci_dev_info_10b7_5951, + &pci_dev_info_10b7_5952, + &pci_dev_info_10b7_5970, + &pci_dev_info_10b7_5b57, + &pci_dev_info_10b7_6000, + &pci_dev_info_10b7_6001, + &pci_dev_info_10b7_6055, + &pci_dev_info_10b7_6056, + &pci_dev_info_10b7_6560, + &pci_dev_info_10b7_6561, + &pci_dev_info_10b7_6562, + &pci_dev_info_10b7_6563, + &pci_dev_info_10b7_6564, + &pci_dev_info_10b7_7646, + &pci_dev_info_10b7_7770, + &pci_dev_info_10b7_7940, + &pci_dev_info_10b7_7980, + &pci_dev_info_10b7_7990, + &pci_dev_info_10b7_80eb, + &pci_dev_info_10b7_8811, + &pci_dev_info_10b7_9000, + &pci_dev_info_10b7_9001, + &pci_dev_info_10b7_9004, + &pci_dev_info_10b7_9005, + &pci_dev_info_10b7_9006, + &pci_dev_info_10b7_900a, + &pci_dev_info_10b7_9050, + &pci_dev_info_10b7_9051, + &pci_dev_info_10b7_9054, + &pci_dev_info_10b7_9055, + &pci_dev_info_10b7_9056, + &pci_dev_info_10b7_9058, + &pci_dev_info_10b7_905a, + &pci_dev_info_10b7_9200, + &pci_dev_info_10b7_9201, + &pci_dev_info_10b7_9202, + &pci_dev_info_10b7_9210, + &pci_dev_info_10b7_9300, + &pci_dev_info_10b7_9800, + &pci_dev_info_10b7_9805, + &pci_dev_info_10b7_9900, + &pci_dev_info_10b7_9902, + &pci_dev_info_10b7_9903, + &pci_dev_info_10b7_9904, + &pci_dev_info_10b7_9905, + &pci_dev_info_10b7_9908, + &pci_dev_info_10b7_9909, + &pci_dev_info_10b7_990a, + &pci_dev_info_10b7_990b, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b8[] = { + &pci_dev_info_10b8_0005, + &pci_dev_info_10b8_0006, + &pci_dev_info_10b8_1000, + &pci_dev_info_10b8_1001, + &pci_dev_info_10b8_2802, + &pci_dev_info_10b8_a011, + &pci_dev_info_10b8_b106, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10b9[] = { + &pci_dev_info_10b9_0101, + &pci_dev_info_10b9_0111, + &pci_dev_info_10b9_0780, + &pci_dev_info_10b9_0782, + &pci_dev_info_10b9_1435, + &pci_dev_info_10b9_1445, + &pci_dev_info_10b9_1449, + &pci_dev_info_10b9_1451, + &pci_dev_info_10b9_1461, + &pci_dev_info_10b9_1489, + &pci_dev_info_10b9_1511, + &pci_dev_info_10b9_1512, + &pci_dev_info_10b9_1513, + &pci_dev_info_10b9_1521, + &pci_dev_info_10b9_1523, + &pci_dev_info_10b9_1531, + &pci_dev_info_10b9_1533, + &pci_dev_info_10b9_1541, + &pci_dev_info_10b9_1543, + &pci_dev_info_10b9_1563, + &pci_dev_info_10b9_1573, + &pci_dev_info_10b9_1621, + &pci_dev_info_10b9_1631, + &pci_dev_info_10b9_1632, + &pci_dev_info_10b9_1641, + &pci_dev_info_10b9_1644, + &pci_dev_info_10b9_1646, + &pci_dev_info_10b9_1647, + &pci_dev_info_10b9_1651, + &pci_dev_info_10b9_1671, + &pci_dev_info_10b9_1672, + &pci_dev_info_10b9_1681, + &pci_dev_info_10b9_1687, + &pci_dev_info_10b9_1689, + &pci_dev_info_10b9_1695, + &pci_dev_info_10b9_1697, + &pci_dev_info_10b9_3141, + &pci_dev_info_10b9_3143, + &pci_dev_info_10b9_3145, + &pci_dev_info_10b9_3147, + &pci_dev_info_10b9_3149, + &pci_dev_info_10b9_3151, + &pci_dev_info_10b9_3307, + &pci_dev_info_10b9_3309, + &pci_dev_info_10b9_3323, + &pci_dev_info_10b9_5212, + &pci_dev_info_10b9_5215, + &pci_dev_info_10b9_5217, + &pci_dev_info_10b9_5219, + &pci_dev_info_10b9_5225, + &pci_dev_info_10b9_5228, + &pci_dev_info_10b9_5229, + &pci_dev_info_10b9_5235, + &pci_dev_info_10b9_5237, + &pci_dev_info_10b9_5239, + &pci_dev_info_10b9_5243, + &pci_dev_info_10b9_5246, + &pci_dev_info_10b9_5247, + &pci_dev_info_10b9_5249, + &pci_dev_info_10b9_524b, + &pci_dev_info_10b9_524c, + &pci_dev_info_10b9_524d, + &pci_dev_info_10b9_524e, + &pci_dev_info_10b9_5251, + &pci_dev_info_10b9_5253, + &pci_dev_info_10b9_5261, + &pci_dev_info_10b9_5263, + &pci_dev_info_10b9_5281, + &pci_dev_info_10b9_5287, + &pci_dev_info_10b9_5288, + &pci_dev_info_10b9_5289, + &pci_dev_info_10b9_5450, + &pci_dev_info_10b9_5451, + &pci_dev_info_10b9_5453, + &pci_dev_info_10b9_5455, + &pci_dev_info_10b9_5457, + &pci_dev_info_10b9_5459, + &pci_dev_info_10b9_545a, + &pci_dev_info_10b9_5461, + &pci_dev_info_10b9_5471, + &pci_dev_info_10b9_5473, + &pci_dev_info_10b9_7101, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ba[] = { + &pci_dev_info_10ba_0301, + &pci_dev_info_10ba_0304, + &pci_dev_info_10ba_0308, + &pci_dev_info_10ba_1002, + NULL +}; +#endif +#define pci_dev_list_10bb NULL +#define pci_dev_list_10bc NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10bd[] = { + &pci_dev_info_10bd_0e34, + NULL +}; +#endif +#define pci_dev_list_10be NULL +#define pci_dev_list_10bf NULL +#define pci_dev_list_10c0 NULL +#define pci_dev_list_10c1 NULL +#define pci_dev_list_10c2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10c3[] = { + &pci_dev_info_10c3_1100, + NULL +}; +#endif +#define pci_dev_list_10c4 NULL +#define pci_dev_list_10c5 NULL +#define pci_dev_list_10c6 NULL +#define pci_dev_list_10c7 NULL +static const pciDeviceInfo *pci_dev_list_10c8[] = { + &pci_dev_info_10c8_0001, + &pci_dev_info_10c8_0002, + &pci_dev_info_10c8_0003, + &pci_dev_info_10c8_0004, + &pci_dev_info_10c8_0005, + &pci_dev_info_10c8_0006, + &pci_dev_info_10c8_0016, + &pci_dev_info_10c8_0025, + &pci_dev_info_10c8_0083, + &pci_dev_info_10c8_8005, + &pci_dev_info_10c8_8006, + &pci_dev_info_10c8_8016, + NULL +}; +#define pci_dev_list_10c9 NULL +#define pci_dev_list_10ca NULL +#define pci_dev_list_10cb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10cc[] = { + &pci_dev_info_10cc_0660, + &pci_dev_info_10cc_0661, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10cd[] = { + &pci_dev_info_10cd_1100, + &pci_dev_info_10cd_1200, + &pci_dev_info_10cd_1300, + &pci_dev_info_10cd_2300, + &pci_dev_info_10cd_2500, + NULL +}; +#endif +#define pci_dev_list_10ce NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10cf[] = { + &pci_dev_info_10cf_2001, + NULL +}; +#endif +#define pci_dev_list_10d1 NULL +#define pci_dev_list_10d2 NULL +#define pci_dev_list_10d3 NULL +#define pci_dev_list_10d4 NULL +#define pci_dev_list_10d5 NULL +#define pci_dev_list_10d6 NULL +#define pci_dev_list_10d7 NULL +#define pci_dev_list_10d8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10d9[] = { + &pci_dev_info_10d9_0431, + &pci_dev_info_10d9_0512, + &pci_dev_info_10d9_0531, + &pci_dev_info_10d9_8625, + &pci_dev_info_10d9_8626, + &pci_dev_info_10d9_8888, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10da[] = { + &pci_dev_info_10da_0508, + &pci_dev_info_10da_3390, + NULL +}; +#endif +#define pci_dev_list_10db NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10dc[] = { + &pci_dev_info_10dc_0001, + &pci_dev_info_10dc_0002, + &pci_dev_info_10dc_0021, + &pci_dev_info_10dc_0022, + &pci_dev_info_10dc_10dc, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10dd[] = { + &pci_dev_info_10dd_0100, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_10de[] = { + &pci_dev_info_10de_0008, + &pci_dev_info_10de_0009, + &pci_dev_info_10de_0010, + &pci_dev_info_10de_0020, + &pci_dev_info_10de_0028, + &pci_dev_info_10de_0029, + &pci_dev_info_10de_002a, + &pci_dev_info_10de_002b, + &pci_dev_info_10de_002c, + &pci_dev_info_10de_002d, + &pci_dev_info_10de_002e, + &pci_dev_info_10de_002f, + &pci_dev_info_10de_0034, + &pci_dev_info_10de_0035, + &pci_dev_info_10de_0036, + &pci_dev_info_10de_0037, + &pci_dev_info_10de_0038, + &pci_dev_info_10de_003a, + &pci_dev_info_10de_003b, + &pci_dev_info_10de_003c, + &pci_dev_info_10de_003d, + &pci_dev_info_10de_003e, + &pci_dev_info_10de_0040, + &pci_dev_info_10de_0041, + &pci_dev_info_10de_0042, + &pci_dev_info_10de_0043, + &pci_dev_info_10de_0044, + &pci_dev_info_10de_0045, + &pci_dev_info_10de_0046, + &pci_dev_info_10de_0047, + &pci_dev_info_10de_0048, + &pci_dev_info_10de_0049, + &pci_dev_info_10de_004d, + &pci_dev_info_10de_004e, + &pci_dev_info_10de_0050, + &pci_dev_info_10de_0051, + &pci_dev_info_10de_0052, + &pci_dev_info_10de_0053, + &pci_dev_info_10de_0054, + &pci_dev_info_10de_0055, + &pci_dev_info_10de_0056, + &pci_dev_info_10de_0057, + &pci_dev_info_10de_0058, + &pci_dev_info_10de_0059, + &pci_dev_info_10de_005a, + &pci_dev_info_10de_005b, + &pci_dev_info_10de_005c, + &pci_dev_info_10de_005d, + &pci_dev_info_10de_005e, + &pci_dev_info_10de_005f, + &pci_dev_info_10de_0060, + &pci_dev_info_10de_0064, + &pci_dev_info_10de_0065, + &pci_dev_info_10de_0066, + &pci_dev_info_10de_0067, + &pci_dev_info_10de_0068, + &pci_dev_info_10de_006a, + &pci_dev_info_10de_006b, + &pci_dev_info_10de_006c, + &pci_dev_info_10de_006d, + &pci_dev_info_10de_006e, + &pci_dev_info_10de_0080, + &pci_dev_info_10de_0084, + &pci_dev_info_10de_0085, + &pci_dev_info_10de_0086, + &pci_dev_info_10de_0087, + &pci_dev_info_10de_0088, + &pci_dev_info_10de_008a, + &pci_dev_info_10de_008b, + &pci_dev_info_10de_008c, + &pci_dev_info_10de_008e, + &pci_dev_info_10de_0090, + &pci_dev_info_10de_0091, + &pci_dev_info_10de_0092, + &pci_dev_info_10de_0093, + &pci_dev_info_10de_0098, + &pci_dev_info_10de_0099, + &pci_dev_info_10de_009d, + &pci_dev_info_10de_00a0, + &pci_dev_info_10de_00c0, + &pci_dev_info_10de_00c1, + &pci_dev_info_10de_00c2, + &pci_dev_info_10de_00c3, + &pci_dev_info_10de_00c8, + &pci_dev_info_10de_00c9, + &pci_dev_info_10de_00cc, + &pci_dev_info_10de_00cd, + &pci_dev_info_10de_00ce, + &pci_dev_info_10de_00d0, + &pci_dev_info_10de_00d1, + &pci_dev_info_10de_00d2, + &pci_dev_info_10de_00d3, + &pci_dev_info_10de_00d4, + &pci_dev_info_10de_00d5, + &pci_dev_info_10de_00d6, + &pci_dev_info_10de_00d7, + &pci_dev_info_10de_00d8, + &pci_dev_info_10de_00d9, + &pci_dev_info_10de_00da, + &pci_dev_info_10de_00dd, + &pci_dev_info_10de_00df, + &pci_dev_info_10de_00e0, + &pci_dev_info_10de_00e1, + &pci_dev_info_10de_00e2, + &pci_dev_info_10de_00e3, + &pci_dev_info_10de_00e4, + &pci_dev_info_10de_00e5, + &pci_dev_info_10de_00e6, + &pci_dev_info_10de_00e7, + &pci_dev_info_10de_00e8, + &pci_dev_info_10de_00ea, + &pci_dev_info_10de_00ed, + &pci_dev_info_10de_00ee, + &pci_dev_info_10de_00f0, + &pci_dev_info_10de_00f1, + &pci_dev_info_10de_00f2, + &pci_dev_info_10de_00f3, + &pci_dev_info_10de_00f4, + &pci_dev_info_10de_00f5, + &pci_dev_info_10de_00f6, + &pci_dev_info_10de_00f8, + &pci_dev_info_10de_00f9, + &pci_dev_info_10de_00fa, + &pci_dev_info_10de_00fb, + &pci_dev_info_10de_00fc, + &pci_dev_info_10de_00fd, + &pci_dev_info_10de_00fe, + &pci_dev_info_10de_00ff, + &pci_dev_info_10de_0100, + &pci_dev_info_10de_0101, + &pci_dev_info_10de_0103, + &pci_dev_info_10de_0110, + &pci_dev_info_10de_0111, + &pci_dev_info_10de_0112, + &pci_dev_info_10de_0113, + &pci_dev_info_10de_0140, + &pci_dev_info_10de_0141, + &pci_dev_info_10de_0142, + &pci_dev_info_10de_0144, + &pci_dev_info_10de_0145, + &pci_dev_info_10de_0146, + &pci_dev_info_10de_0147, + &pci_dev_info_10de_0148, + &pci_dev_info_10de_0149, + &pci_dev_info_10de_014a, + &pci_dev_info_10de_014c, + &pci_dev_info_10de_014d, + &pci_dev_info_10de_014e, + &pci_dev_info_10de_014f, + &pci_dev_info_10de_0150, + &pci_dev_info_10de_0151, + &pci_dev_info_10de_0152, + &pci_dev_info_10de_0153, + &pci_dev_info_10de_0160, + &pci_dev_info_10de_0161, + &pci_dev_info_10de_0162, + &pci_dev_info_10de_0163, + &pci_dev_info_10de_0164, + &pci_dev_info_10de_0165, + &pci_dev_info_10de_0166, + &pci_dev_info_10de_0167, + &pci_dev_info_10de_0168, + &pci_dev_info_10de_0169, + &pci_dev_info_10de_0170, + &pci_dev_info_10de_0171, + &pci_dev_info_10de_0172, + &pci_dev_info_10de_0173, + &pci_dev_info_10de_0174, + &pci_dev_info_10de_0175, + &pci_dev_info_10de_0176, + &pci_dev_info_10de_0177, + &pci_dev_info_10de_0178, + &pci_dev_info_10de_0179, + &pci_dev_info_10de_017a, + &pci_dev_info_10de_017b, + &pci_dev_info_10de_017c, + &pci_dev_info_10de_017d, + &pci_dev_info_10de_0181, + &pci_dev_info_10de_0182, + &pci_dev_info_10de_0183, + &pci_dev_info_10de_0185, + &pci_dev_info_10de_0186, + &pci_dev_info_10de_0187, + &pci_dev_info_10de_0188, + &pci_dev_info_10de_018a, + &pci_dev_info_10de_018b, + &pci_dev_info_10de_018c, + &pci_dev_info_10de_018d, + &pci_dev_info_10de_01a0, + &pci_dev_info_10de_01a4, + &pci_dev_info_10de_01ab, + &pci_dev_info_10de_01ac, + &pci_dev_info_10de_01ad, + &pci_dev_info_10de_01b0, + &pci_dev_info_10de_01b1, + &pci_dev_info_10de_01b2, + &pci_dev_info_10de_01b4, + &pci_dev_info_10de_01b7, + &pci_dev_info_10de_01b8, + &pci_dev_info_10de_01bc, + &pci_dev_info_10de_01c1, + &pci_dev_info_10de_01c2, + &pci_dev_info_10de_01c3, + &pci_dev_info_10de_01d1, + &pci_dev_info_10de_01d6, + &pci_dev_info_10de_01d7, + &pci_dev_info_10de_01d8, + &pci_dev_info_10de_01da, + &pci_dev_info_10de_01de, + &pci_dev_info_10de_01df, + &pci_dev_info_10de_01e0, + &pci_dev_info_10de_01e8, + &pci_dev_info_10de_01ea, + &pci_dev_info_10de_01eb, + &pci_dev_info_10de_01ec, + &pci_dev_info_10de_01ed, + &pci_dev_info_10de_01ee, + &pci_dev_info_10de_01ef, + &pci_dev_info_10de_01f0, + &pci_dev_info_10de_0200, + &pci_dev_info_10de_0201, + &pci_dev_info_10de_0202, + &pci_dev_info_10de_0203, + &pci_dev_info_10de_0211, + &pci_dev_info_10de_0212, + &pci_dev_info_10de_0215, + &pci_dev_info_10de_0218, + &pci_dev_info_10de_0221, + &pci_dev_info_10de_0240, + &pci_dev_info_10de_0241, + &pci_dev_info_10de_0242, + &pci_dev_info_10de_0243, + &pci_dev_info_10de_0244, + &pci_dev_info_10de_0245, + &pci_dev_info_10de_0246, + &pci_dev_info_10de_0247, + &pci_dev_info_10de_0248, + &pci_dev_info_10de_0249, + &pci_dev_info_10de_024a, + &pci_dev_info_10de_024b, + &pci_dev_info_10de_024c, + &pci_dev_info_10de_024d, + &pci_dev_info_10de_024e, + &pci_dev_info_10de_024f, + &pci_dev_info_10de_0250, + &pci_dev_info_10de_0251, + &pci_dev_info_10de_0252, + &pci_dev_info_10de_0253, + &pci_dev_info_10de_0258, + &pci_dev_info_10de_0259, + &pci_dev_info_10de_025b, + &pci_dev_info_10de_0260, + &pci_dev_info_10de_0261, + &pci_dev_info_10de_0262, + &pci_dev_info_10de_0263, + &pci_dev_info_10de_0264, + &pci_dev_info_10de_0265, + &pci_dev_info_10de_0266, + &pci_dev_info_10de_0267, + &pci_dev_info_10de_0268, + &pci_dev_info_10de_0269, + &pci_dev_info_10de_026a, + &pci_dev_info_10de_026b, + &pci_dev_info_10de_026c, + &pci_dev_info_10de_026d, + &pci_dev_info_10de_026e, + &pci_dev_info_10de_026f, + &pci_dev_info_10de_0270, + &pci_dev_info_10de_0271, + &pci_dev_info_10de_0272, + &pci_dev_info_10de_027e, + &pci_dev_info_10de_027f, + &pci_dev_info_10de_0280, + &pci_dev_info_10de_0281, + &pci_dev_info_10de_0282, + &pci_dev_info_10de_0286, + &pci_dev_info_10de_0288, + &pci_dev_info_10de_0289, + &pci_dev_info_10de_028c, + &pci_dev_info_10de_0290, + &pci_dev_info_10de_0291, + &pci_dev_info_10de_0292, + &pci_dev_info_10de_0298, + &pci_dev_info_10de_0299, + &pci_dev_info_10de_029a, + &pci_dev_info_10de_029b, + &pci_dev_info_10de_029c, + &pci_dev_info_10de_029d, + &pci_dev_info_10de_029e, + &pci_dev_info_10de_029f, + &pci_dev_info_10de_02a0, + &pci_dev_info_10de_02e1, + &pci_dev_info_10de_02f0, + &pci_dev_info_10de_02f1, + &pci_dev_info_10de_02f2, + &pci_dev_info_10de_02f3, + &pci_dev_info_10de_02f4, + &pci_dev_info_10de_02f5, + &pci_dev_info_10de_02f6, + &pci_dev_info_10de_02f7, + &pci_dev_info_10de_02f8, + &pci_dev_info_10de_02f9, + &pci_dev_info_10de_02fa, + &pci_dev_info_10de_02fb, + &pci_dev_info_10de_02fc, + &pci_dev_info_10de_02fd, + &pci_dev_info_10de_02fe, + &pci_dev_info_10de_02ff, + &pci_dev_info_10de_0300, + &pci_dev_info_10de_0301, + &pci_dev_info_10de_0302, + &pci_dev_info_10de_0308, + &pci_dev_info_10de_0309, + &pci_dev_info_10de_0311, + &pci_dev_info_10de_0312, + &pci_dev_info_10de_0313, + &pci_dev_info_10de_0314, + &pci_dev_info_10de_0316, + &pci_dev_info_10de_0317, + &pci_dev_info_10de_031a, + &pci_dev_info_10de_031b, + &pci_dev_info_10de_031c, + &pci_dev_info_10de_031d, + &pci_dev_info_10de_031e, + &pci_dev_info_10de_031f, + &pci_dev_info_10de_0320, + &pci_dev_info_10de_0321, + &pci_dev_info_10de_0322, + &pci_dev_info_10de_0323, + &pci_dev_info_10de_0324, + &pci_dev_info_10de_0325, + &pci_dev_info_10de_0326, + &pci_dev_info_10de_0327, + &pci_dev_info_10de_0328, + &pci_dev_info_10de_0329, + &pci_dev_info_10de_032a, + &pci_dev_info_10de_032b, + &pci_dev_info_10de_032c, + &pci_dev_info_10de_032d, + &pci_dev_info_10de_032f, + &pci_dev_info_10de_0330, + &pci_dev_info_10de_0331, + &pci_dev_info_10de_0332, + &pci_dev_info_10de_0333, + &pci_dev_info_10de_0334, + &pci_dev_info_10de_0338, + &pci_dev_info_10de_033f, + &pci_dev_info_10de_0341, + &pci_dev_info_10de_0342, + &pci_dev_info_10de_0343, + &pci_dev_info_10de_0344, + &pci_dev_info_10de_0345, + &pci_dev_info_10de_0347, + &pci_dev_info_10de_0348, + &pci_dev_info_10de_0349, + &pci_dev_info_10de_034b, + &pci_dev_info_10de_034c, + &pci_dev_info_10de_034e, + &pci_dev_info_10de_034f, + &pci_dev_info_10de_0360, + &pci_dev_info_10de_0361, + &pci_dev_info_10de_0362, + &pci_dev_info_10de_0363, + &pci_dev_info_10de_0364, + &pci_dev_info_10de_0365, + &pci_dev_info_10de_0366, + &pci_dev_info_10de_0367, + &pci_dev_info_10de_0368, + &pci_dev_info_10de_0369, + &pci_dev_info_10de_036a, + &pci_dev_info_10de_036b, + &pci_dev_info_10de_036c, + &pci_dev_info_10de_036d, + &pci_dev_info_10de_036e, + &pci_dev_info_10de_0370, + &pci_dev_info_10de_0371, + &pci_dev_info_10de_0372, + &pci_dev_info_10de_0373, + &pci_dev_info_10de_0374, + &pci_dev_info_10de_0375, + &pci_dev_info_10de_0376, + &pci_dev_info_10de_0377, + &pci_dev_info_10de_0378, + &pci_dev_info_10de_037a, + &pci_dev_info_10de_037e, + &pci_dev_info_10de_037f, + &pci_dev_info_10de_0391, + &pci_dev_info_10de_0392, + &pci_dev_info_10de_0393, + &pci_dev_info_10de_0398, + &pci_dev_info_10de_039e, + &pci_dev_info_10de_03a0, + &pci_dev_info_10de_03a1, + &pci_dev_info_10de_03a2, + &pci_dev_info_10de_03a3, + &pci_dev_info_10de_03a4, + &pci_dev_info_10de_03a5, + &pci_dev_info_10de_03a6, + &pci_dev_info_10de_03a7, + &pci_dev_info_10de_03a8, + &pci_dev_info_10de_03a9, + &pci_dev_info_10de_03aa, + &pci_dev_info_10de_03ab, + &pci_dev_info_10de_03ac, + &pci_dev_info_10de_03ad, + &pci_dev_info_10de_03ae, + &pci_dev_info_10de_03af, + &pci_dev_info_10de_03b0, + &pci_dev_info_10de_03b1, + &pci_dev_info_10de_03b2, + &pci_dev_info_10de_03b3, + &pci_dev_info_10de_03b4, + &pci_dev_info_10de_03b5, + &pci_dev_info_10de_03b6, + &pci_dev_info_10de_03b7, + &pci_dev_info_10de_03b8, + &pci_dev_info_10de_03b9, + &pci_dev_info_10de_03ba, + &pci_dev_info_10de_03bb, + &pci_dev_info_10de_03d0, + &pci_dev_info_10de_03d1, + &pci_dev_info_10de_03d2, + &pci_dev_info_10de_03d5, + &pci_dev_info_10de_03e0, + &pci_dev_info_10de_03e1, + &pci_dev_info_10de_03e2, + &pci_dev_info_10de_03e3, + &pci_dev_info_10de_03e4, + &pci_dev_info_10de_03e5, + &pci_dev_info_10de_03e6, + &pci_dev_info_10de_03e7, + &pci_dev_info_10de_03e8, + &pci_dev_info_10de_03e9, + &pci_dev_info_10de_03ea, + &pci_dev_info_10de_03eb, + &pci_dev_info_10de_03ec, + &pci_dev_info_10de_03ee, + &pci_dev_info_10de_03ef, + &pci_dev_info_10de_03f0, + &pci_dev_info_10de_03f1, + &pci_dev_info_10de_03f2, + &pci_dev_info_10de_03f3, + &pci_dev_info_10de_03f4, + &pci_dev_info_10de_03f5, + &pci_dev_info_10de_03f6, + &pci_dev_info_10de_03f7, + &pci_dev_info_10de_0440, + &pci_dev_info_10de_0441, + &pci_dev_info_10de_0442, + &pci_dev_info_10de_0443, + &pci_dev_info_10de_0444, + &pci_dev_info_10de_0445, + &pci_dev_info_10de_0446, + &pci_dev_info_10de_0447, + &pci_dev_info_10de_0448, + &pci_dev_info_10de_0449, + &pci_dev_info_10de_044a, + &pci_dev_info_10de_044b, + &pci_dev_info_10de_044c, + &pci_dev_info_10de_044d, + &pci_dev_info_10de_044e, + &pci_dev_info_10de_044f, + &pci_dev_info_10de_0450, + &pci_dev_info_10de_0451, + &pci_dev_info_10de_0452, + &pci_dev_info_10de_0453, + &pci_dev_info_10de_0454, + &pci_dev_info_10de_0455, + &pci_dev_info_10de_0456, + &pci_dev_info_10de_0457, + &pci_dev_info_10de_0458, + &pci_dev_info_10de_0459, + &pci_dev_info_10de_045a, + &pci_dev_info_10de_045c, + &pci_dev_info_10de_045d, + &pci_dev_info_10de_045e, + &pci_dev_info_10de_045f, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10df[] = { + &pci_dev_info_10df_1ae5, + &pci_dev_info_10df_f085, + &pci_dev_info_10df_f095, + &pci_dev_info_10df_f098, + &pci_dev_info_10df_f0a1, + &pci_dev_info_10df_f0a5, + &pci_dev_info_10df_f0b5, + &pci_dev_info_10df_f0d1, + &pci_dev_info_10df_f0d5, + &pci_dev_info_10df_f0e1, + &pci_dev_info_10df_f0e5, + &pci_dev_info_10df_f0f5, + &pci_dev_info_10df_f700, + &pci_dev_info_10df_f701, + &pci_dev_info_10df_f800, + &pci_dev_info_10df_f801, + &pci_dev_info_10df_f900, + &pci_dev_info_10df_f901, + &pci_dev_info_10df_f980, + &pci_dev_info_10df_f981, + &pci_dev_info_10df_f982, + &pci_dev_info_10df_fa00, + &pci_dev_info_10df_fb00, + &pci_dev_info_10df_fc00, + &pci_dev_info_10df_fc10, + &pci_dev_info_10df_fc20, + &pci_dev_info_10df_fd00, + &pci_dev_info_10df_fe00, + &pci_dev_info_10df_ff00, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_10e0[] = { + &pci_dev_info_10e0_5026, + &pci_dev_info_10e0_5027, + &pci_dev_info_10e0_5028, + &pci_dev_info_10e0_8849, + &pci_dev_info_10e0_8853, + &pci_dev_info_10e0_9128, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10e1[] = { + &pci_dev_info_10e1_0391, + &pci_dev_info_10e1_690c, + &pci_dev_info_10e1_dc29, + NULL +}; +#endif +#define pci_dev_list_10e2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10e3[] = { + &pci_dev_info_10e3_0000, + &pci_dev_info_10e3_0108, + &pci_dev_info_10e3_0148, + &pci_dev_info_10e3_0860, + &pci_dev_info_10e3_0862, + &pci_dev_info_10e3_8260, + &pci_dev_info_10e3_8261, + &pci_dev_info_10e3_a108, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10e4[] = { + &pci_dev_info_10e4_8029, + NULL +}; +#endif +#define pci_dev_list_10e5 NULL +#define pci_dev_list_10e6 NULL +#define pci_dev_list_10e7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10e8[] = { + &pci_dev_info_10e8_1072, + &pci_dev_info_10e8_2011, + &pci_dev_info_10e8_4750, + &pci_dev_info_10e8_5920, + &pci_dev_info_10e8_8043, + &pci_dev_info_10e8_8062, + &pci_dev_info_10e8_807d, + &pci_dev_info_10e8_8088, + &pci_dev_info_10e8_8089, + &pci_dev_info_10e8_809c, + &pci_dev_info_10e8_80d7, + &pci_dev_info_10e8_80d9, + &pci_dev_info_10e8_80da, + &pci_dev_info_10e8_811a, + &pci_dev_info_10e8_814c, + &pci_dev_info_10e8_8170, + &pci_dev_info_10e8_81e6, + &pci_dev_info_10e8_8291, + &pci_dev_info_10e8_82c4, + &pci_dev_info_10e8_82c5, + &pci_dev_info_10e8_82c6, + &pci_dev_info_10e8_82c7, + &pci_dev_info_10e8_82ca, + &pci_dev_info_10e8_82db, + &pci_dev_info_10e8_82e2, + &pci_dev_info_10e8_8851, + NULL +}; +#endif +#define pci_dev_list_10e9 NULL +static const pciDeviceInfo *pci_dev_list_10ea[] = { + &pci_dev_info_10ea_1680, + &pci_dev_info_10ea_1682, + &pci_dev_info_10ea_1683, + &pci_dev_info_10ea_2000, + &pci_dev_info_10ea_2010, + &pci_dev_info_10ea_5000, + &pci_dev_info_10ea_5050, + &pci_dev_info_10ea_5202, + &pci_dev_info_10ea_5252, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10eb[] = { + &pci_dev_info_10eb_0101, + &pci_dev_info_10eb_8111, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ec[] = { + &pci_dev_info_10ec_0139, + &pci_dev_info_10ec_0883, + &pci_dev_info_10ec_8029, + &pci_dev_info_10ec_8129, + &pci_dev_info_10ec_8136, + &pci_dev_info_10ec_8138, + &pci_dev_info_10ec_8139, + &pci_dev_info_10ec_8167, + &pci_dev_info_10ec_8168, + &pci_dev_info_10ec_8169, + &pci_dev_info_10ec_8180, + &pci_dev_info_10ec_8185, + &pci_dev_info_10ec_8197, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ed[] = { + &pci_dev_info_10ed_7310, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ee[] = { + &pci_dev_info_10ee_0205, + &pci_dev_info_10ee_0210, + &pci_dev_info_10ee_0314, + &pci_dev_info_10ee_0405, + &pci_dev_info_10ee_0410, + &pci_dev_info_10ee_3fc0, + &pci_dev_info_10ee_3fc1, + &pci_dev_info_10ee_3fc2, + &pci_dev_info_10ee_3fc3, + &pci_dev_info_10ee_3fc4, + &pci_dev_info_10ee_3fc5, + &pci_dev_info_10ee_3fc6, + &pci_dev_info_10ee_8381, + &pci_dev_info_10ee_d154, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10ef[] = { + &pci_dev_info_10ef_8154, + NULL +}; +#endif +#define pci_dev_list_10f0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10f1[] = { + &pci_dev_info_10f1_2865, + NULL +}; +#endif +#define pci_dev_list_10f2 NULL +#define pci_dev_list_10f3 NULL +#define pci_dev_list_10f4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10f5[] = { + &pci_dev_info_10f5_a001, + NULL +}; +#endif +#define pci_dev_list_10f6 NULL +#define pci_dev_list_10f7 NULL +#define pci_dev_list_10f8 NULL +#define pci_dev_list_10f9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10fa[] = { + &pci_dev_info_10fa_000c, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10fb[] = { + &pci_dev_info_10fb_186f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_10fc[] = { + &pci_dev_info_10fc_0003, + &pci_dev_info_10fc_0005, + NULL +}; +#endif +#define pci_dev_list_10fd NULL +#define pci_dev_list_10fe NULL +#define pci_dev_list_10ff NULL +#define pci_dev_list_1100 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1101[] = { + &pci_dev_info_1101_1060, + &pci_dev_info_1101_1622, + &pci_dev_info_1101_9100, + &pci_dev_info_1101_9400, + &pci_dev_info_1101_9401, + &pci_dev_info_1101_9500, + &pci_dev_info_1101_9502, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1102[] = { + &pci_dev_info_1102_0002, + &pci_dev_info_1102_0004, + &pci_dev_info_1102_0005, + &pci_dev_info_1102_0006, + &pci_dev_info_1102_0007, + &pci_dev_info_1102_0008, + &pci_dev_info_1102_4001, + &pci_dev_info_1102_7002, + &pci_dev_info_1102_7003, + &pci_dev_info_1102_7004, + &pci_dev_info_1102_7005, + &pci_dev_info_1102_8064, + &pci_dev_info_1102_8938, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1103[] = { + &pci_dev_info_1103_0003, + &pci_dev_info_1103_0004, + &pci_dev_info_1103_0005, + &pci_dev_info_1103_0006, + &pci_dev_info_1103_0007, + &pci_dev_info_1103_0008, + &pci_dev_info_1103_0009, + NULL +}; +#endif +#define pci_dev_list_1104 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1105[] = { + &pci_dev_info_1105_1105, + &pci_dev_info_1105_8300, + &pci_dev_info_1105_8400, + &pci_dev_info_1105_8401, + &pci_dev_info_1105_8470, + &pci_dev_info_1105_8471, + &pci_dev_info_1105_8475, + &pci_dev_info_1105_8476, + &pci_dev_info_1105_8485, + &pci_dev_info_1105_8486, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1106[] = { + &pci_dev_info_1106_0102, + &pci_dev_info_1106_0130, + &pci_dev_info_1106_0204, + &pci_dev_info_1106_0208, + &pci_dev_info_1106_0238, + &pci_dev_info_1106_0258, + &pci_dev_info_1106_0259, + &pci_dev_info_1106_0269, + &pci_dev_info_1106_0282, + &pci_dev_info_1106_0290, + &pci_dev_info_1106_0293, + &pci_dev_info_1106_0296, + &pci_dev_info_1106_0305, + &pci_dev_info_1106_0308, + &pci_dev_info_1106_0314, + &pci_dev_info_1106_0324, + &pci_dev_info_1106_0327, + &pci_dev_info_1106_0336, + &pci_dev_info_1106_0340, + &pci_dev_info_1106_0351, + &pci_dev_info_1106_0364, + &pci_dev_info_1106_0391, + &pci_dev_info_1106_0501, + &pci_dev_info_1106_0505, + &pci_dev_info_1106_0561, + &pci_dev_info_1106_0571, + &pci_dev_info_1106_0576, + &pci_dev_info_1106_0585, + &pci_dev_info_1106_0586, + &pci_dev_info_1106_0591, + &pci_dev_info_1106_0595, + &pci_dev_info_1106_0596, + &pci_dev_info_1106_0597, + &pci_dev_info_1106_0598, + &pci_dev_info_1106_0601, + &pci_dev_info_1106_0605, + &pci_dev_info_1106_0680, + &pci_dev_info_1106_0686, + &pci_dev_info_1106_0691, + &pci_dev_info_1106_0693, + &pci_dev_info_1106_0698, + &pci_dev_info_1106_0926, + &pci_dev_info_1106_1000, + &pci_dev_info_1106_1106, + &pci_dev_info_1106_1204, + &pci_dev_info_1106_1208, + &pci_dev_info_1106_1238, + &pci_dev_info_1106_1258, + &pci_dev_info_1106_1259, + &pci_dev_info_1106_1269, + &pci_dev_info_1106_1282, + &pci_dev_info_1106_1290, + &pci_dev_info_1106_1293, + &pci_dev_info_1106_1296, + &pci_dev_info_1106_1308, + &pci_dev_info_1106_1314, + &pci_dev_info_1106_1324, + &pci_dev_info_1106_1327, + &pci_dev_info_1106_1336, + &pci_dev_info_1106_1340, + &pci_dev_info_1106_1351, + &pci_dev_info_1106_1364, + &pci_dev_info_1106_1571, + &pci_dev_info_1106_1595, + &pci_dev_info_1106_2204, + &pci_dev_info_1106_2208, + &pci_dev_info_1106_2238, + &pci_dev_info_1106_2258, + &pci_dev_info_1106_2259, + &pci_dev_info_1106_2269, + &pci_dev_info_1106_2282, + &pci_dev_info_1106_2290, + &pci_dev_info_1106_2293, + &pci_dev_info_1106_2296, + &pci_dev_info_1106_2308, + &pci_dev_info_1106_2314, + &pci_dev_info_1106_2324, + &pci_dev_info_1106_2327, + &pci_dev_info_1106_2336, + &pci_dev_info_1106_2340, + &pci_dev_info_1106_2351, + &pci_dev_info_1106_2364, + &pci_dev_info_1106_287a, + &pci_dev_info_1106_287b, + &pci_dev_info_1106_287c, + &pci_dev_info_1106_287d, + &pci_dev_info_1106_287e, + &pci_dev_info_1106_3022, + &pci_dev_info_1106_3038, + &pci_dev_info_1106_3040, + &pci_dev_info_1106_3043, + &pci_dev_info_1106_3044, + &pci_dev_info_1106_3050, + &pci_dev_info_1106_3051, + &pci_dev_info_1106_3053, + &pci_dev_info_1106_3057, + &pci_dev_info_1106_3058, + &pci_dev_info_1106_3059, + &pci_dev_info_1106_3065, + &pci_dev_info_1106_3068, + &pci_dev_info_1106_3074, + &pci_dev_info_1106_3091, + &pci_dev_info_1106_3099, + &pci_dev_info_1106_3101, + &pci_dev_info_1106_3102, + &pci_dev_info_1106_3103, + &pci_dev_info_1106_3104, + &pci_dev_info_1106_3106, + &pci_dev_info_1106_3108, + &pci_dev_info_1106_3109, + &pci_dev_info_1106_3112, + &pci_dev_info_1106_3113, + &pci_dev_info_1106_3116, + &pci_dev_info_1106_3118, + &pci_dev_info_1106_3119, + &pci_dev_info_1106_3122, + &pci_dev_info_1106_3123, + &pci_dev_info_1106_3128, + &pci_dev_info_1106_3133, + &pci_dev_info_1106_3147, + &pci_dev_info_1106_3148, + &pci_dev_info_1106_3149, + &pci_dev_info_1106_3156, + &pci_dev_info_1106_3164, + &pci_dev_info_1106_3168, + &pci_dev_info_1106_3177, + &pci_dev_info_1106_3178, + &pci_dev_info_1106_3188, + &pci_dev_info_1106_3189, + &pci_dev_info_1106_3204, + &pci_dev_info_1106_3205, + &pci_dev_info_1106_3208, + &pci_dev_info_1106_3213, + &pci_dev_info_1106_3218, + &pci_dev_info_1106_3227, + &pci_dev_info_1106_3238, + &pci_dev_info_1106_3249, + &pci_dev_info_1106_324a, + &pci_dev_info_1106_324b, + &pci_dev_info_1106_324e, + &pci_dev_info_1106_3258, + &pci_dev_info_1106_3259, + &pci_dev_info_1106_3269, + &pci_dev_info_1106_3282, + &pci_dev_info_1106_3287, + &pci_dev_info_1106_3288, + &pci_dev_info_1106_3290, + &pci_dev_info_1106_3296, + &pci_dev_info_1106_3324, + &pci_dev_info_1106_3327, + &pci_dev_info_1106_3336, + &pci_dev_info_1106_3337, + &pci_dev_info_1106_3340, + &pci_dev_info_1106_3344, + &pci_dev_info_1106_3349, + &pci_dev_info_1106_3351, + &pci_dev_info_1106_3364, + &pci_dev_info_1106_337a, + &pci_dev_info_1106_337b, + &pci_dev_info_1106_4149, + &pci_dev_info_1106_4204, + &pci_dev_info_1106_4208, + &pci_dev_info_1106_4238, + &pci_dev_info_1106_4258, + &pci_dev_info_1106_4259, + &pci_dev_info_1106_4269, + &pci_dev_info_1106_4282, + &pci_dev_info_1106_4290, + &pci_dev_info_1106_4293, + &pci_dev_info_1106_4296, + &pci_dev_info_1106_4308, + &pci_dev_info_1106_4314, + &pci_dev_info_1106_4324, + &pci_dev_info_1106_4327, + &pci_dev_info_1106_4336, + &pci_dev_info_1106_4340, + &pci_dev_info_1106_4351, + &pci_dev_info_1106_4364, + &pci_dev_info_1106_5030, + &pci_dev_info_1106_5208, + &pci_dev_info_1106_5238, + &pci_dev_info_1106_5290, + &pci_dev_info_1106_5308, + &pci_dev_info_1106_5327, + &pci_dev_info_1106_5336, + &pci_dev_info_1106_5340, + &pci_dev_info_1106_5351, + &pci_dev_info_1106_5364, + &pci_dev_info_1106_6100, + &pci_dev_info_1106_6327, + &pci_dev_info_1106_7204, + &pci_dev_info_1106_7205, + &pci_dev_info_1106_7208, + &pci_dev_info_1106_7238, + &pci_dev_info_1106_7258, + &pci_dev_info_1106_7259, + &pci_dev_info_1106_7269, + &pci_dev_info_1106_7282, + &pci_dev_info_1106_7290, + &pci_dev_info_1106_7293, + &pci_dev_info_1106_7296, + &pci_dev_info_1106_7308, + &pci_dev_info_1106_7314, + &pci_dev_info_1106_7324, + &pci_dev_info_1106_7327, + &pci_dev_info_1106_7336, + &pci_dev_info_1106_7340, + &pci_dev_info_1106_7351, + &pci_dev_info_1106_7364, + &pci_dev_info_1106_8231, + &pci_dev_info_1106_8235, + &pci_dev_info_1106_8305, + &pci_dev_info_1106_8324, + &pci_dev_info_1106_8391, + &pci_dev_info_1106_8501, + &pci_dev_info_1106_8596, + &pci_dev_info_1106_8597, + &pci_dev_info_1106_8598, + &pci_dev_info_1106_8601, + &pci_dev_info_1106_8605, + &pci_dev_info_1106_8691, + &pci_dev_info_1106_8693, + &pci_dev_info_1106_a208, + &pci_dev_info_1106_a238, + &pci_dev_info_1106_a327, + &pci_dev_info_1106_a364, + &pci_dev_info_1106_b091, + &pci_dev_info_1106_b099, + &pci_dev_info_1106_b101, + &pci_dev_info_1106_b102, + &pci_dev_info_1106_b103, + &pci_dev_info_1106_b112, + &pci_dev_info_1106_b113, + &pci_dev_info_1106_b115, + &pci_dev_info_1106_b168, + &pci_dev_info_1106_b188, + &pci_dev_info_1106_b198, + &pci_dev_info_1106_b213, + &pci_dev_info_1106_b999, + &pci_dev_info_1106_c208, + &pci_dev_info_1106_c238, + &pci_dev_info_1106_c327, + &pci_dev_info_1106_c340, + &pci_dev_info_1106_c364, + &pci_dev_info_1106_d104, + &pci_dev_info_1106_d208, + &pci_dev_info_1106_d213, + &pci_dev_info_1106_d238, + &pci_dev_info_1106_d340, + &pci_dev_info_1106_e208, + &pci_dev_info_1106_e238, + &pci_dev_info_1106_e340, + &pci_dev_info_1106_f208, + &pci_dev_info_1106_f238, + &pci_dev_info_1106_f340, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1107[] = { + &pci_dev_info_1107_0576, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1108[] = { + &pci_dev_info_1108_0100, + &pci_dev_info_1108_0101, + &pci_dev_info_1108_0105, + &pci_dev_info_1108_0108, + &pci_dev_info_1108_0138, + &pci_dev_info_1108_0139, + &pci_dev_info_1108_013c, + &pci_dev_info_1108_013d, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1109[] = { + &pci_dev_info_1109_1400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_110a[] = { + &pci_dev_info_110a_0002, + &pci_dev_info_110a_0005, + &pci_dev_info_110a_0006, + &pci_dev_info_110a_0015, + &pci_dev_info_110a_001d, + &pci_dev_info_110a_007b, + &pci_dev_info_110a_007c, + &pci_dev_info_110a_007d, + &pci_dev_info_110a_2101, + &pci_dev_info_110a_2102, + &pci_dev_info_110a_2104, + &pci_dev_info_110a_3142, + &pci_dev_info_110a_4021, + &pci_dev_info_110a_4029, + &pci_dev_info_110a_4942, + &pci_dev_info_110a_6120, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_110b[] = { + &pci_dev_info_110b_0001, + &pci_dev_info_110b_0004, + NULL +}; +#endif +#define pci_dev_list_110c NULL +#define pci_dev_list_110d NULL +#define pci_dev_list_110e NULL +#define pci_dev_list_110f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1110[] = { + &pci_dev_info_1110_6037, + &pci_dev_info_1110_6073, + NULL +}; +#endif +#define pci_dev_list_1111 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1112[] = { + &pci_dev_info_1112_2200, + &pci_dev_info_1112_2300, + &pci_dev_info_1112_2340, + &pci_dev_info_1112_2400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1113[] = { + &pci_dev_info_1113_1211, + &pci_dev_info_1113_1216, + &pci_dev_info_1113_1217, + &pci_dev_info_1113_5105, + &pci_dev_info_1113_9211, + &pci_dev_info_1113_9511, + &pci_dev_info_1113_d301, + &pci_dev_info_1113_ec02, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1114[] = { + &pci_dev_info_1114_0506, + NULL +}; +#endif +#define pci_dev_list_1115 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1116[] = { + &pci_dev_info_1116_0022, + &pci_dev_info_1116_0023, + &pci_dev_info_1116_0024, + &pci_dev_info_1116_0025, + &pci_dev_info_1116_0026, + &pci_dev_info_1116_0027, + &pci_dev_info_1116_0028, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1117[] = { + &pci_dev_info_1117_9500, + &pci_dev_info_1117_9501, + NULL +}; +#endif +#define pci_dev_list_1118 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1119[] = { + &pci_dev_info_1119_0000, + &pci_dev_info_1119_0001, + &pci_dev_info_1119_0002, + &pci_dev_info_1119_0003, + &pci_dev_info_1119_0004, + &pci_dev_info_1119_0005, + &pci_dev_info_1119_0006, + &pci_dev_info_1119_0007, + &pci_dev_info_1119_0008, + &pci_dev_info_1119_0009, + &pci_dev_info_1119_000a, + &pci_dev_info_1119_000b, + &pci_dev_info_1119_000c, + &pci_dev_info_1119_000d, + &pci_dev_info_1119_0010, + &pci_dev_info_1119_0011, + &pci_dev_info_1119_0012, + &pci_dev_info_1119_0013, + &pci_dev_info_1119_0100, + &pci_dev_info_1119_0101, + &pci_dev_info_1119_0102, + &pci_dev_info_1119_0103, + &pci_dev_info_1119_0104, + &pci_dev_info_1119_0105, + &pci_dev_info_1119_0110, + &pci_dev_info_1119_0111, + &pci_dev_info_1119_0112, + &pci_dev_info_1119_0113, + &pci_dev_info_1119_0114, + &pci_dev_info_1119_0115, + &pci_dev_info_1119_0118, + &pci_dev_info_1119_0119, + &pci_dev_info_1119_011a, + &pci_dev_info_1119_011b, + &pci_dev_info_1119_0120, + &pci_dev_info_1119_0121, + &pci_dev_info_1119_0122, + &pci_dev_info_1119_0123, + &pci_dev_info_1119_0124, + &pci_dev_info_1119_0125, + &pci_dev_info_1119_0136, + &pci_dev_info_1119_0137, + &pci_dev_info_1119_0138, + &pci_dev_info_1119_0139, + &pci_dev_info_1119_013a, + &pci_dev_info_1119_013b, + &pci_dev_info_1119_013c, + &pci_dev_info_1119_013d, + &pci_dev_info_1119_013e, + &pci_dev_info_1119_013f, + &pci_dev_info_1119_0166, + &pci_dev_info_1119_0167, + &pci_dev_info_1119_0168, + &pci_dev_info_1119_0169, + &pci_dev_info_1119_016a, + &pci_dev_info_1119_016b, + &pci_dev_info_1119_016c, + &pci_dev_info_1119_016d, + &pci_dev_info_1119_016e, + &pci_dev_info_1119_016f, + &pci_dev_info_1119_01d6, + &pci_dev_info_1119_01d7, + &pci_dev_info_1119_01f6, + &pci_dev_info_1119_01f7, + &pci_dev_info_1119_01fc, + &pci_dev_info_1119_01fd, + &pci_dev_info_1119_01fe, + &pci_dev_info_1119_01ff, + &pci_dev_info_1119_0210, + &pci_dev_info_1119_0211, + &pci_dev_info_1119_0260, + &pci_dev_info_1119_0261, + &pci_dev_info_1119_02ff, + &pci_dev_info_1119_0300, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_111a[] = { + &pci_dev_info_111a_0000, + &pci_dev_info_111a_0002, + &pci_dev_info_111a_0003, + &pci_dev_info_111a_0005, + &pci_dev_info_111a_0007, + &pci_dev_info_111a_1203, + NULL +}; +#endif +#define pci_dev_list_111b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_111c[] = { + &pci_dev_info_111c_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_111d[] = { + &pci_dev_info_111d_0001, + &pci_dev_info_111d_0003, + &pci_dev_info_111d_0004, + &pci_dev_info_111d_0005, + NULL +}; +#endif +#define pci_dev_list_111e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_111f[] = { + &pci_dev_info_111f_4a47, + &pci_dev_info_111f_5243, + NULL +}; +#endif +#define pci_dev_list_1120 NULL +#define pci_dev_list_1121 NULL +#define pci_dev_list_1122 NULL +#define pci_dev_list_1123 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1124[] = { + &pci_dev_info_1124_2581, + NULL +}; +#endif +#define pci_dev_list_1125 NULL +#define pci_dev_list_1126 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1127[] = { + &pci_dev_info_1127_0200, + &pci_dev_info_1127_0210, + &pci_dev_info_1127_0250, + &pci_dev_info_1127_0300, + &pci_dev_info_1127_0310, + &pci_dev_info_1127_0400, + NULL +}; +#endif +#define pci_dev_list_1129 NULL +#define pci_dev_list_112a NULL +#define pci_dev_list_112b NULL +#define pci_dev_list_112c NULL +#define pci_dev_list_112d NULL +#define pci_dev_list_112e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_112f[] = { + &pci_dev_info_112f_0000, + &pci_dev_info_112f_0001, + &pci_dev_info_112f_0008, + NULL +}; +#endif +#define pci_dev_list_1130 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1131[] = { + &pci_dev_info_1131_1561, + &pci_dev_info_1131_1562, + &pci_dev_info_1131_3400, + &pci_dev_info_1131_5400, + &pci_dev_info_1131_5402, + &pci_dev_info_1131_5405, + &pci_dev_info_1131_5406, + &pci_dev_info_1131_7130, + &pci_dev_info_1131_7133, + &pci_dev_info_1131_7134, + &pci_dev_info_1131_7145, + &pci_dev_info_1131_7146, + &pci_dev_info_1131_9730, + NULL +}; +#endif +#define pci_dev_list_1132 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1133[] = { + &pci_dev_info_1133_7901, + &pci_dev_info_1133_7902, + &pci_dev_info_1133_7911, + &pci_dev_info_1133_7912, + &pci_dev_info_1133_7941, + &pci_dev_info_1133_7942, + &pci_dev_info_1133_7943, + &pci_dev_info_1133_7944, + &pci_dev_info_1133_b921, + &pci_dev_info_1133_b922, + &pci_dev_info_1133_b923, + &pci_dev_info_1133_e001, + &pci_dev_info_1133_e002, + &pci_dev_info_1133_e003, + &pci_dev_info_1133_e004, + &pci_dev_info_1133_e005, + &pci_dev_info_1133_e006, + &pci_dev_info_1133_e007, + &pci_dev_info_1133_e008, + &pci_dev_info_1133_e009, + &pci_dev_info_1133_e00a, + &pci_dev_info_1133_e00b, + &pci_dev_info_1133_e00c, + &pci_dev_info_1133_e00d, + &pci_dev_info_1133_e00e, + &pci_dev_info_1133_e010, + &pci_dev_info_1133_e011, + &pci_dev_info_1133_e012, + &pci_dev_info_1133_e013, + &pci_dev_info_1133_e014, + &pci_dev_info_1133_e015, + &pci_dev_info_1133_e016, + &pci_dev_info_1133_e017, + &pci_dev_info_1133_e018, + &pci_dev_info_1133_e019, + &pci_dev_info_1133_e01a, + &pci_dev_info_1133_e01b, + &pci_dev_info_1133_e01c, + &pci_dev_info_1133_e01e, + &pci_dev_info_1133_e020, + &pci_dev_info_1133_e022, + &pci_dev_info_1133_e024, + &pci_dev_info_1133_e028, + &pci_dev_info_1133_e02a, + &pci_dev_info_1133_e02c, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1134[] = { + &pci_dev_info_1134_0001, + &pci_dev_info_1134_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1135[] = { + &pci_dev_info_1135_0001, + NULL +}; +#endif +#define pci_dev_list_1136 NULL +#define pci_dev_list_1137 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1138[] = { + &pci_dev_info_1138_8905, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1139[] = { + &pci_dev_info_1139_0001, + NULL +}; +#endif +#define pci_dev_list_113a NULL +#define pci_dev_list_113b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_113c[] = { + &pci_dev_info_113c_0000, + &pci_dev_info_113c_0001, + &pci_dev_info_113c_0911, + &pci_dev_info_113c_0912, + &pci_dev_info_113c_0913, + &pci_dev_info_113c_0914, + NULL +}; +#endif +#define pci_dev_list_113d NULL +#define pci_dev_list_113e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_113f[] = { + &pci_dev_info_113f_0808, + &pci_dev_info_113f_1010, + &pci_dev_info_113f_80c0, + &pci_dev_info_113f_80c4, + &pci_dev_info_113f_80c8, + &pci_dev_info_113f_8888, + &pci_dev_info_113f_9090, + NULL +}; +#endif +#define pci_dev_list_1140 NULL +#define pci_dev_list_1141 NULL +static const pciDeviceInfo *pci_dev_list_1142[] = { + &pci_dev_info_1142_3210, + &pci_dev_info_1142_6422, + &pci_dev_info_1142_6424, + &pci_dev_info_1142_6425, + &pci_dev_info_1142_643d, + NULL +}; +#define pci_dev_list_1143 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1144[] = { + &pci_dev_info_1144_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1145[] = { + &pci_dev_info_1145_8007, + &pci_dev_info_1145_f007, + &pci_dev_info_1145_f010, + &pci_dev_info_1145_f012, + &pci_dev_info_1145_f013, + &pci_dev_info_1145_f015, + &pci_dev_info_1145_f020, + NULL +}; +#endif +#define pci_dev_list_1146 NULL +#define pci_dev_list_1147 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1148[] = { + &pci_dev_info_1148_4000, + &pci_dev_info_1148_4200, + &pci_dev_info_1148_4300, + &pci_dev_info_1148_4320, + &pci_dev_info_1148_4400, + &pci_dev_info_1148_4500, + &pci_dev_info_1148_9000, + &pci_dev_info_1148_9843, + &pci_dev_info_1148_9e00, + NULL +}; +#endif +#define pci_dev_list_1149 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_114a[] = { + &pci_dev_info_114a_5579, + &pci_dev_info_114a_5587, + &pci_dev_info_114a_6504, + &pci_dev_info_114a_7587, + NULL +}; +#endif +#define pci_dev_list_114b NULL +#define pci_dev_list_114c NULL +#define pci_dev_list_114d NULL +#define pci_dev_list_114e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_114f[] = { + &pci_dev_info_114f_0002, + &pci_dev_info_114f_0003, + &pci_dev_info_114f_0004, + &pci_dev_info_114f_0005, + &pci_dev_info_114f_0006, + &pci_dev_info_114f_0009, + &pci_dev_info_114f_000a, + &pci_dev_info_114f_000c, + &pci_dev_info_114f_000d, + &pci_dev_info_114f_0011, + &pci_dev_info_114f_0012, + &pci_dev_info_114f_0014, + &pci_dev_info_114f_0015, + &pci_dev_info_114f_0016, + &pci_dev_info_114f_0017, + &pci_dev_info_114f_001a, + &pci_dev_info_114f_001b, + &pci_dev_info_114f_001d, + &pci_dev_info_114f_0023, + &pci_dev_info_114f_0024, + &pci_dev_info_114f_0026, + &pci_dev_info_114f_0027, + &pci_dev_info_114f_0028, + &pci_dev_info_114f_0029, + &pci_dev_info_114f_0034, + &pci_dev_info_114f_0035, + &pci_dev_info_114f_0040, + &pci_dev_info_114f_0042, + &pci_dev_info_114f_0043, + &pci_dev_info_114f_0044, + &pci_dev_info_114f_0045, + &pci_dev_info_114f_004e, + &pci_dev_info_114f_0070, + &pci_dev_info_114f_0071, + &pci_dev_info_114f_0072, + &pci_dev_info_114f_0073, + &pci_dev_info_114f_00b0, + &pci_dev_info_114f_00b1, + &pci_dev_info_114f_00c8, + &pci_dev_info_114f_00c9, + &pci_dev_info_114f_00ca, + &pci_dev_info_114f_00cb, + &pci_dev_info_114f_00d0, + &pci_dev_info_114f_00d1, + &pci_dev_info_114f_6001, + NULL +}; +#endif +#define pci_dev_list_1150 NULL +#define pci_dev_list_1151 NULL +#define pci_dev_list_1152 NULL +#define pci_dev_list_1153 NULL +#define pci_dev_list_1154 NULL +#define pci_dev_list_1155 NULL +#define pci_dev_list_1156 NULL +#define pci_dev_list_1157 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1158[] = { + &pci_dev_info_1158_3011, + &pci_dev_info_1158_9050, + &pci_dev_info_1158_9051, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1159[] = { + &pci_dev_info_1159_0001, + NULL +}; +#endif +#define pci_dev_list_115a NULL +#define pci_dev_list_115b NULL +#define pci_dev_list_115c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_115d[] = { + &pci_dev_info_115d_0003, + &pci_dev_info_115d_0005, + &pci_dev_info_115d_0007, + &pci_dev_info_115d_000b, + &pci_dev_info_115d_000c, + &pci_dev_info_115d_000f, + &pci_dev_info_115d_00d4, + &pci_dev_info_115d_0101, + &pci_dev_info_115d_0103, + NULL +}; +#endif +#define pci_dev_list_115e NULL +#define pci_dev_list_115f NULL +#define pci_dev_list_1160 NULL +#define pci_dev_list_1161 NULL +#define pci_dev_list_1162 NULL +static const pciDeviceInfo *pci_dev_list_1163[] = { + &pci_dev_info_1163_0001, + &pci_dev_info_1163_2000, + NULL +}; +#define pci_dev_list_1164 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1165[] = { + &pci_dev_info_1165_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1166[] = { + &pci_dev_info_1166_0000, + &pci_dev_info_1166_0005, + &pci_dev_info_1166_0006, + &pci_dev_info_1166_0007, + &pci_dev_info_1166_0008, + &pci_dev_info_1166_0009, + &pci_dev_info_1166_0010, + &pci_dev_info_1166_0011, + &pci_dev_info_1166_0012, + &pci_dev_info_1166_0013, + &pci_dev_info_1166_0014, + &pci_dev_info_1166_0015, + &pci_dev_info_1166_0016, + &pci_dev_info_1166_0017, + &pci_dev_info_1166_0036, + &pci_dev_info_1166_0101, + &pci_dev_info_1166_0103, + &pci_dev_info_1166_0104, + &pci_dev_info_1166_0110, + &pci_dev_info_1166_0130, + &pci_dev_info_1166_0132, + &pci_dev_info_1166_0140, + &pci_dev_info_1166_0141, + &pci_dev_info_1166_0142, + &pci_dev_info_1166_0200, + &pci_dev_info_1166_0201, + &pci_dev_info_1166_0203, + &pci_dev_info_1166_0205, + &pci_dev_info_1166_0211, + &pci_dev_info_1166_0212, + &pci_dev_info_1166_0213, + &pci_dev_info_1166_0214, + &pci_dev_info_1166_0217, + &pci_dev_info_1166_0220, + &pci_dev_info_1166_0221, + &pci_dev_info_1166_0223, + &pci_dev_info_1166_0225, + &pci_dev_info_1166_0227, + &pci_dev_info_1166_0230, + &pci_dev_info_1166_0234, + &pci_dev_info_1166_0240, + &pci_dev_info_1166_0241, + &pci_dev_info_1166_0242, + &pci_dev_info_1166_024a, + &pci_dev_info_1166_024b, + NULL +}; +#endif +#define pci_dev_list_1167 NULL +#define pci_dev_list_1168 NULL +#define pci_dev_list_1169 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_116a[] = { + &pci_dev_info_116a_6100, + &pci_dev_info_116a_6800, + &pci_dev_info_116a_7100, + &pci_dev_info_116a_7800, + NULL +}; +#endif +#define pci_dev_list_116b NULL +#define pci_dev_list_116c NULL +#define pci_dev_list_116d NULL +#define pci_dev_list_116e NULL +#define pci_dev_list_116f NULL +#define pci_dev_list_1170 NULL +#define pci_dev_list_1171 NULL +#define pci_dev_list_1172 NULL +#define pci_dev_list_1173 NULL +#define pci_dev_list_1174 NULL +#define pci_dev_list_1175 NULL +#define pci_dev_list_1176 NULL +#define pci_dev_list_1177 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1178[] = { + &pci_dev_info_1178_afa1, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1179[] = { + &pci_dev_info_1179_0102, + &pci_dev_info_1179_0103, + &pci_dev_info_1179_0404, + &pci_dev_info_1179_0406, + &pci_dev_info_1179_0407, + &pci_dev_info_1179_0601, + &pci_dev_info_1179_0603, + &pci_dev_info_1179_060a, + &pci_dev_info_1179_060f, + &pci_dev_info_1179_0617, + &pci_dev_info_1179_0618, + &pci_dev_info_1179_0701, + &pci_dev_info_1179_0804, + &pci_dev_info_1179_0805, + &pci_dev_info_1179_0d01, + NULL +}; +#endif +#define pci_dev_list_117a NULL +#define pci_dev_list_117b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_117c[] = { + &pci_dev_info_117c_0030, + NULL +}; +#endif +#define pci_dev_list_117d NULL +#define pci_dev_list_117e NULL +#define pci_dev_list_117f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1180[] = { + &pci_dev_info_1180_0465, + &pci_dev_info_1180_0466, + &pci_dev_info_1180_0475, + &pci_dev_info_1180_0476, + &pci_dev_info_1180_0477, + &pci_dev_info_1180_0478, + &pci_dev_info_1180_0511, + &pci_dev_info_1180_0522, + &pci_dev_info_1180_0551, + &pci_dev_info_1180_0552, + &pci_dev_info_1180_0554, + &pci_dev_info_1180_0575, + &pci_dev_info_1180_0576, + &pci_dev_info_1180_0592, + &pci_dev_info_1180_0811, + &pci_dev_info_1180_0822, + &pci_dev_info_1180_0841, + &pci_dev_info_1180_0852, + NULL +}; +#endif +#define pci_dev_list_1181 NULL +#define pci_dev_list_1183 NULL +#define pci_dev_list_1184 NULL +#define pci_dev_list_1185 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1186[] = { + &pci_dev_info_1186_0100, + &pci_dev_info_1186_1002, + &pci_dev_info_1186_1025, + &pci_dev_info_1186_1026, + &pci_dev_info_1186_1043, + &pci_dev_info_1186_1300, + &pci_dev_info_1186_1340, + &pci_dev_info_1186_1405, + &pci_dev_info_1186_1541, + &pci_dev_info_1186_1561, + &pci_dev_info_1186_2027, + &pci_dev_info_1186_3203, + &pci_dev_info_1186_3300, + &pci_dev_info_1186_3a03, + &pci_dev_info_1186_3a04, + &pci_dev_info_1186_3a05, + &pci_dev_info_1186_3a07, + &pci_dev_info_1186_3a08, + &pci_dev_info_1186_3a10, + &pci_dev_info_1186_3a11, + &pci_dev_info_1186_3a12, + &pci_dev_info_1186_3a13, + &pci_dev_info_1186_3a14, + &pci_dev_info_1186_3a63, + &pci_dev_info_1186_4000, + &pci_dev_info_1186_4300, + &pci_dev_info_1186_4800, + &pci_dev_info_1186_4b01, + &pci_dev_info_1186_4c00, + &pci_dev_info_1186_8400, + NULL +}; +#endif +#define pci_dev_list_1187 NULL +#define pci_dev_list_1188 NULL +#define pci_dev_list_1189 NULL +#define pci_dev_list_118a NULL +#define pci_dev_list_118b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_118c[] = { + &pci_dev_info_118c_0014, + &pci_dev_info_118c_1117, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_118d[] = { + &pci_dev_info_118d_0001, + &pci_dev_info_118d_0012, + &pci_dev_info_118d_0014, + &pci_dev_info_118d_0024, + &pci_dev_info_118d_0044, + &pci_dev_info_118d_0112, + &pci_dev_info_118d_0114, + &pci_dev_info_118d_0124, + &pci_dev_info_118d_0144, + &pci_dev_info_118d_0212, + &pci_dev_info_118d_0214, + &pci_dev_info_118d_0224, + &pci_dev_info_118d_0244, + &pci_dev_info_118d_0312, + &pci_dev_info_118d_0314, + &pci_dev_info_118d_0324, + &pci_dev_info_118d_0344, + NULL +}; +#endif +#define pci_dev_list_118e NULL +#define pci_dev_list_118f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1190[] = { + &pci_dev_info_1190_c731, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1191[] = { + &pci_dev_info_1191_0003, + &pci_dev_info_1191_0004, + &pci_dev_info_1191_0005, + &pci_dev_info_1191_0006, + &pci_dev_info_1191_0007, + &pci_dev_info_1191_0008, + &pci_dev_info_1191_0009, + &pci_dev_info_1191_8002, + &pci_dev_info_1191_8010, + &pci_dev_info_1191_8020, + &pci_dev_info_1191_8030, + &pci_dev_info_1191_8040, + &pci_dev_info_1191_8050, + &pci_dev_info_1191_8060, + &pci_dev_info_1191_8080, + &pci_dev_info_1191_8081, + &pci_dev_info_1191_808a, + NULL +}; +#endif +#define pci_dev_list_1192 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1193[] = { + &pci_dev_info_1193_0001, + &pci_dev_info_1193_0002, + NULL +}; +#endif +#define pci_dev_list_1194 NULL +#define pci_dev_list_1195 NULL +#define pci_dev_list_1196 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1197[] = { + &pci_dev_info_1197_010c, + NULL +}; +#endif +#define pci_dev_list_1198 NULL +#define pci_dev_list_1199 NULL +#define pci_dev_list_119a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_119b[] = { + &pci_dev_info_119b_1221, + NULL +}; +#endif +#define pci_dev_list_119c NULL +#define pci_dev_list_119d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_119e[] = { + &pci_dev_info_119e_0001, + &pci_dev_info_119e_0003, + NULL +}; +#endif +#define pci_dev_list_119f NULL +#define pci_dev_list_11a0 NULL +#define pci_dev_list_11a1 NULL +#define pci_dev_list_11a2 NULL +#define pci_dev_list_11a3 NULL +#define pci_dev_list_11a4 NULL +#define pci_dev_list_11a5 NULL +#define pci_dev_list_11a6 NULL +#define pci_dev_list_11a7 NULL +#define pci_dev_list_11a8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11a9[] = { + &pci_dev_info_11a9_4240, + NULL +}; +#endif +#define pci_dev_list_11aa NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11ab[] = { + &pci_dev_info_11ab_0146, + &pci_dev_info_11ab_138f, + &pci_dev_info_11ab_1fa6, + &pci_dev_info_11ab_1fa7, + &pci_dev_info_11ab_1faa, + &pci_dev_info_11ab_4320, + &pci_dev_info_11ab_4340, + &pci_dev_info_11ab_4341, + &pci_dev_info_11ab_4342, + &pci_dev_info_11ab_4343, + &pci_dev_info_11ab_4344, + &pci_dev_info_11ab_4345, + &pci_dev_info_11ab_4346, + &pci_dev_info_11ab_4347, + &pci_dev_info_11ab_4350, + &pci_dev_info_11ab_4351, + &pci_dev_info_11ab_4352, + &pci_dev_info_11ab_4360, + &pci_dev_info_11ab_4361, + &pci_dev_info_11ab_4362, + &pci_dev_info_11ab_4363, + &pci_dev_info_11ab_4611, + &pci_dev_info_11ab_4620, + &pci_dev_info_11ab_4801, + &pci_dev_info_11ab_5005, + &pci_dev_info_11ab_5040, + &pci_dev_info_11ab_5041, + &pci_dev_info_11ab_5080, + &pci_dev_info_11ab_5081, + &pci_dev_info_11ab_6041, + &pci_dev_info_11ab_6081, + &pci_dev_info_11ab_6460, + &pci_dev_info_11ab_6480, + &pci_dev_info_11ab_6485, + &pci_dev_info_11ab_f003, + NULL +}; +#endif +#define pci_dev_list_11ac NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11ad[] = { + &pci_dev_info_11ad_0002, + &pci_dev_info_11ad_c115, + NULL +}; +#endif +#define pci_dev_list_11ae NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11af[] = { + &pci_dev_info_11af_0001, + &pci_dev_info_11af_ee40, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11b0[] = { + &pci_dev_info_11b0_0002, + &pci_dev_info_11b0_0292, + &pci_dev_info_11b0_0960, + &pci_dev_info_11b0_c960, + NULL +}; +#endif +#define pci_dev_list_11b1 NULL +#define pci_dev_list_11b2 NULL +#define pci_dev_list_11b3 NULL +#define pci_dev_list_11b4 NULL +#define pci_dev_list_11b5 NULL +#define pci_dev_list_11b6 NULL +#define pci_dev_list_11b7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11b8[] = { + &pci_dev_info_11b8_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11b9[] = { + &pci_dev_info_11b9_c0ed, + NULL +}; +#endif +#define pci_dev_list_11ba NULL +#define pci_dev_list_11bb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11bc[] = { + &pci_dev_info_11bc_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11bd[] = { + &pci_dev_info_11bd_002e, + &pci_dev_info_11bd_bede, + NULL +}; +#endif +#define pci_dev_list_11be NULL +#define pci_dev_list_11bf NULL +#define pci_dev_list_11c0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11c1[] = { + &pci_dev_info_11c1_0440, + &pci_dev_info_11c1_0441, + &pci_dev_info_11c1_0442, + &pci_dev_info_11c1_0443, + &pci_dev_info_11c1_0444, + &pci_dev_info_11c1_0445, + &pci_dev_info_11c1_0446, + &pci_dev_info_11c1_0447, + &pci_dev_info_11c1_0448, + &pci_dev_info_11c1_0449, + &pci_dev_info_11c1_044a, + &pci_dev_info_11c1_044b, + &pci_dev_info_11c1_044c, + &pci_dev_info_11c1_044d, + &pci_dev_info_11c1_044e, + &pci_dev_info_11c1_044f, + &pci_dev_info_11c1_0450, + &pci_dev_info_11c1_0451, + &pci_dev_info_11c1_0452, + &pci_dev_info_11c1_0453, + &pci_dev_info_11c1_0454, + &pci_dev_info_11c1_0455, + &pci_dev_info_11c1_0456, + &pci_dev_info_11c1_0457, + &pci_dev_info_11c1_0458, + &pci_dev_info_11c1_0459, + &pci_dev_info_11c1_045a, + &pci_dev_info_11c1_045c, + &pci_dev_info_11c1_0461, + &pci_dev_info_11c1_0462, + &pci_dev_info_11c1_0480, + &pci_dev_info_11c1_048c, + &pci_dev_info_11c1_048f, + &pci_dev_info_11c1_5801, + &pci_dev_info_11c1_5802, + &pci_dev_info_11c1_5803, + &pci_dev_info_11c1_5811, + &pci_dev_info_11c1_8110, + &pci_dev_info_11c1_ab10, + &pci_dev_info_11c1_ab11, + &pci_dev_info_11c1_ab20, + &pci_dev_info_11c1_ab21, + &pci_dev_info_11c1_ab30, + &pci_dev_info_11c1_ed00, + &pci_dev_info_11c1_ed01, + NULL +}; +#endif +#define pci_dev_list_11c2 NULL +#define pci_dev_list_11c3 NULL +#define pci_dev_list_11c4 NULL +#define pci_dev_list_11c5 NULL +#define pci_dev_list_11c6 NULL +#define pci_dev_list_11c7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11c8[] = { + &pci_dev_info_11c8_0658, + &pci_dev_info_11c8_d665, + &pci_dev_info_11c8_d667, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11c9[] = { + &pci_dev_info_11c9_0010, + &pci_dev_info_11c9_0011, + NULL +}; +#endif +#define pci_dev_list_11ca NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11cb[] = { + &pci_dev_info_11cb_2000, + &pci_dev_info_11cb_4000, + &pci_dev_info_11cb_8000, + NULL +}; +#endif +#define pci_dev_list_11cc NULL +#define pci_dev_list_11cd NULL +#define pci_dev_list_11ce NULL +#define pci_dev_list_11cf NULL +#define pci_dev_list_11d0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11d1[] = { + &pci_dev_info_11d1_01f7, + NULL +}; +#endif +#define pci_dev_list_11d2 NULL +#define pci_dev_list_11d3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11d4[] = { + &pci_dev_info_11d4_1535, + &pci_dev_info_11d4_1805, + &pci_dev_info_11d4_1889, + &pci_dev_info_11d4_1986, + &pci_dev_info_11d4_5340, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11d5[] = { + &pci_dev_info_11d5_0115, + &pci_dev_info_11d5_0117, + NULL +}; +#endif +#define pci_dev_list_11d6 NULL +#define pci_dev_list_11d7 NULL +#define pci_dev_list_11d8 NULL +#define pci_dev_list_11d9 NULL +#define pci_dev_list_11da NULL +#define pci_dev_list_11db NULL +#define pci_dev_list_11dc NULL +#define pci_dev_list_11dd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11de[] = { + &pci_dev_info_11de_6057, + &pci_dev_info_11de_6120, + NULL +}; +#endif +#define pci_dev_list_11df NULL +#define pci_dev_list_11e0 NULL +#define pci_dev_list_11e1 NULL +#define pci_dev_list_11e2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11e3[] = { + &pci_dev_info_11e3_0001, + &pci_dev_info_11e3_5030, + NULL +}; +#endif +#define pci_dev_list_11e4 NULL +#define pci_dev_list_11e5 NULL +#define pci_dev_list_11e6 NULL +#define pci_dev_list_11e7 NULL +#define pci_dev_list_11e8 NULL +#define pci_dev_list_11e9 NULL +#define pci_dev_list_11ea NULL +#define pci_dev_list_11eb NULL +#define pci_dev_list_11ec NULL +#define pci_dev_list_11ed NULL +#define pci_dev_list_11ee NULL +#define pci_dev_list_11ef NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11f0[] = { + &pci_dev_info_11f0_4231, + &pci_dev_info_11f0_4232, + &pci_dev_info_11f0_4233, + &pci_dev_info_11f0_4234, + &pci_dev_info_11f0_4235, + &pci_dev_info_11f0_4236, + &pci_dev_info_11f0_4731, + NULL +}; +#endif +#define pci_dev_list_11f1 NULL +#define pci_dev_list_11f2 NULL +#define pci_dev_list_11f3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11f4[] = { + &pci_dev_info_11f4_2915, + NULL +}; +#endif +#define pci_dev_list_11f5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11f6[] = { + &pci_dev_info_11f6_0112, + &pci_dev_info_11f6_0113, + &pci_dev_info_11f6_1401, + &pci_dev_info_11f6_2011, + &pci_dev_info_11f6_2201, + &pci_dev_info_11f6_9881, + NULL +}; +#endif +#define pci_dev_list_11f7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11f8[] = { + &pci_dev_info_11f8_7375, + NULL +}; +#endif +#define pci_dev_list_11f9 NULL +#define pci_dev_list_11fa NULL +#define pci_dev_list_11fb NULL +#define pci_dev_list_11fc NULL +#define pci_dev_list_11fd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11fe[] = { + &pci_dev_info_11fe_0001, + &pci_dev_info_11fe_0002, + &pci_dev_info_11fe_0003, + &pci_dev_info_11fe_0004, + &pci_dev_info_11fe_0005, + &pci_dev_info_11fe_0006, + &pci_dev_info_11fe_0007, + &pci_dev_info_11fe_0008, + &pci_dev_info_11fe_0009, + &pci_dev_info_11fe_000a, + &pci_dev_info_11fe_000b, + &pci_dev_info_11fe_000c, + &pci_dev_info_11fe_000d, + &pci_dev_info_11fe_000e, + &pci_dev_info_11fe_000f, + &pci_dev_info_11fe_0801, + &pci_dev_info_11fe_0802, + &pci_dev_info_11fe_0803, + &pci_dev_info_11fe_0805, + &pci_dev_info_11fe_080c, + &pci_dev_info_11fe_080d, + &pci_dev_info_11fe_0812, + &pci_dev_info_11fe_0903, + &pci_dev_info_11fe_8015, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_11ff[] = { + &pci_dev_info_11ff_0003, + NULL +}; +#endif +#define pci_dev_list_1200 NULL +#define pci_dev_list_1201 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1202[] = { + &pci_dev_info_1202_4300, + NULL +}; +#endif +#define pci_dev_list_1203 NULL +#define pci_dev_list_1204 NULL +#define pci_dev_list_1205 NULL +#define pci_dev_list_1206 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1208[] = { + &pci_dev_info_1208_4853, + NULL +}; +#endif +#define pci_dev_list_1209 NULL +#define pci_dev_list_120a NULL +#define pci_dev_list_120b NULL +#define pci_dev_list_120c NULL +#define pci_dev_list_120d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_120e[] = { + &pci_dev_info_120e_0100, + &pci_dev_info_120e_0101, + &pci_dev_info_120e_0102, + &pci_dev_info_120e_0103, + &pci_dev_info_120e_0104, + &pci_dev_info_120e_0105, + &pci_dev_info_120e_0200, + &pci_dev_info_120e_0201, + &pci_dev_info_120e_0300, + &pci_dev_info_120e_0301, + &pci_dev_info_120e_0310, + &pci_dev_info_120e_0311, + &pci_dev_info_120e_0320, + &pci_dev_info_120e_0321, + &pci_dev_info_120e_0400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_120f[] = { + &pci_dev_info_120f_0001, + NULL +}; +#endif +#define pci_dev_list_1210 NULL +#define pci_dev_list_1211 NULL +#define pci_dev_list_1212 NULL +#define pci_dev_list_1213 NULL +#define pci_dev_list_1214 NULL +#define pci_dev_list_1215 NULL +#define pci_dev_list_1216 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1217[] = { + &pci_dev_info_1217_00f7, + &pci_dev_info_1217_6729, + &pci_dev_info_1217_673a, + &pci_dev_info_1217_6832, + &pci_dev_info_1217_6836, + &pci_dev_info_1217_6872, + &pci_dev_info_1217_6925, + &pci_dev_info_1217_6933, + &pci_dev_info_1217_6972, + &pci_dev_info_1217_7110, + &pci_dev_info_1217_7112, + &pci_dev_info_1217_7113, + &pci_dev_info_1217_7114, + &pci_dev_info_1217_7120, + &pci_dev_info_1217_7130, + &pci_dev_info_1217_7134, + &pci_dev_info_1217_7135, + &pci_dev_info_1217_71e2, + &pci_dev_info_1217_7212, + &pci_dev_info_1217_7213, + &pci_dev_info_1217_7223, + &pci_dev_info_1217_7233, + NULL +}; +#endif +#define pci_dev_list_1218 NULL +#define pci_dev_list_1219 NULL +static const pciDeviceInfo *pci_dev_list_121a[] = { + &pci_dev_info_121a_0001, + &pci_dev_info_121a_0002, + &pci_dev_info_121a_0003, + &pci_dev_info_121a_0004, + &pci_dev_info_121a_0005, + &pci_dev_info_121a_0009, + &pci_dev_info_121a_0057, + NULL +}; +#define pci_dev_list_121b NULL +#define pci_dev_list_121c NULL +#define pci_dev_list_121d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_121e[] = { + &pci_dev_info_121e_0201, + NULL +}; +#endif +#define pci_dev_list_121f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1220[] = { + &pci_dev_info_1220_1220, + NULL +}; +#endif +#define pci_dev_list_1221 NULL +#define pci_dev_list_1222 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1223[] = { + &pci_dev_info_1223_0003, + &pci_dev_info_1223_0004, + &pci_dev_info_1223_0005, + &pci_dev_info_1223_0008, + &pci_dev_info_1223_0009, + &pci_dev_info_1223_000a, + &pci_dev_info_1223_000b, + &pci_dev_info_1223_000c, + &pci_dev_info_1223_000d, + &pci_dev_info_1223_000e, + NULL +}; +#endif +#define pci_dev_list_1224 NULL +#define pci_dev_list_1225 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1227[] = { + &pci_dev_info_1227_0006, + &pci_dev_info_1227_0023, + NULL +}; +#endif +#define pci_dev_list_1228 NULL +#define pci_dev_list_1229 NULL +#define pci_dev_list_122a NULL +#define pci_dev_list_122b NULL +#define pci_dev_list_122c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_122d[] = { + &pci_dev_info_122d_1206, + &pci_dev_info_122d_1400, + &pci_dev_info_122d_50dc, + &pci_dev_info_122d_80da, + NULL +}; +#endif +#define pci_dev_list_122e NULL +#define pci_dev_list_122f NULL +#define pci_dev_list_1230 NULL +#define pci_dev_list_1231 NULL +#define pci_dev_list_1232 NULL +#define pci_dev_list_1233 NULL +#define pci_dev_list_1234 NULL +#define pci_dev_list_1235 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1236[] = { + &pci_dev_info_1236_0000, + &pci_dev_info_1236_6401, + NULL +}; +#endif +#define pci_dev_list_1237 NULL +#define pci_dev_list_1238 NULL +#define pci_dev_list_1239 NULL +#define pci_dev_list_123a NULL +#define pci_dev_list_123b NULL +#define pci_dev_list_123c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_123d[] = { + &pci_dev_info_123d_0000, + &pci_dev_info_123d_0002, + &pci_dev_info_123d_0003, + NULL +}; +#endif +#define pci_dev_list_123e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_123f[] = { + &pci_dev_info_123f_00e4, + &pci_dev_info_123f_8120, + &pci_dev_info_123f_8888, + NULL +}; +#endif +#define pci_dev_list_1240 NULL +#define pci_dev_list_1241 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1242[] = { + &pci_dev_info_1242_1560, + &pci_dev_info_1242_4643, + &pci_dev_info_1242_6562, + &pci_dev_info_1242_656a, + NULL +}; +#endif +#define pci_dev_list_1243 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1244[] = { + &pci_dev_info_1244_0700, + &pci_dev_info_1244_0800, + &pci_dev_info_1244_0a00, + &pci_dev_info_1244_0e00, + &pci_dev_info_1244_1100, + &pci_dev_info_1244_1200, + &pci_dev_info_1244_2700, + &pci_dev_info_1244_2900, + NULL +}; +#endif +#define pci_dev_list_1245 NULL +#define pci_dev_list_1246 NULL +#define pci_dev_list_1247 NULL +#define pci_dev_list_1248 NULL +#define pci_dev_list_1249 NULL +#define pci_dev_list_124a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_124b[] = { + &pci_dev_info_124b_0040, + NULL +}; +#endif +#define pci_dev_list_124c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_124d[] = { + &pci_dev_info_124d_0000, + &pci_dev_info_124d_0002, + &pci_dev_info_124d_0003, + &pci_dev_info_124d_0004, + NULL +}; +#endif +#define pci_dev_list_124e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_124f[] = { + &pci_dev_info_124f_0041, + NULL +}; +#endif +#define pci_dev_list_1250 NULL +#define pci_dev_list_1251 NULL +#define pci_dev_list_1253 NULL +#define pci_dev_list_1254 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1255[] = { + &pci_dev_info_1255_1110, + &pci_dev_info_1255_1210, + &pci_dev_info_1255_2110, + &pci_dev_info_1255_2120, + &pci_dev_info_1255_2130, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1256[] = { + &pci_dev_info_1256_4201, + &pci_dev_info_1256_4401, + &pci_dev_info_1256_5201, + NULL +}; +#endif +#define pci_dev_list_1257 NULL +#define pci_dev_list_1258 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1259[] = { + &pci_dev_info_1259_2560, + &pci_dev_info_1259_a117, + &pci_dev_info_1259_a11e, + &pci_dev_info_1259_a120, + NULL +}; +#endif +#define pci_dev_list_125a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_125b[] = { + &pci_dev_info_125b_1400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_125c[] = { + &pci_dev_info_125c_0101, + &pci_dev_info_125c_0640, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_125d[] = { + &pci_dev_info_125d_0000, + &pci_dev_info_125d_1948, + &pci_dev_info_125d_1968, + &pci_dev_info_125d_1969, + &pci_dev_info_125d_1978, + &pci_dev_info_125d_1988, + &pci_dev_info_125d_1989, + &pci_dev_info_125d_1998, + &pci_dev_info_125d_1999, + &pci_dev_info_125d_199a, + &pci_dev_info_125d_199b, + &pci_dev_info_125d_2808, + &pci_dev_info_125d_2838, + &pci_dev_info_125d_2898, + NULL +}; +#endif +#define pci_dev_list_125e NULL +#define pci_dev_list_125f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1260[] = { + &pci_dev_info_1260_3872, + &pci_dev_info_1260_3873, + &pci_dev_info_1260_3886, + &pci_dev_info_1260_3890, + &pci_dev_info_1260_8130, + &pci_dev_info_1260_8131, + &pci_dev_info_1260_ffff, + NULL +}; +#endif +#define pci_dev_list_1261 NULL +#define pci_dev_list_1262 NULL +#define pci_dev_list_1263 NULL +#define pci_dev_list_1264 NULL +#define pci_dev_list_1265 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1266[] = { + &pci_dev_info_1266_0001, + &pci_dev_info_1266_1910, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1267[] = { + &pci_dev_info_1267_5352, + &pci_dev_info_1267_5a4b, + NULL +}; +#endif +#define pci_dev_list_1268 NULL +#define pci_dev_list_1269 NULL +#define pci_dev_list_126a NULL +#define pci_dev_list_126b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_126c[] = { + &pci_dev_info_126c_1211, + &pci_dev_info_126c_126c, + NULL +}; +#endif +#define pci_dev_list_126d NULL +#define pci_dev_list_126e NULL +static const pciDeviceInfo *pci_dev_list_126f[] = { + &pci_dev_info_126f_0501, + &pci_dev_info_126f_0510, + &pci_dev_info_126f_0710, + &pci_dev_info_126f_0712, + &pci_dev_info_126f_0720, + &pci_dev_info_126f_0730, + &pci_dev_info_126f_0810, + &pci_dev_info_126f_0811, + &pci_dev_info_126f_0820, + &pci_dev_info_126f_0910, + NULL +}; +#define pci_dev_list_1270 NULL +#define pci_dev_list_1271 NULL +#define pci_dev_list_1272 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1273[] = { + &pci_dev_info_1273_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1274[] = { + &pci_dev_info_1274_1171, + &pci_dev_info_1274_1371, + &pci_dev_info_1274_5000, + &pci_dev_info_1274_5880, + NULL +}; +#endif +#define pci_dev_list_1275 NULL +#define pci_dev_list_1276 NULL +#define pci_dev_list_1277 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1278[] = { + &pci_dev_info_1278_0701, + &pci_dev_info_1278_0710, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1279[] = { + &pci_dev_info_1279_0060, + &pci_dev_info_1279_0061, + &pci_dev_info_1279_0295, + &pci_dev_info_1279_0395, + &pci_dev_info_1279_0396, + &pci_dev_info_1279_0397, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_127a[] = { + &pci_dev_info_127a_1002, + &pci_dev_info_127a_1003, + &pci_dev_info_127a_1004, + &pci_dev_info_127a_1005, + &pci_dev_info_127a_1022, + &pci_dev_info_127a_1023, + &pci_dev_info_127a_1024, + &pci_dev_info_127a_1025, + &pci_dev_info_127a_1026, + &pci_dev_info_127a_1032, + &pci_dev_info_127a_1033, + &pci_dev_info_127a_1034, + &pci_dev_info_127a_1035, + &pci_dev_info_127a_1036, + &pci_dev_info_127a_1085, + &pci_dev_info_127a_2005, + &pci_dev_info_127a_2013, + &pci_dev_info_127a_2014, + &pci_dev_info_127a_2015, + &pci_dev_info_127a_2016, + &pci_dev_info_127a_4311, + &pci_dev_info_127a_4320, + &pci_dev_info_127a_4321, + &pci_dev_info_127a_4322, + &pci_dev_info_127a_8234, + NULL +}; +#endif +#define pci_dev_list_127b NULL +#define pci_dev_list_127c NULL +#define pci_dev_list_127d NULL +#define pci_dev_list_127e NULL +#define pci_dev_list_127f NULL +#define pci_dev_list_1280 NULL +#define pci_dev_list_1281 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1282[] = { + &pci_dev_info_1282_9009, + &pci_dev_info_1282_9100, + &pci_dev_info_1282_9102, + &pci_dev_info_1282_9132, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1283[] = { + &pci_dev_info_1283_673a, + &pci_dev_info_1283_8211, + &pci_dev_info_1283_8212, + &pci_dev_info_1283_8330, + &pci_dev_info_1283_8872, + &pci_dev_info_1283_8888, + &pci_dev_info_1283_8889, + &pci_dev_info_1283_e886, + NULL +}; +#endif +#define pci_dev_list_1284 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1285[] = { + &pci_dev_info_1285_0100, + NULL +}; +#endif +#define pci_dev_list_1286 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1287[] = { + &pci_dev_info_1287_001e, + &pci_dev_info_1287_001f, + NULL +}; +#endif +#define pci_dev_list_1288 NULL +#define pci_dev_list_1289 NULL +#define pci_dev_list_128a NULL +#define pci_dev_list_128b NULL +#define pci_dev_list_128c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_128d[] = { + &pci_dev_info_128d_0021, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_128e[] = { + &pci_dev_info_128e_0008, + &pci_dev_info_128e_0009, + &pci_dev_info_128e_000a, + &pci_dev_info_128e_000b, + &pci_dev_info_128e_000c, + NULL +}; +#endif +#define pci_dev_list_128f NULL +#define pci_dev_list_1290 NULL +#define pci_dev_list_1291 NULL +#define pci_dev_list_1292 NULL +#define pci_dev_list_1293 NULL +#define pci_dev_list_1294 NULL +#define pci_dev_list_1295 NULL +#define pci_dev_list_1296 NULL +#define pci_dev_list_1297 NULL +#define pci_dev_list_1298 NULL +#define pci_dev_list_1299 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_129a[] = { + &pci_dev_info_129a_0615, + NULL +}; +#endif +#define pci_dev_list_129b NULL +#define pci_dev_list_129c NULL +#define pci_dev_list_129d NULL +#define pci_dev_list_129e NULL +#define pci_dev_list_129f NULL +#define pci_dev_list_12a0 NULL +#define pci_dev_list_12a1 NULL +#define pci_dev_list_12a2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12a3[] = { + &pci_dev_info_12a3_8105, + NULL +}; +#endif +#define pci_dev_list_12a4 NULL +#define pci_dev_list_12a5 NULL +#define pci_dev_list_12a6 NULL +#define pci_dev_list_12a7 NULL +#define pci_dev_list_12a8 NULL +#define pci_dev_list_12a9 NULL +#define pci_dev_list_12aa NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12ab[] = { + &pci_dev_info_12ab_0002, + &pci_dev_info_12ab_3000, + NULL +}; +#endif +#define pci_dev_list_12ac NULL +#define pci_dev_list_12ad NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12ae[] = { + &pci_dev_info_12ae_0001, + &pci_dev_info_12ae_0002, + &pci_dev_info_12ae_00fa, + NULL +}; +#endif +#define pci_dev_list_12af NULL +#define pci_dev_list_12b0 NULL +#define pci_dev_list_12b1 NULL +#define pci_dev_list_12b2 NULL +#define pci_dev_list_12b3 NULL +#define pci_dev_list_12b4 NULL +#define pci_dev_list_12b5 NULL +#define pci_dev_list_12b6 NULL +#define pci_dev_list_12b7 NULL +#define pci_dev_list_12b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12b9[] = { + &pci_dev_info_12b9_1006, + &pci_dev_info_12b9_1007, + &pci_dev_info_12b9_1008, + NULL +}; +#endif +#define pci_dev_list_12ba NULL +#define pci_dev_list_12bb NULL +#define pci_dev_list_12bc NULL +#define pci_dev_list_12bd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12be[] = { + &pci_dev_info_12be_3041, + &pci_dev_info_12be_3042, + NULL +}; +#endif +#define pci_dev_list_12bf NULL +#define pci_dev_list_12c0 NULL +#define pci_dev_list_12c1 NULL +#define pci_dev_list_12c2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12c3[] = { + &pci_dev_info_12c3_0058, + &pci_dev_info_12c3_5598, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12c4[] = { + &pci_dev_info_12c4_0001, + &pci_dev_info_12c4_0002, + &pci_dev_info_12c4_0003, + &pci_dev_info_12c4_0004, + &pci_dev_info_12c4_0005, + &pci_dev_info_12c4_0006, + &pci_dev_info_12c4_0007, + &pci_dev_info_12c4_0008, + &pci_dev_info_12c4_0009, + &pci_dev_info_12c4_000a, + &pci_dev_info_12c4_000b, + &pci_dev_info_12c4_000c, + &pci_dev_info_12c4_000d, + &pci_dev_info_12c4_0100, + &pci_dev_info_12c4_0201, + &pci_dev_info_12c4_0202, + &pci_dev_info_12c4_0300, + &pci_dev_info_12c4_0301, + &pci_dev_info_12c4_0302, + &pci_dev_info_12c4_0310, + &pci_dev_info_12c4_0311, + &pci_dev_info_12c4_0312, + &pci_dev_info_12c4_0320, + &pci_dev_info_12c4_0321, + &pci_dev_info_12c4_0322, + &pci_dev_info_12c4_0330, + &pci_dev_info_12c4_0331, + &pci_dev_info_12c4_0332, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12c5[] = { + &pci_dev_info_12c5_007e, + &pci_dev_info_12c5_007f, + &pci_dev_info_12c5_0081, + &pci_dev_info_12c5_0085, + &pci_dev_info_12c5_0086, + NULL +}; +#endif +#define pci_dev_list_12c6 NULL +#define pci_dev_list_12c7 NULL +#define pci_dev_list_12c8 NULL +#define pci_dev_list_12c9 NULL +#define pci_dev_list_12ca NULL +#define pci_dev_list_12cb NULL +#define pci_dev_list_12cc NULL +#define pci_dev_list_12cd NULL +#define pci_dev_list_12ce NULL +#define pci_dev_list_12cf NULL +#define pci_dev_list_12d0 NULL +#define pci_dev_list_12d1 NULL +static const pciDeviceInfo *pci_dev_list_12d2[] = { + &pci_dev_info_12d2_0008, + &pci_dev_info_12d2_0009, + &pci_dev_info_12d2_0018, + &pci_dev_info_12d2_0019, + &pci_dev_info_12d2_0020, + &pci_dev_info_12d2_0028, + &pci_dev_info_12d2_0029, + &pci_dev_info_12d2_002c, + &pci_dev_info_12d2_00a0, + NULL +}; +#define pci_dev_list_12d3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12d4[] = { + &pci_dev_info_12d4_0200, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12d5[] = { + &pci_dev_info_12d5_0003, + &pci_dev_info_12d5_1000, + NULL +}; +#endif +#define pci_dev_list_12d6 NULL +#define pci_dev_list_12d7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12d8[] = { + &pci_dev_info_12d8_8150, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12d9[] = { + &pci_dev_info_12d9_0002, + &pci_dev_info_12d9_0004, + &pci_dev_info_12d9_0005, + &pci_dev_info_12d9_1078, + NULL +}; +#endif +#define pci_dev_list_12da NULL +#define pci_dev_list_12db NULL +#define pci_dev_list_12dc NULL +#define pci_dev_list_12dd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12de[] = { + &pci_dev_info_12de_0200, + NULL +}; +#endif +#define pci_dev_list_12df NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12e0[] = { + &pci_dev_info_12e0_0010, + &pci_dev_info_12e0_0020, + &pci_dev_info_12e0_0030, + NULL +}; +#endif +#define pci_dev_list_12e1 NULL +#define pci_dev_list_12e2 NULL +#define pci_dev_list_12e3 NULL +#define pci_dev_list_12e4 NULL +#define pci_dev_list_12e5 NULL +#define pci_dev_list_12e6 NULL +#define pci_dev_list_12e7 NULL +#define pci_dev_list_12e8 NULL +#define pci_dev_list_12e9 NULL +#define pci_dev_list_12ea NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12eb[] = { + &pci_dev_info_12eb_0001, + &pci_dev_info_12eb_0002, + &pci_dev_info_12eb_0003, + &pci_dev_info_12eb_8803, + NULL +}; +#endif +#define pci_dev_list_12ec NULL +#define pci_dev_list_12ed NULL +#define pci_dev_list_12ee NULL +#define pci_dev_list_12ef NULL +#define pci_dev_list_12f0 NULL +#define pci_dev_list_12f1 NULL +#define pci_dev_list_12f2 NULL +#define pci_dev_list_12f3 NULL +#define pci_dev_list_12f4 NULL +#define pci_dev_list_12f5 NULL +#define pci_dev_list_12f6 NULL +#define pci_dev_list_12f7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12f8[] = { + &pci_dev_info_12f8_0002, + NULL +}; +#endif +#define pci_dev_list_12f9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_12fb[] = { + &pci_dev_info_12fb_0001, + &pci_dev_info_12fb_00f5, + &pci_dev_info_12fb_02ad, + &pci_dev_info_12fb_2adc, + &pci_dev_info_12fb_3100, + &pci_dev_info_12fb_3500, + &pci_dev_info_12fb_4d4f, + &pci_dev_info_12fb_8120, + &pci_dev_info_12fb_da62, + &pci_dev_info_12fb_db62, + &pci_dev_info_12fb_dc62, + &pci_dev_info_12fb_dd62, + &pci_dev_info_12fb_eddc, + &pci_dev_info_12fb_fa01, + NULL +}; +#endif +#define pci_dev_list_12fc NULL +#define pci_dev_list_12fd NULL +#define pci_dev_list_12fe NULL +#define pci_dev_list_12ff NULL +#define pci_dev_list_1300 NULL +#define pci_dev_list_1302 NULL +#define pci_dev_list_1303 NULL +#define pci_dev_list_1304 NULL +#define pci_dev_list_1305 NULL +#define pci_dev_list_1306 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1307[] = { + &pci_dev_info_1307_0001, + &pci_dev_info_1307_000b, + &pci_dev_info_1307_000c, + &pci_dev_info_1307_000d, + &pci_dev_info_1307_000f, + &pci_dev_info_1307_0010, + &pci_dev_info_1307_0014, + &pci_dev_info_1307_0015, + &pci_dev_info_1307_0016, + &pci_dev_info_1307_0017, + &pci_dev_info_1307_0018, + &pci_dev_info_1307_0019, + &pci_dev_info_1307_001a, + &pci_dev_info_1307_001b, + &pci_dev_info_1307_001c, + &pci_dev_info_1307_001d, + &pci_dev_info_1307_001e, + &pci_dev_info_1307_001f, + &pci_dev_info_1307_0020, + &pci_dev_info_1307_0021, + &pci_dev_info_1307_0022, + &pci_dev_info_1307_0023, + &pci_dev_info_1307_0024, + &pci_dev_info_1307_0025, + &pci_dev_info_1307_0026, + &pci_dev_info_1307_0027, + &pci_dev_info_1307_0028, + &pci_dev_info_1307_0029, + &pci_dev_info_1307_002c, + &pci_dev_info_1307_0033, + &pci_dev_info_1307_0034, + &pci_dev_info_1307_0035, + &pci_dev_info_1307_0036, + &pci_dev_info_1307_0037, + &pci_dev_info_1307_004c, + &pci_dev_info_1307_004d, + &pci_dev_info_1307_0052, + &pci_dev_info_1307_0054, + &pci_dev_info_1307_005e, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1308[] = { + &pci_dev_info_1308_0001, + NULL +}; +#endif +#define pci_dev_list_1309 NULL +#define pci_dev_list_130a NULL +#define pci_dev_list_130b NULL +#define pci_dev_list_130c NULL +#define pci_dev_list_130d NULL +#define pci_dev_list_130e NULL +#define pci_dev_list_130f NULL +#define pci_dev_list_1310 NULL +#define pci_dev_list_1311 NULL +#define pci_dev_list_1312 NULL +#define pci_dev_list_1313 NULL +#define pci_dev_list_1316 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1317[] = { + &pci_dev_info_1317_0981, + &pci_dev_info_1317_0985, + &pci_dev_info_1317_1985, + &pci_dev_info_1317_2850, + &pci_dev_info_1317_5120, + &pci_dev_info_1317_8201, + &pci_dev_info_1317_8211, + &pci_dev_info_1317_9511, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1318[] = { + &pci_dev_info_1318_0911, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1319[] = { + &pci_dev_info_1319_0801, + &pci_dev_info_1319_0802, + &pci_dev_info_1319_1000, + &pci_dev_info_1319_1001, + NULL +}; +#endif +#define pci_dev_list_131a NULL +#define pci_dev_list_131c NULL +#define pci_dev_list_131d NULL +#define pci_dev_list_131e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_131f[] = { + &pci_dev_info_131f_1000, + &pci_dev_info_131f_1001, + &pci_dev_info_131f_1002, + &pci_dev_info_131f_1010, + &pci_dev_info_131f_1011, + &pci_dev_info_131f_1012, + &pci_dev_info_131f_1020, + &pci_dev_info_131f_1021, + &pci_dev_info_131f_1030, + &pci_dev_info_131f_1031, + &pci_dev_info_131f_1032, + &pci_dev_info_131f_1034, + &pci_dev_info_131f_1035, + &pci_dev_info_131f_1036, + &pci_dev_info_131f_1050, + &pci_dev_info_131f_1051, + &pci_dev_info_131f_1052, + &pci_dev_info_131f_2000, + &pci_dev_info_131f_2001, + &pci_dev_info_131f_2002, + &pci_dev_info_131f_2010, + &pci_dev_info_131f_2011, + &pci_dev_info_131f_2012, + &pci_dev_info_131f_2020, + &pci_dev_info_131f_2021, + &pci_dev_info_131f_2030, + &pci_dev_info_131f_2031, + &pci_dev_info_131f_2032, + &pci_dev_info_131f_2040, + &pci_dev_info_131f_2041, + &pci_dev_info_131f_2042, + &pci_dev_info_131f_2050, + &pci_dev_info_131f_2051, + &pci_dev_info_131f_2052, + &pci_dev_info_131f_2060, + &pci_dev_info_131f_2061, + &pci_dev_info_131f_2062, + &pci_dev_info_131f_2081, + NULL +}; +#endif +#define pci_dev_list_1320 NULL +#define pci_dev_list_1321 NULL +#define pci_dev_list_1322 NULL +#define pci_dev_list_1323 NULL +#define pci_dev_list_1324 NULL +#define pci_dev_list_1325 NULL +#define pci_dev_list_1326 NULL +#define pci_dev_list_1327 NULL +#define pci_dev_list_1328 NULL +#define pci_dev_list_1329 NULL +#define pci_dev_list_132a NULL +#define pci_dev_list_132b NULL +#define pci_dev_list_132c NULL +#define pci_dev_list_132d NULL +#define pci_dev_list_1330 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1331[] = { + &pci_dev_info_1331_0030, + &pci_dev_info_1331_8200, + &pci_dev_info_1331_8201, + &pci_dev_info_1331_8202, + &pci_dev_info_1331_8210, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1332[] = { + &pci_dev_info_1332_5415, + &pci_dev_info_1332_5425, + &pci_dev_info_1332_6140, + NULL +}; +#endif +#define pci_dev_list_1334 NULL +#define pci_dev_list_1335 NULL +#define pci_dev_list_1337 NULL +#define pci_dev_list_1338 NULL +#define pci_dev_list_133a NULL +#define pci_dev_list_133b NULL +#define pci_dev_list_133c NULL +#define pci_dev_list_133d NULL +#define pci_dev_list_133e NULL +#define pci_dev_list_133f NULL +#define pci_dev_list_1340 NULL +#define pci_dev_list_1341 NULL +#define pci_dev_list_1342 NULL +#define pci_dev_list_1343 NULL +#define pci_dev_list_1344 NULL +#define pci_dev_list_1345 NULL +#define pci_dev_list_1347 NULL +#define pci_dev_list_1349 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_134a[] = { + &pci_dev_info_134a_0001, + &pci_dev_info_134a_0002, + NULL +}; +#endif +#define pci_dev_list_134b NULL +#define pci_dev_list_134c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_134d[] = { + &pci_dev_info_134d_2189, + &pci_dev_info_134d_2486, + &pci_dev_info_134d_7890, + &pci_dev_info_134d_7891, + &pci_dev_info_134d_7892, + &pci_dev_info_134d_7893, + &pci_dev_info_134d_7894, + &pci_dev_info_134d_7895, + &pci_dev_info_134d_7896, + &pci_dev_info_134d_7897, + NULL +}; +#endif +#define pci_dev_list_134e NULL +#define pci_dev_list_134f NULL +#define pci_dev_list_1350 NULL +#define pci_dev_list_1351 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1353[] = { + &pci_dev_info_1353_0002, + &pci_dev_info_1353_0003, + &pci_dev_info_1353_0004, + &pci_dev_info_1353_0005, + NULL +}; +#endif +#define pci_dev_list_1354 NULL +#define pci_dev_list_1355 NULL +#define pci_dev_list_1356 NULL +#define pci_dev_list_1359 NULL +#define pci_dev_list_135a NULL +#define pci_dev_list_135b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_135c[] = { + &pci_dev_info_135c_0010, + &pci_dev_info_135c_0020, + &pci_dev_info_135c_0030, + &pci_dev_info_135c_0040, + &pci_dev_info_135c_0050, + &pci_dev_info_135c_0060, + &pci_dev_info_135c_00f0, + &pci_dev_info_135c_0170, + &pci_dev_info_135c_0180, + &pci_dev_info_135c_0190, + &pci_dev_info_135c_01a0, + &pci_dev_info_135c_01b0, + &pci_dev_info_135c_01c0, + NULL +}; +#endif +#define pci_dev_list_135d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_135e[] = { + &pci_dev_info_135e_5101, + &pci_dev_info_135e_7101, + &pci_dev_info_135e_7201, + &pci_dev_info_135e_7202, + &pci_dev_info_135e_7401, + &pci_dev_info_135e_7402, + &pci_dev_info_135e_7801, + &pci_dev_info_135e_7804, + &pci_dev_info_135e_8001, + NULL +}; +#endif +#define pci_dev_list_135f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1360[] = { + &pci_dev_info_1360_0101, + &pci_dev_info_1360_0102, + &pci_dev_info_1360_0103, + &pci_dev_info_1360_0104, + &pci_dev_info_1360_0201, + &pci_dev_info_1360_0202, + &pci_dev_info_1360_0203, + &pci_dev_info_1360_0204, + &pci_dev_info_1360_0301, + &pci_dev_info_1360_0302, + &pci_dev_info_1360_0303, + NULL +}; +#endif +#define pci_dev_list_1361 NULL +#define pci_dev_list_1362 NULL +#define pci_dev_list_1363 NULL +#define pci_dev_list_1364 NULL +#define pci_dev_list_1365 NULL +#define pci_dev_list_1366 NULL +#define pci_dev_list_1367 NULL +#define pci_dev_list_1368 NULL +#define pci_dev_list_1369 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_136a[] = { + &pci_dev_info_136a_0004, + &pci_dev_info_136a_0007, + &pci_dev_info_136a_0008, + &pci_dev_info_136a_000a, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_136b[] = { + &pci_dev_info_136b_ff01, + NULL +}; +#endif +#define pci_dev_list_136c NULL +#define pci_dev_list_136d NULL +#define pci_dev_list_136f NULL +#define pci_dev_list_1370 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1371[] = { + &pci_dev_info_1371_434e, + NULL +}; +#endif +#define pci_dev_list_1373 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1374[] = { + &pci_dev_info_1374_0024, + &pci_dev_info_1374_0025, + &pci_dev_info_1374_0026, + &pci_dev_info_1374_0027, + &pci_dev_info_1374_0029, + &pci_dev_info_1374_002a, + &pci_dev_info_1374_002b, + &pci_dev_info_1374_002c, + &pci_dev_info_1374_002d, + &pci_dev_info_1374_002e, + &pci_dev_info_1374_002f, + &pci_dev_info_1374_0030, + &pci_dev_info_1374_0031, + &pci_dev_info_1374_0032, + &pci_dev_info_1374_0034, + &pci_dev_info_1374_0035, + &pci_dev_info_1374_0036, + &pci_dev_info_1374_0037, + &pci_dev_info_1374_0038, + &pci_dev_info_1374_0039, + &pci_dev_info_1374_003a, + NULL +}; +#endif +#define pci_dev_list_1375 NULL +#define pci_dev_list_1376 NULL +#define pci_dev_list_1377 NULL +#define pci_dev_list_1378 NULL +#define pci_dev_list_1379 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_137a[] = { + &pci_dev_info_137a_0001, + NULL +}; +#endif +#define pci_dev_list_137b NULL +#define pci_dev_list_137c NULL +#define pci_dev_list_137d NULL +#define pci_dev_list_137e NULL +#define pci_dev_list_137f NULL +#define pci_dev_list_1380 NULL +#define pci_dev_list_1381 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1382[] = { + &pci_dev_info_1382_0001, + &pci_dev_info_1382_2008, + &pci_dev_info_1382_2048, + &pci_dev_info_1382_2088, + &pci_dev_info_1382_20c8, + &pci_dev_info_1382_4008, + &pci_dev_info_1382_4010, + &pci_dev_info_1382_4048, + &pci_dev_info_1382_4088, + &pci_dev_info_1382_4248, + &pci_dev_info_1382_4424, + NULL +}; +#endif +#define pci_dev_list_1383 NULL +#define pci_dev_list_1384 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1385[] = { + &pci_dev_info_1385_0013, + &pci_dev_info_1385_311a, + &pci_dev_info_1385_4100, + &pci_dev_info_1385_4105, + &pci_dev_info_1385_4251, + &pci_dev_info_1385_4400, + &pci_dev_info_1385_4600, + &pci_dev_info_1385_4601, + &pci_dev_info_1385_4610, + &pci_dev_info_1385_4800, + &pci_dev_info_1385_4900, + &pci_dev_info_1385_4a00, + &pci_dev_info_1385_4b00, + &pci_dev_info_1385_4c00, + &pci_dev_info_1385_4d00, + &pci_dev_info_1385_4e00, + &pci_dev_info_1385_4f00, + &pci_dev_info_1385_5200, + &pci_dev_info_1385_620a, + &pci_dev_info_1385_622a, + &pci_dev_info_1385_630a, + &pci_dev_info_1385_6b00, + &pci_dev_info_1385_6d00, + &pci_dev_info_1385_7b00, + &pci_dev_info_1385_7c00, + &pci_dev_info_1385_7d00, + &pci_dev_info_1385_7e00, + &pci_dev_info_1385_f004, + NULL +}; +#endif +#define pci_dev_list_1386 NULL +#define pci_dev_list_1387 NULL +#define pci_dev_list_1388 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1389[] = { + &pci_dev_info_1389_0001, + NULL +}; +#endif +#define pci_dev_list_138a NULL +#define pci_dev_list_138b NULL +#define pci_dev_list_138c NULL +#define pci_dev_list_138d NULL +#define pci_dev_list_138e NULL +#define pci_dev_list_138f NULL +#define pci_dev_list_1390 NULL +#define pci_dev_list_1391 NULL +#define pci_dev_list_1392 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1393[] = { + &pci_dev_info_1393_1040, + &pci_dev_info_1393_1141, + &pci_dev_info_1393_1680, + &pci_dev_info_1393_2040, + &pci_dev_info_1393_2180, + &pci_dev_info_1393_3200, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1394[] = { + &pci_dev_info_1394_0001, + NULL +}; +#endif +#define pci_dev_list_1395 NULL +#define pci_dev_list_1396 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1397[] = { + &pci_dev_info_1397_08b4, + &pci_dev_info_1397_16b8, + &pci_dev_info_1397_2bd0, + NULL +}; +#endif +#define pci_dev_list_1398 NULL +#define pci_dev_list_1399 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_139a[] = { + &pci_dev_info_139a_0001, + &pci_dev_info_139a_0003, + &pci_dev_info_139a_0005, + NULL +}; +#endif +#define pci_dev_list_139b NULL +#define pci_dev_list_139c NULL +#define pci_dev_list_139d NULL +#define pci_dev_list_139e NULL +#define pci_dev_list_139f NULL +#define pci_dev_list_13a0 NULL +#define pci_dev_list_13a1 NULL +#define pci_dev_list_13a2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13a3[] = { + &pci_dev_info_13a3_0005, + &pci_dev_info_13a3_0006, + &pci_dev_info_13a3_0007, + &pci_dev_info_13a3_0012, + &pci_dev_info_13a3_0014, + &pci_dev_info_13a3_0016, + &pci_dev_info_13a3_0017, + &pci_dev_info_13a3_0018, + &pci_dev_info_13a3_001d, + &pci_dev_info_13a3_0020, + &pci_dev_info_13a3_0026, + NULL +}; +#endif +#define pci_dev_list_13a4 NULL +#define pci_dev_list_13a5 NULL +#define pci_dev_list_13a6 NULL +#define pci_dev_list_13a7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13a8[] = { + &pci_dev_info_13a8_0152, + &pci_dev_info_13a8_0154, + &pci_dev_info_13a8_0158, + NULL +}; +#endif +#define pci_dev_list_13a9 NULL +#define pci_dev_list_13aa NULL +#define pci_dev_list_13ab NULL +#define pci_dev_list_13ac NULL +#define pci_dev_list_13ad NULL +#define pci_dev_list_13ae NULL +#define pci_dev_list_13af NULL +#define pci_dev_list_13b0 NULL +#define pci_dev_list_13b1 NULL +#define pci_dev_list_13b2 NULL +#define pci_dev_list_13b3 NULL +#define pci_dev_list_13b4 NULL +#define pci_dev_list_13b5 NULL +#define pci_dev_list_13b6 NULL +#define pci_dev_list_13b7 NULL +#define pci_dev_list_13b8 NULL +#define pci_dev_list_13b9 NULL +#define pci_dev_list_13ba NULL +#define pci_dev_list_13bb NULL +#define pci_dev_list_13bc NULL +#define pci_dev_list_13bd NULL +#define pci_dev_list_13be NULL +#define pci_dev_list_13bf NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13c0[] = { + &pci_dev_info_13c0_0010, + &pci_dev_info_13c0_0020, + &pci_dev_info_13c0_0030, + &pci_dev_info_13c0_0210, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13c1[] = { + &pci_dev_info_13c1_1000, + &pci_dev_info_13c1_1001, + &pci_dev_info_13c1_1002, + &pci_dev_info_13c1_1003, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13c2[] = { + &pci_dev_info_13c2_000e, + NULL +}; +#endif +#define pci_dev_list_13c3 NULL +#define pci_dev_list_13c4 NULL +#define pci_dev_list_13c5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13c6[] = { + &pci_dev_info_13c6_0520, + &pci_dev_info_13c6_0620, + &pci_dev_info_13c6_0820, + NULL +}; +#endif +#define pci_dev_list_13c7 NULL +#define pci_dev_list_13c8 NULL +#define pci_dev_list_13c9 NULL +#define pci_dev_list_13ca NULL +#define pci_dev_list_13cb NULL +#define pci_dev_list_13cc NULL +#define pci_dev_list_13cd NULL +#define pci_dev_list_13ce NULL +#define pci_dev_list_13cf NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13d0[] = { + &pci_dev_info_13d0_2103, + &pci_dev_info_13d0_2200, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13d1[] = { + &pci_dev_info_13d1_ab02, + &pci_dev_info_13d1_ab03, + &pci_dev_info_13d1_ab06, + &pci_dev_info_13d1_ab08, + NULL +}; +#endif +#define pci_dev_list_13d2 NULL +#define pci_dev_list_13d3 NULL +#define pci_dev_list_13d4 NULL +#define pci_dev_list_13d5 NULL +#define pci_dev_list_13d6 NULL +#define pci_dev_list_13d7 NULL +#define pci_dev_list_13d8 NULL +#define pci_dev_list_13d9 NULL +#define pci_dev_list_13da NULL +#define pci_dev_list_13db NULL +#define pci_dev_list_13dc NULL +#define pci_dev_list_13dd NULL +#define pci_dev_list_13de NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13df[] = { + &pci_dev_info_13df_0001, + NULL +}; +#endif +#define pci_dev_list_13e0 NULL +#define pci_dev_list_13e1 NULL +#define pci_dev_list_13e2 NULL +#define pci_dev_list_13e3 NULL +#define pci_dev_list_13e4 NULL +#define pci_dev_list_13e5 NULL +#define pci_dev_list_13e6 NULL +#define pci_dev_list_13e7 NULL +#define pci_dev_list_13e8 NULL +#define pci_dev_list_13e9 NULL +#define pci_dev_list_13ea NULL +#define pci_dev_list_13eb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13ec[] = { + &pci_dev_info_13ec_000a, + NULL +}; +#endif +#define pci_dev_list_13ed NULL +#define pci_dev_list_13ee NULL +#define pci_dev_list_13ef NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13f0[] = { + &pci_dev_info_13f0_0200, + &pci_dev_info_13f0_0201, + &pci_dev_info_13f0_1023, + NULL +}; +#endif +#define pci_dev_list_13f1 NULL +#define pci_dev_list_13f2 NULL +#define pci_dev_list_13f3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13f4[] = { + &pci_dev_info_13f4_1401, + NULL +}; +#endif +#define pci_dev_list_13f5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13f6[] = { + &pci_dev_info_13f6_0011, + &pci_dev_info_13f6_0100, + &pci_dev_info_13f6_0101, + &pci_dev_info_13f6_0111, + &pci_dev_info_13f6_0211, + NULL +}; +#endif +#define pci_dev_list_13f7 NULL +#define pci_dev_list_13f8 NULL +#define pci_dev_list_13f9 NULL +#define pci_dev_list_13fa NULL +#define pci_dev_list_13fb NULL +#define pci_dev_list_13fc NULL +#define pci_dev_list_13fd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_13fe[] = { + &pci_dev_info_13fe_1240, + &pci_dev_info_13fe_1600, + &pci_dev_info_13fe_16ff, + &pci_dev_info_13fe_1733, + &pci_dev_info_13fe_1752, + &pci_dev_info_13fe_1754, + &pci_dev_info_13fe_1756, + NULL +}; +#endif +#define pci_dev_list_13ff NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1400[] = { + &pci_dev_info_1400_1401, + NULL +}; +#endif +#define pci_dev_list_1401 NULL +#define pci_dev_list_1402 NULL +#define pci_dev_list_1403 NULL +#define pci_dev_list_1404 NULL +#define pci_dev_list_1405 NULL +#define pci_dev_list_1406 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1407[] = { + &pci_dev_info_1407_0100, + &pci_dev_info_1407_0101, + &pci_dev_info_1407_0102, + &pci_dev_info_1407_0110, + &pci_dev_info_1407_0111, + &pci_dev_info_1407_0120, + &pci_dev_info_1407_0121, + &pci_dev_info_1407_0180, + &pci_dev_info_1407_0181, + &pci_dev_info_1407_0200, + &pci_dev_info_1407_0201, + &pci_dev_info_1407_0202, + &pci_dev_info_1407_0220, + &pci_dev_info_1407_0221, + &pci_dev_info_1407_0500, + &pci_dev_info_1407_0600, + &pci_dev_info_1407_8000, + &pci_dev_info_1407_8001, + &pci_dev_info_1407_8002, + &pci_dev_info_1407_8003, + &pci_dev_info_1407_8800, + NULL +}; +#endif +#define pci_dev_list_1408 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1409[] = { + &pci_dev_info_1409_7168, + NULL +}; +#endif +#define pci_dev_list_140a NULL +#define pci_dev_list_140b NULL +#define pci_dev_list_140c NULL +#define pci_dev_list_140d NULL +#define pci_dev_list_140e NULL +#define pci_dev_list_140f NULL +#define pci_dev_list_1410 NULL +#define pci_dev_list_1411 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1412[] = { + &pci_dev_info_1412_1712, + &pci_dev_info_1412_1724, + NULL +}; +#endif +#define pci_dev_list_1413 NULL +#define pci_dev_list_1414 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1415[] = { + &pci_dev_info_1415_8403, + &pci_dev_info_1415_9500, + &pci_dev_info_1415_9501, + &pci_dev_info_1415_950a, + &pci_dev_info_1415_950b, + &pci_dev_info_1415_9510, + &pci_dev_info_1415_9511, + &pci_dev_info_1415_9512, + &pci_dev_info_1415_9513, + &pci_dev_info_1415_9521, + &pci_dev_info_1415_9523, + NULL +}; +#endif +#define pci_dev_list_1416 NULL +#define pci_dev_list_1417 NULL +#define pci_dev_list_1418 NULL +#define pci_dev_list_1419 NULL +#define pci_dev_list_141a NULL +#define pci_dev_list_141b NULL +#define pci_dev_list_141d NULL +#define pci_dev_list_141e NULL +#define pci_dev_list_141f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1420[] = { + &pci_dev_info_1420_8002, + &pci_dev_info_1420_8003, + NULL +}; +#endif +#define pci_dev_list_1421 NULL +#define pci_dev_list_1422 NULL +#define pci_dev_list_1423 NULL +#define pci_dev_list_1424 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1425[] = { + &pci_dev_info_1425_000b, + NULL +}; +#endif +#define pci_dev_list_1426 NULL +#define pci_dev_list_1427 NULL +#define pci_dev_list_1428 NULL +#define pci_dev_list_1429 NULL +#define pci_dev_list_142a NULL +#define pci_dev_list_142b NULL +#define pci_dev_list_142c NULL +#define pci_dev_list_142d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_142e[] = { + &pci_dev_info_142e_4020, + &pci_dev_info_142e_4337, + NULL +}; +#endif +#define pci_dev_list_142f NULL +#define pci_dev_list_1430 NULL +#define pci_dev_list_1431 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1432[] = { + &pci_dev_info_1432_9130, + NULL +}; +#endif +#define pci_dev_list_1433 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1435[] = { + &pci_dev_info_1435_4520, + &pci_dev_info_1435_6020, + &pci_dev_info_1435_6030, + &pci_dev_info_1435_6420, + &pci_dev_info_1435_6430, + &pci_dev_info_1435_7520, + &pci_dev_info_1435_7820, + NULL +}; +#endif +#define pci_dev_list_1436 NULL +#define pci_dev_list_1437 NULL +#define pci_dev_list_1438 NULL +#define pci_dev_list_1439 NULL +#define pci_dev_list_143a NULL +#define pci_dev_list_143b NULL +#define pci_dev_list_143c NULL +#define pci_dev_list_143d NULL +#define pci_dev_list_143e NULL +#define pci_dev_list_143f NULL +#define pci_dev_list_1440 NULL +#define pci_dev_list_1441 NULL +#define pci_dev_list_1442 NULL +#define pci_dev_list_1443 NULL +#define pci_dev_list_1444 NULL +#define pci_dev_list_1445 NULL +#define pci_dev_list_1446 NULL +#define pci_dev_list_1447 NULL +#define pci_dev_list_1448 NULL +#define pci_dev_list_1449 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_144a[] = { + &pci_dev_info_144a_7296, + &pci_dev_info_144a_7432, + &pci_dev_info_144a_7433, + &pci_dev_info_144a_7434, + &pci_dev_info_144a_7841, + &pci_dev_info_144a_8133, + &pci_dev_info_144a_8164, + &pci_dev_info_144a_8554, + &pci_dev_info_144a_9111, + &pci_dev_info_144a_9113, + &pci_dev_info_144a_9114, + NULL +}; +#endif +#define pci_dev_list_144b NULL +#define pci_dev_list_144c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_144d[] = { + &pci_dev_info_144d_c00c, + NULL +}; +#endif +#define pci_dev_list_144e NULL +#define pci_dev_list_144f NULL +#define pci_dev_list_1450 NULL +#define pci_dev_list_1451 NULL +#define pci_dev_list_1453 NULL +#define pci_dev_list_1454 NULL +#define pci_dev_list_1455 NULL +#define pci_dev_list_1456 NULL +#define pci_dev_list_1457 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1458[] = { + &pci_dev_info_1458_0c11, + &pci_dev_info_1458_e911, + NULL +}; +#endif +#define pci_dev_list_1459 NULL +#define pci_dev_list_145a NULL +#define pci_dev_list_145b NULL +#define pci_dev_list_145c NULL +#define pci_dev_list_145d NULL +#define pci_dev_list_145e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_145f[] = { + &pci_dev_info_145f_0001, + NULL +}; +#endif +#define pci_dev_list_1460 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1461[] = { + &pci_dev_info_1461_f436, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1462[] = { + &pci_dev_info_1462_5501, + &pci_dev_info_1462_6819, + &pci_dev_info_1462_6825, + &pci_dev_info_1462_6834, + &pci_dev_info_1462_7125, + &pci_dev_info_1462_8725, + &pci_dev_info_1462_9000, + &pci_dev_info_1462_9110, + &pci_dev_info_1462_9119, + &pci_dev_info_1462_9123, + &pci_dev_info_1462_9510, + &pci_dev_info_1462_9511, + &pci_dev_info_1462_9591, + NULL +}; +#endif +#define pci_dev_list_1463 NULL +#define pci_dev_list_1464 NULL +#define pci_dev_list_1465 NULL +#define pci_dev_list_1466 NULL +#define pci_dev_list_1467 NULL +#define pci_dev_list_1468 NULL +#define pci_dev_list_1469 NULL +#define pci_dev_list_146a NULL +#define pci_dev_list_146b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_146c[] = { + &pci_dev_info_146c_1430, + NULL +}; +#endif +#define pci_dev_list_146d NULL +#define pci_dev_list_146e NULL +#define pci_dev_list_146f NULL +#define pci_dev_list_1470 NULL +#define pci_dev_list_1471 NULL +#define pci_dev_list_1472 NULL +#define pci_dev_list_1473 NULL +#define pci_dev_list_1474 NULL +#define pci_dev_list_1475 NULL +#define pci_dev_list_1476 NULL +#define pci_dev_list_1477 NULL +#define pci_dev_list_1478 NULL +#define pci_dev_list_1479 NULL +#define pci_dev_list_147a NULL +#define pci_dev_list_147b NULL +#define pci_dev_list_147c NULL +#define pci_dev_list_147d NULL +#define pci_dev_list_147e NULL +#define pci_dev_list_147f NULL +#define pci_dev_list_1480 NULL +#define pci_dev_list_1481 NULL +#define pci_dev_list_1482 NULL +#define pci_dev_list_1483 NULL +#define pci_dev_list_1484 NULL +#define pci_dev_list_1485 NULL +#define pci_dev_list_1486 NULL +#define pci_dev_list_1487 NULL +#define pci_dev_list_1488 NULL +#define pci_dev_list_1489 NULL +#define pci_dev_list_148a NULL +#define pci_dev_list_148b NULL +#define pci_dev_list_148c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_148d[] = { + &pci_dev_info_148d_1003, + NULL +}; +#endif +#define pci_dev_list_148e NULL +#define pci_dev_list_148f NULL +#define pci_dev_list_1490 NULL +#define pci_dev_list_1491 NULL +#define pci_dev_list_1492 NULL +#define pci_dev_list_1493 NULL +#define pci_dev_list_1494 NULL +#define pci_dev_list_1495 NULL +#define pci_dev_list_1496 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1497[] = { + &pci_dev_info_1497_1497, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1498[] = { + &pci_dev_info_1498_0330, + &pci_dev_info_1498_0385, + &pci_dev_info_1498_21cc, + &pci_dev_info_1498_21cd, + &pci_dev_info_1498_30c8, + NULL +}; +#endif +#define pci_dev_list_1499 NULL +#define pci_dev_list_149a NULL +#define pci_dev_list_149b NULL +#define pci_dev_list_149c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_149d[] = { + &pci_dev_info_149d_0001, + NULL +}; +#endif +#define pci_dev_list_149e NULL +#define pci_dev_list_149f NULL +#define pci_dev_list_14a0 NULL +#define pci_dev_list_14a1 NULL +#define pci_dev_list_14a2 NULL +#define pci_dev_list_14a3 NULL +#define pci_dev_list_14a4 NULL +#define pci_dev_list_14a5 NULL +#define pci_dev_list_14a6 NULL +#define pci_dev_list_14a7 NULL +#define pci_dev_list_14a8 NULL +#define pci_dev_list_14a9 NULL +#define pci_dev_list_14aa NULL +#define pci_dev_list_14ab NULL +#define pci_dev_list_14ac NULL +#define pci_dev_list_14ad NULL +#define pci_dev_list_14ae NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14af[] = { + &pci_dev_info_14af_7102, + NULL +}; +#endif +#define pci_dev_list_14b0 NULL +#define pci_dev_list_14b1 NULL +#define pci_dev_list_14b2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14b3[] = { + &pci_dev_info_14b3_0000, + NULL +}; +#endif +#define pci_dev_list_14b4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14b5[] = { + &pci_dev_info_14b5_0200, + &pci_dev_info_14b5_0300, + &pci_dev_info_14b5_0400, + &pci_dev_info_14b5_0600, + &pci_dev_info_14b5_0800, + &pci_dev_info_14b5_0900, + &pci_dev_info_14b5_0a00, + &pci_dev_info_14b5_0b00, + NULL +}; +#endif +#define pci_dev_list_14b6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14b7[] = { + &pci_dev_info_14b7_0001, + NULL +}; +#endif +#define pci_dev_list_14b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14b9[] = { + &pci_dev_info_14b9_0001, + &pci_dev_info_14b9_0340, + &pci_dev_info_14b9_0350, + &pci_dev_info_14b9_4500, + &pci_dev_info_14b9_4800, + &pci_dev_info_14b9_a504, + &pci_dev_info_14b9_a505, + &pci_dev_info_14b9_a506, + NULL +}; +#endif +#define pci_dev_list_14ba NULL +#define pci_dev_list_14bb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14bc[] = { + &pci_dev_info_14bc_d002, + &pci_dev_info_14bc_d00f, + NULL +}; +#endif +#define pci_dev_list_14bd NULL +#define pci_dev_list_14be NULL +#define pci_dev_list_14bf NULL +#define pci_dev_list_14c0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14c1[] = { + &pci_dev_info_14c1_0008, + &pci_dev_info_14c1_8043, + NULL +}; +#endif +#define pci_dev_list_14c2 NULL +#define pci_dev_list_14c3 NULL +#define pci_dev_list_14c4 NULL +#define pci_dev_list_14c5 NULL +#define pci_dev_list_14c6 NULL +#define pci_dev_list_14c7 NULL +#define pci_dev_list_14c8 NULL +#define pci_dev_list_14c9 NULL +#define pci_dev_list_14ca NULL +#define pci_dev_list_14cb NULL +#define pci_dev_list_14cc NULL +#define pci_dev_list_14cd NULL +#define pci_dev_list_14ce NULL +#define pci_dev_list_14cf NULL +#define pci_dev_list_14d0 NULL +#define pci_dev_list_14d1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14d2[] = { + &pci_dev_info_14d2_8001, + &pci_dev_info_14d2_8002, + &pci_dev_info_14d2_8010, + &pci_dev_info_14d2_8011, + &pci_dev_info_14d2_8020, + &pci_dev_info_14d2_8021, + &pci_dev_info_14d2_8040, + &pci_dev_info_14d2_8080, + &pci_dev_info_14d2_a000, + &pci_dev_info_14d2_a001, + &pci_dev_info_14d2_a003, + &pci_dev_info_14d2_a004, + &pci_dev_info_14d2_a005, + &pci_dev_info_14d2_e001, + &pci_dev_info_14d2_e010, + &pci_dev_info_14d2_e020, + NULL +}; +#endif +#define pci_dev_list_14d3 NULL +#define pci_dev_list_14d4 NULL +#define pci_dev_list_14d5 NULL +#define pci_dev_list_14d6 NULL +#define pci_dev_list_14d7 NULL +#define pci_dev_list_14d8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14d9[] = { + &pci_dev_info_14d9_0010, + &pci_dev_info_14d9_9000, + NULL +}; +#endif +#define pci_dev_list_14da NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14db[] = { + &pci_dev_info_14db_2120, + &pci_dev_info_14db_2182, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14dc[] = { + &pci_dev_info_14dc_0000, + &pci_dev_info_14dc_0001, + &pci_dev_info_14dc_0002, + &pci_dev_info_14dc_0003, + &pci_dev_info_14dc_0004, + &pci_dev_info_14dc_0005, + &pci_dev_info_14dc_0006, + &pci_dev_info_14dc_0007, + &pci_dev_info_14dc_0008, + &pci_dev_info_14dc_0009, + &pci_dev_info_14dc_000a, + &pci_dev_info_14dc_000b, + NULL +}; +#endif +#define pci_dev_list_14dd NULL +#define pci_dev_list_14de NULL +#define pci_dev_list_14df NULL +#define pci_dev_list_14e1 NULL +#define pci_dev_list_14e2 NULL +#define pci_dev_list_14e3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14e4[] = { + &pci_dev_info_14e4_0800, + &pci_dev_info_14e4_0804, + &pci_dev_info_14e4_0805, + &pci_dev_info_14e4_0806, + &pci_dev_info_14e4_080b, + &pci_dev_info_14e4_080f, + &pci_dev_info_14e4_0811, + &pci_dev_info_14e4_0816, + &pci_dev_info_14e4_1600, + &pci_dev_info_14e4_1601, + &pci_dev_info_14e4_1644, + &pci_dev_info_14e4_1645, + &pci_dev_info_14e4_1646, + &pci_dev_info_14e4_1647, + &pci_dev_info_14e4_1648, + &pci_dev_info_14e4_164a, + &pci_dev_info_14e4_164c, + &pci_dev_info_14e4_164d, + &pci_dev_info_14e4_1653, + &pci_dev_info_14e4_1654, + &pci_dev_info_14e4_1659, + &pci_dev_info_14e4_165d, + &pci_dev_info_14e4_165e, + &pci_dev_info_14e4_1668, + &pci_dev_info_14e4_1669, + &pci_dev_info_14e4_166a, + &pci_dev_info_14e4_166b, + &pci_dev_info_14e4_166e, + &pci_dev_info_14e4_1672, + &pci_dev_info_14e4_1673, + &pci_dev_info_14e4_1677, + &pci_dev_info_14e4_1678, + &pci_dev_info_14e4_1679, + &pci_dev_info_14e4_167a, + &pci_dev_info_14e4_167b, + &pci_dev_info_14e4_167d, + &pci_dev_info_14e4_167e, + &pci_dev_info_14e4_1693, + &pci_dev_info_14e4_1696, + &pci_dev_info_14e4_169a, + &pci_dev_info_14e4_169b, + &pci_dev_info_14e4_169c, + &pci_dev_info_14e4_169d, + &pci_dev_info_14e4_16a6, + &pci_dev_info_14e4_16a7, + &pci_dev_info_14e4_16a8, + &pci_dev_info_14e4_16aa, + &pci_dev_info_14e4_16ac, + &pci_dev_info_14e4_16c6, + &pci_dev_info_14e4_16c7, + &pci_dev_info_14e4_16dd, + &pci_dev_info_14e4_16f7, + &pci_dev_info_14e4_16fd, + &pci_dev_info_14e4_16fe, + &pci_dev_info_14e4_170c, + &pci_dev_info_14e4_170d, + &pci_dev_info_14e4_170e, + &pci_dev_info_14e4_3352, + &pci_dev_info_14e4_3360, + &pci_dev_info_14e4_4210, + &pci_dev_info_14e4_4211, + &pci_dev_info_14e4_4212, + &pci_dev_info_14e4_4301, + &pci_dev_info_14e4_4305, + &pci_dev_info_14e4_4306, + &pci_dev_info_14e4_4307, + &pci_dev_info_14e4_4310, + &pci_dev_info_14e4_4311, + &pci_dev_info_14e4_4312, + &pci_dev_info_14e4_4313, + &pci_dev_info_14e4_4315, + &pci_dev_info_14e4_4318, + &pci_dev_info_14e4_4319, + &pci_dev_info_14e4_4320, + &pci_dev_info_14e4_4321, + &pci_dev_info_14e4_4322, + &pci_dev_info_14e4_4324, + &pci_dev_info_14e4_4325, + &pci_dev_info_14e4_4326, + &pci_dev_info_14e4_4329, + &pci_dev_info_14e4_4401, + &pci_dev_info_14e4_4402, + &pci_dev_info_14e4_4403, + &pci_dev_info_14e4_4410, + &pci_dev_info_14e4_4411, + &pci_dev_info_14e4_4412, + &pci_dev_info_14e4_4430, + &pci_dev_info_14e4_4432, + &pci_dev_info_14e4_4610, + &pci_dev_info_14e4_4611, + &pci_dev_info_14e4_4612, + &pci_dev_info_14e4_4613, + &pci_dev_info_14e4_4614, + &pci_dev_info_14e4_4615, + &pci_dev_info_14e4_4704, + &pci_dev_info_14e4_4705, + &pci_dev_info_14e4_4706, + &pci_dev_info_14e4_4707, + &pci_dev_info_14e4_4708, + &pci_dev_info_14e4_4710, + &pci_dev_info_14e4_4711, + &pci_dev_info_14e4_4712, + &pci_dev_info_14e4_4713, + &pci_dev_info_14e4_4714, + &pci_dev_info_14e4_4715, + &pci_dev_info_14e4_4716, + &pci_dev_info_14e4_4717, + &pci_dev_info_14e4_4718, + &pci_dev_info_14e4_4719, + &pci_dev_info_14e4_4720, + &pci_dev_info_14e4_5365, + &pci_dev_info_14e4_5600, + &pci_dev_info_14e4_5605, + &pci_dev_info_14e4_5615, + &pci_dev_info_14e4_5625, + &pci_dev_info_14e4_5645, + &pci_dev_info_14e4_5670, + &pci_dev_info_14e4_5680, + &pci_dev_info_14e4_5690, + &pci_dev_info_14e4_5691, + &pci_dev_info_14e4_5692, + &pci_dev_info_14e4_5820, + &pci_dev_info_14e4_5821, + &pci_dev_info_14e4_5822, + &pci_dev_info_14e4_5823, + &pci_dev_info_14e4_5824, + &pci_dev_info_14e4_5840, + &pci_dev_info_14e4_5841, + &pci_dev_info_14e4_5850, + NULL +}; +#endif +#define pci_dev_list_14e5 NULL +#define pci_dev_list_14e6 NULL +#define pci_dev_list_14e7 NULL +#define pci_dev_list_14e8 NULL +#define pci_dev_list_14e9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14ea[] = { + &pci_dev_info_14ea_ab06, + &pci_dev_info_14ea_ab07, + &pci_dev_info_14ea_ab08, + NULL +}; +#endif +#define pci_dev_list_14eb NULL +#define pci_dev_list_14ec NULL +#define pci_dev_list_14ed NULL +#define pci_dev_list_14ee NULL +#define pci_dev_list_14ef NULL +#define pci_dev_list_14f0 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14f1[] = { + &pci_dev_info_14f1_1002, + &pci_dev_info_14f1_1003, + &pci_dev_info_14f1_1004, + &pci_dev_info_14f1_1005, + &pci_dev_info_14f1_1006, + &pci_dev_info_14f1_1022, + &pci_dev_info_14f1_1023, + &pci_dev_info_14f1_1024, + &pci_dev_info_14f1_1025, + &pci_dev_info_14f1_1026, + &pci_dev_info_14f1_1032, + &pci_dev_info_14f1_1033, + &pci_dev_info_14f1_1034, + &pci_dev_info_14f1_1035, + &pci_dev_info_14f1_1036, + &pci_dev_info_14f1_1052, + &pci_dev_info_14f1_1053, + &pci_dev_info_14f1_1054, + &pci_dev_info_14f1_1055, + &pci_dev_info_14f1_1056, + &pci_dev_info_14f1_1057, + &pci_dev_info_14f1_1059, + &pci_dev_info_14f1_1063, + &pci_dev_info_14f1_1064, + &pci_dev_info_14f1_1065, + &pci_dev_info_14f1_1066, + &pci_dev_info_14f1_1085, + &pci_dev_info_14f1_1433, + &pci_dev_info_14f1_1434, + &pci_dev_info_14f1_1435, + &pci_dev_info_14f1_1436, + &pci_dev_info_14f1_1453, + &pci_dev_info_14f1_1454, + &pci_dev_info_14f1_1455, + &pci_dev_info_14f1_1456, + &pci_dev_info_14f1_1610, + &pci_dev_info_14f1_1611, + &pci_dev_info_14f1_1620, + &pci_dev_info_14f1_1621, + &pci_dev_info_14f1_1622, + &pci_dev_info_14f1_1803, + &pci_dev_info_14f1_1811, + &pci_dev_info_14f1_1815, + &pci_dev_info_14f1_2003, + &pci_dev_info_14f1_2004, + &pci_dev_info_14f1_2005, + &pci_dev_info_14f1_2006, + &pci_dev_info_14f1_2013, + &pci_dev_info_14f1_2014, + &pci_dev_info_14f1_2015, + &pci_dev_info_14f1_2016, + &pci_dev_info_14f1_2043, + &pci_dev_info_14f1_2044, + &pci_dev_info_14f1_2045, + &pci_dev_info_14f1_2046, + &pci_dev_info_14f1_2063, + &pci_dev_info_14f1_2064, + &pci_dev_info_14f1_2065, + &pci_dev_info_14f1_2066, + &pci_dev_info_14f1_2093, + &pci_dev_info_14f1_2143, + &pci_dev_info_14f1_2144, + &pci_dev_info_14f1_2145, + &pci_dev_info_14f1_2146, + &pci_dev_info_14f1_2163, + &pci_dev_info_14f1_2164, + &pci_dev_info_14f1_2165, + &pci_dev_info_14f1_2166, + &pci_dev_info_14f1_2343, + &pci_dev_info_14f1_2344, + &pci_dev_info_14f1_2345, + &pci_dev_info_14f1_2346, + &pci_dev_info_14f1_2363, + &pci_dev_info_14f1_2364, + &pci_dev_info_14f1_2365, + &pci_dev_info_14f1_2366, + &pci_dev_info_14f1_2443, + &pci_dev_info_14f1_2444, + &pci_dev_info_14f1_2445, + &pci_dev_info_14f1_2446, + &pci_dev_info_14f1_2463, + &pci_dev_info_14f1_2464, + &pci_dev_info_14f1_2465, + &pci_dev_info_14f1_2466, + &pci_dev_info_14f1_2bfa, + &pci_dev_info_14f1_2f00, + &pci_dev_info_14f1_2f02, + &pci_dev_info_14f1_2f11, + &pci_dev_info_14f1_2f20, + &pci_dev_info_14f1_8234, + &pci_dev_info_14f1_8800, + &pci_dev_info_14f1_8801, + &pci_dev_info_14f1_8802, + &pci_dev_info_14f1_8804, + &pci_dev_info_14f1_8811, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14f2[] = { + &pci_dev_info_14f2_0120, + &pci_dev_info_14f2_0121, + &pci_dev_info_14f2_0122, + &pci_dev_info_14f2_0123, + &pci_dev_info_14f2_0124, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14f3[] = { + &pci_dev_info_14f3_2030, + &pci_dev_info_14f3_2050, + &pci_dev_info_14f3_2060, + NULL +}; +#endif +#define pci_dev_list_14f4 NULL +#define pci_dev_list_14f5 NULL +#define pci_dev_list_14f6 NULL +#define pci_dev_list_14f7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14f8[] = { + &pci_dev_info_14f8_2077, + NULL +}; +#endif +#define pci_dev_list_14f9 NULL +#define pci_dev_list_14fa NULL +#define pci_dev_list_14fb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_14fc[] = { + &pci_dev_info_14fc_0000, + &pci_dev_info_14fc_0001, + &pci_dev_info_14fc_0002, + NULL +}; +#endif +#define pci_dev_list_14fd NULL +#define pci_dev_list_14fe NULL +#define pci_dev_list_14ff NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1500[] = { + &pci_dev_info_1500_1360, + NULL +}; +#endif +#define pci_dev_list_1501 NULL +#define pci_dev_list_1502 NULL +#define pci_dev_list_1503 NULL +#define pci_dev_list_1504 NULL +#define pci_dev_list_1505 NULL +#define pci_dev_list_1506 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1507[] = { + &pci_dev_info_1507_0001, + &pci_dev_info_1507_0002, + &pci_dev_info_1507_0003, + &pci_dev_info_1507_0100, + &pci_dev_info_1507_0431, + &pci_dev_info_1507_4801, + &pci_dev_info_1507_4802, + &pci_dev_info_1507_4803, + &pci_dev_info_1507_4806, + NULL +}; +#endif +#define pci_dev_list_1508 NULL +#define pci_dev_list_1509 NULL +#define pci_dev_list_150a NULL +#define pci_dev_list_150b NULL +#define pci_dev_list_150c NULL +#define pci_dev_list_150d NULL +#define pci_dev_list_150e NULL +#define pci_dev_list_150f NULL +#define pci_dev_list_1510 NULL +#define pci_dev_list_1511 NULL +#define pci_dev_list_1512 NULL +#define pci_dev_list_1513 NULL +#define pci_dev_list_1514 NULL +#define pci_dev_list_1515 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1516[] = { + &pci_dev_info_1516_0800, + &pci_dev_info_1516_0803, + &pci_dev_info_1516_0891, + NULL +}; +#endif +#define pci_dev_list_1517 NULL +#define pci_dev_list_1518 NULL +#define pci_dev_list_1519 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_151a[] = { + &pci_dev_info_151a_1002, + &pci_dev_info_151a_1004, + &pci_dev_info_151a_1008, + NULL +}; +#endif +#define pci_dev_list_151b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_151c[] = { + &pci_dev_info_151c_0003, + &pci_dev_info_151c_4000, + NULL +}; +#endif +#define pci_dev_list_151d NULL +#define pci_dev_list_151e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_151f[] = { + &pci_dev_info_151f_0000, + NULL +}; +#endif +#define pci_dev_list_1520 NULL +#define pci_dev_list_1521 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1522[] = { + &pci_dev_info_1522_0100, + NULL +}; +#endif +#define pci_dev_list_1523 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1524[] = { + &pci_dev_info_1524_0510, + &pci_dev_info_1524_0520, + &pci_dev_info_1524_0530, + &pci_dev_info_1524_0550, + &pci_dev_info_1524_0610, + &pci_dev_info_1524_1211, + &pci_dev_info_1524_1225, + &pci_dev_info_1524_1410, + &pci_dev_info_1524_1411, + &pci_dev_info_1524_1412, + &pci_dev_info_1524_1420, + &pci_dev_info_1524_1421, + &pci_dev_info_1524_1422, + NULL +}; +#endif +#define pci_dev_list_1525 NULL +#define pci_dev_list_1526 NULL +#define pci_dev_list_1527 NULL +#define pci_dev_list_1528 NULL +#define pci_dev_list_1529 NULL +#define pci_dev_list_152a NULL +#define pci_dev_list_152b NULL +#define pci_dev_list_152c NULL +#define pci_dev_list_152d NULL +#define pci_dev_list_152e NULL +#define pci_dev_list_152f NULL +#define pci_dev_list_1530 NULL +#define pci_dev_list_1531 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1532[] = { + &pci_dev_info_1532_0020, + NULL +}; +#endif +#define pci_dev_list_1533 NULL +#define pci_dev_list_1534 NULL +#define pci_dev_list_1535 NULL +#define pci_dev_list_1537 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1538[] = { + &pci_dev_info_1538_0303, + NULL +}; +#endif +#define pci_dev_list_1539 NULL +#define pci_dev_list_153a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_153b[] = { + &pci_dev_info_153b_1144, + &pci_dev_info_153b_1147, + &pci_dev_info_153b_1158, + NULL +}; +#endif +#define pci_dev_list_153c NULL +#define pci_dev_list_153d NULL +#define pci_dev_list_153e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_153f[] = { + &pci_dev_info_153f_0001, + NULL +}; +#endif +#define pci_dev_list_1540 NULL +#define pci_dev_list_1541 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1542[] = { + &pci_dev_info_1542_9260, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1543[] = { + &pci_dev_info_1543_3052, + &pci_dev_info_1543_4c22, + NULL +}; +#endif +#define pci_dev_list_1544 NULL +#define pci_dev_list_1545 NULL +#define pci_dev_list_1546 NULL +#define pci_dev_list_1547 NULL +#define pci_dev_list_1548 NULL +#define pci_dev_list_1549 NULL +#define pci_dev_list_154a NULL +#define pci_dev_list_154b NULL +#define pci_dev_list_154c NULL +#define pci_dev_list_154d NULL +#define pci_dev_list_154e NULL +#define pci_dev_list_154f NULL +#define pci_dev_list_1550 NULL +#define pci_dev_list_1551 NULL +#define pci_dev_list_1552 NULL +#define pci_dev_list_1553 NULL +#define pci_dev_list_1554 NULL +#define pci_dev_list_1555 NULL +#define pci_dev_list_1556 NULL +#define pci_dev_list_1557 NULL +#define pci_dev_list_1558 NULL +#define pci_dev_list_1559 NULL +#define pci_dev_list_155a NULL +#define pci_dev_list_155b NULL +#define pci_dev_list_155c NULL +#define pci_dev_list_155d NULL +#define pci_dev_list_155e NULL +#define pci_dev_list_155f NULL +#define pci_dev_list_1560 NULL +#define pci_dev_list_1561 NULL +#define pci_dev_list_1562 NULL +#define pci_dev_list_1563 NULL +#define pci_dev_list_1564 NULL +#define pci_dev_list_1565 NULL +#define pci_dev_list_1566 NULL +#define pci_dev_list_1567 NULL +#define pci_dev_list_1568 NULL +#define pci_dev_list_1569 NULL +#define pci_dev_list_156a NULL +#define pci_dev_list_156b NULL +#define pci_dev_list_156c NULL +#define pci_dev_list_156d NULL +#define pci_dev_list_156e NULL +#define pci_dev_list_156f NULL +#define pci_dev_list_1570 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1571[] = { + &pci_dev_info_1571_a001, + &pci_dev_info_1571_a002, + &pci_dev_info_1571_a003, + &pci_dev_info_1571_a004, + &pci_dev_info_1571_a005, + &pci_dev_info_1571_a006, + &pci_dev_info_1571_a007, + &pci_dev_info_1571_a008, + &pci_dev_info_1571_a009, + &pci_dev_info_1571_a00a, + &pci_dev_info_1571_a00b, + &pci_dev_info_1571_a00c, + &pci_dev_info_1571_a00d, + &pci_dev_info_1571_a201, + &pci_dev_info_1571_a202, + &pci_dev_info_1571_a203, + &pci_dev_info_1571_a204, + &pci_dev_info_1571_a205, + &pci_dev_info_1571_a206, + NULL +}; +#endif +#define pci_dev_list_1572 NULL +#define pci_dev_list_1573 NULL +#define pci_dev_list_1574 NULL +#define pci_dev_list_1575 NULL +#define pci_dev_list_1576 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1578[] = { + &pci_dev_info_1578_5615, + NULL +}; +#endif +#define pci_dev_list_1579 NULL +#define pci_dev_list_157a NULL +#define pci_dev_list_157b NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_157c[] = { + &pci_dev_info_157c_8001, + NULL +}; +#endif +#define pci_dev_list_157d NULL +#define pci_dev_list_157e NULL +#define pci_dev_list_157f NULL +#define pci_dev_list_1580 NULL +#define pci_dev_list_1581 NULL +#define pci_dev_list_1582 NULL +#define pci_dev_list_1583 NULL +#define pci_dev_list_1584 NULL +#define pci_dev_list_1585 NULL +#define pci_dev_list_1586 NULL +#define pci_dev_list_1587 NULL +#define pci_dev_list_1588 NULL +#define pci_dev_list_1589 NULL +#define pci_dev_list_158a NULL +#define pci_dev_list_158b NULL +#define pci_dev_list_158c NULL +#define pci_dev_list_158d NULL +#define pci_dev_list_158e NULL +#define pci_dev_list_158f NULL +#define pci_dev_list_1590 NULL +#define pci_dev_list_1591 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1592[] = { + &pci_dev_info_1592_0781, + &pci_dev_info_1592_0782, + &pci_dev_info_1592_0783, + &pci_dev_info_1592_0785, + &pci_dev_info_1592_0786, + &pci_dev_info_1592_0787, + &pci_dev_info_1592_0788, + &pci_dev_info_1592_078a, + NULL +}; +#endif +#define pci_dev_list_1593 NULL +#define pci_dev_list_1594 NULL +#define pci_dev_list_1595 NULL +#define pci_dev_list_1596 NULL +#define pci_dev_list_1597 NULL +#define pci_dev_list_1598 NULL +#define pci_dev_list_1599 NULL +#define pci_dev_list_159a NULL +#define pci_dev_list_159b NULL +#define pci_dev_list_159c NULL +#define pci_dev_list_159d NULL +#define pci_dev_list_159e NULL +#define pci_dev_list_159f NULL +#define pci_dev_list_15a0 NULL +#define pci_dev_list_15a1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15a2[] = { + &pci_dev_info_15a2_0001, + NULL +}; +#endif +#define pci_dev_list_15a3 NULL +#define pci_dev_list_15a4 NULL +#define pci_dev_list_15a5 NULL +#define pci_dev_list_15a6 NULL +#define pci_dev_list_15a7 NULL +#define pci_dev_list_15a8 NULL +#define pci_dev_list_15aa NULL +#define pci_dev_list_15ab NULL +#define pci_dev_list_15ac NULL +static const pciDeviceInfo *pci_dev_list_15ad[] = { + &pci_dev_info_15ad_0405, + &pci_dev_info_15ad_0710, + &pci_dev_info_15ad_0720, + NULL +}; +#define pci_dev_list_15ae NULL +#define pci_dev_list_15b0 NULL +#define pci_dev_list_15b1 NULL +#define pci_dev_list_15b2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15b3[] = { + &pci_dev_info_15b3_5274, + &pci_dev_info_15b3_5a44, + &pci_dev_info_15b3_5a45, + &pci_dev_info_15b3_5a46, + &pci_dev_info_15b3_5e8d, + &pci_dev_info_15b3_6274, + &pci_dev_info_15b3_6278, + &pci_dev_info_15b3_6279, + &pci_dev_info_15b3_6282, + NULL +}; +#endif +#define pci_dev_list_15b4 NULL +#define pci_dev_list_15b5 NULL +#define pci_dev_list_15b6 NULL +#define pci_dev_list_15b7 NULL +#define pci_dev_list_15b8 NULL +#define pci_dev_list_15b9 NULL +#define pci_dev_list_15ba NULL +#define pci_dev_list_15bb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15bc[] = { + &pci_dev_info_15bc_1100, + &pci_dev_info_15bc_2922, + &pci_dev_info_15bc_2928, + &pci_dev_info_15bc_2929, + NULL +}; +#endif +#define pci_dev_list_15bd NULL +#define pci_dev_list_15be NULL +#define pci_dev_list_15bf NULL +#define pci_dev_list_15c0 NULL +#define pci_dev_list_15c1 NULL +#define pci_dev_list_15c2 NULL +#define pci_dev_list_15c3 NULL +#define pci_dev_list_15c4 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15c5[] = { + &pci_dev_info_15c5_8010, + NULL +}; +#endif +#define pci_dev_list_15c6 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15c7[] = { + &pci_dev_info_15c7_0349, + NULL +}; +#endif +#define pci_dev_list_15c8 NULL +#define pci_dev_list_15c9 NULL +#define pci_dev_list_15ca NULL +#define pci_dev_list_15cb NULL +#define pci_dev_list_15cc NULL +#define pci_dev_list_15cd NULL +#define pci_dev_list_15ce NULL +#define pci_dev_list_15cf NULL +#define pci_dev_list_15d1 NULL +#define pci_dev_list_15d2 NULL +#define pci_dev_list_15d3 NULL +#define pci_dev_list_15d4 NULL +#define pci_dev_list_15d5 NULL +#define pci_dev_list_15d6 NULL +#define pci_dev_list_15d7 NULL +#define pci_dev_list_15d8 NULL +#define pci_dev_list_15d9 NULL +#define pci_dev_list_15da NULL +#define pci_dev_list_15db NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15dc[] = { + &pci_dev_info_15dc_0001, + NULL +}; +#endif +#define pci_dev_list_15dd NULL +#define pci_dev_list_15de NULL +#define pci_dev_list_15df NULL +#define pci_dev_list_15e0 NULL +#define pci_dev_list_15e1 NULL +#define pci_dev_list_15e2 NULL +#define pci_dev_list_15e3 NULL +#define pci_dev_list_15e4 NULL +#define pci_dev_list_15e5 NULL +#define pci_dev_list_15e6 NULL +#define pci_dev_list_15e7 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15e8[] = { + &pci_dev_info_15e8_0130, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15e9[] = { + &pci_dev_info_15e9_1841, + NULL +}; +#endif +#define pci_dev_list_15ea NULL +#define pci_dev_list_15eb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_15ec[] = { + &pci_dev_info_15ec_3101, + &pci_dev_info_15ec_5102, + NULL +}; +#endif +#define pci_dev_list_15ed NULL +#define pci_dev_list_15ee NULL +#define pci_dev_list_15ef NULL +#define pci_dev_list_15f0 NULL +#define pci_dev_list_15f1 NULL +#define pci_dev_list_15f2 NULL +#define pci_dev_list_15f3 NULL +#define pci_dev_list_15f4 NULL +#define pci_dev_list_15f5 NULL +#define pci_dev_list_15f6 NULL +#define pci_dev_list_15f7 NULL +#define pci_dev_list_15f8 NULL +#define pci_dev_list_15f9 NULL +#define pci_dev_list_15fa NULL +#define pci_dev_list_15fb NULL +#define pci_dev_list_15fc NULL +#define pci_dev_list_15fd NULL +#define pci_dev_list_15fe NULL +#define pci_dev_list_15ff NULL +#define pci_dev_list_1600 NULL +#define pci_dev_list_1601 NULL +#define pci_dev_list_1602 NULL +#define pci_dev_list_1603 NULL +#define pci_dev_list_1604 NULL +#define pci_dev_list_1605 NULL +#define pci_dev_list_1606 NULL +#define pci_dev_list_1607 NULL +#define pci_dev_list_1608 NULL +#define pci_dev_list_1609 NULL +#define pci_dev_list_1612 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1619[] = { + &pci_dev_info_1619_0400, + &pci_dev_info_1619_0440, + &pci_dev_info_1619_0610, + &pci_dev_info_1619_0620, + &pci_dev_info_1619_0640, + &pci_dev_info_1619_1610, + &pci_dev_info_1619_2610, + NULL +}; +#endif +#define pci_dev_list_161f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1626[] = { + &pci_dev_info_1626_8410, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1629[] = { + &pci_dev_info_1629_1003, + &pci_dev_info_1629_2002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1637[] = { + &pci_dev_info_1637_3874, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1638[] = { + &pci_dev_info_1638_1100, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_163c[] = { + &pci_dev_info_163c_3052, + &pci_dev_info_163c_5449, + NULL +}; +#endif +#define pci_dev_list_1657 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_165a[] = { + &pci_dev_info_165a_c100, + &pci_dev_info_165a_d200, + &pci_dev_info_165a_d300, + NULL +}; +#endif +#define pci_dev_list_165d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_165f[] = { + &pci_dev_info_165f_1020, + NULL +}; +#endif +#define pci_dev_list_1661 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1668[] = { + &pci_dev_info_1668_0100, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_166d[] = { + &pci_dev_info_166d_0001, + &pci_dev_info_166d_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1677[] = { + &pci_dev_info_1677_104e, + &pci_dev_info_1677_12d7, + &pci_dev_info_1677_20ad, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_167b[] = { + &pci_dev_info_167b_2102, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_167d[] = { + &pci_dev_info_167d_a000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1681[] = { + &pci_dev_info_1681_0010, + NULL +}; +#endif +#define pci_dev_list_1682 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1688[] = { + &pci_dev_info_1688_1170, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_168c[] = { + &pci_dev_info_168c_0007, + &pci_dev_info_168c_0011, + &pci_dev_info_168c_0012, + &pci_dev_info_168c_0013, + &pci_dev_info_168c_001a, + &pci_dev_info_168c_001b, + &pci_dev_info_168c_0020, + &pci_dev_info_168c_1014, + NULL +}; +#endif +#define pci_dev_list_1695 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_169c[] = { + &pci_dev_info_169c_0044, + NULL +}; +#endif +#define pci_dev_list_16a5 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16ab[] = { + &pci_dev_info_16ab_1100, + &pci_dev_info_16ab_1101, + &pci_dev_info_16ab_1102, + &pci_dev_info_16ab_8501, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16ae[] = { + &pci_dev_info_16ae_1141, + NULL +}; +#endif +#define pci_dev_list_16af NULL +#define pci_dev_list_16b4 NULL +#define pci_dev_list_16b8 NULL +#define pci_dev_list_16be NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16c6[] = { + &pci_dev_info_16c6_8695, + NULL +}; +#endif +#define pci_dev_list_16c8 NULL +#define pci_dev_list_16c9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16ca[] = { + &pci_dev_info_16ca_0001, + NULL +}; +#endif +#define pci_dev_list_16cd NULL +#define pci_dev_list_16ce NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16d5[] = { + &pci_dev_info_16d5_4d4e, + NULL +}; +#endif +#define pci_dev_list_16df NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16e3[] = { + &pci_dev_info_16e3_1e0f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16e5[] = { + &pci_dev_info_16e5_6000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16ec[] = { + &pci_dev_info_16ec_00ff, + &pci_dev_info_16ec_0116, + &pci_dev_info_16ec_2f00, + &pci_dev_info_16ec_3685, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16ed[] = { + &pci_dev_info_16ed_1001, + NULL +}; +#endif +#define pci_dev_list_16f3 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_16f4[] = { + &pci_dev_info_16f4_8000, + NULL +}; +#endif +#define pci_dev_list_16f6 NULL +#define pci_dev_list_1702 NULL +#define pci_dev_list_1705 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_170b[] = { + &pci_dev_info_170b_0100, + NULL +}; +#endif +#define pci_dev_list_170c NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1725[] = { + &pci_dev_info_1725_7174, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_172a[] = { + &pci_dev_info_172a_13c8, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1734[] = { + &pci_dev_info_1734_1078, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1737[] = { + &pci_dev_info_1737_0013, + &pci_dev_info_1737_0015, + &pci_dev_info_1737_1032, + &pci_dev_info_1737_1064, + &pci_dev_info_1737_ab08, + &pci_dev_info_1737_ab09, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_173b[] = { + &pci_dev_info_173b_03e8, + &pci_dev_info_173b_03e9, + &pci_dev_info_173b_03ea, + &pci_dev_info_173b_03eb, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1743[] = { + &pci_dev_info_1743_8139, + NULL +}; +#endif +#define pci_dev_list_1749 NULL +#define pci_dev_list_174b NULL +#define pci_dev_list_174d NULL +#define pci_dev_list_175c NULL +#define pci_dev_list_175e NULL +#define pci_dev_list_1775 NULL +#define pci_dev_list_1787 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1796[] = { + &pci_dev_info_1796_0001, + &pci_dev_info_1796_0002, + &pci_dev_info_1796_0003, + &pci_dev_info_1796_0004, + &pci_dev_info_1796_0005, + &pci_dev_info_1796_0006, + NULL +}; +#endif +#define pci_dev_list_1797 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1799[] = { + &pci_dev_info_1799_6001, + &pci_dev_info_1799_6020, + &pci_dev_info_1799_6060, + &pci_dev_info_1799_7000, + &pci_dev_info_1799_700a, + &pci_dev_info_1799_7010, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_179c[] = { + &pci_dev_info_179c_0557, + &pci_dev_info_179c_0566, + &pci_dev_info_179c_5031, + &pci_dev_info_179c_5121, + &pci_dev_info_179c_5211, + &pci_dev_info_179c_5679, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17a0[] = { + &pci_dev_info_17a0_8033, + &pci_dev_info_17a0_8034, + NULL +}; +#endif +#define pci_dev_list_17aa NULL +#define pci_dev_list_17af NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17b3[] = { + &pci_dev_info_17b3_ab08, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17b4[] = { + &pci_dev_info_17b4_0011, + NULL +}; +#endif +#define pci_dev_list_17c0 NULL +#define pci_dev_list_17c2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17cb[] = { + &pci_dev_info_17cb_0001, + &pci_dev_info_17cb_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17cc[] = { + &pci_dev_info_17cc_2280, + NULL +}; +#endif +#define pci_dev_list_17cf NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17d3[] = { + &pci_dev_info_17d3_1110, + &pci_dev_info_17d3_1120, + &pci_dev_info_17d3_1130, + &pci_dev_info_17d3_1160, + &pci_dev_info_17d3_1210, + &pci_dev_info_17d3_1220, + &pci_dev_info_17d3_1230, + &pci_dev_info_17d3_1260, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17d5[] = { + &pci_dev_info_17d5_5831, + &pci_dev_info_17d5_5832, + NULL +}; +#endif +#define pci_dev_list_17db NULL +#define pci_dev_list_17de NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17e4[] = { + &pci_dev_info_17e4_0001, + &pci_dev_info_17e4_0002, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17e6[] = { + &pci_dev_info_17e6_0010, + &pci_dev_info_17e6_0011, + &pci_dev_info_17e6_0021, + NULL +}; +#endif +#define pci_dev_list_17ee NULL +#define pci_dev_list_17f2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_17fe[] = { + &pci_dev_info_17fe_2120, + &pci_dev_info_17fe_2220, + NULL +}; +#endif +#define pci_dev_list_17ff NULL +#define pci_dev_list_1809 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1813[] = { + &pci_dev_info_1813_4000, + &pci_dev_info_1813_4100, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1814[] = { + &pci_dev_info_1814_0101, + &pci_dev_info_1814_0200, + &pci_dev_info_1814_0201, + &pci_dev_info_1814_0301, + &pci_dev_info_1814_0302, + &pci_dev_info_1814_0401, + NULL +}; +#endif +#define pci_dev_list_1820 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1822[] = { + &pci_dev_info_1822_4e35, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_182d[] = { + &pci_dev_info_182d_3069, + &pci_dev_info_182d_9790, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_182e[] = { + &pci_dev_info_182e_0008, + NULL +}; +#endif +#define pci_dev_list_1830 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_183b[] = { + &pci_dev_info_183b_08a7, + &pci_dev_info_183b_08a8, + &pci_dev_info_183b_08a9, + &pci_dev_info_183b_08b0, + NULL +}; +#endif +#define pci_dev_list_1849 NULL +#define pci_dev_list_184a NULL +#define pci_dev_list_1851 NULL +#define pci_dev_list_1852 NULL +#define pci_dev_list_1853 NULL +#define pci_dev_list_1854 NULL +#define pci_dev_list_185b NULL +#define pci_dev_list_185f NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1864[] = { + &pci_dev_info_1864_2110, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1867[] = { + &pci_dev_info_1867_5a44, + &pci_dev_info_1867_5a45, + &pci_dev_info_1867_5a46, + &pci_dev_info_1867_6278, + &pci_dev_info_1867_6282, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_187e[] = { + &pci_dev_info_187e_3403, + &pci_dev_info_187e_340e, + NULL +}; +#endif +#define pci_dev_list_1885 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1888[] = { + &pci_dev_info_1888_0301, + &pci_dev_info_1888_0601, + &pci_dev_info_1888_0710, + &pci_dev_info_1888_0720, + NULL +}; +#endif +#define pci_dev_list_188a NULL +#define pci_dev_list_1890 NULL +#define pci_dev_list_1894 NULL +#define pci_dev_list_1896 NULL +#define pci_dev_list_18a1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18ac[] = { + &pci_dev_info_18ac_d500, + &pci_dev_info_18ac_d800, + &pci_dev_info_18ac_d810, + &pci_dev_info_18ac_d820, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18b8[] = { + &pci_dev_info_18b8_b001, + NULL +}; +#endif +#define pci_dev_list_18bc NULL +#define pci_dev_list_18c3 NULL +#define pci_dev_list_18c8 NULL +#define pci_dev_list_18c9 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18ca[] = { + &pci_dev_info_18ca_0020, + &pci_dev_info_18ca_0040, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18d2[] = { + &pci_dev_info_18d2_3069, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18dd[] = { + &pci_dev_info_18dd_4c6f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18e6[] = { + &pci_dev_info_18e6_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18ec[] = { + &pci_dev_info_18ec_c006, + &pci_dev_info_18ec_c045, + &pci_dev_info_18ec_c050, + &pci_dev_info_18ec_c058, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18f6[] = { + &pci_dev_info_18f6_1000, + &pci_dev_info_18f6_1050, + &pci_dev_info_18f6_2000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_18f7[] = { + &pci_dev_info_18f7_0001, + &pci_dev_info_18f7_0002, + &pci_dev_info_18f7_0004, + &pci_dev_info_18f7_0005, + &pci_dev_info_18f7_000a, + NULL +}; +#endif +#define pci_dev_list_18fb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1904[] = { + &pci_dev_info_1904_8139, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1923[] = { + &pci_dev_info_1923_0040, + &pci_dev_info_1923_0100, + &pci_dev_info_1923_0300, + &pci_dev_info_1923_0400, + NULL +}; +#endif +#define pci_dev_list_1924 NULL +#define pci_dev_list_192e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1931[] = { + &pci_dev_info_1931_000c, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1942[] = { + &pci_dev_info_1942_e511, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_194a[] = { + &pci_dev_info_194a_1111, + &pci_dev_info_194a_1112, + &pci_dev_info_194a_1113, + &pci_dev_info_194a_1114, + &pci_dev_info_194a_1115, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1957[] = { + &pci_dev_info_1957_0012, + &pci_dev_info_1957_0080, + &pci_dev_info_1957_0081, + &pci_dev_info_1957_0082, + &pci_dev_info_1957_0083, + &pci_dev_info_1957_0084, + &pci_dev_info_1957_0085, + &pci_dev_info_1957_0086, + &pci_dev_info_1957_0087, + NULL +}; +#endif +#define pci_dev_list_1958 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1966[] = { + &pci_dev_info_1966_1975, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1969[] = { + &pci_dev_info_1969_1048, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_196a[] = { + &pci_dev_info_196a_0101, + &pci_dev_info_196a_0102, + NULL +}; +#endif +#define pci_dev_list_196d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_197b[] = { + &pci_dev_info_197b_2360, + &pci_dev_info_197b_2361, + &pci_dev_info_197b_2363, + &pci_dev_info_197b_2365, + &pci_dev_info_197b_2366, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1989[] = { + &pci_dev_info_1989_0001, + &pci_dev_info_1989_8001, + NULL +}; +#endif +#define pci_dev_list_1993 NULL +#define pci_dev_list_199a NULL +#define pci_dev_list_19a8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_19ac[] = { + &pci_dev_info_19ac_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_19ae[] = { + &pci_dev_info_19ae_0520, + NULL +}; +#endif +#define pci_dev_list_19d4 NULL +#define pci_dev_list_19e2 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_19e7[] = { + &pci_dev_info_19e7_1001, + &pci_dev_info_19e7_1002, + &pci_dev_info_19e7_1003, + &pci_dev_info_19e7_1004, + &pci_dev_info_19e7_1005, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1a03[] = { + &pci_dev_info_1a03_2000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1a08[] = { + &pci_dev_info_1a08_0000, + NULL +}; +#endif +#define pci_dev_list_1a1d NULL +#define pci_dev_list_1a29 NULL +#define pci_dev_list_1a51 NULL +#define pci_dev_list_1b13 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1c1c[] = { + &pci_dev_info_1c1c_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1d44[] = { + &pci_dev_info_1d44_a400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1de1[] = { + &pci_dev_info_1de1_0391, + &pci_dev_info_1de1_2020, + &pci_dev_info_1de1_690c, + &pci_dev_info_1de1_dc29, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1fc0[] = { + &pci_dev_info_1fc0_0300, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1fc1[] = { + &pci_dev_info_1fc1_000d, + &pci_dev_info_1fc1_0010, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_1fce[] = { + &pci_dev_info_1fce_0001, + NULL +}; +#endif +#define pci_dev_list_2000 NULL +#define pci_dev_list_2001 NULL +#define pci_dev_list_2003 NULL +#define pci_dev_list_2004 NULL +#define pci_dev_list_21c3 NULL +#define pci_dev_list_22b8 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_2348[] = { + &pci_dev_info_2348_2010, + NULL +}; +#endif +#define pci_dev_list_2646 NULL +#define pci_dev_list_270b NULL +#define pci_dev_list_270f NULL +#define pci_dev_list_2711 NULL +#define pci_dev_list_2a15 NULL +#define pci_dev_list_3000 NULL +#define pci_dev_list_3142 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_3388[] = { + &pci_dev_info_3388_0013, + &pci_dev_info_3388_0014, + &pci_dev_info_3388_0020, + &pci_dev_info_3388_0021, + &pci_dev_info_3388_0022, + &pci_dev_info_3388_0026, + &pci_dev_info_3388_101a, + &pci_dev_info_3388_101b, + &pci_dev_info_3388_8011, + &pci_dev_info_3388_8012, + &pci_dev_info_3388_8013, + NULL +}; +#endif +#define pci_dev_list_3411 NULL +#define pci_dev_list_3513 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_3842[] = { + &pci_dev_info_3842_c370, + NULL +}; +#endif +#define pci_dev_list_38ef NULL +static const pciDeviceInfo *pci_dev_list_3d3d[] = { + &pci_dev_info_3d3d_0001, + &pci_dev_info_3d3d_0002, + &pci_dev_info_3d3d_0003, + &pci_dev_info_3d3d_0004, + &pci_dev_info_3d3d_0005, + &pci_dev_info_3d3d_0006, + &pci_dev_info_3d3d_0007, + &pci_dev_info_3d3d_0008, + &pci_dev_info_3d3d_0009, + &pci_dev_info_3d3d_000a, + &pci_dev_info_3d3d_000c, + &pci_dev_info_3d3d_000d, + &pci_dev_info_3d3d_0011, + &pci_dev_info_3d3d_0012, + &pci_dev_info_3d3d_0013, + &pci_dev_info_3d3d_0020, + &pci_dev_info_3d3d_0022, + &pci_dev_info_3d3d_0024, + &pci_dev_info_3d3d_0100, + &pci_dev_info_3d3d_07a1, + &pci_dev_info_3d3d_07a2, + &pci_dev_info_3d3d_07a3, + &pci_dev_info_3d3d_1004, + &pci_dev_info_3d3d_3d04, + &pci_dev_info_3d3d_ffff, + NULL +}; +static const pciDeviceInfo *pci_dev_list_4005[] = { + &pci_dev_info_4005_0300, + &pci_dev_info_4005_0308, + &pci_dev_info_4005_0309, + &pci_dev_info_4005_1064, + &pci_dev_info_4005_2064, + &pci_dev_info_4005_2128, + &pci_dev_info_4005_2301, + &pci_dev_info_4005_2302, + &pci_dev_info_4005_2303, + &pci_dev_info_4005_2364, + &pci_dev_info_4005_2464, + &pci_dev_info_4005_2501, + &pci_dev_info_4005_4000, + &pci_dev_info_4005_4710, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4033[] = { + &pci_dev_info_4033_1360, + NULL +}; +#endif +#define pci_dev_list_4143 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4144[] = { + &pci_dev_info_4144_0044, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_416c[] = { + &pci_dev_info_416c_0100, + &pci_dev_info_416c_0200, + NULL +}; +#endif +#define pci_dev_list_4321 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4444[] = { + &pci_dev_info_4444_0016, + &pci_dev_info_4444_0803, + NULL +}; +#endif +#define pci_dev_list_4468 NULL +#define pci_dev_list_4594 NULL +#define pci_dev_list_45fb NULL +#define pci_dev_list_4680 NULL +#define pci_dev_list_4843 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4916[] = { + &pci_dev_info_4916_1960, + NULL +}; +#endif +#define pci_dev_list_4943 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_494f[] = { + &pci_dev_info_494f_10e8, + NULL +}; +#endif +#define pci_dev_list_4978 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4a14[] = { + &pci_dev_info_4a14_5000, + NULL +}; +#endif +#define pci_dev_list_4b10 NULL +#define pci_dev_list_4c48 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4c53[] = { + &pci_dev_info_4c53_0000, + &pci_dev_info_4c53_0001, + NULL +}; +#endif +#define pci_dev_list_4ca1 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4d51[] = { + &pci_dev_info_4d51_0200, + NULL +}; +#endif +#define pci_dev_list_4d54 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_4ddc[] = { + &pci_dev_info_4ddc_0100, + &pci_dev_info_4ddc_0801, + &pci_dev_info_4ddc_0802, + &pci_dev_info_4ddc_0811, + &pci_dev_info_4ddc_0812, + &pci_dev_info_4ddc_0881, + &pci_dev_info_4ddc_0882, + &pci_dev_info_4ddc_0891, + &pci_dev_info_4ddc_0892, + &pci_dev_info_4ddc_0901, + &pci_dev_info_4ddc_0902, + &pci_dev_info_4ddc_0903, + &pci_dev_info_4ddc_0904, + &pci_dev_info_4ddc_0b01, + &pci_dev_info_4ddc_0b02, + &pci_dev_info_4ddc_0b03, + &pci_dev_info_4ddc_0b04, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5046[] = { + &pci_dev_info_5046_1001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5053[] = { + &pci_dev_info_5053_2010, + NULL +}; +#endif +#define pci_dev_list_5136 NULL +#define pci_dev_list_5143 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5145[] = { + &pci_dev_info_5145_3031, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5168[] = { + &pci_dev_info_5168_0300, + &pci_dev_info_5168_0301, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5301[] = { + &pci_dev_info_5301_0001, + NULL +}; +#endif +static const pciDeviceInfo *pci_dev_list_5333[] = { + &pci_dev_info_5333_0551, + &pci_dev_info_5333_5631, + &pci_dev_info_5333_8800, + &pci_dev_info_5333_8801, + &pci_dev_info_5333_8810, + &pci_dev_info_5333_8811, + &pci_dev_info_5333_8812, + &pci_dev_info_5333_8813, + &pci_dev_info_5333_8814, + &pci_dev_info_5333_8815, + &pci_dev_info_5333_883d, + &pci_dev_info_5333_8870, + &pci_dev_info_5333_8880, + &pci_dev_info_5333_8881, + &pci_dev_info_5333_8882, + &pci_dev_info_5333_8883, + &pci_dev_info_5333_88b0, + &pci_dev_info_5333_88b1, + &pci_dev_info_5333_88b2, + &pci_dev_info_5333_88b3, + &pci_dev_info_5333_88c0, + &pci_dev_info_5333_88c1, + &pci_dev_info_5333_88c2, + &pci_dev_info_5333_88c3, + &pci_dev_info_5333_88d0, + &pci_dev_info_5333_88d1, + &pci_dev_info_5333_88d2, + &pci_dev_info_5333_88d3, + &pci_dev_info_5333_88f0, + &pci_dev_info_5333_88f1, + &pci_dev_info_5333_88f2, + &pci_dev_info_5333_88f3, + &pci_dev_info_5333_8900, + &pci_dev_info_5333_8901, + &pci_dev_info_5333_8902, + &pci_dev_info_5333_8903, + &pci_dev_info_5333_8904, + &pci_dev_info_5333_8905, + &pci_dev_info_5333_8906, + &pci_dev_info_5333_8907, + &pci_dev_info_5333_8908, + &pci_dev_info_5333_8909, + &pci_dev_info_5333_890a, + &pci_dev_info_5333_890b, + &pci_dev_info_5333_890c, + &pci_dev_info_5333_890d, + &pci_dev_info_5333_890e, + &pci_dev_info_5333_890f, + &pci_dev_info_5333_8a01, + &pci_dev_info_5333_8a10, + &pci_dev_info_5333_8a13, + &pci_dev_info_5333_8a20, + &pci_dev_info_5333_8a21, + &pci_dev_info_5333_8a22, + &pci_dev_info_5333_8a23, + &pci_dev_info_5333_8a25, + &pci_dev_info_5333_8a26, + &pci_dev_info_5333_8c00, + &pci_dev_info_5333_8c01, + &pci_dev_info_5333_8c02, + &pci_dev_info_5333_8c03, + &pci_dev_info_5333_8c10, + &pci_dev_info_5333_8c11, + &pci_dev_info_5333_8c12, + &pci_dev_info_5333_8c13, + &pci_dev_info_5333_8c22, + &pci_dev_info_5333_8c24, + &pci_dev_info_5333_8c26, + &pci_dev_info_5333_8c2a, + &pci_dev_info_5333_8c2b, + &pci_dev_info_5333_8c2c, + &pci_dev_info_5333_8c2d, + &pci_dev_info_5333_8c2e, + &pci_dev_info_5333_8c2f, + &pci_dev_info_5333_8d01, + &pci_dev_info_5333_8d02, + &pci_dev_info_5333_8d03, + &pci_dev_info_5333_8d04, + &pci_dev_info_5333_9102, + &pci_dev_info_5333_ca00, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_544c[] = { + &pci_dev_info_544c_0350, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5455[] = { + &pci_dev_info_5455_4458, + NULL +}; +#endif +#define pci_dev_list_5519 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5544[] = { + &pci_dev_info_5544_0001, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5555[] = { + &pci_dev_info_5555_0003, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_5654[] = { + &pci_dev_info_5654_3132, + NULL +}; +#endif +#define pci_dev_list_5700 NULL +#define pci_dev_list_5851 NULL +#define pci_dev_list_6356 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_6374[] = { + &pci_dev_info_6374_6773, + NULL +}; +#endif +#define pci_dev_list_6409 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_6666[] = { + &pci_dev_info_6666_0001, + &pci_dev_info_6666_0002, + &pci_dev_info_6666_0004, + &pci_dev_info_6666_0101, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_7063[] = { + &pci_dev_info_7063_2000, + &pci_dev_info_7063_3000, + &pci_dev_info_7063_5500, + NULL +}; +#endif +#define pci_dev_list_7604 NULL +#define pci_dev_list_7bde NULL +#define pci_dev_list_7fed NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_8008[] = { + &pci_dev_info_8008_0010, + &pci_dev_info_8008_0011, + NULL +}; +#endif +#define pci_dev_list_807d NULL +static const pciDeviceInfo *pci_dev_list_8086[] = { + &pci_dev_info_8086_0007, + &pci_dev_info_8086_0008, + &pci_dev_info_8086_0039, + &pci_dev_info_8086_0122, + &pci_dev_info_8086_0309, + &pci_dev_info_8086_030d, + &pci_dev_info_8086_0326, + &pci_dev_info_8086_0327, + &pci_dev_info_8086_0329, + &pci_dev_info_8086_032a, + &pci_dev_info_8086_032c, + &pci_dev_info_8086_0330, + &pci_dev_info_8086_0331, + &pci_dev_info_8086_0332, + &pci_dev_info_8086_0333, + &pci_dev_info_8086_0334, + &pci_dev_info_8086_0335, + &pci_dev_info_8086_0336, + &pci_dev_info_8086_0340, + &pci_dev_info_8086_0341, + &pci_dev_info_8086_0370, + &pci_dev_info_8086_0371, + &pci_dev_info_8086_0372, + &pci_dev_info_8086_0373, + &pci_dev_info_8086_0374, + &pci_dev_info_8086_0482, + &pci_dev_info_8086_0483, + &pci_dev_info_8086_0484, + &pci_dev_info_8086_0486, + &pci_dev_info_8086_04a3, + &pci_dev_info_8086_04d0, + &pci_dev_info_8086_0500, + &pci_dev_info_8086_0501, + &pci_dev_info_8086_0502, + &pci_dev_info_8086_0503, + &pci_dev_info_8086_0510, + &pci_dev_info_8086_0511, + &pci_dev_info_8086_0512, + &pci_dev_info_8086_0513, + &pci_dev_info_8086_0514, + &pci_dev_info_8086_0515, + &pci_dev_info_8086_0516, + &pci_dev_info_8086_0530, + &pci_dev_info_8086_0531, + &pci_dev_info_8086_0532, + &pci_dev_info_8086_0533, + &pci_dev_info_8086_0534, + &pci_dev_info_8086_0535, + &pci_dev_info_8086_0536, + &pci_dev_info_8086_0537, + &pci_dev_info_8086_0600, + &pci_dev_info_8086_061f, + &pci_dev_info_8086_0960, + &pci_dev_info_8086_0962, + &pci_dev_info_8086_0964, + &pci_dev_info_8086_1000, + &pci_dev_info_8086_1001, + &pci_dev_info_8086_1002, + &pci_dev_info_8086_1004, + &pci_dev_info_8086_1008, + &pci_dev_info_8086_1009, + &pci_dev_info_8086_100a, + &pci_dev_info_8086_100c, + &pci_dev_info_8086_100d, + &pci_dev_info_8086_100e, + &pci_dev_info_8086_100f, + &pci_dev_info_8086_1010, + &pci_dev_info_8086_1011, + &pci_dev_info_8086_1012, + &pci_dev_info_8086_1013, + &pci_dev_info_8086_1014, + &pci_dev_info_8086_1015, + &pci_dev_info_8086_1016, + &pci_dev_info_8086_1017, + &pci_dev_info_8086_1018, + &pci_dev_info_8086_1019, + &pci_dev_info_8086_101a, + &pci_dev_info_8086_101d, + &pci_dev_info_8086_101e, + &pci_dev_info_8086_1026, + &pci_dev_info_8086_1027, + &pci_dev_info_8086_1028, + &pci_dev_info_8086_1029, + &pci_dev_info_8086_1030, + &pci_dev_info_8086_1031, + &pci_dev_info_8086_1032, + &pci_dev_info_8086_1033, + &pci_dev_info_8086_1034, + &pci_dev_info_8086_1035, + &pci_dev_info_8086_1036, + &pci_dev_info_8086_1037, + &pci_dev_info_8086_1038, + &pci_dev_info_8086_1039, + &pci_dev_info_8086_103a, + &pci_dev_info_8086_103b, + &pci_dev_info_8086_103c, + &pci_dev_info_8086_103d, + &pci_dev_info_8086_103e, + &pci_dev_info_8086_1040, + &pci_dev_info_8086_1043, + &pci_dev_info_8086_1048, + &pci_dev_info_8086_1049, + &pci_dev_info_8086_104a, + &pci_dev_info_8086_104b, + &pci_dev_info_8086_104c, + &pci_dev_info_8086_104d, + &pci_dev_info_8086_1050, + &pci_dev_info_8086_1051, + &pci_dev_info_8086_1052, + &pci_dev_info_8086_1053, + &pci_dev_info_8086_1059, + &pci_dev_info_8086_105b, + &pci_dev_info_8086_105e, + &pci_dev_info_8086_105f, + &pci_dev_info_8086_1060, + &pci_dev_info_8086_1064, + &pci_dev_info_8086_1065, + &pci_dev_info_8086_1066, + &pci_dev_info_8086_1067, + &pci_dev_info_8086_1068, + &pci_dev_info_8086_1069, + &pci_dev_info_8086_106a, + &pci_dev_info_8086_106b, + &pci_dev_info_8086_1075, + &pci_dev_info_8086_1076, + &pci_dev_info_8086_1077, + &pci_dev_info_8086_1078, + &pci_dev_info_8086_1079, + &pci_dev_info_8086_107a, + &pci_dev_info_8086_107b, + &pci_dev_info_8086_107c, + &pci_dev_info_8086_107d, + &pci_dev_info_8086_107e, + &pci_dev_info_8086_107f, + &pci_dev_info_8086_1080, + &pci_dev_info_8086_1081, + &pci_dev_info_8086_1082, + &pci_dev_info_8086_1083, + &pci_dev_info_8086_1084, + &pci_dev_info_8086_1085, + &pci_dev_info_8086_1086, + &pci_dev_info_8086_1087, + &pci_dev_info_8086_1089, + &pci_dev_info_8086_108a, + &pci_dev_info_8086_108b, + &pci_dev_info_8086_108c, + &pci_dev_info_8086_108e, + &pci_dev_info_8086_108f, + &pci_dev_info_8086_1092, + &pci_dev_info_8086_1096, + &pci_dev_info_8086_1097, + &pci_dev_info_8086_1098, + &pci_dev_info_8086_1099, + &pci_dev_info_8086_109a, + &pci_dev_info_8086_109b, + &pci_dev_info_8086_10a0, + &pci_dev_info_8086_10a1, + &pci_dev_info_8086_10b0, + &pci_dev_info_8086_10b2, + &pci_dev_info_8086_10b3, + &pci_dev_info_8086_10b4, + &pci_dev_info_8086_10b5, + &pci_dev_info_8086_10b9, + &pci_dev_info_8086_10ba, + &pci_dev_info_8086_10bb, + &pci_dev_info_8086_1107, + &pci_dev_info_8086_1130, + &pci_dev_info_8086_1131, + &pci_dev_info_8086_1132, + &pci_dev_info_8086_1161, + &pci_dev_info_8086_1162, + &pci_dev_info_8086_1200, + &pci_dev_info_8086_1209, + &pci_dev_info_8086_1221, + &pci_dev_info_8086_1222, + &pci_dev_info_8086_1223, + &pci_dev_info_8086_1225, + &pci_dev_info_8086_1226, + &pci_dev_info_8086_1227, + &pci_dev_info_8086_1228, + &pci_dev_info_8086_1229, + &pci_dev_info_8086_122d, + &pci_dev_info_8086_122e, + &pci_dev_info_8086_1230, + &pci_dev_info_8086_1231, + &pci_dev_info_8086_1234, + &pci_dev_info_8086_1235, + &pci_dev_info_8086_1237, + &pci_dev_info_8086_1239, + &pci_dev_info_8086_123b, + &pci_dev_info_8086_123c, + &pci_dev_info_8086_123d, + &pci_dev_info_8086_123e, + &pci_dev_info_8086_123f, + &pci_dev_info_8086_1240, + &pci_dev_info_8086_124b, + &pci_dev_info_8086_1250, + &pci_dev_info_8086_1360, + &pci_dev_info_8086_1361, + &pci_dev_info_8086_1460, + &pci_dev_info_8086_1461, + &pci_dev_info_8086_1462, + &pci_dev_info_8086_1960, + &pci_dev_info_8086_1962, + &pci_dev_info_8086_1a21, + &pci_dev_info_8086_1a23, + &pci_dev_info_8086_1a24, + &pci_dev_info_8086_1a30, + &pci_dev_info_8086_1a31, + &pci_dev_info_8086_1a38, + &pci_dev_info_8086_1a48, + &pci_dev_info_8086_2410, + &pci_dev_info_8086_2411, + &pci_dev_info_8086_2412, + &pci_dev_info_8086_2413, + &pci_dev_info_8086_2415, + &pci_dev_info_8086_2416, + &pci_dev_info_8086_2418, + &pci_dev_info_8086_2420, + &pci_dev_info_8086_2421, + &pci_dev_info_8086_2422, + &pci_dev_info_8086_2423, + &pci_dev_info_8086_2425, + &pci_dev_info_8086_2426, + &pci_dev_info_8086_2428, + &pci_dev_info_8086_2440, + &pci_dev_info_8086_2442, + &pci_dev_info_8086_2443, + &pci_dev_info_8086_2444, + &pci_dev_info_8086_2445, + &pci_dev_info_8086_2446, + &pci_dev_info_8086_2448, + &pci_dev_info_8086_2449, + &pci_dev_info_8086_244a, + &pci_dev_info_8086_244b, + &pci_dev_info_8086_244c, + &pci_dev_info_8086_244e, + &pci_dev_info_8086_2450, + &pci_dev_info_8086_2452, + &pci_dev_info_8086_2453, + &pci_dev_info_8086_2459, + &pci_dev_info_8086_245b, + &pci_dev_info_8086_245d, + &pci_dev_info_8086_245e, + &pci_dev_info_8086_2480, + &pci_dev_info_8086_2482, + &pci_dev_info_8086_2483, + &pci_dev_info_8086_2484, + &pci_dev_info_8086_2485, + &pci_dev_info_8086_2486, + &pci_dev_info_8086_2487, + &pci_dev_info_8086_248a, + &pci_dev_info_8086_248b, + &pci_dev_info_8086_248c, + &pci_dev_info_8086_24c0, + &pci_dev_info_8086_24c1, + &pci_dev_info_8086_24c2, + &pci_dev_info_8086_24c3, + &pci_dev_info_8086_24c4, + &pci_dev_info_8086_24c5, + &pci_dev_info_8086_24c6, + &pci_dev_info_8086_24c7, + &pci_dev_info_8086_24ca, + &pci_dev_info_8086_24cb, + &pci_dev_info_8086_24cc, + &pci_dev_info_8086_24cd, + &pci_dev_info_8086_24d0, + &pci_dev_info_8086_24d1, + &pci_dev_info_8086_24d2, + &pci_dev_info_8086_24d3, + &pci_dev_info_8086_24d4, + &pci_dev_info_8086_24d5, + &pci_dev_info_8086_24d6, + &pci_dev_info_8086_24d7, + &pci_dev_info_8086_24db, + &pci_dev_info_8086_24dc, + &pci_dev_info_8086_24dd, + &pci_dev_info_8086_24de, + &pci_dev_info_8086_24df, + &pci_dev_info_8086_2500, + &pci_dev_info_8086_2501, + &pci_dev_info_8086_250b, + &pci_dev_info_8086_250f, + &pci_dev_info_8086_2520, + &pci_dev_info_8086_2521, + &pci_dev_info_8086_2530, + &pci_dev_info_8086_2531, + &pci_dev_info_8086_2532, + &pci_dev_info_8086_2533, + &pci_dev_info_8086_2534, + &pci_dev_info_8086_2540, + &pci_dev_info_8086_2541, + &pci_dev_info_8086_2543, + &pci_dev_info_8086_2544, + &pci_dev_info_8086_2545, + &pci_dev_info_8086_2546, + &pci_dev_info_8086_2547, + &pci_dev_info_8086_2548, + &pci_dev_info_8086_254c, + &pci_dev_info_8086_2550, + &pci_dev_info_8086_2551, + &pci_dev_info_8086_2552, + &pci_dev_info_8086_2553, + &pci_dev_info_8086_2554, + &pci_dev_info_8086_255d, + &pci_dev_info_8086_2560, + &pci_dev_info_8086_2561, + &pci_dev_info_8086_2562, + &pci_dev_info_8086_2570, + &pci_dev_info_8086_2571, + &pci_dev_info_8086_2572, + &pci_dev_info_8086_2573, + &pci_dev_info_8086_2576, + &pci_dev_info_8086_2578, + &pci_dev_info_8086_2579, + &pci_dev_info_8086_257b, + &pci_dev_info_8086_257e, + &pci_dev_info_8086_2580, + &pci_dev_info_8086_2581, + &pci_dev_info_8086_2582, + &pci_dev_info_8086_2584, + &pci_dev_info_8086_2585, + &pci_dev_info_8086_2588, + &pci_dev_info_8086_2589, + &pci_dev_info_8086_258a, + &pci_dev_info_8086_2590, + &pci_dev_info_8086_2591, + &pci_dev_info_8086_2592, + &pci_dev_info_8086_25a1, + &pci_dev_info_8086_25a2, + &pci_dev_info_8086_25a3, + &pci_dev_info_8086_25a4, + &pci_dev_info_8086_25a6, + &pci_dev_info_8086_25a7, + &pci_dev_info_8086_25a9, + &pci_dev_info_8086_25aa, + &pci_dev_info_8086_25ab, + &pci_dev_info_8086_25ac, + &pci_dev_info_8086_25ad, + &pci_dev_info_8086_25ae, + &pci_dev_info_8086_25b0, + &pci_dev_info_8086_25c0, + &pci_dev_info_8086_25d0, + &pci_dev_info_8086_25d4, + &pci_dev_info_8086_25d8, + &pci_dev_info_8086_25e2, + &pci_dev_info_8086_25e3, + &pci_dev_info_8086_25e4, + &pci_dev_info_8086_25e5, + &pci_dev_info_8086_25e6, + &pci_dev_info_8086_25e7, + &pci_dev_info_8086_25f0, + &pci_dev_info_8086_25f1, + &pci_dev_info_8086_25f3, + &pci_dev_info_8086_25f5, + &pci_dev_info_8086_25f6, + &pci_dev_info_8086_25f7, + &pci_dev_info_8086_25f8, + &pci_dev_info_8086_25f9, + &pci_dev_info_8086_25fa, + &pci_dev_info_8086_2600, + &pci_dev_info_8086_2601, + &pci_dev_info_8086_2602, + &pci_dev_info_8086_2603, + &pci_dev_info_8086_2604, + &pci_dev_info_8086_2605, + &pci_dev_info_8086_2606, + &pci_dev_info_8086_2607, + &pci_dev_info_8086_2608, + &pci_dev_info_8086_2609, + &pci_dev_info_8086_260a, + &pci_dev_info_8086_260c, + &pci_dev_info_8086_2610, + &pci_dev_info_8086_2611, + &pci_dev_info_8086_2612, + &pci_dev_info_8086_2613, + &pci_dev_info_8086_2614, + &pci_dev_info_8086_2615, + &pci_dev_info_8086_2617, + &pci_dev_info_8086_2618, + &pci_dev_info_8086_2619, + &pci_dev_info_8086_261a, + &pci_dev_info_8086_261b, + &pci_dev_info_8086_261c, + &pci_dev_info_8086_261d, + &pci_dev_info_8086_261e, + &pci_dev_info_8086_2620, + &pci_dev_info_8086_2621, + &pci_dev_info_8086_2622, + &pci_dev_info_8086_2623, + &pci_dev_info_8086_2624, + &pci_dev_info_8086_2625, + &pci_dev_info_8086_2626, + &pci_dev_info_8086_2627, + &pci_dev_info_8086_2640, + &pci_dev_info_8086_2641, + &pci_dev_info_8086_2642, + &pci_dev_info_8086_2651, + &pci_dev_info_8086_2652, + &pci_dev_info_8086_2653, + &pci_dev_info_8086_2658, + &pci_dev_info_8086_2659, + &pci_dev_info_8086_265a, + &pci_dev_info_8086_265b, + &pci_dev_info_8086_265c, + &pci_dev_info_8086_2660, + &pci_dev_info_8086_2662, + &pci_dev_info_8086_2664, + &pci_dev_info_8086_2666, + &pci_dev_info_8086_2668, + &pci_dev_info_8086_266a, + &pci_dev_info_8086_266c, + &pci_dev_info_8086_266d, + &pci_dev_info_8086_266e, + &pci_dev_info_8086_266f, + &pci_dev_info_8086_2670, + &pci_dev_info_8086_2680, + &pci_dev_info_8086_2681, + &pci_dev_info_8086_2682, + &pci_dev_info_8086_2683, + &pci_dev_info_8086_2688, + &pci_dev_info_8086_2689, + &pci_dev_info_8086_268a, + &pci_dev_info_8086_268b, + &pci_dev_info_8086_268c, + &pci_dev_info_8086_2690, + &pci_dev_info_8086_2692, + &pci_dev_info_8086_2694, + &pci_dev_info_8086_2696, + &pci_dev_info_8086_2698, + &pci_dev_info_8086_2699, + &pci_dev_info_8086_269a, + &pci_dev_info_8086_269b, + &pci_dev_info_8086_269e, + &pci_dev_info_8086_2770, + &pci_dev_info_8086_2771, + &pci_dev_info_8086_2772, + &pci_dev_info_8086_2774, + &pci_dev_info_8086_2775, + &pci_dev_info_8086_2776, + &pci_dev_info_8086_2778, + &pci_dev_info_8086_2779, + &pci_dev_info_8086_277a, + &pci_dev_info_8086_277c, + &pci_dev_info_8086_277d, + &pci_dev_info_8086_2782, + &pci_dev_info_8086_2792, + &pci_dev_info_8086_27a0, + &pci_dev_info_8086_27a1, + &pci_dev_info_8086_27a2, + &pci_dev_info_8086_27a6, + &pci_dev_info_8086_27b0, + &pci_dev_info_8086_27b8, + &pci_dev_info_8086_27b9, + &pci_dev_info_8086_27bd, + &pci_dev_info_8086_27c0, + &pci_dev_info_8086_27c1, + &pci_dev_info_8086_27c3, + &pci_dev_info_8086_27c4, + &pci_dev_info_8086_27c5, + &pci_dev_info_8086_27c6, + &pci_dev_info_8086_27c8, + &pci_dev_info_8086_27c9, + &pci_dev_info_8086_27ca, + &pci_dev_info_8086_27cb, + &pci_dev_info_8086_27cc, + &pci_dev_info_8086_27d0, + &pci_dev_info_8086_27d2, + &pci_dev_info_8086_27d4, + &pci_dev_info_8086_27d6, + &pci_dev_info_8086_27d8, + &pci_dev_info_8086_27da, + &pci_dev_info_8086_27dc, + &pci_dev_info_8086_27dd, + &pci_dev_info_8086_27de, + &pci_dev_info_8086_27df, + &pci_dev_info_8086_27e0, + &pci_dev_info_8086_27e2, + &pci_dev_info_8086_2810, + &pci_dev_info_8086_2811, + &pci_dev_info_8086_2812, + &pci_dev_info_8086_2814, + &pci_dev_info_8086_2815, + &pci_dev_info_8086_2820, + &pci_dev_info_8086_2821, + &pci_dev_info_8086_2822, + &pci_dev_info_8086_2824, + &pci_dev_info_8086_2825, + &pci_dev_info_8086_2828, + &pci_dev_info_8086_2829, + &pci_dev_info_8086_282a, + &pci_dev_info_8086_2830, + &pci_dev_info_8086_2831, + &pci_dev_info_8086_2832, + &pci_dev_info_8086_2834, + &pci_dev_info_8086_2835, + &pci_dev_info_8086_2836, + &pci_dev_info_8086_283a, + &pci_dev_info_8086_283e, + &pci_dev_info_8086_283f, + &pci_dev_info_8086_2841, + &pci_dev_info_8086_2843, + &pci_dev_info_8086_2845, + &pci_dev_info_8086_2847, + &pci_dev_info_8086_2849, + &pci_dev_info_8086_284b, + &pci_dev_info_8086_284f, + &pci_dev_info_8086_2850, + &pci_dev_info_8086_2970, + &pci_dev_info_8086_2971, + &pci_dev_info_8086_2972, + &pci_dev_info_8086_2973, + &pci_dev_info_8086_2974, + &pci_dev_info_8086_2975, + &pci_dev_info_8086_2976, + &pci_dev_info_8086_2977, + &pci_dev_info_8086_2980, + &pci_dev_info_8086_2981, + &pci_dev_info_8086_2982, + &pci_dev_info_8086_2990, + &pci_dev_info_8086_2991, + &pci_dev_info_8086_2992, + &pci_dev_info_8086_2993, + &pci_dev_info_8086_2994, + &pci_dev_info_8086_2995, + &pci_dev_info_8086_2996, + &pci_dev_info_8086_2997, + &pci_dev_info_8086_29a0, + &pci_dev_info_8086_29a1, + &pci_dev_info_8086_29a2, + &pci_dev_info_8086_29a3, + &pci_dev_info_8086_29a4, + &pci_dev_info_8086_29a5, + &pci_dev_info_8086_29a6, + &pci_dev_info_8086_29a7, + &pci_dev_info_8086_2a00, + &pci_dev_info_8086_2a01, + &pci_dev_info_8086_2a02, + &pci_dev_info_8086_2a03, + &pci_dev_info_8086_2a04, + &pci_dev_info_8086_2a05, + &pci_dev_info_8086_2a06, + &pci_dev_info_8086_2a07, + &pci_dev_info_8086_3092, + &pci_dev_info_8086_3200, + &pci_dev_info_8086_3340, + &pci_dev_info_8086_3341, + &pci_dev_info_8086_3500, + &pci_dev_info_8086_3501, + &pci_dev_info_8086_3504, + &pci_dev_info_8086_3505, + &pci_dev_info_8086_350c, + &pci_dev_info_8086_350d, + &pci_dev_info_8086_3510, + &pci_dev_info_8086_3511, + &pci_dev_info_8086_3514, + &pci_dev_info_8086_3515, + &pci_dev_info_8086_3518, + &pci_dev_info_8086_3519, + &pci_dev_info_8086_3575, + &pci_dev_info_8086_3576, + &pci_dev_info_8086_3577, + &pci_dev_info_8086_3578, + &pci_dev_info_8086_3580, + &pci_dev_info_8086_3581, + &pci_dev_info_8086_3582, + &pci_dev_info_8086_3584, + &pci_dev_info_8086_3585, + &pci_dev_info_8086_3590, + &pci_dev_info_8086_3591, + &pci_dev_info_8086_3592, + &pci_dev_info_8086_3593, + &pci_dev_info_8086_3594, + &pci_dev_info_8086_3595, + &pci_dev_info_8086_3596, + &pci_dev_info_8086_3597, + &pci_dev_info_8086_3598, + &pci_dev_info_8086_3599, + &pci_dev_info_8086_359a, + &pci_dev_info_8086_359b, + &pci_dev_info_8086_359e, + &pci_dev_info_8086_35b0, + &pci_dev_info_8086_35b1, + &pci_dev_info_8086_35b5, + &pci_dev_info_8086_35b6, + &pci_dev_info_8086_35b7, + &pci_dev_info_8086_35c8, + &pci_dev_info_8086_4220, + &pci_dev_info_8086_4222, + &pci_dev_info_8086_4223, + &pci_dev_info_8086_4224, + &pci_dev_info_8086_4227, + &pci_dev_info_8086_5001, + &pci_dev_info_8086_5200, + &pci_dev_info_8086_5201, + &pci_dev_info_8086_530d, + &pci_dev_info_8086_7000, + &pci_dev_info_8086_7010, + &pci_dev_info_8086_7020, + &pci_dev_info_8086_7030, + &pci_dev_info_8086_7050, + &pci_dev_info_8086_7051, + &pci_dev_info_8086_7100, + &pci_dev_info_8086_7110, + &pci_dev_info_8086_7111, + &pci_dev_info_8086_7112, + &pci_dev_info_8086_7113, + &pci_dev_info_8086_7120, + &pci_dev_info_8086_7121, + &pci_dev_info_8086_7122, + &pci_dev_info_8086_7123, + &pci_dev_info_8086_7124, + &pci_dev_info_8086_7125, + &pci_dev_info_8086_7126, + &pci_dev_info_8086_7128, + &pci_dev_info_8086_712a, + &pci_dev_info_8086_7180, + &pci_dev_info_8086_7181, + &pci_dev_info_8086_7190, + &pci_dev_info_8086_7191, + &pci_dev_info_8086_7192, + &pci_dev_info_8086_7194, + &pci_dev_info_8086_7195, + &pci_dev_info_8086_7196, + &pci_dev_info_8086_7198, + &pci_dev_info_8086_7199, + &pci_dev_info_8086_719a, + &pci_dev_info_8086_719b, + &pci_dev_info_8086_71a0, + &pci_dev_info_8086_71a1, + &pci_dev_info_8086_71a2, + &pci_dev_info_8086_7600, + &pci_dev_info_8086_7601, + &pci_dev_info_8086_7602, + &pci_dev_info_8086_7603, + &pci_dev_info_8086_7800, + &pci_dev_info_8086_84c4, + &pci_dev_info_8086_84c5, + &pci_dev_info_8086_84ca, + &pci_dev_info_8086_84cb, + &pci_dev_info_8086_84e0, + &pci_dev_info_8086_84e1, + &pci_dev_info_8086_84e2, + &pci_dev_info_8086_84e3, + &pci_dev_info_8086_84e4, + &pci_dev_info_8086_84e6, + &pci_dev_info_8086_84ea, + &pci_dev_info_8086_8500, + &pci_dev_info_8086_9000, + &pci_dev_info_8086_9001, + &pci_dev_info_8086_9002, + &pci_dev_info_8086_9004, + &pci_dev_info_8086_9621, + &pci_dev_info_8086_9622, + &pci_dev_info_8086_9641, + &pci_dev_info_8086_96a1, + &pci_dev_info_8086_b152, + &pci_dev_info_8086_b154, + &pci_dev_info_8086_b555, + NULL +}; +#define pci_dev_list_8401 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_8686[] = { + &pci_dev_info_8686_1010, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_8800[] = { + &pci_dev_info_8800_2008, + NULL +}; +#endif +#define pci_dev_list_8866 NULL +#define pci_dev_list_8888 NULL +#define pci_dev_list_8912 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_8c4a[] = { + &pci_dev_info_8c4a_1980, + NULL +}; +#endif +#define pci_dev_list_8e0e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_8e2e[] = { + &pci_dev_info_8e2e_3000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_9004[] = { + &pci_dev_info_9004_0078, + &pci_dev_info_9004_1078, + &pci_dev_info_9004_1160, + &pci_dev_info_9004_2178, + &pci_dev_info_9004_3860, + &pci_dev_info_9004_3b78, + &pci_dev_info_9004_5075, + &pci_dev_info_9004_5078, + &pci_dev_info_9004_5175, + &pci_dev_info_9004_5178, + &pci_dev_info_9004_5275, + &pci_dev_info_9004_5278, + &pci_dev_info_9004_5375, + &pci_dev_info_9004_5378, + &pci_dev_info_9004_5475, + &pci_dev_info_9004_5478, + &pci_dev_info_9004_5575, + &pci_dev_info_9004_5578, + &pci_dev_info_9004_5647, + &pci_dev_info_9004_5675, + &pci_dev_info_9004_5678, + &pci_dev_info_9004_5775, + &pci_dev_info_9004_5778, + &pci_dev_info_9004_5800, + &pci_dev_info_9004_5900, + &pci_dev_info_9004_5905, + &pci_dev_info_9004_6038, + &pci_dev_info_9004_6075, + &pci_dev_info_9004_6078, + &pci_dev_info_9004_6178, + &pci_dev_info_9004_6278, + &pci_dev_info_9004_6378, + &pci_dev_info_9004_6478, + &pci_dev_info_9004_6578, + &pci_dev_info_9004_6678, + &pci_dev_info_9004_6778, + &pci_dev_info_9004_6915, + &pci_dev_info_9004_7078, + &pci_dev_info_9004_7178, + &pci_dev_info_9004_7278, + &pci_dev_info_9004_7378, + &pci_dev_info_9004_7478, + &pci_dev_info_9004_7578, + &pci_dev_info_9004_7678, + &pci_dev_info_9004_7710, + &pci_dev_info_9004_7711, + &pci_dev_info_9004_7778, + &pci_dev_info_9004_7810, + &pci_dev_info_9004_7815, + &pci_dev_info_9004_7850, + &pci_dev_info_9004_7855, + &pci_dev_info_9004_7860, + &pci_dev_info_9004_7870, + &pci_dev_info_9004_7871, + &pci_dev_info_9004_7872, + &pci_dev_info_9004_7873, + &pci_dev_info_9004_7874, + &pci_dev_info_9004_7880, + &pci_dev_info_9004_7890, + &pci_dev_info_9004_7891, + &pci_dev_info_9004_7892, + &pci_dev_info_9004_7893, + &pci_dev_info_9004_7894, + &pci_dev_info_9004_7895, + &pci_dev_info_9004_7896, + &pci_dev_info_9004_7897, + &pci_dev_info_9004_8078, + &pci_dev_info_9004_8178, + &pci_dev_info_9004_8278, + &pci_dev_info_9004_8378, + &pci_dev_info_9004_8478, + &pci_dev_info_9004_8578, + &pci_dev_info_9004_8678, + &pci_dev_info_9004_8778, + &pci_dev_info_9004_8878, + &pci_dev_info_9004_8b78, + &pci_dev_info_9004_ec78, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_9005[] = { + &pci_dev_info_9005_0010, + &pci_dev_info_9005_0011, + &pci_dev_info_9005_0013, + &pci_dev_info_9005_001f, + &pci_dev_info_9005_0020, + &pci_dev_info_9005_002f, + &pci_dev_info_9005_0030, + &pci_dev_info_9005_003f, + &pci_dev_info_9005_0050, + &pci_dev_info_9005_0051, + &pci_dev_info_9005_0053, + &pci_dev_info_9005_005f, + &pci_dev_info_9005_0080, + &pci_dev_info_9005_0081, + &pci_dev_info_9005_0083, + &pci_dev_info_9005_008f, + &pci_dev_info_9005_00c0, + &pci_dev_info_9005_00c1, + &pci_dev_info_9005_00c3, + &pci_dev_info_9005_00c5, + &pci_dev_info_9005_00cf, + &pci_dev_info_9005_0241, + &pci_dev_info_9005_0250, + &pci_dev_info_9005_0279, + &pci_dev_info_9005_0283, + &pci_dev_info_9005_0284, + &pci_dev_info_9005_0285, + &pci_dev_info_9005_0286, + &pci_dev_info_9005_0410, + &pci_dev_info_9005_0412, + &pci_dev_info_9005_041e, + &pci_dev_info_9005_041f, + &pci_dev_info_9005_0430, + &pci_dev_info_9005_0432, + &pci_dev_info_9005_043e, + &pci_dev_info_9005_043f, + &pci_dev_info_9005_0500, + &pci_dev_info_9005_0503, + &pci_dev_info_9005_0910, + &pci_dev_info_9005_091e, + &pci_dev_info_9005_8000, + &pci_dev_info_9005_800f, + &pci_dev_info_9005_8010, + &pci_dev_info_9005_8011, + &pci_dev_info_9005_8012, + &pci_dev_info_9005_8013, + &pci_dev_info_9005_8014, + &pci_dev_info_9005_8015, + &pci_dev_info_9005_8016, + &pci_dev_info_9005_8017, + &pci_dev_info_9005_801c, + &pci_dev_info_9005_801d, + &pci_dev_info_9005_801e, + &pci_dev_info_9005_801f, + &pci_dev_info_9005_8080, + &pci_dev_info_9005_808f, + &pci_dev_info_9005_8090, + &pci_dev_info_9005_8091, + &pci_dev_info_9005_8092, + &pci_dev_info_9005_8093, + &pci_dev_info_9005_8094, + &pci_dev_info_9005_8095, + &pci_dev_info_9005_8096, + &pci_dev_info_9005_8097, + &pci_dev_info_9005_809c, + &pci_dev_info_9005_809d, + &pci_dev_info_9005_809e, + &pci_dev_info_9005_809f, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_907f[] = { + &pci_dev_info_907f_2015, + NULL +}; +#endif +#define pci_dev_list_919a NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_9412[] = { + &pci_dev_info_9412_6565, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_9699[] = { + &pci_dev_info_9699_6565, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_9710[] = { + &pci_dev_info_9710_7780, + &pci_dev_info_9710_9805, + &pci_dev_info_9710_9815, + &pci_dev_info_9710_9835, + &pci_dev_info_9710_9845, + &pci_dev_info_9710_9855, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_9902[] = { + &pci_dev_info_9902_0001, + &pci_dev_info_9902_0002, + &pci_dev_info_9902_0003, + NULL +}; +#endif +#define pci_dev_list_a0a0 NULL +#define pci_dev_list_a0f1 NULL +#define pci_dev_list_a200 NULL +#define pci_dev_list_a259 NULL +#define pci_dev_list_a25b NULL +#define pci_dev_list_a304 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_a727[] = { + &pci_dev_info_a727_0013, + NULL +}; +#endif +#define pci_dev_list_aa42 NULL +#define pci_dev_list_ac1e NULL +#define pci_dev_list_ac3d NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_aecb[] = { + &pci_dev_info_aecb_6250, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_affe[] = { + &pci_dev_info_affe_02e1, + &pci_dev_info_affe_dead, + NULL +}; +#endif +#define pci_dev_list_b10b NULL +#define pci_dev_list_b1b3 NULL +#define pci_dev_list_bd11 NULL +#define pci_dev_list_c001 NULL +#define pci_dev_list_c0a9 NULL +#define pci_dev_list_c0de NULL +#define pci_dev_list_c0fe NULL +#define pci_dev_list_ca50 NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_cafe[] = { + &pci_dev_info_cafe_0003, + NULL +}; +#endif +#define pci_dev_list_cccc NULL +#define pci_dev_list_ccec NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_cddd[] = { + &pci_dev_info_cddd_0101, + &pci_dev_info_cddd_0200, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_d161[] = { + &pci_dev_info_d161_0205, + &pci_dev_info_d161_0210, + &pci_dev_info_d161_0405, + &pci_dev_info_d161_0406, + &pci_dev_info_d161_0410, + &pci_dev_info_d161_0411, + &pci_dev_info_d161_2400, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_d4d4[] = { + &pci_dev_info_d4d4_0601, + NULL +}; +#endif +#define pci_dev_list_d531 NULL +#define pci_dev_list_d84d NULL +#define pci_dev_list_dead NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_deaf[] = { + &pci_dev_info_deaf_9050, + &pci_dev_info_deaf_9051, + &pci_dev_info_deaf_9052, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_e000[] = { + &pci_dev_info_e000_e000, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_e159[] = { + &pci_dev_info_e159_0001, + &pci_dev_info_e159_0002, + NULL +}; +#endif +#define pci_dev_list_e4bf NULL +#define pci_dev_list_e55e NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_ea01[] = { + &pci_dev_info_ea01_000a, + &pci_dev_info_ea01_0032, + &pci_dev_info_ea01_003e, + &pci_dev_info_ea01_0041, + &pci_dev_info_ea01_0043, + &pci_dev_info_ea01_0046, + &pci_dev_info_ea01_0052, + &pci_dev_info_ea01_0800, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_ea60[] = { + &pci_dev_info_ea60_9896, + &pci_dev_info_ea60_9897, + &pci_dev_info_ea60_9898, + NULL +}; +#endif +#define pci_dev_list_eabb NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_eace[] = { + &pci_dev_info_eace_3100, + &pci_dev_info_eace_3200, + &pci_dev_info_eace_320e, + &pci_dev_info_eace_340e, + &pci_dev_info_eace_341e, + &pci_dev_info_eace_3500, + &pci_dev_info_eace_351c, + &pci_dev_info_eace_4100, + &pci_dev_info_eace_4110, + &pci_dev_info_eace_4220, + &pci_dev_info_eace_422e, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_ec80[] = { + &pci_dev_info_ec80_ec00, + NULL +}; +#endif +#define pci_dev_list_ecc0 NULL +static const pciDeviceInfo *pci_dev_list_edd8[] = { + &pci_dev_info_edd8_a091, + &pci_dev_info_edd8_a099, + &pci_dev_info_edd8_a0a1, + &pci_dev_info_edd8_a0a9, + NULL +}; +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_f1d0[] = { + &pci_dev_info_f1d0_c0fe, + &pci_dev_info_f1d0_c0ff, + &pci_dev_info_f1d0_cafe, + &pci_dev_info_f1d0_cfee, + &pci_dev_info_f1d0_dcaf, + &pci_dev_info_f1d0_dfee, + &pci_dev_info_f1d0_efac, + &pci_dev_info_f1d0_facd, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_fa57[] = { + &pci_dev_info_fa57_0001, + NULL +}; +#endif +#define pci_dev_list_fab7 NULL +#define pci_dev_list_febd NULL +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_feda[] = { + &pci_dev_info_feda_a0fa, + &pci_dev_info_feda_a10e, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_fede[] = { + &pci_dev_info_fede_0003, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_fffd[] = { + &pci_dev_info_fffd_0101, + NULL +}; +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO +static const pciDeviceInfo *pci_dev_list_fffe[] = { + &pci_dev_info_fffe_0405, + &pci_dev_info_fffe_0710, + NULL +}; +#endif +#define pci_dev_list_ffff NULL + +static const pciVendorInfo pciVendorInfoList[] = { +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0000, pci_vendor_0000, pci_dev_list_0000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x001a, pci_vendor_001a, pci_dev_list_001a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0033, pci_vendor_0033, pci_dev_list_0033}, +#endif + {0x003d, pci_vendor_003d, pci_dev_list_003d}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0059, pci_vendor_0059, pci_dev_list_0059}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0070, pci_vendor_0070, pci_dev_list_0070}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0071, pci_vendor_0071, pci_dev_list_0071}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0095, pci_vendor_0095, pci_dev_list_0095}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x00a7, pci_vendor_00a7, pci_dev_list_00a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x00f5, pci_vendor_00f5, pci_dev_list_00f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0100, pci_vendor_0100, pci_dev_list_0100}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0123, pci_vendor_0123, pci_dev_list_0123}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x018a, pci_vendor_018a, pci_dev_list_018a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x021b, pci_vendor_021b, pci_dev_list_021b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0270, pci_vendor_0270, pci_dev_list_0270}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0291, pci_vendor_0291, pci_dev_list_0291}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x02ac, pci_vendor_02ac, pci_dev_list_02ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0315, pci_vendor_0315, pci_dev_list_0315}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0357, pci_vendor_0357, pci_dev_list_0357}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0432, pci_vendor_0432, pci_dev_list_0432}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x045e, pci_vendor_045e, pci_dev_list_045e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0482, pci_vendor_0482, pci_dev_list_0482}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x04cf, pci_vendor_04cf, pci_dev_list_04cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x050d, pci_vendor_050d, pci_dev_list_050d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x05a9, pci_vendor_05a9, pci_dev_list_05a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x05e3, pci_vendor_05e3, pci_dev_list_05e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x066f, pci_vendor_066f, pci_dev_list_066f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0675, pci_vendor_0675, pci_dev_list_0675}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x067b, pci_vendor_067b, pci_dev_list_067b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0721, pci_vendor_0721, pci_dev_list_0721}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x07e2, pci_vendor_07e2, pci_dev_list_07e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0925, pci_vendor_0925, pci_dev_list_0925}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x093a, pci_vendor_093a, pci_dev_list_093a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x09c1, pci_vendor_09c1, pci_dev_list_09c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0a89, pci_vendor_0a89, pci_dev_list_0a89}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0b0b, pci_vendor_0b0b, pci_dev_list_0b0b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0b49, pci_vendor_0b49, pci_dev_list_0b49}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0ccd, pci_vendor_0ccd, pci_dev_list_0ccd}, +#endif + {0x0e11, pci_vendor_0e11, pci_dev_list_0e11}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0e21, pci_vendor_0e21, pci_dev_list_0e21}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0e55, pci_vendor_0e55, pci_dev_list_0e55}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0eac, pci_vendor_0eac, pci_dev_list_0eac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1000, pci_vendor_1000, pci_dev_list_1000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1001, pci_vendor_1001, pci_dev_list_1001}, +#endif + {0x1002, pci_vendor_1002, pci_dev_list_1002}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1003, pci_vendor_1003, pci_dev_list_1003}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1004, pci_vendor_1004, pci_dev_list_1004}, +#endif + {0x1005, pci_vendor_1005, pci_dev_list_1005}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1006, pci_vendor_1006, pci_dev_list_1006}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1007, pci_vendor_1007, pci_dev_list_1007}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1008, pci_vendor_1008, pci_dev_list_1008}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x100a, pci_vendor_100a, pci_dev_list_100a}, +#endif + {0x100b, pci_vendor_100b, pci_dev_list_100b}, + {0x100c, pci_vendor_100c, pci_dev_list_100c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x100d, pci_vendor_100d, pci_dev_list_100d}, +#endif + {0x100e, pci_vendor_100e, pci_dev_list_100e}, + {0x1010, pci_vendor_1010, pci_dev_list_1010}, + {0x1011, pci_vendor_1011, pci_dev_list_1011}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1012, pci_vendor_1012, pci_dev_list_1012}, +#endif + {0x1013, pci_vendor_1013, pci_dev_list_1013}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1014, pci_vendor_1014, pci_dev_list_1014}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1015, pci_vendor_1015, pci_dev_list_1015}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1016, pci_vendor_1016, pci_dev_list_1016}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1017, pci_vendor_1017, pci_dev_list_1017}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1018, pci_vendor_1018, pci_dev_list_1018}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1019, pci_vendor_1019, pci_dev_list_1019}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101a, pci_vendor_101a, pci_dev_list_101a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101b, pci_vendor_101b, pci_dev_list_101b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101c, pci_vendor_101c, pci_dev_list_101c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101e, pci_vendor_101e, pci_dev_list_101e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101f, pci_vendor_101f, pci_dev_list_101f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1020, pci_vendor_1020, pci_dev_list_1020}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1021, pci_vendor_1021, pci_dev_list_1021}, +#endif + {0x1022, pci_vendor_1022, pci_dev_list_1022}, + {0x1023, pci_vendor_1023, pci_dev_list_1023}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1024, pci_vendor_1024, pci_dev_list_1024}, +#endif + {0x1025, pci_vendor_1025, pci_dev_list_1025}, + {0x1028, pci_vendor_1028, pci_dev_list_1028}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1029, pci_vendor_1029, pci_dev_list_1029}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102a, pci_vendor_102a, pci_dev_list_102a}, +#endif + {0x102b, pci_vendor_102b, pci_dev_list_102b}, + {0x102c, pci_vendor_102c, pci_dev_list_102c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102d, pci_vendor_102d, pci_dev_list_102d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102e, pci_vendor_102e, pci_dev_list_102e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102f, pci_vendor_102f, pci_dev_list_102f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1030, pci_vendor_1030, pci_dev_list_1030}, +#endif + {0x1031, pci_vendor_1031, pci_dev_list_1031}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1032, pci_vendor_1032, pci_dev_list_1032}, +#endif + {0x1033, pci_vendor_1033, pci_dev_list_1033}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1034, pci_vendor_1034, pci_dev_list_1034}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1035, pci_vendor_1035, pci_dev_list_1035}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1036, pci_vendor_1036, pci_dev_list_1036}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1037, pci_vendor_1037, pci_dev_list_1037}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1038, pci_vendor_1038, pci_dev_list_1038}, +#endif + {0x1039, pci_vendor_1039, pci_dev_list_1039}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103a, pci_vendor_103a, pci_dev_list_103a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103b, pci_vendor_103b, pci_dev_list_103b}, +#endif + {0x103c, pci_vendor_103c, pci_dev_list_103c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103e, pci_vendor_103e, pci_dev_list_103e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103f, pci_vendor_103f, pci_dev_list_103f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1040, pci_vendor_1040, pci_dev_list_1040}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1041, pci_vendor_1041, pci_dev_list_1041}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1042, pci_vendor_1042, pci_dev_list_1042}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1043, pci_vendor_1043, pci_dev_list_1043}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1044, pci_vendor_1044, pci_dev_list_1044}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1045, pci_vendor_1045, pci_dev_list_1045}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1046, pci_vendor_1046, pci_dev_list_1046}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1047, pci_vendor_1047, pci_dev_list_1047}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1048, pci_vendor_1048, pci_dev_list_1048}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1049, pci_vendor_1049, pci_dev_list_1049}, +#endif + {0x104a, pci_vendor_104a, pci_dev_list_104a}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x104b, pci_vendor_104b, pci_dev_list_104b}, +#endif + {0x104c, pci_vendor_104c, pci_dev_list_104c}, + {0x104d, pci_vendor_104d, pci_dev_list_104d}, + {0x104e, pci_vendor_104e, pci_dev_list_104e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x104f, pci_vendor_104f, pci_dev_list_104f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1050, pci_vendor_1050, pci_dev_list_1050}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1051, pci_vendor_1051, pci_dev_list_1051}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1052, pci_vendor_1052, pci_dev_list_1052}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1053, pci_vendor_1053, pci_dev_list_1053}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1054, pci_vendor_1054, pci_dev_list_1054}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1055, pci_vendor_1055, pci_dev_list_1055}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1056, pci_vendor_1056, pci_dev_list_1056}, +#endif + {0x1057, pci_vendor_1057, pci_dev_list_1057}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1058, pci_vendor_1058, pci_dev_list_1058}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1059, pci_vendor_1059, pci_dev_list_1059}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105a, pci_vendor_105a, pci_dev_list_105a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105b, pci_vendor_105b, pci_dev_list_105b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105c, pci_vendor_105c, pci_dev_list_105c}, +#endif + {0x105d, pci_vendor_105d, pci_dev_list_105d}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105e, pci_vendor_105e, pci_dev_list_105e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105f, pci_vendor_105f, pci_dev_list_105f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1060, pci_vendor_1060, pci_dev_list_1060}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1061, pci_vendor_1061, pci_dev_list_1061}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1062, pci_vendor_1062, pci_dev_list_1062}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1063, pci_vendor_1063, pci_dev_list_1063}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1064, pci_vendor_1064, pci_dev_list_1064}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1065, pci_vendor_1065, pci_dev_list_1065}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1066, pci_vendor_1066, pci_dev_list_1066}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1067, pci_vendor_1067, pci_dev_list_1067}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1068, pci_vendor_1068, pci_dev_list_1068}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1069, pci_vendor_1069, pci_dev_list_1069}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106a, pci_vendor_106a, pci_dev_list_106a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106b, pci_vendor_106b, pci_dev_list_106b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106c, pci_vendor_106c, pci_dev_list_106c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106d, pci_vendor_106d, pci_dev_list_106d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106e, pci_vendor_106e, pci_dev_list_106e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106f, pci_vendor_106f, pci_dev_list_106f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1070, pci_vendor_1070, pci_dev_list_1070}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1071, pci_vendor_1071, pci_dev_list_1071}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1072, pci_vendor_1072, pci_dev_list_1072}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1073, pci_vendor_1073, pci_dev_list_1073}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1074, pci_vendor_1074, pci_dev_list_1074}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1075, pci_vendor_1075, pci_dev_list_1075}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1076, pci_vendor_1076, pci_dev_list_1076}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1077, pci_vendor_1077, pci_dev_list_1077}, +#endif + {0x1078, pci_vendor_1078, pci_dev_list_1078}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1079, pci_vendor_1079, pci_dev_list_1079}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107a, pci_vendor_107a, pci_dev_list_107a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107b, pci_vendor_107b, pci_dev_list_107b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107c, pci_vendor_107c, pci_dev_list_107c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107d, pci_vendor_107d, pci_dev_list_107d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107e, pci_vendor_107e, pci_dev_list_107e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107f, pci_vendor_107f, pci_dev_list_107f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1080, pci_vendor_1080, pci_dev_list_1080}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1081, pci_vendor_1081, pci_dev_list_1081}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1082, pci_vendor_1082, pci_dev_list_1082}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1083, pci_vendor_1083, pci_dev_list_1083}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1084, pci_vendor_1084, pci_dev_list_1084}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1085, pci_vendor_1085, pci_dev_list_1085}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1086, pci_vendor_1086, pci_dev_list_1086}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1087, pci_vendor_1087, pci_dev_list_1087}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1088, pci_vendor_1088, pci_dev_list_1088}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1089, pci_vendor_1089, pci_dev_list_1089}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108a, pci_vendor_108a, pci_dev_list_108a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108c, pci_vendor_108c, pci_dev_list_108c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108d, pci_vendor_108d, pci_dev_list_108d}, +#endif + {0x108e, pci_vendor_108e, pci_dev_list_108e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108f, pci_vendor_108f, pci_dev_list_108f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1090, pci_vendor_1090, pci_dev_list_1090}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1091, pci_vendor_1091, pci_dev_list_1091}, +#endif + {0x1092, pci_vendor_1092, pci_dev_list_1092}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1093, pci_vendor_1093, pci_dev_list_1093}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1094, pci_vendor_1094, pci_dev_list_1094}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1095, pci_vendor_1095, pci_dev_list_1095}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1096, pci_vendor_1096, pci_dev_list_1096}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1097, pci_vendor_1097, pci_dev_list_1097}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1098, pci_vendor_1098, pci_dev_list_1098}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1099, pci_vendor_1099, pci_dev_list_1099}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109a, pci_vendor_109a, pci_dev_list_109a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109b, pci_vendor_109b, pci_dev_list_109b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109c, pci_vendor_109c, pci_dev_list_109c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109d, pci_vendor_109d, pci_dev_list_109d}, +#endif + {0x109e, pci_vendor_109e, pci_dev_list_109e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109f, pci_vendor_109f, pci_dev_list_109f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a0, pci_vendor_10a0, pci_dev_list_10a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a1, pci_vendor_10a1, pci_dev_list_10a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a2, pci_vendor_10a2, pci_dev_list_10a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a3, pci_vendor_10a3, pci_dev_list_10a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a4, pci_vendor_10a4, pci_dev_list_10a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a5, pci_vendor_10a5, pci_dev_list_10a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a6, pci_vendor_10a6, pci_dev_list_10a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a7, pci_vendor_10a7, pci_dev_list_10a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a8, pci_vendor_10a8, pci_dev_list_10a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a9, pci_vendor_10a9, pci_dev_list_10a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10aa, pci_vendor_10aa, pci_dev_list_10aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ab, pci_vendor_10ab, pci_dev_list_10ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ac, pci_vendor_10ac, pci_dev_list_10ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ad, pci_vendor_10ad, pci_dev_list_10ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ae, pci_vendor_10ae, pci_dev_list_10ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10af, pci_vendor_10af, pci_dev_list_10af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b0, pci_vendor_10b0, pci_dev_list_10b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b1, pci_vendor_10b1, pci_dev_list_10b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b2, pci_vendor_10b2, pci_dev_list_10b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b3, pci_vendor_10b3, pci_dev_list_10b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b4, pci_vendor_10b4, pci_dev_list_10b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b5, pci_vendor_10b5, pci_dev_list_10b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b6, pci_vendor_10b6, pci_dev_list_10b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b7, pci_vendor_10b7, pci_dev_list_10b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b8, pci_vendor_10b8, pci_dev_list_10b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b9, pci_vendor_10b9, pci_dev_list_10b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ba, pci_vendor_10ba, pci_dev_list_10ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bb, pci_vendor_10bb, pci_dev_list_10bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bc, pci_vendor_10bc, pci_dev_list_10bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bd, pci_vendor_10bd, pci_dev_list_10bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10be, pci_vendor_10be, pci_dev_list_10be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bf, pci_vendor_10bf, pci_dev_list_10bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c0, pci_vendor_10c0, pci_dev_list_10c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c1, pci_vendor_10c1, pci_dev_list_10c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c2, pci_vendor_10c2, pci_dev_list_10c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c3, pci_vendor_10c3, pci_dev_list_10c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c4, pci_vendor_10c4, pci_dev_list_10c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c5, pci_vendor_10c5, pci_dev_list_10c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c6, pci_vendor_10c6, pci_dev_list_10c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c7, pci_vendor_10c7, pci_dev_list_10c7}, +#endif + {0x10c8, pci_vendor_10c8, pci_dev_list_10c8}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c9, pci_vendor_10c9, pci_dev_list_10c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ca, pci_vendor_10ca, pci_dev_list_10ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cb, pci_vendor_10cb, pci_dev_list_10cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cc, pci_vendor_10cc, pci_dev_list_10cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cd, pci_vendor_10cd, pci_dev_list_10cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ce, pci_vendor_10ce, pci_dev_list_10ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cf, pci_vendor_10cf, pci_dev_list_10cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d1, pci_vendor_10d1, pci_dev_list_10d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d2, pci_vendor_10d2, pci_dev_list_10d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d3, pci_vendor_10d3, pci_dev_list_10d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d4, pci_vendor_10d4, pci_dev_list_10d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d5, pci_vendor_10d5, pci_dev_list_10d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d6, pci_vendor_10d6, pci_dev_list_10d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d7, pci_vendor_10d7, pci_dev_list_10d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d8, pci_vendor_10d8, pci_dev_list_10d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d9, pci_vendor_10d9, pci_dev_list_10d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10da, pci_vendor_10da, pci_dev_list_10da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10db, pci_vendor_10db, pci_dev_list_10db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10dc, pci_vendor_10dc, pci_dev_list_10dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10dd, pci_vendor_10dd, pci_dev_list_10dd}, +#endif + {0x10de, pci_vendor_10de, pci_dev_list_10de}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10df, pci_vendor_10df, pci_dev_list_10df}, +#endif + {0x10e0, pci_vendor_10e0, pci_dev_list_10e0}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e1, pci_vendor_10e1, pci_dev_list_10e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e2, pci_vendor_10e2, pci_dev_list_10e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e3, pci_vendor_10e3, pci_dev_list_10e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e4, pci_vendor_10e4, pci_dev_list_10e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e5, pci_vendor_10e5, pci_dev_list_10e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e6, pci_vendor_10e6, pci_dev_list_10e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e7, pci_vendor_10e7, pci_dev_list_10e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e8, pci_vendor_10e8, pci_dev_list_10e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e9, pci_vendor_10e9, pci_dev_list_10e9}, +#endif + {0x10ea, pci_vendor_10ea, pci_dev_list_10ea}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10eb, pci_vendor_10eb, pci_dev_list_10eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ec, pci_vendor_10ec, pci_dev_list_10ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ed, pci_vendor_10ed, pci_dev_list_10ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ee, pci_vendor_10ee, pci_dev_list_10ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ef, pci_vendor_10ef, pci_dev_list_10ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f0, pci_vendor_10f0, pci_dev_list_10f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f1, pci_vendor_10f1, pci_dev_list_10f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f2, pci_vendor_10f2, pci_dev_list_10f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f3, pci_vendor_10f3, pci_dev_list_10f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f4, pci_vendor_10f4, pci_dev_list_10f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f5, pci_vendor_10f5, pci_dev_list_10f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f6, pci_vendor_10f6, pci_dev_list_10f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f7, pci_vendor_10f7, pci_dev_list_10f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f8, pci_vendor_10f8, pci_dev_list_10f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f9, pci_vendor_10f9, pci_dev_list_10f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fa, pci_vendor_10fa, pci_dev_list_10fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fb, pci_vendor_10fb, pci_dev_list_10fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fc, pci_vendor_10fc, pci_dev_list_10fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fd, pci_vendor_10fd, pci_dev_list_10fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fe, pci_vendor_10fe, pci_dev_list_10fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ff, pci_vendor_10ff, pci_dev_list_10ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1100, pci_vendor_1100, pci_dev_list_1100}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1101, pci_vendor_1101, pci_dev_list_1101}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1102, pci_vendor_1102, pci_dev_list_1102}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1103, pci_vendor_1103, pci_dev_list_1103}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1104, pci_vendor_1104, pci_dev_list_1104}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1105, pci_vendor_1105, pci_dev_list_1105}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1106, pci_vendor_1106, pci_dev_list_1106}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1107, pci_vendor_1107, pci_dev_list_1107}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1108, pci_vendor_1108, pci_dev_list_1108}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1109, pci_vendor_1109, pci_dev_list_1109}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110a, pci_vendor_110a, pci_dev_list_110a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110b, pci_vendor_110b, pci_dev_list_110b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110c, pci_vendor_110c, pci_dev_list_110c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110d, pci_vendor_110d, pci_dev_list_110d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110e, pci_vendor_110e, pci_dev_list_110e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110f, pci_vendor_110f, pci_dev_list_110f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1110, pci_vendor_1110, pci_dev_list_1110}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1111, pci_vendor_1111, pci_dev_list_1111}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1112, pci_vendor_1112, pci_dev_list_1112}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1113, pci_vendor_1113, pci_dev_list_1113}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1114, pci_vendor_1114, pci_dev_list_1114}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1115, pci_vendor_1115, pci_dev_list_1115}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1116, pci_vendor_1116, pci_dev_list_1116}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1117, pci_vendor_1117, pci_dev_list_1117}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1118, pci_vendor_1118, pci_dev_list_1118}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1119, pci_vendor_1119, pci_dev_list_1119}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111a, pci_vendor_111a, pci_dev_list_111a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111b, pci_vendor_111b, pci_dev_list_111b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111c, pci_vendor_111c, pci_dev_list_111c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111d, pci_vendor_111d, pci_dev_list_111d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111e, pci_vendor_111e, pci_dev_list_111e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111f, pci_vendor_111f, pci_dev_list_111f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1120, pci_vendor_1120, pci_dev_list_1120}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1121, pci_vendor_1121, pci_dev_list_1121}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1122, pci_vendor_1122, pci_dev_list_1122}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1123, pci_vendor_1123, pci_dev_list_1123}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1124, pci_vendor_1124, pci_dev_list_1124}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1125, pci_vendor_1125, pci_dev_list_1125}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1126, pci_vendor_1126, pci_dev_list_1126}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1127, pci_vendor_1127, pci_dev_list_1127}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1129, pci_vendor_1129, pci_dev_list_1129}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112a, pci_vendor_112a, pci_dev_list_112a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112b, pci_vendor_112b, pci_dev_list_112b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112c, pci_vendor_112c, pci_dev_list_112c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112d, pci_vendor_112d, pci_dev_list_112d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112e, pci_vendor_112e, pci_dev_list_112e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112f, pci_vendor_112f, pci_dev_list_112f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1130, pci_vendor_1130, pci_dev_list_1130}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1131, pci_vendor_1131, pci_dev_list_1131}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1132, pci_vendor_1132, pci_dev_list_1132}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1133, pci_vendor_1133, pci_dev_list_1133}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1134, pci_vendor_1134, pci_dev_list_1134}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1135, pci_vendor_1135, pci_dev_list_1135}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1136, pci_vendor_1136, pci_dev_list_1136}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1137, pci_vendor_1137, pci_dev_list_1137}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1138, pci_vendor_1138, pci_dev_list_1138}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1139, pci_vendor_1139, pci_dev_list_1139}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113a, pci_vendor_113a, pci_dev_list_113a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113b, pci_vendor_113b, pci_dev_list_113b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113c, pci_vendor_113c, pci_dev_list_113c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113d, pci_vendor_113d, pci_dev_list_113d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113e, pci_vendor_113e, pci_dev_list_113e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113f, pci_vendor_113f, pci_dev_list_113f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1140, pci_vendor_1140, pci_dev_list_1140}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1141, pci_vendor_1141, pci_dev_list_1141}, +#endif + {0x1142, pci_vendor_1142, pci_dev_list_1142}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1143, pci_vendor_1143, pci_dev_list_1143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1144, pci_vendor_1144, pci_dev_list_1144}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1145, pci_vendor_1145, pci_dev_list_1145}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1146, pci_vendor_1146, pci_dev_list_1146}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1147, pci_vendor_1147, pci_dev_list_1147}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1148, pci_vendor_1148, pci_dev_list_1148}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1149, pci_vendor_1149, pci_dev_list_1149}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114a, pci_vendor_114a, pci_dev_list_114a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114b, pci_vendor_114b, pci_dev_list_114b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114c, pci_vendor_114c, pci_dev_list_114c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114d, pci_vendor_114d, pci_dev_list_114d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114e, pci_vendor_114e, pci_dev_list_114e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114f, pci_vendor_114f, pci_dev_list_114f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1150, pci_vendor_1150, pci_dev_list_1150}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1151, pci_vendor_1151, pci_dev_list_1151}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1152, pci_vendor_1152, pci_dev_list_1152}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1153, pci_vendor_1153, pci_dev_list_1153}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1154, pci_vendor_1154, pci_dev_list_1154}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1155, pci_vendor_1155, pci_dev_list_1155}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1156, pci_vendor_1156, pci_dev_list_1156}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1157, pci_vendor_1157, pci_dev_list_1157}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1158, pci_vendor_1158, pci_dev_list_1158}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1159, pci_vendor_1159, pci_dev_list_1159}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115a, pci_vendor_115a, pci_dev_list_115a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115b, pci_vendor_115b, pci_dev_list_115b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115c, pci_vendor_115c, pci_dev_list_115c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115d, pci_vendor_115d, pci_dev_list_115d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115e, pci_vendor_115e, pci_dev_list_115e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115f, pci_vendor_115f, pci_dev_list_115f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1160, pci_vendor_1160, pci_dev_list_1160}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1161, pci_vendor_1161, pci_dev_list_1161}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1162, pci_vendor_1162, pci_dev_list_1162}, +#endif + {0x1163, pci_vendor_1163, pci_dev_list_1163}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1164, pci_vendor_1164, pci_dev_list_1164}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1165, pci_vendor_1165, pci_dev_list_1165}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1166, pci_vendor_1166, pci_dev_list_1166}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1167, pci_vendor_1167, pci_dev_list_1167}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1168, pci_vendor_1168, pci_dev_list_1168}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1169, pci_vendor_1169, pci_dev_list_1169}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116a, pci_vendor_116a, pci_dev_list_116a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116b, pci_vendor_116b, pci_dev_list_116b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116c, pci_vendor_116c, pci_dev_list_116c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116d, pci_vendor_116d, pci_dev_list_116d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116e, pci_vendor_116e, pci_dev_list_116e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116f, pci_vendor_116f, pci_dev_list_116f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1170, pci_vendor_1170, pci_dev_list_1170}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1171, pci_vendor_1171, pci_dev_list_1171}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1172, pci_vendor_1172, pci_dev_list_1172}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1173, pci_vendor_1173, pci_dev_list_1173}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1174, pci_vendor_1174, pci_dev_list_1174}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1175, pci_vendor_1175, pci_dev_list_1175}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1176, pci_vendor_1176, pci_dev_list_1176}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1177, pci_vendor_1177, pci_dev_list_1177}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1178, pci_vendor_1178, pci_dev_list_1178}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1179, pci_vendor_1179, pci_dev_list_1179}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117a, pci_vendor_117a, pci_dev_list_117a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117b, pci_vendor_117b, pci_dev_list_117b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117c, pci_vendor_117c, pci_dev_list_117c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117d, pci_vendor_117d, pci_dev_list_117d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117e, pci_vendor_117e, pci_dev_list_117e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117f, pci_vendor_117f, pci_dev_list_117f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1180, pci_vendor_1180, pci_dev_list_1180}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1181, pci_vendor_1181, pci_dev_list_1181}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1183, pci_vendor_1183, pci_dev_list_1183}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1184, pci_vendor_1184, pci_dev_list_1184}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1185, pci_vendor_1185, pci_dev_list_1185}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1186, pci_vendor_1186, pci_dev_list_1186}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1187, pci_vendor_1187, pci_dev_list_1187}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1188, pci_vendor_1188, pci_dev_list_1188}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1189, pci_vendor_1189, pci_dev_list_1189}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118a, pci_vendor_118a, pci_dev_list_118a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118b, pci_vendor_118b, pci_dev_list_118b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118c, pci_vendor_118c, pci_dev_list_118c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118d, pci_vendor_118d, pci_dev_list_118d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118e, pci_vendor_118e, pci_dev_list_118e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118f, pci_vendor_118f, pci_dev_list_118f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1190, pci_vendor_1190, pci_dev_list_1190}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1191, pci_vendor_1191, pci_dev_list_1191}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1192, pci_vendor_1192, pci_dev_list_1192}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1193, pci_vendor_1193, pci_dev_list_1193}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1194, pci_vendor_1194, pci_dev_list_1194}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1195, pci_vendor_1195, pci_dev_list_1195}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1196, pci_vendor_1196, pci_dev_list_1196}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1197, pci_vendor_1197, pci_dev_list_1197}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1198, pci_vendor_1198, pci_dev_list_1198}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1199, pci_vendor_1199, pci_dev_list_1199}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119a, pci_vendor_119a, pci_dev_list_119a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119b, pci_vendor_119b, pci_dev_list_119b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119c, pci_vendor_119c, pci_dev_list_119c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119d, pci_vendor_119d, pci_dev_list_119d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119e, pci_vendor_119e, pci_dev_list_119e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119f, pci_vendor_119f, pci_dev_list_119f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a0, pci_vendor_11a0, pci_dev_list_11a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a1, pci_vendor_11a1, pci_dev_list_11a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a2, pci_vendor_11a2, pci_dev_list_11a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a3, pci_vendor_11a3, pci_dev_list_11a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a4, pci_vendor_11a4, pci_dev_list_11a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a5, pci_vendor_11a5, pci_dev_list_11a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a6, pci_vendor_11a6, pci_dev_list_11a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a7, pci_vendor_11a7, pci_dev_list_11a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a8, pci_vendor_11a8, pci_dev_list_11a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a9, pci_vendor_11a9, pci_dev_list_11a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11aa, pci_vendor_11aa, pci_dev_list_11aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ab, pci_vendor_11ab, pci_dev_list_11ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ac, pci_vendor_11ac, pci_dev_list_11ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ad, pci_vendor_11ad, pci_dev_list_11ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ae, pci_vendor_11ae, pci_dev_list_11ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11af, pci_vendor_11af, pci_dev_list_11af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b0, pci_vendor_11b0, pci_dev_list_11b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b1, pci_vendor_11b1, pci_dev_list_11b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b2, pci_vendor_11b2, pci_dev_list_11b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b3, pci_vendor_11b3, pci_dev_list_11b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b4, pci_vendor_11b4, pci_dev_list_11b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b5, pci_vendor_11b5, pci_dev_list_11b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b6, pci_vendor_11b6, pci_dev_list_11b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b7, pci_vendor_11b7, pci_dev_list_11b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b8, pci_vendor_11b8, pci_dev_list_11b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b9, pci_vendor_11b9, pci_dev_list_11b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ba, pci_vendor_11ba, pci_dev_list_11ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bb, pci_vendor_11bb, pci_dev_list_11bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bc, pci_vendor_11bc, pci_dev_list_11bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bd, pci_vendor_11bd, pci_dev_list_11bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11be, pci_vendor_11be, pci_dev_list_11be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bf, pci_vendor_11bf, pci_dev_list_11bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c0, pci_vendor_11c0, pci_dev_list_11c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c1, pci_vendor_11c1, pci_dev_list_11c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c2, pci_vendor_11c2, pci_dev_list_11c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c3, pci_vendor_11c3, pci_dev_list_11c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c4, pci_vendor_11c4, pci_dev_list_11c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c5, pci_vendor_11c5, pci_dev_list_11c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c6, pci_vendor_11c6, pci_dev_list_11c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c7, pci_vendor_11c7, pci_dev_list_11c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c8, pci_vendor_11c8, pci_dev_list_11c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c9, pci_vendor_11c9, pci_dev_list_11c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ca, pci_vendor_11ca, pci_dev_list_11ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cb, pci_vendor_11cb, pci_dev_list_11cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cc, pci_vendor_11cc, pci_dev_list_11cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cd, pci_vendor_11cd, pci_dev_list_11cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ce, pci_vendor_11ce, pci_dev_list_11ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cf, pci_vendor_11cf, pci_dev_list_11cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d0, pci_vendor_11d0, pci_dev_list_11d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d1, pci_vendor_11d1, pci_dev_list_11d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d2, pci_vendor_11d2, pci_dev_list_11d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d3, pci_vendor_11d3, pci_dev_list_11d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d4, pci_vendor_11d4, pci_dev_list_11d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d5, pci_vendor_11d5, pci_dev_list_11d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d6, pci_vendor_11d6, pci_dev_list_11d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d7, pci_vendor_11d7, pci_dev_list_11d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d8, pci_vendor_11d8, pci_dev_list_11d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d9, pci_vendor_11d9, pci_dev_list_11d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11da, pci_vendor_11da, pci_dev_list_11da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11db, pci_vendor_11db, pci_dev_list_11db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11dc, pci_vendor_11dc, pci_dev_list_11dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11dd, pci_vendor_11dd, pci_dev_list_11dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11de, pci_vendor_11de, pci_dev_list_11de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11df, pci_vendor_11df, pci_dev_list_11df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e0, pci_vendor_11e0, pci_dev_list_11e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e1, pci_vendor_11e1, pci_dev_list_11e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e2, pci_vendor_11e2, pci_dev_list_11e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e3, pci_vendor_11e3, pci_dev_list_11e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e4, pci_vendor_11e4, pci_dev_list_11e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e5, pci_vendor_11e5, pci_dev_list_11e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e6, pci_vendor_11e6, pci_dev_list_11e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e7, pci_vendor_11e7, pci_dev_list_11e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e8, pci_vendor_11e8, pci_dev_list_11e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e9, pci_vendor_11e9, pci_dev_list_11e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ea, pci_vendor_11ea, pci_dev_list_11ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11eb, pci_vendor_11eb, pci_dev_list_11eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ec, pci_vendor_11ec, pci_dev_list_11ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ed, pci_vendor_11ed, pci_dev_list_11ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ee, pci_vendor_11ee, pci_dev_list_11ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ef, pci_vendor_11ef, pci_dev_list_11ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f0, pci_vendor_11f0, pci_dev_list_11f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f1, pci_vendor_11f1, pci_dev_list_11f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f2, pci_vendor_11f2, pci_dev_list_11f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f3, pci_vendor_11f3, pci_dev_list_11f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f4, pci_vendor_11f4, pci_dev_list_11f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f5, pci_vendor_11f5, pci_dev_list_11f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f6, pci_vendor_11f6, pci_dev_list_11f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f7, pci_vendor_11f7, pci_dev_list_11f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f8, pci_vendor_11f8, pci_dev_list_11f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f9, pci_vendor_11f9, pci_dev_list_11f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fa, pci_vendor_11fa, pci_dev_list_11fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fb, pci_vendor_11fb, pci_dev_list_11fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fc, pci_vendor_11fc, pci_dev_list_11fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fd, pci_vendor_11fd, pci_dev_list_11fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fe, pci_vendor_11fe, pci_dev_list_11fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ff, pci_vendor_11ff, pci_dev_list_11ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1200, pci_vendor_1200, pci_dev_list_1200}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1201, pci_vendor_1201, pci_dev_list_1201}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1202, pci_vendor_1202, pci_dev_list_1202}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1203, pci_vendor_1203, pci_dev_list_1203}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1204, pci_vendor_1204, pci_dev_list_1204}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1205, pci_vendor_1205, pci_dev_list_1205}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1206, pci_vendor_1206, pci_dev_list_1206}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1208, pci_vendor_1208, pci_dev_list_1208}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1209, pci_vendor_1209, pci_dev_list_1209}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120a, pci_vendor_120a, pci_dev_list_120a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120b, pci_vendor_120b, pci_dev_list_120b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120c, pci_vendor_120c, pci_dev_list_120c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120d, pci_vendor_120d, pci_dev_list_120d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120e, pci_vendor_120e, pci_dev_list_120e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120f, pci_vendor_120f, pci_dev_list_120f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1210, pci_vendor_1210, pci_dev_list_1210}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1211, pci_vendor_1211, pci_dev_list_1211}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1212, pci_vendor_1212, pci_dev_list_1212}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1213, pci_vendor_1213, pci_dev_list_1213}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1214, pci_vendor_1214, pci_dev_list_1214}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1215, pci_vendor_1215, pci_dev_list_1215}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1216, pci_vendor_1216, pci_dev_list_1216}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1217, pci_vendor_1217, pci_dev_list_1217}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1218, pci_vendor_1218, pci_dev_list_1218}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1219, pci_vendor_1219, pci_dev_list_1219}, +#endif + {0x121a, pci_vendor_121a, pci_dev_list_121a}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121b, pci_vendor_121b, pci_dev_list_121b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121c, pci_vendor_121c, pci_dev_list_121c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121d, pci_vendor_121d, pci_dev_list_121d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121e, pci_vendor_121e, pci_dev_list_121e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121f, pci_vendor_121f, pci_dev_list_121f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1220, pci_vendor_1220, pci_dev_list_1220}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1221, pci_vendor_1221, pci_dev_list_1221}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1222, pci_vendor_1222, pci_dev_list_1222}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1223, pci_vendor_1223, pci_dev_list_1223}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1224, pci_vendor_1224, pci_dev_list_1224}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1225, pci_vendor_1225, pci_dev_list_1225}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1227, pci_vendor_1227, pci_dev_list_1227}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1228, pci_vendor_1228, pci_dev_list_1228}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1229, pci_vendor_1229, pci_dev_list_1229}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122a, pci_vendor_122a, pci_dev_list_122a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122b, pci_vendor_122b, pci_dev_list_122b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122c, pci_vendor_122c, pci_dev_list_122c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122d, pci_vendor_122d, pci_dev_list_122d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122e, pci_vendor_122e, pci_dev_list_122e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122f, pci_vendor_122f, pci_dev_list_122f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1230, pci_vendor_1230, pci_dev_list_1230}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1231, pci_vendor_1231, pci_dev_list_1231}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1232, pci_vendor_1232, pci_dev_list_1232}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1233, pci_vendor_1233, pci_dev_list_1233}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1234, pci_vendor_1234, pci_dev_list_1234}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1235, pci_vendor_1235, pci_dev_list_1235}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1236, pci_vendor_1236, pci_dev_list_1236}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1237, pci_vendor_1237, pci_dev_list_1237}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1238, pci_vendor_1238, pci_dev_list_1238}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1239, pci_vendor_1239, pci_dev_list_1239}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123a, pci_vendor_123a, pci_dev_list_123a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123b, pci_vendor_123b, pci_dev_list_123b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123c, pci_vendor_123c, pci_dev_list_123c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123d, pci_vendor_123d, pci_dev_list_123d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123e, pci_vendor_123e, pci_dev_list_123e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123f, pci_vendor_123f, pci_dev_list_123f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1240, pci_vendor_1240, pci_dev_list_1240}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1241, pci_vendor_1241, pci_dev_list_1241}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1242, pci_vendor_1242, pci_dev_list_1242}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1243, pci_vendor_1243, pci_dev_list_1243}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1244, pci_vendor_1244, pci_dev_list_1244}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1245, pci_vendor_1245, pci_dev_list_1245}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1246, pci_vendor_1246, pci_dev_list_1246}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1247, pci_vendor_1247, pci_dev_list_1247}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1248, pci_vendor_1248, pci_dev_list_1248}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1249, pci_vendor_1249, pci_dev_list_1249}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124a, pci_vendor_124a, pci_dev_list_124a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124b, pci_vendor_124b, pci_dev_list_124b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124c, pci_vendor_124c, pci_dev_list_124c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124d, pci_vendor_124d, pci_dev_list_124d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124e, pci_vendor_124e, pci_dev_list_124e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124f, pci_vendor_124f, pci_dev_list_124f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1250, pci_vendor_1250, pci_dev_list_1250}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1251, pci_vendor_1251, pci_dev_list_1251}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1253, pci_vendor_1253, pci_dev_list_1253}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1254, pci_vendor_1254, pci_dev_list_1254}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1255, pci_vendor_1255, pci_dev_list_1255}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1256, pci_vendor_1256, pci_dev_list_1256}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1257, pci_vendor_1257, pci_dev_list_1257}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1258, pci_vendor_1258, pci_dev_list_1258}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1259, pci_vendor_1259, pci_dev_list_1259}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125a, pci_vendor_125a, pci_dev_list_125a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125b, pci_vendor_125b, pci_dev_list_125b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125c, pci_vendor_125c, pci_dev_list_125c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125d, pci_vendor_125d, pci_dev_list_125d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125e, pci_vendor_125e, pci_dev_list_125e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125f, pci_vendor_125f, pci_dev_list_125f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1260, pci_vendor_1260, pci_dev_list_1260}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1261, pci_vendor_1261, pci_dev_list_1261}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1262, pci_vendor_1262, pci_dev_list_1262}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1263, pci_vendor_1263, pci_dev_list_1263}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1264, pci_vendor_1264, pci_dev_list_1264}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1265, pci_vendor_1265, pci_dev_list_1265}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1266, pci_vendor_1266, pci_dev_list_1266}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1267, pci_vendor_1267, pci_dev_list_1267}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1268, pci_vendor_1268, pci_dev_list_1268}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1269, pci_vendor_1269, pci_dev_list_1269}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126a, pci_vendor_126a, pci_dev_list_126a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126b, pci_vendor_126b, pci_dev_list_126b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126c, pci_vendor_126c, pci_dev_list_126c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126d, pci_vendor_126d, pci_dev_list_126d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126e, pci_vendor_126e, pci_dev_list_126e}, +#endif + {0x126f, pci_vendor_126f, pci_dev_list_126f}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1270, pci_vendor_1270, pci_dev_list_1270}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1271, pci_vendor_1271, pci_dev_list_1271}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1272, pci_vendor_1272, pci_dev_list_1272}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1273, pci_vendor_1273, pci_dev_list_1273}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1274, pci_vendor_1274, pci_dev_list_1274}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1275, pci_vendor_1275, pci_dev_list_1275}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1276, pci_vendor_1276, pci_dev_list_1276}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1277, pci_vendor_1277, pci_dev_list_1277}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1278, pci_vendor_1278, pci_dev_list_1278}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1279, pci_vendor_1279, pci_dev_list_1279}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127a, pci_vendor_127a, pci_dev_list_127a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127b, pci_vendor_127b, pci_dev_list_127b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127c, pci_vendor_127c, pci_dev_list_127c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127d, pci_vendor_127d, pci_dev_list_127d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127e, pci_vendor_127e, pci_dev_list_127e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127f, pci_vendor_127f, pci_dev_list_127f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1280, pci_vendor_1280, pci_dev_list_1280}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1281, pci_vendor_1281, pci_dev_list_1281}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1282, pci_vendor_1282, pci_dev_list_1282}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1283, pci_vendor_1283, pci_dev_list_1283}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1284, pci_vendor_1284, pci_dev_list_1284}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1285, pci_vendor_1285, pci_dev_list_1285}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1286, pci_vendor_1286, pci_dev_list_1286}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1287, pci_vendor_1287, pci_dev_list_1287}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1288, pci_vendor_1288, pci_dev_list_1288}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1289, pci_vendor_1289, pci_dev_list_1289}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128a, pci_vendor_128a, pci_dev_list_128a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128b, pci_vendor_128b, pci_dev_list_128b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128c, pci_vendor_128c, pci_dev_list_128c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128d, pci_vendor_128d, pci_dev_list_128d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128e, pci_vendor_128e, pci_dev_list_128e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128f, pci_vendor_128f, pci_dev_list_128f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1290, pci_vendor_1290, pci_dev_list_1290}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1291, pci_vendor_1291, pci_dev_list_1291}, +#endif + {0x1292, pci_vendor_1292, pci_dev_list_1292}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1293, pci_vendor_1293, pci_dev_list_1293}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1294, pci_vendor_1294, pci_dev_list_1294}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1295, pci_vendor_1295, pci_dev_list_1295}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1296, pci_vendor_1296, pci_dev_list_1296}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1297, pci_vendor_1297, pci_dev_list_1297}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1298, pci_vendor_1298, pci_dev_list_1298}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1299, pci_vendor_1299, pci_dev_list_1299}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129a, pci_vendor_129a, pci_dev_list_129a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129b, pci_vendor_129b, pci_dev_list_129b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129c, pci_vendor_129c, pci_dev_list_129c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129d, pci_vendor_129d, pci_dev_list_129d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129e, pci_vendor_129e, pci_dev_list_129e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129f, pci_vendor_129f, pci_dev_list_129f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a0, pci_vendor_12a0, pci_dev_list_12a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a1, pci_vendor_12a1, pci_dev_list_12a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a2, pci_vendor_12a2, pci_dev_list_12a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a3, pci_vendor_12a3, pci_dev_list_12a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a4, pci_vendor_12a4, pci_dev_list_12a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a5, pci_vendor_12a5, pci_dev_list_12a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a6, pci_vendor_12a6, pci_dev_list_12a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a7, pci_vendor_12a7, pci_dev_list_12a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a8, pci_vendor_12a8, pci_dev_list_12a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a9, pci_vendor_12a9, pci_dev_list_12a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12aa, pci_vendor_12aa, pci_dev_list_12aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ab, pci_vendor_12ab, pci_dev_list_12ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ac, pci_vendor_12ac, pci_dev_list_12ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ad, pci_vendor_12ad, pci_dev_list_12ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ae, pci_vendor_12ae, pci_dev_list_12ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12af, pci_vendor_12af, pci_dev_list_12af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b0, pci_vendor_12b0, pci_dev_list_12b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b1, pci_vendor_12b1, pci_dev_list_12b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b2, pci_vendor_12b2, pci_dev_list_12b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b3, pci_vendor_12b3, pci_dev_list_12b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b4, pci_vendor_12b4, pci_dev_list_12b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b5, pci_vendor_12b5, pci_dev_list_12b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b6, pci_vendor_12b6, pci_dev_list_12b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b7, pci_vendor_12b7, pci_dev_list_12b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b8, pci_vendor_12b8, pci_dev_list_12b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b9, pci_vendor_12b9, pci_dev_list_12b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ba, pci_vendor_12ba, pci_dev_list_12ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bb, pci_vendor_12bb, pci_dev_list_12bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bc, pci_vendor_12bc, pci_dev_list_12bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bd, pci_vendor_12bd, pci_dev_list_12bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12be, pci_vendor_12be, pci_dev_list_12be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bf, pci_vendor_12bf, pci_dev_list_12bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c0, pci_vendor_12c0, pci_dev_list_12c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c1, pci_vendor_12c1, pci_dev_list_12c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c2, pci_vendor_12c2, pci_dev_list_12c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c3, pci_vendor_12c3, pci_dev_list_12c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c4, pci_vendor_12c4, pci_dev_list_12c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c5, pci_vendor_12c5, pci_dev_list_12c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c6, pci_vendor_12c6, pci_dev_list_12c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c7, pci_vendor_12c7, pci_dev_list_12c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c8, pci_vendor_12c8, pci_dev_list_12c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c9, pci_vendor_12c9, pci_dev_list_12c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ca, pci_vendor_12ca, pci_dev_list_12ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cb, pci_vendor_12cb, pci_dev_list_12cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cc, pci_vendor_12cc, pci_dev_list_12cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cd, pci_vendor_12cd, pci_dev_list_12cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ce, pci_vendor_12ce, pci_dev_list_12ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cf, pci_vendor_12cf, pci_dev_list_12cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d0, pci_vendor_12d0, pci_dev_list_12d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d1, pci_vendor_12d1, pci_dev_list_12d1}, +#endif + {0x12d2, pci_vendor_12d2, pci_dev_list_12d2}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d3, pci_vendor_12d3, pci_dev_list_12d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d4, pci_vendor_12d4, pci_dev_list_12d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d5, pci_vendor_12d5, pci_dev_list_12d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d6, pci_vendor_12d6, pci_dev_list_12d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d7, pci_vendor_12d7, pci_dev_list_12d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d8, pci_vendor_12d8, pci_dev_list_12d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d9, pci_vendor_12d9, pci_dev_list_12d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12da, pci_vendor_12da, pci_dev_list_12da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12db, pci_vendor_12db, pci_dev_list_12db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12dc, pci_vendor_12dc, pci_dev_list_12dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12dd, pci_vendor_12dd, pci_dev_list_12dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12de, pci_vendor_12de, pci_dev_list_12de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12df, pci_vendor_12df, pci_dev_list_12df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e0, pci_vendor_12e0, pci_dev_list_12e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e1, pci_vendor_12e1, pci_dev_list_12e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e2, pci_vendor_12e2, pci_dev_list_12e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e3, pci_vendor_12e3, pci_dev_list_12e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e4, pci_vendor_12e4, pci_dev_list_12e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e5, pci_vendor_12e5, pci_dev_list_12e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e6, pci_vendor_12e6, pci_dev_list_12e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e7, pci_vendor_12e7, pci_dev_list_12e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e8, pci_vendor_12e8, pci_dev_list_12e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e9, pci_vendor_12e9, pci_dev_list_12e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ea, pci_vendor_12ea, pci_dev_list_12ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12eb, pci_vendor_12eb, pci_dev_list_12eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ec, pci_vendor_12ec, pci_dev_list_12ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ed, pci_vendor_12ed, pci_dev_list_12ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ee, pci_vendor_12ee, pci_dev_list_12ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ef, pci_vendor_12ef, pci_dev_list_12ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f0, pci_vendor_12f0, pci_dev_list_12f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f1, pci_vendor_12f1, pci_dev_list_12f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f2, pci_vendor_12f2, pci_dev_list_12f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f3, pci_vendor_12f3, pci_dev_list_12f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f4, pci_vendor_12f4, pci_dev_list_12f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f5, pci_vendor_12f5, pci_dev_list_12f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f6, pci_vendor_12f6, pci_dev_list_12f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f7, pci_vendor_12f7, pci_dev_list_12f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f8, pci_vendor_12f8, pci_dev_list_12f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f9, pci_vendor_12f9, pci_dev_list_12f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fb, pci_vendor_12fb, pci_dev_list_12fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fc, pci_vendor_12fc, pci_dev_list_12fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fd, pci_vendor_12fd, pci_dev_list_12fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fe, pci_vendor_12fe, pci_dev_list_12fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ff, pci_vendor_12ff, pci_dev_list_12ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1300, pci_vendor_1300, pci_dev_list_1300}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1302, pci_vendor_1302, pci_dev_list_1302}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1303, pci_vendor_1303, pci_dev_list_1303}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1304, pci_vendor_1304, pci_dev_list_1304}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1305, pci_vendor_1305, pci_dev_list_1305}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1306, pci_vendor_1306, pci_dev_list_1306}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1307, pci_vendor_1307, pci_dev_list_1307}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1308, pci_vendor_1308, pci_dev_list_1308}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1309, pci_vendor_1309, pci_dev_list_1309}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130a, pci_vendor_130a, pci_dev_list_130a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130b, pci_vendor_130b, pci_dev_list_130b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130c, pci_vendor_130c, pci_dev_list_130c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130d, pci_vendor_130d, pci_dev_list_130d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130e, pci_vendor_130e, pci_dev_list_130e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130f, pci_vendor_130f, pci_dev_list_130f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1310, pci_vendor_1310, pci_dev_list_1310}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1311, pci_vendor_1311, pci_dev_list_1311}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1312, pci_vendor_1312, pci_dev_list_1312}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1313, pci_vendor_1313, pci_dev_list_1313}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1316, pci_vendor_1316, pci_dev_list_1316}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1317, pci_vendor_1317, pci_dev_list_1317}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1318, pci_vendor_1318, pci_dev_list_1318}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1319, pci_vendor_1319, pci_dev_list_1319}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131a, pci_vendor_131a, pci_dev_list_131a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131c, pci_vendor_131c, pci_dev_list_131c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131d, pci_vendor_131d, pci_dev_list_131d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131e, pci_vendor_131e, pci_dev_list_131e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131f, pci_vendor_131f, pci_dev_list_131f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1320, pci_vendor_1320, pci_dev_list_1320}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1321, pci_vendor_1321, pci_dev_list_1321}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1322, pci_vendor_1322, pci_dev_list_1322}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1323, pci_vendor_1323, pci_dev_list_1323}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1324, pci_vendor_1324, pci_dev_list_1324}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1325, pci_vendor_1325, pci_dev_list_1325}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1326, pci_vendor_1326, pci_dev_list_1326}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1327, pci_vendor_1327, pci_dev_list_1327}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1328, pci_vendor_1328, pci_dev_list_1328}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1329, pci_vendor_1329, pci_dev_list_1329}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132a, pci_vendor_132a, pci_dev_list_132a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132b, pci_vendor_132b, pci_dev_list_132b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132c, pci_vendor_132c, pci_dev_list_132c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132d, pci_vendor_132d, pci_dev_list_132d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1330, pci_vendor_1330, pci_dev_list_1330}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1331, pci_vendor_1331, pci_dev_list_1331}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1332, pci_vendor_1332, pci_dev_list_1332}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1334, pci_vendor_1334, pci_dev_list_1334}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1335, pci_vendor_1335, pci_dev_list_1335}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1337, pci_vendor_1337, pci_dev_list_1337}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1338, pci_vendor_1338, pci_dev_list_1338}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133a, pci_vendor_133a, pci_dev_list_133a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133b, pci_vendor_133b, pci_dev_list_133b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133c, pci_vendor_133c, pci_dev_list_133c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133d, pci_vendor_133d, pci_dev_list_133d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133e, pci_vendor_133e, pci_dev_list_133e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133f, pci_vendor_133f, pci_dev_list_133f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1340, pci_vendor_1340, pci_dev_list_1340}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1341, pci_vendor_1341, pci_dev_list_1341}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1342, pci_vendor_1342, pci_dev_list_1342}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1343, pci_vendor_1343, pci_dev_list_1343}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1344, pci_vendor_1344, pci_dev_list_1344}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1345, pci_vendor_1345, pci_dev_list_1345}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1347, pci_vendor_1347, pci_dev_list_1347}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1349, pci_vendor_1349, pci_dev_list_1349}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134a, pci_vendor_134a, pci_dev_list_134a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134b, pci_vendor_134b, pci_dev_list_134b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134c, pci_vendor_134c, pci_dev_list_134c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134d, pci_vendor_134d, pci_dev_list_134d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134e, pci_vendor_134e, pci_dev_list_134e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134f, pci_vendor_134f, pci_dev_list_134f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1350, pci_vendor_1350, pci_dev_list_1350}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1351, pci_vendor_1351, pci_dev_list_1351}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1353, pci_vendor_1353, pci_dev_list_1353}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1354, pci_vendor_1354, pci_dev_list_1354}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1355, pci_vendor_1355, pci_dev_list_1355}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1356, pci_vendor_1356, pci_dev_list_1356}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1359, pci_vendor_1359, pci_dev_list_1359}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135a, pci_vendor_135a, pci_dev_list_135a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135b, pci_vendor_135b, pci_dev_list_135b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135c, pci_vendor_135c, pci_dev_list_135c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135d, pci_vendor_135d, pci_dev_list_135d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135e, pci_vendor_135e, pci_dev_list_135e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135f, pci_vendor_135f, pci_dev_list_135f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1360, pci_vendor_1360, pci_dev_list_1360}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1361, pci_vendor_1361, pci_dev_list_1361}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1362, pci_vendor_1362, pci_dev_list_1362}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1363, pci_vendor_1363, pci_dev_list_1363}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1364, pci_vendor_1364, pci_dev_list_1364}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1365, pci_vendor_1365, pci_dev_list_1365}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1366, pci_vendor_1366, pci_dev_list_1366}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1367, pci_vendor_1367, pci_dev_list_1367}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1368, pci_vendor_1368, pci_dev_list_1368}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1369, pci_vendor_1369, pci_dev_list_1369}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136a, pci_vendor_136a, pci_dev_list_136a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136b, pci_vendor_136b, pci_dev_list_136b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136c, pci_vendor_136c, pci_dev_list_136c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136d, pci_vendor_136d, pci_dev_list_136d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136f, pci_vendor_136f, pci_dev_list_136f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1370, pci_vendor_1370, pci_dev_list_1370}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1371, pci_vendor_1371, pci_dev_list_1371}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1373, pci_vendor_1373, pci_dev_list_1373}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1374, pci_vendor_1374, pci_dev_list_1374}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1375, pci_vendor_1375, pci_dev_list_1375}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1376, pci_vendor_1376, pci_dev_list_1376}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1377, pci_vendor_1377, pci_dev_list_1377}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1378, pci_vendor_1378, pci_dev_list_1378}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1379, pci_vendor_1379, pci_dev_list_1379}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137a, pci_vendor_137a, pci_dev_list_137a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137b, pci_vendor_137b, pci_dev_list_137b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137c, pci_vendor_137c, pci_dev_list_137c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137d, pci_vendor_137d, pci_dev_list_137d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137e, pci_vendor_137e, pci_dev_list_137e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137f, pci_vendor_137f, pci_dev_list_137f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1380, pci_vendor_1380, pci_dev_list_1380}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1381, pci_vendor_1381, pci_dev_list_1381}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1382, pci_vendor_1382, pci_dev_list_1382}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1383, pci_vendor_1383, pci_dev_list_1383}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1384, pci_vendor_1384, pci_dev_list_1384}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1385, pci_vendor_1385, pci_dev_list_1385}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1386, pci_vendor_1386, pci_dev_list_1386}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1387, pci_vendor_1387, pci_dev_list_1387}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1388, pci_vendor_1388, pci_dev_list_1388}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1389, pci_vendor_1389, pci_dev_list_1389}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138a, pci_vendor_138a, pci_dev_list_138a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138b, pci_vendor_138b, pci_dev_list_138b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138c, pci_vendor_138c, pci_dev_list_138c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138d, pci_vendor_138d, pci_dev_list_138d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138e, pci_vendor_138e, pci_dev_list_138e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138f, pci_vendor_138f, pci_dev_list_138f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1390, pci_vendor_1390, pci_dev_list_1390}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1391, pci_vendor_1391, pci_dev_list_1391}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1392, pci_vendor_1392, pci_dev_list_1392}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1393, pci_vendor_1393, pci_dev_list_1393}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1394, pci_vendor_1394, pci_dev_list_1394}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1395, pci_vendor_1395, pci_dev_list_1395}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1396, pci_vendor_1396, pci_dev_list_1396}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1397, pci_vendor_1397, pci_dev_list_1397}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1398, pci_vendor_1398, pci_dev_list_1398}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1399, pci_vendor_1399, pci_dev_list_1399}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139a, pci_vendor_139a, pci_dev_list_139a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139b, pci_vendor_139b, pci_dev_list_139b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139c, pci_vendor_139c, pci_dev_list_139c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139d, pci_vendor_139d, pci_dev_list_139d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139e, pci_vendor_139e, pci_dev_list_139e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139f, pci_vendor_139f, pci_dev_list_139f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a0, pci_vendor_13a0, pci_dev_list_13a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a1, pci_vendor_13a1, pci_dev_list_13a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a2, pci_vendor_13a2, pci_dev_list_13a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a3, pci_vendor_13a3, pci_dev_list_13a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a4, pci_vendor_13a4, pci_dev_list_13a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a5, pci_vendor_13a5, pci_dev_list_13a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a6, pci_vendor_13a6, pci_dev_list_13a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a7, pci_vendor_13a7, pci_dev_list_13a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a8, pci_vendor_13a8, pci_dev_list_13a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a9, pci_vendor_13a9, pci_dev_list_13a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13aa, pci_vendor_13aa, pci_dev_list_13aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ab, pci_vendor_13ab, pci_dev_list_13ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ac, pci_vendor_13ac, pci_dev_list_13ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ad, pci_vendor_13ad, pci_dev_list_13ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ae, pci_vendor_13ae, pci_dev_list_13ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13af, pci_vendor_13af, pci_dev_list_13af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b0, pci_vendor_13b0, pci_dev_list_13b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b1, pci_vendor_13b1, pci_dev_list_13b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b2, pci_vendor_13b2, pci_dev_list_13b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b3, pci_vendor_13b3, pci_dev_list_13b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b4, pci_vendor_13b4, pci_dev_list_13b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b5, pci_vendor_13b5, pci_dev_list_13b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b6, pci_vendor_13b6, pci_dev_list_13b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b7, pci_vendor_13b7, pci_dev_list_13b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b8, pci_vendor_13b8, pci_dev_list_13b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b9, pci_vendor_13b9, pci_dev_list_13b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ba, pci_vendor_13ba, pci_dev_list_13ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bb, pci_vendor_13bb, pci_dev_list_13bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bc, pci_vendor_13bc, pci_dev_list_13bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bd, pci_vendor_13bd, pci_dev_list_13bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13be, pci_vendor_13be, pci_dev_list_13be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bf, pci_vendor_13bf, pci_dev_list_13bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c0, pci_vendor_13c0, pci_dev_list_13c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c1, pci_vendor_13c1, pci_dev_list_13c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c2, pci_vendor_13c2, pci_dev_list_13c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c3, pci_vendor_13c3, pci_dev_list_13c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c4, pci_vendor_13c4, pci_dev_list_13c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c5, pci_vendor_13c5, pci_dev_list_13c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c6, pci_vendor_13c6, pci_dev_list_13c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c7, pci_vendor_13c7, pci_dev_list_13c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c8, pci_vendor_13c8, pci_dev_list_13c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c9, pci_vendor_13c9, pci_dev_list_13c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ca, pci_vendor_13ca, pci_dev_list_13ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cb, pci_vendor_13cb, pci_dev_list_13cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cc, pci_vendor_13cc, pci_dev_list_13cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cd, pci_vendor_13cd, pci_dev_list_13cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ce, pci_vendor_13ce, pci_dev_list_13ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cf, pci_vendor_13cf, pci_dev_list_13cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d0, pci_vendor_13d0, pci_dev_list_13d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d1, pci_vendor_13d1, pci_dev_list_13d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d2, pci_vendor_13d2, pci_dev_list_13d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d3, pci_vendor_13d3, pci_dev_list_13d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d4, pci_vendor_13d4, pci_dev_list_13d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d5, pci_vendor_13d5, pci_dev_list_13d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d6, pci_vendor_13d6, pci_dev_list_13d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d7, pci_vendor_13d7, pci_dev_list_13d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d8, pci_vendor_13d8, pci_dev_list_13d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d9, pci_vendor_13d9, pci_dev_list_13d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13da, pci_vendor_13da, pci_dev_list_13da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13db, pci_vendor_13db, pci_dev_list_13db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13dc, pci_vendor_13dc, pci_dev_list_13dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13dd, pci_vendor_13dd, pci_dev_list_13dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13de, pci_vendor_13de, pci_dev_list_13de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13df, pci_vendor_13df, pci_dev_list_13df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e0, pci_vendor_13e0, pci_dev_list_13e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e1, pci_vendor_13e1, pci_dev_list_13e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e2, pci_vendor_13e2, pci_dev_list_13e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e3, pci_vendor_13e3, pci_dev_list_13e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e4, pci_vendor_13e4, pci_dev_list_13e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e5, pci_vendor_13e5, pci_dev_list_13e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e6, pci_vendor_13e6, pci_dev_list_13e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e7, pci_vendor_13e7, pci_dev_list_13e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e8, pci_vendor_13e8, pci_dev_list_13e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e9, pci_vendor_13e9, pci_dev_list_13e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ea, pci_vendor_13ea, pci_dev_list_13ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13eb, pci_vendor_13eb, pci_dev_list_13eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ec, pci_vendor_13ec, pci_dev_list_13ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ed, pci_vendor_13ed, pci_dev_list_13ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ee, pci_vendor_13ee, pci_dev_list_13ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ef, pci_vendor_13ef, pci_dev_list_13ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f0, pci_vendor_13f0, pci_dev_list_13f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f1, pci_vendor_13f1, pci_dev_list_13f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f2, pci_vendor_13f2, pci_dev_list_13f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f3, pci_vendor_13f3, pci_dev_list_13f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f4, pci_vendor_13f4, pci_dev_list_13f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f5, pci_vendor_13f5, pci_dev_list_13f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f6, pci_vendor_13f6, pci_dev_list_13f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f7, pci_vendor_13f7, pci_dev_list_13f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f8, pci_vendor_13f8, pci_dev_list_13f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f9, pci_vendor_13f9, pci_dev_list_13f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fa, pci_vendor_13fa, pci_dev_list_13fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fb, pci_vendor_13fb, pci_dev_list_13fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fc, pci_vendor_13fc, pci_dev_list_13fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fd, pci_vendor_13fd, pci_dev_list_13fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fe, pci_vendor_13fe, pci_dev_list_13fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ff, pci_vendor_13ff, pci_dev_list_13ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1400, pci_vendor_1400, pci_dev_list_1400}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1401, pci_vendor_1401, pci_dev_list_1401}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1402, pci_vendor_1402, pci_dev_list_1402}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1403, pci_vendor_1403, pci_dev_list_1403}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1404, pci_vendor_1404, pci_dev_list_1404}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1405, pci_vendor_1405, pci_dev_list_1405}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1406, pci_vendor_1406, pci_dev_list_1406}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1407, pci_vendor_1407, pci_dev_list_1407}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1408, pci_vendor_1408, pci_dev_list_1408}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1409, pci_vendor_1409, pci_dev_list_1409}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140a, pci_vendor_140a, pci_dev_list_140a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140b, pci_vendor_140b, pci_dev_list_140b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140c, pci_vendor_140c, pci_dev_list_140c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140d, pci_vendor_140d, pci_dev_list_140d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140e, pci_vendor_140e, pci_dev_list_140e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140f, pci_vendor_140f, pci_dev_list_140f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1410, pci_vendor_1410, pci_dev_list_1410}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1411, pci_vendor_1411, pci_dev_list_1411}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1412, pci_vendor_1412, pci_dev_list_1412}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1413, pci_vendor_1413, pci_dev_list_1413}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1414, pci_vendor_1414, pci_dev_list_1414}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1415, pci_vendor_1415, pci_dev_list_1415}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1416, pci_vendor_1416, pci_dev_list_1416}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1417, pci_vendor_1417, pci_dev_list_1417}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1418, pci_vendor_1418, pci_dev_list_1418}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1419, pci_vendor_1419, pci_dev_list_1419}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141a, pci_vendor_141a, pci_dev_list_141a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141b, pci_vendor_141b, pci_dev_list_141b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141d, pci_vendor_141d, pci_dev_list_141d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141e, pci_vendor_141e, pci_dev_list_141e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141f, pci_vendor_141f, pci_dev_list_141f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1420, pci_vendor_1420, pci_dev_list_1420}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1421, pci_vendor_1421, pci_dev_list_1421}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1422, pci_vendor_1422, pci_dev_list_1422}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1423, pci_vendor_1423, pci_dev_list_1423}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1424, pci_vendor_1424, pci_dev_list_1424}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1425, pci_vendor_1425, pci_dev_list_1425}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1426, pci_vendor_1426, pci_dev_list_1426}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1427, pci_vendor_1427, pci_dev_list_1427}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1428, pci_vendor_1428, pci_dev_list_1428}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1429, pci_vendor_1429, pci_dev_list_1429}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142a, pci_vendor_142a, pci_dev_list_142a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142b, pci_vendor_142b, pci_dev_list_142b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142c, pci_vendor_142c, pci_dev_list_142c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142d, pci_vendor_142d, pci_dev_list_142d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142e, pci_vendor_142e, pci_dev_list_142e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142f, pci_vendor_142f, pci_dev_list_142f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1430, pci_vendor_1430, pci_dev_list_1430}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1431, pci_vendor_1431, pci_dev_list_1431}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1432, pci_vendor_1432, pci_dev_list_1432}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1433, pci_vendor_1433, pci_dev_list_1433}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1435, pci_vendor_1435, pci_dev_list_1435}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1436, pci_vendor_1436, pci_dev_list_1436}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1437, pci_vendor_1437, pci_dev_list_1437}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1438, pci_vendor_1438, pci_dev_list_1438}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1439, pci_vendor_1439, pci_dev_list_1439}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143a, pci_vendor_143a, pci_dev_list_143a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143b, pci_vendor_143b, pci_dev_list_143b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143c, pci_vendor_143c, pci_dev_list_143c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143d, pci_vendor_143d, pci_dev_list_143d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143e, pci_vendor_143e, pci_dev_list_143e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143f, pci_vendor_143f, pci_dev_list_143f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1440, pci_vendor_1440, pci_dev_list_1440}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1441, pci_vendor_1441, pci_dev_list_1441}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1442, pci_vendor_1442, pci_dev_list_1442}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1443, pci_vendor_1443, pci_dev_list_1443}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1444, pci_vendor_1444, pci_dev_list_1444}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1445, pci_vendor_1445, pci_dev_list_1445}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1446, pci_vendor_1446, pci_dev_list_1446}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1447, pci_vendor_1447, pci_dev_list_1447}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1448, pci_vendor_1448, pci_dev_list_1448}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1449, pci_vendor_1449, pci_dev_list_1449}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144a, pci_vendor_144a, pci_dev_list_144a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144b, pci_vendor_144b, pci_dev_list_144b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144c, pci_vendor_144c, pci_dev_list_144c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144d, pci_vendor_144d, pci_dev_list_144d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144e, pci_vendor_144e, pci_dev_list_144e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144f, pci_vendor_144f, pci_dev_list_144f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1450, pci_vendor_1450, pci_dev_list_1450}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1451, pci_vendor_1451, pci_dev_list_1451}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1453, pci_vendor_1453, pci_dev_list_1453}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1454, pci_vendor_1454, pci_dev_list_1454}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1455, pci_vendor_1455, pci_dev_list_1455}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1456, pci_vendor_1456, pci_dev_list_1456}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1457, pci_vendor_1457, pci_dev_list_1457}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1458, pci_vendor_1458, pci_dev_list_1458}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1459, pci_vendor_1459, pci_dev_list_1459}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145a, pci_vendor_145a, pci_dev_list_145a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145b, pci_vendor_145b, pci_dev_list_145b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145c, pci_vendor_145c, pci_dev_list_145c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145d, pci_vendor_145d, pci_dev_list_145d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145e, pci_vendor_145e, pci_dev_list_145e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145f, pci_vendor_145f, pci_dev_list_145f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1460, pci_vendor_1460, pci_dev_list_1460}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1461, pci_vendor_1461, pci_dev_list_1461}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1462, pci_vendor_1462, pci_dev_list_1462}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1463, pci_vendor_1463, pci_dev_list_1463}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1464, pci_vendor_1464, pci_dev_list_1464}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1465, pci_vendor_1465, pci_dev_list_1465}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1466, pci_vendor_1466, pci_dev_list_1466}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1467, pci_vendor_1467, pci_dev_list_1467}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1468, pci_vendor_1468, pci_dev_list_1468}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1469, pci_vendor_1469, pci_dev_list_1469}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146a, pci_vendor_146a, pci_dev_list_146a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146b, pci_vendor_146b, pci_dev_list_146b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146c, pci_vendor_146c, pci_dev_list_146c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146d, pci_vendor_146d, pci_dev_list_146d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146e, pci_vendor_146e, pci_dev_list_146e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146f, pci_vendor_146f, pci_dev_list_146f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1470, pci_vendor_1470, pci_dev_list_1470}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1471, pci_vendor_1471, pci_dev_list_1471}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1472, pci_vendor_1472, pci_dev_list_1472}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1473, pci_vendor_1473, pci_dev_list_1473}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1474, pci_vendor_1474, pci_dev_list_1474}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1475, pci_vendor_1475, pci_dev_list_1475}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1476, pci_vendor_1476, pci_dev_list_1476}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1477, pci_vendor_1477, pci_dev_list_1477}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1478, pci_vendor_1478, pci_dev_list_1478}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1479, pci_vendor_1479, pci_dev_list_1479}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147a, pci_vendor_147a, pci_dev_list_147a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147b, pci_vendor_147b, pci_dev_list_147b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147c, pci_vendor_147c, pci_dev_list_147c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147d, pci_vendor_147d, pci_dev_list_147d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147e, pci_vendor_147e, pci_dev_list_147e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147f, pci_vendor_147f, pci_dev_list_147f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1480, pci_vendor_1480, pci_dev_list_1480}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1481, pci_vendor_1481, pci_dev_list_1481}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1482, pci_vendor_1482, pci_dev_list_1482}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1483, pci_vendor_1483, pci_dev_list_1483}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1484, pci_vendor_1484, pci_dev_list_1484}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1485, pci_vendor_1485, pci_dev_list_1485}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1486, pci_vendor_1486, pci_dev_list_1486}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1487, pci_vendor_1487, pci_dev_list_1487}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1488, pci_vendor_1488, pci_dev_list_1488}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1489, pci_vendor_1489, pci_dev_list_1489}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148a, pci_vendor_148a, pci_dev_list_148a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148b, pci_vendor_148b, pci_dev_list_148b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148c, pci_vendor_148c, pci_dev_list_148c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148d, pci_vendor_148d, pci_dev_list_148d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148e, pci_vendor_148e, pci_dev_list_148e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148f, pci_vendor_148f, pci_dev_list_148f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1490, pci_vendor_1490, pci_dev_list_1490}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1491, pci_vendor_1491, pci_dev_list_1491}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1492, pci_vendor_1492, pci_dev_list_1492}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1493, pci_vendor_1493, pci_dev_list_1493}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1494, pci_vendor_1494, pci_dev_list_1494}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1495, pci_vendor_1495, pci_dev_list_1495}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1496, pci_vendor_1496, pci_dev_list_1496}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1497, pci_vendor_1497, pci_dev_list_1497}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1498, pci_vendor_1498, pci_dev_list_1498}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1499, pci_vendor_1499, pci_dev_list_1499}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149a, pci_vendor_149a, pci_dev_list_149a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149b, pci_vendor_149b, pci_dev_list_149b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149c, pci_vendor_149c, pci_dev_list_149c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149d, pci_vendor_149d, pci_dev_list_149d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149e, pci_vendor_149e, pci_dev_list_149e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149f, pci_vendor_149f, pci_dev_list_149f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a0, pci_vendor_14a0, pci_dev_list_14a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a1, pci_vendor_14a1, pci_dev_list_14a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a2, pci_vendor_14a2, pci_dev_list_14a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a3, pci_vendor_14a3, pci_dev_list_14a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a4, pci_vendor_14a4, pci_dev_list_14a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a5, pci_vendor_14a5, pci_dev_list_14a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a6, pci_vendor_14a6, pci_dev_list_14a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a7, pci_vendor_14a7, pci_dev_list_14a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a8, pci_vendor_14a8, pci_dev_list_14a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a9, pci_vendor_14a9, pci_dev_list_14a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14aa, pci_vendor_14aa, pci_dev_list_14aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ab, pci_vendor_14ab, pci_dev_list_14ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ac, pci_vendor_14ac, pci_dev_list_14ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ad, pci_vendor_14ad, pci_dev_list_14ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ae, pci_vendor_14ae, pci_dev_list_14ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14af, pci_vendor_14af, pci_dev_list_14af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b0, pci_vendor_14b0, pci_dev_list_14b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b1, pci_vendor_14b1, pci_dev_list_14b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b2, pci_vendor_14b2, pci_dev_list_14b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b3, pci_vendor_14b3, pci_dev_list_14b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b4, pci_vendor_14b4, pci_dev_list_14b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b5, pci_vendor_14b5, pci_dev_list_14b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b6, pci_vendor_14b6, pci_dev_list_14b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b7, pci_vendor_14b7, pci_dev_list_14b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b8, pci_vendor_14b8, pci_dev_list_14b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b9, pci_vendor_14b9, pci_dev_list_14b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ba, pci_vendor_14ba, pci_dev_list_14ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bb, pci_vendor_14bb, pci_dev_list_14bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bc, pci_vendor_14bc, pci_dev_list_14bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bd, pci_vendor_14bd, pci_dev_list_14bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14be, pci_vendor_14be, pci_dev_list_14be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bf, pci_vendor_14bf, pci_dev_list_14bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c0, pci_vendor_14c0, pci_dev_list_14c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c1, pci_vendor_14c1, pci_dev_list_14c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c2, pci_vendor_14c2, pci_dev_list_14c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c3, pci_vendor_14c3, pci_dev_list_14c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c4, pci_vendor_14c4, pci_dev_list_14c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c5, pci_vendor_14c5, pci_dev_list_14c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c6, pci_vendor_14c6, pci_dev_list_14c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c7, pci_vendor_14c7, pci_dev_list_14c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c8, pci_vendor_14c8, pci_dev_list_14c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c9, pci_vendor_14c9, pci_dev_list_14c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ca, pci_vendor_14ca, pci_dev_list_14ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cb, pci_vendor_14cb, pci_dev_list_14cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cc, pci_vendor_14cc, pci_dev_list_14cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cd, pci_vendor_14cd, pci_dev_list_14cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ce, pci_vendor_14ce, pci_dev_list_14ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cf, pci_vendor_14cf, pci_dev_list_14cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d0, pci_vendor_14d0, pci_dev_list_14d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d1, pci_vendor_14d1, pci_dev_list_14d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d2, pci_vendor_14d2, pci_dev_list_14d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d3, pci_vendor_14d3, pci_dev_list_14d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d4, pci_vendor_14d4, pci_dev_list_14d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d5, pci_vendor_14d5, pci_dev_list_14d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d6, pci_vendor_14d6, pci_dev_list_14d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d7, pci_vendor_14d7, pci_dev_list_14d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d8, pci_vendor_14d8, pci_dev_list_14d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d9, pci_vendor_14d9, pci_dev_list_14d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14da, pci_vendor_14da, pci_dev_list_14da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14db, pci_vendor_14db, pci_dev_list_14db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14dc, pci_vendor_14dc, pci_dev_list_14dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14dd, pci_vendor_14dd, pci_dev_list_14dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14de, pci_vendor_14de, pci_dev_list_14de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14df, pci_vendor_14df, pci_dev_list_14df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e1, pci_vendor_14e1, pci_dev_list_14e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e2, pci_vendor_14e2, pci_dev_list_14e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e3, pci_vendor_14e3, pci_dev_list_14e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e4, pci_vendor_14e4, pci_dev_list_14e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e5, pci_vendor_14e5, pci_dev_list_14e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e6, pci_vendor_14e6, pci_dev_list_14e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e7, pci_vendor_14e7, pci_dev_list_14e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e8, pci_vendor_14e8, pci_dev_list_14e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e9, pci_vendor_14e9, pci_dev_list_14e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ea, pci_vendor_14ea, pci_dev_list_14ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14eb, pci_vendor_14eb, pci_dev_list_14eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ec, pci_vendor_14ec, pci_dev_list_14ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ed, pci_vendor_14ed, pci_dev_list_14ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ee, pci_vendor_14ee, pci_dev_list_14ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ef, pci_vendor_14ef, pci_dev_list_14ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f0, pci_vendor_14f0, pci_dev_list_14f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f1, pci_vendor_14f1, pci_dev_list_14f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f2, pci_vendor_14f2, pci_dev_list_14f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f3, pci_vendor_14f3, pci_dev_list_14f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f4, pci_vendor_14f4, pci_dev_list_14f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f5, pci_vendor_14f5, pci_dev_list_14f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f6, pci_vendor_14f6, pci_dev_list_14f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f7, pci_vendor_14f7, pci_dev_list_14f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f8, pci_vendor_14f8, pci_dev_list_14f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f9, pci_vendor_14f9, pci_dev_list_14f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fa, pci_vendor_14fa, pci_dev_list_14fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fb, pci_vendor_14fb, pci_dev_list_14fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fc, pci_vendor_14fc, pci_dev_list_14fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fd, pci_vendor_14fd, pci_dev_list_14fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fe, pci_vendor_14fe, pci_dev_list_14fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ff, pci_vendor_14ff, pci_dev_list_14ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1500, pci_vendor_1500, pci_dev_list_1500}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1501, pci_vendor_1501, pci_dev_list_1501}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1502, pci_vendor_1502, pci_dev_list_1502}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1503, pci_vendor_1503, pci_dev_list_1503}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1504, pci_vendor_1504, pci_dev_list_1504}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1505, pci_vendor_1505, pci_dev_list_1505}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1506, pci_vendor_1506, pci_dev_list_1506}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1507, pci_vendor_1507, pci_dev_list_1507}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1508, pci_vendor_1508, pci_dev_list_1508}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1509, pci_vendor_1509, pci_dev_list_1509}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150a, pci_vendor_150a, pci_dev_list_150a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150b, pci_vendor_150b, pci_dev_list_150b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150c, pci_vendor_150c, pci_dev_list_150c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150d, pci_vendor_150d, pci_dev_list_150d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150e, pci_vendor_150e, pci_dev_list_150e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150f, pci_vendor_150f, pci_dev_list_150f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1510, pci_vendor_1510, pci_dev_list_1510}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1511, pci_vendor_1511, pci_dev_list_1511}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1512, pci_vendor_1512, pci_dev_list_1512}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1513, pci_vendor_1513, pci_dev_list_1513}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1514, pci_vendor_1514, pci_dev_list_1514}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1515, pci_vendor_1515, pci_dev_list_1515}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1516, pci_vendor_1516, pci_dev_list_1516}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1517, pci_vendor_1517, pci_dev_list_1517}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1518, pci_vendor_1518, pci_dev_list_1518}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1519, pci_vendor_1519, pci_dev_list_1519}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151a, pci_vendor_151a, pci_dev_list_151a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151b, pci_vendor_151b, pci_dev_list_151b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151c, pci_vendor_151c, pci_dev_list_151c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151d, pci_vendor_151d, pci_dev_list_151d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151e, pci_vendor_151e, pci_dev_list_151e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151f, pci_vendor_151f, pci_dev_list_151f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1520, pci_vendor_1520, pci_dev_list_1520}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1521, pci_vendor_1521, pci_dev_list_1521}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1522, pci_vendor_1522, pci_dev_list_1522}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1523, pci_vendor_1523, pci_dev_list_1523}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1524, pci_vendor_1524, pci_dev_list_1524}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1525, pci_vendor_1525, pci_dev_list_1525}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1526, pci_vendor_1526, pci_dev_list_1526}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1527, pci_vendor_1527, pci_dev_list_1527}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1528, pci_vendor_1528, pci_dev_list_1528}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1529, pci_vendor_1529, pci_dev_list_1529}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152a, pci_vendor_152a, pci_dev_list_152a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152b, pci_vendor_152b, pci_dev_list_152b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152c, pci_vendor_152c, pci_dev_list_152c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152d, pci_vendor_152d, pci_dev_list_152d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152e, pci_vendor_152e, pci_dev_list_152e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152f, pci_vendor_152f, pci_dev_list_152f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1530, pci_vendor_1530, pci_dev_list_1530}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1531, pci_vendor_1531, pci_dev_list_1531}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1532, pci_vendor_1532, pci_dev_list_1532}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1533, pci_vendor_1533, pci_dev_list_1533}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1534, pci_vendor_1534, pci_dev_list_1534}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1535, pci_vendor_1535, pci_dev_list_1535}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1537, pci_vendor_1537, pci_dev_list_1537}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1538, pci_vendor_1538, pci_dev_list_1538}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1539, pci_vendor_1539, pci_dev_list_1539}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153a, pci_vendor_153a, pci_dev_list_153a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153b, pci_vendor_153b, pci_dev_list_153b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153c, pci_vendor_153c, pci_dev_list_153c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153d, pci_vendor_153d, pci_dev_list_153d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153e, pci_vendor_153e, pci_dev_list_153e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153f, pci_vendor_153f, pci_dev_list_153f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1540, pci_vendor_1540, pci_dev_list_1540}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1541, pci_vendor_1541, pci_dev_list_1541}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1542, pci_vendor_1542, pci_dev_list_1542}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1543, pci_vendor_1543, pci_dev_list_1543}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1544, pci_vendor_1544, pci_dev_list_1544}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1545, pci_vendor_1545, pci_dev_list_1545}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1546, pci_vendor_1546, pci_dev_list_1546}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1547, pci_vendor_1547, pci_dev_list_1547}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1548, pci_vendor_1548, pci_dev_list_1548}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1549, pci_vendor_1549, pci_dev_list_1549}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154a, pci_vendor_154a, pci_dev_list_154a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154b, pci_vendor_154b, pci_dev_list_154b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154c, pci_vendor_154c, pci_dev_list_154c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154d, pci_vendor_154d, pci_dev_list_154d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154e, pci_vendor_154e, pci_dev_list_154e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154f, pci_vendor_154f, pci_dev_list_154f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1550, pci_vendor_1550, pci_dev_list_1550}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1551, pci_vendor_1551, pci_dev_list_1551}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1552, pci_vendor_1552, pci_dev_list_1552}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1553, pci_vendor_1553, pci_dev_list_1553}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1554, pci_vendor_1554, pci_dev_list_1554}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1555, pci_vendor_1555, pci_dev_list_1555}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1556, pci_vendor_1556, pci_dev_list_1556}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1557, pci_vendor_1557, pci_dev_list_1557}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1558, pci_vendor_1558, pci_dev_list_1558}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1559, pci_vendor_1559, pci_dev_list_1559}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155a, pci_vendor_155a, pci_dev_list_155a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155b, pci_vendor_155b, pci_dev_list_155b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155c, pci_vendor_155c, pci_dev_list_155c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155d, pci_vendor_155d, pci_dev_list_155d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155e, pci_vendor_155e, pci_dev_list_155e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155f, pci_vendor_155f, pci_dev_list_155f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1560, pci_vendor_1560, pci_dev_list_1560}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1561, pci_vendor_1561, pci_dev_list_1561}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1562, pci_vendor_1562, pci_dev_list_1562}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1563, pci_vendor_1563, pci_dev_list_1563}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1564, pci_vendor_1564, pci_dev_list_1564}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1565, pci_vendor_1565, pci_dev_list_1565}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1566, pci_vendor_1566, pci_dev_list_1566}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1567, pci_vendor_1567, pci_dev_list_1567}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1568, pci_vendor_1568, pci_dev_list_1568}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1569, pci_vendor_1569, pci_dev_list_1569}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156a, pci_vendor_156a, pci_dev_list_156a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156b, pci_vendor_156b, pci_dev_list_156b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156c, pci_vendor_156c, pci_dev_list_156c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156d, pci_vendor_156d, pci_dev_list_156d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156e, pci_vendor_156e, pci_dev_list_156e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156f, pci_vendor_156f, pci_dev_list_156f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1570, pci_vendor_1570, pci_dev_list_1570}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1571, pci_vendor_1571, pci_dev_list_1571}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1572, pci_vendor_1572, pci_dev_list_1572}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1573, pci_vendor_1573, pci_dev_list_1573}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1574, pci_vendor_1574, pci_dev_list_1574}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1575, pci_vendor_1575, pci_dev_list_1575}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1576, pci_vendor_1576, pci_dev_list_1576}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1578, pci_vendor_1578, pci_dev_list_1578}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1579, pci_vendor_1579, pci_dev_list_1579}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157a, pci_vendor_157a, pci_dev_list_157a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157b, pci_vendor_157b, pci_dev_list_157b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157c, pci_vendor_157c, pci_dev_list_157c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157d, pci_vendor_157d, pci_dev_list_157d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157e, pci_vendor_157e, pci_dev_list_157e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157f, pci_vendor_157f, pci_dev_list_157f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1580, pci_vendor_1580, pci_dev_list_1580}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1581, pci_vendor_1581, pci_dev_list_1581}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1582, pci_vendor_1582, pci_dev_list_1582}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1583, pci_vendor_1583, pci_dev_list_1583}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1584, pci_vendor_1584, pci_dev_list_1584}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1585, pci_vendor_1585, pci_dev_list_1585}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1586, pci_vendor_1586, pci_dev_list_1586}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1587, pci_vendor_1587, pci_dev_list_1587}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1588, pci_vendor_1588, pci_dev_list_1588}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1589, pci_vendor_1589, pci_dev_list_1589}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158a, pci_vendor_158a, pci_dev_list_158a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158b, pci_vendor_158b, pci_dev_list_158b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158c, pci_vendor_158c, pci_dev_list_158c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158d, pci_vendor_158d, pci_dev_list_158d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158e, pci_vendor_158e, pci_dev_list_158e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158f, pci_vendor_158f, pci_dev_list_158f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1590, pci_vendor_1590, pci_dev_list_1590}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1591, pci_vendor_1591, pci_dev_list_1591}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1592, pci_vendor_1592, pci_dev_list_1592}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1593, pci_vendor_1593, pci_dev_list_1593}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1594, pci_vendor_1594, pci_dev_list_1594}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1595, pci_vendor_1595, pci_dev_list_1595}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1596, pci_vendor_1596, pci_dev_list_1596}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1597, pci_vendor_1597, pci_dev_list_1597}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1598, pci_vendor_1598, pci_dev_list_1598}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1599, pci_vendor_1599, pci_dev_list_1599}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159a, pci_vendor_159a, pci_dev_list_159a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159b, pci_vendor_159b, pci_dev_list_159b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159c, pci_vendor_159c, pci_dev_list_159c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159d, pci_vendor_159d, pci_dev_list_159d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159e, pci_vendor_159e, pci_dev_list_159e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159f, pci_vendor_159f, pci_dev_list_159f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a0, pci_vendor_15a0, pci_dev_list_15a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a1, pci_vendor_15a1, pci_dev_list_15a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a2, pci_vendor_15a2, pci_dev_list_15a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a3, pci_vendor_15a3, pci_dev_list_15a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a4, pci_vendor_15a4, pci_dev_list_15a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a5, pci_vendor_15a5, pci_dev_list_15a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a6, pci_vendor_15a6, pci_dev_list_15a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a7, pci_vendor_15a7, pci_dev_list_15a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a8, pci_vendor_15a8, pci_dev_list_15a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15aa, pci_vendor_15aa, pci_dev_list_15aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ab, pci_vendor_15ab, pci_dev_list_15ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ac, pci_vendor_15ac, pci_dev_list_15ac}, +#endif + {0x15ad, pci_vendor_15ad, pci_dev_list_15ad}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ae, pci_vendor_15ae, pci_dev_list_15ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b0, pci_vendor_15b0, pci_dev_list_15b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b1, pci_vendor_15b1, pci_dev_list_15b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b2, pci_vendor_15b2, pci_dev_list_15b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b3, pci_vendor_15b3, pci_dev_list_15b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b4, pci_vendor_15b4, pci_dev_list_15b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b5, pci_vendor_15b5, pci_dev_list_15b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b6, pci_vendor_15b6, pci_dev_list_15b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b7, pci_vendor_15b7, pci_dev_list_15b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b8, pci_vendor_15b8, pci_dev_list_15b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b9, pci_vendor_15b9, pci_dev_list_15b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ba, pci_vendor_15ba, pci_dev_list_15ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bb, pci_vendor_15bb, pci_dev_list_15bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bc, pci_vendor_15bc, pci_dev_list_15bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bd, pci_vendor_15bd, pci_dev_list_15bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15be, pci_vendor_15be, pci_dev_list_15be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bf, pci_vendor_15bf, pci_dev_list_15bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c0, pci_vendor_15c0, pci_dev_list_15c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c1, pci_vendor_15c1, pci_dev_list_15c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c2, pci_vendor_15c2, pci_dev_list_15c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c3, pci_vendor_15c3, pci_dev_list_15c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c4, pci_vendor_15c4, pci_dev_list_15c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c5, pci_vendor_15c5, pci_dev_list_15c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c6, pci_vendor_15c6, pci_dev_list_15c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c7, pci_vendor_15c7, pci_dev_list_15c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c8, pci_vendor_15c8, pci_dev_list_15c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c9, pci_vendor_15c9, pci_dev_list_15c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ca, pci_vendor_15ca, pci_dev_list_15ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cb, pci_vendor_15cb, pci_dev_list_15cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cc, pci_vendor_15cc, pci_dev_list_15cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cd, pci_vendor_15cd, pci_dev_list_15cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ce, pci_vendor_15ce, pci_dev_list_15ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cf, pci_vendor_15cf, pci_dev_list_15cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d1, pci_vendor_15d1, pci_dev_list_15d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d2, pci_vendor_15d2, pci_dev_list_15d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d3, pci_vendor_15d3, pci_dev_list_15d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d4, pci_vendor_15d4, pci_dev_list_15d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d5, pci_vendor_15d5, pci_dev_list_15d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d6, pci_vendor_15d6, pci_dev_list_15d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d7, pci_vendor_15d7, pci_dev_list_15d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d8, pci_vendor_15d8, pci_dev_list_15d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d9, pci_vendor_15d9, pci_dev_list_15d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15da, pci_vendor_15da, pci_dev_list_15da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15db, pci_vendor_15db, pci_dev_list_15db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15dc, pci_vendor_15dc, pci_dev_list_15dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15dd, pci_vendor_15dd, pci_dev_list_15dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15de, pci_vendor_15de, pci_dev_list_15de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15df, pci_vendor_15df, pci_dev_list_15df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e0, pci_vendor_15e0, pci_dev_list_15e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e1, pci_vendor_15e1, pci_dev_list_15e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e2, pci_vendor_15e2, pci_dev_list_15e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e3, pci_vendor_15e3, pci_dev_list_15e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e4, pci_vendor_15e4, pci_dev_list_15e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e5, pci_vendor_15e5, pci_dev_list_15e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e6, pci_vendor_15e6, pci_dev_list_15e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e7, pci_vendor_15e7, pci_dev_list_15e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e8, pci_vendor_15e8, pci_dev_list_15e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e9, pci_vendor_15e9, pci_dev_list_15e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ea, pci_vendor_15ea, pci_dev_list_15ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15eb, pci_vendor_15eb, pci_dev_list_15eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ec, pci_vendor_15ec, pci_dev_list_15ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ed, pci_vendor_15ed, pci_dev_list_15ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ee, pci_vendor_15ee, pci_dev_list_15ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ef, pci_vendor_15ef, pci_dev_list_15ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f0, pci_vendor_15f0, pci_dev_list_15f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f1, pci_vendor_15f1, pci_dev_list_15f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f2, pci_vendor_15f2, pci_dev_list_15f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f3, pci_vendor_15f3, pci_dev_list_15f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f4, pci_vendor_15f4, pci_dev_list_15f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f5, pci_vendor_15f5, pci_dev_list_15f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f6, pci_vendor_15f6, pci_dev_list_15f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f7, pci_vendor_15f7, pci_dev_list_15f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f8, pci_vendor_15f8, pci_dev_list_15f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f9, pci_vendor_15f9, pci_dev_list_15f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fa, pci_vendor_15fa, pci_dev_list_15fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fb, pci_vendor_15fb, pci_dev_list_15fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fc, pci_vendor_15fc, pci_dev_list_15fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fd, pci_vendor_15fd, pci_dev_list_15fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fe, pci_vendor_15fe, pci_dev_list_15fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ff, pci_vendor_15ff, pci_dev_list_15ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1600, pci_vendor_1600, pci_dev_list_1600}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1601, pci_vendor_1601, pci_dev_list_1601}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1602, pci_vendor_1602, pci_dev_list_1602}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1603, pci_vendor_1603, pci_dev_list_1603}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1604, pci_vendor_1604, pci_dev_list_1604}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1605, pci_vendor_1605, pci_dev_list_1605}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1606, pci_vendor_1606, pci_dev_list_1606}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1607, pci_vendor_1607, pci_dev_list_1607}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1608, pci_vendor_1608, pci_dev_list_1608}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1609, pci_vendor_1609, pci_dev_list_1609}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1612, pci_vendor_1612, pci_dev_list_1612}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1619, pci_vendor_1619, pci_dev_list_1619}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x161f, pci_vendor_161f, pci_dev_list_161f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1626, pci_vendor_1626, pci_dev_list_1626}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1629, pci_vendor_1629, pci_dev_list_1629}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1637, pci_vendor_1637, pci_dev_list_1637}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1638, pci_vendor_1638, pci_dev_list_1638}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x163c, pci_vendor_163c, pci_dev_list_163c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1657, pci_vendor_1657, pci_dev_list_1657}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165a, pci_vendor_165a, pci_dev_list_165a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165d, pci_vendor_165d, pci_dev_list_165d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165f, pci_vendor_165f, pci_dev_list_165f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1661, pci_vendor_1661, pci_dev_list_1661}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1668, pci_vendor_1668, pci_dev_list_1668}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x166d, pci_vendor_166d, pci_dev_list_166d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1677, pci_vendor_1677, pci_dev_list_1677}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x167b, pci_vendor_167b, pci_dev_list_167b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x167d, pci_vendor_167d, pci_dev_list_167d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1681, pci_vendor_1681, pci_dev_list_1681}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1682, pci_vendor_1682, pci_dev_list_1682}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1688, pci_vendor_1688, pci_dev_list_1688}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x168c, pci_vendor_168c, pci_dev_list_168c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1695, pci_vendor_1695, pci_dev_list_1695}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x169c, pci_vendor_169c, pci_dev_list_169c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16a5, pci_vendor_16a5, pci_dev_list_16a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ab, pci_vendor_16ab, pci_dev_list_16ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ae, pci_vendor_16ae, pci_dev_list_16ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16af, pci_vendor_16af, pci_dev_list_16af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16b4, pci_vendor_16b4, pci_dev_list_16b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16b8, pci_vendor_16b8, pci_dev_list_16b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16be, pci_vendor_16be, pci_dev_list_16be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16c6, pci_vendor_16c6, pci_dev_list_16c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16c8, pci_vendor_16c8, pci_dev_list_16c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16c9, pci_vendor_16c9, pci_dev_list_16c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ca, pci_vendor_16ca, pci_dev_list_16ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16cd, pci_vendor_16cd, pci_dev_list_16cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ce, pci_vendor_16ce, pci_dev_list_16ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16d5, pci_vendor_16d5, pci_dev_list_16d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16df, pci_vendor_16df, pci_dev_list_16df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16e3, pci_vendor_16e3, pci_dev_list_16e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16e5, pci_vendor_16e5, pci_dev_list_16e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ec, pci_vendor_16ec, pci_dev_list_16ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ed, pci_vendor_16ed, pci_dev_list_16ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f3, pci_vendor_16f3, pci_dev_list_16f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f4, pci_vendor_16f4, pci_dev_list_16f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f6, pci_vendor_16f6, pci_dev_list_16f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1702, pci_vendor_1702, pci_dev_list_1702}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1705, pci_vendor_1705, pci_dev_list_1705}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x170b, pci_vendor_170b, pci_dev_list_170b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x170c, pci_vendor_170c, pci_dev_list_170c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1725, pci_vendor_1725, pci_dev_list_1725}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x172a, pci_vendor_172a, pci_dev_list_172a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1734, pci_vendor_1734, pci_dev_list_1734}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1737, pci_vendor_1737, pci_dev_list_1737}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x173b, pci_vendor_173b, pci_dev_list_173b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1743, pci_vendor_1743, pci_dev_list_1743}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1749, pci_vendor_1749, pci_dev_list_1749}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x174b, pci_vendor_174b, pci_dev_list_174b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x174d, pci_vendor_174d, pci_dev_list_174d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x175c, pci_vendor_175c, pci_dev_list_175c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x175e, pci_vendor_175e, pci_dev_list_175e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1775, pci_vendor_1775, pci_dev_list_1775}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1787, pci_vendor_1787, pci_dev_list_1787}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1796, pci_vendor_1796, pci_dev_list_1796}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1797, pci_vendor_1797, pci_dev_list_1797}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1799, pci_vendor_1799, pci_dev_list_1799}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x179c, pci_vendor_179c, pci_dev_list_179c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17a0, pci_vendor_17a0, pci_dev_list_17a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17aa, pci_vendor_17aa, pci_dev_list_17aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17af, pci_vendor_17af, pci_dev_list_17af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17b3, pci_vendor_17b3, pci_dev_list_17b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17b4, pci_vendor_17b4, pci_dev_list_17b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17c0, pci_vendor_17c0, pci_dev_list_17c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17c2, pci_vendor_17c2, pci_dev_list_17c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cb, pci_vendor_17cb, pci_dev_list_17cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cc, pci_vendor_17cc, pci_dev_list_17cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cf, pci_vendor_17cf, pci_dev_list_17cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17d3, pci_vendor_17d3, pci_dev_list_17d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17d5, pci_vendor_17d5, pci_dev_list_17d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17db, pci_vendor_17db, pci_dev_list_17db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17de, pci_vendor_17de, pci_dev_list_17de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17e4, pci_vendor_17e4, pci_dev_list_17e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17e6, pci_vendor_17e6, pci_dev_list_17e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17ee, pci_vendor_17ee, pci_dev_list_17ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17f2, pci_vendor_17f2, pci_dev_list_17f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17fe, pci_vendor_17fe, pci_dev_list_17fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17ff, pci_vendor_17ff, pci_dev_list_17ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1809, pci_vendor_1809, pci_dev_list_1809}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1813, pci_vendor_1813, pci_dev_list_1813}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1814, pci_vendor_1814, pci_dev_list_1814}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1820, pci_vendor_1820, pci_dev_list_1820}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1822, pci_vendor_1822, pci_dev_list_1822}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x182d, pci_vendor_182d, pci_dev_list_182d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x182e, pci_vendor_182e, pci_dev_list_182e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1830, pci_vendor_1830, pci_dev_list_1830}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x183b, pci_vendor_183b, pci_dev_list_183b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1849, pci_vendor_1849, pci_dev_list_1849}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x184a, pci_vendor_184a, pci_dev_list_184a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1851, pci_vendor_1851, pci_dev_list_1851}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1852, pci_vendor_1852, pci_dev_list_1852}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1853, pci_vendor_1853, pci_dev_list_1853}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1854, pci_vendor_1854, pci_dev_list_1854}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x185b, pci_vendor_185b, pci_dev_list_185b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x185f, pci_vendor_185f, pci_dev_list_185f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1864, pci_vendor_1864, pci_dev_list_1864}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1867, pci_vendor_1867, pci_dev_list_1867}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x187e, pci_vendor_187e, pci_dev_list_187e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1885, pci_vendor_1885, pci_dev_list_1885}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1888, pci_vendor_1888, pci_dev_list_1888}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x188a, pci_vendor_188a, pci_dev_list_188a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1890, pci_vendor_1890, pci_dev_list_1890}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1894, pci_vendor_1894, pci_dev_list_1894}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1896, pci_vendor_1896, pci_dev_list_1896}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18a1, pci_vendor_18a1, pci_dev_list_18a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ac, pci_vendor_18ac, pci_dev_list_18ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18b8, pci_vendor_18b8, pci_dev_list_18b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18bc, pci_vendor_18bc, pci_dev_list_18bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18c3, pci_vendor_18c3, pci_dev_list_18c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18c8, pci_vendor_18c8, pci_dev_list_18c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18c9, pci_vendor_18c9, pci_dev_list_18c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ca, pci_vendor_18ca, pci_dev_list_18ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18d2, pci_vendor_18d2, pci_dev_list_18d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18dd, pci_vendor_18dd, pci_dev_list_18dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18e6, pci_vendor_18e6, pci_dev_list_18e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ec, pci_vendor_18ec, pci_dev_list_18ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18f6, pci_vendor_18f6, pci_dev_list_18f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18f7, pci_vendor_18f7, pci_dev_list_18f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18fb, pci_vendor_18fb, pci_dev_list_18fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1904, pci_vendor_1904, pci_dev_list_1904}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1923, pci_vendor_1923, pci_dev_list_1923}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1924, pci_vendor_1924, pci_dev_list_1924}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x192e, pci_vendor_192e, pci_dev_list_192e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1931, pci_vendor_1931, pci_dev_list_1931}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1942, pci_vendor_1942, pci_dev_list_1942}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x194a, pci_vendor_194a, pci_dev_list_194a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1957, pci_vendor_1957, pci_dev_list_1957}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1958, pci_vendor_1958, pci_dev_list_1958}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1966, pci_vendor_1966, pci_dev_list_1966}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1969, pci_vendor_1969, pci_dev_list_1969}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x196a, pci_vendor_196a, pci_dev_list_196a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x196d, pci_vendor_196d, pci_dev_list_196d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x197b, pci_vendor_197b, pci_dev_list_197b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1989, pci_vendor_1989, pci_dev_list_1989}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1993, pci_vendor_1993, pci_dev_list_1993}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x199a, pci_vendor_199a, pci_dev_list_199a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19a8, pci_vendor_19a8, pci_dev_list_19a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19ac, pci_vendor_19ac, pci_dev_list_19ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19ae, pci_vendor_19ae, pci_dev_list_19ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19d4, pci_vendor_19d4, pci_dev_list_19d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19e2, pci_vendor_19e2, pci_dev_list_19e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19e7, pci_vendor_19e7, pci_dev_list_19e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1a03, pci_vendor_1a03, pci_dev_list_1a03}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1a08, pci_vendor_1a08, pci_dev_list_1a08}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1a1d, pci_vendor_1a1d, pci_dev_list_1a1d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1a29, pci_vendor_1a29, pci_dev_list_1a29}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1a51, pci_vendor_1a51, pci_dev_list_1a51}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1b13, pci_vendor_1b13, pci_dev_list_1b13}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1c1c, pci_vendor_1c1c, pci_dev_list_1c1c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1d44, pci_vendor_1d44, pci_dev_list_1d44}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1de1, pci_vendor_1de1, pci_dev_list_1de1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fc0, pci_vendor_1fc0, pci_dev_list_1fc0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fc1, pci_vendor_1fc1, pci_dev_list_1fc1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fce, pci_vendor_1fce, pci_dev_list_1fce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2000, pci_vendor_2000, pci_dev_list_2000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2001, pci_vendor_2001, pci_dev_list_2001}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2003, pci_vendor_2003, pci_dev_list_2003}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2004, pci_vendor_2004, pci_dev_list_2004}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x21c3, pci_vendor_21c3, pci_dev_list_21c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x22b8, pci_vendor_22b8, pci_dev_list_22b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2348, pci_vendor_2348, pci_dev_list_2348}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2646, pci_vendor_2646, pci_dev_list_2646}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x270b, pci_vendor_270b, pci_dev_list_270b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x270f, pci_vendor_270f, pci_dev_list_270f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2711, pci_vendor_2711, pci_dev_list_2711}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2a15, pci_vendor_2a15, pci_dev_list_2a15}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3000, pci_vendor_3000, pci_dev_list_3000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3142, pci_vendor_3142, pci_dev_list_3142}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3388, pci_vendor_3388, pci_dev_list_3388}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3411, pci_vendor_3411, pci_dev_list_3411}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3513, pci_vendor_3513, pci_dev_list_3513}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3842, pci_vendor_3842, pci_dev_list_3842}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x38ef, pci_vendor_38ef, pci_dev_list_38ef}, +#endif + {0x3d3d, pci_vendor_3d3d, pci_dev_list_3d3d}, + {0x4005, pci_vendor_4005, pci_dev_list_4005}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4033, pci_vendor_4033, pci_dev_list_4033}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4143, pci_vendor_4143, pci_dev_list_4143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4144, pci_vendor_4144, pci_dev_list_4144}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x416c, pci_vendor_416c, pci_dev_list_416c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4321, pci_vendor_4321, pci_dev_list_4321}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4444, pci_vendor_4444, pci_dev_list_4444}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4468, pci_vendor_4468, pci_dev_list_4468}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4594, pci_vendor_4594, pci_dev_list_4594}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x45fb, pci_vendor_45fb, pci_dev_list_45fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4680, pci_vendor_4680, pci_dev_list_4680}, +#endif + {0x4843, pci_vendor_4843, pci_dev_list_4843}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4916, pci_vendor_4916, pci_dev_list_4916}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4943, pci_vendor_4943, pci_dev_list_4943}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x494f, pci_vendor_494f, pci_dev_list_494f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4978, pci_vendor_4978, pci_dev_list_4978}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4a14, pci_vendor_4a14, pci_dev_list_4a14}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4b10, pci_vendor_4b10, pci_dev_list_4b10}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4c48, pci_vendor_4c48, pci_dev_list_4c48}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4c53, pci_vendor_4c53, pci_dev_list_4c53}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4ca1, pci_vendor_4ca1, pci_dev_list_4ca1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4d51, pci_vendor_4d51, pci_dev_list_4d51}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4d54, pci_vendor_4d54, pci_dev_list_4d54}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4ddc, pci_vendor_4ddc, pci_dev_list_4ddc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5046, pci_vendor_5046, pci_dev_list_5046}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5053, pci_vendor_5053, pci_dev_list_5053}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5136, pci_vendor_5136, pci_dev_list_5136}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5143, pci_vendor_5143, pci_dev_list_5143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5145, pci_vendor_5145, pci_dev_list_5145}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5168, pci_vendor_5168, pci_dev_list_5168}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5301, pci_vendor_5301, pci_dev_list_5301}, +#endif + {0x5333, pci_vendor_5333, pci_dev_list_5333}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x544c, pci_vendor_544c, pci_dev_list_544c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5455, pci_vendor_5455, pci_dev_list_5455}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5519, pci_vendor_5519, pci_dev_list_5519}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5544, pci_vendor_5544, pci_dev_list_5544}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5555, pci_vendor_5555, pci_dev_list_5555}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5654, pci_vendor_5654, pci_dev_list_5654}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5700, pci_vendor_5700, pci_dev_list_5700}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5851, pci_vendor_5851, pci_dev_list_5851}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6356, pci_vendor_6356, pci_dev_list_6356}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6374, pci_vendor_6374, pci_dev_list_6374}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6409, pci_vendor_6409, pci_dev_list_6409}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6666, pci_vendor_6666, pci_dev_list_6666}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7063, pci_vendor_7063, pci_dev_list_7063}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7604, pci_vendor_7604, pci_dev_list_7604}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7bde, pci_vendor_7bde, pci_dev_list_7bde}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7fed, pci_vendor_7fed, pci_dev_list_7fed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8008, pci_vendor_8008, pci_dev_list_8008}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x807d, pci_vendor_807d, pci_dev_list_807d}, +#endif + {0x8086, pci_vendor_8086, pci_dev_list_8086}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8401, pci_vendor_8401, pci_dev_list_8401}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8686, pci_vendor_8686, pci_dev_list_8686}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8800, pci_vendor_8800, pci_dev_list_8800}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8866, pci_vendor_8866, pci_dev_list_8866}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8888, pci_vendor_8888, pci_dev_list_8888}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8912, pci_vendor_8912, pci_dev_list_8912}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8c4a, pci_vendor_8c4a, pci_dev_list_8c4a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8e0e, pci_vendor_8e0e, pci_dev_list_8e0e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8e2e, pci_vendor_8e2e, pci_dev_list_8e2e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9004, pci_vendor_9004, pci_dev_list_9004}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9005, pci_vendor_9005, pci_dev_list_9005}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x907f, pci_vendor_907f, pci_dev_list_907f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x919a, pci_vendor_919a, pci_dev_list_919a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9412, pci_vendor_9412, pci_dev_list_9412}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9699, pci_vendor_9699, pci_dev_list_9699}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9710, pci_vendor_9710, pci_dev_list_9710}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9902, pci_vendor_9902, pci_dev_list_9902}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa0a0, pci_vendor_a0a0, pci_dev_list_a0a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa0f1, pci_vendor_a0f1, pci_dev_list_a0f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa200, pci_vendor_a200, pci_dev_list_a200}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa259, pci_vendor_a259, pci_dev_list_a259}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa25b, pci_vendor_a25b, pci_dev_list_a25b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa304, pci_vendor_a304, pci_dev_list_a304}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa727, pci_vendor_a727, pci_dev_list_a727}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xaa42, pci_vendor_aa42, pci_dev_list_aa42}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xac1e, pci_vendor_ac1e, pci_dev_list_ac1e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xac3d, pci_vendor_ac3d, pci_dev_list_ac3d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xaecb, pci_vendor_aecb, pci_dev_list_aecb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xaffe, pci_vendor_affe, pci_dev_list_affe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xb10b, pci_vendor_b10b, pci_dev_list_b10b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xb1b3, pci_vendor_b1b3, pci_dev_list_b1b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xbd11, pci_vendor_bd11, pci_dev_list_bd11}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc001, pci_vendor_c001, pci_dev_list_c001}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc0a9, pci_vendor_c0a9, pci_dev_list_c0a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc0de, pci_vendor_c0de, pci_dev_list_c0de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc0fe, pci_vendor_c0fe, pci_dev_list_c0fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xca50, pci_vendor_ca50, pci_dev_list_ca50}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xcafe, pci_vendor_cafe, pci_dev_list_cafe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xcccc, pci_vendor_cccc, pci_dev_list_cccc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xccec, pci_vendor_ccec, pci_dev_list_ccec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xcddd, pci_vendor_cddd, pci_dev_list_cddd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd161, pci_vendor_d161, pci_dev_list_d161}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd4d4, pci_vendor_d4d4, pci_dev_list_d4d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd531, pci_vendor_d531, pci_dev_list_d531}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd84d, pci_vendor_d84d, pci_dev_list_d84d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xdead, pci_vendor_dead, pci_dev_list_dead}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xdeaf, pci_vendor_deaf, pci_dev_list_deaf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe000, pci_vendor_e000, pci_dev_list_e000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe159, pci_vendor_e159, pci_dev_list_e159}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe4bf, pci_vendor_e4bf, pci_dev_list_e4bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe55e, pci_vendor_e55e, pci_dev_list_e55e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xea01, pci_vendor_ea01, pci_dev_list_ea01}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xea60, pci_vendor_ea60, pci_dev_list_ea60}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xeabb, pci_vendor_eabb, pci_dev_list_eabb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xeace, pci_vendor_eace, pci_dev_list_eace}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xec80, pci_vendor_ec80, pci_dev_list_ec80}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xecc0, pci_vendor_ecc0, pci_dev_list_ecc0}, +#endif + {0xedd8, pci_vendor_edd8, pci_dev_list_edd8}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xf1d0, pci_vendor_f1d0, pci_dev_list_f1d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfa57, pci_vendor_fa57, pci_dev_list_fa57}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfab7, pci_vendor_fab7, pci_dev_list_fab7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfebd, pci_vendor_febd, pci_dev_list_febd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfeda, pci_vendor_feda, pci_dev_list_feda}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfede, pci_vendor_fede, pci_dev_list_fede}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfffd, pci_vendor_fffd, pci_dev_list_fffd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfffe, pci_vendor_fffe, pci_dev_list_fffe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xffff, pci_vendor_ffff, pci_dev_list_ffff}, +#endif + {0x0000, NULL, NULL} +}; + +#if defined(INIT_VENDOR_SUBSYS_INFO) && defined(INIT_SUBSYS_INFO) +static const pciVendorSubsysInfo pciVendorSubsysInfoList[] = { +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0000, pci_vendor_0000, pci_ss_list_0000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x001a, pci_vendor_001a, pci_ss_list_001a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0033, pci_vendor_0033, pci_ss_list_0033}, +#endif + {0x003d, pci_vendor_003d, pci_ss_list_003d}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0059, pci_vendor_0059, pci_ss_list_0059}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0070, pci_vendor_0070, pci_ss_list_0070}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0071, pci_vendor_0071, pci_ss_list_0071}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0095, pci_vendor_0095, pci_ss_list_0095}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x00a7, pci_vendor_00a7, pci_ss_list_00a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x00f5, pci_vendor_00f5, pci_ss_list_00f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0100, pci_vendor_0100, pci_ss_list_0100}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0123, pci_vendor_0123, pci_ss_list_0123}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x018a, pci_vendor_018a, pci_ss_list_018a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x021b, pci_vendor_021b, pci_ss_list_021b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0270, pci_vendor_0270, pci_ss_list_0270}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0291, pci_vendor_0291, pci_ss_list_0291}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x02ac, pci_vendor_02ac, pci_ss_list_02ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0315, pci_vendor_0315, pci_ss_list_0315}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0357, pci_vendor_0357, pci_ss_list_0357}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0432, pci_vendor_0432, pci_ss_list_0432}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x045e, pci_vendor_045e, pci_ss_list_045e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0482, pci_vendor_0482, pci_ss_list_0482}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x04cf, pci_vendor_04cf, pci_ss_list_04cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x050d, pci_vendor_050d, pci_ss_list_050d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x05a9, pci_vendor_05a9, pci_ss_list_05a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x05e3, pci_vendor_05e3, pci_ss_list_05e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x066f, pci_vendor_066f, pci_ss_list_066f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0675, pci_vendor_0675, pci_ss_list_0675}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x067b, pci_vendor_067b, pci_ss_list_067b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0721, pci_vendor_0721, pci_ss_list_0721}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x07e2, pci_vendor_07e2, pci_ss_list_07e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0925, pci_vendor_0925, pci_ss_list_0925}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x093a, pci_vendor_093a, pci_ss_list_093a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x09c1, pci_vendor_09c1, pci_ss_list_09c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0a89, pci_vendor_0a89, pci_ss_list_0a89}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0b0b, pci_vendor_0b0b, pci_ss_list_0b0b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0b49, pci_vendor_0b49, pci_ss_list_0b49}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0ccd, pci_vendor_0ccd, pci_ss_list_0ccd}, +#endif + {0x0e11, pci_vendor_0e11, pci_ss_list_0e11}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0e21, pci_vendor_0e21, pci_ss_list_0e21}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0e55, pci_vendor_0e55, pci_ss_list_0e55}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x0eac, pci_vendor_0eac, pci_ss_list_0eac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1000, pci_vendor_1000, pci_ss_list_1000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1001, pci_vendor_1001, pci_ss_list_1001}, +#endif + {0x1002, pci_vendor_1002, pci_ss_list_1002}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1003, pci_vendor_1003, pci_ss_list_1003}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1004, pci_vendor_1004, pci_ss_list_1004}, +#endif + {0x1005, pci_vendor_1005, pci_ss_list_1005}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1006, pci_vendor_1006, pci_ss_list_1006}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1007, pci_vendor_1007, pci_ss_list_1007}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1008, pci_vendor_1008, pci_ss_list_1008}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x100a, pci_vendor_100a, pci_ss_list_100a}, +#endif + {0x100b, pci_vendor_100b, pci_ss_list_100b}, + {0x100c, pci_vendor_100c, pci_ss_list_100c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x100d, pci_vendor_100d, pci_ss_list_100d}, +#endif + {0x100e, pci_vendor_100e, pci_ss_list_100e}, + {0x1010, pci_vendor_1010, pci_ss_list_1010}, + {0x1011, pci_vendor_1011, pci_ss_list_1011}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1012, pci_vendor_1012, pci_ss_list_1012}, +#endif + {0x1013, pci_vendor_1013, pci_ss_list_1013}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1014, pci_vendor_1014, pci_ss_list_1014}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1015, pci_vendor_1015, pci_ss_list_1015}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1016, pci_vendor_1016, pci_ss_list_1016}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1017, pci_vendor_1017, pci_ss_list_1017}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1018, pci_vendor_1018, pci_ss_list_1018}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1019, pci_vendor_1019, pci_ss_list_1019}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101a, pci_vendor_101a, pci_ss_list_101a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101b, pci_vendor_101b, pci_ss_list_101b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101c, pci_vendor_101c, pci_ss_list_101c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101e, pci_vendor_101e, pci_ss_list_101e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x101f, pci_vendor_101f, pci_ss_list_101f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1020, pci_vendor_1020, pci_ss_list_1020}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1021, pci_vendor_1021, pci_ss_list_1021}, +#endif + {0x1022, pci_vendor_1022, pci_ss_list_1022}, + {0x1023, pci_vendor_1023, pci_ss_list_1023}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1024, pci_vendor_1024, pci_ss_list_1024}, +#endif + {0x1025, pci_vendor_1025, pci_ss_list_1025}, + {0x1028, pci_vendor_1028, pci_ss_list_1028}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1029, pci_vendor_1029, pci_ss_list_1029}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102a, pci_vendor_102a, pci_ss_list_102a}, +#endif + {0x102b, pci_vendor_102b, pci_ss_list_102b}, + {0x102c, pci_vendor_102c, pci_ss_list_102c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102d, pci_vendor_102d, pci_ss_list_102d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102e, pci_vendor_102e, pci_ss_list_102e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x102f, pci_vendor_102f, pci_ss_list_102f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1030, pci_vendor_1030, pci_ss_list_1030}, +#endif + {0x1031, pci_vendor_1031, pci_ss_list_1031}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1032, pci_vendor_1032, pci_ss_list_1032}, +#endif + {0x1033, pci_vendor_1033, pci_ss_list_1033}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1034, pci_vendor_1034, pci_ss_list_1034}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1035, pci_vendor_1035, pci_ss_list_1035}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1036, pci_vendor_1036, pci_ss_list_1036}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1037, pci_vendor_1037, pci_ss_list_1037}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1038, pci_vendor_1038, pci_ss_list_1038}, +#endif + {0x1039, pci_vendor_1039, pci_ss_list_1039}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103a, pci_vendor_103a, pci_ss_list_103a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103b, pci_vendor_103b, pci_ss_list_103b}, +#endif + {0x103c, pci_vendor_103c, pci_ss_list_103c}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103e, pci_vendor_103e, pci_ss_list_103e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x103f, pci_vendor_103f, pci_ss_list_103f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1040, pci_vendor_1040, pci_ss_list_1040}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1041, pci_vendor_1041, pci_ss_list_1041}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1042, pci_vendor_1042, pci_ss_list_1042}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1043, pci_vendor_1043, pci_ss_list_1043}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1044, pci_vendor_1044, pci_ss_list_1044}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1045, pci_vendor_1045, pci_ss_list_1045}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1046, pci_vendor_1046, pci_ss_list_1046}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1047, pci_vendor_1047, pci_ss_list_1047}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1048, pci_vendor_1048, pci_ss_list_1048}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1049, pci_vendor_1049, pci_ss_list_1049}, +#endif + {0x104a, pci_vendor_104a, pci_ss_list_104a}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x104b, pci_vendor_104b, pci_ss_list_104b}, +#endif + {0x104c, pci_vendor_104c, pci_ss_list_104c}, + {0x104d, pci_vendor_104d, pci_ss_list_104d}, + {0x104e, pci_vendor_104e, pci_ss_list_104e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x104f, pci_vendor_104f, pci_ss_list_104f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1050, pci_vendor_1050, pci_ss_list_1050}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1051, pci_vendor_1051, pci_ss_list_1051}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1052, pci_vendor_1052, pci_ss_list_1052}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1053, pci_vendor_1053, pci_ss_list_1053}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1054, pci_vendor_1054, pci_ss_list_1054}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1055, pci_vendor_1055, pci_ss_list_1055}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1056, pci_vendor_1056, pci_ss_list_1056}, +#endif + {0x1057, pci_vendor_1057, pci_ss_list_1057}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1058, pci_vendor_1058, pci_ss_list_1058}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1059, pci_vendor_1059, pci_ss_list_1059}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105a, pci_vendor_105a, pci_ss_list_105a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105b, pci_vendor_105b, pci_ss_list_105b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105c, pci_vendor_105c, pci_ss_list_105c}, +#endif + {0x105d, pci_vendor_105d, pci_ss_list_105d}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105e, pci_vendor_105e, pci_ss_list_105e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x105f, pci_vendor_105f, pci_ss_list_105f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1060, pci_vendor_1060, pci_ss_list_1060}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1061, pci_vendor_1061, pci_ss_list_1061}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1062, pci_vendor_1062, pci_ss_list_1062}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1063, pci_vendor_1063, pci_ss_list_1063}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1064, pci_vendor_1064, pci_ss_list_1064}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1065, pci_vendor_1065, pci_ss_list_1065}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1066, pci_vendor_1066, pci_ss_list_1066}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1067, pci_vendor_1067, pci_ss_list_1067}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1068, pci_vendor_1068, pci_ss_list_1068}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1069, pci_vendor_1069, pci_ss_list_1069}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106a, pci_vendor_106a, pci_ss_list_106a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106b, pci_vendor_106b, pci_ss_list_106b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106c, pci_vendor_106c, pci_ss_list_106c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106d, pci_vendor_106d, pci_ss_list_106d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106e, pci_vendor_106e, pci_ss_list_106e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x106f, pci_vendor_106f, pci_ss_list_106f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1070, pci_vendor_1070, pci_ss_list_1070}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1071, pci_vendor_1071, pci_ss_list_1071}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1072, pci_vendor_1072, pci_ss_list_1072}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1073, pci_vendor_1073, pci_ss_list_1073}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1074, pci_vendor_1074, pci_ss_list_1074}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1075, pci_vendor_1075, pci_ss_list_1075}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1076, pci_vendor_1076, pci_ss_list_1076}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1077, pci_vendor_1077, pci_ss_list_1077}, +#endif + {0x1078, pci_vendor_1078, pci_ss_list_1078}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1079, pci_vendor_1079, pci_ss_list_1079}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107a, pci_vendor_107a, pci_ss_list_107a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107b, pci_vendor_107b, pci_ss_list_107b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107c, pci_vendor_107c, pci_ss_list_107c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107d, pci_vendor_107d, pci_ss_list_107d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107e, pci_vendor_107e, pci_ss_list_107e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x107f, pci_vendor_107f, pci_ss_list_107f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1080, pci_vendor_1080, pci_ss_list_1080}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1081, pci_vendor_1081, pci_ss_list_1081}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1082, pci_vendor_1082, pci_ss_list_1082}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1083, pci_vendor_1083, pci_ss_list_1083}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1084, pci_vendor_1084, pci_ss_list_1084}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1085, pci_vendor_1085, pci_ss_list_1085}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1086, pci_vendor_1086, pci_ss_list_1086}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1087, pci_vendor_1087, pci_ss_list_1087}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1088, pci_vendor_1088, pci_ss_list_1088}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1089, pci_vendor_1089, pci_ss_list_1089}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108a, pci_vendor_108a, pci_ss_list_108a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108c, pci_vendor_108c, pci_ss_list_108c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108d, pci_vendor_108d, pci_ss_list_108d}, +#endif + {0x108e, pci_vendor_108e, pci_ss_list_108e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x108f, pci_vendor_108f, pci_ss_list_108f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1090, pci_vendor_1090, pci_ss_list_1090}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1091, pci_vendor_1091, pci_ss_list_1091}, +#endif + {0x1092, pci_vendor_1092, pci_ss_list_1092}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1093, pci_vendor_1093, pci_ss_list_1093}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1094, pci_vendor_1094, pci_ss_list_1094}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1095, pci_vendor_1095, pci_ss_list_1095}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1096, pci_vendor_1096, pci_ss_list_1096}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1097, pci_vendor_1097, pci_ss_list_1097}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1098, pci_vendor_1098, pci_ss_list_1098}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1099, pci_vendor_1099, pci_ss_list_1099}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109a, pci_vendor_109a, pci_ss_list_109a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109b, pci_vendor_109b, pci_ss_list_109b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109c, pci_vendor_109c, pci_ss_list_109c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109d, pci_vendor_109d, pci_ss_list_109d}, +#endif + {0x109e, pci_vendor_109e, pci_ss_list_109e}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x109f, pci_vendor_109f, pci_ss_list_109f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a0, pci_vendor_10a0, pci_ss_list_10a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a1, pci_vendor_10a1, pci_ss_list_10a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a2, pci_vendor_10a2, pci_ss_list_10a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a3, pci_vendor_10a3, pci_ss_list_10a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a4, pci_vendor_10a4, pci_ss_list_10a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a5, pci_vendor_10a5, pci_ss_list_10a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a6, pci_vendor_10a6, pci_ss_list_10a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a7, pci_vendor_10a7, pci_ss_list_10a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a8, pci_vendor_10a8, pci_ss_list_10a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10a9, pci_vendor_10a9, pci_ss_list_10a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10aa, pci_vendor_10aa, pci_ss_list_10aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ab, pci_vendor_10ab, pci_ss_list_10ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ac, pci_vendor_10ac, pci_ss_list_10ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ad, pci_vendor_10ad, pci_ss_list_10ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ae, pci_vendor_10ae, pci_ss_list_10ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10af, pci_vendor_10af, pci_ss_list_10af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b0, pci_vendor_10b0, pci_ss_list_10b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b1, pci_vendor_10b1, pci_ss_list_10b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b2, pci_vendor_10b2, pci_ss_list_10b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b3, pci_vendor_10b3, pci_ss_list_10b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b4, pci_vendor_10b4, pci_ss_list_10b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b5, pci_vendor_10b5, pci_ss_list_10b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b6, pci_vendor_10b6, pci_ss_list_10b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b7, pci_vendor_10b7, pci_ss_list_10b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b8, pci_vendor_10b8, pci_ss_list_10b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10b9, pci_vendor_10b9, pci_ss_list_10b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ba, pci_vendor_10ba, pci_ss_list_10ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bb, pci_vendor_10bb, pci_ss_list_10bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bc, pci_vendor_10bc, pci_ss_list_10bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bd, pci_vendor_10bd, pci_ss_list_10bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10be, pci_vendor_10be, pci_ss_list_10be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10bf, pci_vendor_10bf, pci_ss_list_10bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c0, pci_vendor_10c0, pci_ss_list_10c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c1, pci_vendor_10c1, pci_ss_list_10c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c2, pci_vendor_10c2, pci_ss_list_10c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c3, pci_vendor_10c3, pci_ss_list_10c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c4, pci_vendor_10c4, pci_ss_list_10c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c5, pci_vendor_10c5, pci_ss_list_10c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c6, pci_vendor_10c6, pci_ss_list_10c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c7, pci_vendor_10c7, pci_ss_list_10c7}, +#endif + {0x10c8, pci_vendor_10c8, pci_ss_list_10c8}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10c9, pci_vendor_10c9, pci_ss_list_10c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ca, pci_vendor_10ca, pci_ss_list_10ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cb, pci_vendor_10cb, pci_ss_list_10cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cc, pci_vendor_10cc, pci_ss_list_10cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cd, pci_vendor_10cd, pci_ss_list_10cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ce, pci_vendor_10ce, pci_ss_list_10ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10cf, pci_vendor_10cf, pci_ss_list_10cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d1, pci_vendor_10d1, pci_ss_list_10d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d2, pci_vendor_10d2, pci_ss_list_10d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d3, pci_vendor_10d3, pci_ss_list_10d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d4, pci_vendor_10d4, pci_ss_list_10d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d5, pci_vendor_10d5, pci_ss_list_10d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d6, pci_vendor_10d6, pci_ss_list_10d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d7, pci_vendor_10d7, pci_ss_list_10d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d8, pci_vendor_10d8, pci_ss_list_10d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10d9, pci_vendor_10d9, pci_ss_list_10d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10da, pci_vendor_10da, pci_ss_list_10da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10db, pci_vendor_10db, pci_ss_list_10db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10dc, pci_vendor_10dc, pci_ss_list_10dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10dd, pci_vendor_10dd, pci_ss_list_10dd}, +#endif + {0x10de, pci_vendor_10de, pci_ss_list_10de}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10df, pci_vendor_10df, pci_ss_list_10df}, +#endif + {0x10e0, pci_vendor_10e0, pci_ss_list_10e0}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e1, pci_vendor_10e1, pci_ss_list_10e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e2, pci_vendor_10e2, pci_ss_list_10e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e3, pci_vendor_10e3, pci_ss_list_10e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e4, pci_vendor_10e4, pci_ss_list_10e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e5, pci_vendor_10e5, pci_ss_list_10e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e6, pci_vendor_10e6, pci_ss_list_10e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e7, pci_vendor_10e7, pci_ss_list_10e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e8, pci_vendor_10e8, pci_ss_list_10e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10e9, pci_vendor_10e9, pci_ss_list_10e9}, +#endif + {0x10ea, pci_vendor_10ea, pci_ss_list_10ea}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10eb, pci_vendor_10eb, pci_ss_list_10eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ec, pci_vendor_10ec, pci_ss_list_10ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ed, pci_vendor_10ed, pci_ss_list_10ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ee, pci_vendor_10ee, pci_ss_list_10ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ef, pci_vendor_10ef, pci_ss_list_10ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f0, pci_vendor_10f0, pci_ss_list_10f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f1, pci_vendor_10f1, pci_ss_list_10f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f2, pci_vendor_10f2, pci_ss_list_10f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f3, pci_vendor_10f3, pci_ss_list_10f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f4, pci_vendor_10f4, pci_ss_list_10f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f5, pci_vendor_10f5, pci_ss_list_10f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f6, pci_vendor_10f6, pci_ss_list_10f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f7, pci_vendor_10f7, pci_ss_list_10f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f8, pci_vendor_10f8, pci_ss_list_10f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10f9, pci_vendor_10f9, pci_ss_list_10f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fa, pci_vendor_10fa, pci_ss_list_10fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fb, pci_vendor_10fb, pci_ss_list_10fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fc, pci_vendor_10fc, pci_ss_list_10fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fd, pci_vendor_10fd, pci_ss_list_10fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10fe, pci_vendor_10fe, pci_ss_list_10fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x10ff, pci_vendor_10ff, pci_ss_list_10ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1100, pci_vendor_1100, pci_ss_list_1100}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1101, pci_vendor_1101, pci_ss_list_1101}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1102, pci_vendor_1102, pci_ss_list_1102}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1103, pci_vendor_1103, pci_ss_list_1103}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1104, pci_vendor_1104, pci_ss_list_1104}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1105, pci_vendor_1105, pci_ss_list_1105}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1106, pci_vendor_1106, pci_ss_list_1106}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1107, pci_vendor_1107, pci_ss_list_1107}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1108, pci_vendor_1108, pci_ss_list_1108}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1109, pci_vendor_1109, pci_ss_list_1109}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110a, pci_vendor_110a, pci_ss_list_110a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110b, pci_vendor_110b, pci_ss_list_110b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110c, pci_vendor_110c, pci_ss_list_110c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110d, pci_vendor_110d, pci_ss_list_110d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110e, pci_vendor_110e, pci_ss_list_110e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x110f, pci_vendor_110f, pci_ss_list_110f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1110, pci_vendor_1110, pci_ss_list_1110}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1111, pci_vendor_1111, pci_ss_list_1111}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1112, pci_vendor_1112, pci_ss_list_1112}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1113, pci_vendor_1113, pci_ss_list_1113}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1114, pci_vendor_1114, pci_ss_list_1114}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1115, pci_vendor_1115, pci_ss_list_1115}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1116, pci_vendor_1116, pci_ss_list_1116}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1117, pci_vendor_1117, pci_ss_list_1117}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1118, pci_vendor_1118, pci_ss_list_1118}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1119, pci_vendor_1119, pci_ss_list_1119}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111a, pci_vendor_111a, pci_ss_list_111a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111b, pci_vendor_111b, pci_ss_list_111b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111c, pci_vendor_111c, pci_ss_list_111c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111d, pci_vendor_111d, pci_ss_list_111d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111e, pci_vendor_111e, pci_ss_list_111e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x111f, pci_vendor_111f, pci_ss_list_111f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1120, pci_vendor_1120, pci_ss_list_1120}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1121, pci_vendor_1121, pci_ss_list_1121}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1122, pci_vendor_1122, pci_ss_list_1122}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1123, pci_vendor_1123, pci_ss_list_1123}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1124, pci_vendor_1124, pci_ss_list_1124}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1125, pci_vendor_1125, pci_ss_list_1125}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1126, pci_vendor_1126, pci_ss_list_1126}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1127, pci_vendor_1127, pci_ss_list_1127}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1129, pci_vendor_1129, pci_ss_list_1129}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112a, pci_vendor_112a, pci_ss_list_112a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112b, pci_vendor_112b, pci_ss_list_112b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112c, pci_vendor_112c, pci_ss_list_112c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112d, pci_vendor_112d, pci_ss_list_112d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112e, pci_vendor_112e, pci_ss_list_112e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x112f, pci_vendor_112f, pci_ss_list_112f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1130, pci_vendor_1130, pci_ss_list_1130}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1131, pci_vendor_1131, pci_ss_list_1131}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1132, pci_vendor_1132, pci_ss_list_1132}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1133, pci_vendor_1133, pci_ss_list_1133}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1134, pci_vendor_1134, pci_ss_list_1134}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1135, pci_vendor_1135, pci_ss_list_1135}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1136, pci_vendor_1136, pci_ss_list_1136}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1137, pci_vendor_1137, pci_ss_list_1137}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1138, pci_vendor_1138, pci_ss_list_1138}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1139, pci_vendor_1139, pci_ss_list_1139}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113a, pci_vendor_113a, pci_ss_list_113a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113b, pci_vendor_113b, pci_ss_list_113b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113c, pci_vendor_113c, pci_ss_list_113c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113d, pci_vendor_113d, pci_ss_list_113d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113e, pci_vendor_113e, pci_ss_list_113e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x113f, pci_vendor_113f, pci_ss_list_113f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1140, pci_vendor_1140, pci_ss_list_1140}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1141, pci_vendor_1141, pci_ss_list_1141}, +#endif + {0x1142, pci_vendor_1142, pci_ss_list_1142}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1143, pci_vendor_1143, pci_ss_list_1143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1144, pci_vendor_1144, pci_ss_list_1144}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1145, pci_vendor_1145, pci_ss_list_1145}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1146, pci_vendor_1146, pci_ss_list_1146}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1147, pci_vendor_1147, pci_ss_list_1147}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1148, pci_vendor_1148, pci_ss_list_1148}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1149, pci_vendor_1149, pci_ss_list_1149}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114a, pci_vendor_114a, pci_ss_list_114a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114b, pci_vendor_114b, pci_ss_list_114b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114c, pci_vendor_114c, pci_ss_list_114c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114d, pci_vendor_114d, pci_ss_list_114d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114e, pci_vendor_114e, pci_ss_list_114e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x114f, pci_vendor_114f, pci_ss_list_114f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1150, pci_vendor_1150, pci_ss_list_1150}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1151, pci_vendor_1151, pci_ss_list_1151}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1152, pci_vendor_1152, pci_ss_list_1152}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1153, pci_vendor_1153, pci_ss_list_1153}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1154, pci_vendor_1154, pci_ss_list_1154}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1155, pci_vendor_1155, pci_ss_list_1155}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1156, pci_vendor_1156, pci_ss_list_1156}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1157, pci_vendor_1157, pci_ss_list_1157}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1158, pci_vendor_1158, pci_ss_list_1158}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1159, pci_vendor_1159, pci_ss_list_1159}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115a, pci_vendor_115a, pci_ss_list_115a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115b, pci_vendor_115b, pci_ss_list_115b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115c, pci_vendor_115c, pci_ss_list_115c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115d, pci_vendor_115d, pci_ss_list_115d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115e, pci_vendor_115e, pci_ss_list_115e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x115f, pci_vendor_115f, pci_ss_list_115f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1160, pci_vendor_1160, pci_ss_list_1160}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1161, pci_vendor_1161, pci_ss_list_1161}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1162, pci_vendor_1162, pci_ss_list_1162}, +#endif + {0x1163, pci_vendor_1163, pci_ss_list_1163}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1164, pci_vendor_1164, pci_ss_list_1164}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1165, pci_vendor_1165, pci_ss_list_1165}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1166, pci_vendor_1166, pci_ss_list_1166}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1167, pci_vendor_1167, pci_ss_list_1167}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1168, pci_vendor_1168, pci_ss_list_1168}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1169, pci_vendor_1169, pci_ss_list_1169}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116a, pci_vendor_116a, pci_ss_list_116a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116b, pci_vendor_116b, pci_ss_list_116b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116c, pci_vendor_116c, pci_ss_list_116c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116d, pci_vendor_116d, pci_ss_list_116d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116e, pci_vendor_116e, pci_ss_list_116e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x116f, pci_vendor_116f, pci_ss_list_116f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1170, pci_vendor_1170, pci_ss_list_1170}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1171, pci_vendor_1171, pci_ss_list_1171}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1172, pci_vendor_1172, pci_ss_list_1172}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1173, pci_vendor_1173, pci_ss_list_1173}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1174, pci_vendor_1174, pci_ss_list_1174}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1175, pci_vendor_1175, pci_ss_list_1175}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1176, pci_vendor_1176, pci_ss_list_1176}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1177, pci_vendor_1177, pci_ss_list_1177}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1178, pci_vendor_1178, pci_ss_list_1178}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1179, pci_vendor_1179, pci_ss_list_1179}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117a, pci_vendor_117a, pci_ss_list_117a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117b, pci_vendor_117b, pci_ss_list_117b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117c, pci_vendor_117c, pci_ss_list_117c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117d, pci_vendor_117d, pci_ss_list_117d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117e, pci_vendor_117e, pci_ss_list_117e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x117f, pci_vendor_117f, pci_ss_list_117f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1180, pci_vendor_1180, pci_ss_list_1180}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1181, pci_vendor_1181, pci_ss_list_1181}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1183, pci_vendor_1183, pci_ss_list_1183}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1184, pci_vendor_1184, pci_ss_list_1184}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1185, pci_vendor_1185, pci_ss_list_1185}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1186, pci_vendor_1186, pci_ss_list_1186}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1187, pci_vendor_1187, pci_ss_list_1187}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1188, pci_vendor_1188, pci_ss_list_1188}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1189, pci_vendor_1189, pci_ss_list_1189}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118a, pci_vendor_118a, pci_ss_list_118a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118b, pci_vendor_118b, pci_ss_list_118b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118c, pci_vendor_118c, pci_ss_list_118c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118d, pci_vendor_118d, pci_ss_list_118d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118e, pci_vendor_118e, pci_ss_list_118e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x118f, pci_vendor_118f, pci_ss_list_118f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1190, pci_vendor_1190, pci_ss_list_1190}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1191, pci_vendor_1191, pci_ss_list_1191}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1192, pci_vendor_1192, pci_ss_list_1192}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1193, pci_vendor_1193, pci_ss_list_1193}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1194, pci_vendor_1194, pci_ss_list_1194}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1195, pci_vendor_1195, pci_ss_list_1195}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1196, pci_vendor_1196, pci_ss_list_1196}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1197, pci_vendor_1197, pci_ss_list_1197}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1198, pci_vendor_1198, pci_ss_list_1198}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1199, pci_vendor_1199, pci_ss_list_1199}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119a, pci_vendor_119a, pci_ss_list_119a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119b, pci_vendor_119b, pci_ss_list_119b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119c, pci_vendor_119c, pci_ss_list_119c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119d, pci_vendor_119d, pci_ss_list_119d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119e, pci_vendor_119e, pci_ss_list_119e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x119f, pci_vendor_119f, pci_ss_list_119f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a0, pci_vendor_11a0, pci_ss_list_11a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a1, pci_vendor_11a1, pci_ss_list_11a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a2, pci_vendor_11a2, pci_ss_list_11a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a3, pci_vendor_11a3, pci_ss_list_11a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a4, pci_vendor_11a4, pci_ss_list_11a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a5, pci_vendor_11a5, pci_ss_list_11a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a6, pci_vendor_11a6, pci_ss_list_11a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a7, pci_vendor_11a7, pci_ss_list_11a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a8, pci_vendor_11a8, pci_ss_list_11a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11a9, pci_vendor_11a9, pci_ss_list_11a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11aa, pci_vendor_11aa, pci_ss_list_11aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ab, pci_vendor_11ab, pci_ss_list_11ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ac, pci_vendor_11ac, pci_ss_list_11ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ad, pci_vendor_11ad, pci_ss_list_11ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ae, pci_vendor_11ae, pci_ss_list_11ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11af, pci_vendor_11af, pci_ss_list_11af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b0, pci_vendor_11b0, pci_ss_list_11b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b1, pci_vendor_11b1, pci_ss_list_11b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b2, pci_vendor_11b2, pci_ss_list_11b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b3, pci_vendor_11b3, pci_ss_list_11b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b4, pci_vendor_11b4, pci_ss_list_11b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b5, pci_vendor_11b5, pci_ss_list_11b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b6, pci_vendor_11b6, pci_ss_list_11b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b7, pci_vendor_11b7, pci_ss_list_11b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b8, pci_vendor_11b8, pci_ss_list_11b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11b9, pci_vendor_11b9, pci_ss_list_11b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ba, pci_vendor_11ba, pci_ss_list_11ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bb, pci_vendor_11bb, pci_ss_list_11bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bc, pci_vendor_11bc, pci_ss_list_11bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bd, pci_vendor_11bd, pci_ss_list_11bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11be, pci_vendor_11be, pci_ss_list_11be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11bf, pci_vendor_11bf, pci_ss_list_11bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c0, pci_vendor_11c0, pci_ss_list_11c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c1, pci_vendor_11c1, pci_ss_list_11c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c2, pci_vendor_11c2, pci_ss_list_11c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c3, pci_vendor_11c3, pci_ss_list_11c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c4, pci_vendor_11c4, pci_ss_list_11c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c5, pci_vendor_11c5, pci_ss_list_11c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c6, pci_vendor_11c6, pci_ss_list_11c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c7, pci_vendor_11c7, pci_ss_list_11c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c8, pci_vendor_11c8, pci_ss_list_11c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11c9, pci_vendor_11c9, pci_ss_list_11c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ca, pci_vendor_11ca, pci_ss_list_11ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cb, pci_vendor_11cb, pci_ss_list_11cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cc, pci_vendor_11cc, pci_ss_list_11cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cd, pci_vendor_11cd, pci_ss_list_11cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ce, pci_vendor_11ce, pci_ss_list_11ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11cf, pci_vendor_11cf, pci_ss_list_11cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d0, pci_vendor_11d0, pci_ss_list_11d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d1, pci_vendor_11d1, pci_ss_list_11d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d2, pci_vendor_11d2, pci_ss_list_11d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d3, pci_vendor_11d3, pci_ss_list_11d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d4, pci_vendor_11d4, pci_ss_list_11d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d5, pci_vendor_11d5, pci_ss_list_11d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d6, pci_vendor_11d6, pci_ss_list_11d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d7, pci_vendor_11d7, pci_ss_list_11d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d8, pci_vendor_11d8, pci_ss_list_11d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11d9, pci_vendor_11d9, pci_ss_list_11d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11da, pci_vendor_11da, pci_ss_list_11da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11db, pci_vendor_11db, pci_ss_list_11db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11dc, pci_vendor_11dc, pci_ss_list_11dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11dd, pci_vendor_11dd, pci_ss_list_11dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11de, pci_vendor_11de, pci_ss_list_11de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11df, pci_vendor_11df, pci_ss_list_11df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e0, pci_vendor_11e0, pci_ss_list_11e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e1, pci_vendor_11e1, pci_ss_list_11e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e2, pci_vendor_11e2, pci_ss_list_11e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e3, pci_vendor_11e3, pci_ss_list_11e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e4, pci_vendor_11e4, pci_ss_list_11e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e5, pci_vendor_11e5, pci_ss_list_11e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e6, pci_vendor_11e6, pci_ss_list_11e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e7, pci_vendor_11e7, pci_ss_list_11e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e8, pci_vendor_11e8, pci_ss_list_11e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11e9, pci_vendor_11e9, pci_ss_list_11e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ea, pci_vendor_11ea, pci_ss_list_11ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11eb, pci_vendor_11eb, pci_ss_list_11eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ec, pci_vendor_11ec, pci_ss_list_11ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ed, pci_vendor_11ed, pci_ss_list_11ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ee, pci_vendor_11ee, pci_ss_list_11ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ef, pci_vendor_11ef, pci_ss_list_11ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f0, pci_vendor_11f0, pci_ss_list_11f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f1, pci_vendor_11f1, pci_ss_list_11f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f2, pci_vendor_11f2, pci_ss_list_11f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f3, pci_vendor_11f3, pci_ss_list_11f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f4, pci_vendor_11f4, pci_ss_list_11f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f5, pci_vendor_11f5, pci_ss_list_11f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f6, pci_vendor_11f6, pci_ss_list_11f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f7, pci_vendor_11f7, pci_ss_list_11f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f8, pci_vendor_11f8, pci_ss_list_11f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11f9, pci_vendor_11f9, pci_ss_list_11f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fa, pci_vendor_11fa, pci_ss_list_11fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fb, pci_vendor_11fb, pci_ss_list_11fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fc, pci_vendor_11fc, pci_ss_list_11fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fd, pci_vendor_11fd, pci_ss_list_11fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11fe, pci_vendor_11fe, pci_ss_list_11fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x11ff, pci_vendor_11ff, pci_ss_list_11ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1200, pci_vendor_1200, pci_ss_list_1200}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1201, pci_vendor_1201, pci_ss_list_1201}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1202, pci_vendor_1202, pci_ss_list_1202}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1203, pci_vendor_1203, pci_ss_list_1203}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1204, pci_vendor_1204, pci_ss_list_1204}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1205, pci_vendor_1205, pci_ss_list_1205}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1206, pci_vendor_1206, pci_ss_list_1206}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1208, pci_vendor_1208, pci_ss_list_1208}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1209, pci_vendor_1209, pci_ss_list_1209}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120a, pci_vendor_120a, pci_ss_list_120a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120b, pci_vendor_120b, pci_ss_list_120b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120c, pci_vendor_120c, pci_ss_list_120c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120d, pci_vendor_120d, pci_ss_list_120d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120e, pci_vendor_120e, pci_ss_list_120e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x120f, pci_vendor_120f, pci_ss_list_120f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1210, pci_vendor_1210, pci_ss_list_1210}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1211, pci_vendor_1211, pci_ss_list_1211}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1212, pci_vendor_1212, pci_ss_list_1212}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1213, pci_vendor_1213, pci_ss_list_1213}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1214, pci_vendor_1214, pci_ss_list_1214}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1215, pci_vendor_1215, pci_ss_list_1215}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1216, pci_vendor_1216, pci_ss_list_1216}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1217, pci_vendor_1217, pci_ss_list_1217}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1218, pci_vendor_1218, pci_ss_list_1218}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1219, pci_vendor_1219, pci_ss_list_1219}, +#endif + {0x121a, pci_vendor_121a, pci_ss_list_121a}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121b, pci_vendor_121b, pci_ss_list_121b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121c, pci_vendor_121c, pci_ss_list_121c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121d, pci_vendor_121d, pci_ss_list_121d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121e, pci_vendor_121e, pci_ss_list_121e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x121f, pci_vendor_121f, pci_ss_list_121f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1220, pci_vendor_1220, pci_ss_list_1220}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1221, pci_vendor_1221, pci_ss_list_1221}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1222, pci_vendor_1222, pci_ss_list_1222}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1223, pci_vendor_1223, pci_ss_list_1223}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1224, pci_vendor_1224, pci_ss_list_1224}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1225, pci_vendor_1225, pci_ss_list_1225}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1227, pci_vendor_1227, pci_ss_list_1227}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1228, pci_vendor_1228, pci_ss_list_1228}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1229, pci_vendor_1229, pci_ss_list_1229}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122a, pci_vendor_122a, pci_ss_list_122a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122b, pci_vendor_122b, pci_ss_list_122b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122c, pci_vendor_122c, pci_ss_list_122c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122d, pci_vendor_122d, pci_ss_list_122d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122e, pci_vendor_122e, pci_ss_list_122e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x122f, pci_vendor_122f, pci_ss_list_122f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1230, pci_vendor_1230, pci_ss_list_1230}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1231, pci_vendor_1231, pci_ss_list_1231}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1232, pci_vendor_1232, pci_ss_list_1232}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1233, pci_vendor_1233, pci_ss_list_1233}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1234, pci_vendor_1234, pci_ss_list_1234}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1235, pci_vendor_1235, pci_ss_list_1235}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1236, pci_vendor_1236, pci_ss_list_1236}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1237, pci_vendor_1237, pci_ss_list_1237}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1238, pci_vendor_1238, pci_ss_list_1238}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1239, pci_vendor_1239, pci_ss_list_1239}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123a, pci_vendor_123a, pci_ss_list_123a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123b, pci_vendor_123b, pci_ss_list_123b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123c, pci_vendor_123c, pci_ss_list_123c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123d, pci_vendor_123d, pci_ss_list_123d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123e, pci_vendor_123e, pci_ss_list_123e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x123f, pci_vendor_123f, pci_ss_list_123f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1240, pci_vendor_1240, pci_ss_list_1240}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1241, pci_vendor_1241, pci_ss_list_1241}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1242, pci_vendor_1242, pci_ss_list_1242}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1243, pci_vendor_1243, pci_ss_list_1243}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1244, pci_vendor_1244, pci_ss_list_1244}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1245, pci_vendor_1245, pci_ss_list_1245}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1246, pci_vendor_1246, pci_ss_list_1246}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1247, pci_vendor_1247, pci_ss_list_1247}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1248, pci_vendor_1248, pci_ss_list_1248}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1249, pci_vendor_1249, pci_ss_list_1249}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124a, pci_vendor_124a, pci_ss_list_124a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124b, pci_vendor_124b, pci_ss_list_124b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124c, pci_vendor_124c, pci_ss_list_124c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124d, pci_vendor_124d, pci_ss_list_124d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124e, pci_vendor_124e, pci_ss_list_124e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x124f, pci_vendor_124f, pci_ss_list_124f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1250, pci_vendor_1250, pci_ss_list_1250}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1251, pci_vendor_1251, pci_ss_list_1251}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1253, pci_vendor_1253, pci_ss_list_1253}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1254, pci_vendor_1254, pci_ss_list_1254}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1255, pci_vendor_1255, pci_ss_list_1255}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1256, pci_vendor_1256, pci_ss_list_1256}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1257, pci_vendor_1257, pci_ss_list_1257}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1258, pci_vendor_1258, pci_ss_list_1258}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1259, pci_vendor_1259, pci_ss_list_1259}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125a, pci_vendor_125a, pci_ss_list_125a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125b, pci_vendor_125b, pci_ss_list_125b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125c, pci_vendor_125c, pci_ss_list_125c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125d, pci_vendor_125d, pci_ss_list_125d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125e, pci_vendor_125e, pci_ss_list_125e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x125f, pci_vendor_125f, pci_ss_list_125f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1260, pci_vendor_1260, pci_ss_list_1260}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1261, pci_vendor_1261, pci_ss_list_1261}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1262, pci_vendor_1262, pci_ss_list_1262}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1263, pci_vendor_1263, pci_ss_list_1263}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1264, pci_vendor_1264, pci_ss_list_1264}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1265, pci_vendor_1265, pci_ss_list_1265}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1266, pci_vendor_1266, pci_ss_list_1266}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1267, pci_vendor_1267, pci_ss_list_1267}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1268, pci_vendor_1268, pci_ss_list_1268}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1269, pci_vendor_1269, pci_ss_list_1269}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126a, pci_vendor_126a, pci_ss_list_126a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126b, pci_vendor_126b, pci_ss_list_126b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126c, pci_vendor_126c, pci_ss_list_126c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126d, pci_vendor_126d, pci_ss_list_126d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x126e, pci_vendor_126e, pci_ss_list_126e}, +#endif + {0x126f, pci_vendor_126f, pci_ss_list_126f}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1270, pci_vendor_1270, pci_ss_list_1270}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1271, pci_vendor_1271, pci_ss_list_1271}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1272, pci_vendor_1272, pci_ss_list_1272}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1273, pci_vendor_1273, pci_ss_list_1273}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1274, pci_vendor_1274, pci_ss_list_1274}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1275, pci_vendor_1275, pci_ss_list_1275}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1276, pci_vendor_1276, pci_ss_list_1276}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1277, pci_vendor_1277, pci_ss_list_1277}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1278, pci_vendor_1278, pci_ss_list_1278}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1279, pci_vendor_1279, pci_ss_list_1279}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127a, pci_vendor_127a, pci_ss_list_127a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127b, pci_vendor_127b, pci_ss_list_127b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127c, pci_vendor_127c, pci_ss_list_127c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127d, pci_vendor_127d, pci_ss_list_127d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127e, pci_vendor_127e, pci_ss_list_127e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x127f, pci_vendor_127f, pci_ss_list_127f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1280, pci_vendor_1280, pci_ss_list_1280}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1281, pci_vendor_1281, pci_ss_list_1281}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1282, pci_vendor_1282, pci_ss_list_1282}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1283, pci_vendor_1283, pci_ss_list_1283}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1284, pci_vendor_1284, pci_ss_list_1284}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1285, pci_vendor_1285, pci_ss_list_1285}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1286, pci_vendor_1286, pci_ss_list_1286}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1287, pci_vendor_1287, pci_ss_list_1287}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1288, pci_vendor_1288, pci_ss_list_1288}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1289, pci_vendor_1289, pci_ss_list_1289}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128a, pci_vendor_128a, pci_ss_list_128a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128b, pci_vendor_128b, pci_ss_list_128b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128c, pci_vendor_128c, pci_ss_list_128c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128d, pci_vendor_128d, pci_ss_list_128d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128e, pci_vendor_128e, pci_ss_list_128e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x128f, pci_vendor_128f, pci_ss_list_128f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1290, pci_vendor_1290, pci_ss_list_1290}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1291, pci_vendor_1291, pci_ss_list_1291}, +#endif + {0x1292, pci_vendor_1292, pci_ss_list_1292}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1293, pci_vendor_1293, pci_ss_list_1293}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1294, pci_vendor_1294, pci_ss_list_1294}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1295, pci_vendor_1295, pci_ss_list_1295}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1296, pci_vendor_1296, pci_ss_list_1296}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1297, pci_vendor_1297, pci_ss_list_1297}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1298, pci_vendor_1298, pci_ss_list_1298}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1299, pci_vendor_1299, pci_ss_list_1299}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129a, pci_vendor_129a, pci_ss_list_129a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129b, pci_vendor_129b, pci_ss_list_129b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129c, pci_vendor_129c, pci_ss_list_129c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129d, pci_vendor_129d, pci_ss_list_129d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129e, pci_vendor_129e, pci_ss_list_129e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x129f, pci_vendor_129f, pci_ss_list_129f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a0, pci_vendor_12a0, pci_ss_list_12a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a1, pci_vendor_12a1, pci_ss_list_12a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a2, pci_vendor_12a2, pci_ss_list_12a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a3, pci_vendor_12a3, pci_ss_list_12a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a4, pci_vendor_12a4, pci_ss_list_12a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a5, pci_vendor_12a5, pci_ss_list_12a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a6, pci_vendor_12a6, pci_ss_list_12a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a7, pci_vendor_12a7, pci_ss_list_12a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a8, pci_vendor_12a8, pci_ss_list_12a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12a9, pci_vendor_12a9, pci_ss_list_12a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12aa, pci_vendor_12aa, pci_ss_list_12aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ab, pci_vendor_12ab, pci_ss_list_12ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ac, pci_vendor_12ac, pci_ss_list_12ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ad, pci_vendor_12ad, pci_ss_list_12ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ae, pci_vendor_12ae, pci_ss_list_12ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12af, pci_vendor_12af, pci_ss_list_12af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b0, pci_vendor_12b0, pci_ss_list_12b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b1, pci_vendor_12b1, pci_ss_list_12b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b2, pci_vendor_12b2, pci_ss_list_12b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b3, pci_vendor_12b3, pci_ss_list_12b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b4, pci_vendor_12b4, pci_ss_list_12b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b5, pci_vendor_12b5, pci_ss_list_12b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b6, pci_vendor_12b6, pci_ss_list_12b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b7, pci_vendor_12b7, pci_ss_list_12b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b8, pci_vendor_12b8, pci_ss_list_12b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12b9, pci_vendor_12b9, pci_ss_list_12b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ba, pci_vendor_12ba, pci_ss_list_12ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bb, pci_vendor_12bb, pci_ss_list_12bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bc, pci_vendor_12bc, pci_ss_list_12bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bd, pci_vendor_12bd, pci_ss_list_12bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12be, pci_vendor_12be, pci_ss_list_12be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12bf, pci_vendor_12bf, pci_ss_list_12bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c0, pci_vendor_12c0, pci_ss_list_12c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c1, pci_vendor_12c1, pci_ss_list_12c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c2, pci_vendor_12c2, pci_ss_list_12c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c3, pci_vendor_12c3, pci_ss_list_12c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c4, pci_vendor_12c4, pci_ss_list_12c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c5, pci_vendor_12c5, pci_ss_list_12c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c6, pci_vendor_12c6, pci_ss_list_12c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c7, pci_vendor_12c7, pci_ss_list_12c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c8, pci_vendor_12c8, pci_ss_list_12c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12c9, pci_vendor_12c9, pci_ss_list_12c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ca, pci_vendor_12ca, pci_ss_list_12ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cb, pci_vendor_12cb, pci_ss_list_12cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cc, pci_vendor_12cc, pci_ss_list_12cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cd, pci_vendor_12cd, pci_ss_list_12cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ce, pci_vendor_12ce, pci_ss_list_12ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12cf, pci_vendor_12cf, pci_ss_list_12cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d0, pci_vendor_12d0, pci_ss_list_12d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d1, pci_vendor_12d1, pci_ss_list_12d1}, +#endif + {0x12d2, pci_vendor_12d2, pci_ss_list_12d2}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d3, pci_vendor_12d3, pci_ss_list_12d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d4, pci_vendor_12d4, pci_ss_list_12d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d5, pci_vendor_12d5, pci_ss_list_12d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d6, pci_vendor_12d6, pci_ss_list_12d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d7, pci_vendor_12d7, pci_ss_list_12d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d8, pci_vendor_12d8, pci_ss_list_12d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12d9, pci_vendor_12d9, pci_ss_list_12d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12da, pci_vendor_12da, pci_ss_list_12da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12db, pci_vendor_12db, pci_ss_list_12db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12dc, pci_vendor_12dc, pci_ss_list_12dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12dd, pci_vendor_12dd, pci_ss_list_12dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12de, pci_vendor_12de, pci_ss_list_12de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12df, pci_vendor_12df, pci_ss_list_12df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e0, pci_vendor_12e0, pci_ss_list_12e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e1, pci_vendor_12e1, pci_ss_list_12e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e2, pci_vendor_12e2, pci_ss_list_12e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e3, pci_vendor_12e3, pci_ss_list_12e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e4, pci_vendor_12e4, pci_ss_list_12e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e5, pci_vendor_12e5, pci_ss_list_12e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e6, pci_vendor_12e6, pci_ss_list_12e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e7, pci_vendor_12e7, pci_ss_list_12e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e8, pci_vendor_12e8, pci_ss_list_12e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12e9, pci_vendor_12e9, pci_ss_list_12e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ea, pci_vendor_12ea, pci_ss_list_12ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12eb, pci_vendor_12eb, pci_ss_list_12eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ec, pci_vendor_12ec, pci_ss_list_12ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ed, pci_vendor_12ed, pci_ss_list_12ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ee, pci_vendor_12ee, pci_ss_list_12ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ef, pci_vendor_12ef, pci_ss_list_12ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f0, pci_vendor_12f0, pci_ss_list_12f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f1, pci_vendor_12f1, pci_ss_list_12f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f2, pci_vendor_12f2, pci_ss_list_12f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f3, pci_vendor_12f3, pci_ss_list_12f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f4, pci_vendor_12f4, pci_ss_list_12f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f5, pci_vendor_12f5, pci_ss_list_12f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f6, pci_vendor_12f6, pci_ss_list_12f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f7, pci_vendor_12f7, pci_ss_list_12f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f8, pci_vendor_12f8, pci_ss_list_12f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12f9, pci_vendor_12f9, pci_ss_list_12f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fb, pci_vendor_12fb, pci_ss_list_12fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fc, pci_vendor_12fc, pci_ss_list_12fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fd, pci_vendor_12fd, pci_ss_list_12fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12fe, pci_vendor_12fe, pci_ss_list_12fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x12ff, pci_vendor_12ff, pci_ss_list_12ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1300, pci_vendor_1300, pci_ss_list_1300}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1302, pci_vendor_1302, pci_ss_list_1302}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1303, pci_vendor_1303, pci_ss_list_1303}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1304, pci_vendor_1304, pci_ss_list_1304}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1305, pci_vendor_1305, pci_ss_list_1305}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1306, pci_vendor_1306, pci_ss_list_1306}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1307, pci_vendor_1307, pci_ss_list_1307}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1308, pci_vendor_1308, pci_ss_list_1308}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1309, pci_vendor_1309, pci_ss_list_1309}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130a, pci_vendor_130a, pci_ss_list_130a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130b, pci_vendor_130b, pci_ss_list_130b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130c, pci_vendor_130c, pci_ss_list_130c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130d, pci_vendor_130d, pci_ss_list_130d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130e, pci_vendor_130e, pci_ss_list_130e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x130f, pci_vendor_130f, pci_ss_list_130f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1310, pci_vendor_1310, pci_ss_list_1310}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1311, pci_vendor_1311, pci_ss_list_1311}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1312, pci_vendor_1312, pci_ss_list_1312}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1313, pci_vendor_1313, pci_ss_list_1313}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1316, pci_vendor_1316, pci_ss_list_1316}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1317, pci_vendor_1317, pci_ss_list_1317}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1318, pci_vendor_1318, pci_ss_list_1318}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1319, pci_vendor_1319, pci_ss_list_1319}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131a, pci_vendor_131a, pci_ss_list_131a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131c, pci_vendor_131c, pci_ss_list_131c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131d, pci_vendor_131d, pci_ss_list_131d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131e, pci_vendor_131e, pci_ss_list_131e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x131f, pci_vendor_131f, pci_ss_list_131f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1320, pci_vendor_1320, pci_ss_list_1320}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1321, pci_vendor_1321, pci_ss_list_1321}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1322, pci_vendor_1322, pci_ss_list_1322}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1323, pci_vendor_1323, pci_ss_list_1323}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1324, pci_vendor_1324, pci_ss_list_1324}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1325, pci_vendor_1325, pci_ss_list_1325}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1326, pci_vendor_1326, pci_ss_list_1326}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1327, pci_vendor_1327, pci_ss_list_1327}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1328, pci_vendor_1328, pci_ss_list_1328}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1329, pci_vendor_1329, pci_ss_list_1329}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132a, pci_vendor_132a, pci_ss_list_132a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132b, pci_vendor_132b, pci_ss_list_132b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132c, pci_vendor_132c, pci_ss_list_132c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x132d, pci_vendor_132d, pci_ss_list_132d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1330, pci_vendor_1330, pci_ss_list_1330}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1331, pci_vendor_1331, pci_ss_list_1331}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1332, pci_vendor_1332, pci_ss_list_1332}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1334, pci_vendor_1334, pci_ss_list_1334}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1335, pci_vendor_1335, pci_ss_list_1335}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1337, pci_vendor_1337, pci_ss_list_1337}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1338, pci_vendor_1338, pci_ss_list_1338}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133a, pci_vendor_133a, pci_ss_list_133a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133b, pci_vendor_133b, pci_ss_list_133b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133c, pci_vendor_133c, pci_ss_list_133c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133d, pci_vendor_133d, pci_ss_list_133d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133e, pci_vendor_133e, pci_ss_list_133e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x133f, pci_vendor_133f, pci_ss_list_133f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1340, pci_vendor_1340, pci_ss_list_1340}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1341, pci_vendor_1341, pci_ss_list_1341}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1342, pci_vendor_1342, pci_ss_list_1342}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1343, pci_vendor_1343, pci_ss_list_1343}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1344, pci_vendor_1344, pci_ss_list_1344}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1345, pci_vendor_1345, pci_ss_list_1345}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1347, pci_vendor_1347, pci_ss_list_1347}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1349, pci_vendor_1349, pci_ss_list_1349}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134a, pci_vendor_134a, pci_ss_list_134a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134b, pci_vendor_134b, pci_ss_list_134b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134c, pci_vendor_134c, pci_ss_list_134c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134d, pci_vendor_134d, pci_ss_list_134d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134e, pci_vendor_134e, pci_ss_list_134e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x134f, pci_vendor_134f, pci_ss_list_134f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1350, pci_vendor_1350, pci_ss_list_1350}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1351, pci_vendor_1351, pci_ss_list_1351}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1353, pci_vendor_1353, pci_ss_list_1353}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1354, pci_vendor_1354, pci_ss_list_1354}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1355, pci_vendor_1355, pci_ss_list_1355}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1356, pci_vendor_1356, pci_ss_list_1356}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1359, pci_vendor_1359, pci_ss_list_1359}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135a, pci_vendor_135a, pci_ss_list_135a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135b, pci_vendor_135b, pci_ss_list_135b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135c, pci_vendor_135c, pci_ss_list_135c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135d, pci_vendor_135d, pci_ss_list_135d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135e, pci_vendor_135e, pci_ss_list_135e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x135f, pci_vendor_135f, pci_ss_list_135f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1360, pci_vendor_1360, pci_ss_list_1360}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1361, pci_vendor_1361, pci_ss_list_1361}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1362, pci_vendor_1362, pci_ss_list_1362}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1363, pci_vendor_1363, pci_ss_list_1363}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1364, pci_vendor_1364, pci_ss_list_1364}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1365, pci_vendor_1365, pci_ss_list_1365}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1366, pci_vendor_1366, pci_ss_list_1366}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1367, pci_vendor_1367, pci_ss_list_1367}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1368, pci_vendor_1368, pci_ss_list_1368}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1369, pci_vendor_1369, pci_ss_list_1369}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136a, pci_vendor_136a, pci_ss_list_136a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136b, pci_vendor_136b, pci_ss_list_136b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136c, pci_vendor_136c, pci_ss_list_136c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136d, pci_vendor_136d, pci_ss_list_136d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x136f, pci_vendor_136f, pci_ss_list_136f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1370, pci_vendor_1370, pci_ss_list_1370}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1371, pci_vendor_1371, pci_ss_list_1371}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1373, pci_vendor_1373, pci_ss_list_1373}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1374, pci_vendor_1374, pci_ss_list_1374}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1375, pci_vendor_1375, pci_ss_list_1375}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1376, pci_vendor_1376, pci_ss_list_1376}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1377, pci_vendor_1377, pci_ss_list_1377}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1378, pci_vendor_1378, pci_ss_list_1378}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1379, pci_vendor_1379, pci_ss_list_1379}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137a, pci_vendor_137a, pci_ss_list_137a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137b, pci_vendor_137b, pci_ss_list_137b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137c, pci_vendor_137c, pci_ss_list_137c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137d, pci_vendor_137d, pci_ss_list_137d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137e, pci_vendor_137e, pci_ss_list_137e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x137f, pci_vendor_137f, pci_ss_list_137f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1380, pci_vendor_1380, pci_ss_list_1380}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1381, pci_vendor_1381, pci_ss_list_1381}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1382, pci_vendor_1382, pci_ss_list_1382}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1383, pci_vendor_1383, pci_ss_list_1383}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1384, pci_vendor_1384, pci_ss_list_1384}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1385, pci_vendor_1385, pci_ss_list_1385}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1386, pci_vendor_1386, pci_ss_list_1386}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1387, pci_vendor_1387, pci_ss_list_1387}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1388, pci_vendor_1388, pci_ss_list_1388}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1389, pci_vendor_1389, pci_ss_list_1389}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138a, pci_vendor_138a, pci_ss_list_138a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138b, pci_vendor_138b, pci_ss_list_138b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138c, pci_vendor_138c, pci_ss_list_138c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138d, pci_vendor_138d, pci_ss_list_138d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138e, pci_vendor_138e, pci_ss_list_138e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x138f, pci_vendor_138f, pci_ss_list_138f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1390, pci_vendor_1390, pci_ss_list_1390}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1391, pci_vendor_1391, pci_ss_list_1391}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1392, pci_vendor_1392, pci_ss_list_1392}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1393, pci_vendor_1393, pci_ss_list_1393}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1394, pci_vendor_1394, pci_ss_list_1394}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1395, pci_vendor_1395, pci_ss_list_1395}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1396, pci_vendor_1396, pci_ss_list_1396}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1397, pci_vendor_1397, pci_ss_list_1397}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1398, pci_vendor_1398, pci_ss_list_1398}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1399, pci_vendor_1399, pci_ss_list_1399}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139a, pci_vendor_139a, pci_ss_list_139a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139b, pci_vendor_139b, pci_ss_list_139b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139c, pci_vendor_139c, pci_ss_list_139c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139d, pci_vendor_139d, pci_ss_list_139d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139e, pci_vendor_139e, pci_ss_list_139e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x139f, pci_vendor_139f, pci_ss_list_139f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a0, pci_vendor_13a0, pci_ss_list_13a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a1, pci_vendor_13a1, pci_ss_list_13a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a2, pci_vendor_13a2, pci_ss_list_13a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a3, pci_vendor_13a3, pci_ss_list_13a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a4, pci_vendor_13a4, pci_ss_list_13a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a5, pci_vendor_13a5, pci_ss_list_13a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a6, pci_vendor_13a6, pci_ss_list_13a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a7, pci_vendor_13a7, pci_ss_list_13a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a8, pci_vendor_13a8, pci_ss_list_13a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13a9, pci_vendor_13a9, pci_ss_list_13a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13aa, pci_vendor_13aa, pci_ss_list_13aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ab, pci_vendor_13ab, pci_ss_list_13ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ac, pci_vendor_13ac, pci_ss_list_13ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ad, pci_vendor_13ad, pci_ss_list_13ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ae, pci_vendor_13ae, pci_ss_list_13ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13af, pci_vendor_13af, pci_ss_list_13af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b0, pci_vendor_13b0, pci_ss_list_13b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b1, pci_vendor_13b1, pci_ss_list_13b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b2, pci_vendor_13b2, pci_ss_list_13b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b3, pci_vendor_13b3, pci_ss_list_13b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b4, pci_vendor_13b4, pci_ss_list_13b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b5, pci_vendor_13b5, pci_ss_list_13b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b6, pci_vendor_13b6, pci_ss_list_13b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b7, pci_vendor_13b7, pci_ss_list_13b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b8, pci_vendor_13b8, pci_ss_list_13b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13b9, pci_vendor_13b9, pci_ss_list_13b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ba, pci_vendor_13ba, pci_ss_list_13ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bb, pci_vendor_13bb, pci_ss_list_13bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bc, pci_vendor_13bc, pci_ss_list_13bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bd, pci_vendor_13bd, pci_ss_list_13bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13be, pci_vendor_13be, pci_ss_list_13be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13bf, pci_vendor_13bf, pci_ss_list_13bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c0, pci_vendor_13c0, pci_ss_list_13c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c1, pci_vendor_13c1, pci_ss_list_13c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c2, pci_vendor_13c2, pci_ss_list_13c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c3, pci_vendor_13c3, pci_ss_list_13c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c4, pci_vendor_13c4, pci_ss_list_13c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c5, pci_vendor_13c5, pci_ss_list_13c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c6, pci_vendor_13c6, pci_ss_list_13c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c7, pci_vendor_13c7, pci_ss_list_13c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c8, pci_vendor_13c8, pci_ss_list_13c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13c9, pci_vendor_13c9, pci_ss_list_13c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ca, pci_vendor_13ca, pci_ss_list_13ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cb, pci_vendor_13cb, pci_ss_list_13cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cc, pci_vendor_13cc, pci_ss_list_13cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cd, pci_vendor_13cd, pci_ss_list_13cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ce, pci_vendor_13ce, pci_ss_list_13ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13cf, pci_vendor_13cf, pci_ss_list_13cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d0, pci_vendor_13d0, pci_ss_list_13d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d1, pci_vendor_13d1, pci_ss_list_13d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d2, pci_vendor_13d2, pci_ss_list_13d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d3, pci_vendor_13d3, pci_ss_list_13d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d4, pci_vendor_13d4, pci_ss_list_13d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d5, pci_vendor_13d5, pci_ss_list_13d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d6, pci_vendor_13d6, pci_ss_list_13d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d7, pci_vendor_13d7, pci_ss_list_13d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d8, pci_vendor_13d8, pci_ss_list_13d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13d9, pci_vendor_13d9, pci_ss_list_13d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13da, pci_vendor_13da, pci_ss_list_13da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13db, pci_vendor_13db, pci_ss_list_13db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13dc, pci_vendor_13dc, pci_ss_list_13dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13dd, pci_vendor_13dd, pci_ss_list_13dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13de, pci_vendor_13de, pci_ss_list_13de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13df, pci_vendor_13df, pci_ss_list_13df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e0, pci_vendor_13e0, pci_ss_list_13e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e1, pci_vendor_13e1, pci_ss_list_13e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e2, pci_vendor_13e2, pci_ss_list_13e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e3, pci_vendor_13e3, pci_ss_list_13e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e4, pci_vendor_13e4, pci_ss_list_13e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e5, pci_vendor_13e5, pci_ss_list_13e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e6, pci_vendor_13e6, pci_ss_list_13e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e7, pci_vendor_13e7, pci_ss_list_13e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e8, pci_vendor_13e8, pci_ss_list_13e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13e9, pci_vendor_13e9, pci_ss_list_13e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ea, pci_vendor_13ea, pci_ss_list_13ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13eb, pci_vendor_13eb, pci_ss_list_13eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ec, pci_vendor_13ec, pci_ss_list_13ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ed, pci_vendor_13ed, pci_ss_list_13ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ee, pci_vendor_13ee, pci_ss_list_13ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ef, pci_vendor_13ef, pci_ss_list_13ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f0, pci_vendor_13f0, pci_ss_list_13f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f1, pci_vendor_13f1, pci_ss_list_13f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f2, pci_vendor_13f2, pci_ss_list_13f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f3, pci_vendor_13f3, pci_ss_list_13f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f4, pci_vendor_13f4, pci_ss_list_13f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f5, pci_vendor_13f5, pci_ss_list_13f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f6, pci_vendor_13f6, pci_ss_list_13f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f7, pci_vendor_13f7, pci_ss_list_13f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f8, pci_vendor_13f8, pci_ss_list_13f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13f9, pci_vendor_13f9, pci_ss_list_13f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fa, pci_vendor_13fa, pci_ss_list_13fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fb, pci_vendor_13fb, pci_ss_list_13fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fc, pci_vendor_13fc, pci_ss_list_13fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fd, pci_vendor_13fd, pci_ss_list_13fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13fe, pci_vendor_13fe, pci_ss_list_13fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x13ff, pci_vendor_13ff, pci_ss_list_13ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1400, pci_vendor_1400, pci_ss_list_1400}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1401, pci_vendor_1401, pci_ss_list_1401}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1402, pci_vendor_1402, pci_ss_list_1402}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1403, pci_vendor_1403, pci_ss_list_1403}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1404, pci_vendor_1404, pci_ss_list_1404}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1405, pci_vendor_1405, pci_ss_list_1405}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1406, pci_vendor_1406, pci_ss_list_1406}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1407, pci_vendor_1407, pci_ss_list_1407}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1408, pci_vendor_1408, pci_ss_list_1408}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1409, pci_vendor_1409, pci_ss_list_1409}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140a, pci_vendor_140a, pci_ss_list_140a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140b, pci_vendor_140b, pci_ss_list_140b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140c, pci_vendor_140c, pci_ss_list_140c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140d, pci_vendor_140d, pci_ss_list_140d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140e, pci_vendor_140e, pci_ss_list_140e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x140f, pci_vendor_140f, pci_ss_list_140f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1410, pci_vendor_1410, pci_ss_list_1410}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1411, pci_vendor_1411, pci_ss_list_1411}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1412, pci_vendor_1412, pci_ss_list_1412}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1413, pci_vendor_1413, pci_ss_list_1413}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1414, pci_vendor_1414, pci_ss_list_1414}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1415, pci_vendor_1415, pci_ss_list_1415}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1416, pci_vendor_1416, pci_ss_list_1416}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1417, pci_vendor_1417, pci_ss_list_1417}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1418, pci_vendor_1418, pci_ss_list_1418}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1419, pci_vendor_1419, pci_ss_list_1419}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141a, pci_vendor_141a, pci_ss_list_141a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141b, pci_vendor_141b, pci_ss_list_141b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141d, pci_vendor_141d, pci_ss_list_141d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141e, pci_vendor_141e, pci_ss_list_141e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x141f, pci_vendor_141f, pci_ss_list_141f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1420, pci_vendor_1420, pci_ss_list_1420}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1421, pci_vendor_1421, pci_ss_list_1421}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1422, pci_vendor_1422, pci_ss_list_1422}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1423, pci_vendor_1423, pci_ss_list_1423}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1424, pci_vendor_1424, pci_ss_list_1424}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1425, pci_vendor_1425, pci_ss_list_1425}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1426, pci_vendor_1426, pci_ss_list_1426}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1427, pci_vendor_1427, pci_ss_list_1427}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1428, pci_vendor_1428, pci_ss_list_1428}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1429, pci_vendor_1429, pci_ss_list_1429}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142a, pci_vendor_142a, pci_ss_list_142a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142b, pci_vendor_142b, pci_ss_list_142b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142c, pci_vendor_142c, pci_ss_list_142c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142d, pci_vendor_142d, pci_ss_list_142d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142e, pci_vendor_142e, pci_ss_list_142e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x142f, pci_vendor_142f, pci_ss_list_142f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1430, pci_vendor_1430, pci_ss_list_1430}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1431, pci_vendor_1431, pci_ss_list_1431}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1432, pci_vendor_1432, pci_ss_list_1432}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1433, pci_vendor_1433, pci_ss_list_1433}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1435, pci_vendor_1435, pci_ss_list_1435}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1436, pci_vendor_1436, pci_ss_list_1436}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1437, pci_vendor_1437, pci_ss_list_1437}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1438, pci_vendor_1438, pci_ss_list_1438}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1439, pci_vendor_1439, pci_ss_list_1439}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143a, pci_vendor_143a, pci_ss_list_143a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143b, pci_vendor_143b, pci_ss_list_143b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143c, pci_vendor_143c, pci_ss_list_143c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143d, pci_vendor_143d, pci_ss_list_143d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143e, pci_vendor_143e, pci_ss_list_143e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x143f, pci_vendor_143f, pci_ss_list_143f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1440, pci_vendor_1440, pci_ss_list_1440}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1441, pci_vendor_1441, pci_ss_list_1441}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1442, pci_vendor_1442, pci_ss_list_1442}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1443, pci_vendor_1443, pci_ss_list_1443}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1444, pci_vendor_1444, pci_ss_list_1444}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1445, pci_vendor_1445, pci_ss_list_1445}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1446, pci_vendor_1446, pci_ss_list_1446}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1447, pci_vendor_1447, pci_ss_list_1447}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1448, pci_vendor_1448, pci_ss_list_1448}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1449, pci_vendor_1449, pci_ss_list_1449}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144a, pci_vendor_144a, pci_ss_list_144a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144b, pci_vendor_144b, pci_ss_list_144b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144c, pci_vendor_144c, pci_ss_list_144c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144d, pci_vendor_144d, pci_ss_list_144d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144e, pci_vendor_144e, pci_ss_list_144e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x144f, pci_vendor_144f, pci_ss_list_144f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1450, pci_vendor_1450, pci_ss_list_1450}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1451, pci_vendor_1451, pci_ss_list_1451}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1453, pci_vendor_1453, pci_ss_list_1453}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1454, pci_vendor_1454, pci_ss_list_1454}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1455, pci_vendor_1455, pci_ss_list_1455}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1456, pci_vendor_1456, pci_ss_list_1456}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1457, pci_vendor_1457, pci_ss_list_1457}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1458, pci_vendor_1458, pci_ss_list_1458}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1459, pci_vendor_1459, pci_ss_list_1459}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145a, pci_vendor_145a, pci_ss_list_145a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145b, pci_vendor_145b, pci_ss_list_145b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145c, pci_vendor_145c, pci_ss_list_145c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145d, pci_vendor_145d, pci_ss_list_145d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145e, pci_vendor_145e, pci_ss_list_145e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x145f, pci_vendor_145f, pci_ss_list_145f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1460, pci_vendor_1460, pci_ss_list_1460}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1461, pci_vendor_1461, pci_ss_list_1461}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1462, pci_vendor_1462, pci_ss_list_1462}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1463, pci_vendor_1463, pci_ss_list_1463}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1464, pci_vendor_1464, pci_ss_list_1464}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1465, pci_vendor_1465, pci_ss_list_1465}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1466, pci_vendor_1466, pci_ss_list_1466}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1467, pci_vendor_1467, pci_ss_list_1467}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1468, pci_vendor_1468, pci_ss_list_1468}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1469, pci_vendor_1469, pci_ss_list_1469}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146a, pci_vendor_146a, pci_ss_list_146a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146b, pci_vendor_146b, pci_ss_list_146b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146c, pci_vendor_146c, pci_ss_list_146c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146d, pci_vendor_146d, pci_ss_list_146d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146e, pci_vendor_146e, pci_ss_list_146e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x146f, pci_vendor_146f, pci_ss_list_146f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1470, pci_vendor_1470, pci_ss_list_1470}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1471, pci_vendor_1471, pci_ss_list_1471}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1472, pci_vendor_1472, pci_ss_list_1472}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1473, pci_vendor_1473, pci_ss_list_1473}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1474, pci_vendor_1474, pci_ss_list_1474}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1475, pci_vendor_1475, pci_ss_list_1475}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1476, pci_vendor_1476, pci_ss_list_1476}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1477, pci_vendor_1477, pci_ss_list_1477}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1478, pci_vendor_1478, pci_ss_list_1478}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1479, pci_vendor_1479, pci_ss_list_1479}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147a, pci_vendor_147a, pci_ss_list_147a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147b, pci_vendor_147b, pci_ss_list_147b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147c, pci_vendor_147c, pci_ss_list_147c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147d, pci_vendor_147d, pci_ss_list_147d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147e, pci_vendor_147e, pci_ss_list_147e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x147f, pci_vendor_147f, pci_ss_list_147f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1480, pci_vendor_1480, pci_ss_list_1480}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1481, pci_vendor_1481, pci_ss_list_1481}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1482, pci_vendor_1482, pci_ss_list_1482}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1483, pci_vendor_1483, pci_ss_list_1483}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1484, pci_vendor_1484, pci_ss_list_1484}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1485, pci_vendor_1485, pci_ss_list_1485}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1486, pci_vendor_1486, pci_ss_list_1486}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1487, pci_vendor_1487, pci_ss_list_1487}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1488, pci_vendor_1488, pci_ss_list_1488}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1489, pci_vendor_1489, pci_ss_list_1489}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148a, pci_vendor_148a, pci_ss_list_148a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148b, pci_vendor_148b, pci_ss_list_148b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148c, pci_vendor_148c, pci_ss_list_148c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148d, pci_vendor_148d, pci_ss_list_148d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148e, pci_vendor_148e, pci_ss_list_148e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x148f, pci_vendor_148f, pci_ss_list_148f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1490, pci_vendor_1490, pci_ss_list_1490}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1491, pci_vendor_1491, pci_ss_list_1491}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1492, pci_vendor_1492, pci_ss_list_1492}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1493, pci_vendor_1493, pci_ss_list_1493}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1494, pci_vendor_1494, pci_ss_list_1494}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1495, pci_vendor_1495, pci_ss_list_1495}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1496, pci_vendor_1496, pci_ss_list_1496}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1497, pci_vendor_1497, pci_ss_list_1497}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1498, pci_vendor_1498, pci_ss_list_1498}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1499, pci_vendor_1499, pci_ss_list_1499}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149a, pci_vendor_149a, pci_ss_list_149a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149b, pci_vendor_149b, pci_ss_list_149b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149c, pci_vendor_149c, pci_ss_list_149c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149d, pci_vendor_149d, pci_ss_list_149d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149e, pci_vendor_149e, pci_ss_list_149e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x149f, pci_vendor_149f, pci_ss_list_149f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a0, pci_vendor_14a0, pci_ss_list_14a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a1, pci_vendor_14a1, pci_ss_list_14a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a2, pci_vendor_14a2, pci_ss_list_14a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a3, pci_vendor_14a3, pci_ss_list_14a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a4, pci_vendor_14a4, pci_ss_list_14a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a5, pci_vendor_14a5, pci_ss_list_14a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a6, pci_vendor_14a6, pci_ss_list_14a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a7, pci_vendor_14a7, pci_ss_list_14a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a8, pci_vendor_14a8, pci_ss_list_14a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14a9, pci_vendor_14a9, pci_ss_list_14a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14aa, pci_vendor_14aa, pci_ss_list_14aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ab, pci_vendor_14ab, pci_ss_list_14ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ac, pci_vendor_14ac, pci_ss_list_14ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ad, pci_vendor_14ad, pci_ss_list_14ad}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ae, pci_vendor_14ae, pci_ss_list_14ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14af, pci_vendor_14af, pci_ss_list_14af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b0, pci_vendor_14b0, pci_ss_list_14b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b1, pci_vendor_14b1, pci_ss_list_14b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b2, pci_vendor_14b2, pci_ss_list_14b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b3, pci_vendor_14b3, pci_ss_list_14b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b4, pci_vendor_14b4, pci_ss_list_14b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b5, pci_vendor_14b5, pci_ss_list_14b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b6, pci_vendor_14b6, pci_ss_list_14b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b7, pci_vendor_14b7, pci_ss_list_14b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b8, pci_vendor_14b8, pci_ss_list_14b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14b9, pci_vendor_14b9, pci_ss_list_14b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ba, pci_vendor_14ba, pci_ss_list_14ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bb, pci_vendor_14bb, pci_ss_list_14bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bc, pci_vendor_14bc, pci_ss_list_14bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bd, pci_vendor_14bd, pci_ss_list_14bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14be, pci_vendor_14be, pci_ss_list_14be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14bf, pci_vendor_14bf, pci_ss_list_14bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c0, pci_vendor_14c0, pci_ss_list_14c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c1, pci_vendor_14c1, pci_ss_list_14c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c2, pci_vendor_14c2, pci_ss_list_14c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c3, pci_vendor_14c3, pci_ss_list_14c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c4, pci_vendor_14c4, pci_ss_list_14c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c5, pci_vendor_14c5, pci_ss_list_14c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c6, pci_vendor_14c6, pci_ss_list_14c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c7, pci_vendor_14c7, pci_ss_list_14c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c8, pci_vendor_14c8, pci_ss_list_14c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14c9, pci_vendor_14c9, pci_ss_list_14c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ca, pci_vendor_14ca, pci_ss_list_14ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cb, pci_vendor_14cb, pci_ss_list_14cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cc, pci_vendor_14cc, pci_ss_list_14cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cd, pci_vendor_14cd, pci_ss_list_14cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ce, pci_vendor_14ce, pci_ss_list_14ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14cf, pci_vendor_14cf, pci_ss_list_14cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d0, pci_vendor_14d0, pci_ss_list_14d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d1, pci_vendor_14d1, pci_ss_list_14d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d2, pci_vendor_14d2, pci_ss_list_14d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d3, pci_vendor_14d3, pci_ss_list_14d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d4, pci_vendor_14d4, pci_ss_list_14d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d5, pci_vendor_14d5, pci_ss_list_14d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d6, pci_vendor_14d6, pci_ss_list_14d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d7, pci_vendor_14d7, pci_ss_list_14d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d8, pci_vendor_14d8, pci_ss_list_14d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14d9, pci_vendor_14d9, pci_ss_list_14d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14da, pci_vendor_14da, pci_ss_list_14da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14db, pci_vendor_14db, pci_ss_list_14db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14dc, pci_vendor_14dc, pci_ss_list_14dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14dd, pci_vendor_14dd, pci_ss_list_14dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14de, pci_vendor_14de, pci_ss_list_14de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14df, pci_vendor_14df, pci_ss_list_14df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e1, pci_vendor_14e1, pci_ss_list_14e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e2, pci_vendor_14e2, pci_ss_list_14e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e3, pci_vendor_14e3, pci_ss_list_14e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e4, pci_vendor_14e4, pci_ss_list_14e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e5, pci_vendor_14e5, pci_ss_list_14e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e6, pci_vendor_14e6, pci_ss_list_14e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e7, pci_vendor_14e7, pci_ss_list_14e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e8, pci_vendor_14e8, pci_ss_list_14e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14e9, pci_vendor_14e9, pci_ss_list_14e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ea, pci_vendor_14ea, pci_ss_list_14ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14eb, pci_vendor_14eb, pci_ss_list_14eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ec, pci_vendor_14ec, pci_ss_list_14ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ed, pci_vendor_14ed, pci_ss_list_14ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ee, pci_vendor_14ee, pci_ss_list_14ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ef, pci_vendor_14ef, pci_ss_list_14ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f0, pci_vendor_14f0, pci_ss_list_14f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f1, pci_vendor_14f1, pci_ss_list_14f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f2, pci_vendor_14f2, pci_ss_list_14f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f3, pci_vendor_14f3, pci_ss_list_14f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f4, pci_vendor_14f4, pci_ss_list_14f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f5, pci_vendor_14f5, pci_ss_list_14f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f6, pci_vendor_14f6, pci_ss_list_14f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f7, pci_vendor_14f7, pci_ss_list_14f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f8, pci_vendor_14f8, pci_ss_list_14f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14f9, pci_vendor_14f9, pci_ss_list_14f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fa, pci_vendor_14fa, pci_ss_list_14fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fb, pci_vendor_14fb, pci_ss_list_14fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fc, pci_vendor_14fc, pci_ss_list_14fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fd, pci_vendor_14fd, pci_ss_list_14fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14fe, pci_vendor_14fe, pci_ss_list_14fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x14ff, pci_vendor_14ff, pci_ss_list_14ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1500, pci_vendor_1500, pci_ss_list_1500}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1501, pci_vendor_1501, pci_ss_list_1501}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1502, pci_vendor_1502, pci_ss_list_1502}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1503, pci_vendor_1503, pci_ss_list_1503}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1504, pci_vendor_1504, pci_ss_list_1504}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1505, pci_vendor_1505, pci_ss_list_1505}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1506, pci_vendor_1506, pci_ss_list_1506}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1507, pci_vendor_1507, pci_ss_list_1507}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1508, pci_vendor_1508, pci_ss_list_1508}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1509, pci_vendor_1509, pci_ss_list_1509}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150a, pci_vendor_150a, pci_ss_list_150a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150b, pci_vendor_150b, pci_ss_list_150b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150c, pci_vendor_150c, pci_ss_list_150c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150d, pci_vendor_150d, pci_ss_list_150d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150e, pci_vendor_150e, pci_ss_list_150e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x150f, pci_vendor_150f, pci_ss_list_150f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1510, pci_vendor_1510, pci_ss_list_1510}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1511, pci_vendor_1511, pci_ss_list_1511}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1512, pci_vendor_1512, pci_ss_list_1512}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1513, pci_vendor_1513, pci_ss_list_1513}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1514, pci_vendor_1514, pci_ss_list_1514}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1515, pci_vendor_1515, pci_ss_list_1515}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1516, pci_vendor_1516, pci_ss_list_1516}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1517, pci_vendor_1517, pci_ss_list_1517}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1518, pci_vendor_1518, pci_ss_list_1518}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1519, pci_vendor_1519, pci_ss_list_1519}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151a, pci_vendor_151a, pci_ss_list_151a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151b, pci_vendor_151b, pci_ss_list_151b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151c, pci_vendor_151c, pci_ss_list_151c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151d, pci_vendor_151d, pci_ss_list_151d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151e, pci_vendor_151e, pci_ss_list_151e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x151f, pci_vendor_151f, pci_ss_list_151f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1520, pci_vendor_1520, pci_ss_list_1520}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1521, pci_vendor_1521, pci_ss_list_1521}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1522, pci_vendor_1522, pci_ss_list_1522}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1523, pci_vendor_1523, pci_ss_list_1523}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1524, pci_vendor_1524, pci_ss_list_1524}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1525, pci_vendor_1525, pci_ss_list_1525}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1526, pci_vendor_1526, pci_ss_list_1526}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1527, pci_vendor_1527, pci_ss_list_1527}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1528, pci_vendor_1528, pci_ss_list_1528}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1529, pci_vendor_1529, pci_ss_list_1529}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152a, pci_vendor_152a, pci_ss_list_152a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152b, pci_vendor_152b, pci_ss_list_152b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152c, pci_vendor_152c, pci_ss_list_152c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152d, pci_vendor_152d, pci_ss_list_152d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152e, pci_vendor_152e, pci_ss_list_152e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x152f, pci_vendor_152f, pci_ss_list_152f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1530, pci_vendor_1530, pci_ss_list_1530}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1531, pci_vendor_1531, pci_ss_list_1531}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1532, pci_vendor_1532, pci_ss_list_1532}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1533, pci_vendor_1533, pci_ss_list_1533}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1534, pci_vendor_1534, pci_ss_list_1534}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1535, pci_vendor_1535, pci_ss_list_1535}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1537, pci_vendor_1537, pci_ss_list_1537}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1538, pci_vendor_1538, pci_ss_list_1538}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1539, pci_vendor_1539, pci_ss_list_1539}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153a, pci_vendor_153a, pci_ss_list_153a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153b, pci_vendor_153b, pci_ss_list_153b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153c, pci_vendor_153c, pci_ss_list_153c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153d, pci_vendor_153d, pci_ss_list_153d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153e, pci_vendor_153e, pci_ss_list_153e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x153f, pci_vendor_153f, pci_ss_list_153f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1540, pci_vendor_1540, pci_ss_list_1540}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1541, pci_vendor_1541, pci_ss_list_1541}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1542, pci_vendor_1542, pci_ss_list_1542}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1543, pci_vendor_1543, pci_ss_list_1543}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1544, pci_vendor_1544, pci_ss_list_1544}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1545, pci_vendor_1545, pci_ss_list_1545}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1546, pci_vendor_1546, pci_ss_list_1546}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1547, pci_vendor_1547, pci_ss_list_1547}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1548, pci_vendor_1548, pci_ss_list_1548}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1549, pci_vendor_1549, pci_ss_list_1549}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154a, pci_vendor_154a, pci_ss_list_154a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154b, pci_vendor_154b, pci_ss_list_154b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154c, pci_vendor_154c, pci_ss_list_154c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154d, pci_vendor_154d, pci_ss_list_154d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154e, pci_vendor_154e, pci_ss_list_154e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x154f, pci_vendor_154f, pci_ss_list_154f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1550, pci_vendor_1550, pci_ss_list_1550}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1551, pci_vendor_1551, pci_ss_list_1551}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1552, pci_vendor_1552, pci_ss_list_1552}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1553, pci_vendor_1553, pci_ss_list_1553}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1554, pci_vendor_1554, pci_ss_list_1554}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1555, pci_vendor_1555, pci_ss_list_1555}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1556, pci_vendor_1556, pci_ss_list_1556}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1557, pci_vendor_1557, pci_ss_list_1557}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1558, pci_vendor_1558, pci_ss_list_1558}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1559, pci_vendor_1559, pci_ss_list_1559}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155a, pci_vendor_155a, pci_ss_list_155a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155b, pci_vendor_155b, pci_ss_list_155b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155c, pci_vendor_155c, pci_ss_list_155c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155d, pci_vendor_155d, pci_ss_list_155d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155e, pci_vendor_155e, pci_ss_list_155e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x155f, pci_vendor_155f, pci_ss_list_155f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1560, pci_vendor_1560, pci_ss_list_1560}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1561, pci_vendor_1561, pci_ss_list_1561}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1562, pci_vendor_1562, pci_ss_list_1562}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1563, pci_vendor_1563, pci_ss_list_1563}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1564, pci_vendor_1564, pci_ss_list_1564}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1565, pci_vendor_1565, pci_ss_list_1565}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1566, pci_vendor_1566, pci_ss_list_1566}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1567, pci_vendor_1567, pci_ss_list_1567}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1568, pci_vendor_1568, pci_ss_list_1568}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1569, pci_vendor_1569, pci_ss_list_1569}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156a, pci_vendor_156a, pci_ss_list_156a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156b, pci_vendor_156b, pci_ss_list_156b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156c, pci_vendor_156c, pci_ss_list_156c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156d, pci_vendor_156d, pci_ss_list_156d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156e, pci_vendor_156e, pci_ss_list_156e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x156f, pci_vendor_156f, pci_ss_list_156f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1570, pci_vendor_1570, pci_ss_list_1570}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1571, pci_vendor_1571, pci_ss_list_1571}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1572, pci_vendor_1572, pci_ss_list_1572}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1573, pci_vendor_1573, pci_ss_list_1573}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1574, pci_vendor_1574, pci_ss_list_1574}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1575, pci_vendor_1575, pci_ss_list_1575}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1576, pci_vendor_1576, pci_ss_list_1576}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1578, pci_vendor_1578, pci_ss_list_1578}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1579, pci_vendor_1579, pci_ss_list_1579}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157a, pci_vendor_157a, pci_ss_list_157a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157b, pci_vendor_157b, pci_ss_list_157b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157c, pci_vendor_157c, pci_ss_list_157c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157d, pci_vendor_157d, pci_ss_list_157d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157e, pci_vendor_157e, pci_ss_list_157e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x157f, pci_vendor_157f, pci_ss_list_157f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1580, pci_vendor_1580, pci_ss_list_1580}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1581, pci_vendor_1581, pci_ss_list_1581}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1582, pci_vendor_1582, pci_ss_list_1582}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1583, pci_vendor_1583, pci_ss_list_1583}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1584, pci_vendor_1584, pci_ss_list_1584}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1585, pci_vendor_1585, pci_ss_list_1585}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1586, pci_vendor_1586, pci_ss_list_1586}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1587, pci_vendor_1587, pci_ss_list_1587}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1588, pci_vendor_1588, pci_ss_list_1588}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1589, pci_vendor_1589, pci_ss_list_1589}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158a, pci_vendor_158a, pci_ss_list_158a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158b, pci_vendor_158b, pci_ss_list_158b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158c, pci_vendor_158c, pci_ss_list_158c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158d, pci_vendor_158d, pci_ss_list_158d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158e, pci_vendor_158e, pci_ss_list_158e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x158f, pci_vendor_158f, pci_ss_list_158f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1590, pci_vendor_1590, pci_ss_list_1590}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1591, pci_vendor_1591, pci_ss_list_1591}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1592, pci_vendor_1592, pci_ss_list_1592}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1593, pci_vendor_1593, pci_ss_list_1593}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1594, pci_vendor_1594, pci_ss_list_1594}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1595, pci_vendor_1595, pci_ss_list_1595}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1596, pci_vendor_1596, pci_ss_list_1596}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1597, pci_vendor_1597, pci_ss_list_1597}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1598, pci_vendor_1598, pci_ss_list_1598}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1599, pci_vendor_1599, pci_ss_list_1599}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159a, pci_vendor_159a, pci_ss_list_159a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159b, pci_vendor_159b, pci_ss_list_159b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159c, pci_vendor_159c, pci_ss_list_159c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159d, pci_vendor_159d, pci_ss_list_159d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159e, pci_vendor_159e, pci_ss_list_159e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x159f, pci_vendor_159f, pci_ss_list_159f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a0, pci_vendor_15a0, pci_ss_list_15a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a1, pci_vendor_15a1, pci_ss_list_15a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a2, pci_vendor_15a2, pci_ss_list_15a2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a3, pci_vendor_15a3, pci_ss_list_15a3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a4, pci_vendor_15a4, pci_ss_list_15a4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a5, pci_vendor_15a5, pci_ss_list_15a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a6, pci_vendor_15a6, pci_ss_list_15a6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a7, pci_vendor_15a7, pci_ss_list_15a7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15a8, pci_vendor_15a8, pci_ss_list_15a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15aa, pci_vendor_15aa, pci_ss_list_15aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ab, pci_vendor_15ab, pci_ss_list_15ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ac, pci_vendor_15ac, pci_ss_list_15ac}, +#endif + {0x15ad, pci_vendor_15ad, pci_ss_list_15ad}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ae, pci_vendor_15ae, pci_ss_list_15ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b0, pci_vendor_15b0, pci_ss_list_15b0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b1, pci_vendor_15b1, pci_ss_list_15b1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b2, pci_vendor_15b2, pci_ss_list_15b2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b3, pci_vendor_15b3, pci_ss_list_15b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b4, pci_vendor_15b4, pci_ss_list_15b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b5, pci_vendor_15b5, pci_ss_list_15b5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b6, pci_vendor_15b6, pci_ss_list_15b6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b7, pci_vendor_15b7, pci_ss_list_15b7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b8, pci_vendor_15b8, pci_ss_list_15b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15b9, pci_vendor_15b9, pci_ss_list_15b9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ba, pci_vendor_15ba, pci_ss_list_15ba}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bb, pci_vendor_15bb, pci_ss_list_15bb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bc, pci_vendor_15bc, pci_ss_list_15bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bd, pci_vendor_15bd, pci_ss_list_15bd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15be, pci_vendor_15be, pci_ss_list_15be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15bf, pci_vendor_15bf, pci_ss_list_15bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c0, pci_vendor_15c0, pci_ss_list_15c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c1, pci_vendor_15c1, pci_ss_list_15c1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c2, pci_vendor_15c2, pci_ss_list_15c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c3, pci_vendor_15c3, pci_ss_list_15c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c4, pci_vendor_15c4, pci_ss_list_15c4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c5, pci_vendor_15c5, pci_ss_list_15c5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c6, pci_vendor_15c6, pci_ss_list_15c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c7, pci_vendor_15c7, pci_ss_list_15c7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c8, pci_vendor_15c8, pci_ss_list_15c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15c9, pci_vendor_15c9, pci_ss_list_15c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ca, pci_vendor_15ca, pci_ss_list_15ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cb, pci_vendor_15cb, pci_ss_list_15cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cc, pci_vendor_15cc, pci_ss_list_15cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cd, pci_vendor_15cd, pci_ss_list_15cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ce, pci_vendor_15ce, pci_ss_list_15ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15cf, pci_vendor_15cf, pci_ss_list_15cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d1, pci_vendor_15d1, pci_ss_list_15d1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d2, pci_vendor_15d2, pci_ss_list_15d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d3, pci_vendor_15d3, pci_ss_list_15d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d4, pci_vendor_15d4, pci_ss_list_15d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d5, pci_vendor_15d5, pci_ss_list_15d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d6, pci_vendor_15d6, pci_ss_list_15d6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d7, pci_vendor_15d7, pci_ss_list_15d7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d8, pci_vendor_15d8, pci_ss_list_15d8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15d9, pci_vendor_15d9, pci_ss_list_15d9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15da, pci_vendor_15da, pci_ss_list_15da}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15db, pci_vendor_15db, pci_ss_list_15db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15dc, pci_vendor_15dc, pci_ss_list_15dc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15dd, pci_vendor_15dd, pci_ss_list_15dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15de, pci_vendor_15de, pci_ss_list_15de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15df, pci_vendor_15df, pci_ss_list_15df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e0, pci_vendor_15e0, pci_ss_list_15e0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e1, pci_vendor_15e1, pci_ss_list_15e1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e2, pci_vendor_15e2, pci_ss_list_15e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e3, pci_vendor_15e3, pci_ss_list_15e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e4, pci_vendor_15e4, pci_ss_list_15e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e5, pci_vendor_15e5, pci_ss_list_15e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e6, pci_vendor_15e6, pci_ss_list_15e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e7, pci_vendor_15e7, pci_ss_list_15e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e8, pci_vendor_15e8, pci_ss_list_15e8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15e9, pci_vendor_15e9, pci_ss_list_15e9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ea, pci_vendor_15ea, pci_ss_list_15ea}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15eb, pci_vendor_15eb, pci_ss_list_15eb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ec, pci_vendor_15ec, pci_ss_list_15ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ed, pci_vendor_15ed, pci_ss_list_15ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ee, pci_vendor_15ee, pci_ss_list_15ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ef, pci_vendor_15ef, pci_ss_list_15ef}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f0, pci_vendor_15f0, pci_ss_list_15f0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f1, pci_vendor_15f1, pci_ss_list_15f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f2, pci_vendor_15f2, pci_ss_list_15f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f3, pci_vendor_15f3, pci_ss_list_15f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f4, pci_vendor_15f4, pci_ss_list_15f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f5, pci_vendor_15f5, pci_ss_list_15f5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f6, pci_vendor_15f6, pci_ss_list_15f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f7, pci_vendor_15f7, pci_ss_list_15f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f8, pci_vendor_15f8, pci_ss_list_15f8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15f9, pci_vendor_15f9, pci_ss_list_15f9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fa, pci_vendor_15fa, pci_ss_list_15fa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fb, pci_vendor_15fb, pci_ss_list_15fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fc, pci_vendor_15fc, pci_ss_list_15fc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fd, pci_vendor_15fd, pci_ss_list_15fd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15fe, pci_vendor_15fe, pci_ss_list_15fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x15ff, pci_vendor_15ff, pci_ss_list_15ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1600, pci_vendor_1600, pci_ss_list_1600}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1601, pci_vendor_1601, pci_ss_list_1601}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1602, pci_vendor_1602, pci_ss_list_1602}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1603, pci_vendor_1603, pci_ss_list_1603}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1604, pci_vendor_1604, pci_ss_list_1604}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1605, pci_vendor_1605, pci_ss_list_1605}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1606, pci_vendor_1606, pci_ss_list_1606}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1607, pci_vendor_1607, pci_ss_list_1607}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1608, pci_vendor_1608, pci_ss_list_1608}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1609, pci_vendor_1609, pci_ss_list_1609}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1612, pci_vendor_1612, pci_ss_list_1612}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1619, pci_vendor_1619, pci_ss_list_1619}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x161f, pci_vendor_161f, pci_ss_list_161f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1626, pci_vendor_1626, pci_ss_list_1626}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1629, pci_vendor_1629, pci_ss_list_1629}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1637, pci_vendor_1637, pci_ss_list_1637}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1638, pci_vendor_1638, pci_ss_list_1638}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x163c, pci_vendor_163c, pci_ss_list_163c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1657, pci_vendor_1657, pci_ss_list_1657}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165a, pci_vendor_165a, pci_ss_list_165a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165d, pci_vendor_165d, pci_ss_list_165d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x165f, pci_vendor_165f, pci_ss_list_165f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1661, pci_vendor_1661, pci_ss_list_1661}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1668, pci_vendor_1668, pci_ss_list_1668}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x166d, pci_vendor_166d, pci_ss_list_166d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1677, pci_vendor_1677, pci_ss_list_1677}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x167b, pci_vendor_167b, pci_ss_list_167b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x167d, pci_vendor_167d, pci_ss_list_167d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1681, pci_vendor_1681, pci_ss_list_1681}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1682, pci_vendor_1682, pci_ss_list_1682}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1688, pci_vendor_1688, pci_ss_list_1688}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x168c, pci_vendor_168c, pci_ss_list_168c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1695, pci_vendor_1695, pci_ss_list_1695}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x169c, pci_vendor_169c, pci_ss_list_169c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16a5, pci_vendor_16a5, pci_ss_list_16a5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ab, pci_vendor_16ab, pci_ss_list_16ab}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ae, pci_vendor_16ae, pci_ss_list_16ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16af, pci_vendor_16af, pci_ss_list_16af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16b4, pci_vendor_16b4, pci_ss_list_16b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16b8, pci_vendor_16b8, pci_ss_list_16b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16be, pci_vendor_16be, pci_ss_list_16be}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16c6, pci_vendor_16c6, pci_ss_list_16c6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16c8, pci_vendor_16c8, pci_ss_list_16c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16c9, pci_vendor_16c9, pci_ss_list_16c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ca, pci_vendor_16ca, pci_ss_list_16ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16cd, pci_vendor_16cd, pci_ss_list_16cd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ce, pci_vendor_16ce, pci_ss_list_16ce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16d5, pci_vendor_16d5, pci_ss_list_16d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16df, pci_vendor_16df, pci_ss_list_16df}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16e3, pci_vendor_16e3, pci_ss_list_16e3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16e5, pci_vendor_16e5, pci_ss_list_16e5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ec, pci_vendor_16ec, pci_ss_list_16ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16ed, pci_vendor_16ed, pci_ss_list_16ed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f3, pci_vendor_16f3, pci_ss_list_16f3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f4, pci_vendor_16f4, pci_ss_list_16f4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x16f6, pci_vendor_16f6, pci_ss_list_16f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1702, pci_vendor_1702, pci_ss_list_1702}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1705, pci_vendor_1705, pci_ss_list_1705}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x170b, pci_vendor_170b, pci_ss_list_170b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x170c, pci_vendor_170c, pci_ss_list_170c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1725, pci_vendor_1725, pci_ss_list_1725}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x172a, pci_vendor_172a, pci_ss_list_172a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1734, pci_vendor_1734, pci_ss_list_1734}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1737, pci_vendor_1737, pci_ss_list_1737}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x173b, pci_vendor_173b, pci_ss_list_173b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1743, pci_vendor_1743, pci_ss_list_1743}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1749, pci_vendor_1749, pci_ss_list_1749}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x174b, pci_vendor_174b, pci_ss_list_174b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x174d, pci_vendor_174d, pci_ss_list_174d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x175c, pci_vendor_175c, pci_ss_list_175c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x175e, pci_vendor_175e, pci_ss_list_175e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1775, pci_vendor_1775, pci_ss_list_1775}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1787, pci_vendor_1787, pci_ss_list_1787}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1796, pci_vendor_1796, pci_ss_list_1796}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1797, pci_vendor_1797, pci_ss_list_1797}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1799, pci_vendor_1799, pci_ss_list_1799}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x179c, pci_vendor_179c, pci_ss_list_179c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17a0, pci_vendor_17a0, pci_ss_list_17a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17aa, pci_vendor_17aa, pci_ss_list_17aa}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17af, pci_vendor_17af, pci_ss_list_17af}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17b3, pci_vendor_17b3, pci_ss_list_17b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17b4, pci_vendor_17b4, pci_ss_list_17b4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17c0, pci_vendor_17c0, pci_ss_list_17c0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17c2, pci_vendor_17c2, pci_ss_list_17c2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cb, pci_vendor_17cb, pci_ss_list_17cb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cc, pci_vendor_17cc, pci_ss_list_17cc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17cf, pci_vendor_17cf, pci_ss_list_17cf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17d3, pci_vendor_17d3, pci_ss_list_17d3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17d5, pci_vendor_17d5, pci_ss_list_17d5}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17db, pci_vendor_17db, pci_ss_list_17db}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17de, pci_vendor_17de, pci_ss_list_17de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17e4, pci_vendor_17e4, pci_ss_list_17e4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17e6, pci_vendor_17e6, pci_ss_list_17e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17ee, pci_vendor_17ee, pci_ss_list_17ee}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17f2, pci_vendor_17f2, pci_ss_list_17f2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17fe, pci_vendor_17fe, pci_ss_list_17fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x17ff, pci_vendor_17ff, pci_ss_list_17ff}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1809, pci_vendor_1809, pci_ss_list_1809}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1813, pci_vendor_1813, pci_ss_list_1813}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1814, pci_vendor_1814, pci_ss_list_1814}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1820, pci_vendor_1820, pci_ss_list_1820}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1822, pci_vendor_1822, pci_ss_list_1822}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x182d, pci_vendor_182d, pci_ss_list_182d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x182e, pci_vendor_182e, pci_ss_list_182e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1830, pci_vendor_1830, pci_ss_list_1830}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x183b, pci_vendor_183b, pci_ss_list_183b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1849, pci_vendor_1849, pci_ss_list_1849}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x184a, pci_vendor_184a, pci_ss_list_184a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1851, pci_vendor_1851, pci_ss_list_1851}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1852, pci_vendor_1852, pci_ss_list_1852}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1853, pci_vendor_1853, pci_ss_list_1853}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1854, pci_vendor_1854, pci_ss_list_1854}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x185b, pci_vendor_185b, pci_ss_list_185b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x185f, pci_vendor_185f, pci_ss_list_185f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1864, pci_vendor_1864, pci_ss_list_1864}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1867, pci_vendor_1867, pci_ss_list_1867}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x187e, pci_vendor_187e, pci_ss_list_187e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1885, pci_vendor_1885, pci_ss_list_1885}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1888, pci_vendor_1888, pci_ss_list_1888}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x188a, pci_vendor_188a, pci_ss_list_188a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1890, pci_vendor_1890, pci_ss_list_1890}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1894, pci_vendor_1894, pci_ss_list_1894}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1896, pci_vendor_1896, pci_ss_list_1896}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18a1, pci_vendor_18a1, pci_ss_list_18a1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ac, pci_vendor_18ac, pci_ss_list_18ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18b8, pci_vendor_18b8, pci_ss_list_18b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18bc, pci_vendor_18bc, pci_ss_list_18bc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18c3, pci_vendor_18c3, pci_ss_list_18c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18c8, pci_vendor_18c8, pci_ss_list_18c8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18c9, pci_vendor_18c9, pci_ss_list_18c9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ca, pci_vendor_18ca, pci_ss_list_18ca}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18d2, pci_vendor_18d2, pci_ss_list_18d2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18dd, pci_vendor_18dd, pci_ss_list_18dd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18e6, pci_vendor_18e6, pci_ss_list_18e6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18ec, pci_vendor_18ec, pci_ss_list_18ec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18f6, pci_vendor_18f6, pci_ss_list_18f6}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18f7, pci_vendor_18f7, pci_ss_list_18f7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x18fb, pci_vendor_18fb, pci_ss_list_18fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1904, pci_vendor_1904, pci_ss_list_1904}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1923, pci_vendor_1923, pci_ss_list_1923}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1924, pci_vendor_1924, pci_ss_list_1924}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x192e, pci_vendor_192e, pci_ss_list_192e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1931, pci_vendor_1931, pci_ss_list_1931}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1942, pci_vendor_1942, pci_ss_list_1942}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x194a, pci_vendor_194a, pci_ss_list_194a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1957, pci_vendor_1957, pci_ss_list_1957}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1958, pci_vendor_1958, pci_ss_list_1958}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1966, pci_vendor_1966, pci_ss_list_1966}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1969, pci_vendor_1969, pci_ss_list_1969}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x196a, pci_vendor_196a, pci_ss_list_196a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x196d, pci_vendor_196d, pci_ss_list_196d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x197b, pci_vendor_197b, pci_ss_list_197b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1989, pci_vendor_1989, pci_ss_list_1989}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1993, pci_vendor_1993, pci_ss_list_1993}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x199a, pci_vendor_199a, pci_ss_list_199a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19a8, pci_vendor_19a8, pci_ss_list_19a8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19ac, pci_vendor_19ac, pci_ss_list_19ac}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19ae, pci_vendor_19ae, pci_ss_list_19ae}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19d4, pci_vendor_19d4, pci_ss_list_19d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19e2, pci_vendor_19e2, pci_ss_list_19e2}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x19e7, pci_vendor_19e7, pci_ss_list_19e7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1a03, pci_vendor_1a03, pci_ss_list_1a03}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1a08, pci_vendor_1a08, pci_ss_list_1a08}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1a1d, pci_vendor_1a1d, pci_ss_list_1a1d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1a29, pci_vendor_1a29, pci_ss_list_1a29}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1a51, pci_vendor_1a51, pci_ss_list_1a51}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1b13, pci_vendor_1b13, pci_ss_list_1b13}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1c1c, pci_vendor_1c1c, pci_ss_list_1c1c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1d44, pci_vendor_1d44, pci_ss_list_1d44}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1de1, pci_vendor_1de1, pci_ss_list_1de1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fc0, pci_vendor_1fc0, pci_ss_list_1fc0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fc1, pci_vendor_1fc1, pci_ss_list_1fc1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x1fce, pci_vendor_1fce, pci_ss_list_1fce}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2000, pci_vendor_2000, pci_ss_list_2000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2001, pci_vendor_2001, pci_ss_list_2001}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2003, pci_vendor_2003, pci_ss_list_2003}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2004, pci_vendor_2004, pci_ss_list_2004}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x21c3, pci_vendor_21c3, pci_ss_list_21c3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x22b8, pci_vendor_22b8, pci_ss_list_22b8}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2348, pci_vendor_2348, pci_ss_list_2348}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2646, pci_vendor_2646, pci_ss_list_2646}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x270b, pci_vendor_270b, pci_ss_list_270b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x270f, pci_vendor_270f, pci_ss_list_270f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2711, pci_vendor_2711, pci_ss_list_2711}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x2a15, pci_vendor_2a15, pci_ss_list_2a15}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3000, pci_vendor_3000, pci_ss_list_3000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3142, pci_vendor_3142, pci_ss_list_3142}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3388, pci_vendor_3388, pci_ss_list_3388}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3411, pci_vendor_3411, pci_ss_list_3411}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3513, pci_vendor_3513, pci_ss_list_3513}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x3842, pci_vendor_3842, pci_ss_list_3842}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x38ef, pci_vendor_38ef, pci_ss_list_38ef}, +#endif + {0x3d3d, pci_vendor_3d3d, pci_ss_list_3d3d}, + {0x4005, pci_vendor_4005, pci_ss_list_4005}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4033, pci_vendor_4033, pci_ss_list_4033}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4143, pci_vendor_4143, pci_ss_list_4143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4144, pci_vendor_4144, pci_ss_list_4144}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x416c, pci_vendor_416c, pci_ss_list_416c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4321, pci_vendor_4321, pci_ss_list_4321}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4444, pci_vendor_4444, pci_ss_list_4444}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4468, pci_vendor_4468, pci_ss_list_4468}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4594, pci_vendor_4594, pci_ss_list_4594}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x45fb, pci_vendor_45fb, pci_ss_list_45fb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4680, pci_vendor_4680, pci_ss_list_4680}, +#endif + {0x4843, pci_vendor_4843, pci_ss_list_4843}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4916, pci_vendor_4916, pci_ss_list_4916}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4943, pci_vendor_4943, pci_ss_list_4943}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x494f, pci_vendor_494f, pci_ss_list_494f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4978, pci_vendor_4978, pci_ss_list_4978}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4a14, pci_vendor_4a14, pci_ss_list_4a14}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4b10, pci_vendor_4b10, pci_ss_list_4b10}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4c48, pci_vendor_4c48, pci_ss_list_4c48}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4c53, pci_vendor_4c53, pci_ss_list_4c53}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4ca1, pci_vendor_4ca1, pci_ss_list_4ca1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4d51, pci_vendor_4d51, pci_ss_list_4d51}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4d54, pci_vendor_4d54, pci_ss_list_4d54}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x4ddc, pci_vendor_4ddc, pci_ss_list_4ddc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5046, pci_vendor_5046, pci_ss_list_5046}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5053, pci_vendor_5053, pci_ss_list_5053}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5136, pci_vendor_5136, pci_ss_list_5136}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5143, pci_vendor_5143, pci_ss_list_5143}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5145, pci_vendor_5145, pci_ss_list_5145}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5168, pci_vendor_5168, pci_ss_list_5168}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5301, pci_vendor_5301, pci_ss_list_5301}, +#endif + {0x5333, pci_vendor_5333, pci_ss_list_5333}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x544c, pci_vendor_544c, pci_ss_list_544c}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5455, pci_vendor_5455, pci_ss_list_5455}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5519, pci_vendor_5519, pci_ss_list_5519}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5544, pci_vendor_5544, pci_ss_list_5544}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5555, pci_vendor_5555, pci_ss_list_5555}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5654, pci_vendor_5654, pci_ss_list_5654}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5700, pci_vendor_5700, pci_ss_list_5700}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x5851, pci_vendor_5851, pci_ss_list_5851}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6356, pci_vendor_6356, pci_ss_list_6356}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6374, pci_vendor_6374, pci_ss_list_6374}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6409, pci_vendor_6409, pci_ss_list_6409}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x6666, pci_vendor_6666, pci_ss_list_6666}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7063, pci_vendor_7063, pci_ss_list_7063}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7604, pci_vendor_7604, pci_ss_list_7604}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7bde, pci_vendor_7bde, pci_ss_list_7bde}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x7fed, pci_vendor_7fed, pci_ss_list_7fed}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8008, pci_vendor_8008, pci_ss_list_8008}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x807d, pci_vendor_807d, pci_ss_list_807d}, +#endif + {0x8086, pci_vendor_8086, pci_ss_list_8086}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8401, pci_vendor_8401, pci_ss_list_8401}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8686, pci_vendor_8686, pci_ss_list_8686}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8800, pci_vendor_8800, pci_ss_list_8800}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8866, pci_vendor_8866, pci_ss_list_8866}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8888, pci_vendor_8888, pci_ss_list_8888}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8912, pci_vendor_8912, pci_ss_list_8912}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8c4a, pci_vendor_8c4a, pci_ss_list_8c4a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8e0e, pci_vendor_8e0e, pci_ss_list_8e0e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x8e2e, pci_vendor_8e2e, pci_ss_list_8e2e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9004, pci_vendor_9004, pci_ss_list_9004}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9005, pci_vendor_9005, pci_ss_list_9005}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x907f, pci_vendor_907f, pci_ss_list_907f}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x919a, pci_vendor_919a, pci_ss_list_919a}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9412, pci_vendor_9412, pci_ss_list_9412}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9699, pci_vendor_9699, pci_ss_list_9699}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9710, pci_vendor_9710, pci_ss_list_9710}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0x9902, pci_vendor_9902, pci_ss_list_9902}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa0a0, pci_vendor_a0a0, pci_ss_list_a0a0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa0f1, pci_vendor_a0f1, pci_ss_list_a0f1}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa200, pci_vendor_a200, pci_ss_list_a200}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa259, pci_vendor_a259, pci_ss_list_a259}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa25b, pci_vendor_a25b, pci_ss_list_a25b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa304, pci_vendor_a304, pci_ss_list_a304}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xa727, pci_vendor_a727, pci_ss_list_a727}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xaa42, pci_vendor_aa42, pci_ss_list_aa42}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xac1e, pci_vendor_ac1e, pci_ss_list_ac1e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xac3d, pci_vendor_ac3d, pci_ss_list_ac3d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xaecb, pci_vendor_aecb, pci_ss_list_aecb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xaffe, pci_vendor_affe, pci_ss_list_affe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xb10b, pci_vendor_b10b, pci_ss_list_b10b}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xb1b3, pci_vendor_b1b3, pci_ss_list_b1b3}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xbd11, pci_vendor_bd11, pci_ss_list_bd11}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc001, pci_vendor_c001, pci_ss_list_c001}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc0a9, pci_vendor_c0a9, pci_ss_list_c0a9}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc0de, pci_vendor_c0de, pci_ss_list_c0de}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xc0fe, pci_vendor_c0fe, pci_ss_list_c0fe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xca50, pci_vendor_ca50, pci_ss_list_ca50}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xcafe, pci_vendor_cafe, pci_ss_list_cafe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xcccc, pci_vendor_cccc, pci_ss_list_cccc}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xccec, pci_vendor_ccec, pci_ss_list_ccec}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xcddd, pci_vendor_cddd, pci_ss_list_cddd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd161, pci_vendor_d161, pci_ss_list_d161}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd4d4, pci_vendor_d4d4, pci_ss_list_d4d4}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd531, pci_vendor_d531, pci_ss_list_d531}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xd84d, pci_vendor_d84d, pci_ss_list_d84d}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xdead, pci_vendor_dead, pci_ss_list_dead}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xdeaf, pci_vendor_deaf, pci_ss_list_deaf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe000, pci_vendor_e000, pci_ss_list_e000}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe159, pci_vendor_e159, pci_ss_list_e159}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe4bf, pci_vendor_e4bf, pci_ss_list_e4bf}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xe55e, pci_vendor_e55e, pci_ss_list_e55e}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xea01, pci_vendor_ea01, pci_ss_list_ea01}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xea60, pci_vendor_ea60, pci_ss_list_ea60}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xeabb, pci_vendor_eabb, pci_ss_list_eabb}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xeace, pci_vendor_eace, pci_ss_list_eace}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xec80, pci_vendor_ec80, pci_ss_list_ec80}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xecc0, pci_vendor_ecc0, pci_ss_list_ecc0}, +#endif + {0xedd8, pci_vendor_edd8, pci_ss_list_edd8}, +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xf1d0, pci_vendor_f1d0, pci_ss_list_f1d0}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfa57, pci_vendor_fa57, pci_ss_list_fa57}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfab7, pci_vendor_fab7, pci_ss_list_fab7}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfebd, pci_vendor_febd, pci_ss_list_febd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfeda, pci_vendor_feda, pci_ss_list_feda}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfede, pci_vendor_fede, pci_ss_list_fede}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfffd, pci_vendor_fffd, pci_ss_list_fffd}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xfffe, pci_vendor_fffe, pci_ss_list_fffe}, +#endif +#ifdef VENDOR_INCLUDE_NONVIDEO + {0xffff, pci_vendor_ffff, pci_ss_list_ffff}, +#endif + {0x0000, NULL, NULL} +}; +#endif diff --git a/hw/xfree86/utils/xorgcfg/Makefile.am b/hw/xfree86/utils/xorgcfg/Makefile.am index 73e4042ae..309ed5c0a 100644 --- a/hw/xfree86/utils/xorgcfg/Makefile.am +++ b/hw/xfree86/utils/xorgcfg/Makefile.am @@ -56,6 +56,7 @@ endif if NEED_STRLCAT STRL_SRCS = $(top_srcdir)/os/strlcat.c $(top_srcdir)/os/strlcpy.c endif +endif BUILD_XORGCFG xorgcfg_SOURCES = \ accessx.c \ @@ -95,10 +96,7 @@ xorgcfg_SOURCES = \ xf86config.h \ $(STRL_SRCS) -XBMdir = $(includedir)/X11/bitmaps -XPMdir = $(includedir)/X11/pixmaps - -XBM_DATA = \ +BITMAPS = \ card.xbm \ keyboard.xbm \ monitor.xbm \ @@ -112,7 +110,7 @@ XBM_DATA = \ shorter.xbm \ taller.xbm -XPM_DATA = \ +PIXMAPS = \ card.xpm \ computer.xpm \ keyboard.xpm \ @@ -122,6 +120,13 @@ XPM_DATA = \ # Rules needed to cpp man page & app-defaults include $(top_srcdir)/cpprules.in +if BUILD_XORGCFG +XBMdir = $(includedir)/X11/bitmaps +XPMdir = $(includedir)/X11/pixmaps + +XBM_DATA = $(BITMAPS) +XPM_DATA = $(PIXMAPS) + # App default files (*.ad) appdefaultdir = @APPDEFAULTDIR@ @@ -146,7 +151,6 @@ appman_DATA = $(appman_PRE:man=@APP_MAN_SUFFIX@) all-local: $(appman_PRE) $(appman_DATA) -EXTRA_DIST = $(XBM_DATA) $(XPM_DATA) XOrgCfg.pre xorgcfg.man.pre BUILT_SOURCES = $(appman_PRE) CLEANFILES = $(APPDEFAULTFILES) $(BUILT_SOURCES) $(appman_DATA) @@ -156,4 +160,6 @@ SUFFIXES += .$(APP_MAN_SUFFIX) .man -rm -f $@ $(LN_S) $< $@ -endif +endif BUILD_XORGCFG + +EXTRA_DIST = $(BITMAPS) $(PIXMAPS) XOrgCfg.pre xorgcfg.man.pre diff --git a/hw/xfree86/utils/xorgcfg/text-mode.c b/hw/xfree86/utils/xorgcfg/text-mode.c index 10f4b698f..0fc5770ca 100644 --- a/hw/xfree86/utils/xorgcfg/text-mode.c +++ b/hw/xfree86/utils/xorgcfg/text-mode.c @@ -1128,6 +1128,7 @@ CardConfig(void) static char *xdrivers[] = { "apm", "ark", + "ast", "ati", "r128", "radeon", diff --git a/hw/xfree86/utils/xorgconfig/Cards b/hw/xfree86/utils/xorgconfig/Cards index bf30eab1d..b95928c37 100644 --- a/hw/xfree86/utils/xorgconfig/Cards +++ b/hw/xfree86/utils/xorgconfig/Cards @@ -51,6 +51,11 @@ NAME ** Ark Logic (generic) [ark] SERVER SVGA DRIVER ark +NAME ** ASPEED Technology (generic) [ast] +#CHIPSET ast +SERVER SVGA +DRIVER ast + NAME ** ATI (generic) [ati] #CHIPSET ati SERVER SVGA diff --git a/hw/xfree86/xorgconf.cpp b/hw/xfree86/xorgconf.cpp index c94c1e5a4..6c522134e 100644 --- a/hw/xfree86/xorgconf.cpp +++ b/hw/xfree86/xorgconf.cpp @@ -54,12 +54,9 @@ XCOMM command (or a combination of both methods) FontPath LOCALFONTPATH FontPath MISCFONTPATH - FontPath DPI75USFONTPATH - FontPath DPI100USFONTPATH FontPath T1FONTPATH - FontPath TRUETYPEFONTPATH + FontPath TRUETYPEFONTPATH FontPath CIDFONTPATH - FontPath SPFONTPATH FontPath DPI75FONTPATH FontPath DPI100FONTPATH diff --git a/hw/xnest/Makefile.am b/hw/xnest/Makefile.am index b237788bc..d40d122f4 100644 --- a/hw/xnest/Makefile.am +++ b/hw/xnest/Makefile.am @@ -51,7 +51,7 @@ Xnest_LDFLAGS = AM_CFLAGS = -DHAVE_XNEST_CONFIG_H \ -DNO_HW_ONLY_EXTS \ - \ + $(DIX_CFLAGS) \ $(XNESTMODULES_CFLAGS) EXTRA_DIST = os2Stub.c \ diff --git a/hw/xprint/config/C/print/models/PS2PDFspooldir-GS/Makefile.am b/hw/xprint/config/C/print/models/PS2PDFspooldir-GS/Makefile.am index 37b57d7bb..2b73b9dad 100644 --- a/hw/xprint/config/C/print/models/PS2PDFspooldir-GS/Makefile.am +++ b/hw/xprint/config/C/print/models/PS2PDFspooldir-GS/Makefile.am @@ -1,3 +1,4 @@ xpcdir = @xpconfigdir@/C/print/models/PS2PDFspooldir-GS -dist_xpc_DATA = model-config ps2pdf_spooltodir.sh +dist_xpc_DATA = model-config +dist_xpc_SCRIPTS = ps2pdf_spooltodir.sh diff --git a/hw/xprint/config/C/print/models/PSspooldir/Makefile.am b/hw/xprint/config/C/print/models/PSspooldir/Makefile.am index 52313aa23..717cd2c36 100644 --- a/hw/xprint/config/C/print/models/PSspooldir/Makefile.am +++ b/hw/xprint/config/C/print/models/PSspooldir/Makefile.am @@ -1,3 +1,4 @@ xpcdir = @xpconfigdir@/C/print/models/PSspooldir -dist_xpc_DATA = model-config spooltodir.sh +dist_xpc_DATA = model-config +dist_xpc_SCRIPTS = spooltodir.sh diff --git a/hw/xprint/config/Makefile.am b/hw/xprint/config/Makefile.am index a5ea214c4..197d19de0 100644 --- a/hw/xprint/config/Makefile.am +++ b/hw/xprint/config/Makefile.am @@ -709,4 +709,4 @@ install-data-local: remove-links uninstall-hook: remove-links -EXTRA_DIST = README +dist_xpconfig_DATA = README diff --git a/hw/xprint/doc/Xprt.html b/hw/xprint/doc/Xprt.html index f84a3c134..2aa0c9e3c 100644 --- a/hw/xprint/doc/Xprt.html +++ b/hw/xprint/doc/Xprt.html @@ -4,7 +4,7 @@ applications to use devices like printers, FAX or create documents in formats like PostScript, PCL or PDF. It may be used by clients such as mozilla. -

Xprint is a very flexible, extensible, scaleable, client/server +

Xprint is a very flexible, extensible, scalable, client/server print system based on ISO 10175 (and some other specs) and the X11 rendering protocol. Using Xprint an application can search, query and use devices like @@ -44,11 +44,11 @@ font databases.

-pn

permits the server to continue running if it fails to establish all of its well-known sockets (connection points for clients), but establishes at least - one.

-XpFile file

Sets an altername Xprinters file (see section FILES).

-XpSpoolerType spoolername

+ one.

-XpFile file

Sets an alternate Xprinters file (see section FILES).

-XpSpoolerType spoolername

Defines the spooler system to be used for print job spooling. Supported values in xprint.mozdev.org release 009 are:

aix
aix4
bsd
osf
solaris
sysv
uxp
cups
lprng
other
none

- (multiple values can be specified, seperated by ':', the first active spooler will be chosen). + (multiple values can be specified, separated by ':', the first active spooler will be chosen). The default value is platform-specific and can be obtained via 

Xprt -h

.

ENVIRONMENT

diff --git a/hw/xprint/doc/Xprt.man.pre b/hw/xprint/doc/Xprt.man.pre index 7599a1344..837619cb2 100644 --- a/hw/xprint/doc/Xprt.man.pre +++ b/hw/xprint/doc/Xprt.man.pre @@ -20,7 +20,7 @@ applications to use devices like printers, FAX or create documents in formats like PostScript, PCL or PDF. It may be used by clients such as mozilla. .PP -Xprint is a very flexible, extensible, scaleable, client/server +Xprint is a very flexible, extensible, scalable, client/server print system based on ISO 10175 (and some other specs) and the X11 rendering protocol. Using Xprint an application can search, query and use devices like @@ -85,7 +85,7 @@ points for clients), but establishes at least one. .TP \fB\-XpFile \fIfile\fB\fR -Sets an altername Xprinters file (see section FILES). +Sets an alternate Xprinters file (see section FILES). .TP \fB\-XpSpoolerType \fIspoolername\fB\fR Defines the spooler system to be used for print job spooling. @@ -113,7 +113,7 @@ other none -(multiple values can be specified, seperated by ':', the first active spooler will be chosen). +(multiple values can be specified, separated by ':', the first active spooler will be chosen). The default value is platform-specific and can be obtained via .nf diff --git a/hw/xprint/doc/Xprt.sgml b/hw/xprint/doc/Xprt.sgml index 0ffa39fcb..a62499263 100644 --- a/hw/xprint/doc/Xprt.sgml +++ b/hw/xprint/doc/Xprt.sgml @@ -55,7 +55,7 @@ HTML generation can be done like this: clients such as mozilla. - Xprint is a very flexible, extensible, scaleable, client/server + Xprint is a very flexible, extensible, scalable, client/server print system based on ISO 10175 (and some other specs) and the X11 rendering protocol. Using Xprint an application can search, query and use devices like @@ -155,7 +155,7 @@ HTML generation can be done like this: - Sets an altername Xprinters file (see section FILES). + Sets an alternate Xprinters file (see section FILES). @@ -178,7 +178,7 @@ HTML generation can be done like this: other none - (multiple values can be specified, seperated by ':', the first active spooler will be chosen). + (multiple values can be specified, separated by ':', the first active spooler will be chosen). The default value is platform-specific and can be obtained via Xprt -h. diff --git a/hw/xprint/etc/Xsession.d/cde_xsessiond_xprint.sh b/hw/xprint/etc/Xsession.d/92xprint-xpserverlist similarity index 65% rename from hw/xprint/etc/Xsession.d/cde_xsessiond_xprint.sh rename to hw/xprint/etc/Xsession.d/92xprint-xpserverlist index 3fb6bba7c..60d964a34 100644 --- a/hw/xprint/etc/Xsession.d/cde_xsessiond_xprint.sh +++ b/hw/xprint/etc/Xsession.d/92xprint-xpserverlist @@ -1,19 +1,19 @@ #!/bin/sh ##################################################################### -### File: 0018.xprint +### File: 92xprint-xpserverlist ### -### Default Location: /usr/dt/config/Xsession.d/ +### Default Location: /etc/X11/Xsession.d/ ### ### Purpose: Setup Xprint env vars ### ### Description: This script is invoked by means of the Xsession file ### at user login. ### -### Invoked by: /usr/dt/bin/Xsession +### Invoked by: /etc/X11/Xsession ### ### (c) Copyright 2003-2004 Roland Mainz ### -### please send bugfixes or comments to http://xprint.mozdev.org/ +### please send bugfixes or comments to https://bugs.freedesktop.org ### ##################################################################### @@ -22,8 +22,8 @@ # Obtain list of Xprint servers # -if [ -f "/etc/init.d/xprint" ] ; then - XPSERVERLIST="`/bin/sh /etc/init.d/xprint get_xpserverlist`" +if [ -x "/etc/init.d/xprint" ] ; then + XPSERVERLIST="`/etc/init.d/xprint get_xpserverlist`" export XPSERVERLIST fi diff --git a/hw/xprint/etc/Xsession.d/Makefile.am b/hw/xprint/etc/Xsession.d/Makefile.am index e0277d9d4..96a5ee73b 100644 --- a/hw/xprint/etc/Xsession.d/Makefile.am +++ b/hw/xprint/etc/Xsession.d/Makefile.am @@ -1 +1,2 @@ -EXTRA_DIST = cde_xsessiond_xprint.sh +xpcdir = $(sysconfdir)/X11/Xsession.d +dist_xpc_DATA = 92xprint-xpserverlist diff --git a/include/dix-config.h.in b/include/dix-config.h.in index 69dc674a9..65c42e6af 100644 --- a/include/dix-config.h.in +++ b/include/dix-config.h.in @@ -112,6 +112,9 @@ /* Define to 1 if you have the `geteuid' function. */ #undef HAVE_GETEUID +/* Define to 1 if you have the `getisax' function. */ +#undef HAVE_GETISAX + /* Define to 1 if you have the `getopt' function. */ #undef HAVE_GETOPT @@ -308,6 +311,9 @@ /* unaligned word accesses behave as expected */ #undef WORKING_UNALIGNED_INT +/* Build X-ACE extension */ +#undef XACE + /* Support XCMisc extension */ #undef XCMISC diff --git a/include/dix.h b/include/dix.h index 99f77f404..f346b43a2 100644 --- a/include/dix.h +++ b/include/dix.h @@ -87,12 +87,9 @@ SOFTWARE. ((client->lastDrawableID == did) ? \ client->lastDrawable : (DrawablePtr)LookupDrawable(did, client)) -#ifdef XCSECURITY +#ifdef XACE #define SECURITY_VERIFY_DRAWABLE(pDraw, did, client, mode)\ - if (client->lastDrawableID == did && !client->trustLevel)\ - pDraw = client->lastDrawable;\ - else \ {\ pDraw = (DrawablePtr) SecurityLookupIDByClass(client, did, \ RC_DRAWABLE, mode);\ @@ -106,9 +103,6 @@ SOFTWARE. } #define SECURITY_VERIFY_GEOMETRABLE(pDraw, did, client, mode)\ - if (client->lastDrawableID == did && !client->trustLevel)\ - pDraw = client->lastDrawable;\ - else \ {\ pDraw = (DrawablePtr) SecurityLookupIDByClass(client, did, \ RC_DRAWABLE, mode);\ @@ -120,9 +114,6 @@ SOFTWARE. } #define SECURITY_VERIFY_GC(pGC, rid, client, mode)\ - if (client->lastGCID == rid && !client->trustLevel)\ - pGC = client->lastGC;\ - else\ pGC = (GC *) SecurityLookupIDByType(client, rid, RT_GC, mode);\ if (!pGC)\ {\ @@ -139,7 +130,7 @@ SOFTWARE. #define VERIFY_GC(pGC, rid, client)\ SECURITY_VERIFY_GC(pGC, rid, client, SecurityUnknownAccess) -#else /* not XCSECURITY */ +#else /* not XACE */ #define VERIFY_DRAWABLE(pDraw, did, client)\ if (client->lastDrawableID == did)\ @@ -189,7 +180,7 @@ SOFTWARE. #define SECURITY_VERIFY_GC(pGC, rid, client, mode)\ VERIFY_GC(pGC, rid, client) -#endif /* XCSECURITY */ +#endif /* XACE */ /* * We think that most hardware implementations of DBE will want @@ -384,7 +375,7 @@ extern int CompareISOLatin1Lowered( unsigned char * /*b*/, int blen); -#ifdef XCSECURITY +#ifdef XACE extern WindowPtr SecurityLookupWindow( XID /*rid*/, @@ -420,7 +411,7 @@ extern pointer LookupDrawable( #define SecurityLookupDrawable(rid, client, access_mode) \ LookupDrawable(rid, client) -#endif /* XCSECURITY */ +#endif /* XACE */ extern ClientPtr LookupClient( XID /*rid*/, diff --git a/include/dixstruct.h b/include/dixstruct.h index 9645a9be3..b5ffcca49 100644 --- a/include/dixstruct.h +++ b/include/dixstruct.h @@ -128,16 +128,6 @@ typedef struct _Client { int requestLogIndex; #endif unsigned long replyBytesRemaining; -#ifdef XCSECURITY - XID authId; - unsigned int trustLevel; - pointer (* CheckAccess)( - ClientPtr /*pClient*/, - XID /*id*/, - RESTYPE /*classes*/, - Mask /*access_mode*/, - pointer /*resourceval*/); -#endif #ifdef XAPPGROUP struct _AppGroupRec* appgroup; #endif diff --git a/include/extension.h b/include/extension.h index 6e6081740..74975c50b 100644 --- a/include/extension.h +++ b/include/extension.h @@ -58,6 +58,14 @@ extern Bool EnableDisableExtension(char *name, Bool enable); extern void EnableDisableExtensionError(char *name, Bool enable); +extern void ResetExtensionPrivates(void); + +extern int AllocateExtensionPrivateIndex(void); + +extern Bool AllocateExtensionPrivate( + int /*index*/, + unsigned /*amount*/); + extern void InitExtensions(int argc, char **argv); extern void InitVisualWrap(void); diff --git a/include/extnsionst.h b/include/extnsionst.h index 8873f0cf9..38d4bd7d9 100644 --- a/include/extnsionst.h +++ b/include/extnsionst.h @@ -48,6 +48,7 @@ SOFTWARE. #ifndef EXTENSIONSTRUCT_H #define EXTENSIONSTRUCT_H +#include "dix.h" #include "misc.h" #include "screenint.h" #include "extension.h" @@ -68,9 +69,7 @@ typedef struct _ExtensionEntry { pointer extPrivate; unsigned short (* MinorOpcode)( /* called for errors */ ClientPtr /* client */); -#ifdef XCSECURITY - Bool secure; /* extension visible to untrusted clients? */ -#endif + DevUnion *devPrivates; } ExtensionEntry; /* @@ -127,6 +126,7 @@ extern Bool AddExtensionAlias( ExtensionEntry * /*extension*/); extern ExtensionEntry *CheckExtension(const char *extname); +extern ExtensionEntry *GetExtensionEntry(int major); extern ExtensionLookupProc LookupProc( char* /*name*/, diff --git a/include/resource.h b/include/resource.h index f513141c0..fd0caaeb5 100644 --- a/include/resource.h +++ b/include/resource.h @@ -225,8 +225,6 @@ extern pointer LookupClientResourceComplex( #define SecurityWriteAccess (1<<1) /* changing the object */ #define SecurityDestroyAccess (1<<2) /* destroying the object */ -#ifdef XCSECURITY - extern pointer SecurityLookupIDByType( ClientPtr /*client*/, XID /*id*/, @@ -239,15 +237,6 @@ extern pointer SecurityLookupIDByClass( RESTYPE /*classes*/, Mask /*access_mode*/); -#else /* not XCSECURITY */ - -#define SecurityLookupIDByType(client, id, rtype, access_mode) \ - LookupIDByType(id, rtype) - -#define SecurityLookupIDByClass(client, id, classes, access_mode) \ - LookupIDByClass(id, classes) - -#endif /* XCSECURITY */ extern void GetXIDRange( int /*client*/, diff --git a/mi/mieq.c b/mi/mieq.c index a7c6f9a51..a69ce7037 100644 --- a/mi/mieq.c +++ b/mi/mieq.c @@ -32,6 +32,10 @@ in this Software without prior written authorization from The Open Group. * */ +#if HAVE_DIX_CONFIG_H +#include +#endif + # define NEED_EVENTS # include # include diff --git a/mi/miinitext.c b/mi/miinitext.c index 80bacaa7a..aafd014ae 100644 --- a/mi/miinitext.c +++ b/mi/miinitext.c @@ -241,6 +241,9 @@ typedef void (*InitExtension)(INITARGS); #define _XAG_SERVER_ #include #endif +#ifdef XACE +#include "xace.h" +#endif #ifdef XCSECURITY #include "securitysrv.h" #include @@ -311,7 +314,11 @@ extern void DbeExtensionInit(INITARGS); #ifdef XAPPGROUP extern void XagExtensionInit(INITARGS); #endif +#ifdef XACE +extern void XaceExtensionInit(INITARGS); +#endif #ifdef XCSECURITY +extern void SecurityExtensionSetup(INITARGS); extern void SecurityExtensionInit(INITARGS); #endif #ifdef XPRINT @@ -522,6 +529,9 @@ InitExtensions(argc, argv) int argc; char *argv[]; { +#ifdef XCSECURITY + SecurityExtensionSetup(); +#endif #ifdef PANORAMIX # if !defined(PRINT_ONLY_SERVER) && !defined(NO_PANORAMIX) if (!noPanoramiXExtension) PanoramiXExtensionInit(); @@ -584,6 +594,9 @@ InitExtensions(argc, argv) #ifdef XAPPGROUP if (!noXagExtension) XagExtensionInit(); #endif +#ifdef XACE + XaceExtensionInit(); +#endif #ifdef XCSECURITY if (!noSecurityExtension) SecurityExtensionInit(); #endif @@ -686,8 +699,11 @@ static ExtensionModule staticExtensions[] = { #ifdef XAPPGROUP { XagExtensionInit, XAGNAME, &noXagExtension, NULL, NULL }, #endif +#ifdef XACE + { XaceExtensionInit, XACE_EXTENSION_NAME, NULL, NULL, NULL }, +#endif #ifdef XCSECURITY - { SecurityExtensionInit, SECURITY_EXTENSION_NAME, &noSecurityExtension, NULL, NULL }, + { SecurityExtensionInit, SECURITY_EXTENSION_NAME, &noSecurityExtension, SecurityExtensionSetup, NULL }, #endif #ifdef XPRINT { XpExtensionInit, XP_PRINTNAME, NULL, NULL, NULL }, diff --git a/os/access.c b/os/access.c index 69e305182..cdb17589c 100644 --- a/os/access.c +++ b/os/access.c @@ -202,8 +202,8 @@ SOFTWARE. #include "dixstruct.h" #include "osdep.h" -#ifdef XCSECURITY -#include "securitysrv.h" +#ifdef XACE +#include "xace.h" #endif #ifndef PATH_MAX @@ -1386,15 +1386,6 @@ _X_EXPORT Bool LocalClient(ClientPtr client) pointer addr; register HOST *host; -#ifdef XCSECURITY - /* untrusted clients can't change host access */ - if (client->trustLevel != XSecurityClientTrusted) - { - SecurityAudit("client %d attempted to change host access\n", - client->index); - return FALSE; - } -#endif if (!_XSERVTransGetPeerAddr (((OsCommPtr)client->osPrivate)->trans_conn, ¬used, &alen, &from)) { @@ -1537,6 +1528,11 @@ AuthorizedClient(ClientPtr client) { if (!client || defeatAccessControl) return TRUE; +#ifdef XACE + /* untrusted clients can't change host access */ + if (!XaceHook(XACE_HOSTLIST_ACCESS, client, SecurityWriteAccess)) + return FALSE; +#endif return LocalClient(client); } diff --git a/os/connection.c b/os/connection.c index b64cda196..571ba58ab 100644 --- a/os/connection.c +++ b/os/connection.c @@ -148,6 +148,9 @@ extern __const__ int _nfiles; #ifdef XAPPGROUP #include "appgroup.h" #endif +#ifdef XACE +#include "xace.h" +#endif #ifdef XCSECURITY #include "securitysrv.h" #endif @@ -690,9 +693,8 @@ ClientAuthorized(ClientPtr client, /* indicate to Xdmcp protocol that we've opened new client */ XdmcpOpenDisplay(priv->fd); #endif /* XDMCP */ -#ifdef XAPPGROUP - if (ClientStateCallback) - XagCallClientStateChange (client); +#ifdef XACE + XaceHook(XACE_AUTH_AVAIL, client, auth_id); #endif /* At this point, if the client is authorized to change the access control * list, we should getpeername() information, and add the client to diff --git a/render/picture.c b/render/picture.c index 566d91e09..a3443c20e 100644 --- a/render/picture.c +++ b/render/picture.c @@ -1459,18 +1459,25 @@ SetPictureClipRegion (PicturePtr pPicture, return result; } +static Bool +transformIsIdentity(PictTransform *t) +{ + return ((t->matrix[0][0] == t->matrix[1][1]) && + (t->matrix[0][0] == t->matrix[2][2]) && + (t->matrix[0][0] != 0) && + (t->matrix[0][1] == 0) && + (t->matrix[0][2] == 0) && + (t->matrix[1][0] == 0) && + (t->matrix[1][2] == 0) && + (t->matrix[2][0] == 0) && + (t->matrix[2][1] == 0)); +} int SetPictureTransform (PicturePtr pPicture, PictTransform *transform) { - static const PictTransform identity = { { - { xFixed1, 0x00000, 0x00000 }, - { 0x00000, xFixed1, 0x00000 }, - { 0x00000, 0x00000, xFixed1 }, - } }; - - if (transform && memcmp (transform, &identity, sizeof (PictTransform)) == 0) + if (transform && transformIsIdentity (transform)) transform = 0; if (transform) diff --git a/xkb/ddxList.c b/xkb/ddxList.c index f94a869ae..034f694ed 100644 --- a/xkb/ddxList.c +++ b/xkb/ddxList.c @@ -269,7 +269,7 @@ char tmpname[PATH_MAX]; #ifndef WIN32 if (haveDir) fclose(in); - else if ((rval=pclose(in))!=0) { + else if ((rval=Pclose(in))!=0) { if (xkbDebugFlags) ErrorF("xkbcomp returned exit code %d\n",rval); } diff --git a/xkb/xkbUtils.c b/xkb/xkbUtils.c index ee0abbeae..26ff35e89 100644 --- a/xkb/xkbUtils.c +++ b/xkb/xkbUtils.c @@ -754,12 +754,12 @@ unsigned char grp; grp= state->locked_group; - if (grp>=ctrls->num_groups || grp < 0) - state->locked_group= XkbAdjustGroup(grp,ctrls); + if (grp>=ctrls->num_groups) + state->locked_group= XkbAdjustGroup(XkbCharToInt(grp),ctrls); grp= state->locked_group+state->base_group+state->latched_group; - if (grp>=ctrls->num_groups || grp < 0) - state->group= XkbAdjustGroup(grp,ctrls); + if (grp>=ctrls->num_groups) + state->group= XkbAdjustGroup(XkbCharToInt(grp),ctrls); else state->group= grp; XkbComputeCompatState(xkbi); return;