1038 lines
26 KiB
C
1038 lines
26 KiB
C
/*
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* Copyright © 2004 Eric Anholt
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that
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* copyright notice and this permission notice appear in supporting
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* documentation, and that the name of Eric Anholt not be used in
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* advertising or publicity pertaining to distribution of the software without
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* specific, written prior permission. Eric Anholt makes no
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* representations about the suitability of this software for any purpose. It
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* is provided "as is" without express or implied warranty.
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*
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* ERIC ANHOLT DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
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* EVENT SHALL ERIC ANHOLT BE LIABLE FOR ANY SPECIAL, INDIRECT OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <sys/time.h>
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#include "ati.h"
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#include "ati_reg.h"
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#include "ati_dma.h"
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#include "ati_draw.h"
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#ifdef USE_DRI
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#include "radeon_common.h"
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#include "r128_common.h"
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#include "ati_sarea.h"
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#endif /* USE_DRI */
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#include "agp.h"
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#define DEBUG_FIFO 0
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extern CARD32 r128_cce_microcode[];
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extern CARD32 radeon_cp_microcode[][2];
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extern CARD32 r200_cp_microcode[][2];
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extern CARD32 r300_cp_microcode[][2];
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#if DEBUG_FIFO
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static void
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ATIDebugFifo(ATIScreenInfo *atis)
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{
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ATICardInfo *atic = atis->atic;
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char *mmio = atic->reg_base;
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if (atic->is_radeon) {
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ErrorF("RADEON_REG_CP_CSQ_CNTL: 0x%08x\n",
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MMIO_IN32(mmio, RADEON_REG_CP_CSQ_CNTL));
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ErrorF("RADEON_REG_CP_CSQ_STAT: 0x%08x\n",
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MMIO_IN32(mmio, RADEON_REG_CP_CSQ_STAT));
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ErrorF("RADEON_REG_RBBM_STATUS: 0x%08x\n",
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MMIO_IN32(mmio, RADEON_REG_RBBM_STATUS));
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ErrorF("RADEON_REG_RB3D_DSTCACHE_CTLSTAT: 0x%08x\n",
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MMIO_IN32(mmio, RADEON_REG_RB3D_DSTCACHE_CTLSTAT));
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} else {
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ErrorF("R128_REG_PM4_BUFFER_CNTL: 0x%08x\n",
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MMIO_IN32(mmio, R128_REG_PM4_BUFFER_CNTL));
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ErrorF("R128_REG_PM4_STAT: 0x%08x\n",
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MMIO_IN32(mmio, R128_REG_PM4_STAT));
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ErrorF("R128_REG_GUI_STAT: 0x%08x\n",
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MMIO_IN32(mmio, R128_REG_GUI_STAT));
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ErrorF("R128_REG_PC_NGUI_CTLSTAT: 0x%08x\n",
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MMIO_IN32(mmio, R128_REG_PC_NGUI_CTLSTAT));
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}
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}
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#endif
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static void
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ATIUploadMicrocode(ATIScreenInfo *atis)
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{
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ATICardInfo *atic = atis->atic;
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char *mmio = atic->reg_base;
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int i;
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MMIO_OUT32(mmio, ATI_REG_MICROCODE_RAM_ADDR, 0);
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if (atic->is_radeon && atic->is_r300) {
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for (i = 0; i < 256; i++) {
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MMIO_OUT32(mmio, ATI_REG_MICROCODE_RAM_DATAH,
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r300_cp_microcode[i][1]);
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MMIO_OUT32(mmio, ATI_REG_MICROCODE_RAM_DATAL,
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r300_cp_microcode[i][0]);
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}
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} else if (atic->is_radeon && atic->is_r200) {
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for (i = 0; i < 256; i++) {
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MMIO_OUT32(mmio, ATI_REG_MICROCODE_RAM_DATAH,
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r200_cp_microcode[i][1]);
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MMIO_OUT32(mmio, ATI_REG_MICROCODE_RAM_DATAL,
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r200_cp_microcode[i][0]);
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}
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} else if (atic->is_radeon && atic->is_r100) {
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for (i = 0; i < 256; i++) {
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MMIO_OUT32(mmio, ATI_REG_MICROCODE_RAM_DATAH,
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radeon_cp_microcode[i][1]);
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MMIO_OUT32(mmio, ATI_REG_MICROCODE_RAM_DATAL,
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radeon_cp_microcode[i][0]);
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}
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} else {
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for (i = 0; i < 256; i++) {
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MMIO_OUT32(mmio, ATI_REG_MICROCODE_RAM_DATAH,
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r128_cce_microcode[i * 2]);
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MMIO_OUT32(mmio, ATI_REG_MICROCODE_RAM_DATAL,
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r128_cce_microcode[i * 2 + 1]);
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}
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}
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}
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/* Required when reading from video memory after acceleration to make sure all
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* data has been flushed to video memory from the pixel cache.
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*/
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static void
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ATIFlushPixelCache(ATIScreenInfo *atis)
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{
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ATICardInfo *atic = atis->atic;
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char *mmio = atic->reg_base;
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CARD32 temp;
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TIMEOUT_LOCALS;
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if (atic->is_radeon) {
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temp = MMIO_IN32(mmio, RADEON_REG_RB3D_DSTCACHE_CTLSTAT);
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temp |= RADEON_RB3D_DC_FLUSH_ALL;
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MMIO_OUT32(mmio, RADEON_REG_RB3D_DSTCACHE_CTLSTAT, temp);
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WHILE_NOT_TIMEOUT(.2) {
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if ((MMIO_IN32(mmio, RADEON_REG_RB3D_DSTCACHE_CTLSTAT) &
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RADEON_RB3D_DC_BUSY) == 0)
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break;
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}
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} else {
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temp = MMIO_IN32(mmio, R128_REG_PC_NGUI_CTLSTAT);
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temp |= R128_PC_FLUSH_ALL;
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MMIO_OUT32(mmio, R128_REG_PC_NGUI_CTLSTAT, temp);
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WHILE_NOT_TIMEOUT(.2) {
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if ((MMIO_IN32(mmio, R128_REG_PC_NGUI_CTLSTAT) &
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R128_PC_BUSY) != R128_PC_BUSY)
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break;
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}
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}
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if (TIMEDOUT())
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ErrorF("Timeout flushing pixel cache.\n");
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}
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static void
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ATIEngineReset(ATIScreenInfo *atis)
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{
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ATICardInfo *atic = atis->atic;
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char *mmio = atic->reg_base;
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CARD32 clockcntlindex, mclkcntl;
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#if DEBUG_FIFO
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ErrorF("Engine Reset!\n");
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ATIDebugFifo(atis);
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#endif
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ATIFlushPixelCache(atis);
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clockcntlindex = MMIO_IN32(mmio, ATI_REG_CLOCK_CNTL_INDEX);
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if (atic->is_r300)
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R300CGWorkaround(atis);
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if (atic->is_radeon) {
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CARD32 host_path_cntl;
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mclkcntl = INPLL(mmio, RADEON_REG_MCLK_CNTL);
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OUTPLL(mmio, RADEON_REG_MCLK_CNTL, mclkcntl |
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RADEON_FORCEON_MCLKA |
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RADEON_FORCEON_MCLKB |
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RADEON_FORCEON_YCLKA |
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RADEON_FORCEON_YCLKB |
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RADEON_FORCEON_MC |
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RADEON_FORCEON_AIC);
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host_path_cntl = MMIO_IN32(mmio, RADEON_REG_HOST_PATH_CNTL);
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if (atic->is_r300) {
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MMIO_OUT32(mmio, RADEON_REG_RBBM_SOFT_RESET,
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RADEON_SOFT_RESET_CP |
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RADEON_SOFT_RESET_HI |
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RADEON_SOFT_RESET_E2);
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} else {
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MMIO_OUT32(mmio, RADEON_REG_RBBM_SOFT_RESET,
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RADEON_SOFT_RESET_CP |
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RADEON_SOFT_RESET_SE |
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RADEON_SOFT_RESET_RE |
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RADEON_SOFT_RESET_PP |
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RADEON_SOFT_RESET_E2 |
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RADEON_SOFT_RESET_RB);
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}
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MMIO_IN32(mmio, RADEON_REG_RBBM_SOFT_RESET);
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MMIO_OUT32(mmio, RADEON_REG_RBBM_SOFT_RESET, 0);
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MMIO_OUT32(mmio, RADEON_REG_HOST_PATH_CNTL, host_path_cntl |
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RADEON_HDP_SOFT_RESET);
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MMIO_IN32(mmio, RADEON_REG_HOST_PATH_CNTL);
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MMIO_OUT32(mmio, RADEON_REG_HOST_PATH_CNTL, host_path_cntl);
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MMIO_OUT32(mmio, ATI_REG_CLOCK_CNTL_INDEX, clockcntlindex);
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OUTPLL(mmio, RADEON_REG_MCLK_CNTL, mclkcntl);
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if (atic->is_r300)
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R300CGWorkaround(atis);
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} else {
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CARD32 temp;
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mclkcntl = INPLL(mmio, R128_REG_MCLK_CNTL);
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OUTPLL(mmio, R128_REG_MCLK_CNTL,
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mclkcntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP);
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temp = MMIO_IN32(mmio, R128_REG_GEN_RESET_CNTL);
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MMIO_OUT32(mmio, R128_REG_GEN_RESET_CNTL,
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temp | R128_SOFT_RESET_GUI);
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temp = MMIO_IN32(mmio, R128_REG_GEN_RESET_CNTL);
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MMIO_OUT32(mmio, R128_REG_GEN_RESET_CNTL,
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temp & ~R128_SOFT_RESET_GUI);
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temp = MMIO_IN32(mmio, R128_REG_GEN_RESET_CNTL);
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OUTPLL(mmio, R128_REG_MCLK_CNTL, mclkcntl);
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MMIO_OUT32(mmio, ATI_REG_CLOCK_CNTL_INDEX, clockcntlindex);
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}
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#ifdef USE_DRI
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if (atis->using_dri) {
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ATIDRIDMAReset(atis);
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ATIDRIDMAStart(atis);
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}
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#endif
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}
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static void
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ATIWaitAvailMMIO(ATIScreenInfo *atis, int n)
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{
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ATICardInfo *atic = atis->atic;
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char *mmio = atic->reg_base;
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TIMEOUT_LOCALS;
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if (atis->mmio_avail >= n) {
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atis->mmio_avail -= n;
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return;
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}
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if (atic->is_radeon) {
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WHILE_NOT_TIMEOUT(.2) {
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atis->mmio_avail = MMIO_IN32(mmio,
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RADEON_REG_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
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if (atis->mmio_avail >= n)
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break;
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}
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} else {
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WHILE_NOT_TIMEOUT(.2) {
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atis->mmio_avail = MMIO_IN32(mmio, R128_REG_GUI_STAT) &
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0xfff;
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if (atis->mmio_avail >= n)
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break;
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}
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}
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if (TIMEDOUT()) {
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ErrorF("Timeout waiting for %d MMIO slots.\n", n);
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ATIEngineReset(atis);
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ATIDrawSetup(atis->screen->pScreen);
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}
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atis->mmio_avail -= n;
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}
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static int
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ATIGetAvailPrimary(ATIScreenInfo *atis)
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{
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ATICardInfo *atic = atis->atic;
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char *mmio = atic->reg_base;
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if (atic->is_radeon) {
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int csq_stat, diff;
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csq_stat = MMIO_IN32(mmio, RADEON_REG_CP_CSQ_STAT);
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if (atic->is_r200)
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diff = ((csq_stat & R200_CSQ_WPTR_PRIMARY_MASK) >> 9) -
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(csq_stat & R200_CSQ_RPTR_PRIMARY_MASK);
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else
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diff = ((csq_stat & RADEON_CSQ_WPTR_PRIMARY_MASK) >> 8) -
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(csq_stat & RADEON_CSQ_RPTR_PRIMARY_MASK);
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if (diff < 0)
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return -diff;
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else
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return atis->cce_pri_size - diff;
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} else {
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return MMIO_IN32(mmio, R128_REG_PM4_STAT) &
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R128_PM4_FIFOCNT_MASK;
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}
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}
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static void
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ATIWaitAvailPrimary(ATIScreenInfo *atis, int n)
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{
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TIMEOUT_LOCALS;
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if (atis->cce_pri_avail >= n) {
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atis->cce_pri_avail -= n;
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return;
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}
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WHILE_NOT_TIMEOUT(.2) {
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if (atis->cce_pri_avail >= n)
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break;
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atis->cce_pri_avail = ATIGetAvailPrimary(atis);
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if (atis->cce_pri_avail >= n)
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break;
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}
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if (TIMEDOUT()) {
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ErrorF("Timeout waiting for %d CCE slots (%d avail).\n", n,
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atis->cce_pri_avail);
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ATIEngineReset(atis);
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ATIDrawSetup(atis->screen->pScreen);
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}
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atis->cce_pri_avail -= n;
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}
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void
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ATIWaitIdle(ATIScreenInfo *atis)
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{
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ATICardInfo *atic = atis->atic;
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char *mmio = atic->reg_base;
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TIMEOUT_LOCALS;
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if (atis->indirectBuffer != NULL)
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ATIFlushIndirect(atis, 0);
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#ifdef USE_DRI
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if (atis->using_dri) {
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int ret = 0;
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int cmd = (atic->is_radeon ? DRM_RADEON_CP_IDLE :
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DRM_R128_CCE_IDLE);
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WHILE_NOT_TIMEOUT(2) {
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ret = drmCommandNone(atic->drmFd, cmd);
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if (ret != -EBUSY)
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break;
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}
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if (TIMEDOUT()) {
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ATIDebugFifo(atis);
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FatalError("Timed out idling CCE (card hung)\n");
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}
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if (ret != 0)
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ErrorF("Failed to idle DMA, returned %d\n", ret);
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return;
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}
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#endif
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if (!atic->is_radeon && (atis->using_pseudo || atis->using_dma)) {
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ATIWaitAvailPrimary(atis, atis->cce_pri_size);
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WHILE_NOT_TIMEOUT(.2) {
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if ((MMIO_IN32(mmio, R128_REG_PM4_STAT) &
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(R128_PM4_BUSY | R128_PM4_GUI_ACTIVE)) == 0)
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break;
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}
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if (TIMEDOUT()) {
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ErrorF("Timeout idling CCE, resetting...\n");
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ATIEngineReset(atis);
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ATIDrawSetup(atis->screen->pScreen);
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}
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}
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/* Radeon CP idle is the same as MMIO idle. */
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if (atis->using_pio || atic->is_radeon) {
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/* Empty the fifo */
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ATIWaitAvailMMIO(atis, 64);
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if (atic->is_radeon) {
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WHILE_NOT_TIMEOUT(.2) {
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if ((MMIO_IN32(mmio, RADEON_REG_RBBM_STATUS) &
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RADEON_RBBM_ACTIVE) == 0)
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break;
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}
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} else {
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WHILE_NOT_TIMEOUT(.2) {
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if ((MMIO_IN32(mmio, R128_REG_GUI_STAT) &
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R128_GUI_ACTIVE) == 0)
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break;
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}
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}
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if (TIMEDOUT()) {
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ErrorF("Timeout idling accelerator, resetting...\n");
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ATIEngineReset(atis);
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ATIDrawSetup(atis->screen->pScreen);
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}
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}
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ATIFlushPixelCache(atis);
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#if DEBUG_FIFO
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ErrorF("Idle?\n");
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ATIDebugFifo(atis);
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#endif
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}
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dmaBuf *
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ATIGetDMABuffer(ATIScreenInfo *atis)
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{
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dmaBuf *buf;
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buf = (dmaBuf *)xalloc(sizeof(dmaBuf));
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if (buf == NULL)
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return NULL;
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#ifdef USE_DRI
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if (atis->using_dri) {
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buf->drmBuf = ATIDRIGetBuffer(atis);
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if (buf->drmBuf == NULL) {
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xfree(buf);
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return NULL;
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}
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buf->size = buf->drmBuf->total;
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buf->used = buf->drmBuf->used;
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buf->address = buf->drmBuf->address;
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return buf;
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}
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#endif /* USE_DRI */
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if (atis->using_dma)
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buf->size = atis->ring_len / 2;
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else
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buf->size = 512 * 1024;
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buf->address = xalloc(buf->size);
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if (buf->address == NULL) {
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xfree(buf);
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return NULL;
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}
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buf->used = 0;
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return buf;
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}
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/* Decode a type-3 packet into MMIO register writes. Only some type-3 packets
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* supported, and only partially.
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*/
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static void
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ATIDispatchPacket3MMIO(ATIScreenInfo *atis, CARD32 header, CARD32 *addr,
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int count)
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{
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ATICardInfo *atic = atis->atic;
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char *mmio = atic->reg_base;
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CARD32 settings;
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int i = 0;
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settings = addr[i++];
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if ((settings & ATI_GMC_SRC_PITCH_OFFSET_CNTL) != 0)
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MMIO_OUT32(mmio, ATI_REG_SRC_PITCH_OFFSET, addr[i++]);
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if ((settings & ATI_GMC_DST_PITCH_OFFSET_CNTL) != 0)
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MMIO_OUT32(mmio, ATI_REG_DST_PITCH_OFFSET, addr[i++]);
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if ((settings & ATI_GMC_BRUSH_MASK) == ATI_GMC_BRUSH_SOLID_COLOR)
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MMIO_OUT32(mmio, ATI_REG_DP_BRUSH_FRGD_CLR, addr[i++]);
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switch (header & (ATI_CCE_PACKETTYPE_MASK |
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ATI_CCE_PACKET3_IT_OPCODE_MASK))
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{
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case ATI_CCE_PACKET3_PAINT_MULTI:
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while (i < count) {
|
|
MMIO_OUT32(mmio, ATI_REG_DST_Y_X,
|
|
(addr[i] >> 16) | (addr[i] << 16));
|
|
i++;
|
|
MMIO_OUT32(mmio, ATI_REG_DST_HEIGHT_WIDTH,
|
|
(addr[i] >> 16) | (addr[i] << 16));
|
|
i++;
|
|
}
|
|
break;
|
|
case ATI_CCE_PACKET3_BITBLT_MULTI:
|
|
while (i < count) {
|
|
MMIO_OUT32(mmio, ATI_REG_SRC_Y_X,
|
|
(addr[i] >> 16) | (addr[i] << 16));
|
|
i++;
|
|
MMIO_OUT32(mmio, ATI_REG_DST_Y_X,
|
|
(addr[i] >> 16) | (addr[i] << 16));
|
|
i++;
|
|
MMIO_OUT32(mmio, ATI_REG_DST_HEIGHT_WIDTH,
|
|
(addr[i] >> 16) | (addr[i] << 16));
|
|
i++;
|
|
}
|
|
break;
|
|
default:
|
|
ErrorF("Unsupported packet: 0x%x\n", header);
|
|
}
|
|
}
|
|
|
|
/* Dispatch packets by decoding them and writing to registers. Doesn't support
|
|
* the type 3 packets.
|
|
*/
|
|
static void
|
|
ATIDispatchIndirectMMIO(ATIScreenInfo *atis)
|
|
{
|
|
ATICardInfo *atic = atis->atic;
|
|
dmaBuf *buf = atis->indirectBuffer;
|
|
char *mmio = atic->reg_base;
|
|
CARD32 *addr;
|
|
CARD32 reg;
|
|
int i, n, count;
|
|
|
|
addr = (CARD32 *)((char *)buf->address + atis->indirectStart);
|
|
count = (buf->used - atis->indirectStart) / 4;
|
|
|
|
for (i = 0; i < count; i++) {
|
|
CARD32 header = addr[i];
|
|
|
|
switch (header & ATI_CCE_PACKETTYPE_MASK)
|
|
{
|
|
case ATI_CCE_PACKET0:
|
|
n = ((header & ATI_CCE_PACKET0_COUNT_MASK) >> 16) + 1;
|
|
reg = (header & ATI_CCE_PACKET0_REG_MASK) << 2;
|
|
ATIWaitAvailMMIO(atis, n);
|
|
while (n > 0) {
|
|
i++;
|
|
MMIO_OUT32(mmio, reg, addr[i]);
|
|
if ((header & ATI_CCE_PACKET0_ONE_REG_WR) == 0)
|
|
reg += 4;
|
|
n--;
|
|
}
|
|
break;
|
|
case ATI_CCE_PACKET1:
|
|
reg = (header & ATI_CCE_PACKET1_REG_1) << 2;
|
|
MMIO_OUT32(mmio, reg, addr[++i]);
|
|
reg = ((header & ATI_CCE_PACKET1_REG_2) >>
|
|
ATI_CCE_PACKET1_REG_2_SHIFT) << 2;
|
|
MMIO_OUT32(mmio, reg, addr[++i]);
|
|
break;
|
|
case ATI_CCE_PACKET2:
|
|
/* PACKET2 is a no-op packet. */
|
|
break;
|
|
case ATI_CCE_PACKET3:
|
|
n = ((header & ATI_CCE_PACKET3_COUNT_MASK) >> 16) + 1;
|
|
ATIDispatchPacket3MMIO(atis, header, &addr[i], n);
|
|
i += n;
|
|
break;
|
|
default:
|
|
ErrorF("Unsupported packet: 0x%x\n", addr[i]);
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Dispatch packets by sending them through the MMIO aperture. */
|
|
static void
|
|
R128DispatchIndirectPDMA(ATIScreenInfo *atis)
|
|
{
|
|
ATICardInfo *atic = atis->atic;
|
|
dmaBuf *buf = atis->indirectBuffer;
|
|
char *mmio = atic->reg_base;
|
|
CARD32 *addr;
|
|
int count;
|
|
|
|
addr = (CARD32 *)((char *)buf->address + atis->indirectStart);
|
|
count = (buf->used - atis->indirectStart) / 4;
|
|
|
|
while (count > 1) {
|
|
ATIWaitAvailPrimary(atis, 2);
|
|
MMIO_OUT32(mmio, R128_REG_PM4_FIFO_DATA_EVEN, *addr++);
|
|
MMIO_OUT32(mmio, R128_REG_PM4_FIFO_DATA_ODD, *addr++);
|
|
count -= 2;
|
|
}
|
|
|
|
/* Submit last DWORD if necessary. */
|
|
if (count != 0) {
|
|
ATIWaitAvailPrimary(atis, 2);
|
|
MMIO_OUT32(mmio, R128_REG_PM4_FIFO_DATA_EVEN, *addr++);
|
|
MMIO_OUT32(mmio, R128_REG_PM4_FIFO_DATA_ODD, ATI_CCE_PACKET2);
|
|
}
|
|
}
|
|
|
|
/* Dispatch packets by sending them through the MMIO aperture, using the
|
|
* primary CCE ring. */
|
|
static void
|
|
RadeonDispatchIndirectPDMA(ATIScreenInfo *atis)
|
|
{
|
|
ATICardInfo *atic = atis->atic;
|
|
dmaBuf *buf = atis->indirectBuffer;
|
|
char *mmio = atic->reg_base;
|
|
CARD32 *addr;
|
|
int count, avail, reg, i;
|
|
TIMEOUT_LOCALS;
|
|
|
|
addr = (CARD32 *)((char *)buf->address + atis->indirectStart);
|
|
count = (buf->used - atis->indirectStart) / 4;
|
|
|
|
reg = RADEON_REG_CSQ_APER_PRIMARY;
|
|
WHILE_NOT_TIMEOUT(3) {
|
|
/* 3 seconds is empirical, using render_bench on an r100. */
|
|
if (count <= 0)
|
|
break;
|
|
avail = ATIGetAvailPrimary(atis);
|
|
for (i = 0; i < min(count, avail); i++) {
|
|
MMIO_OUT32(mmio, reg, *addr++);
|
|
if (reg == RADEON_REG_CSQ_APER_PRIMARY_END)
|
|
reg = RADEON_REG_CSQ_APER_PRIMARY;
|
|
else
|
|
reg += 4;
|
|
}
|
|
count -= i;
|
|
}
|
|
if (TIMEDOUT()) {
|
|
ErrorF("Timeout submitting packets, resetting...\n");
|
|
ATIEngineReset(atis);
|
|
ATIDrawSetup(atis->screen->pScreen);
|
|
}
|
|
}
|
|
|
|
|
|
/* Dispatch packets by writing them to the (primary) ring buffer, which happens
|
|
* to be in framebuffer memory.
|
|
*/
|
|
static void
|
|
R128DispatchIndirectDMA(ATIScreenInfo *atis)
|
|
{
|
|
ATICardInfo *atic = atis->atic;
|
|
dmaBuf *buf = atis->indirectBuffer;
|
|
char *mmio = atic->reg_base;
|
|
CARD32 *addr;
|
|
int count, ring_count;
|
|
TIMEOUT_LOCALS;
|
|
|
|
addr = (CARD32 *)((char *)buf->address + atis->indirectStart);
|
|
count = (buf->used - atis->indirectStart) / 4;
|
|
ring_count = atis->ring_len / 4;
|
|
|
|
WHILE_NOT_TIMEOUT(.2) {
|
|
if (count <= 0)
|
|
break;
|
|
|
|
atis->ring_addr[atis->ring_write++] = *addr++;
|
|
if (atis->ring_write >= ring_count)
|
|
atis->ring_write = 0;
|
|
while (atis->ring_write == atis->ring_read) {
|
|
atis->ring_read = MMIO_IN32(mmio, ATI_REG_CCE_RPTR);
|
|
}
|
|
count--;
|
|
}
|
|
if (TIMEDOUT()) {
|
|
ErrorF("Timeout submitting packets, resetting...\n");
|
|
ATIEngineReset(atis);
|
|
ATIDrawSetup(atis->screen->pScreen);
|
|
}
|
|
|
|
/* Workaround for some early Rage 128 ASIC spins where the CCE parser
|
|
* may read up to 32 DWORDS beyond the end of the ring buffer memory
|
|
* before wrapping around, if the ring buffer was empty and a <32 DWORD
|
|
* packet that wraps around the end of the ring buffer is submitted.
|
|
* To work around that, copy the beginning of the ring buffer past the
|
|
* end if that may happen.
|
|
*/
|
|
if (atis->ring_write < 32)
|
|
memcpy(atis->ring_addr + ring_count, atis->ring_addr, 32 * 4);
|
|
|
|
/* Update write pointer */
|
|
MMIO_OUT32(mmio, ATI_REG_CCE_WPTR, atis->ring_write);
|
|
}
|
|
|
|
void
|
|
ATIFlushIndirect(ATIScreenInfo *atis, Bool discard)
|
|
{
|
|
ATICardInfo *atic = atis->atic;
|
|
dmaBuf *buf = atis->indirectBuffer;
|
|
|
|
if ((atis->indirectStart == buf->used) && !discard)
|
|
return;
|
|
|
|
#if DEBUG_FIFO
|
|
ErrorF("Dispatching %d DWORDS\n", (buf->used - atis->indirectStart) /
|
|
4);
|
|
#endif
|
|
|
|
#ifdef USE_DRI
|
|
if (atis->using_dri) {
|
|
buf->drmBuf->used = buf->used;
|
|
ATIDRIDispatchIndirect(atis, discard);
|
|
if (discard) {
|
|
buf->drmBuf = ATIDRIGetBuffer(atis);
|
|
buf->size = buf->drmBuf->total;
|
|
buf->used = buf->drmBuf->used;
|
|
buf->address = buf->drmBuf->address;
|
|
atis->indirectStart = 0;
|
|
} else {
|
|
/* Start on a double word boundary */
|
|
atis->indirectStart = buf->used = (buf->used + 7) & ~7;
|
|
}
|
|
return;
|
|
}
|
|
#endif /* USE_DRI */
|
|
|
|
if (atis->using_dma && !atic->is_radeon)
|
|
R128DispatchIndirectDMA(atis);
|
|
else if (atis->using_pseudo) {
|
|
if (atic->is_radeon)
|
|
RadeonDispatchIndirectPDMA(atis);
|
|
else
|
|
R128DispatchIndirectPDMA(atis);
|
|
} else
|
|
ATIDispatchIndirectMMIO(atis);
|
|
|
|
buf->used = 0;
|
|
atis->indirectStart = 0;
|
|
}
|
|
|
|
static Bool
|
|
ATIInitAGP(ScreenPtr pScreen, int size)
|
|
{
|
|
KdScreenPriv(pScreen);
|
|
ATIScreenInfo(pScreenPriv);
|
|
ATICardInfo(pScreenPriv);
|
|
AgpInfoPtr agp_info;
|
|
int screennum = atis->screen->mynum;
|
|
|
|
if (atic->is_radeon)
|
|
return FALSE;
|
|
|
|
if (!KdAgpGARTSupported())
|
|
return FALSE;
|
|
|
|
if (!KdAcquireGART(screennum))
|
|
return FALSE;
|
|
|
|
atis->agp_key = KdAllocateGARTMemory(screennum, size, 0, NULL);
|
|
if (atis->agp_key == -1) {
|
|
ErrorF("Failed to allocate %dKB GART memory\n", size/1024);
|
|
KdReleaseGART(screennum);
|
|
return FALSE;
|
|
}
|
|
|
|
if (!KdBindGARTMemory(screennum, atis->agp_key, 0)) {
|
|
ErrorF("Failed to bind GART memory\n");
|
|
KdReleaseGART(screennum);
|
|
return FALSE;
|
|
}
|
|
|
|
agp_info = KdGetAGPInfo(screennum);
|
|
if (agp_info == NULL) {
|
|
KdUnbindGARTMemory(screennum, atis->agp_key);
|
|
KdReleaseGART(screennum);
|
|
return FALSE;
|
|
}
|
|
|
|
atis->agp_addr = KdMapDevice(agp_info->base, agp_info->size);
|
|
if (atis->agp_addr == NULL) {
|
|
ErrorF("Failed to map GART memory\n");
|
|
KdUnbindGARTMemory(screennum, atis->agp_key);
|
|
KdReleaseGART(screennum);
|
|
free(agp_info);
|
|
return FALSE;
|
|
}
|
|
KdSetMappedMode(agp_info->base, agp_info->size,
|
|
KD_MAPPED_MODE_FRAMEBUFFER);
|
|
|
|
atis->agp_size = size;
|
|
free(agp_info);
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
static void
|
|
ATIFiniAGP(ScreenPtr pScreen)
|
|
{
|
|
KdScreenPriv(pScreen);
|
|
ATIScreenInfo(pScreenPriv);
|
|
int screennum = atis->screen->mynum;
|
|
|
|
KdUnbindGARTMemory(screennum, atis->agp_key);
|
|
KdReleaseGART(screennum);
|
|
atis->agp_addr = NULL;
|
|
atis->agp_size = 0;
|
|
}
|
|
|
|
static Bool
|
|
ATIPseudoDMAInit(ScreenPtr pScreen)
|
|
{
|
|
KdScreenPriv(pScreen);
|
|
ATIScreenInfo(pScreenPriv);
|
|
ATICardInfo(pScreenPriv);
|
|
char *mmio = atic->reg_base;
|
|
|
|
if (atic->is_r300)
|
|
return FALSE;
|
|
|
|
ATIUploadMicrocode(atis);
|
|
ATIEngineReset(atis);
|
|
|
|
if (atic->is_r200) {
|
|
MMIO_OUT32(mmio, RADEON_REG_CP_CSQ_CNTL,
|
|
RADEON_CSQ_PRIPIO_INDDIS);
|
|
atis->cce_pri_size = MMIO_IN32(mmio, RADEON_REG_CP_CSQ_CNTL) &
|
|
R200_CSQ_CNT_PRIMARY_MASK;
|
|
MMIO_OUT32(mmio, RADEON_REG_ME_CNTL, RADEON_ME_MODE_FREE_RUN);
|
|
} else if (atic->is_radeon) {
|
|
MMIO_OUT32(mmio, RADEON_REG_CP_CSQ_CNTL,
|
|
RADEON_CSQ_PRIPIO_INDDIS);
|
|
atis->cce_pri_size = MMIO_IN32(mmio, RADEON_REG_CP_CSQ_CNTL) &
|
|
RADEON_CSQ_CNT_PRIMARY_MASK;
|
|
MMIO_OUT32(mmio, RADEON_REG_ME_CNTL, RADEON_ME_MODE_FREE_RUN);
|
|
} else {
|
|
MMIO_OUT32(mmio, R128_REG_PM4_BUFFER_CNTL, R128_PM4_192PIO |
|
|
R128_PM4_BUFFER_CNTL_NOUPDATE);
|
|
atis->cce_pri_size = 192;
|
|
MMIO_OUT32(mmio, R128_REG_PM4_MICRO_CNTL,
|
|
R128_PM4_MICRO_FREERUN);
|
|
}
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
static Bool
|
|
ATIPseudoDMAFini(ScreenPtr pScreen)
|
|
{ KdScreenPriv(pScreen);
|
|
ATIScreenInfo(pScreenPriv);
|
|
ATICardInfo(pScreenPriv);
|
|
char *mmio = atic->reg_base;
|
|
|
|
if (atic->is_radeon) {
|
|
MMIO_OUT32(mmio, RADEON_REG_ME_CNTL, 0);
|
|
MMIO_OUT32(mmio, RADEON_REG_CP_CSQ_CNTL,
|
|
RADEON_CSQ_PRIDIS_INDDIS);
|
|
} else {
|
|
MMIO_OUT32(mmio, R128_REG_PM4_MICRO_CNTL, 0);
|
|
MMIO_OUT32(mmio, R128_REG_PM4_BUFFER_CNTL,
|
|
R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE);
|
|
}
|
|
atis->cce_pri_size = 0;
|
|
|
|
ATIEngineReset(atis);
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
static Bool
|
|
ATIDMAInit(ScreenPtr pScreen, Bool use_agp)
|
|
{
|
|
KdScreenPriv(pScreen);
|
|
ATIScreenInfo(pScreenPriv);
|
|
ATICardInfo(pScreenPriv);
|
|
char *mmio = atic->reg_base;
|
|
int dma_offset;
|
|
CARD32 tmp;
|
|
|
|
/* XXX: Not for radeons. Yet? */
|
|
if (atic->is_radeon)
|
|
return FALSE;
|
|
|
|
if (use_agp) {
|
|
if (1)
|
|
return FALSE; /* XXX */
|
|
/* Allocate a 1MB AGP space, but only use 128k + 128 for DMA.
|
|
* XXX: Should use the rest for things like scratch space.
|
|
*/
|
|
if (!ATIInitAGP(pScreen, 1024 * 1024))
|
|
return FALSE;
|
|
atis->ring_addr = atis->agp_addr;
|
|
atis->ring_len = 128 * 1024;
|
|
dma_offset = R128_AGP_OFFSET;
|
|
} else {
|
|
if (1)
|
|
return FALSE; /* XXX */
|
|
/* Allocate a 128K buffer, plus 32 DWORDS to give space for the
|
|
* R128 ASIC bug workaround.
|
|
*/
|
|
atis->dma_space = KdOffscreenAlloc(pScreen, 128 * 1024 + 128,
|
|
128, TRUE, NULL, NULL);
|
|
if (atis->dma_space == NULL)
|
|
return FALSE;
|
|
atis->ring_addr = (CARD32 *)(atis->dma_space->offset +
|
|
pScreenPriv->screen->memory_base);
|
|
atis->ring_len = 128 * 1024;
|
|
dma_offset = atis->dma_space->offset;
|
|
}
|
|
|
|
ATIUploadMicrocode(atis);
|
|
ATIEngineReset(atis);
|
|
|
|
atis->ring_read = 0;
|
|
atis->ring_write = 0;
|
|
|
|
tmp = MMIO_IN32(mmio, ATI_REG_BUS_CNTL);
|
|
MMIO_OUT32(mmio, ATI_REG_BUS_CNTL, tmp & ~ATI_BUS_MASTER_DIS);
|
|
|
|
MMIO_OUT32(mmio, ATI_REG_CCE_RB_BASE, dma_offset);
|
|
MMIO_OUT32(mmio, ATI_REG_CCE_WPTR, atis->ring_write);
|
|
MMIO_OUT32(mmio, ATI_REG_CCE_RPTR, atis->ring_read);
|
|
MMIO_OUT32(mmio, ATI_REG_CCE_RPTR_ADDR, 0 /* XXX? */);
|
|
|
|
if (atic->is_r200) {
|
|
MMIO_OUT32(mmio, RADEON_REG_CP_CSQ_CNTL,
|
|
RADEON_CSQ_PRIBM_INDBM);
|
|
atis->cce_pri_size = MMIO_IN32(mmio, RADEON_REG_CP_CSQ_CNTL) &
|
|
R200_CSQ_CNT_PRIMARY_MASK;
|
|
MMIO_OUT32(mmio, RADEON_REG_ME_CNTL, RADEON_ME_MODE_FREE_RUN);
|
|
} else if (atic->is_radeon) {
|
|
MMIO_OUT32(mmio, RADEON_REG_CP_CSQ_CNTL,
|
|
RADEON_CSQ_PRIBM_INDBM);
|
|
atis->cce_pri_size = MMIO_IN32(mmio, RADEON_REG_CP_CSQ_CNTL) &
|
|
RADEON_CSQ_CNT_PRIMARY_MASK;
|
|
MMIO_OUT32(mmio, RADEON_REG_ME_CNTL, RADEON_ME_MODE_FREE_RUN);
|
|
} else {
|
|
MMIO_OUT32(mmio, R128_REG_PM4_BUFFER_WM_CNTL,
|
|
((R128_WATERMARK_L/4) << R128_WMA_SHIFT) |
|
|
((R128_WATERMARK_M/4) << R128_WMB_SHIFT) |
|
|
((R128_WATERMARK_N/4) << R128_WMC_SHIFT) |
|
|
((R128_WATERMARK_K/64) << R128_WB_WM_SHIFT));
|
|
/* The sample code reads from an undocumneted register
|
|
* (PM4_BUFFER_ADDR). Perhaps it's a write posting thing? Do
|
|
* a read in case that's it.
|
|
*/
|
|
MMIO_IN32(mmio, R128_REG_PM4_BUFFER_CNTL);
|
|
if (use_agp) {
|
|
/* XXX Magic num */
|
|
MMIO_OUT32(mmio, R128_REG_PCI_GART_PAGE, 1);
|
|
MMIO_OUT32(mmio, R128_REG_PM4_BUFFER_CNTL,
|
|
ATILog2(atis->ring_len) |
|
|
R128_PM4_192BM |
|
|
R128_PM4_BUFFER_CNTL_NOUPDATE);
|
|
} else {
|
|
MMIO_OUT32(mmio, R128_REG_PM4_BUFFER_CNTL,
|
|
ATILog2(atis->ring_len) |
|
|
R128_PM4_192BM |
|
|
R128_PM4_BUFFER_CNTL_NOUPDATE |
|
|
R128_PM4_IN_FRAME_BUFFER);
|
|
}
|
|
atis->cce_pri_size = 192;
|
|
MMIO_IN32(mmio, R128_REG_PM4_BUFFER_CNTL);
|
|
MMIO_OUT32(mmio, R128_REG_PM4_MICRO_CNTL,
|
|
R128_PM4_MICRO_FREERUN);
|
|
}
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
static Bool
|
|
ATIDMAFini(ScreenPtr pScreen)
|
|
{
|
|
KdScreenPriv(pScreen);
|
|
ATIScreenInfo(pScreenPriv);
|
|
ATICardInfo(pScreenPriv);
|
|
char *mmio = atic->reg_base;
|
|
|
|
if (atic->is_radeon) {
|
|
MMIO_OUT32(mmio, RADEON_REG_ME_CNTL, 0);
|
|
MMIO_OUT32(mmio, RADEON_REG_CP_CSQ_CNTL,
|
|
RADEON_CSQ_PRIDIS_INDDIS);
|
|
} else {
|
|
MMIO_OUT32(mmio, ATI_REG_CCE_WPTR,
|
|
atis->ring_write | R128_PM4_BUFFER_DL_DONE);
|
|
MMIO_OUT32(mmio, R128_REG_PM4_MICRO_CNTL, 0);
|
|
MMIO_OUT32(mmio, R128_REG_PM4_BUFFER_CNTL,
|
|
R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE);
|
|
}
|
|
atis->cce_pri_size = 0;
|
|
|
|
ATIEngineReset(atis);
|
|
|
|
if (atis->using_agp)
|
|
ATIFiniAGP(pScreen);
|
|
else
|
|
KdOffscreenFree(pScreen, atis->dma_space);
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
void
|
|
ATIDMASetup(ScreenPtr pScreen)
|
|
{
|
|
KdScreenPriv(pScreen);
|
|
ATICardInfo(pScreenPriv);
|
|
ATIScreenInfo(pScreenPriv);
|
|
|
|
#ifdef USE_DRI
|
|
if (atis->using_dri)
|
|
ATIDRIDMAStart(atis);
|
|
#endif /* USE_DRI */
|
|
|
|
if (!atis->using_dri) {
|
|
atis->using_agp = FALSE;
|
|
if (atic->is_agp && ATIDMAInit(pScreen, TRUE)) {
|
|
atis->using_agp = TRUE;
|
|
atis->using_dma = TRUE;
|
|
} else if (ATIDMAInit(pScreen, FALSE)) {
|
|
atis->using_agp = FALSE;
|
|
atis->using_dma = TRUE;
|
|
} else if (ATIPseudoDMAInit(pScreen))
|
|
atis->using_pseudo = TRUE;
|
|
else
|
|
atis->using_pio = TRUE;
|
|
}
|
|
|
|
atis->indirectBuffer = ATIGetDMABuffer(atis);
|
|
if (atis->indirectBuffer == FALSE)
|
|
FatalError("Failed to allocate DMA buffer.\n");
|
|
|
|
if (atis->using_dri)
|
|
ErrorF("Initialized %s DRI DMA\n",
|
|
atis->using_agp ? "AGP" : "PCI");
|
|
else if (atis->using_dma && atis->using_agp)
|
|
ErrorF("Initialized AGP DMA\n");
|
|
else if (atis->using_dma)
|
|
ErrorF("Initialized framebuffer pseudo-DMA\n");
|
|
else if (atis->using_pseudo)
|
|
ErrorF("Initialized pseudo-DMA\n");
|
|
else if (atis->using_pio)
|
|
ErrorF("Initialized PIO\n");
|
|
}
|
|
|
|
void
|
|
ATIDMATeardown(ScreenPtr pScreen)
|
|
{
|
|
KdScreenPriv(pScreen);
|
|
ATIScreenInfo(pScreenPriv);
|
|
|
|
ATIWaitIdle(atis);
|
|
|
|
#ifdef USE_DRI
|
|
if (atis->using_dri)
|
|
ATIDRIDMAStop(atis);
|
|
#endif /* USE_DRI */
|
|
|
|
if (atis->using_dma)
|
|
ATIDMAFini(pScreen);
|
|
|
|
if (atis->using_pseudo)
|
|
ATIPseudoDMAFini(pScreen);
|
|
|
|
if (atis->using_pio || atis->using_pseudo || atis->using_dma) {
|
|
xfree(atis->indirectBuffer->address);
|
|
xfree(atis->indirectBuffer);
|
|
}
|
|
atis->indirectBuffer = NULL;
|
|
|
|
atis->using_pio = FALSE;
|
|
atis->using_pseudo = FALSE;
|
|
atis->using_dma = FALSE;
|
|
atis->using_agp = FALSE;
|
|
}
|
|
|