958 lines
23 KiB
C
958 lines
23 KiB
C
/*
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* Copyright (c) 1997-2003 by The XFree86 Project, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Except as contained in this notice, the name of the copyright holder(s)
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* and author(s) shall not be used in advertising or otherwise to promote
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* the sale, use or other dealings in this Software without prior written
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* authorization from the copyright holder(s) and author(s).
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*/
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/*
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* This file contains the interfaces to the bus-specific code
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*/
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#ifdef HAVE_XORG_CONFIG_H
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#include <xorg-config.h>
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#endif
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#include <ctype.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <X11/X.h>
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#include <pciaccess.h>
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#include "os.h"
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#include "Pci.h"
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#include "xf86.h"
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#include "xf86Priv.h"
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#include "xf86Resources.h"
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/* Bus-specific headers */
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#include "xf86Bus.h"
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#define XF86_OS_PRIVS
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#define NEED_OS_RAC_PROTOS
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#include "xf86_OSproc.h"
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#include "xf86RAC.h"
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/* Bus-specific globals */
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Bool pciSlotClaimed = FALSE;
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static struct pci_device ** xf86PciVideoInfo = NULL; /* PCI probe for video hw */
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/* PCI classes that get included in xf86PciVideoInfo */
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#define PCIINFOCLASSES(c) \
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( (((c) & 0x00ff0000) == (PCI_CLASS_PREHISTORIC << 16)) \
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|| (((c) & 0x00ff0000) == (PCI_CLASS_DISPLAY << 16)) \
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|| ((((c) & 0x00ffff00) \
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== ((PCI_CLASS_MULTIMEDIA << 16) | (PCI_SUBCLASS_MULTIMEDIA_VIDEO << 8)))) \
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|| ((((c) & 0x00ffff00) \
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== ((PCI_CLASS_PROCESSOR << 16) | (PCI_SUBCLASS_PROCESSOR_COPROC << 8)))) )
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/*
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* PCI classes that have messages printed always. The others are only
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* have a message printed when the vendor/dev IDs are recognised.
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*/
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#define PCIALWAYSPRINTCLASSES(c) \
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( (((c) & 0x00ffff00) \
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== ((PCI_CLASS_PREHISTORIC << 16) | (PCI_SUBCLASS_PREHISTORIC_VGA << 8))) \
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|| (((c) & 0x00ff0000) == (PCI_CLASS_DISPLAY << 16)) \
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|| ((((c) & 0x00ffff00) \
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== ((PCI_CLASS_MULTIMEDIA << 16) | (PCI_SUBCLASS_MULTIMEDIA_VIDEO << 8)))) )
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#define IS_VGA(c) \
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(((c) & 0x00ffff00) \
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== ((PCI_CLASS_DISPLAY << 16) | (PCI_SUBCLASS_DISPLAY_VGA << 8)))
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/*
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* PCI classes for which potentially destructive checking of the map sizes
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* may be done. Any classes where this may be unsafe should be omitted
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* from this list.
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*/
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#define PCINONSYSTEMCLASSES(c) PCIALWAYSPRINTCLASSES(c)
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/*
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* PCI classes that use RAC
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*/
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#define PCISHAREDIOCLASSES(c) \
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( (((c) & 0x00ffff00) \
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== ((PCI_CLASS_PREHISTORIC << 16) | (PCI_SUBCLASS_PREHISTORIC_VGA << 8))) \
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|| IS_VGA(c) )
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void
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xf86FormatPciBusNumber(int busnum, char *buffer)
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{
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/* 'buffer' should be at least 8 characters long */
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if (busnum < 256)
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sprintf(buffer, "%d", busnum);
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else
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sprintf(buffer, "%d@%d", busnum & 0x00ff, busnum >> 8);
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}
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/*
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* IO enable/disable related routines for PCI
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*/
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#define pArg ((pciArg*)arg)
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#define SETBITS PCI_CMD_IO_ENABLE
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static void
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pciIoAccessEnable(void* arg)
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{
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#if 0
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#ifdef DEBUG
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ErrorF("pciIoAccessEnable: 0x%05lx\n", *(PCITAG *)arg);
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#endif
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pArg->ctrl |= SETBITS | PCI_CMD_MASTER_ENABLE;
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pci_device_cfg_write_u32(pArg->dev, pArg->ctrl, PCI_CMD_STAT_REG);
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#endif
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}
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static void
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pciIoAccessDisable(void* arg)
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{
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#if 0
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#ifdef DEBUG
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ErrorF("pciIoAccessDisable: 0x%05lx\n", *(PCITAG *)arg);
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#endif
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pArg->ctrl &= ~SETBITS;
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pci_device_cfg_write_u32(pArg->dev, pArg->ctrl, PCI_CMD_STAT_REG);
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#endif
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}
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#undef SETBITS
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#define SETBITS (PCI_CMD_IO_ENABLE | PCI_CMD_MEM_ENABLE)
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static void
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pciIo_MemAccessEnable(void* arg)
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{
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#if 0
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#ifdef DEBUG
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ErrorF("pciIo_MemAccessEnable: 0x%05lx\n", *(PCITAG *)arg);
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#endif
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pArg->ctrl |= SETBITS | PCI_CMD_MASTER_ENABLE;
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pci_device_cfg_write_u32(pArg->dev, pArg->ctrl, PCI_CMD_STAT_REG);
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#endif
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}
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static void
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pciIo_MemAccessDisable(void* arg)
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{
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#if 0
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#ifdef DEBUG
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ErrorF("pciIo_MemAccessDisable: 0x%05lx\n", *(PCITAG *)arg);
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#endif
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pArg->ctrl &= ~SETBITS;
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pci_device_cfg_write_u32(pArg->dev, pArg->ctrl, PCI_CMD_STAT_REG);
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#endif
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}
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#undef SETBITS
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#define SETBITS (PCI_CMD_MEM_ENABLE)
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static void
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pciMemAccessEnable(void* arg)
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{
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#if 0
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#ifdef DEBUG
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ErrorF("pciMemAccessEnable: 0x%05lx\n", *(PCITAG *)arg);
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#endif
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pArg->ctrl |= SETBITS | PCI_CMD_MASTER_ENABLE;
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pci_device_cfg_write_u32(pArg->dev, pArg->ctrl, PCI_CMD_STAT_REG);
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#endif
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}
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static void
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pciMemAccessDisable(void* arg)
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{
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#if 0
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#ifdef DEBUG
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ErrorF("pciMemAccessDisable: 0x%05lx\n", *(PCITAG *)arg);
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#endif
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pArg->ctrl &= ~SETBITS;
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pci_device_cfg_write_u32(pArg->dev, pArg->ctrl, PCI_CMD_STAT_REG);
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#endif
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}
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#undef SETBITS
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#undef pArg
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/* move to OS layer */
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#define MASKBITS (PCI_PCI_BRIDGE_VGA_EN | PCI_PCI_BRIDGE_MASTER_ABORT_EN)
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static void
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pciBusAccessEnable(BusAccPtr ptr)
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{
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#if 0
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struct pci_device * const dev = ptr->busdep.pci.dev;
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uint16_t ctrl;
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#ifdef DEBUG
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ErrorF("pciBusAccessEnable: bus=%d\n", ptr->busdep.pci.bus);
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#endif
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pci_device_cfg_read_u16( dev, & ctrl, PCI_PCI_BRIDGE_CONTROL_REG );
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if ((ctrl & MASKBITS) != PCI_PCI_BRIDGE_VGA_EN) {
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ctrl = (ctrl | PCI_PCI_BRIDGE_VGA_EN) &
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~(PCI_PCI_BRIDGE_MASTER_ABORT_EN | PCI_PCI_BRIDGE_SECONDARY_RESET);
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pci_device_cfg_write_u16(dev, ctrl, PCI_PCI_BRIDGE_CONTROL_REG);
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}
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#endif
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}
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/* move to OS layer */
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static void
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pciBusAccessDisable(BusAccPtr ptr)
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{
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#if 0
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struct pci_device * const dev = ptr->busdep.pci.dev;
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uint16_t ctrl;
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#ifdef DEBUG
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ErrorF("pciBusAccessDisable: bus=%d\n", ptr->busdep.pci.bus);
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#endif
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pci_device_cfg_read_u16( dev, & ctrl, PCI_PCI_BRIDGE_CONTROL_REG );
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if (ctrl & MASKBITS) {
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ctrl &= ~(MASKBITS | PCI_PCI_BRIDGE_SECONDARY_RESET);
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pci_device_cfg_write_u16(dev, ctrl, PCI_PCI_BRIDGE_CONTROL_REG);
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}
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#endif
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}
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#undef MASKBITS
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static void
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pciSetBusAccess(BusAccPtr ptr)
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{
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#if 0
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#ifdef DEBUG
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ErrorF("pciSetBusAccess: route VGA to bus %d\n", ptr->busdep.pci.bus);
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#endif
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if (!ptr->primary && !ptr->current)
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return;
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if (ptr->current && ptr->current->disable_f)
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(*ptr->current->disable_f)(ptr->current);
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ptr->current = NULL;
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/* walk down */
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while (ptr->primary) { /* No enable for root bus */
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if (ptr != ptr->primary->current) {
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if (ptr->primary->current && ptr->primary->current->disable_f)
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(*ptr->primary->current->disable_f)(ptr->primary->current);
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if (ptr->enable_f)
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(*ptr->enable_f)(ptr);
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ptr->primary->current = ptr;
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}
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ptr = ptr->primary;
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}
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#endif
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}
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/* move to OS layer */
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static void
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savePciState( struct pci_device * dev, pciSavePtr ptr )
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{
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#if 0
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int i;
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pci_device_cfg_read_u32( dev, & ptr->command, PCI_CMD_STAT_REG );
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for ( i = 0; i < 6; i++ ) {
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pci_device_cfg_read_u32( dev, & ptr->base[i],
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PCI_CMD_BASE_REG + (i * 4) );
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}
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pci_device_cfg_read_u32( dev, & ptr->biosBase, PCI_CMD_BIOS_REG );
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#endif
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}
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/* move to OS layer */
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#if 0
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static void
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restorePciState( struct pci_device * dev, pciSavePtr ptr)
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{
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int i;
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/* disable card before setting anything */
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pci_device_cfg_write_bits(dev, PCI_CMD_MEM_ENABLE | PCI_CMD_IO_ENABLE, 0,
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PCI_CMD_STAT_REG);
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pci_device_cfg_write_u32(dev, ptr->biosBase, PCI_CMD_BIOS_REG);
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for ( i = 0; i < 6; i++ ) {
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pci_device_cfg_write_u32(dev, ptr->base[i],
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PCI_CMD_BASE_REG + (i * 4));
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}
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pci_device_cfg_write_u32(dev, ptr->command, PCI_CMD_STAT_REG);
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}
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#endif
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/* move to OS layer */
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static void
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savePciBusState(BusAccPtr ptr)
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{
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#if 0
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struct pci_device * const dev = ptr->busdep.pci.dev;
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uint16_t temp;
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pci_device_cfg_read_u16( dev, & temp, PCI_PCI_BRIDGE_CONTROL_REG );
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ptr->busdep.pci.save.control = temp & ~PCI_PCI_BRIDGE_SECONDARY_RESET;
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/* Allow master aborts to complete normally on non-root buses */
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if ( ptr->busdep.pci.save.control & PCI_PCI_BRIDGE_MASTER_ABORT_EN ) {
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temp = ptr->busdep.pci.save.control & ~PCI_PCI_BRIDGE_MASTER_ABORT_EN;
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pci_device_cfg_read_u16( dev, & temp, PCI_PCI_BRIDGE_CONTROL_REG );
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}
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#endif
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}
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/* move to OS layer */
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#define MASKBITS (PCI_PCI_BRIDGE_VGA_EN | PCI_PCI_BRIDGE_MASTER_ABORT_EN)
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static void
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restorePciBusState(BusAccPtr ptr)
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{
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#if 0
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struct pci_device * const dev = ptr->busdep.pci.dev;
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uint16_t ctrl;
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/* Only restore the bits we've changed (and don't cause resets) */
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pci_device_cfg_read_u16( dev, & ctrl, PCI_PCI_BRIDGE_CONTROL_REG );
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if ((ctrl ^ ptr->busdep.pci.save.control) & MASKBITS) {
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ctrl &= ~(MASKBITS | PCI_PCI_BRIDGE_SECONDARY_RESET);
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ctrl |= ptr->busdep.pci.save.control & MASKBITS;
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pci_device_cfg_write_u16(dev, ctrl, PCI_PCI_BRIDGE_CONTROL_REG);
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}
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#endif
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}
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#undef MASKBITS
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/*
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* xf86Bus.c interface
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*/
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void
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xf86PciProbe(void)
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{
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int i = 0, k;
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int num = 0;
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struct pci_device *info;
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struct pci_device_iterator *iter;
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if (!xf86scanpci()) {
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xf86PciVideoInfo = NULL;
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return;
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}
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iter = pci_slot_match_iterator_create(& xf86IsolateDevice);
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while ((info = pci_device_next(iter)) != NULL) {
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if (PCIINFOCLASSES(info->device_class)) {
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num++;
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xf86PciVideoInfo = xnfrealloc(xf86PciVideoInfo,
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(sizeof(struct pci_device *)
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* (num + 1)));
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xf86PciVideoInfo[num] = NULL;
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xf86PciVideoInfo[num - 1] = info;
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pci_device_probe(info);
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info->user_data = 0;
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}
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}
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/* If we haven't found a primary device try a different heuristic */
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if (primaryBus.type == BUS_NONE && num) {
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for (i = 0; i < num; i++) {
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uint16_t command;
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info = xf86PciVideoInfo[i];
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pci_device_cfg_read_u16(info, & command, 4);
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if ((command & PCI_CMD_MEM_ENABLE)
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&& ((num == 1) || IS_VGA(info->device_class))) {
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if (primaryBus.type == BUS_NONE) {
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primaryBus.type = BUS_PCI;
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primaryBus.id.pci = info;
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} else {
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xf86Msg(X_NOTICE,
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"More than one possible primary device found\n");
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primaryBus.type ^= (BusType)(-1);
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}
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}
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}
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}
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/* Print a summary of the video devices found */
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for (k = 0; k < num; k++) {
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const char *vendorname = NULL, *chipname = NULL;
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const char *prim = " ";
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Bool memdone = FALSE, iodone = FALSE;
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info = xf86PciVideoInfo[k];
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vendorname = pci_device_get_vendor_name( info );
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chipname = pci_device_get_device_name( info );
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if ((!vendorname || !chipname) &&
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!PCIALWAYSPRINTCLASSES(info->device_class))
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continue;
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if (xf86IsPrimaryPci(info))
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prim = "*";
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xf86Msg( X_PROBED, "PCI:%s(%u@%u:%u:%u) ", prim, info->domain,
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info->bus, info->dev, info->func );
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if (vendorname)
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xf86ErrorF("%s ", vendorname);
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else
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xf86ErrorF("unknown vendor (0x%04x) ", info->vendor_id);
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if (chipname)
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xf86ErrorF("%s ", chipname);
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else
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xf86ErrorF("unknown chipset (0x%04x) ", info->device_id);
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xf86ErrorF("rev %d", info->revision);
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for (i = 0; i < 6; i++) {
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struct pci_mem_region * r = & info->regions[i];
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if ( r->size && ! r->is_IO ) {
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if (!memdone) {
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xf86ErrorF(", Mem @ ");
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memdone = TRUE;
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} else
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xf86ErrorF(", ");
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xf86ErrorF("0x%08lx/%ld", (long)r->base_addr, (long)r->size);
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}
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}
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for (i = 0; i < 6; i++) {
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struct pci_mem_region * r = & info->regions[i];
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if ( r->size && r->is_IO ) {
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if (!iodone) {
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xf86ErrorF(", I/O @ ");
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iodone = TRUE;
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} else
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xf86ErrorF(", ");
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xf86ErrorF("0x%08lx/%ld", (long)r->base_addr, (long)r->size);
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}
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}
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if ( info->rom_size ) {
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xf86ErrorF(", BIOS @ 0x\?\?\?\?\?\?\?\?/%ld", (long)info->rom_size);
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}
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xf86ErrorF("\n");
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}
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}
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void
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initPciState(void)
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{
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unsigned i;
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pciAccPtr pcaccp;
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if (xf86PciVideoInfo == NULL) {
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return;
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}
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for (i = 0 ; xf86PciVideoInfo[i] != NULL ; i++) {
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struct pci_device * const pvp = xf86PciVideoInfo[i];
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if (pvp->user_data == 0) {
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pcaccp = xnfalloc( sizeof( pciAccRec ) );
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pvp->user_data = (intptr_t) pcaccp;
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pcaccp->arg.dev = pvp;
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pcaccp->ioAccess.AccessDisable = pciIoAccessDisable;
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pcaccp->ioAccess.AccessEnable = pciIoAccessEnable;
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pcaccp->ioAccess.arg = &pcaccp->arg;
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pcaccp->io_memAccess.AccessDisable = pciIo_MemAccessDisable;
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pcaccp->io_memAccess.AccessEnable = pciIo_MemAccessEnable;
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pcaccp->io_memAccess.arg = &pcaccp->arg;
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pcaccp->memAccess.AccessDisable = pciMemAccessDisable;
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pcaccp->memAccess.AccessEnable = pciMemAccessEnable;
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pcaccp->memAccess.arg = &pcaccp->arg;
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pcaccp->ctrl = PCISHAREDIOCLASSES(pvp->device_class);
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savePciState(pvp, &pcaccp->save);
|
|
pcaccp->arg.ctrl = pcaccp->save.command;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* initPciBusState() - fill out the BusAccRec for a PCI bus.
|
|
* Theory: each bus is associated with one bridge connecting it
|
|
* to its parent bus. The address of a bridge is therefore stored
|
|
* in the BusAccRec of the bus it connects to. Each bus can
|
|
* have several bridges connecting secondary buses to it. Only one
|
|
* of these bridges can be open. Therefore the status of a bridge
|
|
* associated with a bus is stored in the BusAccRec of the parent
|
|
* the bridge connects to. The first member of the structure is
|
|
* a pointer to a function that open access to this bus. This function
|
|
* receives a pointer to the structure itself as argument. This
|
|
* design should be common to BusAccRecs of any type of buses we
|
|
* support. The remeinder of the structure is bus type specific.
|
|
* In this case it contains a pointer to the structure of the
|
|
* parent bus. Thus enabling access to a specific bus is simple:
|
|
* 1. Close any bridge going to secondary buses.
|
|
* 2. Climb down the ladder and enable any bridge on buses
|
|
* on the path from the CPU to this bus.
|
|
*/
|
|
|
|
void
|
|
initPciBusState(void)
|
|
{
|
|
static const struct pci_id_match bridge_match = {
|
|
PCI_MATCH_ANY, PCI_MATCH_ANY, PCI_MATCH_ANY, PCI_MATCH_ANY,
|
|
(PCI_CLASS_BRIDGE << 16), 0x0000ff0000, 0
|
|
};
|
|
struct pci_device *dev;
|
|
struct pci_device_iterator *iter;
|
|
BusAccPtr pbap, pbap_tmp;
|
|
|
|
iter = pci_id_match_iterator_create(& bridge_match);
|
|
while((dev = pci_device_next(iter)) != NULL) {
|
|
const uint8_t subclass = (dev->device_class >> 8) & 0x0ff;
|
|
int primary;
|
|
int secondary;
|
|
int subordinate;
|
|
|
|
|
|
pci_device_get_bridge_buses(dev, &primary, &secondary, &subordinate);
|
|
|
|
pbap = xnfcalloc(1,sizeof(BusAccRec));
|
|
pbap->busdep.pci.bus = secondary;
|
|
pbap->busdep.pci.primary_bus = primary;
|
|
pbap->busdep_type = BUS_PCI;
|
|
pbap->busdep.pci.dev = dev;
|
|
|
|
pbap->set_f = pciSetBusAccess;
|
|
|
|
switch (subclass) {
|
|
case PCI_SUBCLASS_BRIDGE_HOST:
|
|
pbap->type = BUS_PCI;
|
|
break;
|
|
case PCI_SUBCLASS_BRIDGE_PCI:
|
|
case PCI_SUBCLASS_BRIDGE_CARDBUS:
|
|
pbap->type = BUS_PCI;
|
|
pbap->save_f = savePciBusState;
|
|
pbap->restore_f = restorePciBusState;
|
|
pbap->enable_f = pciBusAccessEnable;
|
|
pbap->disable_f = pciBusAccessDisable;
|
|
savePciBusState(pbap);
|
|
break;
|
|
}
|
|
pbap->next = xf86BusAccInfo;
|
|
xf86BusAccInfo = pbap;
|
|
}
|
|
|
|
pci_iterator_destroy(iter);
|
|
|
|
for (pbap = xf86BusAccInfo; pbap; pbap = pbap->next) {
|
|
pbap->primary = NULL;
|
|
|
|
if (pbap->busdep_type == BUS_PCI
|
|
&& pbap->busdep.pci.primary_bus > -1) {
|
|
pbap_tmp = xf86BusAccInfo;
|
|
while (pbap_tmp) {
|
|
if (pbap_tmp->busdep_type == BUS_PCI &&
|
|
pbap_tmp->busdep.pci.bus == pbap->busdep.pci.primary_bus) {
|
|
/* Don't create loops */
|
|
if (pbap == pbap_tmp)
|
|
break;
|
|
pbap->primary = pbap_tmp;
|
|
break;
|
|
}
|
|
pbap_tmp = pbap_tmp->next;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
PciStateEnter(void)
|
|
{
|
|
#if 0
|
|
unsigned i;
|
|
|
|
if (xf86PciVideoInfo == NULL)
|
|
return;
|
|
|
|
for ( i = 0 ; xf86PciVideoInfo[i] != NULL ; i++ ) {
|
|
pciAccPtr paccp = (pciAccPtr) xf86PciVideoInfo[i]->user_data;
|
|
|
|
if ( (paccp != NULL) && paccp->ctrl ) {
|
|
savePciState(paccp->arg.dev, &paccp->save);
|
|
restorePciState(paccp->arg.dev, &paccp->restore);
|
|
paccp->arg.ctrl = paccp->restore.command;
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
|
|
void
|
|
PciBusStateEnter(void)
|
|
{
|
|
#if 0
|
|
BusAccPtr pbap = xf86BusAccInfo;
|
|
|
|
while (pbap) {
|
|
if (pbap->save_f)
|
|
pbap->save_f(pbap);
|
|
pbap = pbap->next;
|
|
}
|
|
#endif
|
|
}
|
|
|
|
void
|
|
PciStateLeave(void)
|
|
{
|
|
#if 0
|
|
unsigned i;
|
|
|
|
if (xf86PciVideoInfo == NULL)
|
|
return;
|
|
|
|
for ( i = 0 ; xf86PciVideoInfo[i] != NULL ; i++ ) {
|
|
pciAccPtr paccp = (pciAccPtr) xf86PciVideoInfo[i]->user_data;
|
|
|
|
if ( (paccp != NULL) && paccp->ctrl ) {
|
|
savePciState(paccp->arg.dev, &paccp->restore);
|
|
restorePciState(paccp->arg.dev, &paccp->save);
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
|
|
void
|
|
PciBusStateLeave(void)
|
|
{
|
|
#if 0
|
|
BusAccPtr pbap = xf86BusAccInfo;
|
|
|
|
while (pbap) {
|
|
if (pbap->restore_f)
|
|
pbap->restore_f(pbap);
|
|
pbap = pbap->next;
|
|
}
|
|
#endif
|
|
}
|
|
|
|
void
|
|
DisablePciAccess(void)
|
|
{
|
|
#if 0
|
|
unsigned i;
|
|
|
|
if (xf86PciVideoInfo == NULL)
|
|
return;
|
|
|
|
for ( i = 0 ; xf86PciVideoInfo[i] != NULL ; i++ ) {
|
|
pciAccPtr paccp = (pciAccPtr) xf86PciVideoInfo[i]->user_data;
|
|
|
|
if ( (paccp != NULL) && paccp->ctrl ) {
|
|
pciIo_MemAccessDisable(paccp->io_memAccess.arg);
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
|
|
void
|
|
DisablePciBusAccess(void)
|
|
{
|
|
#if 0
|
|
BusAccPtr pbap = xf86BusAccInfo;
|
|
|
|
while (pbap) {
|
|
if (pbap->disable_f)
|
|
pbap->disable_f(pbap);
|
|
if (pbap->primary)
|
|
pbap->primary->current = NULL;
|
|
pbap = pbap->next;
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* If the slot requested is already in use, return -1.
|
|
* Otherwise, claim the slot for the screen requesting it.
|
|
*/
|
|
|
|
int
|
|
xf86ClaimPciSlot(struct pci_device * d, DriverPtr drvp,
|
|
int chipset, GDevPtr dev, Bool active)
|
|
{
|
|
EntityPtr p = NULL;
|
|
pciAccPtr paccp = (pciAccPtr) d->user_data;
|
|
BusAccPtr pbap = xf86BusAccInfo;
|
|
const unsigned bus = PCI_MAKE_BUS(d->domain, d->bus);
|
|
|
|
int num;
|
|
|
|
if (xf86CheckPciSlot(d)) {
|
|
num = xf86AllocateEntity();
|
|
p = xf86Entities[num];
|
|
p->driver = drvp;
|
|
p->chipset = chipset;
|
|
p->bus.type = BUS_PCI;
|
|
p->bus.id.pci = d;
|
|
p->active = active;
|
|
p->inUse = FALSE;
|
|
if (dev)
|
|
xf86AddDevToEntity(num, dev);
|
|
/* Here we initialize the access structure */
|
|
p->access = xnfcalloc(1,sizeof(EntityAccessRec));
|
|
if (paccp != NULL) {
|
|
p->access->fallback = & paccp->io_memAccess;
|
|
p->access->pAccess = & paccp->io_memAccess;
|
|
paccp->ctrl = TRUE; /* mark control if not already */
|
|
}
|
|
else {
|
|
p->access->fallback = &AccessNULL;
|
|
p->access->pAccess = &AccessNULL;
|
|
}
|
|
|
|
p->busAcc = NULL;
|
|
while (pbap) {
|
|
if (pbap->type == BUS_PCI && pbap->busdep.pci.bus == bus)
|
|
p->busAcc = pbap;
|
|
pbap = pbap->next;
|
|
}
|
|
|
|
pciSlotClaimed = TRUE;
|
|
|
|
if (active) {
|
|
/* Map in this domain's I/O space */
|
|
p->domainIO = xf86MapLegacyIO(d);
|
|
}
|
|
|
|
return num;
|
|
} else
|
|
return -1;
|
|
}
|
|
|
|
/*
|
|
* Parse a BUS ID string, and return the PCI bus parameters if it was
|
|
* in the correct format for a PCI bus id.
|
|
*/
|
|
|
|
Bool
|
|
xf86ParsePciBusString(const char *busID, int *bus, int *device, int *func)
|
|
{
|
|
/*
|
|
* The format is assumed to be "bus[@domain]:device[:func]", where domain,
|
|
* bus, device and func are decimal integers. domain and func may be
|
|
* omitted and assumed to be zero, although doing this isn't encouraged.
|
|
*/
|
|
|
|
char *p, *s, *d;
|
|
const char *id;
|
|
int i;
|
|
|
|
if (StringToBusType(busID, &id) != BUS_PCI)
|
|
return FALSE;
|
|
|
|
s = xstrdup(id);
|
|
p = strtok(s, ":");
|
|
if (p == NULL || *p == 0) {
|
|
xfree(s);
|
|
return FALSE;
|
|
}
|
|
d = strpbrk(p, "@");
|
|
if (d != NULL) {
|
|
*(d++) = 0;
|
|
for (i = 0; d[i] != 0; i++) {
|
|
if (!isdigit(d[i])) {
|
|
xfree(s);
|
|
return FALSE;
|
|
}
|
|
}
|
|
}
|
|
for (i = 0; p[i] != 0; i++) {
|
|
if (!isdigit(p[i])) {
|
|
xfree(s);
|
|
return FALSE;
|
|
}
|
|
}
|
|
*bus = atoi(p);
|
|
if (d != NULL && *d != 0)
|
|
*bus += atoi(d) << 8;
|
|
p = strtok(NULL, ":");
|
|
if (p == NULL || *p == 0) {
|
|
xfree(s);
|
|
return FALSE;
|
|
}
|
|
for (i = 0; p[i] != 0; i++) {
|
|
if (!isdigit(p[i])) {
|
|
xfree(s);
|
|
return FALSE;
|
|
}
|
|
}
|
|
*device = atoi(p);
|
|
*func = 0;
|
|
p = strtok(NULL, ":");
|
|
if (p == NULL || *p == 0) {
|
|
xfree(s);
|
|
return TRUE;
|
|
}
|
|
for (i = 0; p[i] != 0; i++) {
|
|
if (!isdigit(p[i])) {
|
|
xfree(s);
|
|
return FALSE;
|
|
}
|
|
}
|
|
*func = atoi(p);
|
|
xfree(s);
|
|
return TRUE;
|
|
}
|
|
|
|
/*
|
|
* Compare a BUS ID string with a PCI bus id. Return TRUE if they match.
|
|
*/
|
|
|
|
Bool
|
|
xf86ComparePciBusString(const char *busID, int bus, int device, int func)
|
|
{
|
|
int ibus, idevice, ifunc;
|
|
|
|
if (xf86ParsePciBusString(busID, &ibus, &idevice, &ifunc)) {
|
|
return bus == ibus && device == idevice && func == ifunc;
|
|
} else {
|
|
return FALSE;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* xf86IsPrimaryPci() -- return TRUE if primary device
|
|
* is PCI and bus, dev and func numbers match.
|
|
*/
|
|
|
|
Bool
|
|
xf86IsPrimaryPci(struct pci_device *pPci)
|
|
{
|
|
return ((primaryBus.type == BUS_PCI) && (pPci == primaryBus.id.pci));
|
|
}
|
|
|
|
/*
|
|
* xf86GetPciInfoForEntity() -- Get the pciVideoRec of entity.
|
|
*/
|
|
struct pci_device *
|
|
xf86GetPciInfoForEntity(int entityIndex)
|
|
{
|
|
EntityPtr p;
|
|
|
|
if (entityIndex >= xf86NumEntities)
|
|
return NULL;
|
|
|
|
p = xf86Entities[entityIndex];
|
|
return (p->bus.type == BUS_PCI) ? p->bus.id.pci : NULL;
|
|
}
|
|
|
|
/*
|
|
* xf86CheckPciMemBase() checks that the memory base value matches one of the
|
|
* PCI base address register values for the given PCI device.
|
|
*/
|
|
Bool
|
|
xf86CheckPciMemBase( struct pci_device * pPci, memType base )
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < 6; i++)
|
|
if (base == pPci->regions[i].base_addr)
|
|
return TRUE;
|
|
return FALSE;
|
|
}
|
|
|
|
/*
|
|
* Check if the slot requested is free. If it is already in use, return FALSE.
|
|
*/
|
|
|
|
Bool
|
|
xf86CheckPciSlot(const struct pci_device *d)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < xf86NumEntities; i++) {
|
|
const EntityPtr p = xf86Entities[i];
|
|
|
|
if ((p->bus.type == BUS_PCI) && (p->bus.id.pci == d)) {
|
|
return FALSE;
|
|
}
|
|
}
|
|
return TRUE;
|
|
}
|
|
|
|
|
|
void
|
|
pciConvertRange2Host(int entityIndex, resRange *pRange)
|
|
{
|
|
struct pci_device *const pvp = xf86GetPciInfoForEntity(entityIndex);
|
|
const PCITAG tag = PCI_MAKE_TAG(PCI_MAKE_BUS(pvp->domain, pvp->bus),
|
|
pvp->dev, pvp->func);
|
|
|
|
if (pvp == NULL) {
|
|
return;
|
|
}
|
|
|
|
if (!(pRange->type & ResBus))
|
|
return;
|
|
|
|
switch(pRange->type & ResPhysMask) {
|
|
case ResMem:
|
|
switch(pRange->type & ResExtMask) {
|
|
case ResBlock:
|
|
pRange->rBegin = pciBusAddrToHostAddr(tag,PCI_MEM, pRange->rBegin);
|
|
pRange->rEnd = pciBusAddrToHostAddr(tag,PCI_MEM, pRange->rEnd);
|
|
break;
|
|
case ResSparse:
|
|
pRange->rBase = pciBusAddrToHostAddr(tag,PCI_MEM_SPARSE_BASE,
|
|
pRange->rBegin);
|
|
pRange->rMask = pciBusAddrToHostAddr(tag,PCI_MEM_SPARSE_MASK,
|
|
pRange->rEnd);
|
|
break;
|
|
}
|
|
break;
|
|
case ResIo:
|
|
switch(pRange->type & ResExtMask) {
|
|
case ResBlock:
|
|
pRange->rBegin = pciBusAddrToHostAddr(tag,PCI_IO, pRange->rBegin);
|
|
pRange->rEnd = pciBusAddrToHostAddr(tag,PCI_IO, pRange->rEnd);
|
|
break;
|
|
case ResSparse:
|
|
pRange->rBase = pciBusAddrToHostAddr(tag,PCI_IO_SPARSE_BASE
|
|
, pRange->rBegin);
|
|
pRange->rMask = pciBusAddrToHostAddr(tag,PCI_IO_SPARSE_MASK
|
|
, pRange->rEnd);
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
|
|
/* Set domain number */
|
|
pRange->type &= ~(ResDomain | ResBus);
|
|
pRange->type |= pvp->domain << 24;
|
|
}
|