462 lines
15 KiB
C
462 lines
15 KiB
C
/* radeon_common.h -- common header definitions for Radeon 2D/3D/DRM suite
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*
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* Copyright 2000 VA Linux Systems, Inc., Fremont, California.
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* Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Author:
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* Gareth Hughes <gareth@valinux.com>
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* Kevin E. Martin <martin@valinux.com>
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* Keith Whitwell <keith@tungstengraphics.com>
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*
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* Converted to common header format:
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* Jens Owen <jens@tungstengraphics.com>
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*
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* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_common.h,v 1.2 2003/04/07 01:22:09 martin Exp $
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*
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*/
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#ifndef _RADEON_COMMON_H_
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#define _RADEON_COMMON_H_
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#include <inttypes.h>
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/* WARNING: If you change any of these defines, make sure to change
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* the kernel include file as well (radeon_drm.h)
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*/
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/* Driver specific DRM command indices
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* NOTE: these are not OS specific, but they are driver specific
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*/
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#define DRM_RADEON_CP_INIT 0x00
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#define DRM_RADEON_CP_START 0x01
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#define DRM_RADEON_CP_STOP 0x02
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#define DRM_RADEON_CP_RESET 0x03
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#define DRM_RADEON_CP_IDLE 0x04
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#define DRM_RADEON_RESET 0x05
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#define DRM_RADEON_FULLSCREEN 0x06
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#define DRM_RADEON_SWAP 0x07
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#define DRM_RADEON_CLEAR 0x08
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#define DRM_RADEON_VERTEX 0x09
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#define DRM_RADEON_INDICES 0x0a
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#define DRM_RADEON_STIPPLE 0x0c
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#define DRM_RADEON_INDIRECT 0x0d
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#define DRM_RADEON_TEXTURE 0x0e
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#define DRM_RADEON_VERTEX2 0x0f
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#define DRM_RADEON_CMDBUF 0x10
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#define DRM_RADEON_GETPARAM 0x11
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#define DRM_RADEON_FLIP 0x12
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#define DRM_RADEON_ALLOC 0x13
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#define DRM_RADEON_FREE 0x14
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#define DRM_RADEON_INIT_HEAP 0x15
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#define DRM_RADEON_IRQ_EMIT 0x16
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#define DRM_RADEON_IRQ_WAIT 0x17
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#define DRM_RADEON_CP_RESUME 0x18
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#define DRM_RADEON_SETPARAM 0x19
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#define DRM_RADEON_MAX_DRM_COMMAND_INDEX 0x39
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#define RADEON_FRONT 0x1
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#define RADEON_BACK 0x2
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#define RADEON_DEPTH 0x4
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#define RADEON_STENCIL 0x8
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#define RADEON_CLEAR_X1 0
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#define RADEON_CLEAR_Y1 1
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#define RADEON_CLEAR_X2 2
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#define RADEON_CLEAR_Y2 3
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#define RADEON_CLEAR_DEPTH 4
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typedef struct {
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enum {
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DRM_RADEON_INIT_CP = 0x01,
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DRM_RADEON_CLEANUP_CP = 0x02,
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DRM_RADEON_INIT_R200_CP = 0x03
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} func;
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unsigned long sarea_priv_offset;
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int is_pci;
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int cp_mode;
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int gart_size;
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int ring_size;
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int usec_timeout;
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unsigned int fb_bpp;
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unsigned int front_offset, front_pitch;
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unsigned int back_offset, back_pitch;
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unsigned int depth_bpp;
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unsigned int depth_offset, depth_pitch;
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unsigned long fb_offset;
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unsigned long mmio_offset;
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unsigned long ring_offset;
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unsigned long ring_rptr_offset;
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unsigned long buffers_offset;
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unsigned long gart_textures_offset;
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} drmRadeonInit;
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typedef struct {
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int flush;
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int idle;
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} drmRadeonCPStop;
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typedef struct {
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int idx;
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int start;
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int end;
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int discard;
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} drmRadeonIndirect;
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typedef union drmRadeonClearR {
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float f[5];
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unsigned int ui[5];
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} drmRadeonClearRect;
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typedef struct drmRadeonClearT {
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unsigned int flags;
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unsigned int clear_color;
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unsigned int clear_depth;
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unsigned int color_mask;
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unsigned int depth_mask; /* misnamed field: should be stencil */
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drmRadeonClearRect *depth_boxes;
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} drmRadeonClearType;
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typedef struct drmRadeonFullscreenT {
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enum {
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RADEON_INIT_FULLSCREEN = 0x01,
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RADEON_CLEANUP_FULLSCREEN = 0x02
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} func;
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} drmRadeonFullscreenType;
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typedef struct {
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unsigned int *mask;
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} drmRadeonStipple;
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typedef struct {
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unsigned int x;
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unsigned int y;
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unsigned int width;
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unsigned int height;
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const void *data;
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} drmRadeonTexImage;
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typedef struct {
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unsigned int offset;
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int pitch;
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int format;
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int width; /* Texture image coordinates */
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int height;
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drmRadeonTexImage *image;
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} drmRadeonTexture;
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#define RADEON_MAX_TEXTURE_UNITS 3
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/* Layout matches drm_radeon_state_t in linux drm_radeon.h.
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*/
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typedef struct {
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struct {
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unsigned int pp_misc; /* 0x1c14 */
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unsigned int pp_fog_color;
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unsigned int re_solid_color;
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unsigned int rb3d_blendcntl;
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unsigned int rb3d_depthoffset;
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unsigned int rb3d_depthpitch;
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unsigned int rb3d_zstencilcntl;
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unsigned int pp_cntl; /* 0x1c38 */
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unsigned int rb3d_cntl;
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unsigned int rb3d_coloroffset;
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unsigned int re_width_height;
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unsigned int rb3d_colorpitch;
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} context;
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struct {
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unsigned int se_cntl;
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} setup1;
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struct {
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unsigned int se_coord_fmt; /* 0x1c50 */
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} vertex;
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struct {
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unsigned int re_line_pattern; /* 0x1cd0 */
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unsigned int re_line_state;
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unsigned int se_line_width; /* 0x1db8 */
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} line;
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struct {
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unsigned int pp_lum_matrix; /* 0x1d00 */
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unsigned int pp_rot_matrix_0; /* 0x1d58 */
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unsigned int pp_rot_matrix_1;
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} bumpmap;
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struct {
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unsigned int rb3d_stencilrefmask; /* 0x1d7c */
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unsigned int rb3d_ropcntl;
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unsigned int rb3d_planemask;
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} mask;
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struct {
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unsigned int se_vport_xscale; /* 0x1d98 */
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unsigned int se_vport_xoffset;
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unsigned int se_vport_yscale;
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unsigned int se_vport_yoffset;
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unsigned int se_vport_zscale;
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unsigned int se_vport_zoffset;
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} viewport;
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struct {
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unsigned int se_cntl_status; /* 0x2140 */
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} setup2;
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struct {
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unsigned int re_top_left; /*ignored*/ /* 0x26c0 */
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unsigned int re_misc;
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} misc;
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struct {
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unsigned int pp_txfilter;
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unsigned int pp_txformat;
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unsigned int pp_txoffset;
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unsigned int pp_txcblend;
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unsigned int pp_txablend;
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unsigned int pp_tfactor;
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unsigned int pp_border_color;
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} texture[RADEON_MAX_TEXTURE_UNITS];
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struct {
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unsigned int se_zbias_factor;
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unsigned int se_zbias_constant;
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} zbias;
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unsigned int dirty;
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} drmRadeonState;
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/* 1.1 vertex ioctl. Used in compatibility modes.
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*/
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typedef struct {
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int prim;
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int idx; /* Index of vertex buffer */
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int count; /* Number of vertices in buffer */
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int discard; /* Client finished with buffer? */
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} drmRadeonVertex;
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typedef struct {
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unsigned int start;
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unsigned int finish;
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unsigned int prim:8;
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unsigned int stateidx:8;
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unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
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unsigned int vc_format;
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} drmRadeonPrim;
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typedef struct {
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int idx; /* Index of vertex buffer */
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int discard; /* Client finished with buffer? */
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int nr_states;
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drmRadeonState *state;
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int nr_prims;
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drmRadeonPrim *prim;
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} drmRadeonVertex2;
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#define RADEON_MAX_STATES 16
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#define RADEON_MAX_PRIMS 64
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/* Command buffer. Replace with true dma stream?
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*/
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typedef struct {
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int bufsz;
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char *buf;
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int nbox;
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drmClipRect *boxes;
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} drmRadeonCmdBuffer;
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/* New style per-packet identifiers for use in cmd_buffer ioctl with
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* the RADEON_EMIT_PACKET command. Comments relate new packets to old
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* state bits and the packet size:
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*/
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#define RADEON_EMIT_PP_MISC 0 /* context/7 */
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#define RADEON_EMIT_PP_CNTL 1 /* context/3 */
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#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */
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#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */
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#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */
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#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */
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#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */
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#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */
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#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */
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#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */
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#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */
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#define RADEON_EMIT_RE_MISC 11 /* misc/1 */
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#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */
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#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */
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#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */
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#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */
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#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */
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#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */
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#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */
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#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */
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#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */
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#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */
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#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */
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#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */
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#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */
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#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */
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#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */
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#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */
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#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */
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#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/6 */
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#define R200_EMIT_TFACTOR_0 30 /* tf/6 */
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#define R200_EMIT_VTX_FMT_0 31 /* vtx/4 */
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#define R200_EMIT_VAP_CTL 32 /* vap/1 */
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#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */
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#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */
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#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */
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#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */
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#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */
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#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */
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#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */
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#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */
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#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */
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#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */
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#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */
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#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */
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#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */
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#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */
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#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */
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#define R200_EMIT_VTE_CNTL 48 /* vte/1 */
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#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */
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#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */
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#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */
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#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */
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#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */
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#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */
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#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */
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#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */
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#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */
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#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */
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#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */
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#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */
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#define R200_EMIT_PP_CUBIC_FACES_0 61
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#define R200_EMIT_PP_CUBIC_OFFSETS_0 62
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#define R200_EMIT_PP_CUBIC_FACES_1 63
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#define R200_EMIT_PP_CUBIC_OFFSETS_1 64
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#define R200_EMIT_PP_CUBIC_FACES_2 65
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#define R200_EMIT_PP_CUBIC_OFFSETS_2 66
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#define R200_EMIT_PP_CUBIC_FACES_3 67
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#define R200_EMIT_PP_CUBIC_OFFSETS_3 68
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#define R200_EMIT_PP_CUBIC_FACES_4 69
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#define R200_EMIT_PP_CUBIC_OFFSETS_4 70
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#define R200_EMIT_PP_CUBIC_FACES_5 71
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#define R200_EMIT_PP_CUBIC_OFFSETS_5 72
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#define RADEON_EMIT_PP_TEX_SIZE_0 73
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#define RADEON_EMIT_PP_TEX_SIZE_1 74
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#define RADEON_EMIT_PP_TEX_SIZE_2 75
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#define RADEON_MAX_STATE_PACKETS 76
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/* Commands understood by cmd_buffer ioctl. More can be added but
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* obviously these can't be removed or changed:
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*/
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#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */
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#define RADEON_CMD_SCALARS 2 /* emit scalar data */
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#define RADEON_CMD_VECTORS 3 /* emit vector data */
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#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
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#define RADEON_CMD_PACKET3 5 /* emit hw packet */
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#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
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#define RADEON_CMD_SCALARS2 7 /* R200 stopgap */
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#define RADEON_CMD_WAIT 8 /* synchronization */
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typedef union {
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int i;
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struct {
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unsigned char cmd_type, pad0, pad1, pad2;
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} header;
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struct {
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unsigned char cmd_type, packet_id, pad0, pad1;
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} packet;
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struct {
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unsigned char cmd_type, offset, stride, count;
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} scalars;
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struct {
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unsigned char cmd_type, offset, stride, count;
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} vectors;
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struct {
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unsigned char cmd_type, buf_idx, pad0, pad1;
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} dma;
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struct {
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unsigned char cmd_type, flags, pad0, pad1;
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} wait;
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} drmRadeonCmdHeader;
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#define RADEON_WAIT_2D 0x1
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#define RADEON_WAIT_3D 0x2
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typedef struct drm_radeon_getparam {
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int param;
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int *value;
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} drmRadeonGetParam;
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#define RADEON_PARAM_GART_BUFFER_OFFSET 1
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#define RADEON_PARAM_LAST_FRAME 2
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#define RADEON_PARAM_LAST_DISPATCH 3
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#define RADEON_PARAM_LAST_CLEAR 4
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#define RADEON_PARAM_IRQ_NR 5
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#define RADEON_PARAM_GART_BASE 6
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#define RADEON_MEM_REGION_GART 1
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#define RADEON_MEM_REGION_FB 2
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typedef struct drm_radeon_mem_alloc {
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int region;
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int alignment;
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int size;
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int *region_offset; /* offset from start of fb or GART */
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} drmRadeonMemAlloc;
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typedef struct drm_radeon_mem_free {
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int region;
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int region_offset;
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} drmRadeonMemFree;
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typedef struct drm_radeon_mem_init_heap {
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int region;
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int size;
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int start;
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} drmRadeonMemInitHeap;
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/* 1.6: Userspace can request & wait on irq's:
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*/
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typedef struct drm_radeon_irq_emit {
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int *irq_seq;
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} drmRadeonIrqEmit;
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typedef struct drm_radeon_irq_wait {
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int irq_seq;
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} drmRadeonIrqWait;
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/* 1.10: Clients tell the DRM where they think the framebuffer is located in
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* the card's address space, via a new generic ioctl to set parameters
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*/
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typedef struct drm_radeon_set_param {
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unsigned int param;
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int64_t value;
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} drmRadeonSetParam;
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#define RADEON_SETPARAM_FB_LOCATION 1
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#endif
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