546 lines
16 KiB
C
546 lines
16 KiB
C
/*
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* $Id$
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*
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* Copyright 1999 SuSE, Inc.
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that
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* copyright notice and this permission notice appear in supporting
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* documentation, and that the name of SuSE not be used in advertising or
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* publicity pertaining to distribution of the software without specific,
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* written prior permission. SuSE makes no representations about the
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* suitability of this software for any purpose. It is provided "as is"
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* without express or implied warranty.
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*
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* SuSE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL SuSE
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* BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* Author: Keith Packard, SuSE, Inc.
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*/
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/* $XFree86: $ */
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#ifndef _S3_H_
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#define _S3_H_
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#include "kdrive.h"
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#include "s3reg.h"
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#define PLATFORM 300
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/* VESA Approved Register Definitions */
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/*
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* Linear Addressing 000 0000 - 0ff ffff (16m)
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* Image data transfer 100 0000 - 100 7fff (32k)
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* PCI config 100 8000 - 100 8043
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* Packed enhanced regs 100 8100 - 100 814a
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* Streams regs 100 8180 - 100 81ff
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* Current Y pos 100 82e8
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* CRT VGA 3b? regs 100 83b0 - 100 83bf
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* CRT VGA 3c? regs 100 83c0 - 100 83cf
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* CRT VGA 3d? regs 100 83d0 - 100 83df
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* Subsystem status (42e8h) 100 8504
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* Advanced function (42e8h) 100 850c
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* Enhanced regs 100 86e8 - 100 eeea
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* Local peripheral bus 100 ff00 - 100 ff5c
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*
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* We don't care about the image transfer or PCI regs, so
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* this structure starts at the packed enhanced regs
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*/
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typedef volatile CARD32 VOL32;
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typedef volatile CARD16 VOL16;
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typedef volatile CARD8 VOL8;
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typedef volatile struct _s3 {
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VOL32 alt_curxy; /* 8100 */
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VOL32 _pad0; /* 8104 */
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VOL32 alt_step; /* 8108 */
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VOL32 _pad1; /* 810c */
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VOL32 err_term; /* 8110 */
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VOL32 _pad2; /* 8114 */
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VOL32 cmd_gp_stat; /* 8118 */
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VOL32 short_stroke; /* 811c */
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VOL32 bg; /* 8120 */
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VOL32 fg; /* 8124 */
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VOL32 write_mask; /* 8128 */
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VOL32 read_mask; /* 812c */
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VOL32 color_cmp; /* 8130 */
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VOL32 alt_mix; /* 8134 */
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VOL32 scissors_tl; /* 8138 */
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VOL32 scissors_br; /* 813c */
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VOL16 pix_cntl; /* 8140 */
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VOL16 mult_misc2; /* 8142 */
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VOL32 mult_misc_read_sel; /* 8144 */
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VOL32 alt_pcnt; /* 8148 min_axis_pcnt, maj_axis_pcnt */
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VOL8 _pad3[0x19c]; /* 814c */
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VOL16 cur_y; /* 82e8 */
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VOL8 _pad4[0xc6]; /* 82ea */
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VOL8 crt_vga_3b0; /* 83b0 */
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VOL8 crt_vga_3b1; /* 83b1 */
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VOL8 crt_vga_3b2; /* 83b2 */
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VOL8 crt_vga_3b3; /* 83b3 */
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VOL8 crt_vga_3b4; /* 83b4 */
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VOL8 crt_vga_3b5; /* 83b5 */
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VOL8 crt_vga_3b6; /* 83b6 */
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VOL8 crt_vga_3b7; /* 83b7 */
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VOL8 crt_vga_3b8; /* 83b8 */
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VOL8 crt_vga_3b9; /* 83b9 */
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VOL8 crt_vga_3ba; /* 83ba */
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VOL8 crt_vga_3bb; /* 83bb */
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VOL8 crt_vga_3bc; /* 83bc */
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VOL8 crt_vga_3bd; /* 83bd */
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VOL8 crt_vga_3be; /* 83be */
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VOL8 crt_vga_3bf; /* 83bf */
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VOL8 crt_vga_3c0; /* 83c0 */
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VOL8 crt_vga_3c1; /* 83c1 */
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VOL8 crt_vga_3c2; /* 83c2 */
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VOL8 crt_vga_3c3; /* 83c3 */
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VOL8 crt_vga_3c4; /* 83c4 */
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VOL8 crt_vga_3c5; /* 83c5 */
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VOL8 crt_vga_dac_ad_mk; /* 83c6 */
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VOL8 crt_vga_dac_rd_ad; /* 83c7 */
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VOL8 crt_vga_dac_wt_ad; /* 83c8 */
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VOL8 crt_vga_dac_data; /* 83c9 */
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VOL8 crt_vga_3ca; /* 83ca */
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VOL8 crt_vga_3cb; /* 83cb */
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VOL8 crt_vga_3cc; /* 83cc */
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VOL8 crt_vga_3cd; /* 83cd */
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VOL8 crt_vga_3ce; /* 83ce */
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VOL8 crt_vga_3cf; /* 83cf */
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VOL8 crt_vga_3d0; /* 83d0 */
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VOL8 crt_vga_3d1; /* 83d1 */
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VOL8 crt_vga_3d2; /* 83d2 */
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VOL8 crt_vga_3d3; /* 83d3 */
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VOL8 crt_vga_3d4; /* 83d4 */
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VOL8 crt_vga_3d5; /* 83d5 */
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VOL8 crt_vga_3d6; /* 83d6 */
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VOL8 crt_vga_3d7; /* 83d7 */
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VOL8 crt_vga_3d8; /* 83d8 */
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VOL8 crt_vga_3d9; /* 83d9 */
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VOL8 crt_vga_status_1; /* 83da */
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VOL8 crt_vga_3db; /* 83db */
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VOL8 crt_vga_3dc; /* 83dc */
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VOL8 crt_vga_3dd; /* 83dd */
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VOL8 crt_vga_3de; /* 83de */
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VOL8 crt_vga_3df; /* 83df */
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VOL8 _pad5[0x124]; /* 83e0 */
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VOL16 subsys_status; /* 8504 */
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VOL8 _pad6[0x6]; /* 8506 */
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VOL16 adv_control; /* 850c */
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VOL8 _pad7[0x1da]; /* 850e */
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VOL16 cur_x; /* 86e8 */
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VOL8 _pad8[0x3fe]; /* 86ea */
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VOL16 desty_axstp; /* 8ae8 */
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VOL8 _pad9[0x3fe]; /* 8aea */
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VOL16 destx_diastp; /* 8ee8 */
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VOL8 _pad10[0x3fe]; /* 8eea */
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VOL16 enh_err_term; /* 92e8 */
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VOL8 _pad11[0x3fe]; /* 92ea */
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VOL16 maj_axis_pcnt; /* 96e8 */
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VOL8 _pad12[0x3fe]; /* 96ea */
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VOL16 enh_cmd_gp_stat; /* 9ae8 */
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VOL8 _pad13[0x3fe]; /* 9aea */
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VOL16 enh_short_stroke; /* 9ee8 */
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VOL8 _pad14[0x3fe]; /* 9eea */
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VOL16 enh_bg; /* a2e8 */
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VOL8 _pad15[0x3fe]; /* a2ea */
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VOL16 enh_fg; /* a6e8 */
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VOL8 _pad16[0x3fe]; /* a6ea */
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VOL16 enh_wrt_mask; /* aae8 */
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VOL8 _pad17[0x3fe]; /* aaea */
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VOL16 enh_rd_mask; /* aee8 */
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VOL8 _pad18[0x3fe]; /* aeea */
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VOL16 enh_color_cmp; /* b2e8 */
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VOL8 _pad19[0x3fe]; /* b2ea */
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VOL16 enh_bg_mix; /* b6e8 */
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VOL8 _pad20[0x3fe]; /* b6ea */
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VOL16 enh_fg_mix; /* bae8 */
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VOL8 _pad21[0x3fe]; /* baea */
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VOL16 enh_rd_reg_dt; /* bee8 */
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VOL8 _pad22[0x23fe]; /* beea */
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VOL32 pix_trans; /* e2e8 */
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VOL8 _pad23[0x3a974]; /* e2ec */
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VOL32 alt_status_0; /* 48c60 */
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} S3, *S3Ptr;
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#define VGA_STATUS_1_DTM 0x01
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#define VGA_STATUS_1_VSY 0x08
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#define DAC_MASK 0x03c6
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#define DAC_R_INDEX 0x03c7
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#define DAC_W_INDEX 0x03c8
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#define DAC_DATA 0x03c9
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#define DISP_STAT 0x02e8
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#define H_TOTAL 0x02e8
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#define H_DISP 0x06e8
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#define H_SYNC_STRT 0x0ae8
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#define H_SYNC_WID 0x0ee8
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#define V_TOTAL 0x12e8
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#define V_DISP 0x16e8
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#define V_SYNC_STRT 0x1ae8
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#define V_SYNC_WID 0x1ee8
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#define DISP_CNTL 0x22e8
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#define ADVFUNC_CNTL 0x4ae8
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#define SUBSYS_STAT 0x42e8
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#define SUBSYS_CNTL 0x42e8
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#define ROM_PAGE_SEL 0x46e8
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#define CUR_Y 0x82e8
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#define CUR_X 0x86e8
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#define DESTY_AXSTP 0x8ae8
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#define DESTX_DIASTP 0x8ee8
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#define ERR_TERM 0x92e8
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#define MAJ_AXIS_PCNT 0x96e8
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#define GP_STAT 0x9ae8
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#define CMD 0x9ae8
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#define SHORT_STROKE 0x9ee8
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#define BKGD_COLOR 0xa2e8
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#define FRGD_COLOR 0xa6e8
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#define WRT_MASK 0xaae8
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#define RD_MASK 0xaee8
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#define COLOR_CMP 0xb2e8
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#define BKGD_MIX 0xb6e8
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#define FRGD_MIX 0xbae8
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#define MULTIFUNC_CNTL 0xbee8
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#define MIN_AXIS_PCNT 0x0000
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#define SCISSORS_T 0x1000
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#define SCISSORS_L 0x2000
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#define SCISSORS_B 0x3000
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#define SCISSORS_R 0x4000
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#define MEM_CNTL 0x5000
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#define PATTERN_L 0x8000
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#define PATTERN_H 0x9000
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#define PIX_CNTL 0xa000
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#define PIX_TRANS 0xe2e8
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/* Advanced Function Control Regsiter */
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#define CLKSEL 0x0004
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#define DISABPASSTHRU 0x0001
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/* Graphics Processor Status Register */
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#define GPNSLOT 13
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#define GPBUSY_1 0x0080
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#define GPBUSY_2 0x0040
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#define GPBUSY_3 0x0020
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#define GPBUSY_4 0x0010
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#define GPBUSY_5 0x0008
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#define GPBUSY_6 0x0004
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#define GPBUSY_7 0x0002
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#define GPBUSY_8 0x0001
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#define GPBUSY_9 0x8000
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#define GPBUSY_10 0x4000
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#define GPBUSY_11 0x2000
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#define GPBUSY_12 0x1000
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#define GPBUSY_13 0x0800
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#define GPEMPTY 0x0400
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#define GPBUSY 0x0200
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#define DATDRDY 0x0100
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/* Command Register */
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#define CMD_NOP 0x0000
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#define CMD_LINE 0x2000
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#define CMD_RECT 0x4000
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#define CMD_RECTV1 0x6000
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#define CMD_RECTV2 0x8000
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#define CMD_LINEAF 0xa000
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#define CMD_BITBLT 0xc000
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#define CMD_PATBLT 0xe000
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#define CMD_OP_MSK 0xe000
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#define BYTSEQ 0x1000
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#define _32BITNOPAD 0x0600
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#define _32BIT 0x0400
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#define _16BIT 0x0200
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#define _8BIT 0x0000
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#define PCDATA 0x0100
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#define INC_Y 0x0080
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#define YMAJAXIS 0x0040
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#define INC_X 0x0020
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#define DRAW 0x0010
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#define LINETYPE 0x0008
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#define LASTPIX 0x0004 /* Draw last pixel in line */
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#define PLANAR 0x0002
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#define WRTDATA 0x0001
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/* Background Mix Register */
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#define BSS_BKGDCOL 0x0000
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#define BSS_FRGDCOL 0x0020
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#define BSS_PCDATA 0x0040
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#define BSS_BITBLT 0x0060
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/* Foreground Mix Register */
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#define FSS_BKGDCOL 0x0000
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#define FSS_FRGDCOL 0x0020
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#define FSS_PCDATA 0x0040
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#define FSS_BITBLT 0x0060
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/* The Mixes */
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#define MIX_MASK 0x001f
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#define MIX_NOT_DST 0x0000
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#define MIX_0 0x0001
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#define MIX_1 0x0002
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#define MIX_DST 0x0003
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#define MIX_NOT_SRC 0x0004
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#define MIX_XOR 0x0005
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#define MIX_XNOR 0x0006
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#define MIX_SRC 0x0007
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#define MIX_NAND 0x0008
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#define MIX_NOT_SRC_OR_DST 0x0009
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#define MIX_SRC_OR_NOT_DST 0x000a
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#define MIX_OR 0x000b
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#define MIX_AND 0x000c
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#define MIX_SRC_AND_NOT_DST 0x000d
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#define MIX_NOT_SRC_AND_DST 0x000e
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#define MIX_NOR 0x000f
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#define MIX_MIN 0x0010
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#define MIX_DST_MINUS_SRC 0x0011
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#define MIX_SRC_MINUS_DST 0x0012
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#define MIX_PLUS 0x0013
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#define MIX_MAX 0x0014
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#define MIX_HALF__DST_MINUS_SRC 0x0015
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#define MIX_HALF__SRC_MINUS_DST 0x0016
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#define MIX_AVERAGE 0x0017
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#define MIX_DST_MINUS_SRC_SAT 0x0018
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#define MIX_SRC_MINUS_DST_SAT 0x001a
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#define MIX_HALF__DST_MINUS_SRC_SAT 0x001c
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#define MIX_HALF__SRC_MINUS_DST_SAT 0x001e
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#define MIX_AVERAGE_SAT 0x001f
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/* Pixel Control Register */
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#define MIXSEL_FRGDMIX 0x0000
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#define MIXSEL_PATT 0x0040
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#define MIXSEL_EXPPC 0x0080
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#define MIXSEL_EXPBLT 0x00c0
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#define COLCMPOP_F 0x0000
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#define COLCMPOP_T 0x0008
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#define COLCMPOP_GE 0x0010
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#define COLCMPOP_LT 0x0018
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#define COLCMPOP_NE 0x0020
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#define COLCMPOP_EQ 0x0028
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#define COLCMPOP_LE 0x0030
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#define COLCMPOP_GT 0x0038
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#define PLANEMODE 0x0004
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#define S3_SAVAGE4_SLOTS 0x0001ffff
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#define S3_SAVAGE4_2DI 0x00800000
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#define _s3WaitLoop(mask,value){ \
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int __loop = 100000; \
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while (((s3)->alt_status_0 & (mask)) != (value)) \
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if (--__loop == 0) { \
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ErrorF ("savage wait loop failed 0x%x\n", s3->alt_status_0); \
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break; \
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} \
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}
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#define _s3WaitSlot(s3) _s3WaitLoop(0x1, 0x0)
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#define _s3WaitEmpty(s3) _s3WaitLoop(S3_SAVAGE4_SLOTS, 0)
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#define _s3WaitIdleEmpty(s3) _s3WaitLoop(S3_SAVAGE4_SLOTS|S3_SAVAGE4_2DI, \
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S3_SAVAGE4_2DI)
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#define _s3WaitIdle(s3) _s3WaitLoop(S3_SAVAGE4_2DI, S3_SAVAGE4_2DI)
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typedef struct _s3Cursor {
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int width, height;
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int xhot, yhot;
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Bool has_cursor;
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CursorPtr pCursor;
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Pixel source, mask;
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} S3Cursor;
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typedef struct _s3PatternCache {
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int id;
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int x, y;
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} S3PatternCache;
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typedef struct _s3Patterns {
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S3PatternCache *cache;
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int ncache;
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int last_used;
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int last_id;
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} S3Patterns;
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#define S3_CLOCK_REF 14318 /* KHz */
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#define S3_CLOCK(m,n,r) (S3_CLOCK_REF * ((m) + 2) / (((n) + 2) * (1 << (r))))
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#if PLATFORM == 200
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#define S3_MAX_CLOCK 80000 /* KHz */
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#endif
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#if PLATFORM == 300
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#define S3_MAX_CLOCK 135000 /* KHz */
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#endif
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typedef struct _s3Timing {
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/* label */
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int horizontal;
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int vertical;
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int rate;
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/* horizontal timing */
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int hfp; /* front porch */
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int hbp; /* back porch */
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int hblank; /* blanking */
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/* vertical timing */
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int vfp; /* front porch */
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int vbp; /* back porch */
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int vblank; /* blanking */
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/* clock values */
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int dac_m;
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int dac_n;
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int dac_r;
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} S3Timing;
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#define S3_TEXT_SAVE (64*1024)
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typedef struct _s3Save {
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CARD8 cursor_fg;
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CARD8 cursor_bg;
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CARD8 lock1;
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CARD8 lock2;
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CARD8 locksrtc;
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CARD8 clock_mode;
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CARD32 alt_mix;
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CARD32 write_mask;
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CARD32 fg;
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CARD32 bg;
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CARD8 text_save[S3_TEXT_SAVE];
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} S3Save;
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typedef struct _s3CardInfo {
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S3Ptr s3; /* pointer to register structure */
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int memory; /* amount of memory */
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CARD8 *frameBuffer; /* pointer to frame buffer */
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CARD8 *registers; /* pointer to register map */
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S3Vga s3vga;
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S3Save save;
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} S3CardInfo;
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typedef struct _s3ScreenInfo {
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CARD8 *cursor_base; /* pointer to cursor area */
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CARD8 *offscreen; /* pointer to offscreen area */
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int offscreen_y; /* top y coordinate of offscreen area */
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int offscreen_x; /* top x coordinate of offscreen area */
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int offscreen_width; /* width of offscreen area */
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int offscreen_height; /* height of offscreen area */
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S3Cursor cursor;
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S3Patterns patterns;
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} S3ScreenInfo;
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#define getS3CardInfo(kd) ((S3CardInfo *) ((kd)->card->driver))
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#define s3CardInfo(kd) S3CardInfo *s3c = getS3CardInfo(kd)
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#define getS3ScreenInfo(kd) ((S3ScreenInfo *) ((kd)->screen->driver))
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#define s3ScreenInfo(kd) S3ScreenInfo *s3s = getS3ScreenInfo(kd)
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Bool s3CardInit (KdCardInfo *);
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Bool s3ScreenInit (KdScreenInfo *);
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void s3Enable (ScreenPtr pScreen);
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void s3Disable (ScreenPtr pScreen);
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void s3Fini (ScreenPtr pScreen);
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Bool s3CursorInit (ScreenPtr pScreen);
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void s3CursorEnable (ScreenPtr pScreen);
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void s3CursorDisable (ScreenPtr pScreen);
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void s3CursorFini (ScreenPtr pScreen);
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void s3RecolorCursor (ScreenPtr pScreen, int ndef, xColorItem *pdefs);
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Bool s3DrawInit (ScreenPtr pScreen);
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void s3DrawEnable (ScreenPtr pScreen);
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void s3DrawDisable (ScreenPtr pScreen);
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void s3DrawFini (ScreenPtr pScreen);
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void s3GetColors (ScreenPtr pScreen, int ndef, xColorItem *pdefs);
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void s3PutColors (ScreenPtr pScreen, int ndef, xColorItem *pdefs);
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void S3InitCard (KdCardAttr *attr);
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void s3GetClock (int target, int *Mp, int *Np, int *Rp, int maxM, int maxN, int maxR);
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#define S3ModeClock(t) (((t->horizontal + t->hblank) * \
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(t->vertical + t->vblank) * \
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t->rate) / 1000)
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extern KdCardFuncs s3Funcs;
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/*
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* Wait for the begining of the retrace interval
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*/
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#define S3_RETRACE_LOOP_CHECK if (++_loop_count > 300000) {\
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DRAW_DEBUG ((DEBUG_FAILURE, "S3 wait loop failed at %s:%d", \
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__FILE__, __LINE__)); \
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break; \
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}
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#define DRAW_DEBUG(a)
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#define _s3WaitVRetrace(s3) { \
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VOL8 *_status = &s3->crt_vga_status_1; \
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int _loop_count; \
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DRAW_DEBUG ((DEBUG_CRTC, "_s3WaitVRetrace 0x%x", *_status)); \
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_loop_count = 0; \
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while ((*_status & VGA_STATUS_1_VSY) != 0) S3_RETRACE_LOOP_CHECK; \
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_loop_count = 0; \
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while ((*_status & VGA_STATUS_1_VSY) == 0) S3_RETRACE_LOOP_CHECK; \
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}
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/*
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* Wait for the begining of the retrace interval
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*/
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#define _s3WaitVRetraceEnd(s3) { \
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VOL8 *_status = &s3->crt_vga_status_1; \
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int _loop_count; \
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DRAW_DEBUG ((DEBUG_CRTC, "_s3WaitVRetraceEnd 0x%x", *_status)); \
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_loop_count = 0; \
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while ((*_status & VGA_STATUS_1_VSY) == 0) S3_RETRACE_LOOP_CHECK; \
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_loop_count = 0; \
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while ((*_status & VGA_STATUS_1_VSY) != 0) S3_RETRACE_LOOP_CHECK; \
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}
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#define S3_CURSOR_WIDTH 64
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#define S3_CURSOR_HEIGHT 64
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#define S3_CURSOR_SIZE ((S3_CURSOR_WIDTH * S3_CURSOR_HEIGHT + 7) / 8)
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#define S3_TILE_SIZE 8
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/*
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* Ok, so the S3 is broken -- it expects bitmaps to come MSB bit order,
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* but it's willing to take them in LSB byte order. These macros
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* flip bits around without flipping bytes. Instead of using a table
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* and burning memory bandwidth, do them in place with the CPU.
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*/
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/* The MIPS compiler automatically places these constants in registers */
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#define S3InvertBits32(v) { \
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v = ((v & 0x55555555) << 1) | ((v >> 1) & 0x55555555); \
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v = ((v & 0x33333333) << 2) | ((v >> 2) & 0x33333333); \
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v = ((v & 0x0f0f0f0f) << 4) | ((v >> 4) & 0x0f0f0f0f); \
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}
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#define S3InvertBits16(v) { \
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v = ((v & 0x5555) << 1) | ((v >> 1) & 0x5555); \
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v = ((v & 0x3333) << 2) | ((v >> 2) & 0x3333); \
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v = ((v & 0x0f0f) << 4) | ((v >> 4) & 0x0f0f); \
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}
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#define S3InvertBits8(v) { \
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v = ((v & 0x55) << 1) | ((v >> 1) & 0x55); \
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v = ((v & 0x33) << 2) | ((v >> 2) & 0x33); \
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v = ((v & 0x0f) << 4) | ((v >> 4) & 0x0f); \
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}
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#endif /* _S3_H_ */
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