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Reuse index register transfer to avoid compare

This commit is contained in:
drmortalwombat 2025-01-09 20:12:09 +01:00
parent d2fdbd29f5
commit f6a2db7866
1 changed files with 51 additions and 1 deletions
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52
oscar64/NativeCodeGenerator.cpp
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@ -50667,7 +50667,6 @@ bool NativeCodeBasicBlock::PeepHoleOptimizerExits(int pass)
}
}
else if (sz >= 4 &&
mIns[sz - 4].mType == ASMIT_EOR && mIns[sz - 4].mMode == ASMIM_IMMEDIATE && mIns[sz - 4].mAddress == 0x80 &&
mIns[sz - 3].mType == ASMIT_STA && mIns[sz - 3].mMode == ASMIM_ZERO_PAGE &&
@ -51034,6 +51033,57 @@ bool NativeCodeBasicBlock::PeepHoleOptimizerExits(int pass)
}
#endif
#if 1
if (sz >= 1 && mIns[sz - 1].mType == ASMIT_CMP && mIns[sz - 1].mMode == ASMIM_IMMEDIATE && mIns[sz - 1].mAddress == 0x80 && !(mIns[sz - 1].mLive & LIVE_CPU_REG_Z))
{
if (mBranch == ASMIT_BCC || mBranch == ASMIT_BCS)
{
AsmInsType ty = ASMIT_INV;
NativeCodeBasicBlock* nblock;
int tr;
if (mTrueJump->mIns.Size() > 0 && mTrueJump->mIns[0].mType == ASMIT_TAY && !(mTrueJump->mIns[0].mLive & LIVE_CPU_REG_A) && !mFalseJump->mEntryRequiredRegs[CPU_REG_A] && !mFalseJump->mEntryRequiredRegs[CPU_REG_Y])
{
ty = ASMIT_TAY;
tr = CPU_REG_Y;
nblock = mTrueJump;
}
else if (mTrueJump->mIns.Size() > 0 && mTrueJump->mIns[0].mType == ASMIT_TAX && !(mTrueJump->mIns[0].mLive & LIVE_CPU_REG_A) && !mFalseJump->mEntryRequiredRegs[CPU_REG_A] && !mFalseJump->mEntryRequiredRegs[CPU_REG_X])
{
ty = ASMIT_TAX;
tr = CPU_REG_X;
nblock = mTrueJump;
}
else if (mFalseJump->mIns.Size() > 0 && mFalseJump->mIns[0].mType == ASMIT_TAY && !(mFalseJump->mIns[0].mLive & LIVE_CPU_REG_A) && !mTrueJump->mEntryRequiredRegs[CPU_REG_A] && !mTrueJump->mEntryRequiredRegs[CPU_REG_Y])
{
ty = ASMIT_TAY;
tr = CPU_REG_Y;
nblock = mFalseJump;
}
else if (mFalseJump->mIns.Size() > 0 && mFalseJump->mIns[0].mType == ASMIT_TAX && !(mFalseJump->mIns[0].mLive & LIVE_CPU_REG_A) && !mTrueJump->mEntryRequiredRegs[CPU_REG_A] && !mTrueJump->mEntryRequiredRegs[CPU_REG_X])
{
ty = ASMIT_TAX;
tr = CPU_REG_X;
nblock = mFalseJump;
}
if (ty != ASMIT_INV)
{
mIns[sz - 1].mType = ty;
mIns[sz - 1].mMode = ASMIM_IMPLIED;
nblock->mIns.Remove(0);
mExitRequiredRegs += tr;
nblock->mEntryRequiredRegs += tr;
if (mBranch == ASMIT_BCC)
mBranch = ASMIT_BPL;
else
mBranch = ASMIT_BMI;
changed = true;
}
}
}
#endif
#if 1
if (sz > 0 && mFalseJump && mIns[sz - 1].ChangesAccuAndFlag() && mBranch == ASMIT_BMI)
{